target_x86.cc revision 88474b416eb257078e590bf9bc7957cee604a186
1/* 2 * Copyright (C) 2012 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#include "codegen_x86.h" 18#include "dex/compiler_internals.h" 19#include "dex/quick/mir_to_lir-inl.h" 20#include "x86_lir.h" 21 22#include <string> 23 24namespace art { 25 26// FIXME: restore "static" when usage uncovered 27/*static*/ int core_regs[] = { 28 rAX, rCX, rDX, rBX, rX86_SP, rBP, rSI, rDI 29#ifdef TARGET_REX_SUPPORT 30 r8, r9, r10, r11, r12, r13, r14, 15 31#endif 32}; 33/*static*/ int ReservedRegs[] = {rX86_SP}; 34/*static*/ int core_temps[] = {rAX, rCX, rDX, rBX}; 35/*static*/ int FpRegs[] = { 36 fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7, 37#ifdef TARGET_REX_SUPPORT 38 fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15 39#endif 40}; 41/*static*/ int fp_temps[] = { 42 fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7, 43#ifdef TARGET_REX_SUPPORT 44 fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15 45#endif 46}; 47 48RegLocation X86Mir2Lir::LocCReturn() { 49 RegLocation res = X86_LOC_C_RETURN; 50 return res; 51} 52 53RegLocation X86Mir2Lir::LocCReturnWide() { 54 RegLocation res = X86_LOC_C_RETURN_WIDE; 55 return res; 56} 57 58RegLocation X86Mir2Lir::LocCReturnFloat() { 59 RegLocation res = X86_LOC_C_RETURN_FLOAT; 60 return res; 61} 62 63RegLocation X86Mir2Lir::LocCReturnDouble() { 64 RegLocation res = X86_LOC_C_RETURN_DOUBLE; 65 return res; 66} 67 68// Return a target-dependent special register. 69int X86Mir2Lir::TargetReg(SpecialTargetRegister reg) { 70 int res = INVALID_REG; 71 switch (reg) { 72 case kSelf: res = rX86_SELF; break; 73 case kSuspend: res = rX86_SUSPEND; break; 74 case kLr: res = rX86_LR; break; 75 case kPc: res = rX86_PC; break; 76 case kSp: res = rX86_SP; break; 77 case kArg0: res = rX86_ARG0; break; 78 case kArg1: res = rX86_ARG1; break; 79 case kArg2: res = rX86_ARG2; break; 80 case kArg3: res = rX86_ARG3; break; 81 case kFArg0: res = rX86_FARG0; break; 82 case kFArg1: res = rX86_FARG1; break; 83 case kFArg2: res = rX86_FARG2; break; 84 case kFArg3: res = rX86_FARG3; break; 85 case kRet0: res = rX86_RET0; break; 86 case kRet1: res = rX86_RET1; break; 87 case kInvokeTgt: res = rX86_INVOKE_TGT; break; 88 case kHiddenArg: res = rAX; break; 89 case kHiddenFpArg: res = fr0; break; 90 case kCount: res = rX86_COUNT; break; 91 } 92 return res; 93} 94 95// Create a double from a pair of singles. 96int X86Mir2Lir::S2d(int low_reg, int high_reg) { 97 return X86_S2D(low_reg, high_reg); 98} 99 100// Return mask to strip off fp reg flags and bias. 101uint32_t X86Mir2Lir::FpRegMask() { 102 return X86_FP_REG_MASK; 103} 104 105// True if both regs single, both core or both double. 106bool X86Mir2Lir::SameRegType(int reg1, int reg2) { 107 return (X86_REGTYPE(reg1) == X86_REGTYPE(reg2)); 108} 109 110/* 111 * Decode the register id. 112 */ 113uint64_t X86Mir2Lir::GetRegMaskCommon(int reg) { 114 uint64_t seed; 115 int shift; 116 int reg_id; 117 118 reg_id = reg & 0xf; 119 /* Double registers in x86 are just a single FP register */ 120 seed = 1; 121 /* FP register starts at bit position 16 */ 122 shift = X86_FPREG(reg) ? kX86FPReg0 : 0; 123 /* Expand the double register id into single offset */ 124 shift += reg_id; 125 return (seed << shift); 126} 127 128uint64_t X86Mir2Lir::GetPCUseDefEncoding() { 129 /* 130 * FIXME: might make sense to use a virtual resource encoding bit for pc. Might be 131 * able to clean up some of the x86/Arm_Mips differences 132 */ 133 LOG(FATAL) << "Unexpected call to GetPCUseDefEncoding for x86"; 134 return 0ULL; 135} 136 137void X86Mir2Lir::SetupTargetResourceMasks(LIR* lir, uint64_t flags) { 138 DCHECK_EQ(cu_->instruction_set, kX86); 139 DCHECK(!lir->flags.use_def_invalid); 140 141 // X86-specific resource map setup here. 142 if (flags & REG_USE_SP) { 143 lir->u.m.use_mask |= ENCODE_X86_REG_SP; 144 } 145 146 if (flags & REG_DEF_SP) { 147 lir->u.m.def_mask |= ENCODE_X86_REG_SP; 148 } 149 150 if (flags & REG_DEFA) { 151 SetupRegMask(&lir->u.m.def_mask, rAX); 152 } 153 154 if (flags & REG_DEFD) { 155 SetupRegMask(&lir->u.m.def_mask, rDX); 156 } 157 if (flags & REG_USEA) { 158 SetupRegMask(&lir->u.m.use_mask, rAX); 159 } 160 161 if (flags & REG_USEC) { 162 SetupRegMask(&lir->u.m.use_mask, rCX); 163 } 164 165 if (flags & REG_USED) { 166 SetupRegMask(&lir->u.m.use_mask, rDX); 167 } 168} 169 170/* For dumping instructions */ 171static const char* x86RegName[] = { 172 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", 173 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" 174}; 175 176static const char* x86CondName[] = { 177 "O", 178 "NO", 179 "B/NAE/C", 180 "NB/AE/NC", 181 "Z/EQ", 182 "NZ/NE", 183 "BE/NA", 184 "NBE/A", 185 "S", 186 "NS", 187 "P/PE", 188 "NP/PO", 189 "L/NGE", 190 "NL/GE", 191 "LE/NG", 192 "NLE/G" 193}; 194 195/* 196 * Interpret a format string and build a string no longer than size 197 * See format key in Assemble.cc. 198 */ 199std::string X86Mir2Lir::BuildInsnString(const char *fmt, LIR *lir, unsigned char* base_addr) { 200 std::string buf; 201 size_t i = 0; 202 size_t fmt_len = strlen(fmt); 203 while (i < fmt_len) { 204 if (fmt[i] != '!') { 205 buf += fmt[i]; 206 i++; 207 } else { 208 i++; 209 DCHECK_LT(i, fmt_len); 210 char operand_number_ch = fmt[i]; 211 i++; 212 if (operand_number_ch == '!') { 213 buf += "!"; 214 } else { 215 int operand_number = operand_number_ch - '0'; 216 DCHECK_LT(operand_number, 6); // Expect upto 6 LIR operands. 217 DCHECK_LT(i, fmt_len); 218 int operand = lir->operands[operand_number]; 219 switch (fmt[i]) { 220 case 'c': 221 DCHECK_LT(static_cast<size_t>(operand), sizeof(x86CondName)); 222 buf += x86CondName[operand]; 223 break; 224 case 'd': 225 buf += StringPrintf("%d", operand); 226 break; 227 case 'p': { 228 EmbeddedData *tab_rec = reinterpret_cast<EmbeddedData*>(UnwrapPointer(operand)); 229 buf += StringPrintf("0x%08x", tab_rec->offset); 230 break; 231 } 232 case 'r': 233 if (X86_FPREG(operand) || X86_DOUBLEREG(operand)) { 234 int fp_reg = operand & X86_FP_REG_MASK; 235 buf += StringPrintf("xmm%d", fp_reg); 236 } else { 237 DCHECK_LT(static_cast<size_t>(operand), sizeof(x86RegName)); 238 buf += x86RegName[operand]; 239 } 240 break; 241 case 't': 242 buf += StringPrintf("0x%08x (L%p)", 243 reinterpret_cast<uintptr_t>(base_addr) 244 + lir->offset + operand, lir->target); 245 break; 246 default: 247 buf += StringPrintf("DecodeError '%c'", fmt[i]); 248 break; 249 } 250 i++; 251 } 252 } 253 } 254 return buf; 255} 256 257void X86Mir2Lir::DumpResourceMask(LIR *x86LIR, uint64_t mask, const char *prefix) { 258 char buf[256]; 259 buf[0] = 0; 260 261 if (mask == ENCODE_ALL) { 262 strcpy(buf, "all"); 263 } else { 264 char num[8]; 265 int i; 266 267 for (i = 0; i < kX86RegEnd; i++) { 268 if (mask & (1ULL << i)) { 269 sprintf(num, "%d ", i); 270 strcat(buf, num); 271 } 272 } 273 274 if (mask & ENCODE_CCODE) { 275 strcat(buf, "cc "); 276 } 277 /* Memory bits */ 278 if (x86LIR && (mask & ENCODE_DALVIK_REG)) { 279 sprintf(buf + strlen(buf), "dr%d%s", DECODE_ALIAS_INFO_REG(x86LIR->flags.alias_info), 280 (DECODE_ALIAS_INFO_WIDE(x86LIR->flags.alias_info)) ? "(+1)" : ""); 281 } 282 if (mask & ENCODE_LITERAL) { 283 strcat(buf, "lit "); 284 } 285 286 if (mask & ENCODE_HEAP_REF) { 287 strcat(buf, "heap "); 288 } 289 if (mask & ENCODE_MUST_NOT_ALIAS) { 290 strcat(buf, "noalias "); 291 } 292 } 293 if (buf[0]) { 294 LOG(INFO) << prefix << ": " << buf; 295 } 296} 297 298void X86Mir2Lir::AdjustSpillMask() { 299 // Adjustment for LR spilling, x86 has no LR so nothing to do here 300 core_spill_mask_ |= (1 << rRET); 301 num_core_spills_++; 302} 303 304/* 305 * Mark a callee-save fp register as promoted. Note that 306 * vpush/vpop uses contiguous register lists so we must 307 * include any holes in the mask. Associate holes with 308 * Dalvik register INVALID_VREG (0xFFFFU). 309 */ 310void X86Mir2Lir::MarkPreservedSingle(int v_reg, int reg) { 311 UNIMPLEMENTED(WARNING) << "MarkPreservedSingle"; 312#if 0 313 LOG(FATAL) << "No support yet for promoted FP regs"; 314#endif 315} 316 317void X86Mir2Lir::FlushRegWide(int reg1, int reg2) { 318 RegisterInfo* info1 = GetRegInfo(reg1); 319 RegisterInfo* info2 = GetRegInfo(reg2); 320 DCHECK(info1 && info2 && info1->pair && info2->pair && 321 (info1->partner == info2->reg) && 322 (info2->partner == info1->reg)); 323 if ((info1->live && info1->dirty) || (info2->live && info2->dirty)) { 324 if (!(info1->is_temp && info2->is_temp)) { 325 /* Should not happen. If it does, there's a problem in eval_loc */ 326 LOG(FATAL) << "Long half-temp, half-promoted"; 327 } 328 329 info1->dirty = false; 330 info2->dirty = false; 331 if (mir_graph_->SRegToVReg(info2->s_reg) < mir_graph_->SRegToVReg(info1->s_reg)) 332 info1 = info2; 333 int v_reg = mir_graph_->SRegToVReg(info1->s_reg); 334 StoreBaseDispWide(rX86_SP, VRegOffset(v_reg), info1->reg, info1->partner); 335 } 336} 337 338void X86Mir2Lir::FlushReg(int reg) { 339 RegisterInfo* info = GetRegInfo(reg); 340 if (info->live && info->dirty) { 341 info->dirty = false; 342 int v_reg = mir_graph_->SRegToVReg(info->s_reg); 343 StoreBaseDisp(rX86_SP, VRegOffset(v_reg), reg, kWord); 344 } 345} 346 347/* Give access to the target-dependent FP register encoding to common code */ 348bool X86Mir2Lir::IsFpReg(int reg) { 349 return X86_FPREG(reg); 350} 351 352/* Clobber all regs that might be used by an external C call */ 353void X86Mir2Lir::ClobberCalleeSave() { 354 Clobber(rAX); 355 Clobber(rCX); 356 Clobber(rDX); 357} 358 359RegLocation X86Mir2Lir::GetReturnWideAlt() { 360 RegLocation res = LocCReturnWide(); 361 CHECK(res.low_reg == rAX); 362 CHECK(res.high_reg == rDX); 363 Clobber(rAX); 364 Clobber(rDX); 365 MarkInUse(rAX); 366 MarkInUse(rDX); 367 MarkPair(res.low_reg, res.high_reg); 368 return res; 369} 370 371RegLocation X86Mir2Lir::GetReturnAlt() { 372 RegLocation res = LocCReturn(); 373 res.low_reg = rDX; 374 Clobber(rDX); 375 MarkInUse(rDX); 376 return res; 377} 378 379/* To be used when explicitly managing register use */ 380void X86Mir2Lir::LockCallTemps() { 381 LockTemp(rX86_ARG0); 382 LockTemp(rX86_ARG1); 383 LockTemp(rX86_ARG2); 384 LockTemp(rX86_ARG3); 385} 386 387/* To be used when explicitly managing register use */ 388void X86Mir2Lir::FreeCallTemps() { 389 FreeTemp(rX86_ARG0); 390 FreeTemp(rX86_ARG1); 391 FreeTemp(rX86_ARG2); 392 FreeTemp(rX86_ARG3); 393} 394 395void X86Mir2Lir::GenMemBarrier(MemBarrierKind barrier_kind) { 396#if ANDROID_SMP != 0 397 // TODO: optimize fences 398 NewLIR0(kX86Mfence); 399#endif 400} 401/* 402 * Alloc a pair of core registers, or a double. Low reg in low byte, 403 * high reg in next byte. 404 */ 405int X86Mir2Lir::AllocTypedTempPair(bool fp_hint, 406 int reg_class) { 407 int high_reg; 408 int low_reg; 409 int res = 0; 410 411 if (((reg_class == kAnyReg) && fp_hint) || (reg_class == kFPReg)) { 412 low_reg = AllocTempDouble(); 413 high_reg = low_reg + 1; 414 res = (low_reg & 0xff) | ((high_reg & 0xff) << 8); 415 return res; 416 } 417 418 low_reg = AllocTemp(); 419 high_reg = AllocTemp(); 420 res = (low_reg & 0xff) | ((high_reg & 0xff) << 8); 421 return res; 422} 423 424int X86Mir2Lir::AllocTypedTemp(bool fp_hint, int reg_class) { 425 if (((reg_class == kAnyReg) && fp_hint) || (reg_class == kFPReg)) { 426 return AllocTempFloat(); 427 } 428 return AllocTemp(); 429} 430 431void X86Mir2Lir::CompilerInitializeRegAlloc() { 432 int num_regs = sizeof(core_regs)/sizeof(*core_regs); 433 int num_reserved = sizeof(ReservedRegs)/sizeof(*ReservedRegs); 434 int num_temps = sizeof(core_temps)/sizeof(*core_temps); 435 int num_fp_regs = sizeof(FpRegs)/sizeof(*FpRegs); 436 int num_fp_temps = sizeof(fp_temps)/sizeof(*fp_temps); 437 reg_pool_ = static_cast<RegisterPool*>(arena_->Alloc(sizeof(*reg_pool_), 438 ArenaAllocator::kAllocRegAlloc)); 439 reg_pool_->num_core_regs = num_regs; 440 reg_pool_->core_regs = 441 static_cast<RegisterInfo*>(arena_->Alloc(num_regs * sizeof(*reg_pool_->core_regs), 442 ArenaAllocator::kAllocRegAlloc)); 443 reg_pool_->num_fp_regs = num_fp_regs; 444 reg_pool_->FPRegs = 445 static_cast<RegisterInfo *>(arena_->Alloc(num_fp_regs * sizeof(*reg_pool_->FPRegs), 446 ArenaAllocator::kAllocRegAlloc)); 447 CompilerInitPool(reg_pool_->core_regs, core_regs, reg_pool_->num_core_regs); 448 CompilerInitPool(reg_pool_->FPRegs, FpRegs, reg_pool_->num_fp_regs); 449 // Keep special registers from being allocated 450 for (int i = 0; i < num_reserved; i++) { 451 MarkInUse(ReservedRegs[i]); 452 } 453 // Mark temp regs - all others not in use can be used for promotion 454 for (int i = 0; i < num_temps; i++) { 455 MarkTemp(core_temps[i]); 456 } 457 for (int i = 0; i < num_fp_temps; i++) { 458 MarkTemp(fp_temps[i]); 459 } 460} 461 462void X86Mir2Lir::FreeRegLocTemps(RegLocation rl_keep, 463 RegLocation rl_free) { 464 if ((rl_free.low_reg != rl_keep.low_reg) && (rl_free.low_reg != rl_keep.high_reg) && 465 (rl_free.high_reg != rl_keep.low_reg) && (rl_free.high_reg != rl_keep.high_reg)) { 466 // No overlap, free both 467 FreeTemp(rl_free.low_reg); 468 FreeTemp(rl_free.high_reg); 469 } 470} 471 472void X86Mir2Lir::SpillCoreRegs() { 473 if (num_core_spills_ == 0) { 474 return; 475 } 476 // Spill mask not including fake return address register 477 uint32_t mask = core_spill_mask_ & ~(1 << rRET); 478 int offset = frame_size_ - (4 * num_core_spills_); 479 for (int reg = 0; mask; mask >>= 1, reg++) { 480 if (mask & 0x1) { 481 StoreWordDisp(rX86_SP, offset, reg); 482 offset += 4; 483 } 484 } 485} 486 487void X86Mir2Lir::UnSpillCoreRegs() { 488 if (num_core_spills_ == 0) { 489 return; 490 } 491 // Spill mask not including fake return address register 492 uint32_t mask = core_spill_mask_ & ~(1 << rRET); 493 int offset = frame_size_ - (4 * num_core_spills_); 494 for (int reg = 0; mask; mask >>= 1, reg++) { 495 if (mask & 0x1) { 496 LoadWordDisp(rX86_SP, offset, reg); 497 offset += 4; 498 } 499 } 500} 501 502bool X86Mir2Lir::IsUnconditionalBranch(LIR* lir) { 503 return (lir->opcode == kX86Jmp8 || lir->opcode == kX86Jmp32); 504} 505 506X86Mir2Lir::X86Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena) 507 : Mir2Lir(cu, mir_graph, arena) { 508 for (int i = 0; i < kX86Last; i++) { 509 if (X86Mir2Lir::EncodingMap[i].opcode != i) { 510 LOG(FATAL) << "Encoding order for " << X86Mir2Lir::EncodingMap[i].name 511 << " is wrong: expecting " << i << ", seeing " 512 << static_cast<int>(X86Mir2Lir::EncodingMap[i].opcode); 513 } 514 } 515} 516 517Mir2Lir* X86CodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, 518 ArenaAllocator* const arena) { 519 return new X86Mir2Lir(cu, mir_graph, arena); 520} 521 522// Not used in x86 523int X86Mir2Lir::LoadHelper(ThreadOffset offset) { 524 LOG(FATAL) << "Unexpected use of LoadHelper in x86"; 525 return INVALID_REG; 526} 527 528uint64_t X86Mir2Lir::GetTargetInstFlags(int opcode) { 529 DCHECK(!IsPseudoLirOp(opcode)); 530 return X86Mir2Lir::EncodingMap[opcode].flags; 531} 532 533const char* X86Mir2Lir::GetTargetInstName(int opcode) { 534 DCHECK(!IsPseudoLirOp(opcode)); 535 return X86Mir2Lir::EncodingMap[opcode].name; 536} 537 538const char* X86Mir2Lir::GetTargetInstFmt(int opcode) { 539 DCHECK(!IsPseudoLirOp(opcode)); 540 return X86Mir2Lir::EncodingMap[opcode].fmt; 541} 542 543} // namespace art 544