target_x86.cc revision 984305917bf57b3f8d92965e4715a0370cc5bcfb
1/* 2 * Copyright (C) 2012 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#include <string> 18#include <inttypes.h> 19 20#include "codegen_x86.h" 21#include "dex/compiler_internals.h" 22#include "dex/quick/mir_to_lir-inl.h" 23#include "dex/reg_storage_eq.h" 24#include "mirror/array.h" 25#include "mirror/string.h" 26#include "x86_lir.h" 27 28namespace art { 29 30static constexpr RegStorage core_regs_arr_32[] = { 31 rs_rAX, rs_rCX, rs_rDX, rs_rBX, rs_rX86_SP_32, rs_rBP, rs_rSI, rs_rDI, 32}; 33static constexpr RegStorage core_regs_arr_64[] = { 34 rs_rAX, rs_rCX, rs_rDX, rs_rBX, rs_rX86_SP_32, rs_rBP, rs_rSI, rs_rDI, 35 rs_r8, rs_r9, rs_r10, rs_r11, rs_r12, rs_r13, rs_r14, rs_r15 36}; 37static constexpr RegStorage core_regs_arr_64q[] = { 38 rs_r0q, rs_r1q, rs_r2q, rs_r3q, rs_rX86_SP_64, rs_r5q, rs_r6q, rs_r7q, 39 rs_r8q, rs_r9q, rs_r10q, rs_r11q, rs_r12q, rs_r13q, rs_r14q, rs_r15q 40}; 41static constexpr RegStorage sp_regs_arr_32[] = { 42 rs_fr0, rs_fr1, rs_fr2, rs_fr3, rs_fr4, rs_fr5, rs_fr6, rs_fr7, 43}; 44static constexpr RegStorage sp_regs_arr_64[] = { 45 rs_fr0, rs_fr1, rs_fr2, rs_fr3, rs_fr4, rs_fr5, rs_fr6, rs_fr7, 46 rs_fr8, rs_fr9, rs_fr10, rs_fr11, rs_fr12, rs_fr13, rs_fr14, rs_fr15 47}; 48static constexpr RegStorage dp_regs_arr_32[] = { 49 rs_dr0, rs_dr1, rs_dr2, rs_dr3, rs_dr4, rs_dr5, rs_dr6, rs_dr7, 50}; 51static constexpr RegStorage dp_regs_arr_64[] = { 52 rs_dr0, rs_dr1, rs_dr2, rs_dr3, rs_dr4, rs_dr5, rs_dr6, rs_dr7, 53 rs_dr8, rs_dr9, rs_dr10, rs_dr11, rs_dr12, rs_dr13, rs_dr14, rs_dr15 54}; 55static constexpr RegStorage xp_regs_arr_32[] = { 56 rs_xr0, rs_xr1, rs_xr2, rs_xr3, rs_xr4, rs_xr5, rs_xr6, rs_xr7, 57}; 58static constexpr RegStorage xp_regs_arr_64[] = { 59 rs_xr0, rs_xr1, rs_xr2, rs_xr3, rs_xr4, rs_xr5, rs_xr6, rs_xr7, 60 rs_xr8, rs_xr9, rs_xr10, rs_xr11, rs_xr12, rs_xr13, rs_xr14, rs_xr15 61}; 62static constexpr RegStorage reserved_regs_arr_32[] = {rs_rX86_SP_32}; 63static constexpr RegStorage reserved_regs_arr_64[] = {rs_rX86_SP_32}; 64static constexpr RegStorage reserved_regs_arr_64q[] = {rs_rX86_SP_64}; 65static constexpr RegStorage core_temps_arr_32[] = {rs_rAX, rs_rCX, rs_rDX, rs_rBX}; 66static constexpr RegStorage core_temps_arr_64[] = { 67 rs_rAX, rs_rCX, rs_rDX, rs_rSI, rs_rDI, 68 rs_r8, rs_r9, rs_r10, rs_r11 69}; 70 71// How to add register to be available for promotion: 72// 1) Remove register from array defining temp 73// 2) Update ClobberCallerSave 74// 3) Update JNI compiler ABI: 75// 3.1) add reg in JniCallingConvention method 76// 3.2) update CoreSpillMask/FpSpillMask 77// 4) Update entrypoints 78// 4.1) Update constants in asm_support_x86_64.h for new frame size 79// 4.2) Remove entry in SmashCallerSaves 80// 4.3) Update jni_entrypoints to spill/unspill new callee save reg 81// 4.4) Update quick_entrypoints to spill/unspill new callee save reg 82// 5) Update runtime ABI 83// 5.1) Update quick_method_frame_info with new required spills 84// 5.2) Update QuickArgumentVisitor with new offsets to gprs and xmms 85// Note that you cannot use register corresponding to incoming args 86// according to ABI and QCG needs one additional XMM temp for 87// bulk copy in preparation to call. 88static constexpr RegStorage core_temps_arr_64q[] = { 89 rs_r0q, rs_r1q, rs_r2q, rs_r6q, rs_r7q, 90 rs_r8q, rs_r9q, rs_r10q, rs_r11q 91}; 92static constexpr RegStorage sp_temps_arr_32[] = { 93 rs_fr0, rs_fr1, rs_fr2, rs_fr3, rs_fr4, rs_fr5, rs_fr6, rs_fr7, 94}; 95static constexpr RegStorage sp_temps_arr_64[] = { 96 rs_fr0, rs_fr1, rs_fr2, rs_fr3, rs_fr4, rs_fr5, rs_fr6, rs_fr7, 97 rs_fr8, rs_fr9, rs_fr10, rs_fr11 98}; 99static constexpr RegStorage dp_temps_arr_32[] = { 100 rs_dr0, rs_dr1, rs_dr2, rs_dr3, rs_dr4, rs_dr5, rs_dr6, rs_dr7, 101}; 102static constexpr RegStorage dp_temps_arr_64[] = { 103 rs_dr0, rs_dr1, rs_dr2, rs_dr3, rs_dr4, rs_dr5, rs_dr6, rs_dr7, 104 rs_dr8, rs_dr9, rs_dr10, rs_dr11 105}; 106 107static constexpr RegStorage xp_temps_arr_32[] = { 108 rs_xr0, rs_xr1, rs_xr2, rs_xr3, rs_xr4, rs_xr5, rs_xr6, rs_xr7, 109}; 110static constexpr RegStorage xp_temps_arr_64[] = { 111 rs_xr0, rs_xr1, rs_xr2, rs_xr3, rs_xr4, rs_xr5, rs_xr6, rs_xr7, 112 rs_xr8, rs_xr9, rs_xr10, rs_xr11 113}; 114 115static constexpr ArrayRef<const RegStorage> empty_pool; 116static constexpr ArrayRef<const RegStorage> core_regs_32(core_regs_arr_32); 117static constexpr ArrayRef<const RegStorage> core_regs_64(core_regs_arr_64); 118static constexpr ArrayRef<const RegStorage> core_regs_64q(core_regs_arr_64q); 119static constexpr ArrayRef<const RegStorage> sp_regs_32(sp_regs_arr_32); 120static constexpr ArrayRef<const RegStorage> sp_regs_64(sp_regs_arr_64); 121static constexpr ArrayRef<const RegStorage> dp_regs_32(dp_regs_arr_32); 122static constexpr ArrayRef<const RegStorage> dp_regs_64(dp_regs_arr_64); 123static constexpr ArrayRef<const RegStorage> xp_regs_32(xp_regs_arr_32); 124static constexpr ArrayRef<const RegStorage> xp_regs_64(xp_regs_arr_64); 125static constexpr ArrayRef<const RegStorage> reserved_regs_32(reserved_regs_arr_32); 126static constexpr ArrayRef<const RegStorage> reserved_regs_64(reserved_regs_arr_64); 127static constexpr ArrayRef<const RegStorage> reserved_regs_64q(reserved_regs_arr_64q); 128static constexpr ArrayRef<const RegStorage> core_temps_32(core_temps_arr_32); 129static constexpr ArrayRef<const RegStorage> core_temps_64(core_temps_arr_64); 130static constexpr ArrayRef<const RegStorage> core_temps_64q(core_temps_arr_64q); 131static constexpr ArrayRef<const RegStorage> sp_temps_32(sp_temps_arr_32); 132static constexpr ArrayRef<const RegStorage> sp_temps_64(sp_temps_arr_64); 133static constexpr ArrayRef<const RegStorage> dp_temps_32(dp_temps_arr_32); 134static constexpr ArrayRef<const RegStorage> dp_temps_64(dp_temps_arr_64); 135 136static constexpr ArrayRef<const RegStorage> xp_temps_32(xp_temps_arr_32); 137static constexpr ArrayRef<const RegStorage> xp_temps_64(xp_temps_arr_64); 138 139RegStorage rs_rX86_SP; 140 141X86NativeRegisterPool rX86_ARG0; 142X86NativeRegisterPool rX86_ARG1; 143X86NativeRegisterPool rX86_ARG2; 144X86NativeRegisterPool rX86_ARG3; 145X86NativeRegisterPool rX86_ARG4; 146X86NativeRegisterPool rX86_ARG5; 147X86NativeRegisterPool rX86_FARG0; 148X86NativeRegisterPool rX86_FARG1; 149X86NativeRegisterPool rX86_FARG2; 150X86NativeRegisterPool rX86_FARG3; 151X86NativeRegisterPool rX86_FARG4; 152X86NativeRegisterPool rX86_FARG5; 153X86NativeRegisterPool rX86_FARG6; 154X86NativeRegisterPool rX86_FARG7; 155X86NativeRegisterPool rX86_RET0; 156X86NativeRegisterPool rX86_RET1; 157X86NativeRegisterPool rX86_INVOKE_TGT; 158X86NativeRegisterPool rX86_COUNT; 159 160RegStorage rs_rX86_ARG0; 161RegStorage rs_rX86_ARG1; 162RegStorage rs_rX86_ARG2; 163RegStorage rs_rX86_ARG3; 164RegStorage rs_rX86_ARG4; 165RegStorage rs_rX86_ARG5; 166RegStorage rs_rX86_FARG0; 167RegStorage rs_rX86_FARG1; 168RegStorage rs_rX86_FARG2; 169RegStorage rs_rX86_FARG3; 170RegStorage rs_rX86_FARG4; 171RegStorage rs_rX86_FARG5; 172RegStorage rs_rX86_FARG6; 173RegStorage rs_rX86_FARG7; 174RegStorage rs_rX86_RET0; 175RegStorage rs_rX86_RET1; 176RegStorage rs_rX86_INVOKE_TGT; 177RegStorage rs_rX86_COUNT; 178 179RegLocation X86Mir2Lir::LocCReturn() { 180 return x86_loc_c_return; 181} 182 183RegLocation X86Mir2Lir::LocCReturnRef() { 184 return cu_->target64 ? x86_64_loc_c_return_ref : x86_loc_c_return_ref; 185} 186 187RegLocation X86Mir2Lir::LocCReturnWide() { 188 return cu_->target64 ? x86_64_loc_c_return_wide : x86_loc_c_return_wide; 189} 190 191RegLocation X86Mir2Lir::LocCReturnFloat() { 192 return x86_loc_c_return_float; 193} 194 195RegLocation X86Mir2Lir::LocCReturnDouble() { 196 return x86_loc_c_return_double; 197} 198 199// Return a target-dependent special register for 32-bit. 200RegStorage X86Mir2Lir::TargetReg32(SpecialTargetRegister reg) { 201 RegStorage res_reg = RegStorage::InvalidReg(); 202 switch (reg) { 203 case kSelf: res_reg = RegStorage::InvalidReg(); break; 204 case kSuspend: res_reg = RegStorage::InvalidReg(); break; 205 case kLr: res_reg = RegStorage::InvalidReg(); break; 206 case kPc: res_reg = RegStorage::InvalidReg(); break; 207 case kSp: res_reg = rs_rX86_SP_32; break; // This must be the concrete one, as _SP is target- 208 // specific size. 209 case kArg0: res_reg = rs_rX86_ARG0; break; 210 case kArg1: res_reg = rs_rX86_ARG1; break; 211 case kArg2: res_reg = rs_rX86_ARG2; break; 212 case kArg3: res_reg = rs_rX86_ARG3; break; 213 case kArg4: res_reg = rs_rX86_ARG4; break; 214 case kArg5: res_reg = rs_rX86_ARG5; break; 215 case kFArg0: res_reg = rs_rX86_FARG0; break; 216 case kFArg1: res_reg = rs_rX86_FARG1; break; 217 case kFArg2: res_reg = rs_rX86_FARG2; break; 218 case kFArg3: res_reg = rs_rX86_FARG3; break; 219 case kFArg4: res_reg = rs_rX86_FARG4; break; 220 case kFArg5: res_reg = rs_rX86_FARG5; break; 221 case kFArg6: res_reg = rs_rX86_FARG6; break; 222 case kFArg7: res_reg = rs_rX86_FARG7; break; 223 case kRet0: res_reg = rs_rX86_RET0; break; 224 case kRet1: res_reg = rs_rX86_RET1; break; 225 case kInvokeTgt: res_reg = rs_rX86_INVOKE_TGT; break; 226 case kHiddenArg: res_reg = rs_rAX; break; 227 case kHiddenFpArg: DCHECK(!cu_->target64); res_reg = rs_fr0; break; 228 case kCount: res_reg = rs_rX86_COUNT; break; 229 default: res_reg = RegStorage::InvalidReg(); 230 } 231 return res_reg; 232} 233 234RegStorage X86Mir2Lir::TargetReg(SpecialTargetRegister reg) { 235 LOG(FATAL) << "Do not use this function!!!"; 236 return RegStorage::InvalidReg(); 237} 238 239/* 240 * Decode the register id. 241 */ 242ResourceMask X86Mir2Lir::GetRegMaskCommon(const RegStorage& reg) const { 243 /* Double registers in x86 are just a single FP register. This is always just a single bit. */ 244 return ResourceMask::Bit( 245 /* FP register starts at bit position 16 */ 246 ((reg.IsFloat() || reg.StorageSize() > 8) ? kX86FPReg0 : 0) + reg.GetRegNum()); 247} 248 249ResourceMask X86Mir2Lir::GetPCUseDefEncoding() const { 250 return kEncodeNone; 251} 252 253void X86Mir2Lir::SetupTargetResourceMasks(LIR* lir, uint64_t flags, 254 ResourceMask* use_mask, ResourceMask* def_mask) { 255 DCHECK(cu_->instruction_set == kX86 || cu_->instruction_set == kX86_64); 256 DCHECK(!lir->flags.use_def_invalid); 257 258 // X86-specific resource map setup here. 259 if (flags & REG_USE_SP) { 260 use_mask->SetBit(kX86RegSP); 261 } 262 263 if (flags & REG_DEF_SP) { 264 def_mask->SetBit(kX86RegSP); 265 } 266 267 if (flags & REG_DEFA) { 268 SetupRegMask(def_mask, rs_rAX.GetReg()); 269 } 270 271 if (flags & REG_DEFD) { 272 SetupRegMask(def_mask, rs_rDX.GetReg()); 273 } 274 if (flags & REG_USEA) { 275 SetupRegMask(use_mask, rs_rAX.GetReg()); 276 } 277 278 if (flags & REG_USEC) { 279 SetupRegMask(use_mask, rs_rCX.GetReg()); 280 } 281 282 if (flags & REG_USED) { 283 SetupRegMask(use_mask, rs_rDX.GetReg()); 284 } 285 286 if (flags & REG_USEB) { 287 SetupRegMask(use_mask, rs_rBX.GetReg()); 288 } 289 290 // Fixup hard to describe instruction: Uses rAX, rCX, rDI; sets rDI. 291 if (lir->opcode == kX86RepneScasw) { 292 SetupRegMask(use_mask, rs_rAX.GetReg()); 293 SetupRegMask(use_mask, rs_rCX.GetReg()); 294 SetupRegMask(use_mask, rs_rDI.GetReg()); 295 SetupRegMask(def_mask, rs_rDI.GetReg()); 296 } 297 298 if (flags & USE_FP_STACK) { 299 use_mask->SetBit(kX86FPStack); 300 def_mask->SetBit(kX86FPStack); 301 } 302} 303 304/* For dumping instructions */ 305static const char* x86RegName[] = { 306 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", 307 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" 308}; 309 310static const char* x86CondName[] = { 311 "O", 312 "NO", 313 "B/NAE/C", 314 "NB/AE/NC", 315 "Z/EQ", 316 "NZ/NE", 317 "BE/NA", 318 "NBE/A", 319 "S", 320 "NS", 321 "P/PE", 322 "NP/PO", 323 "L/NGE", 324 "NL/GE", 325 "LE/NG", 326 "NLE/G" 327}; 328 329/* 330 * Interpret a format string and build a string no longer than size 331 * See format key in Assemble.cc. 332 */ 333std::string X86Mir2Lir::BuildInsnString(const char *fmt, LIR *lir, unsigned char* base_addr) { 334 std::string buf; 335 size_t i = 0; 336 size_t fmt_len = strlen(fmt); 337 while (i < fmt_len) { 338 if (fmt[i] != '!') { 339 buf += fmt[i]; 340 i++; 341 } else { 342 i++; 343 DCHECK_LT(i, fmt_len); 344 char operand_number_ch = fmt[i]; 345 i++; 346 if (operand_number_ch == '!') { 347 buf += "!"; 348 } else { 349 int operand_number = operand_number_ch - '0'; 350 DCHECK_LT(operand_number, 6); // Expect upto 6 LIR operands. 351 DCHECK_LT(i, fmt_len); 352 int operand = lir->operands[operand_number]; 353 switch (fmt[i]) { 354 case 'c': 355 DCHECK_LT(static_cast<size_t>(operand), sizeof(x86CondName)); 356 buf += x86CondName[operand]; 357 break; 358 case 'd': 359 buf += StringPrintf("%d", operand); 360 break; 361 case 'q': { 362 int64_t value = static_cast<int64_t>(static_cast<int64_t>(operand) << 32 | 363 static_cast<uint32_t>(lir->operands[operand_number+1])); 364 buf +=StringPrintf("%" PRId64, value); 365 } 366 case 'p': { 367 EmbeddedData *tab_rec = reinterpret_cast<EmbeddedData*>(UnwrapPointer(operand)); 368 buf += StringPrintf("0x%08x", tab_rec->offset); 369 break; 370 } 371 case 'r': 372 if (RegStorage::IsFloat(operand)) { 373 int fp_reg = RegStorage::RegNum(operand); 374 buf += StringPrintf("xmm%d", fp_reg); 375 } else { 376 int reg_num = RegStorage::RegNum(operand); 377 DCHECK_LT(static_cast<size_t>(reg_num), sizeof(x86RegName)); 378 buf += x86RegName[reg_num]; 379 } 380 break; 381 case 't': 382 buf += StringPrintf("0x%08" PRIxPTR " (L%p)", 383 reinterpret_cast<uintptr_t>(base_addr) + lir->offset + operand, 384 lir->target); 385 break; 386 default: 387 buf += StringPrintf("DecodeError '%c'", fmt[i]); 388 break; 389 } 390 i++; 391 } 392 } 393 } 394 return buf; 395} 396 397void X86Mir2Lir::DumpResourceMask(LIR *x86LIR, const ResourceMask& mask, const char *prefix) { 398 char buf[256]; 399 buf[0] = 0; 400 401 if (mask.Equals(kEncodeAll)) { 402 strcpy(buf, "all"); 403 } else { 404 char num[8]; 405 int i; 406 407 for (i = 0; i < kX86RegEnd; i++) { 408 if (mask.HasBit(i)) { 409 snprintf(num, arraysize(num), "%d ", i); 410 strcat(buf, num); 411 } 412 } 413 414 if (mask.HasBit(ResourceMask::kCCode)) { 415 strcat(buf, "cc "); 416 } 417 /* Memory bits */ 418 if (x86LIR && (mask.HasBit(ResourceMask::kDalvikReg))) { 419 snprintf(buf + strlen(buf), arraysize(buf) - strlen(buf), "dr%d%s", 420 DECODE_ALIAS_INFO_REG(x86LIR->flags.alias_info), 421 (DECODE_ALIAS_INFO_WIDE(x86LIR->flags.alias_info)) ? "(+1)" : ""); 422 } 423 if (mask.HasBit(ResourceMask::kLiteral)) { 424 strcat(buf, "lit "); 425 } 426 427 if (mask.HasBit(ResourceMask::kHeapRef)) { 428 strcat(buf, "heap "); 429 } 430 if (mask.HasBit(ResourceMask::kMustNotAlias)) { 431 strcat(buf, "noalias "); 432 } 433 } 434 if (buf[0]) { 435 LOG(INFO) << prefix << ": " << buf; 436 } 437} 438 439void X86Mir2Lir::AdjustSpillMask() { 440 // Adjustment for LR spilling, x86 has no LR so nothing to do here 441 core_spill_mask_ |= (1 << rs_rRET.GetRegNum()); 442 num_core_spills_++; 443} 444 445RegStorage X86Mir2Lir::AllocateByteRegister() { 446 RegStorage reg = AllocTypedTemp(false, kCoreReg); 447 if (!cu_->target64) { 448 DCHECK_LT(reg.GetRegNum(), rs_rX86_SP.GetRegNum()); 449 } 450 return reg; 451} 452 453RegStorage X86Mir2Lir::Get128BitRegister(RegStorage reg) { 454 return GetRegInfo(reg)->FindMatchingView(RegisterInfo::k128SoloStorageMask)->GetReg(); 455} 456 457bool X86Mir2Lir::IsByteRegister(RegStorage reg) { 458 return cu_->target64 || reg.GetRegNum() < rs_rX86_SP.GetRegNum(); 459} 460 461/* Clobber all regs that might be used by an external C call */ 462void X86Mir2Lir::ClobberCallerSave() { 463 if (cu_->target64) { 464 Clobber(rs_rAX); 465 Clobber(rs_rCX); 466 Clobber(rs_rDX); 467 Clobber(rs_rSI); 468 Clobber(rs_rDI); 469 470 Clobber(rs_r8); 471 Clobber(rs_r9); 472 Clobber(rs_r10); 473 Clobber(rs_r11); 474 475 Clobber(rs_fr8); 476 Clobber(rs_fr9); 477 Clobber(rs_fr10); 478 Clobber(rs_fr11); 479 } else { 480 Clobber(rs_rAX); 481 Clobber(rs_rCX); 482 Clobber(rs_rDX); 483 Clobber(rs_rBX); 484 } 485 486 Clobber(rs_fr0); 487 Clobber(rs_fr1); 488 Clobber(rs_fr2); 489 Clobber(rs_fr3); 490 Clobber(rs_fr4); 491 Clobber(rs_fr5); 492 Clobber(rs_fr6); 493 Clobber(rs_fr7); 494} 495 496RegLocation X86Mir2Lir::GetReturnWideAlt() { 497 RegLocation res = LocCReturnWide(); 498 DCHECK(res.reg.GetLowReg() == rs_rAX.GetReg()); 499 DCHECK(res.reg.GetHighReg() == rs_rDX.GetReg()); 500 Clobber(rs_rAX); 501 Clobber(rs_rDX); 502 MarkInUse(rs_rAX); 503 MarkInUse(rs_rDX); 504 MarkWide(res.reg); 505 return res; 506} 507 508RegLocation X86Mir2Lir::GetReturnAlt() { 509 RegLocation res = LocCReturn(); 510 res.reg.SetReg(rs_rDX.GetReg()); 511 Clobber(rs_rDX); 512 MarkInUse(rs_rDX); 513 return res; 514} 515 516/* To be used when explicitly managing register use */ 517void X86Mir2Lir::LockCallTemps() { 518 LockTemp(rs_rX86_ARG0); 519 LockTemp(rs_rX86_ARG1); 520 LockTemp(rs_rX86_ARG2); 521 LockTemp(rs_rX86_ARG3); 522 if (cu_->target64) { 523 LockTemp(rs_rX86_ARG4); 524 LockTemp(rs_rX86_ARG5); 525 LockTemp(rs_rX86_FARG0); 526 LockTemp(rs_rX86_FARG1); 527 LockTemp(rs_rX86_FARG2); 528 LockTemp(rs_rX86_FARG3); 529 LockTemp(rs_rX86_FARG4); 530 LockTemp(rs_rX86_FARG5); 531 LockTemp(rs_rX86_FARG6); 532 LockTemp(rs_rX86_FARG7); 533 } 534} 535 536/* To be used when explicitly managing register use */ 537void X86Mir2Lir::FreeCallTemps() { 538 FreeTemp(rs_rX86_ARG0); 539 FreeTemp(rs_rX86_ARG1); 540 FreeTemp(rs_rX86_ARG2); 541 FreeTemp(rs_rX86_ARG3); 542 if (cu_->target64) { 543 FreeTemp(rs_rX86_ARG4); 544 FreeTemp(rs_rX86_ARG5); 545 FreeTemp(rs_rX86_FARG0); 546 FreeTemp(rs_rX86_FARG1); 547 FreeTemp(rs_rX86_FARG2); 548 FreeTemp(rs_rX86_FARG3); 549 FreeTemp(rs_rX86_FARG4); 550 FreeTemp(rs_rX86_FARG5); 551 FreeTemp(rs_rX86_FARG6); 552 FreeTemp(rs_rX86_FARG7); 553 } 554} 555 556bool X86Mir2Lir::ProvidesFullMemoryBarrier(X86OpCode opcode) { 557 switch (opcode) { 558 case kX86LockCmpxchgMR: 559 case kX86LockCmpxchgAR: 560 case kX86LockCmpxchg64M: 561 case kX86LockCmpxchg64A: 562 case kX86XchgMR: 563 case kX86Mfence: 564 // Atomic memory instructions provide full barrier. 565 return true; 566 default: 567 break; 568 } 569 570 // Conservative if cannot prove it provides full barrier. 571 return false; 572} 573 574bool X86Mir2Lir::GenMemBarrier(MemBarrierKind barrier_kind) { 575#if ANDROID_SMP != 0 576 // Start off with using the last LIR as the barrier. If it is not enough, then we will update it. 577 LIR* mem_barrier = last_lir_insn_; 578 579 bool ret = false; 580 /* 581 * According to the JSR-133 Cookbook, for x86 only StoreLoad/AnyAny barriers need memory fence. 582 * All other barriers (LoadAny, AnyStore, StoreStore) are nops due to the x86 memory model. 583 * For those cases, all we need to ensure is that there is a scheduling barrier in place. 584 */ 585 if (barrier_kind == kAnyAny) { 586 // If no LIR exists already that can be used a barrier, then generate an mfence. 587 if (mem_barrier == nullptr) { 588 mem_barrier = NewLIR0(kX86Mfence); 589 ret = true; 590 } 591 592 // If last instruction does not provide full barrier, then insert an mfence. 593 if (ProvidesFullMemoryBarrier(static_cast<X86OpCode>(mem_barrier->opcode)) == false) { 594 mem_barrier = NewLIR0(kX86Mfence); 595 ret = true; 596 } 597 } 598 599 // Now ensure that a scheduling barrier is in place. 600 if (mem_barrier == nullptr) { 601 GenBarrier(); 602 } else { 603 // Mark as a scheduling barrier. 604 DCHECK(!mem_barrier->flags.use_def_invalid); 605 mem_barrier->u.m.def_mask = &kEncodeAll; 606 } 607 return ret; 608#else 609 return false; 610#endif 611} 612 613void X86Mir2Lir::CompilerInitializeRegAlloc() { 614 if (cu_->target64) { 615 reg_pool_ = new (arena_) RegisterPool(this, arena_, core_regs_64, core_regs_64q, sp_regs_64, 616 dp_regs_64, reserved_regs_64, reserved_regs_64q, 617 core_temps_64, core_temps_64q, sp_temps_64, dp_temps_64); 618 } else { 619 reg_pool_ = new (arena_) RegisterPool(this, arena_, core_regs_32, empty_pool, sp_regs_32, 620 dp_regs_32, reserved_regs_32, empty_pool, 621 core_temps_32, empty_pool, sp_temps_32, dp_temps_32); 622 } 623 624 // Target-specific adjustments. 625 626 // Add in XMM registers. 627 const ArrayRef<const RegStorage> *xp_regs = cu_->target64 ? &xp_regs_64 : &xp_regs_32; 628 for (RegStorage reg : *xp_regs) { 629 RegisterInfo* info = new (arena_) RegisterInfo(reg, GetRegMaskCommon(reg)); 630 reginfo_map_.Put(reg.GetReg(), info); 631 } 632 const ArrayRef<const RegStorage> *xp_temps = cu_->target64 ? &xp_temps_64 : &xp_temps_32; 633 for (RegStorage reg : *xp_temps) { 634 RegisterInfo* xp_reg_info = GetRegInfo(reg); 635 xp_reg_info->SetIsTemp(true); 636 } 637 638 // Alias single precision xmm to double xmms. 639 // TODO: as needed, add larger vector sizes - alias all to the largest. 640 GrowableArray<RegisterInfo*>::Iterator it(®_pool_->sp_regs_); 641 for (RegisterInfo* info = it.Next(); info != nullptr; info = it.Next()) { 642 int sp_reg_num = info->GetReg().GetRegNum(); 643 RegStorage xp_reg = RegStorage::Solo128(sp_reg_num); 644 RegisterInfo* xp_reg_info = GetRegInfo(xp_reg); 645 // 128-bit xmm vector register's master storage should refer to itself. 646 DCHECK_EQ(xp_reg_info, xp_reg_info->Master()); 647 648 // Redirect 32-bit vector's master storage to 128-bit vector. 649 info->SetMaster(xp_reg_info); 650 651 RegStorage dp_reg = RegStorage::FloatSolo64(sp_reg_num); 652 RegisterInfo* dp_reg_info = GetRegInfo(dp_reg); 653 // Redirect 64-bit vector's master storage to 128-bit vector. 654 dp_reg_info->SetMaster(xp_reg_info); 655 // Singles should show a single 32-bit mask bit, at first referring to the low half. 656 DCHECK_EQ(info->StorageMask(), 0x1U); 657 } 658 659 if (cu_->target64) { 660 // Alias 32bit W registers to corresponding 64bit X registers. 661 GrowableArray<RegisterInfo*>::Iterator w_it(®_pool_->core_regs_); 662 for (RegisterInfo* info = w_it.Next(); info != nullptr; info = w_it.Next()) { 663 int x_reg_num = info->GetReg().GetRegNum(); 664 RegStorage x_reg = RegStorage::Solo64(x_reg_num); 665 RegisterInfo* x_reg_info = GetRegInfo(x_reg); 666 // 64bit X register's master storage should refer to itself. 667 DCHECK_EQ(x_reg_info, x_reg_info->Master()); 668 // Redirect 32bit W master storage to 64bit X. 669 info->SetMaster(x_reg_info); 670 // 32bit W should show a single 32-bit mask bit, at first referring to the low half. 671 DCHECK_EQ(info->StorageMask(), 0x1U); 672 } 673 } 674 675 // Don't start allocating temps at r0/s0/d0 or you may clobber return regs in early-exit methods. 676 // TODO: adjust for x86/hard float calling convention. 677 reg_pool_->next_core_reg_ = 2; 678 reg_pool_->next_sp_reg_ = 2; 679 reg_pool_->next_dp_reg_ = 1; 680} 681 682int X86Mir2Lir::VectorRegisterSize() { 683 return 128; 684} 685 686int X86Mir2Lir::NumReservableVectorRegisters(bool fp_used) { 687 return fp_used ? 5 : 7; 688} 689 690void X86Mir2Lir::SpillCoreRegs() { 691 if (num_core_spills_ == 0) { 692 return; 693 } 694 // Spill mask not including fake return address register 695 uint32_t mask = core_spill_mask_ & ~(1 << rs_rRET.GetRegNum()); 696 int offset = frame_size_ - (GetInstructionSetPointerSize(cu_->instruction_set) * num_core_spills_); 697 OpSize size = cu_->target64 ? k64 : k32; 698 for (int reg = 0; mask; mask >>= 1, reg++) { 699 if (mask & 0x1) { 700 StoreBaseDisp(rs_rX86_SP, offset, cu_->target64 ? RegStorage::Solo64(reg) : RegStorage::Solo32(reg), 701 size, kNotVolatile); 702 offset += GetInstructionSetPointerSize(cu_->instruction_set); 703 } 704 } 705} 706 707void X86Mir2Lir::UnSpillCoreRegs() { 708 if (num_core_spills_ == 0) { 709 return; 710 } 711 // Spill mask not including fake return address register 712 uint32_t mask = core_spill_mask_ & ~(1 << rs_rRET.GetRegNum()); 713 int offset = frame_size_ - (GetInstructionSetPointerSize(cu_->instruction_set) * num_core_spills_); 714 OpSize size = cu_->target64 ? k64 : k32; 715 for (int reg = 0; mask; mask >>= 1, reg++) { 716 if (mask & 0x1) { 717 LoadBaseDisp(rs_rX86_SP, offset, cu_->target64 ? RegStorage::Solo64(reg) : RegStorage::Solo32(reg), 718 size, kNotVolatile); 719 offset += GetInstructionSetPointerSize(cu_->instruction_set); 720 } 721 } 722} 723 724void X86Mir2Lir::SpillFPRegs() { 725 if (num_fp_spills_ == 0) { 726 return; 727 } 728 uint32_t mask = fp_spill_mask_; 729 int offset = frame_size_ - (GetInstructionSetPointerSize(cu_->instruction_set) * (num_fp_spills_ + num_core_spills_)); 730 for (int reg = 0; mask; mask >>= 1, reg++) { 731 if (mask & 0x1) { 732 StoreBaseDisp(rs_rX86_SP, offset, RegStorage::FloatSolo64(reg), 733 k64, kNotVolatile); 734 offset += sizeof(double); 735 } 736 } 737} 738void X86Mir2Lir::UnSpillFPRegs() { 739 if (num_fp_spills_ == 0) { 740 return; 741 } 742 uint32_t mask = fp_spill_mask_; 743 int offset = frame_size_ - (GetInstructionSetPointerSize(cu_->instruction_set) * (num_fp_spills_ + num_core_spills_)); 744 for (int reg = 0; mask; mask >>= 1, reg++) { 745 if (mask & 0x1) { 746 LoadBaseDisp(rs_rX86_SP, offset, RegStorage::FloatSolo64(reg), 747 k64, kNotVolatile); 748 offset += sizeof(double); 749 } 750 } 751} 752 753 754bool X86Mir2Lir::IsUnconditionalBranch(LIR* lir) { 755 return (lir->opcode == kX86Jmp8 || lir->opcode == kX86Jmp32); 756} 757 758RegisterClass X86Mir2Lir::RegClassForFieldLoadStore(OpSize size, bool is_volatile) { 759 // X86_64 can handle any size. 760 if (cu_->target64) { 761 if (size == kReference) { 762 return kRefReg; 763 } 764 return kCoreReg; 765 } 766 767 if (UNLIKELY(is_volatile)) { 768 // On x86, atomic 64-bit load/store requires an fp register. 769 // Smaller aligned load/store is atomic for both core and fp registers. 770 if (size == k64 || size == kDouble) { 771 return kFPReg; 772 } 773 } 774 return RegClassBySize(size); 775} 776 777X86Mir2Lir::X86Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena) 778 : Mir2Lir(cu, mir_graph, arena), 779 base_of_code_(nullptr), store_method_addr_(false), store_method_addr_used_(false), 780 method_address_insns_(arena, 100, kGrowableArrayMisc), 781 class_type_address_insns_(arena, 100, kGrowableArrayMisc), 782 call_method_insns_(arena, 100, kGrowableArrayMisc), 783 stack_decrement_(nullptr), stack_increment_(nullptr), 784 const_vectors_(nullptr) { 785 store_method_addr_used_ = false; 786 if (kIsDebugBuild) { 787 for (int i = 0; i < kX86Last; i++) { 788 if (X86Mir2Lir::EncodingMap[i].opcode != i) { 789 LOG(FATAL) << "Encoding order for " << X86Mir2Lir::EncodingMap[i].name 790 << " is wrong: expecting " << i << ", seeing " 791 << static_cast<int>(X86Mir2Lir::EncodingMap[i].opcode); 792 } 793 } 794 } 795 if (cu_->target64) { 796 rs_rX86_SP = rs_rX86_SP_64; 797 798 rs_rX86_ARG0 = rs_rDI; 799 rs_rX86_ARG1 = rs_rSI; 800 rs_rX86_ARG2 = rs_rDX; 801 rs_rX86_ARG3 = rs_rCX; 802 rs_rX86_ARG4 = rs_r8; 803 rs_rX86_ARG5 = rs_r9; 804 rs_rX86_FARG0 = rs_fr0; 805 rs_rX86_FARG1 = rs_fr1; 806 rs_rX86_FARG2 = rs_fr2; 807 rs_rX86_FARG3 = rs_fr3; 808 rs_rX86_FARG4 = rs_fr4; 809 rs_rX86_FARG5 = rs_fr5; 810 rs_rX86_FARG6 = rs_fr6; 811 rs_rX86_FARG7 = rs_fr7; 812 rX86_ARG0 = rDI; 813 rX86_ARG1 = rSI; 814 rX86_ARG2 = rDX; 815 rX86_ARG3 = rCX; 816 rX86_ARG4 = r8; 817 rX86_ARG5 = r9; 818 rX86_FARG0 = fr0; 819 rX86_FARG1 = fr1; 820 rX86_FARG2 = fr2; 821 rX86_FARG3 = fr3; 822 rX86_FARG4 = fr4; 823 rX86_FARG5 = fr5; 824 rX86_FARG6 = fr6; 825 rX86_FARG7 = fr7; 826 rs_rX86_INVOKE_TGT = rs_rDI; 827 } else { 828 rs_rX86_SP = rs_rX86_SP_32; 829 830 rs_rX86_ARG0 = rs_rAX; 831 rs_rX86_ARG1 = rs_rCX; 832 rs_rX86_ARG2 = rs_rDX; 833 rs_rX86_ARG3 = rs_rBX; 834 rs_rX86_ARG4 = RegStorage::InvalidReg(); 835 rs_rX86_ARG5 = RegStorage::InvalidReg(); 836 rs_rX86_FARG0 = rs_rAX; 837 rs_rX86_FARG1 = rs_rCX; 838 rs_rX86_FARG2 = rs_rDX; 839 rs_rX86_FARG3 = rs_rBX; 840 rs_rX86_FARG4 = RegStorage::InvalidReg(); 841 rs_rX86_FARG5 = RegStorage::InvalidReg(); 842 rs_rX86_FARG6 = RegStorage::InvalidReg(); 843 rs_rX86_FARG7 = RegStorage::InvalidReg(); 844 rX86_ARG0 = rAX; 845 rX86_ARG1 = rCX; 846 rX86_ARG2 = rDX; 847 rX86_ARG3 = rBX; 848 rX86_FARG0 = rAX; 849 rX86_FARG1 = rCX; 850 rX86_FARG2 = rDX; 851 rX86_FARG3 = rBX; 852 rs_rX86_INVOKE_TGT = rs_rAX; 853 // TODO(64): Initialize with invalid reg 854// rX86_ARG4 = RegStorage::InvalidReg(); 855// rX86_ARG5 = RegStorage::InvalidReg(); 856 } 857 rs_rX86_RET0 = rs_rAX; 858 rs_rX86_RET1 = rs_rDX; 859 rs_rX86_COUNT = rs_rCX; 860 rX86_RET0 = rAX; 861 rX86_RET1 = rDX; 862 rX86_INVOKE_TGT = rAX; 863 rX86_COUNT = rCX; 864 865 // Initialize the number of reserved vector registers 866 num_reserved_vector_regs_ = -1; 867} 868 869Mir2Lir* X86CodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, 870 ArenaAllocator* const arena) { 871 return new X86Mir2Lir(cu, mir_graph, arena); 872} 873 874// Not used in x86(-64) 875RegStorage X86Mir2Lir::LoadHelper(QuickEntrypointEnum trampoline) { 876 LOG(FATAL) << "Unexpected use of LoadHelper in x86"; 877 return RegStorage::InvalidReg(); 878} 879 880LIR* X86Mir2Lir::CheckSuspendUsingLoad() { 881 // First load the pointer in fs:[suspend-trigger] into eax 882 // Then use a test instruction to indirect via that address. 883 NewLIR2(kX86Mov32RT, rs_rAX.GetReg(), cu_->target64 ? 884 Thread::ThreadSuspendTriggerOffset<8>().Int32Value() : 885 Thread::ThreadSuspendTriggerOffset<4>().Int32Value()); 886 return NewLIR3(kX86Test32RM, rs_rAX.GetReg(), rs_rAX.GetReg(), 0); 887} 888 889uint64_t X86Mir2Lir::GetTargetInstFlags(int opcode) { 890 DCHECK(!IsPseudoLirOp(opcode)); 891 return X86Mir2Lir::EncodingMap[opcode].flags; 892} 893 894const char* X86Mir2Lir::GetTargetInstName(int opcode) { 895 DCHECK(!IsPseudoLirOp(opcode)); 896 return X86Mir2Lir::EncodingMap[opcode].name; 897} 898 899const char* X86Mir2Lir::GetTargetInstFmt(int opcode) { 900 DCHECK(!IsPseudoLirOp(opcode)); 901 return X86Mir2Lir::EncodingMap[opcode].fmt; 902} 903 904void X86Mir2Lir::GenConstWide(RegLocation rl_dest, int64_t value) { 905 // Can we do this directly to memory? 906 rl_dest = UpdateLocWide(rl_dest); 907 if ((rl_dest.location == kLocDalvikFrame) || 908 (rl_dest.location == kLocCompilerTemp)) { 909 int32_t val_lo = Low32Bits(value); 910 int32_t val_hi = High32Bits(value); 911 int r_base = rs_rX86_SP.GetReg(); 912 int displacement = SRegOffset(rl_dest.s_reg_low); 913 914 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); 915 LIR * store = NewLIR3(kX86Mov32MI, r_base, displacement + LOWORD_OFFSET, val_lo); 916 AnnotateDalvikRegAccess(store, (displacement + LOWORD_OFFSET) >> 2, 917 false /* is_load */, true /* is64bit */); 918 store = NewLIR3(kX86Mov32MI, r_base, displacement + HIWORD_OFFSET, val_hi); 919 AnnotateDalvikRegAccess(store, (displacement + HIWORD_OFFSET) >> 2, 920 false /* is_load */, true /* is64bit */); 921 return; 922 } 923 924 // Just use the standard code to do the generation. 925 Mir2Lir::GenConstWide(rl_dest, value); 926} 927 928// TODO: Merge with existing RegLocation dumper in vreg_analysis.cc 929void X86Mir2Lir::DumpRegLocation(RegLocation loc) { 930 LOG(INFO) << "location: " << loc.location << ',' 931 << (loc.wide ? " w" : " ") 932 << (loc.defined ? " D" : " ") 933 << (loc.is_const ? " c" : " ") 934 << (loc.fp ? " F" : " ") 935 << (loc.core ? " C" : " ") 936 << (loc.ref ? " r" : " ") 937 << (loc.high_word ? " h" : " ") 938 << (loc.home ? " H" : " ") 939 << ", low: " << static_cast<int>(loc.reg.GetLowReg()) 940 << ", high: " << static_cast<int>(loc.reg.GetHighReg()) 941 << ", s_reg: " << loc.s_reg_low 942 << ", orig: " << loc.orig_sreg; 943} 944 945void X86Mir2Lir::Materialize() { 946 // A good place to put the analysis before starting. 947 AnalyzeMIR(); 948 949 // Now continue with regular code generation. 950 Mir2Lir::Materialize(); 951} 952 953void X86Mir2Lir::LoadMethodAddress(const MethodReference& target_method, InvokeType type, 954 SpecialTargetRegister symbolic_reg) { 955 /* 956 * For x86, just generate a 32 bit move immediate instruction, that will be filled 957 * in at 'link time'. For now, put a unique value based on target to ensure that 958 * code deduplication works. 959 */ 960 int target_method_idx = target_method.dex_method_index; 961 const DexFile* target_dex_file = target_method.dex_file; 962 const DexFile::MethodId& target_method_id = target_dex_file->GetMethodId(target_method_idx); 963 uintptr_t target_method_id_ptr = reinterpret_cast<uintptr_t>(&target_method_id); 964 965 // Generate the move instruction with the unique pointer and save index, dex_file, and type. 966 LIR *move = RawLIR(current_dalvik_offset_, kX86Mov32RI, 967 TargetReg(symbolic_reg, kNotWide).GetReg(), 968 static_cast<int>(target_method_id_ptr), target_method_idx, 969 WrapPointer(const_cast<DexFile*>(target_dex_file)), type); 970 AppendLIR(move); 971 method_address_insns_.Insert(move); 972} 973 974void X86Mir2Lir::LoadClassType(uint32_t type_idx, SpecialTargetRegister symbolic_reg) { 975 /* 976 * For x86, just generate a 32 bit move immediate instruction, that will be filled 977 * in at 'link time'. For now, put a unique value based on target to ensure that 978 * code deduplication works. 979 */ 980 const DexFile::TypeId& id = cu_->dex_file->GetTypeId(type_idx); 981 uintptr_t ptr = reinterpret_cast<uintptr_t>(&id); 982 983 // Generate the move instruction with the unique pointer and save index and type. 984 LIR *move = RawLIR(current_dalvik_offset_, kX86Mov32RI, 985 TargetReg(symbolic_reg, kNotWide).GetReg(), 986 static_cast<int>(ptr), type_idx); 987 AppendLIR(move); 988 class_type_address_insns_.Insert(move); 989} 990 991LIR *X86Mir2Lir::CallWithLinkerFixup(const MethodReference& target_method, InvokeType type) { 992 /* 993 * For x86, just generate a 32 bit call relative instruction, that will be filled 994 * in at 'link time'. For now, put a unique value based on target to ensure that 995 * code deduplication works. 996 */ 997 int target_method_idx = target_method.dex_method_index; 998 const DexFile* target_dex_file = target_method.dex_file; 999 const DexFile::MethodId& target_method_id = target_dex_file->GetMethodId(target_method_idx); 1000 uintptr_t target_method_id_ptr = reinterpret_cast<uintptr_t>(&target_method_id); 1001 1002 // Generate the call instruction with the unique pointer and save index, dex_file, and type. 1003 LIR *call = RawLIR(current_dalvik_offset_, kX86CallI, static_cast<int>(target_method_id_ptr), 1004 target_method_idx, WrapPointer(const_cast<DexFile*>(target_dex_file)), type); 1005 AppendLIR(call); 1006 call_method_insns_.Insert(call); 1007 return call; 1008} 1009 1010/* 1011 * @brief Enter a 32 bit quantity into a buffer 1012 * @param buf buffer. 1013 * @param data Data value. 1014 */ 1015 1016static void PushWord(std::vector<uint8_t>&buf, int32_t data) { 1017 buf.push_back(data & 0xff); 1018 buf.push_back((data >> 8) & 0xff); 1019 buf.push_back((data >> 16) & 0xff); 1020 buf.push_back((data >> 24) & 0xff); 1021} 1022 1023void X86Mir2Lir::InstallLiteralPools() { 1024 // These are handled differently for x86. 1025 DCHECK(code_literal_list_ == nullptr); 1026 DCHECK(method_literal_list_ == nullptr); 1027 DCHECK(class_literal_list_ == nullptr); 1028 1029 // Align to 16 byte boundary. We have implicit knowledge that the start of the method is 1030 // on a 4 byte boundary. How can I check this if it changes (other than aligned loads 1031 // will fail at runtime)? 1032 if (const_vectors_ != nullptr) { 1033 int align_size = (16-4) - (code_buffer_.size() & 0xF); 1034 if (align_size < 0) { 1035 align_size += 16; 1036 } 1037 1038 while (align_size > 0) { 1039 code_buffer_.push_back(0); 1040 align_size--; 1041 } 1042 for (LIR *p = const_vectors_; p != nullptr; p = p->next) { 1043 PushWord(code_buffer_, p->operands[0]); 1044 PushWord(code_buffer_, p->operands[1]); 1045 PushWord(code_buffer_, p->operands[2]); 1046 PushWord(code_buffer_, p->operands[3]); 1047 } 1048 } 1049 1050 // Handle the fixups for methods. 1051 for (uint32_t i = 0; i < method_address_insns_.Size(); i++) { 1052 LIR* p = method_address_insns_.Get(i); 1053 DCHECK_EQ(p->opcode, kX86Mov32RI); 1054 uint32_t target_method_idx = p->operands[2]; 1055 const DexFile* target_dex_file = 1056 reinterpret_cast<const DexFile*>(UnwrapPointer(p->operands[3])); 1057 1058 // The offset to patch is the last 4 bytes of the instruction. 1059 int patch_offset = p->offset + p->flags.size - 4; 1060 cu_->compiler_driver->AddMethodPatch(cu_->dex_file, cu_->class_def_idx, 1061 cu_->method_idx, cu_->invoke_type, 1062 target_method_idx, target_dex_file, 1063 static_cast<InvokeType>(p->operands[4]), 1064 patch_offset); 1065 } 1066 1067 // Handle the fixups for class types. 1068 for (uint32_t i = 0; i < class_type_address_insns_.Size(); i++) { 1069 LIR* p = class_type_address_insns_.Get(i); 1070 DCHECK_EQ(p->opcode, kX86Mov32RI); 1071 uint32_t target_method_idx = p->operands[2]; 1072 1073 // The offset to patch is the last 4 bytes of the instruction. 1074 int patch_offset = p->offset + p->flags.size - 4; 1075 cu_->compiler_driver->AddClassPatch(cu_->dex_file, cu_->class_def_idx, 1076 cu_->method_idx, target_method_idx, patch_offset); 1077 } 1078 1079 // And now the PC-relative calls to methods. 1080 for (uint32_t i = 0; i < call_method_insns_.Size(); i++) { 1081 LIR* p = call_method_insns_.Get(i); 1082 DCHECK_EQ(p->opcode, kX86CallI); 1083 uint32_t target_method_idx = p->operands[1]; 1084 const DexFile* target_dex_file = 1085 reinterpret_cast<const DexFile*>(UnwrapPointer(p->operands[2])); 1086 1087 // The offset to patch is the last 4 bytes of the instruction. 1088 int patch_offset = p->offset + p->flags.size - 4; 1089 cu_->compiler_driver->AddRelativeCodePatch(cu_->dex_file, cu_->class_def_idx, 1090 cu_->method_idx, cu_->invoke_type, 1091 target_method_idx, target_dex_file, 1092 static_cast<InvokeType>(p->operands[3]), 1093 patch_offset, -4 /* offset */); 1094 } 1095 1096 // And do the normal processing. 1097 Mir2Lir::InstallLiteralPools(); 1098} 1099 1100bool X86Mir2Lir::GenInlinedArrayCopyCharArray(CallInfo* info) { 1101 if (cu_->target64) { 1102 // TODO: Implement ArrayCOpy intrinsic for x86_64 1103 return false; 1104 } 1105 1106 RegLocation rl_src = info->args[0]; 1107 RegLocation rl_srcPos = info->args[1]; 1108 RegLocation rl_dst = info->args[2]; 1109 RegLocation rl_dstPos = info->args[3]; 1110 RegLocation rl_length = info->args[4]; 1111 if (rl_srcPos.is_const && (mir_graph_->ConstantValue(rl_srcPos) < 0)) { 1112 return false; 1113 } 1114 if (rl_dstPos.is_const && (mir_graph_->ConstantValue(rl_dstPos) < 0)) { 1115 return false; 1116 } 1117 ClobberCallerSave(); 1118 LockCallTemps(); // Using fixed registers 1119 LoadValueDirectFixed(rl_src , rs_rAX); 1120 LoadValueDirectFixed(rl_dst , rs_rCX); 1121 LIR* src_dst_same = OpCmpBranch(kCondEq, rs_rAX , rs_rCX, nullptr); 1122 LIR* src_null_branch = OpCmpImmBranch(kCondEq, rs_rAX , 0, nullptr); 1123 LIR* dst_null_branch = OpCmpImmBranch(kCondEq, rs_rCX , 0, nullptr); 1124 LoadValueDirectFixed(rl_length , rs_rDX); 1125 LIR* len_negative = OpCmpImmBranch(kCondLt, rs_rDX , 0, nullptr); 1126 LIR* len_too_big = OpCmpImmBranch(kCondGt, rs_rDX , 128, nullptr); 1127 LoadValueDirectFixed(rl_src , rs_rAX); 1128 LoadWordDisp(rs_rAX , mirror::Array::LengthOffset().Int32Value(), rs_rAX); 1129 LIR* src_bad_len = nullptr; 1130 LIR* srcPos_negative = nullptr; 1131 if (!rl_srcPos.is_const) { 1132 LoadValueDirectFixed(rl_srcPos , rs_rBX); 1133 srcPos_negative = OpCmpImmBranch(kCondLt, rs_rBX , 0, nullptr); 1134 OpRegReg(kOpAdd, rs_rBX, rs_rDX); 1135 src_bad_len = OpCmpBranch(kCondLt, rs_rAX , rs_rBX, nullptr); 1136 } else { 1137 int pos_val = mir_graph_->ConstantValue(rl_srcPos.orig_sreg); 1138 if (pos_val == 0) { 1139 src_bad_len = OpCmpBranch(kCondLt, rs_rAX , rs_rDX, nullptr); 1140 } else { 1141 OpRegRegImm(kOpAdd, rs_rBX, rs_rDX, pos_val); 1142 src_bad_len = OpCmpBranch(kCondLt, rs_rAX , rs_rBX, nullptr); 1143 } 1144 } 1145 LIR* dstPos_negative = nullptr; 1146 LIR* dst_bad_len = nullptr; 1147 LoadValueDirectFixed(rl_dst, rs_rAX); 1148 LoadWordDisp(rs_rAX, mirror::Array::LengthOffset().Int32Value(), rs_rAX); 1149 if (!rl_dstPos.is_const) { 1150 LoadValueDirectFixed(rl_dstPos , rs_rBX); 1151 dstPos_negative = OpCmpImmBranch(kCondLt, rs_rBX , 0, nullptr); 1152 OpRegRegReg(kOpAdd, rs_rBX, rs_rBX, rs_rDX); 1153 dst_bad_len = OpCmpBranch(kCondLt, rs_rAX , rs_rBX, nullptr); 1154 } else { 1155 int pos_val = mir_graph_->ConstantValue(rl_dstPos.orig_sreg); 1156 if (pos_val == 0) { 1157 dst_bad_len = OpCmpBranch(kCondLt, rs_rAX , rs_rDX, nullptr); 1158 } else { 1159 OpRegRegImm(kOpAdd, rs_rBX, rs_rDX, pos_val); 1160 dst_bad_len = OpCmpBranch(kCondLt, rs_rAX , rs_rBX, nullptr); 1161 } 1162 } 1163 // everything is checked now 1164 LoadValueDirectFixed(rl_src , rs_rAX); 1165 LoadValueDirectFixed(rl_dst , rs_rBX); 1166 LoadValueDirectFixed(rl_srcPos , rs_rCX); 1167 NewLIR5(kX86Lea32RA, rs_rAX.GetReg(), rs_rAX.GetReg(), 1168 rs_rCX.GetReg() , 1, mirror::Array::DataOffset(2).Int32Value()); 1169 // RAX now holds the address of the first src element to be copied 1170 1171 LoadValueDirectFixed(rl_dstPos , rs_rCX); 1172 NewLIR5(kX86Lea32RA, rs_rBX.GetReg(), rs_rBX.GetReg(), 1173 rs_rCX.GetReg() , 1, mirror::Array::DataOffset(2).Int32Value() ); 1174 // RBX now holds the address of the first dst element to be copied 1175 1176 // check if the number of elements to be copied is odd or even. If odd 1177 // then copy the first element (so that the remaining number of elements 1178 // is even). 1179 LoadValueDirectFixed(rl_length , rs_rCX); 1180 OpRegImm(kOpAnd, rs_rCX, 1); 1181 LIR* jmp_to_begin_loop = OpCmpImmBranch(kCondEq, rs_rCX, 0, nullptr); 1182 OpRegImm(kOpSub, rs_rDX, 1); 1183 LoadBaseIndexedDisp(rs_rAX, rs_rDX, 1, 0, rs_rCX, kSignedHalf); 1184 StoreBaseIndexedDisp(rs_rBX, rs_rDX, 1, 0, rs_rCX, kSignedHalf); 1185 1186 // since the remaining number of elements is even, we will copy by 1187 // two elements at a time. 1188 LIR *beginLoop = NewLIR0(kPseudoTargetLabel); 1189 LIR* jmp_to_ret = OpCmpImmBranch(kCondEq, rs_rDX , 0, nullptr); 1190 OpRegImm(kOpSub, rs_rDX, 2); 1191 LoadBaseIndexedDisp(rs_rAX, rs_rDX, 1, 0, rs_rCX, kSingle); 1192 StoreBaseIndexedDisp(rs_rBX, rs_rDX, 1, 0, rs_rCX, kSingle); 1193 OpUnconditionalBranch(beginLoop); 1194 LIR *check_failed = NewLIR0(kPseudoTargetLabel); 1195 LIR* launchpad_branch = OpUnconditionalBranch(nullptr); 1196 LIR *return_point = NewLIR0(kPseudoTargetLabel); 1197 jmp_to_ret->target = return_point; 1198 jmp_to_begin_loop->target = beginLoop; 1199 src_dst_same->target = check_failed; 1200 len_negative->target = check_failed; 1201 len_too_big->target = check_failed; 1202 src_null_branch->target = check_failed; 1203 if (srcPos_negative != nullptr) 1204 srcPos_negative ->target = check_failed; 1205 if (src_bad_len != nullptr) 1206 src_bad_len->target = check_failed; 1207 dst_null_branch->target = check_failed; 1208 if (dstPos_negative != nullptr) 1209 dstPos_negative->target = check_failed; 1210 if (dst_bad_len != nullptr) 1211 dst_bad_len->target = check_failed; 1212 AddIntrinsicSlowPath(info, launchpad_branch, return_point); 1213 return true; 1214} 1215 1216 1217/* 1218 * Fast string.index_of(I) & (II). Inline check for simple case of char <= 0xffff, 1219 * otherwise bails to standard library code. 1220 */ 1221bool X86Mir2Lir::GenInlinedIndexOf(CallInfo* info, bool zero_based) { 1222 RegLocation rl_obj = info->args[0]; 1223 RegLocation rl_char = info->args[1]; 1224 RegLocation rl_start; // Note: only present in III flavor or IndexOf. 1225 // RBX is callee-save register in 64-bit mode. 1226 RegStorage rs_tmp = cu_->target64 ? rs_r11 : rs_rBX; 1227 int start_value = -1; 1228 1229 uint32_t char_value = 1230 rl_char.is_const ? mir_graph_->ConstantValue(rl_char.orig_sreg) : 0; 1231 1232 if (char_value > 0xFFFF) { 1233 // We have to punt to the real String.indexOf. 1234 return false; 1235 } 1236 1237 // Okay, we are commited to inlining this. 1238 // EAX: 16 bit character being searched. 1239 // ECX: count: number of words to be searched. 1240 // EDI: String being searched. 1241 // EDX: temporary during execution. 1242 // EBX or R11: temporary during execution (depending on mode). 1243 // REP SCASW: search instruction. 1244 1245 FlushReg(rs_rAX); 1246 Clobber(rs_rAX); 1247 LockTemp(rs_rAX); 1248 FlushReg(rs_rCX); 1249 Clobber(rs_rCX); 1250 LockTemp(rs_rCX); 1251 FlushReg(rs_rDX); 1252 Clobber(rs_rDX); 1253 LockTemp(rs_rDX); 1254 FlushReg(rs_tmp); 1255 Clobber(rs_tmp); 1256 LockTemp(rs_tmp); 1257 if (cu_->target64) { 1258 FlushReg(rs_rDI); 1259 Clobber(rs_rDI); 1260 LockTemp(rs_rDI); 1261 } 1262 1263 RegLocation rl_return = GetReturn(kCoreReg); 1264 RegLocation rl_dest = InlineTarget(info); 1265 1266 // Is the string non-NULL? 1267 LoadValueDirectFixed(rl_obj, rs_rDX); 1268 GenNullCheck(rs_rDX, info->opt_flags); 1269 info->opt_flags |= MIR_IGNORE_NULL_CHECK; // Record that we've null checked. 1270 1271 LIR *slowpath_branch = nullptr, *length_compare = nullptr; 1272 1273 // We need the value in EAX. 1274 if (rl_char.is_const) { 1275 LoadConstantNoClobber(rs_rAX, char_value); 1276 } else { 1277 // Does the character fit in 16 bits? Compare it at runtime. 1278 LoadValueDirectFixed(rl_char, rs_rAX); 1279 slowpath_branch = OpCmpImmBranch(kCondGt, rs_rAX, 0xFFFF, nullptr); 1280 } 1281 1282 // From here down, we know that we are looking for a char that fits in 16 bits. 1283 // Location of reference to data array within the String object. 1284 int value_offset = mirror::String::ValueOffset().Int32Value(); 1285 // Location of count within the String object. 1286 int count_offset = mirror::String::CountOffset().Int32Value(); 1287 // Starting offset within data array. 1288 int offset_offset = mirror::String::OffsetOffset().Int32Value(); 1289 // Start of char data with array_. 1290 int data_offset = mirror::Array::DataOffset(sizeof(uint16_t)).Int32Value(); 1291 1292 // Compute the number of words to search in to rCX. 1293 Load32Disp(rs_rDX, count_offset, rs_rCX); 1294 1295 if (!cu_->target64) { 1296 // Possible signal here due to null pointer dereference. 1297 // Note that the signal handler will expect the top word of 1298 // the stack to be the ArtMethod*. If the PUSH edi instruction 1299 // below is ahead of the load above then this will not be true 1300 // and the signal handler will not work. 1301 MarkPossibleNullPointerException(0); 1302 1303 // EDI is callee-save register in 32-bit mode. 1304 NewLIR1(kX86Push32R, rs_rDI.GetReg()); 1305 } 1306 1307 if (zero_based) { 1308 // Start index is not present. 1309 // We have to handle an empty string. Use special instruction JECXZ. 1310 length_compare = NewLIR0(kX86Jecxz8); 1311 1312 // Copy the number of words to search in a temporary register. 1313 // We will use the register at the end to calculate result. 1314 OpRegReg(kOpMov, rs_tmp, rs_rCX); 1315 } else { 1316 // Start index is present. 1317 rl_start = info->args[2]; 1318 1319 // We have to offset by the start index. 1320 if (rl_start.is_const) { 1321 start_value = mir_graph_->ConstantValue(rl_start.orig_sreg); 1322 start_value = std::max(start_value, 0); 1323 1324 // Is the start > count? 1325 length_compare = OpCmpImmBranch(kCondLe, rs_rCX, start_value, nullptr); 1326 OpRegImm(kOpMov, rs_rDI, start_value); 1327 1328 // Copy the number of words to search in a temporary register. 1329 // We will use the register at the end to calculate result. 1330 OpRegReg(kOpMov, rs_tmp, rs_rCX); 1331 1332 if (start_value != 0) { 1333 // Decrease the number of words to search by the start index. 1334 OpRegImm(kOpSub, rs_rCX, start_value); 1335 } 1336 } else { 1337 // Handle "start index < 0" case. 1338 if (!cu_->target64 && rl_start.location != kLocPhysReg) { 1339 // Load the start index from stack, remembering that we pushed EDI. 1340 int displacement = SRegOffset(rl_start.s_reg_low) + sizeof(uint32_t); 1341 { 1342 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); 1343 Load32Disp(rs_rX86_SP, displacement, rs_rDI); 1344 } 1345 } else { 1346 LoadValueDirectFixed(rl_start, rs_rDI); 1347 } 1348 OpRegReg(kOpXor, rs_tmp, rs_tmp); 1349 OpRegReg(kOpCmp, rs_rDI, rs_tmp); 1350 OpCondRegReg(kOpCmov, kCondLt, rs_rDI, rs_tmp); 1351 1352 // The length of the string should be greater than the start index. 1353 length_compare = OpCmpBranch(kCondLe, rs_rCX, rs_rDI, nullptr); 1354 1355 // Copy the number of words to search in a temporary register. 1356 // We will use the register at the end to calculate result. 1357 OpRegReg(kOpMov, rs_tmp, rs_rCX); 1358 1359 // Decrease the number of words to search by the start index. 1360 OpRegReg(kOpSub, rs_rCX, rs_rDI); 1361 } 1362 } 1363 1364 // Load the address of the string into EDI. 1365 // In case of start index we have to add the address to existing value in EDI. 1366 // The string starts at VALUE(String) + 2 * OFFSET(String) + DATA_OFFSET. 1367 if (zero_based || (!zero_based && rl_start.is_const && start_value == 0)) { 1368 Load32Disp(rs_rDX, offset_offset, rs_rDI); 1369 } else { 1370 OpRegMem(kOpAdd, rs_rDI, rs_rDX, offset_offset); 1371 } 1372 OpRegImm(kOpLsl, rs_rDI, 1); 1373 OpRegMem(kOpAdd, rs_rDI, rs_rDX, value_offset); 1374 OpRegImm(kOpAdd, rs_rDI, data_offset); 1375 1376 // EDI now contains the start of the string to be searched. 1377 // We are all prepared to do the search for the character. 1378 NewLIR0(kX86RepneScasw); 1379 1380 // Did we find a match? 1381 LIR* failed_branch = OpCondBranch(kCondNe, nullptr); 1382 1383 // yes, we matched. Compute the index of the result. 1384 OpRegReg(kOpSub, rs_tmp, rs_rCX); 1385 NewLIR3(kX86Lea32RM, rl_return.reg.GetReg(), rs_tmp.GetReg(), -1); 1386 1387 LIR *all_done = NewLIR1(kX86Jmp8, 0); 1388 1389 // Failed to match; return -1. 1390 LIR *not_found = NewLIR0(kPseudoTargetLabel); 1391 length_compare->target = not_found; 1392 failed_branch->target = not_found; 1393 LoadConstantNoClobber(rl_return.reg, -1); 1394 1395 // And join up at the end. 1396 all_done->target = NewLIR0(kPseudoTargetLabel); 1397 1398 if (!cu_->target64) 1399 NewLIR1(kX86Pop32R, rs_rDI.GetReg()); 1400 1401 // Out of line code returns here. 1402 if (slowpath_branch != nullptr) { 1403 LIR *return_point = NewLIR0(kPseudoTargetLabel); 1404 AddIntrinsicSlowPath(info, slowpath_branch, return_point); 1405 } 1406 1407 StoreValue(rl_dest, rl_return); 1408 1409 FreeTemp(rs_rAX); 1410 FreeTemp(rs_rCX); 1411 FreeTemp(rs_rDX); 1412 FreeTemp(rs_tmp); 1413 if (cu_->target64) { 1414 FreeTemp(rs_rDI); 1415 } 1416 1417 return true; 1418} 1419 1420/* 1421 * @brief Enter an 'advance LOC' into the FDE buffer 1422 * @param buf FDE buffer. 1423 * @param increment Amount by which to increase the current location. 1424 */ 1425static void AdvanceLoc(std::vector<uint8_t>&buf, uint32_t increment) { 1426 if (increment < 64) { 1427 // Encoding in opcode. 1428 buf.push_back(0x1 << 6 | increment); 1429 } else if (increment < 256) { 1430 // Single byte delta. 1431 buf.push_back(0x02); 1432 buf.push_back(increment); 1433 } else if (increment < 256 * 256) { 1434 // Two byte delta. 1435 buf.push_back(0x03); 1436 buf.push_back(increment & 0xff); 1437 buf.push_back((increment >> 8) & 0xff); 1438 } else { 1439 // Four byte delta. 1440 buf.push_back(0x04); 1441 PushWord(buf, increment); 1442 } 1443} 1444 1445 1446std::vector<uint8_t>* X86CFIInitialization() { 1447 return X86Mir2Lir::ReturnCommonCallFrameInformation(); 1448} 1449 1450std::vector<uint8_t>* X86Mir2Lir::ReturnCommonCallFrameInformation() { 1451 std::vector<uint8_t>*cfi_info = new std::vector<uint8_t>; 1452 1453 // Length of the CIE (except for this field). 1454 PushWord(*cfi_info, 16); 1455 1456 // CIE id. 1457 PushWord(*cfi_info, 0xFFFFFFFFU); 1458 1459 // Version: 3. 1460 cfi_info->push_back(0x03); 1461 1462 // Augmentation: empty string. 1463 cfi_info->push_back(0x0); 1464 1465 // Code alignment: 1. 1466 cfi_info->push_back(0x01); 1467 1468 // Data alignment: -4. 1469 cfi_info->push_back(0x7C); 1470 1471 // Return address register (R8). 1472 cfi_info->push_back(0x08); 1473 1474 // Initial return PC is 4(ESP): DW_CFA_def_cfa R4 4. 1475 cfi_info->push_back(0x0C); 1476 cfi_info->push_back(0x04); 1477 cfi_info->push_back(0x04); 1478 1479 // Return address location: 0(SP): DW_CFA_offset R8 1 (* -4);. 1480 cfi_info->push_back(0x2 << 6 | 0x08); 1481 cfi_info->push_back(0x01); 1482 1483 // And 2 Noops to align to 4 byte boundary. 1484 cfi_info->push_back(0x0); 1485 cfi_info->push_back(0x0); 1486 1487 DCHECK_EQ(cfi_info->size() & 3, 0U); 1488 return cfi_info; 1489} 1490 1491static void EncodeUnsignedLeb128(std::vector<uint8_t>& buf, uint32_t value) { 1492 uint8_t buffer[12]; 1493 uint8_t *ptr = EncodeUnsignedLeb128(buffer, value); 1494 for (uint8_t *p = buffer; p < ptr; p++) { 1495 buf.push_back(*p); 1496 } 1497} 1498 1499std::vector<uint8_t>* X86Mir2Lir::ReturnCallFrameInformation() { 1500 std::vector<uint8_t>*cfi_info = new std::vector<uint8_t>; 1501 1502 // Generate the FDE for the method. 1503 DCHECK_NE(data_offset_, 0U); 1504 1505 // Length (will be filled in later in this routine). 1506 PushWord(*cfi_info, 0); 1507 1508 // CIE_pointer (can be filled in by linker); might be left at 0 if there is only 1509 // one CIE for the whole debug_frame section. 1510 PushWord(*cfi_info, 0); 1511 1512 // 'initial_location' (filled in by linker). 1513 PushWord(*cfi_info, 0); 1514 1515 // 'address_range' (number of bytes in the method). 1516 PushWord(*cfi_info, data_offset_); 1517 1518 // The instructions in the FDE. 1519 if (stack_decrement_ != nullptr) { 1520 // Advance LOC to just past the stack decrement. 1521 uint32_t pc = NEXT_LIR(stack_decrement_)->offset; 1522 AdvanceLoc(*cfi_info, pc); 1523 1524 // Now update the offset to the call frame: DW_CFA_def_cfa_offset frame_size. 1525 cfi_info->push_back(0x0e); 1526 EncodeUnsignedLeb128(*cfi_info, frame_size_); 1527 1528 // We continue with that stack until the epilogue. 1529 if (stack_increment_ != nullptr) { 1530 uint32_t new_pc = NEXT_LIR(stack_increment_)->offset; 1531 AdvanceLoc(*cfi_info, new_pc - pc); 1532 1533 // We probably have code snippets after the epilogue, so save the 1534 // current state: DW_CFA_remember_state. 1535 cfi_info->push_back(0x0a); 1536 1537 // We have now popped the stack: DW_CFA_def_cfa_offset 4. There is only the return 1538 // PC on the stack now. 1539 cfi_info->push_back(0x0e); 1540 EncodeUnsignedLeb128(*cfi_info, 4); 1541 1542 // Everything after that is the same as before the epilogue. 1543 // Stack bump was followed by RET instruction. 1544 LIR *post_ret_insn = NEXT_LIR(NEXT_LIR(stack_increment_)); 1545 if (post_ret_insn != nullptr) { 1546 pc = new_pc; 1547 new_pc = post_ret_insn->offset; 1548 AdvanceLoc(*cfi_info, new_pc - pc); 1549 // Restore the state: DW_CFA_restore_state. 1550 cfi_info->push_back(0x0b); 1551 } 1552 } 1553 } 1554 1555 // Padding to a multiple of 4 1556 while ((cfi_info->size() & 3) != 0) { 1557 // DW_CFA_nop is encoded as 0. 1558 cfi_info->push_back(0); 1559 } 1560 1561 // Set the length of the FDE inside the generated bytes. 1562 uint32_t length = cfi_info->size() - 4; 1563 (*cfi_info)[0] = length; 1564 (*cfi_info)[1] = length >> 8; 1565 (*cfi_info)[2] = length >> 16; 1566 (*cfi_info)[3] = length >> 24; 1567 return cfi_info; 1568} 1569 1570void X86Mir2Lir::GenMachineSpecificExtendedMethodMIR(BasicBlock* bb, MIR* mir) { 1571 switch (static_cast<ExtendedMIROpcode>(mir->dalvikInsn.opcode)) { 1572 case kMirOpReserveVectorRegisters: 1573 ReserveVectorRegisters(mir); 1574 break; 1575 case kMirOpReturnVectorRegisters: 1576 ReturnVectorRegisters(); 1577 break; 1578 case kMirOpConstVector: 1579 GenConst128(bb, mir); 1580 break; 1581 case kMirOpMoveVector: 1582 GenMoveVector(bb, mir); 1583 break; 1584 case kMirOpPackedMultiply: 1585 GenMultiplyVector(bb, mir); 1586 break; 1587 case kMirOpPackedAddition: 1588 GenAddVector(bb, mir); 1589 break; 1590 case kMirOpPackedSubtract: 1591 GenSubtractVector(bb, mir); 1592 break; 1593 case kMirOpPackedShiftLeft: 1594 GenShiftLeftVector(bb, mir); 1595 break; 1596 case kMirOpPackedSignedShiftRight: 1597 GenSignedShiftRightVector(bb, mir); 1598 break; 1599 case kMirOpPackedUnsignedShiftRight: 1600 GenUnsignedShiftRightVector(bb, mir); 1601 break; 1602 case kMirOpPackedAnd: 1603 GenAndVector(bb, mir); 1604 break; 1605 case kMirOpPackedOr: 1606 GenOrVector(bb, mir); 1607 break; 1608 case kMirOpPackedXor: 1609 GenXorVector(bb, mir); 1610 break; 1611 case kMirOpPackedAddReduce: 1612 GenAddReduceVector(bb, mir); 1613 break; 1614 case kMirOpPackedReduce: 1615 GenReduceVector(bb, mir); 1616 break; 1617 case kMirOpPackedSet: 1618 GenSetVector(bb, mir); 1619 break; 1620 default: 1621 break; 1622 } 1623} 1624 1625void X86Mir2Lir::ReserveVectorRegisters(MIR* mir) { 1626 // We should not try to reserve twice without returning the registers 1627 DCHECK_NE(num_reserved_vector_regs_, -1); 1628 1629 int num_vector_reg = mir->dalvikInsn.vA; 1630 for (int i = 0; i < num_vector_reg; i++) { 1631 RegStorage xp_reg = RegStorage::Solo128(i); 1632 RegisterInfo *xp_reg_info = GetRegInfo(xp_reg); 1633 Clobber(xp_reg); 1634 1635 for (RegisterInfo *info = xp_reg_info->GetAliasChain(); 1636 info != nullptr; 1637 info = info->GetAliasChain()) { 1638 if (info->GetReg().IsSingle()) { 1639 reg_pool_->sp_regs_.Delete(info); 1640 } else { 1641 reg_pool_->dp_regs_.Delete(info); 1642 } 1643 } 1644 } 1645 1646 num_reserved_vector_regs_ = num_vector_reg; 1647} 1648 1649void X86Mir2Lir::ReturnVectorRegisters() { 1650 // Return all the reserved registers 1651 for (int i = 0; i < num_reserved_vector_regs_; i++) { 1652 RegStorage xp_reg = RegStorage::Solo128(i); 1653 RegisterInfo *xp_reg_info = GetRegInfo(xp_reg); 1654 1655 for (RegisterInfo *info = xp_reg_info->GetAliasChain(); 1656 info != nullptr; 1657 info = info->GetAliasChain()) { 1658 if (info->GetReg().IsSingle()) { 1659 reg_pool_->sp_regs_.Insert(info); 1660 } else { 1661 reg_pool_->dp_regs_.Insert(info); 1662 } 1663 } 1664 } 1665 1666 // We don't have anymore reserved vector registers 1667 num_reserved_vector_regs_ = -1; 1668} 1669 1670void X86Mir2Lir::GenConst128(BasicBlock* bb, MIR* mir) { 1671 store_method_addr_used_ = true; 1672 int type_size = mir->dalvikInsn.vB; 1673 // We support 128 bit vectors. 1674 DCHECK_EQ(type_size & 0xFFFF, 128); 1675 RegStorage rs_dest = RegStorage::Solo128(mir->dalvikInsn.vA); 1676 uint32_t *args = mir->dalvikInsn.arg; 1677 int reg = rs_dest.GetReg(); 1678 // Check for all 0 case. 1679 if (args[0] == 0 && args[1] == 0 && args[2] == 0 && args[3] == 0) { 1680 NewLIR2(kX86XorpsRR, reg, reg); 1681 return; 1682 } 1683 1684 // Append the mov const vector to reg opcode. 1685 AppendOpcodeWithConst(kX86MovupsRM, reg, mir); 1686} 1687 1688void X86Mir2Lir::AppendOpcodeWithConst(X86OpCode opcode, int reg, MIR* mir) { 1689 // Okay, load it from the constant vector area. 1690 LIR *data_target = ScanVectorLiteral(mir); 1691 if (data_target == nullptr) { 1692 data_target = AddVectorLiteral(mir); 1693 } 1694 1695 // Address the start of the method. 1696 RegLocation rl_method = mir_graph_->GetRegLocation(base_of_code_->s_reg_low); 1697 if (rl_method.wide) { 1698 rl_method = LoadValueWide(rl_method, kCoreReg); 1699 } else { 1700 rl_method = LoadValue(rl_method, kCoreReg); 1701 } 1702 1703 // Load the proper value from the literal area. 1704 // We don't know the proper offset for the value, so pick one that will force 1705 // 4 byte offset. We will fix this up in the assembler later to have the right 1706 // value. 1707 ScopedMemRefType mem_ref_type(this, ResourceMask::kLiteral); 1708 LIR *load = NewLIR2(opcode, reg, rl_method.reg.GetReg()); 1709 load->flags.fixup = kFixupLoad; 1710 load->target = data_target; 1711} 1712 1713void X86Mir2Lir::GenMoveVector(BasicBlock *bb, MIR *mir) { 1714 // We only support 128 bit registers. 1715 DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U); 1716 RegStorage rs_dest = RegStorage::Solo128(mir->dalvikInsn.vA); 1717 RegStorage rs_src = RegStorage::Solo128(mir->dalvikInsn.vB); 1718 NewLIR2(kX86Mova128RR, rs_dest.GetReg(), rs_src.GetReg()); 1719} 1720 1721void X86Mir2Lir::GenMultiplyVectorSignedByte(BasicBlock *bb, MIR *mir) { 1722 const int BYTE_SIZE = 8; 1723 RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA); 1724 RegStorage rs_src2 = RegStorage::Solo128(mir->dalvikInsn.vB); 1725 RegStorage rs_src1_high_tmp = Get128BitRegister(AllocTempWide()); 1726 1727 /* 1728 * Emulate the behavior of a kSignedByte by separating out the 16 values in the two XMM 1729 * and multiplying 8 at a time before recombining back into one XMM register. 1730 * 1731 * let xmm1, xmm2 be real srcs (keep low bits of 16bit lanes) 1732 * xmm3 is tmp (operate on high bits of 16bit lanes) 1733 * 1734 * xmm3 = xmm1 1735 * xmm1 = xmm1 .* xmm2 1736 * xmm1 = xmm1 & 0x00ff00ff00ff00ff00ff00ff00ff00ff // xmm1 now has low bits 1737 * xmm3 = xmm3 .>> 8 1738 * xmm2 = xmm2 & 0xff00ff00ff00ff00ff00ff00ff00ff00 1739 * xmm2 = xmm2 .* xmm3 // xmm2 now has high bits 1740 * xmm1 = xmm1 | xmm2 // combine results 1741 */ 1742 1743 // Copy xmm1. 1744 NewLIR2(kX86Mova128RR, rs_src1_high_tmp.GetReg(), rs_dest_src1.GetReg()); 1745 1746 // Multiply low bits. 1747 NewLIR2(kX86PmullwRR, rs_dest_src1.GetReg(), rs_src2.GetReg()); 1748 1749 // xmm1 now has low bits. 1750 AndMaskVectorRegister(rs_dest_src1, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF); 1751 1752 // Prepare high bits for multiplication. 1753 NewLIR2(kX86PsrlwRI, rs_src1_high_tmp.GetReg(), BYTE_SIZE); 1754 AndMaskVectorRegister(rs_src2, 0xFF00FF00, 0xFF00FF00, 0xFF00FF00, 0xFF00FF00); 1755 1756 // Multiply high bits and xmm2 now has high bits. 1757 NewLIR2(kX86PmullwRR, rs_src2.GetReg(), rs_src1_high_tmp.GetReg()); 1758 1759 // Combine back into dest XMM register. 1760 NewLIR2(kX86PorRR, rs_dest_src1.GetReg(), rs_src2.GetReg()); 1761} 1762 1763void X86Mir2Lir::GenMultiplyVector(BasicBlock *bb, MIR *mir) { 1764 DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U); 1765 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); 1766 RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA); 1767 RegStorage rs_src2 = RegStorage::Solo128(mir->dalvikInsn.vB); 1768 int opcode = 0; 1769 switch (opsize) { 1770 case k32: 1771 opcode = kX86PmulldRR; 1772 break; 1773 case kSignedHalf: 1774 opcode = kX86PmullwRR; 1775 break; 1776 case kSingle: 1777 opcode = kX86MulpsRR; 1778 break; 1779 case kDouble: 1780 opcode = kX86MulpdRR; 1781 break; 1782 case kSignedByte: 1783 // HW doesn't support 16x16 byte multiplication so emulate it. 1784 GenMultiplyVectorSignedByte(bb, mir); 1785 return; 1786 default: 1787 LOG(FATAL) << "Unsupported vector multiply " << opsize; 1788 break; 1789 } 1790 NewLIR2(opcode, rs_dest_src1.GetReg(), rs_src2.GetReg()); 1791} 1792 1793void X86Mir2Lir::GenAddVector(BasicBlock *bb, MIR *mir) { 1794 DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U); 1795 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); 1796 RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA); 1797 RegStorage rs_src2 = RegStorage::Solo128(mir->dalvikInsn.vB); 1798 int opcode = 0; 1799 switch (opsize) { 1800 case k32: 1801 opcode = kX86PadddRR; 1802 break; 1803 case kSignedHalf: 1804 case kUnsignedHalf: 1805 opcode = kX86PaddwRR; 1806 break; 1807 case kUnsignedByte: 1808 case kSignedByte: 1809 opcode = kX86PaddbRR; 1810 break; 1811 case kSingle: 1812 opcode = kX86AddpsRR; 1813 break; 1814 case kDouble: 1815 opcode = kX86AddpdRR; 1816 break; 1817 default: 1818 LOG(FATAL) << "Unsupported vector addition " << opsize; 1819 break; 1820 } 1821 NewLIR2(opcode, rs_dest_src1.GetReg(), rs_src2.GetReg()); 1822} 1823 1824void X86Mir2Lir::GenSubtractVector(BasicBlock *bb, MIR *mir) { 1825 DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U); 1826 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); 1827 RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA); 1828 RegStorage rs_src2 = RegStorage::Solo128(mir->dalvikInsn.vB); 1829 int opcode = 0; 1830 switch (opsize) { 1831 case k32: 1832 opcode = kX86PsubdRR; 1833 break; 1834 case kSignedHalf: 1835 case kUnsignedHalf: 1836 opcode = kX86PsubwRR; 1837 break; 1838 case kUnsignedByte: 1839 case kSignedByte: 1840 opcode = kX86PsubbRR; 1841 break; 1842 case kSingle: 1843 opcode = kX86SubpsRR; 1844 break; 1845 case kDouble: 1846 opcode = kX86SubpdRR; 1847 break; 1848 default: 1849 LOG(FATAL) << "Unsupported vector subtraction " << opsize; 1850 break; 1851 } 1852 NewLIR2(opcode, rs_dest_src1.GetReg(), rs_src2.GetReg()); 1853} 1854 1855void X86Mir2Lir::GenShiftByteVector(BasicBlock *bb, MIR *mir) { 1856 RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA); 1857 RegStorage rs_tmp = Get128BitRegister(AllocTempWide()); 1858 1859 int opcode = 0; 1860 int imm = mir->dalvikInsn.vB; 1861 1862 switch (static_cast<ExtendedMIROpcode>(mir->dalvikInsn.opcode)) { 1863 case kMirOpPackedShiftLeft: 1864 opcode = kX86PsllwRI; 1865 break; 1866 case kMirOpPackedSignedShiftRight: 1867 opcode = kX86PsrawRI; 1868 break; 1869 case kMirOpPackedUnsignedShiftRight: 1870 opcode = kX86PsrlwRI; 1871 break; 1872 default: 1873 LOG(FATAL) << "Unsupported shift operation on byte vector " << opcode; 1874 break; 1875 } 1876 1877 /* 1878 * xmm1 will have low bits 1879 * xmm2 will have high bits 1880 * 1881 * xmm2 = xmm1 1882 * xmm1 = xmm1 .<< N 1883 * xmm2 = xmm2 && 0xFF00FF00FF00FF00FF00FF00FF00FF00 1884 * xmm2 = xmm2 .<< N 1885 * xmm1 = xmm1 | xmm2 1886 */ 1887 1888 // Copy xmm1. 1889 NewLIR2(kX86Mova128RR, rs_tmp.GetReg(), rs_dest_src1.GetReg()); 1890 1891 // Shift lower values. 1892 NewLIR2(opcode, rs_dest_src1.GetReg(), imm); 1893 1894 // Mask bottom bits. 1895 AndMaskVectorRegister(rs_tmp, 0xFF00FF00, 0xFF00FF00, 0xFF00FF00, 0xFF00FF00); 1896 1897 // Shift higher values. 1898 NewLIR2(opcode, rs_tmp.GetReg(), imm); 1899 1900 // Combine back into dest XMM register. 1901 NewLIR2(kX86PorRR, rs_dest_src1.GetReg(), rs_tmp.GetReg()); 1902} 1903 1904void X86Mir2Lir::GenShiftLeftVector(BasicBlock *bb, MIR *mir) { 1905 DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U); 1906 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); 1907 RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA); 1908 int imm = mir->dalvikInsn.vB; 1909 int opcode = 0; 1910 switch (opsize) { 1911 case k32: 1912 opcode = kX86PslldRI; 1913 break; 1914 case k64: 1915 opcode = kX86PsllqRI; 1916 break; 1917 case kSignedHalf: 1918 case kUnsignedHalf: 1919 opcode = kX86PsllwRI; 1920 break; 1921 case kSignedByte: 1922 case kUnsignedByte: 1923 GenShiftByteVector(bb, mir); 1924 return; 1925 default: 1926 LOG(FATAL) << "Unsupported vector shift left " << opsize; 1927 break; 1928 } 1929 NewLIR2(opcode, rs_dest_src1.GetReg(), imm); 1930} 1931 1932void X86Mir2Lir::GenSignedShiftRightVector(BasicBlock *bb, MIR *mir) { 1933 DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U); 1934 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); 1935 RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA); 1936 int imm = mir->dalvikInsn.vB; 1937 int opcode = 0; 1938 switch (opsize) { 1939 case k32: 1940 opcode = kX86PsradRI; 1941 break; 1942 case kSignedHalf: 1943 case kUnsignedHalf: 1944 opcode = kX86PsrawRI; 1945 break; 1946 case kSignedByte: 1947 case kUnsignedByte: 1948 GenShiftByteVector(bb, mir); 1949 return; 1950 default: 1951 LOG(FATAL) << "Unsupported vector signed shift right " << opsize; 1952 break; 1953 } 1954 NewLIR2(opcode, rs_dest_src1.GetReg(), imm); 1955} 1956 1957void X86Mir2Lir::GenUnsignedShiftRightVector(BasicBlock *bb, MIR *mir) { 1958 DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U); 1959 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); 1960 RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA); 1961 int imm = mir->dalvikInsn.vB; 1962 int opcode = 0; 1963 switch (opsize) { 1964 case k32: 1965 opcode = kX86PsrldRI; 1966 break; 1967 case k64: 1968 opcode = kX86PsrlqRI; 1969 break; 1970 case kSignedHalf: 1971 case kUnsignedHalf: 1972 opcode = kX86PsrlwRI; 1973 break; 1974 case kSignedByte: 1975 case kUnsignedByte: 1976 GenShiftByteVector(bb, mir); 1977 return; 1978 default: 1979 LOG(FATAL) << "Unsupported vector unsigned shift right " << opsize; 1980 break; 1981 } 1982 NewLIR2(opcode, rs_dest_src1.GetReg(), imm); 1983} 1984 1985void X86Mir2Lir::GenAndVector(BasicBlock *bb, MIR *mir) { 1986 // We only support 128 bit registers. 1987 DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U); 1988 RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA); 1989 RegStorage rs_src2 = RegStorage::Solo128(mir->dalvikInsn.vB); 1990 NewLIR2(kX86PandRR, rs_dest_src1.GetReg(), rs_src2.GetReg()); 1991} 1992 1993void X86Mir2Lir::GenOrVector(BasicBlock *bb, MIR *mir) { 1994 // We only support 128 bit registers. 1995 DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U); 1996 RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA); 1997 RegStorage rs_src2 = RegStorage::Solo128(mir->dalvikInsn.vB); 1998 NewLIR2(kX86PorRR, rs_dest_src1.GetReg(), rs_src2.GetReg()); 1999} 2000 2001void X86Mir2Lir::GenXorVector(BasicBlock *bb, MIR *mir) { 2002 // We only support 128 bit registers. 2003 DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U); 2004 RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA); 2005 RegStorage rs_src2 = RegStorage::Solo128(mir->dalvikInsn.vB); 2006 NewLIR2(kX86PxorRR, rs_dest_src1.GetReg(), rs_src2.GetReg()); 2007} 2008 2009void X86Mir2Lir::AndMaskVectorRegister(RegStorage rs_src1, uint32_t m1, uint32_t m2, uint32_t m3, uint32_t m4) { 2010 MaskVectorRegister(kX86PandRM, rs_src1, m1, m2, m3, m4); 2011} 2012 2013void X86Mir2Lir::MaskVectorRegister(X86OpCode opcode, RegStorage rs_src1, uint32_t m0, uint32_t m1, uint32_t m2, uint32_t m3) { 2014 // Create temporary MIR as container for 128-bit binary mask. 2015 MIR const_mir; 2016 MIR* const_mirp = &const_mir; 2017 const_mirp->dalvikInsn.opcode = static_cast<Instruction::Code>(kMirOpConstVector); 2018 const_mirp->dalvikInsn.arg[0] = m0; 2019 const_mirp->dalvikInsn.arg[1] = m1; 2020 const_mirp->dalvikInsn.arg[2] = m2; 2021 const_mirp->dalvikInsn.arg[3] = m3; 2022 2023 // Mask vector with const from literal pool. 2024 AppendOpcodeWithConst(opcode, rs_src1.GetReg(), const_mirp); 2025} 2026 2027void X86Mir2Lir::GenAddReduceVector(BasicBlock *bb, MIR *mir) { 2028 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); 2029 RegStorage rs_src1 = RegStorage::Solo128(mir->dalvikInsn.vB); 2030 RegLocation rl_dest = mir_graph_->GetDest(mir); 2031 RegStorage rs_tmp; 2032 2033 int vec_bytes = (mir->dalvikInsn.vC & 0xFFFF) / 8; 2034 int vec_unit_size = 0; 2035 int opcode = 0; 2036 int extr_opcode = 0; 2037 RegLocation rl_result; 2038 2039 switch (opsize) { 2040 case k32: 2041 extr_opcode = kX86PextrdRRI; 2042 opcode = kX86PhadddRR; 2043 vec_unit_size = 4; 2044 break; 2045 case kSignedByte: 2046 case kUnsignedByte: 2047 extr_opcode = kX86PextrbRRI; 2048 opcode = kX86PhaddwRR; 2049 vec_unit_size = 2; 2050 break; 2051 case kSignedHalf: 2052 case kUnsignedHalf: 2053 extr_opcode = kX86PextrwRRI; 2054 opcode = kX86PhaddwRR; 2055 vec_unit_size = 2; 2056 break; 2057 case kSingle: 2058 rl_result = EvalLoc(rl_dest, kFPReg, true); 2059 vec_unit_size = 4; 2060 for (int i = 0; i < 3; i++) { 2061 NewLIR2(kX86AddssRR, rl_result.reg.GetReg(), rs_src1.GetReg()); 2062 NewLIR3(kX86ShufpsRRI, rs_src1.GetReg(), rs_src1.GetReg(), 0x39); 2063 } 2064 NewLIR2(kX86AddssRR, rl_result.reg.GetReg(), rs_src1.GetReg()); 2065 StoreValue(rl_dest, rl_result); 2066 2067 // For single-precision floats, we are done here 2068 return; 2069 default: 2070 LOG(FATAL) << "Unsupported vector add reduce " << opsize; 2071 break; 2072 } 2073 2074 int elems = vec_bytes / vec_unit_size; 2075 2076 // Emulate horizontal add instruction by reducing 2 vectors with 8 values before adding them again 2077 // TODO is overflow handled correctly? 2078 if (opsize == kSignedByte || opsize == kUnsignedByte) { 2079 rs_tmp = Get128BitRegister(AllocTempWide()); 2080 2081 // tmp = xmm1 .>> 8. 2082 NewLIR2(kX86Mova128RR, rs_tmp.GetReg(), rs_src1.GetReg()); 2083 NewLIR2(kX86PsrlwRI, rs_tmp.GetReg(), 8); 2084 2085 // Zero extend low bits in xmm1. 2086 AndMaskVectorRegister(rs_src1, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF); 2087 } 2088 2089 while (elems > 1) { 2090 if (opsize == kSignedByte || opsize == kUnsignedByte) { 2091 NewLIR2(opcode, rs_tmp.GetReg(), rs_tmp.GetReg()); 2092 } 2093 NewLIR2(opcode, rs_src1.GetReg(), rs_src1.GetReg()); 2094 elems >>= 1; 2095 } 2096 2097 // Combine the results if we separated them. 2098 if (opsize == kSignedByte || opsize == kUnsignedByte) { 2099 NewLIR2(kX86PaddbRR, rs_src1.GetReg(), rs_tmp.GetReg()); 2100 } 2101 2102 // We need to extract to a GPR. 2103 RegStorage temp = AllocTemp(); 2104 NewLIR3(extr_opcode, temp.GetReg(), rs_src1.GetReg(), 0); 2105 2106 // Can we do this directly into memory? 2107 rl_result = UpdateLocTyped(rl_dest, kCoreReg); 2108 if (rl_result.location == kLocPhysReg) { 2109 // Ensure res is in a core reg 2110 rl_result = EvalLoc(rl_dest, kCoreReg, true); 2111 OpRegReg(kOpAdd, rl_result.reg, temp); 2112 StoreFinalValue(rl_dest, rl_result); 2113 } else { 2114 OpMemReg(kOpAdd, rl_result, temp.GetReg()); 2115 } 2116 2117 FreeTemp(temp); 2118} 2119 2120void X86Mir2Lir::GenReduceVector(BasicBlock *bb, MIR *mir) { 2121 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); 2122 RegLocation rl_dest = mir_graph_->GetDest(mir); 2123 RegStorage rs_src1 = RegStorage::Solo128(mir->dalvikInsn.vB); 2124 int extract_index = mir->dalvikInsn.arg[0]; 2125 int extr_opcode = 0; 2126 RegLocation rl_result; 2127 bool is_wide = false; 2128 2129 switch (opsize) { 2130 case k32: 2131 rl_result = UpdateLocTyped(rl_dest, kCoreReg); 2132 extr_opcode = (rl_result.location == kLocPhysReg) ? kX86PextrdMRI : kX86PextrdRRI; 2133 break; 2134 case kSignedHalf: 2135 case kUnsignedHalf: 2136 rl_result= UpdateLocTyped(rl_dest, kCoreReg); 2137 extr_opcode = (rl_result.location == kLocPhysReg) ? kX86PextrwMRI : kX86PextrwRRI; 2138 break; 2139 default: 2140 LOG(FATAL) << "Unsupported vector add reduce " << opsize; 2141 return; 2142 break; 2143 } 2144 2145 if (rl_result.location == kLocPhysReg) { 2146 NewLIR3(extr_opcode, rl_result.reg.GetReg(), rs_src1.GetReg(), extract_index); 2147 if (is_wide == true) { 2148 StoreFinalValue(rl_dest, rl_result); 2149 } else { 2150 StoreFinalValueWide(rl_dest, rl_result); 2151 } 2152 } else { 2153 int displacement = SRegOffset(rl_result.s_reg_low); 2154 LIR *l = NewLIR3(extr_opcode, rs_rX86_SP.GetReg(), displacement, rs_src1.GetReg()); 2155 AnnotateDalvikRegAccess(l, displacement >> 2, true /* is_load */, is_wide /* is_64bit */); 2156 AnnotateDalvikRegAccess(l, displacement >> 2, false /* is_load */, is_wide /* is_64bit */); 2157 } 2158} 2159 2160void X86Mir2Lir::GenSetVector(BasicBlock *bb, MIR *mir) { 2161 DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U); 2162 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); 2163 RegStorage rs_dest = RegStorage::Solo128(mir->dalvikInsn.vA); 2164 int op_low = 0, op_high = 0, imm = 0, op_mov = kX86MovdxrRR; 2165 RegisterClass reg_type = kCoreReg; 2166 2167 switch (opsize) { 2168 case k32: 2169 op_low = kX86PshufdRRI; 2170 break; 2171 case kSingle: 2172 op_low = kX86PshufdRRI; 2173 op_mov = kX86Mova128RR; 2174 reg_type = kFPReg; 2175 break; 2176 case k64: 2177 op_low = kX86PshufdRRI; 2178 imm = 0x44; 2179 break; 2180 case kDouble: 2181 op_low = kX86PshufdRRI; 2182 op_mov = kX86Mova128RR; 2183 reg_type = kFPReg; 2184 imm = 0x44; 2185 break; 2186 case kSignedByte: 2187 case kUnsignedByte: 2188 // Shuffle 8 bit value into 16 bit word. 2189 // We set val = val + (val << 8) below and use 16 bit shuffle. 2190 case kSignedHalf: 2191 case kUnsignedHalf: 2192 // Handles low quadword. 2193 op_low = kX86PshuflwRRI; 2194 // Handles upper quadword. 2195 op_high = kX86PshufdRRI; 2196 break; 2197 default: 2198 LOG(FATAL) << "Unsupported vector set " << opsize; 2199 break; 2200 } 2201 2202 RegLocation rl_src = mir_graph_->GetSrc(mir, 0); 2203 2204 // Load the value from the VR into the reg. 2205 if (rl_src.wide == 0) { 2206 rl_src = LoadValue(rl_src, reg_type); 2207 } else { 2208 rl_src = LoadValueWide(rl_src, reg_type); 2209 } 2210 2211 // If opsize is 8 bits wide then double value and use 16 bit shuffle instead. 2212 if (opsize == kSignedByte || opsize == kUnsignedByte) { 2213 RegStorage temp = AllocTemp(); 2214 // val = val + (val << 8). 2215 NewLIR2(kX86Mov32RR, temp.GetReg(), rl_src.reg.GetReg()); 2216 NewLIR2(kX86Sal32RI, temp.GetReg(), 8); 2217 NewLIR2(kX86Or32RR, rl_src.reg.GetReg(), temp.GetReg()); 2218 FreeTemp(temp); 2219 } 2220 2221 // Load the value into the XMM register. 2222 NewLIR2(op_mov, rs_dest.GetReg(), rl_src.reg.GetReg()); 2223 2224 // Now shuffle the value across the destination. 2225 NewLIR3(op_low, rs_dest.GetReg(), rs_dest.GetReg(), imm); 2226 2227 // And then repeat as needed. 2228 if (op_high != 0) { 2229 NewLIR3(op_high, rs_dest.GetReg(), rs_dest.GetReg(), imm); 2230 } 2231} 2232 2233LIR *X86Mir2Lir::ScanVectorLiteral(MIR *mir) { 2234 int *args = reinterpret_cast<int*>(mir->dalvikInsn.arg); 2235 for (LIR *p = const_vectors_; p != nullptr; p = p->next) { 2236 if (args[0] == p->operands[0] && args[1] == p->operands[1] && 2237 args[2] == p->operands[2] && args[3] == p->operands[3]) { 2238 return p; 2239 } 2240 } 2241 return nullptr; 2242} 2243 2244LIR *X86Mir2Lir::AddVectorLiteral(MIR *mir) { 2245 LIR* new_value = static_cast<LIR*>(arena_->Alloc(sizeof(LIR), kArenaAllocData)); 2246 int *args = reinterpret_cast<int*>(mir->dalvikInsn.arg); 2247 new_value->operands[0] = args[0]; 2248 new_value->operands[1] = args[1]; 2249 new_value->operands[2] = args[2]; 2250 new_value->operands[3] = args[3]; 2251 new_value->next = const_vectors_; 2252 if (const_vectors_ == nullptr) { 2253 estimated_native_code_size_ += 12; // Amount needed to align to 16 byte boundary. 2254 } 2255 estimated_native_code_size_ += 16; // Space for one vector. 2256 const_vectors_ = new_value; 2257 return new_value; 2258} 2259 2260// ------------ ABI support: mapping of args to physical registers ------------- 2261RegStorage X86Mir2Lir::InToRegStorageX86_64Mapper::GetNextReg(bool is_double_or_float, bool is_wide, 2262 bool is_ref) { 2263 const SpecialTargetRegister coreArgMappingToPhysicalReg[] = {kArg1, kArg2, kArg3, kArg4, kArg5}; 2264 const int coreArgMappingToPhysicalRegSize = sizeof(coreArgMappingToPhysicalReg) / 2265 sizeof(SpecialTargetRegister); 2266 const SpecialTargetRegister fpArgMappingToPhysicalReg[] = {kFArg0, kFArg1, kFArg2, kFArg3, 2267 kFArg4, kFArg5, kFArg6, kFArg7}; 2268 const int fpArgMappingToPhysicalRegSize = sizeof(fpArgMappingToPhysicalReg) / 2269 sizeof(SpecialTargetRegister); 2270 2271 if (is_double_or_float) { 2272 if (cur_fp_reg_ < fpArgMappingToPhysicalRegSize) { 2273 return ml_->TargetReg(fpArgMappingToPhysicalReg[cur_fp_reg_++], is_wide ? kWide : kNotWide); 2274 } 2275 } else { 2276 if (cur_core_reg_ < coreArgMappingToPhysicalRegSize) { 2277 return ml_->TargetReg(coreArgMappingToPhysicalReg[cur_core_reg_++], 2278 is_ref ? kRef : (is_wide ? kWide : kNotWide)); 2279 } 2280 } 2281 return RegStorage::InvalidReg(); 2282} 2283 2284RegStorage X86Mir2Lir::InToRegStorageMapping::Get(int in_position) { 2285 DCHECK(IsInitialized()); 2286 auto res = mapping_.find(in_position); 2287 return res != mapping_.end() ? res->second : RegStorage::InvalidReg(); 2288} 2289 2290void X86Mir2Lir::InToRegStorageMapping::Initialize(RegLocation* arg_locs, int count, 2291 InToRegStorageMapper* mapper) { 2292 DCHECK(mapper != nullptr); 2293 max_mapped_in_ = -1; 2294 is_there_stack_mapped_ = false; 2295 for (int in_position = 0; in_position < count; in_position++) { 2296 RegStorage reg = mapper->GetNextReg(arg_locs[in_position].fp, 2297 arg_locs[in_position].wide, arg_locs[in_position].ref); 2298 if (reg.Valid()) { 2299 mapping_[in_position] = reg; 2300 max_mapped_in_ = std::max(max_mapped_in_, in_position); 2301 if (arg_locs[in_position].wide) { 2302 // We covered 2 args, so skip the next one 2303 in_position++; 2304 } 2305 } else { 2306 is_there_stack_mapped_ = true; 2307 } 2308 } 2309 initialized_ = true; 2310} 2311 2312RegStorage X86Mir2Lir::GetArgMappingToPhysicalReg(int arg_num) { 2313 if (!cu_->target64) { 2314 return GetCoreArgMappingToPhysicalReg(arg_num); 2315 } 2316 2317 if (!in_to_reg_storage_mapping_.IsInitialized()) { 2318 int start_vreg = cu_->num_dalvik_registers - cu_->num_ins; 2319 RegLocation* arg_locs = &mir_graph_->reg_location_[start_vreg]; 2320 2321 InToRegStorageX86_64Mapper mapper(this); 2322 in_to_reg_storage_mapping_.Initialize(arg_locs, cu_->num_ins, &mapper); 2323 } 2324 return in_to_reg_storage_mapping_.Get(arg_num); 2325} 2326 2327RegStorage X86Mir2Lir::GetCoreArgMappingToPhysicalReg(int core_arg_num) { 2328 // For the 32-bit internal ABI, the first 3 arguments are passed in registers. 2329 // Not used for 64-bit, TODO: Move X86_32 to the same framework 2330 switch (core_arg_num) { 2331 case 0: 2332 return rs_rX86_ARG1; 2333 case 1: 2334 return rs_rX86_ARG2; 2335 case 2: 2336 return rs_rX86_ARG3; 2337 default: 2338 return RegStorage::InvalidReg(); 2339 } 2340} 2341 2342// ---------End of ABI support: mapping of args to physical registers ------------- 2343 2344/* 2345 * If there are any ins passed in registers that have not been promoted 2346 * to a callee-save register, flush them to the frame. Perform initial 2347 * assignment of promoted arguments. 2348 * 2349 * ArgLocs is an array of location records describing the incoming arguments 2350 * with one location record per word of argument. 2351 */ 2352void X86Mir2Lir::FlushIns(RegLocation* ArgLocs, RegLocation rl_method) { 2353 if (!cu_->target64) return Mir2Lir::FlushIns(ArgLocs, rl_method); 2354 /* 2355 * Dummy up a RegLocation for the incoming Method* 2356 * It will attempt to keep kArg0 live (or copy it to home location 2357 * if promoted). 2358 */ 2359 2360 RegLocation rl_src = rl_method; 2361 rl_src.location = kLocPhysReg; 2362 rl_src.reg = TargetReg(kArg0, kRef); 2363 rl_src.home = false; 2364 MarkLive(rl_src); 2365 StoreValue(rl_method, rl_src); 2366 // If Method* has been promoted, explicitly flush 2367 if (rl_method.location == kLocPhysReg) { 2368 StoreRefDisp(rs_rX86_SP, 0, As32BitReg(TargetReg(kArg0, kRef)), kNotVolatile); 2369 } 2370 2371 if (cu_->num_ins == 0) { 2372 return; 2373 } 2374 2375 int start_vreg = cu_->num_dalvik_registers - cu_->num_ins; 2376 /* 2377 * Copy incoming arguments to their proper home locations. 2378 * NOTE: an older version of dx had an issue in which 2379 * it would reuse static method argument registers. 2380 * This could result in the same Dalvik virtual register 2381 * being promoted to both core and fp regs. To account for this, 2382 * we only copy to the corresponding promoted physical register 2383 * if it matches the type of the SSA name for the incoming 2384 * argument. It is also possible that long and double arguments 2385 * end up half-promoted. In those cases, we must flush the promoted 2386 * half to memory as well. 2387 */ 2388 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); 2389 for (int i = 0; i < cu_->num_ins; i++) { 2390 // get reg corresponding to input 2391 RegStorage reg = GetArgMappingToPhysicalReg(i); 2392 2393 RegLocation* t_loc = &ArgLocs[i]; 2394 if (reg.Valid()) { 2395 // If arriving in register. 2396 2397 // We have already updated the arg location with promoted info 2398 // so we can be based on it. 2399 if (t_loc->location == kLocPhysReg) { 2400 // Just copy it. 2401 OpRegCopy(t_loc->reg, reg); 2402 } else { 2403 // Needs flush. 2404 if (t_loc->ref) { 2405 StoreRefDisp(rs_rX86_SP, SRegOffset(start_vreg + i), reg, kNotVolatile); 2406 } else { 2407 StoreBaseDisp(rs_rX86_SP, SRegOffset(start_vreg + i), reg, t_loc->wide ? k64 : k32, 2408 kNotVolatile); 2409 } 2410 } 2411 } else { 2412 // If arriving in frame & promoted. 2413 if (t_loc->location == kLocPhysReg) { 2414 if (t_loc->ref) { 2415 LoadRefDisp(rs_rX86_SP, SRegOffset(start_vreg + i), t_loc->reg, kNotVolatile); 2416 } else { 2417 LoadBaseDisp(rs_rX86_SP, SRegOffset(start_vreg + i), t_loc->reg, 2418 t_loc->wide ? k64 : k32, kNotVolatile); 2419 } 2420 } 2421 } 2422 if (t_loc->wide) { 2423 // Increment i to skip the next one. 2424 i++; 2425 } 2426 } 2427} 2428 2429/* 2430 * Load up to 5 arguments, the first three of which will be in 2431 * kArg1 .. kArg3. On entry kArg0 contains the current method pointer, 2432 * and as part of the load sequence, it must be replaced with 2433 * the target method pointer. Note, this may also be called 2434 * for "range" variants if the number of arguments is 5 or fewer. 2435 */ 2436int X86Mir2Lir::GenDalvikArgsNoRange(CallInfo* info, 2437 int call_state, LIR** pcrLabel, NextCallInsn next_call_insn, 2438 const MethodReference& target_method, 2439 uint32_t vtable_idx, uintptr_t direct_code, 2440 uintptr_t direct_method, InvokeType type, bool skip_this) { 2441 if (!cu_->target64) { 2442 return Mir2Lir::GenDalvikArgsNoRange(info, 2443 call_state, pcrLabel, next_call_insn, 2444 target_method, 2445 vtable_idx, direct_code, 2446 direct_method, type, skip_this); 2447 } 2448 return GenDalvikArgsRange(info, 2449 call_state, pcrLabel, next_call_insn, 2450 target_method, 2451 vtable_idx, direct_code, 2452 direct_method, type, skip_this); 2453} 2454 2455/* 2456 * May have 0+ arguments (also used for jumbo). Note that 2457 * source virtual registers may be in physical registers, so may 2458 * need to be flushed to home location before copying. This 2459 * applies to arg3 and above (see below). 2460 * 2461 * Two general strategies: 2462 * If < 20 arguments 2463 * Pass args 3-18 using vldm/vstm block copy 2464 * Pass arg0, arg1 & arg2 in kArg1-kArg3 2465 * If 20+ arguments 2466 * Pass args arg19+ using memcpy block copy 2467 * Pass arg0, arg1 & arg2 in kArg1-kArg3 2468 * 2469 */ 2470int X86Mir2Lir::GenDalvikArgsRange(CallInfo* info, int call_state, 2471 LIR** pcrLabel, NextCallInsn next_call_insn, 2472 const MethodReference& target_method, 2473 uint32_t vtable_idx, uintptr_t direct_code, uintptr_t direct_method, 2474 InvokeType type, bool skip_this) { 2475 if (!cu_->target64) { 2476 return Mir2Lir::GenDalvikArgsRange(info, call_state, 2477 pcrLabel, next_call_insn, 2478 target_method, 2479 vtable_idx, direct_code, direct_method, 2480 type, skip_this); 2481 } 2482 2483 /* If no arguments, just return */ 2484 if (info->num_arg_words == 0) 2485 return call_state; 2486 2487 const int start_index = skip_this ? 1 : 0; 2488 2489 InToRegStorageX86_64Mapper mapper(this); 2490 InToRegStorageMapping in_to_reg_storage_mapping; 2491 in_to_reg_storage_mapping.Initialize(info->args, info->num_arg_words, &mapper); 2492 const int last_mapped_in = in_to_reg_storage_mapping.GetMaxMappedIn(); 2493 const int size_of_the_last_mapped = last_mapped_in == -1 ? 1 : 2494 info->args[last_mapped_in].wide ? 2 : 1; 2495 int regs_left_to_pass_via_stack = info->num_arg_words - (last_mapped_in + size_of_the_last_mapped); 2496 2497 // Fisrt of all, check whether it make sense to use bulk copying 2498 // Optimization is aplicable only for range case 2499 // TODO: make a constant instead of 2 2500 if (info->is_range && regs_left_to_pass_via_stack >= 2) { 2501 // Scan the rest of the args - if in phys_reg flush to memory 2502 for (int next_arg = last_mapped_in + size_of_the_last_mapped; next_arg < info->num_arg_words;) { 2503 RegLocation loc = info->args[next_arg]; 2504 if (loc.wide) { 2505 loc = UpdateLocWide(loc); 2506 if (loc.location == kLocPhysReg) { 2507 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); 2508 StoreBaseDisp(rs_rX86_SP, SRegOffset(loc.s_reg_low), loc.reg, k64, kNotVolatile); 2509 } 2510 next_arg += 2; 2511 } else { 2512 loc = UpdateLoc(loc); 2513 if (loc.location == kLocPhysReg) { 2514 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); 2515 StoreBaseDisp(rs_rX86_SP, SRegOffset(loc.s_reg_low), loc.reg, k32, kNotVolatile); 2516 } 2517 next_arg++; 2518 } 2519 } 2520 2521 // Logic below assumes that Method pointer is at offset zero from SP. 2522 DCHECK_EQ(VRegOffset(static_cast<int>(kVRegMethodPtrBaseReg)), 0); 2523 2524 // The rest can be copied together 2525 int start_offset = SRegOffset(info->args[last_mapped_in + size_of_the_last_mapped].s_reg_low); 2526 int outs_offset = StackVisitor::GetOutVROffset(last_mapped_in + size_of_the_last_mapped, 2527 cu_->instruction_set); 2528 2529 int current_src_offset = start_offset; 2530 int current_dest_offset = outs_offset; 2531 2532 // Only davik regs are accessed in this loop; no next_call_insn() calls. 2533 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); 2534 while (regs_left_to_pass_via_stack > 0) { 2535 // This is based on the knowledge that the stack itself is 16-byte aligned. 2536 bool src_is_16b_aligned = (current_src_offset & 0xF) == 0; 2537 bool dest_is_16b_aligned = (current_dest_offset & 0xF) == 0; 2538 size_t bytes_to_move; 2539 2540 /* 2541 * The amount to move defaults to 32-bit. If there are 4 registers left to move, then do a 2542 * a 128-bit move because we won't get the chance to try to aligned. If there are more than 2543 * 4 registers left to move, consider doing a 128-bit only if either src or dest are aligned. 2544 * We do this because we could potentially do a smaller move to align. 2545 */ 2546 if (regs_left_to_pass_via_stack == 4 || 2547 (regs_left_to_pass_via_stack > 4 && (src_is_16b_aligned || dest_is_16b_aligned))) { 2548 // Moving 128-bits via xmm register. 2549 bytes_to_move = sizeof(uint32_t) * 4; 2550 2551 // Allocate a free xmm temp. Since we are working through the calling sequence, 2552 // we expect to have an xmm temporary available. AllocTempDouble will abort if 2553 // there are no free registers. 2554 RegStorage temp = AllocTempDouble(); 2555 2556 LIR* ld1 = nullptr; 2557 LIR* ld2 = nullptr; 2558 LIR* st1 = nullptr; 2559 LIR* st2 = nullptr; 2560 2561 /* 2562 * The logic is similar for both loads and stores. If we have 16-byte alignment, 2563 * do an aligned move. If we have 8-byte alignment, then do the move in two 2564 * parts. This approach prevents possible cache line splits. Finally, fall back 2565 * to doing an unaligned move. In most cases we likely won't split the cache 2566 * line but we cannot prove it and thus take a conservative approach. 2567 */ 2568 bool src_is_8b_aligned = (current_src_offset & 0x7) == 0; 2569 bool dest_is_8b_aligned = (current_dest_offset & 0x7) == 0; 2570 2571 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); 2572 if (src_is_16b_aligned) { 2573 ld1 = OpMovRegMem(temp, rs_rX86_SP, current_src_offset, kMovA128FP); 2574 } else if (src_is_8b_aligned) { 2575 ld1 = OpMovRegMem(temp, rs_rX86_SP, current_src_offset, kMovLo128FP); 2576 ld2 = OpMovRegMem(temp, rs_rX86_SP, current_src_offset + (bytes_to_move >> 1), 2577 kMovHi128FP); 2578 } else { 2579 ld1 = OpMovRegMem(temp, rs_rX86_SP, current_src_offset, kMovU128FP); 2580 } 2581 2582 if (dest_is_16b_aligned) { 2583 st1 = OpMovMemReg(rs_rX86_SP, current_dest_offset, temp, kMovA128FP); 2584 } else if (dest_is_8b_aligned) { 2585 st1 = OpMovMemReg(rs_rX86_SP, current_dest_offset, temp, kMovLo128FP); 2586 st2 = OpMovMemReg(rs_rX86_SP, current_dest_offset + (bytes_to_move >> 1), 2587 temp, kMovHi128FP); 2588 } else { 2589 st1 = OpMovMemReg(rs_rX86_SP, current_dest_offset, temp, kMovU128FP); 2590 } 2591 2592 // TODO If we could keep track of aliasing information for memory accesses that are wider 2593 // than 64-bit, we wouldn't need to set up a barrier. 2594 if (ld1 != nullptr) { 2595 if (ld2 != nullptr) { 2596 // For 64-bit load we can actually set up the aliasing information. 2597 AnnotateDalvikRegAccess(ld1, current_src_offset >> 2, true, true); 2598 AnnotateDalvikRegAccess(ld2, (current_src_offset + (bytes_to_move >> 1)) >> 2, true, true); 2599 } else { 2600 // Set barrier for 128-bit load. 2601 ld1->u.m.def_mask = &kEncodeAll; 2602 } 2603 } 2604 if (st1 != nullptr) { 2605 if (st2 != nullptr) { 2606 // For 64-bit store we can actually set up the aliasing information. 2607 AnnotateDalvikRegAccess(st1, current_dest_offset >> 2, false, true); 2608 AnnotateDalvikRegAccess(st2, (current_dest_offset + (bytes_to_move >> 1)) >> 2, false, true); 2609 } else { 2610 // Set barrier for 128-bit store. 2611 st1->u.m.def_mask = &kEncodeAll; 2612 } 2613 } 2614 2615 // Free the temporary used for the data movement. 2616 FreeTemp(temp); 2617 } else { 2618 // Moving 32-bits via general purpose register. 2619 bytes_to_move = sizeof(uint32_t); 2620 2621 // Instead of allocating a new temp, simply reuse one of the registers being used 2622 // for argument passing. 2623 RegStorage temp = TargetReg(kArg3, kNotWide); 2624 2625 // Now load the argument VR and store to the outs. 2626 Load32Disp(rs_rX86_SP, current_src_offset, temp); 2627 Store32Disp(rs_rX86_SP, current_dest_offset, temp); 2628 } 2629 2630 current_src_offset += bytes_to_move; 2631 current_dest_offset += bytes_to_move; 2632 regs_left_to_pass_via_stack -= (bytes_to_move >> 2); 2633 } 2634 DCHECK_EQ(regs_left_to_pass_via_stack, 0); 2635 } 2636 2637 // Now handle rest not registers if they are 2638 if (in_to_reg_storage_mapping.IsThereStackMapped()) { 2639 RegStorage regSingle = TargetReg(kArg2, kNotWide); 2640 RegStorage regWide = TargetReg(kArg3, kWide); 2641 for (int i = start_index; 2642 i < last_mapped_in + size_of_the_last_mapped + regs_left_to_pass_via_stack; i++) { 2643 RegLocation rl_arg = info->args[i]; 2644 rl_arg = UpdateRawLoc(rl_arg); 2645 RegStorage reg = in_to_reg_storage_mapping.Get(i); 2646 if (!reg.Valid()) { 2647 int out_offset = StackVisitor::GetOutVROffset(i, cu_->instruction_set); 2648 2649 { 2650 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); 2651 if (rl_arg.wide) { 2652 if (rl_arg.location == kLocPhysReg) { 2653 StoreBaseDisp(rs_rX86_SP, out_offset, rl_arg.reg, k64, kNotVolatile); 2654 } else { 2655 LoadValueDirectWideFixed(rl_arg, regWide); 2656 StoreBaseDisp(rs_rX86_SP, out_offset, regWide, k64, kNotVolatile); 2657 } 2658 } else { 2659 if (rl_arg.location == kLocPhysReg) { 2660 StoreBaseDisp(rs_rX86_SP, out_offset, rl_arg.reg, k32, kNotVolatile); 2661 } else { 2662 LoadValueDirectFixed(rl_arg, regSingle); 2663 StoreBaseDisp(rs_rX86_SP, out_offset, regSingle, k32, kNotVolatile); 2664 } 2665 } 2666 } 2667 call_state = next_call_insn(cu_, info, call_state, target_method, 2668 vtable_idx, direct_code, direct_method, type); 2669 } 2670 if (rl_arg.wide) { 2671 i++; 2672 } 2673 } 2674 } 2675 2676 // Finish with mapped registers 2677 for (int i = start_index; i <= last_mapped_in; i++) { 2678 RegLocation rl_arg = info->args[i]; 2679 rl_arg = UpdateRawLoc(rl_arg); 2680 RegStorage reg = in_to_reg_storage_mapping.Get(i); 2681 if (reg.Valid()) { 2682 if (rl_arg.wide) { 2683 LoadValueDirectWideFixed(rl_arg, reg); 2684 } else { 2685 LoadValueDirectFixed(rl_arg, reg); 2686 } 2687 call_state = next_call_insn(cu_, info, call_state, target_method, vtable_idx, 2688 direct_code, direct_method, type); 2689 } 2690 if (rl_arg.wide) { 2691 i++; 2692 } 2693 } 2694 2695 call_state = next_call_insn(cu_, info, call_state, target_method, vtable_idx, 2696 direct_code, direct_method, type); 2697 if (pcrLabel) { 2698 if (!cu_->compiler_driver->GetCompilerOptions().GetImplicitNullChecks()) { 2699 *pcrLabel = GenExplicitNullCheck(TargetReg(kArg1, kRef), info->opt_flags); 2700 } else { 2701 *pcrLabel = nullptr; 2702 // In lieu of generating a check for kArg1 being null, we need to 2703 // perform a load when doing implicit checks. 2704 RegStorage tmp = AllocTemp(); 2705 Load32Disp(TargetReg(kArg1, kRef), 0, tmp); 2706 MarkPossibleNullPointerException(info->opt_flags); 2707 FreeTemp(tmp); 2708 } 2709 } 2710 return call_state; 2711} 2712 2713bool X86Mir2Lir::GenInlinedCharAt(CallInfo* info) { 2714 // Location of reference to data array 2715 int value_offset = mirror::String::ValueOffset().Int32Value(); 2716 // Location of count 2717 int count_offset = mirror::String::CountOffset().Int32Value(); 2718 // Starting offset within data array 2719 int offset_offset = mirror::String::OffsetOffset().Int32Value(); 2720 // Start of char data with array_ 2721 int data_offset = mirror::Array::DataOffset(sizeof(uint16_t)).Int32Value(); 2722 2723 RegLocation rl_obj = info->args[0]; 2724 RegLocation rl_idx = info->args[1]; 2725 rl_obj = LoadValue(rl_obj, kRefReg); 2726 // X86 wants to avoid putting a constant index into a register. 2727 if (!rl_idx.is_const) { 2728 rl_idx = LoadValue(rl_idx, kCoreReg); 2729 } 2730 RegStorage reg_max; 2731 GenNullCheck(rl_obj.reg, info->opt_flags); 2732 bool range_check = (!(info->opt_flags & MIR_IGNORE_RANGE_CHECK)); 2733 LIR* range_check_branch = nullptr; 2734 RegStorage reg_off; 2735 RegStorage reg_ptr; 2736 if (range_check) { 2737 // On x86, we can compare to memory directly 2738 // Set up a launch pad to allow retry in case of bounds violation */ 2739 if (rl_idx.is_const) { 2740 LIR* comparison; 2741 range_check_branch = OpCmpMemImmBranch( 2742 kCondUlt, RegStorage::InvalidReg(), rl_obj.reg, count_offset, 2743 mir_graph_->ConstantValue(rl_idx.orig_sreg), nullptr, &comparison); 2744 MarkPossibleNullPointerExceptionAfter(0, comparison); 2745 } else { 2746 OpRegMem(kOpCmp, rl_idx.reg, rl_obj.reg, count_offset); 2747 MarkPossibleNullPointerException(0); 2748 range_check_branch = OpCondBranch(kCondUge, nullptr); 2749 } 2750 } 2751 reg_off = AllocTemp(); 2752 reg_ptr = AllocTempRef(); 2753 Load32Disp(rl_obj.reg, offset_offset, reg_off); 2754 LoadRefDisp(rl_obj.reg, value_offset, reg_ptr, kNotVolatile); 2755 if (rl_idx.is_const) { 2756 OpRegImm(kOpAdd, reg_off, mir_graph_->ConstantValue(rl_idx.orig_sreg)); 2757 } else { 2758 OpRegReg(kOpAdd, reg_off, rl_idx.reg); 2759 } 2760 FreeTemp(rl_obj.reg); 2761 if (rl_idx.location == kLocPhysReg) { 2762 FreeTemp(rl_idx.reg); 2763 } 2764 RegLocation rl_dest = InlineTarget(info); 2765 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 2766 LoadBaseIndexedDisp(reg_ptr, reg_off, 1, data_offset, rl_result.reg, kUnsignedHalf); 2767 FreeTemp(reg_off); 2768 FreeTemp(reg_ptr); 2769 StoreValue(rl_dest, rl_result); 2770 if (range_check) { 2771 DCHECK(range_check_branch != nullptr); 2772 info->opt_flags |= MIR_IGNORE_NULL_CHECK; // Record that we've already null checked. 2773 AddIntrinsicSlowPath(info, range_check_branch); 2774 } 2775 return true; 2776} 2777 2778} // namespace art 2779