target_x86.cc revision a1758d83e298c9ee31848bcae07c2a35f6efd618
1/* 2 * Copyright (C) 2012 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#include <string> 18#include <inttypes.h> 19 20#include "codegen_x86.h" 21#include "dex/compiler_internals.h" 22#include "dex/quick/mir_to_lir-inl.h" 23#include "mirror/array.h" 24#include "mirror/string.h" 25#include "x86_lir.h" 26 27namespace art { 28 29// FIXME: restore "static" when usage uncovered 30/*static*/ int core_regs[] = { 31 rAX, rCX, rDX, rBX, rX86_SP, rBP, rSI, rDI 32#ifdef TARGET_REX_SUPPORT 33 r8, r9, r10, r11, r12, r13, r14, 15 34#endif 35}; 36/*static*/ int ReservedRegs[] = {rX86_SP}; 37/*static*/ int core_temps[] = {rAX, rCX, rDX, rBX}; 38/*static*/ int FpRegs[] = { 39 fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7, 40#ifdef TARGET_REX_SUPPORT 41 fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15 42#endif 43}; 44/*static*/ int fp_temps[] = { 45 fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7, 46#ifdef TARGET_REX_SUPPORT 47 fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15 48#endif 49}; 50 51RegLocation X86Mir2Lir::LocCReturn() { 52 return x86_loc_c_return; 53} 54 55RegLocation X86Mir2Lir::LocCReturnWide() { 56 return x86_loc_c_return_wide; 57} 58 59RegLocation X86Mir2Lir::LocCReturnFloat() { 60 return x86_loc_c_return_float; 61} 62 63RegLocation X86Mir2Lir::LocCReturnDouble() { 64 return x86_loc_c_return_double; 65} 66 67// Return a target-dependent special register. 68RegStorage X86Mir2Lir::TargetReg(SpecialTargetRegister reg) { 69 int res_reg = RegStorage::kInvalidRegVal; 70 switch (reg) { 71 case kSelf: res_reg = rX86_SELF; break; 72 case kSuspend: res_reg = rX86_SUSPEND; break; 73 case kLr: res_reg = rX86_LR; break; 74 case kPc: res_reg = rX86_PC; break; 75 case kSp: res_reg = rX86_SP; break; 76 case kArg0: res_reg = rX86_ARG0; break; 77 case kArg1: res_reg = rX86_ARG1; break; 78 case kArg2: res_reg = rX86_ARG2; break; 79 case kArg3: res_reg = rX86_ARG3; break; 80 case kFArg0: res_reg = rX86_FARG0; break; 81 case kFArg1: res_reg = rX86_FARG1; break; 82 case kFArg2: res_reg = rX86_FARG2; break; 83 case kFArg3: res_reg = rX86_FARG3; break; 84 case kRet0: res_reg = rX86_RET0; break; 85 case kRet1: res_reg = rX86_RET1; break; 86 case kInvokeTgt: res_reg = rX86_INVOKE_TGT; break; 87 case kHiddenArg: res_reg = rAX; break; 88 case kHiddenFpArg: res_reg = fr0; break; 89 case kCount: res_reg = rX86_COUNT; break; 90 } 91 return RegStorage::Solo32(res_reg); 92} 93 94RegStorage X86Mir2Lir::GetArgMappingToPhysicalReg(int arg_num) { 95 // For the 32-bit internal ABI, the first 3 arguments are passed in registers. 96 // TODO: This is not 64-bit compliant and depends on new internal ABI. 97 switch (arg_num) { 98 case 0: 99 return rs_rX86_ARG1; 100 case 1: 101 return rs_rX86_ARG2; 102 case 2: 103 return rs_rX86_ARG3; 104 default: 105 return RegStorage::InvalidReg(); 106 } 107} 108 109// Create a double from a pair of singles. 110int X86Mir2Lir::S2d(int low_reg, int high_reg) { 111 return X86_S2D(low_reg, high_reg); 112} 113 114// Return mask to strip off fp reg flags and bias. 115uint32_t X86Mir2Lir::FpRegMask() { 116 return X86_FP_REG_MASK; 117} 118 119// True if both regs single, both core or both double. 120bool X86Mir2Lir::SameRegType(int reg1, int reg2) { 121 return (X86_REGTYPE(reg1) == X86_REGTYPE(reg2)); 122} 123 124/* 125 * Decode the register id. 126 */ 127uint64_t X86Mir2Lir::GetRegMaskCommon(int reg) { 128 uint64_t seed; 129 int shift; 130 int reg_id; 131 132 reg_id = reg & 0xf; 133 /* Double registers in x86 are just a single FP register */ 134 seed = 1; 135 /* FP register starts at bit position 16 */ 136 shift = X86_FPREG(reg) ? kX86FPReg0 : 0; 137 /* Expand the double register id into single offset */ 138 shift += reg_id; 139 return (seed << shift); 140} 141 142uint64_t X86Mir2Lir::GetPCUseDefEncoding() { 143 /* 144 * FIXME: might make sense to use a virtual resource encoding bit for pc. Might be 145 * able to clean up some of the x86/Arm_Mips differences 146 */ 147 LOG(FATAL) << "Unexpected call to GetPCUseDefEncoding for x86"; 148 return 0ULL; 149} 150 151void X86Mir2Lir::SetupTargetResourceMasks(LIR* lir, uint64_t flags) { 152 DCHECK(cu_->instruction_set == kX86 || cu_->instruction_set == kX86_64); 153 DCHECK(!lir->flags.use_def_invalid); 154 155 // X86-specific resource map setup here. 156 if (flags & REG_USE_SP) { 157 lir->u.m.use_mask |= ENCODE_X86_REG_SP; 158 } 159 160 if (flags & REG_DEF_SP) { 161 lir->u.m.def_mask |= ENCODE_X86_REG_SP; 162 } 163 164 if (flags & REG_DEFA) { 165 SetupRegMask(&lir->u.m.def_mask, rAX); 166 } 167 168 if (flags & REG_DEFD) { 169 SetupRegMask(&lir->u.m.def_mask, rDX); 170 } 171 if (flags & REG_USEA) { 172 SetupRegMask(&lir->u.m.use_mask, rAX); 173 } 174 175 if (flags & REG_USEC) { 176 SetupRegMask(&lir->u.m.use_mask, rCX); 177 } 178 179 if (flags & REG_USED) { 180 SetupRegMask(&lir->u.m.use_mask, rDX); 181 } 182 183 if (flags & REG_USEB) { 184 SetupRegMask(&lir->u.m.use_mask, rBX); 185 } 186 187 // Fixup hard to describe instruction: Uses rAX, rCX, rDI; sets rDI. 188 if (lir->opcode == kX86RepneScasw) { 189 SetupRegMask(&lir->u.m.use_mask, rAX); 190 SetupRegMask(&lir->u.m.use_mask, rCX); 191 SetupRegMask(&lir->u.m.use_mask, rDI); 192 SetupRegMask(&lir->u.m.def_mask, rDI); 193 } 194 195 if (flags & USE_FP_STACK) { 196 lir->u.m.use_mask |= ENCODE_X86_FP_STACK; 197 lir->u.m.def_mask |= ENCODE_X86_FP_STACK; 198 } 199} 200 201/* For dumping instructions */ 202static const char* x86RegName[] = { 203 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", 204 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" 205}; 206 207static const char* x86CondName[] = { 208 "O", 209 "NO", 210 "B/NAE/C", 211 "NB/AE/NC", 212 "Z/EQ", 213 "NZ/NE", 214 "BE/NA", 215 "NBE/A", 216 "S", 217 "NS", 218 "P/PE", 219 "NP/PO", 220 "L/NGE", 221 "NL/GE", 222 "LE/NG", 223 "NLE/G" 224}; 225 226/* 227 * Interpret a format string and build a string no longer than size 228 * See format key in Assemble.cc. 229 */ 230std::string X86Mir2Lir::BuildInsnString(const char *fmt, LIR *lir, unsigned char* base_addr) { 231 std::string buf; 232 size_t i = 0; 233 size_t fmt_len = strlen(fmt); 234 while (i < fmt_len) { 235 if (fmt[i] != '!') { 236 buf += fmt[i]; 237 i++; 238 } else { 239 i++; 240 DCHECK_LT(i, fmt_len); 241 char operand_number_ch = fmt[i]; 242 i++; 243 if (operand_number_ch == '!') { 244 buf += "!"; 245 } else { 246 int operand_number = operand_number_ch - '0'; 247 DCHECK_LT(operand_number, 6); // Expect upto 6 LIR operands. 248 DCHECK_LT(i, fmt_len); 249 int operand = lir->operands[operand_number]; 250 switch (fmt[i]) { 251 case 'c': 252 DCHECK_LT(static_cast<size_t>(operand), sizeof(x86CondName)); 253 buf += x86CondName[operand]; 254 break; 255 case 'd': 256 buf += StringPrintf("%d", operand); 257 break; 258 case 'p': { 259 EmbeddedData *tab_rec = reinterpret_cast<EmbeddedData*>(UnwrapPointer(operand)); 260 buf += StringPrintf("0x%08x", tab_rec->offset); 261 break; 262 } 263 case 'r': 264 if (X86_FPREG(operand) || X86_DOUBLEREG(operand)) { 265 int fp_reg = operand & X86_FP_REG_MASK; 266 buf += StringPrintf("xmm%d", fp_reg); 267 } else { 268 DCHECK_LT(static_cast<size_t>(operand), sizeof(x86RegName)); 269 buf += x86RegName[operand]; 270 } 271 break; 272 case 't': 273 buf += StringPrintf("0x%08" PRIxPTR " (L%p)", 274 reinterpret_cast<uintptr_t>(base_addr) + lir->offset + operand, 275 lir->target); 276 break; 277 default: 278 buf += StringPrintf("DecodeError '%c'", fmt[i]); 279 break; 280 } 281 i++; 282 } 283 } 284 } 285 return buf; 286} 287 288void X86Mir2Lir::DumpResourceMask(LIR *x86LIR, uint64_t mask, const char *prefix) { 289 char buf[256]; 290 buf[0] = 0; 291 292 if (mask == ENCODE_ALL) { 293 strcpy(buf, "all"); 294 } else { 295 char num[8]; 296 int i; 297 298 for (i = 0; i < kX86RegEnd; i++) { 299 if (mask & (1ULL << i)) { 300 snprintf(num, arraysize(num), "%d ", i); 301 strcat(buf, num); 302 } 303 } 304 305 if (mask & ENCODE_CCODE) { 306 strcat(buf, "cc "); 307 } 308 /* Memory bits */ 309 if (x86LIR && (mask & ENCODE_DALVIK_REG)) { 310 snprintf(buf + strlen(buf), arraysize(buf) - strlen(buf), "dr%d%s", 311 DECODE_ALIAS_INFO_REG(x86LIR->flags.alias_info), 312 (DECODE_ALIAS_INFO_WIDE(x86LIR->flags.alias_info)) ? "(+1)" : ""); 313 } 314 if (mask & ENCODE_LITERAL) { 315 strcat(buf, "lit "); 316 } 317 318 if (mask & ENCODE_HEAP_REF) { 319 strcat(buf, "heap "); 320 } 321 if (mask & ENCODE_MUST_NOT_ALIAS) { 322 strcat(buf, "noalias "); 323 } 324 } 325 if (buf[0]) { 326 LOG(INFO) << prefix << ": " << buf; 327 } 328} 329 330void X86Mir2Lir::AdjustSpillMask() { 331 // Adjustment for LR spilling, x86 has no LR so nothing to do here 332 core_spill_mask_ |= (1 << rRET); 333 num_core_spills_++; 334} 335 336/* 337 * Mark a callee-save fp register as promoted. Note that 338 * vpush/vpop uses contiguous register lists so we must 339 * include any holes in the mask. Associate holes with 340 * Dalvik register INVALID_VREG (0xFFFFU). 341 */ 342void X86Mir2Lir::MarkPreservedSingle(int v_reg, int reg) { 343 UNIMPLEMENTED(WARNING) << "MarkPreservedSingle"; 344#if 0 345 LOG(FATAL) << "No support yet for promoted FP regs"; 346#endif 347} 348 349void X86Mir2Lir::FlushRegWide(RegStorage reg) { 350 RegisterInfo* info1 = GetRegInfo(reg.GetLowReg()); 351 RegisterInfo* info2 = GetRegInfo(reg.GetHighReg()); 352 DCHECK(info1 && info2 && info1->pair && info2->pair && 353 (info1->partner == info2->reg) && 354 (info2->partner == info1->reg)); 355 if ((info1->live && info1->dirty) || (info2->live && info2->dirty)) { 356 if (!(info1->is_temp && info2->is_temp)) { 357 /* Should not happen. If it does, there's a problem in eval_loc */ 358 LOG(FATAL) << "Long half-temp, half-promoted"; 359 } 360 361 info1->dirty = false; 362 info2->dirty = false; 363 if (mir_graph_->SRegToVReg(info2->s_reg) < mir_graph_->SRegToVReg(info1->s_reg)) 364 info1 = info2; 365 int v_reg = mir_graph_->SRegToVReg(info1->s_reg); 366 StoreBaseDispWide(rs_rX86_SP, VRegOffset(v_reg), 367 RegStorage(RegStorage::k64BitPair, info1->reg, info1->partner)); 368 } 369} 370 371void X86Mir2Lir::FlushReg(RegStorage reg) { 372 DCHECK(!reg.IsPair()); 373 RegisterInfo* info = GetRegInfo(reg.GetReg()); 374 if (info->live && info->dirty) { 375 info->dirty = false; 376 int v_reg = mir_graph_->SRegToVReg(info->s_reg); 377 StoreBaseDisp(rs_rX86_SP, VRegOffset(v_reg), reg, kWord); 378 } 379} 380 381/* Give access to the target-dependent FP register encoding to common code */ 382bool X86Mir2Lir::IsFpReg(int reg) { 383 return X86_FPREG(reg); 384} 385 386bool X86Mir2Lir::IsFpReg(RegStorage reg) { 387 return IsFpReg(reg.IsPair() ? reg.GetLowReg() : reg.GetReg()); 388} 389 390/* Clobber all regs that might be used by an external C call */ 391void X86Mir2Lir::ClobberCallerSave() { 392 Clobber(rAX); 393 Clobber(rCX); 394 Clobber(rDX); 395 Clobber(rBX); 396} 397 398RegLocation X86Mir2Lir::GetReturnWideAlt() { 399 RegLocation res = LocCReturnWide(); 400 CHECK(res.reg.GetLowReg() == rAX); 401 CHECK(res.reg.GetHighReg() == rDX); 402 Clobber(rAX); 403 Clobber(rDX); 404 MarkInUse(rAX); 405 MarkInUse(rDX); 406 MarkPair(res.reg.GetLowReg(), res.reg.GetHighReg()); 407 return res; 408} 409 410RegLocation X86Mir2Lir::GetReturnAlt() { 411 RegLocation res = LocCReturn(); 412 res.reg.SetReg(rDX); 413 Clobber(rDX); 414 MarkInUse(rDX); 415 return res; 416} 417 418/* To be used when explicitly managing register use */ 419void X86Mir2Lir::LockCallTemps() { 420 LockTemp(rX86_ARG0); 421 LockTemp(rX86_ARG1); 422 LockTemp(rX86_ARG2); 423 LockTemp(rX86_ARG3); 424} 425 426/* To be used when explicitly managing register use */ 427void X86Mir2Lir::FreeCallTemps() { 428 FreeTemp(rX86_ARG0); 429 FreeTemp(rX86_ARG1); 430 FreeTemp(rX86_ARG2); 431 FreeTemp(rX86_ARG3); 432} 433 434bool X86Mir2Lir::ProvidesFullMemoryBarrier(X86OpCode opcode) { 435 switch (opcode) { 436 case kX86LockCmpxchgMR: 437 case kX86LockCmpxchgAR: 438 case kX86LockCmpxchg8bM: 439 case kX86LockCmpxchg8bA: 440 case kX86XchgMR: 441 case kX86Mfence: 442 // Atomic memory instructions provide full barrier. 443 return true; 444 default: 445 break; 446 } 447 448 // Conservative if cannot prove it provides full barrier. 449 return false; 450} 451 452void X86Mir2Lir::GenMemBarrier(MemBarrierKind barrier_kind) { 453#if ANDROID_SMP != 0 454 // Start off with using the last LIR as the barrier. If it is not enough, then we will update it. 455 LIR* mem_barrier = last_lir_insn_; 456 457 /* 458 * According to the JSR-133 Cookbook, for x86 only StoreLoad barriers need memory fence. All other barriers 459 * (LoadLoad, LoadStore, StoreStore) are nops due to the x86 memory model. For those cases, all we need 460 * to ensure is that there is a scheduling barrier in place. 461 */ 462 if (barrier_kind == kStoreLoad) { 463 // If no LIR exists already that can be used a barrier, then generate an mfence. 464 if (mem_barrier == nullptr) { 465 mem_barrier = NewLIR0(kX86Mfence); 466 } 467 468 // If last instruction does not provide full barrier, then insert an mfence. 469 if (ProvidesFullMemoryBarrier(static_cast<X86OpCode>(mem_barrier->opcode)) == false) { 470 mem_barrier = NewLIR0(kX86Mfence); 471 } 472 } 473 474 // Now ensure that a scheduling barrier is in place. 475 if (mem_barrier == nullptr) { 476 GenBarrier(); 477 } else { 478 // Mark as a scheduling barrier. 479 DCHECK(!mem_barrier->flags.use_def_invalid); 480 mem_barrier->u.m.def_mask = ENCODE_ALL; 481 } 482#endif 483} 484 485// Alloc a pair of core registers, or a double. 486RegStorage X86Mir2Lir::AllocTypedTempWide(bool fp_hint, int reg_class) { 487 if (((reg_class == kAnyReg) && fp_hint) || (reg_class == kFPReg)) { 488 return AllocTempDouble(); 489 } 490 RegStorage low_reg = AllocTemp(); 491 RegStorage high_reg = AllocTemp(); 492 return RegStorage::MakeRegPair(low_reg, high_reg); 493} 494 495RegStorage X86Mir2Lir::AllocTypedTemp(bool fp_hint, int reg_class) { 496 if (((reg_class == kAnyReg) && fp_hint) || (reg_class == kFPReg)) { 497 return AllocTempFloat(); 498 } 499 return AllocTemp(); 500} 501 502void X86Mir2Lir::CompilerInitializeRegAlloc() { 503 int num_regs = sizeof(core_regs)/sizeof(*core_regs); 504 int num_reserved = sizeof(ReservedRegs)/sizeof(*ReservedRegs); 505 int num_temps = sizeof(core_temps)/sizeof(*core_temps); 506 int num_fp_regs = sizeof(FpRegs)/sizeof(*FpRegs); 507 int num_fp_temps = sizeof(fp_temps)/sizeof(*fp_temps); 508 reg_pool_ = static_cast<RegisterPool*>(arena_->Alloc(sizeof(*reg_pool_), 509 kArenaAllocRegAlloc)); 510 reg_pool_->num_core_regs = num_regs; 511 reg_pool_->core_regs = 512 static_cast<RegisterInfo*>(arena_->Alloc(num_regs * sizeof(*reg_pool_->core_regs), 513 kArenaAllocRegAlloc)); 514 reg_pool_->num_fp_regs = num_fp_regs; 515 reg_pool_->FPRegs = 516 static_cast<RegisterInfo *>(arena_->Alloc(num_fp_regs * sizeof(*reg_pool_->FPRegs), 517 kArenaAllocRegAlloc)); 518 CompilerInitPool(reg_pool_->core_regs, core_regs, reg_pool_->num_core_regs); 519 CompilerInitPool(reg_pool_->FPRegs, FpRegs, reg_pool_->num_fp_regs); 520 // Keep special registers from being allocated 521 for (int i = 0; i < num_reserved; i++) { 522 MarkInUse(ReservedRegs[i]); 523 } 524 // Mark temp regs - all others not in use can be used for promotion 525 for (int i = 0; i < num_temps; i++) { 526 MarkTemp(core_temps[i]); 527 } 528 for (int i = 0; i < num_fp_temps; i++) { 529 MarkTemp(fp_temps[i]); 530 } 531} 532 533void X86Mir2Lir::FreeRegLocTemps(RegLocation rl_keep, RegLocation rl_free) { 534 DCHECK(rl_keep.wide); 535 DCHECK(rl_free.wide); 536 int free_low = rl_free.reg.GetLowReg(); 537 int free_high = rl_free.reg.GetHighReg(); 538 int keep_low = rl_keep.reg.GetLowReg(); 539 int keep_high = rl_keep.reg.GetHighReg(); 540 if ((free_low != keep_low) && (free_low != keep_high) && 541 (free_high != keep_low) && (free_high != keep_high)) { 542 // No overlap, free both 543 FreeTemp(free_low); 544 FreeTemp(free_high); 545 } 546} 547 548void X86Mir2Lir::SpillCoreRegs() { 549 if (num_core_spills_ == 0) { 550 return; 551 } 552 // Spill mask not including fake return address register 553 uint32_t mask = core_spill_mask_ & ~(1 << rRET); 554 int offset = frame_size_ - (4 * num_core_spills_); 555 for (int reg = 0; mask; mask >>= 1, reg++) { 556 if (mask & 0x1) { 557 StoreWordDisp(rs_rX86_SP, offset, RegStorage::Solo32(reg)); 558 offset += 4; 559 } 560 } 561} 562 563void X86Mir2Lir::UnSpillCoreRegs() { 564 if (num_core_spills_ == 0) { 565 return; 566 } 567 // Spill mask not including fake return address register 568 uint32_t mask = core_spill_mask_ & ~(1 << rRET); 569 int offset = frame_size_ - (4 * num_core_spills_); 570 for (int reg = 0; mask; mask >>= 1, reg++) { 571 if (mask & 0x1) { 572 LoadWordDisp(rs_rX86_SP, offset, RegStorage::Solo32(reg)); 573 offset += 4; 574 } 575 } 576} 577 578bool X86Mir2Lir::IsUnconditionalBranch(LIR* lir) { 579 return (lir->opcode == kX86Jmp8 || lir->opcode == kX86Jmp32); 580} 581 582X86Mir2Lir::X86Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena) 583 : Mir2Lir(cu, mir_graph, arena), 584 base_of_code_(nullptr), store_method_addr_(false), store_method_addr_used_(false), 585 method_address_insns_(arena, 100, kGrowableArrayMisc), 586 class_type_address_insns_(arena, 100, kGrowableArrayMisc), 587 call_method_insns_(arena, 100, kGrowableArrayMisc), 588 stack_decrement_(nullptr), stack_increment_(nullptr) { 589 if (kIsDebugBuild) { 590 for (int i = 0; i < kX86Last; i++) { 591 if (X86Mir2Lir::EncodingMap[i].opcode != i) { 592 LOG(FATAL) << "Encoding order for " << X86Mir2Lir::EncodingMap[i].name 593 << " is wrong: expecting " << i << ", seeing " 594 << static_cast<int>(X86Mir2Lir::EncodingMap[i].opcode); 595 } 596 } 597 } 598} 599 600Mir2Lir* X86CodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, 601 ArenaAllocator* const arena) { 602 return new X86Mir2Lir(cu, mir_graph, arena); 603} 604 605// Not used in x86 606RegStorage X86Mir2Lir::LoadHelper(ThreadOffset<4> offset) { 607 LOG(FATAL) << "Unexpected use of LoadHelper in x86"; 608 return RegStorage::InvalidReg(); 609} 610 611LIR* X86Mir2Lir::CheckSuspendUsingLoad() { 612 LOG(FATAL) << "Unexpected use of CheckSuspendUsingLoad in x86"; 613 return nullptr; 614} 615 616uint64_t X86Mir2Lir::GetTargetInstFlags(int opcode) { 617 DCHECK(!IsPseudoLirOp(opcode)); 618 return X86Mir2Lir::EncodingMap[opcode].flags; 619} 620 621const char* X86Mir2Lir::GetTargetInstName(int opcode) { 622 DCHECK(!IsPseudoLirOp(opcode)); 623 return X86Mir2Lir::EncodingMap[opcode].name; 624} 625 626const char* X86Mir2Lir::GetTargetInstFmt(int opcode) { 627 DCHECK(!IsPseudoLirOp(opcode)); 628 return X86Mir2Lir::EncodingMap[opcode].fmt; 629} 630 631/* 632 * Return an updated location record with current in-register status. 633 * If the value lives in live temps, reflect that fact. No code 634 * is generated. If the live value is part of an older pair, 635 * clobber both low and high. 636 */ 637// TODO: Reunify with common code after 'pair mess' has been fixed 638RegLocation X86Mir2Lir::UpdateLocWide(RegLocation loc) { 639 DCHECK(loc.wide); 640 DCHECK(CheckCorePoolSanity()); 641 if (loc.location != kLocPhysReg) { 642 DCHECK((loc.location == kLocDalvikFrame) || 643 (loc.location == kLocCompilerTemp)); 644 // Are the dalvik regs already live in physical registers? 645 RegisterInfo* info_lo = AllocLive(loc.s_reg_low, kAnyReg); 646 647 // Handle FP registers specially on x86. 648 if (info_lo && IsFpReg(info_lo->reg)) { 649 bool match = true; 650 651 // We can't match a FP register with a pair of Core registers. 652 match = match && (info_lo->pair == 0); 653 654 if (match) { 655 // We can reuse;update the register usage info. 656 loc.location = kLocPhysReg; 657 loc.vec_len = kVectorLength8; 658 // TODO: use k64BitVector 659 loc.reg = RegStorage(RegStorage::k64BitPair, info_lo->reg, info_lo->reg); 660 DCHECK(IsFpReg(loc.reg.GetLowReg())); 661 return loc; 662 } 663 // We can't easily reuse; clobber and free any overlaps. 664 if (info_lo) { 665 Clobber(info_lo->reg); 666 FreeTemp(info_lo->reg); 667 if (info_lo->pair) 668 Clobber(info_lo->partner); 669 } 670 } else { 671 RegisterInfo* info_hi = AllocLive(GetSRegHi(loc.s_reg_low), kAnyReg); 672 bool match = true; 673 match = match && (info_lo != NULL); 674 match = match && (info_hi != NULL); 675 // Are they both core or both FP? 676 match = match && (IsFpReg(info_lo->reg) == IsFpReg(info_hi->reg)); 677 // If a pair of floating point singles, are they properly aligned? 678 if (match && IsFpReg(info_lo->reg)) { 679 match &= ((info_lo->reg & 0x1) == 0); 680 match &= ((info_hi->reg - info_lo->reg) == 1); 681 } 682 // If previously used as a pair, it is the same pair? 683 if (match && (info_lo->pair || info_hi->pair)) { 684 match = (info_lo->pair == info_hi->pair); 685 match &= ((info_lo->reg == info_hi->partner) && 686 (info_hi->reg == info_lo->partner)); 687 } 688 if (match) { 689 // Can reuse - update the register usage info 690 loc.reg = RegStorage(RegStorage::k64BitPair, info_lo->reg, info_hi->reg); 691 loc.location = kLocPhysReg; 692 MarkPair(loc.reg.GetLowReg(), loc.reg.GetHighReg()); 693 DCHECK(!IsFpReg(loc.reg.GetLowReg()) || ((loc.reg.GetLowReg() & 0x1) == 0)); 694 return loc; 695 } 696 // Can't easily reuse - clobber and free any overlaps 697 if (info_lo) { 698 Clobber(info_lo->reg); 699 FreeTemp(info_lo->reg); 700 if (info_lo->pair) 701 Clobber(info_lo->partner); 702 } 703 if (info_hi) { 704 Clobber(info_hi->reg); 705 FreeTemp(info_hi->reg); 706 if (info_hi->pair) 707 Clobber(info_hi->partner); 708 } 709 } 710 } 711 return loc; 712} 713 714// TODO: Reunify with common code after 'pair mess' has been fixed 715RegLocation X86Mir2Lir::EvalLocWide(RegLocation loc, int reg_class, bool update) { 716 DCHECK(loc.wide); 717 718 loc = UpdateLocWide(loc); 719 720 /* If it is already in a register, we can assume proper form. Is it the right reg class? */ 721 if (loc.location == kLocPhysReg) { 722 DCHECK_EQ(IsFpReg(loc.reg.GetLowReg()), loc.IsVectorScalar()); 723 if (!RegClassMatches(reg_class, loc.reg)) { 724 /* It is the wrong register class. Reallocate and copy. */ 725 if (!IsFpReg(loc.reg.GetLowReg())) { 726 // We want this in a FP reg, and it is in core registers. 727 DCHECK(reg_class != kCoreReg); 728 // Allocate this into any FP reg, and mark it with the right size. 729 int32_t low_reg = AllocTypedTemp(true, reg_class).GetReg(); 730 OpVectorRegCopyWide(low_reg, loc.reg.GetLowReg(), loc.reg.GetHighReg()); 731 CopyRegInfo(low_reg, loc.reg.GetLowReg()); 732 Clobber(loc.reg); 733 loc.reg.SetReg(low_reg); 734 loc.reg.SetHighReg(low_reg); // Play nice with existing code. 735 loc.vec_len = kVectorLength8; 736 } else { 737 // The value is in a FP register, and we want it in a pair of core registers. 738 DCHECK_EQ(reg_class, kCoreReg); 739 DCHECK_EQ(loc.reg.GetLowReg(), loc.reg.GetHighReg()); 740 RegStorage new_regs = AllocTypedTempWide(false, kCoreReg); // Force to core registers. 741 OpRegCopyWide(new_regs, loc.reg); 742 CopyRegInfo(new_regs.GetLowReg(), loc.reg.GetLowReg()); 743 CopyRegInfo(new_regs.GetHighReg(), loc.reg.GetHighReg()); 744 Clobber(loc.reg); 745 loc.reg = new_regs; 746 MarkPair(loc.reg.GetLowReg(), loc.reg.GetHighReg()); 747 DCHECK(!IsFpReg(loc.reg.GetLowReg()) || ((loc.reg.GetLowReg() & 0x1) == 0)); 748 } 749 } 750 return loc; 751 } 752 753 DCHECK_NE(loc.s_reg_low, INVALID_SREG); 754 DCHECK_NE(GetSRegHi(loc.s_reg_low), INVALID_SREG); 755 756 loc.reg = AllocTypedTempWide(loc.fp, reg_class); 757 758 // FIXME: take advantage of RegStorage notation. 759 if (loc.reg.GetLowReg() == loc.reg.GetHighReg()) { 760 DCHECK(IsFpReg(loc.reg.GetLowReg())); 761 loc.vec_len = kVectorLength8; 762 } else { 763 MarkPair(loc.reg.GetLowReg(), loc.reg.GetHighReg()); 764 } 765 if (update) { 766 loc.location = kLocPhysReg; 767 MarkLive(loc.reg.GetLow(), loc.s_reg_low); 768 if (loc.reg.GetLowReg() != loc.reg.GetHighReg()) { 769 MarkLive(loc.reg.GetHigh(), GetSRegHi(loc.s_reg_low)); 770 } 771 } 772 return loc; 773} 774 775// TODO: Reunify with common code after 'pair mess' has been fixed 776RegLocation X86Mir2Lir::EvalLoc(RegLocation loc, int reg_class, bool update) { 777 if (loc.wide) 778 return EvalLocWide(loc, reg_class, update); 779 780 loc = UpdateLoc(loc); 781 782 if (loc.location == kLocPhysReg) { 783 if (!RegClassMatches(reg_class, loc.reg)) { 784 /* Wrong register class. Realloc, copy and transfer ownership. */ 785 RegStorage new_reg = AllocTypedTemp(loc.fp, reg_class); 786 OpRegCopy(new_reg, loc.reg); 787 CopyRegInfo(new_reg, loc.reg); 788 Clobber(loc.reg); 789 loc.reg = new_reg; 790 if (IsFpReg(loc.reg.GetReg()) && reg_class != kCoreReg) 791 loc.vec_len = kVectorLength4; 792 } 793 return loc; 794 } 795 796 DCHECK_NE(loc.s_reg_low, INVALID_SREG); 797 798 loc.reg = AllocTypedTemp(loc.fp, reg_class); 799 if (IsFpReg(loc.reg.GetReg()) && reg_class != kCoreReg) 800 loc.vec_len = kVectorLength4; 801 802 if (update) { 803 loc.location = kLocPhysReg; 804 MarkLive(loc.reg, loc.s_reg_low); 805 } 806 return loc; 807} 808 809RegStorage X86Mir2Lir::AllocTempDouble() { 810 // We really don't need a pair of registers. 811 // FIXME - update to double 812 int reg = AllocTempFloat().GetReg(); 813 return RegStorage(RegStorage::k64BitPair, reg, reg); 814} 815 816// TODO: Reunify with common code after 'pair mess' has been fixed 817void X86Mir2Lir::ResetDefLocWide(RegLocation rl) { 818 DCHECK(rl.wide); 819 RegisterInfo* p_low = IsTemp(rl.reg.GetLowReg()); 820 if (IsFpReg(rl.reg.GetLowReg())) { 821 // We are using only the low register. 822 if (p_low && !(cu_->disable_opt & (1 << kSuppressLoads))) { 823 NullifyRange(p_low->def_start, p_low->def_end, p_low->s_reg, rl.s_reg_low); 824 } 825 ResetDef(rl.reg.GetLowReg()); 826 } else { 827 RegisterInfo* p_high = IsTemp(rl.reg.GetHighReg()); 828 if (p_low && !(cu_->disable_opt & (1 << kSuppressLoads))) { 829 DCHECK(p_low->pair); 830 NullifyRange(p_low->def_start, p_low->def_end, p_low->s_reg, rl.s_reg_low); 831 } 832 if (p_high && !(cu_->disable_opt & (1 << kSuppressLoads))) { 833 DCHECK(p_high->pair); 834 } 835 ResetDef(rl.reg.GetLowReg()); 836 ResetDef(rl.reg.GetHighReg()); 837 } 838} 839 840void X86Mir2Lir::GenConstWide(RegLocation rl_dest, int64_t value) { 841 // Can we do this directly to memory? 842 rl_dest = UpdateLocWide(rl_dest); 843 if ((rl_dest.location == kLocDalvikFrame) || 844 (rl_dest.location == kLocCompilerTemp)) { 845 int32_t val_lo = Low32Bits(value); 846 int32_t val_hi = High32Bits(value); 847 int r_base = TargetReg(kSp).GetReg(); 848 int displacement = SRegOffset(rl_dest.s_reg_low); 849 850 LIR * store = NewLIR3(kX86Mov32MI, r_base, displacement + LOWORD_OFFSET, val_lo); 851 AnnotateDalvikRegAccess(store, (displacement + LOWORD_OFFSET) >> 2, 852 false /* is_load */, true /* is64bit */); 853 store = NewLIR3(kX86Mov32MI, r_base, displacement + HIWORD_OFFSET, val_hi); 854 AnnotateDalvikRegAccess(store, (displacement + HIWORD_OFFSET) >> 2, 855 false /* is_load */, true /* is64bit */); 856 return; 857 } 858 859 // Just use the standard code to do the generation. 860 Mir2Lir::GenConstWide(rl_dest, value); 861} 862 863// TODO: Merge with existing RegLocation dumper in vreg_analysis.cc 864void X86Mir2Lir::DumpRegLocation(RegLocation loc) { 865 LOG(INFO) << "location: " << loc.location << ',' 866 << (loc.wide ? " w" : " ") 867 << (loc.defined ? " D" : " ") 868 << (loc.is_const ? " c" : " ") 869 << (loc.fp ? " F" : " ") 870 << (loc.core ? " C" : " ") 871 << (loc.ref ? " r" : " ") 872 << (loc.high_word ? " h" : " ") 873 << (loc.home ? " H" : " ") 874 << " vec_len: " << loc.vec_len 875 << ", low: " << static_cast<int>(loc.reg.GetLowReg()) 876 << ", high: " << static_cast<int>(loc.reg.GetHighReg()) 877 << ", s_reg: " << loc.s_reg_low 878 << ", orig: " << loc.orig_sreg; 879} 880 881void X86Mir2Lir::Materialize() { 882 // A good place to put the analysis before starting. 883 AnalyzeMIR(); 884 885 // Now continue with regular code generation. 886 Mir2Lir::Materialize(); 887} 888 889void X86Mir2Lir::LoadMethodAddress(const MethodReference& target_method, InvokeType type, 890 SpecialTargetRegister symbolic_reg) { 891 /* 892 * For x86, just generate a 32 bit move immediate instruction, that will be filled 893 * in at 'link time'. For now, put a unique value based on target to ensure that 894 * code deduplication works. 895 */ 896 int target_method_idx = target_method.dex_method_index; 897 const DexFile* target_dex_file = target_method.dex_file; 898 const DexFile::MethodId& target_method_id = target_dex_file->GetMethodId(target_method_idx); 899 uintptr_t target_method_id_ptr = reinterpret_cast<uintptr_t>(&target_method_id); 900 901 // Generate the move instruction with the unique pointer and save index, dex_file, and type. 902 LIR *move = RawLIR(current_dalvik_offset_, kX86Mov32RI, TargetReg(symbolic_reg).GetReg(), 903 static_cast<int>(target_method_id_ptr), target_method_idx, 904 WrapPointer(const_cast<DexFile*>(target_dex_file)), type); 905 AppendLIR(move); 906 method_address_insns_.Insert(move); 907} 908 909void X86Mir2Lir::LoadClassType(uint32_t type_idx, SpecialTargetRegister symbolic_reg) { 910 /* 911 * For x86, just generate a 32 bit move immediate instruction, that will be filled 912 * in at 'link time'. For now, put a unique value based on target to ensure that 913 * code deduplication works. 914 */ 915 const DexFile::TypeId& id = cu_->dex_file->GetTypeId(type_idx); 916 uintptr_t ptr = reinterpret_cast<uintptr_t>(&id); 917 918 // Generate the move instruction with the unique pointer and save index and type. 919 LIR *move = RawLIR(current_dalvik_offset_, kX86Mov32RI, TargetReg(symbolic_reg).GetReg(), 920 static_cast<int>(ptr), type_idx); 921 AppendLIR(move); 922 class_type_address_insns_.Insert(move); 923} 924 925LIR *X86Mir2Lir::CallWithLinkerFixup(const MethodReference& target_method, InvokeType type) { 926 /* 927 * For x86, just generate a 32 bit call relative instruction, that will be filled 928 * in at 'link time'. For now, put a unique value based on target to ensure that 929 * code deduplication works. 930 */ 931 int target_method_idx = target_method.dex_method_index; 932 const DexFile* target_dex_file = target_method.dex_file; 933 const DexFile::MethodId& target_method_id = target_dex_file->GetMethodId(target_method_idx); 934 uintptr_t target_method_id_ptr = reinterpret_cast<uintptr_t>(&target_method_id); 935 936 // Generate the call instruction with the unique pointer and save index, dex_file, and type. 937 LIR *call = RawLIR(current_dalvik_offset_, kX86CallI, static_cast<int>(target_method_id_ptr), 938 target_method_idx, WrapPointer(const_cast<DexFile*>(target_dex_file)), type); 939 AppendLIR(call); 940 call_method_insns_.Insert(call); 941 return call; 942} 943 944void X86Mir2Lir::InstallLiteralPools() { 945 // These are handled differently for x86. 946 DCHECK(code_literal_list_ == nullptr); 947 DCHECK(method_literal_list_ == nullptr); 948 DCHECK(class_literal_list_ == nullptr); 949 950 // Handle the fixups for methods. 951 for (uint32_t i = 0; i < method_address_insns_.Size(); i++) { 952 LIR* p = method_address_insns_.Get(i); 953 DCHECK_EQ(p->opcode, kX86Mov32RI); 954 uint32_t target_method_idx = p->operands[2]; 955 const DexFile* target_dex_file = 956 reinterpret_cast<const DexFile*>(UnwrapPointer(p->operands[3])); 957 958 // The offset to patch is the last 4 bytes of the instruction. 959 int patch_offset = p->offset + p->flags.size - 4; 960 cu_->compiler_driver->AddMethodPatch(cu_->dex_file, cu_->class_def_idx, 961 cu_->method_idx, cu_->invoke_type, 962 target_method_idx, target_dex_file, 963 static_cast<InvokeType>(p->operands[4]), 964 patch_offset); 965 } 966 967 // Handle the fixups for class types. 968 for (uint32_t i = 0; i < class_type_address_insns_.Size(); i++) { 969 LIR* p = class_type_address_insns_.Get(i); 970 DCHECK_EQ(p->opcode, kX86Mov32RI); 971 uint32_t target_method_idx = p->operands[2]; 972 973 // The offset to patch is the last 4 bytes of the instruction. 974 int patch_offset = p->offset + p->flags.size - 4; 975 cu_->compiler_driver->AddClassPatch(cu_->dex_file, cu_->class_def_idx, 976 cu_->method_idx, target_method_idx, patch_offset); 977 } 978 979 // And now the PC-relative calls to methods. 980 for (uint32_t i = 0; i < call_method_insns_.Size(); i++) { 981 LIR* p = call_method_insns_.Get(i); 982 DCHECK_EQ(p->opcode, kX86CallI); 983 uint32_t target_method_idx = p->operands[1]; 984 const DexFile* target_dex_file = 985 reinterpret_cast<const DexFile*>(UnwrapPointer(p->operands[2])); 986 987 // The offset to patch is the last 4 bytes of the instruction. 988 int patch_offset = p->offset + p->flags.size - 4; 989 cu_->compiler_driver->AddRelativeCodePatch(cu_->dex_file, cu_->class_def_idx, 990 cu_->method_idx, cu_->invoke_type, 991 target_method_idx, target_dex_file, 992 static_cast<InvokeType>(p->operands[3]), 993 patch_offset, -4 /* offset */); 994 } 995 996 // And do the normal processing. 997 Mir2Lir::InstallLiteralPools(); 998} 999 1000/* 1001 * Fast string.index_of(I) & (II). Inline check for simple case of char <= 0xffff, 1002 * otherwise bails to standard library code. 1003 */ 1004bool X86Mir2Lir::GenInlinedIndexOf(CallInfo* info, bool zero_based) { 1005 ClobberCallerSave(); 1006 LockCallTemps(); // Using fixed registers 1007 1008 // EAX: 16 bit character being searched. 1009 // ECX: count: number of words to be searched. 1010 // EDI: String being searched. 1011 // EDX: temporary during execution. 1012 // EBX: temporary during execution. 1013 1014 RegLocation rl_obj = info->args[0]; 1015 RegLocation rl_char = info->args[1]; 1016 RegLocation rl_start; // Note: only present in III flavor or IndexOf. 1017 1018 uint32_t char_value = 1019 rl_char.is_const ? mir_graph_->ConstantValue(rl_char.orig_sreg) : 0; 1020 1021 if (char_value > 0xFFFF) { 1022 // We have to punt to the real String.indexOf. 1023 return false; 1024 } 1025 1026 // Okay, we are commited to inlining this. 1027 RegLocation rl_return = GetReturn(false); 1028 RegLocation rl_dest = InlineTarget(info); 1029 1030 // Is the string non-NULL? 1031 LoadValueDirectFixed(rl_obj, rs_rDX); 1032 GenNullCheck(rs_rDX, info->opt_flags); 1033 info->opt_flags |= MIR_IGNORE_NULL_CHECK; // Record that we've null checked. 1034 1035 // Does the character fit in 16 bits? 1036 LIR* launchpad_branch = nullptr; 1037 if (rl_char.is_const) { 1038 // We need the value in EAX. 1039 LoadConstantNoClobber(rs_rAX, char_value); 1040 } else { 1041 // Character is not a constant; compare at runtime. 1042 LoadValueDirectFixed(rl_char, rs_rAX); 1043 launchpad_branch = OpCmpImmBranch(kCondGt, rs_rAX, 0xFFFF, nullptr); 1044 } 1045 1046 // From here down, we know that we are looking for a char that fits in 16 bits. 1047 // Location of reference to data array within the String object. 1048 int value_offset = mirror::String::ValueOffset().Int32Value(); 1049 // Location of count within the String object. 1050 int count_offset = mirror::String::CountOffset().Int32Value(); 1051 // Starting offset within data array. 1052 int offset_offset = mirror::String::OffsetOffset().Int32Value(); 1053 // Start of char data with array_. 1054 int data_offset = mirror::Array::DataOffset(sizeof(uint16_t)).Int32Value(); 1055 1056 // Character is in EAX. 1057 // Object pointer is in EDX. 1058 1059 // We need to preserve EDI, but have no spare registers, so push it on the stack. 1060 // We have to remember that all stack addresses after this are offset by sizeof(EDI). 1061 NewLIR1(kX86Push32R, rDI); 1062 1063 // Compute the number of words to search in to rCX. 1064 LoadWordDisp(rs_rDX, count_offset, rs_rCX); 1065 LIR *length_compare = nullptr; 1066 int start_value = 0; 1067 bool is_index_on_stack = false; 1068 if (zero_based) { 1069 // We have to handle an empty string. Use special instruction JECXZ. 1070 length_compare = NewLIR0(kX86Jecxz8); 1071 } else { 1072 rl_start = info->args[2]; 1073 // We have to offset by the start index. 1074 if (rl_start.is_const) { 1075 start_value = mir_graph_->ConstantValue(rl_start.orig_sreg); 1076 start_value = std::max(start_value, 0); 1077 1078 // Is the start > count? 1079 length_compare = OpCmpImmBranch(kCondLe, rs_rCX, start_value, nullptr); 1080 1081 if (start_value != 0) { 1082 OpRegImm(kOpSub, rs_rCX, start_value); 1083 } 1084 } else { 1085 // Runtime start index. 1086 rl_start = UpdateLoc(rl_start); 1087 if (rl_start.location == kLocPhysReg) { 1088 // Handle "start index < 0" case. 1089 OpRegReg(kOpXor, rs_rBX, rs_rBX); 1090 OpRegReg(kOpCmp, rl_start.reg, rs_rBX); 1091 OpCondRegReg(kOpCmov, kCondLt, rl_start.reg, rs_rBX); 1092 1093 // The length of the string should be greater than the start index. 1094 length_compare = OpCmpBranch(kCondLe, rs_rCX, rl_start.reg, nullptr); 1095 OpRegReg(kOpSub, rs_rCX, rl_start.reg); 1096 if (rl_start.reg == rs_rDI) { 1097 // The special case. We will use EDI further, so lets put start index to stack. 1098 NewLIR1(kX86Push32R, rDI); 1099 is_index_on_stack = true; 1100 } 1101 } else { 1102 // Load the start index from stack, remembering that we pushed EDI. 1103 int displacement = SRegOffset(rl_start.s_reg_low) + sizeof(uint32_t); 1104 LoadWordDisp(rs_rX86_SP, displacement, rs_rBX); 1105 OpRegReg(kOpXor, rs_rDI, rs_rDI); 1106 OpRegReg(kOpCmp, rs_rBX, rs_rDI); 1107 OpCondRegReg(kOpCmov, kCondLt, rs_rBX, rs_rDI); 1108 1109 length_compare = OpCmpBranch(kCondLe, rs_rCX, rs_rBX, nullptr); 1110 OpRegReg(kOpSub, rs_rCX, rs_rBX); 1111 // Put the start index to stack. 1112 NewLIR1(kX86Push32R, rBX); 1113 is_index_on_stack = true; 1114 } 1115 } 1116 } 1117 DCHECK(length_compare != nullptr); 1118 1119 // ECX now contains the count in words to be searched. 1120 1121 // Load the address of the string into EBX. 1122 // The string starts at VALUE(String) + 2 * OFFSET(String) + DATA_OFFSET. 1123 LoadWordDisp(rs_rDX, value_offset, rs_rDI); 1124 LoadWordDisp(rs_rDX, offset_offset, rs_rBX); 1125 OpLea(rs_rBX, rs_rDI, rs_rBX, 1, data_offset); 1126 1127 // Now compute into EDI where the search will start. 1128 if (zero_based || rl_start.is_const) { 1129 if (start_value == 0) { 1130 OpRegCopy(rs_rDI, rs_rBX); 1131 } else { 1132 NewLIR3(kX86Lea32RM, rDI, rBX, 2 * start_value); 1133 } 1134 } else { 1135 if (is_index_on_stack == true) { 1136 // Load the start index from stack. 1137 NewLIR1(kX86Pop32R, rDX); 1138 OpLea(rs_rDI, rs_rBX, rs_rDX, 1, 0); 1139 } else { 1140 OpLea(rs_rDI, rs_rBX, rl_start.reg, 1, 0); 1141 } 1142 } 1143 1144 // EDI now contains the start of the string to be searched. 1145 // We are all prepared to do the search for the character. 1146 NewLIR0(kX86RepneScasw); 1147 1148 // Did we find a match? 1149 LIR* failed_branch = OpCondBranch(kCondNe, nullptr); 1150 1151 // yes, we matched. Compute the index of the result. 1152 // index = ((curr_ptr - orig_ptr) / 2) - 1. 1153 OpRegReg(kOpSub, rs_rDI, rs_rBX); 1154 OpRegImm(kOpAsr, rs_rDI, 1); 1155 NewLIR3(kX86Lea32RM, rl_return.reg.GetReg(), rDI, -1); 1156 LIR *all_done = NewLIR1(kX86Jmp8, 0); 1157 1158 // Failed to match; return -1. 1159 LIR *not_found = NewLIR0(kPseudoTargetLabel); 1160 length_compare->target = not_found; 1161 failed_branch->target = not_found; 1162 LoadConstantNoClobber(rl_return.reg, -1); 1163 1164 // And join up at the end. 1165 all_done->target = NewLIR0(kPseudoTargetLabel); 1166 // Restore EDI from the stack. 1167 NewLIR1(kX86Pop32R, rDI); 1168 1169 // Out of line code returns here. 1170 if (launchpad_branch != nullptr) { 1171 LIR *return_point = NewLIR0(kPseudoTargetLabel); 1172 AddIntrinsicLaunchpad(info, launchpad_branch, return_point); 1173 } 1174 1175 StoreValue(rl_dest, rl_return); 1176 return true; 1177} 1178 1179/* 1180 * @brief Enter a 32 bit quantity into the FDE buffer 1181 * @param buf FDE buffer. 1182 * @param data Data value. 1183 */ 1184static void PushWord(std::vector<uint8_t>&buf, int data) { 1185 buf.push_back(data & 0xff); 1186 buf.push_back((data >> 8) & 0xff); 1187 buf.push_back((data >> 16) & 0xff); 1188 buf.push_back((data >> 24) & 0xff); 1189} 1190 1191/* 1192 * @brief Enter an 'advance LOC' into the FDE buffer 1193 * @param buf FDE buffer. 1194 * @param increment Amount by which to increase the current location. 1195 */ 1196static void AdvanceLoc(std::vector<uint8_t>&buf, uint32_t increment) { 1197 if (increment < 64) { 1198 // Encoding in opcode. 1199 buf.push_back(0x1 << 6 | increment); 1200 } else if (increment < 256) { 1201 // Single byte delta. 1202 buf.push_back(0x02); 1203 buf.push_back(increment); 1204 } else if (increment < 256 * 256) { 1205 // Two byte delta. 1206 buf.push_back(0x03); 1207 buf.push_back(increment & 0xff); 1208 buf.push_back((increment >> 8) & 0xff); 1209 } else { 1210 // Four byte delta. 1211 buf.push_back(0x04); 1212 PushWord(buf, increment); 1213 } 1214} 1215 1216 1217std::vector<uint8_t>* X86CFIInitialization() { 1218 return X86Mir2Lir::ReturnCommonCallFrameInformation(); 1219} 1220 1221std::vector<uint8_t>* X86Mir2Lir::ReturnCommonCallFrameInformation() { 1222 std::vector<uint8_t>*cfi_info = new std::vector<uint8_t>; 1223 1224 // Length of the CIE (except for this field). 1225 PushWord(*cfi_info, 16); 1226 1227 // CIE id. 1228 PushWord(*cfi_info, 0xFFFFFFFFU); 1229 1230 // Version: 3. 1231 cfi_info->push_back(0x03); 1232 1233 // Augmentation: empty string. 1234 cfi_info->push_back(0x0); 1235 1236 // Code alignment: 1. 1237 cfi_info->push_back(0x01); 1238 1239 // Data alignment: -4. 1240 cfi_info->push_back(0x7C); 1241 1242 // Return address register (R8). 1243 cfi_info->push_back(0x08); 1244 1245 // Initial return PC is 4(ESP): DW_CFA_def_cfa R4 4. 1246 cfi_info->push_back(0x0C); 1247 cfi_info->push_back(0x04); 1248 cfi_info->push_back(0x04); 1249 1250 // Return address location: 0(SP): DW_CFA_offset R8 1 (* -4);. 1251 cfi_info->push_back(0x2 << 6 | 0x08); 1252 cfi_info->push_back(0x01); 1253 1254 // And 2 Noops to align to 4 byte boundary. 1255 cfi_info->push_back(0x0); 1256 cfi_info->push_back(0x0); 1257 1258 DCHECK_EQ(cfi_info->size() & 3, 0U); 1259 return cfi_info; 1260} 1261 1262static void EncodeUnsignedLeb128(std::vector<uint8_t>& buf, uint32_t value) { 1263 uint8_t buffer[12]; 1264 uint8_t *ptr = EncodeUnsignedLeb128(buffer, value); 1265 for (uint8_t *p = buffer; p < ptr; p++) { 1266 buf.push_back(*p); 1267 } 1268} 1269 1270std::vector<uint8_t>* X86Mir2Lir::ReturnCallFrameInformation() { 1271 std::vector<uint8_t>*cfi_info = new std::vector<uint8_t>; 1272 1273 // Generate the FDE for the method. 1274 DCHECK_NE(data_offset_, 0U); 1275 1276 // Length (will be filled in later in this routine). 1277 PushWord(*cfi_info, 0); 1278 1279 // CIE_pointer (can be filled in by linker); might be left at 0 if there is only 1280 // one CIE for the whole debug_frame section. 1281 PushWord(*cfi_info, 0); 1282 1283 // 'initial_location' (filled in by linker). 1284 PushWord(*cfi_info, 0); 1285 1286 // 'address_range' (number of bytes in the method). 1287 PushWord(*cfi_info, data_offset_); 1288 1289 // The instructions in the FDE. 1290 if (stack_decrement_ != nullptr) { 1291 // Advance LOC to just past the stack decrement. 1292 uint32_t pc = NEXT_LIR(stack_decrement_)->offset; 1293 AdvanceLoc(*cfi_info, pc); 1294 1295 // Now update the offset to the call frame: DW_CFA_def_cfa_offset frame_size. 1296 cfi_info->push_back(0x0e); 1297 EncodeUnsignedLeb128(*cfi_info, frame_size_); 1298 1299 // We continue with that stack until the epilogue. 1300 if (stack_increment_ != nullptr) { 1301 uint32_t new_pc = NEXT_LIR(stack_increment_)->offset; 1302 AdvanceLoc(*cfi_info, new_pc - pc); 1303 1304 // We probably have code snippets after the epilogue, so save the 1305 // current state: DW_CFA_remember_state. 1306 cfi_info->push_back(0x0a); 1307 1308 // We have now popped the stack: DW_CFA_def_cfa_offset 4. There is only the return 1309 // PC on the stack now. 1310 cfi_info->push_back(0x0e); 1311 EncodeUnsignedLeb128(*cfi_info, 4); 1312 1313 // Everything after that is the same as before the epilogue. 1314 // Stack bump was followed by RET instruction. 1315 LIR *post_ret_insn = NEXT_LIR(NEXT_LIR(stack_increment_)); 1316 if (post_ret_insn != nullptr) { 1317 pc = new_pc; 1318 new_pc = post_ret_insn->offset; 1319 AdvanceLoc(*cfi_info, new_pc - pc); 1320 // Restore the state: DW_CFA_restore_state. 1321 cfi_info->push_back(0x0b); 1322 } 1323 } 1324 } 1325 1326 // Padding to a multiple of 4 1327 while ((cfi_info->size() & 3) != 0) { 1328 // DW_CFA_nop is encoded as 0. 1329 cfi_info->push_back(0); 1330 } 1331 1332 // Set the length of the FDE inside the generated bytes. 1333 uint32_t length = cfi_info->size() - 4; 1334 (*cfi_info)[0] = length; 1335 (*cfi_info)[1] = length >> 8; 1336 (*cfi_info)[2] = length >> 16; 1337 (*cfi_info)[3] = length >> 24; 1338 return cfi_info; 1339} 1340 1341} // namespace art 1342