target_x86.cc revision ae9fd93c39a341e2dffe15c61cc7d9e841fa92c4
1/*
2 * Copyright (C) 2012 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 *      http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#include <string>
18#include <inttypes.h>
19
20#include "codegen_x86.h"
21#include "dex/compiler_internals.h"
22#include "dex/quick/mir_to_lir-inl.h"
23#include "mirror/array.h"
24#include "mirror/string.h"
25#include "x86_lir.h"
26
27namespace art {
28
29// FIXME: restore "static" when usage uncovered
30/*static*/ int core_regs[] = {
31  rAX, rCX, rDX, rBX, rX86_SP, rBP, rSI, rDI
32#ifdef TARGET_REX_SUPPORT
33  r8, r9, r10, r11, r12, r13, r14, 15
34#endif
35};
36/*static*/ int ReservedRegs[] = {rX86_SP};
37/*static*/ int core_temps[] = {rAX, rCX, rDX, rBX};
38/*static*/ int FpRegs[] = {
39  fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7,
40#ifdef TARGET_REX_SUPPORT
41  fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15
42#endif
43};
44/*static*/ int fp_temps[] = {
45  fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7,
46#ifdef TARGET_REX_SUPPORT
47  fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15
48#endif
49};
50
51RegLocation X86Mir2Lir::LocCReturn() {
52  RegLocation res = X86_LOC_C_RETURN;
53  return res;
54}
55
56RegLocation X86Mir2Lir::LocCReturnWide() {
57  RegLocation res = X86_LOC_C_RETURN_WIDE;
58  return res;
59}
60
61RegLocation X86Mir2Lir::LocCReturnFloat() {
62  RegLocation res = X86_LOC_C_RETURN_FLOAT;
63  return res;
64}
65
66RegLocation X86Mir2Lir::LocCReturnDouble() {
67  RegLocation res = X86_LOC_C_RETURN_DOUBLE;
68  return res;
69}
70
71// Return a target-dependent special register.
72int X86Mir2Lir::TargetReg(SpecialTargetRegister reg) {
73  int res = INVALID_REG;
74  switch (reg) {
75    case kSelf: res = rX86_SELF; break;
76    case kSuspend: res =  rX86_SUSPEND; break;
77    case kLr: res =  rX86_LR; break;
78    case kPc: res =  rX86_PC; break;
79    case kSp: res =  rX86_SP; break;
80    case kArg0: res = rX86_ARG0; break;
81    case kArg1: res = rX86_ARG1; break;
82    case kArg2: res = rX86_ARG2; break;
83    case kArg3: res = rX86_ARG3; break;
84    case kFArg0: res = rX86_FARG0; break;
85    case kFArg1: res = rX86_FARG1; break;
86    case kFArg2: res = rX86_FARG2; break;
87    case kFArg3: res = rX86_FARG3; break;
88    case kRet0: res = rX86_RET0; break;
89    case kRet1: res = rX86_RET1; break;
90    case kInvokeTgt: res = rX86_INVOKE_TGT; break;
91    case kHiddenArg: res = rAX; break;
92    case kHiddenFpArg: res = fr0; break;
93    case kCount: res = rX86_COUNT; break;
94  }
95  return res;
96}
97
98int X86Mir2Lir::GetArgMappingToPhysicalReg(int arg_num) {
99  // For the 32-bit internal ABI, the first 3 arguments are passed in registers.
100  // TODO: This is not 64-bit compliant and depends on new internal ABI.
101  switch (arg_num) {
102    case 0:
103      return rX86_ARG1;
104    case 1:
105      return rX86_ARG2;
106    case 2:
107      return rX86_ARG3;
108    default:
109      return INVALID_REG;
110  }
111}
112
113// Create a double from a pair of singles.
114int X86Mir2Lir::S2d(int low_reg, int high_reg) {
115  return X86_S2D(low_reg, high_reg);
116}
117
118// Return mask to strip off fp reg flags and bias.
119uint32_t X86Mir2Lir::FpRegMask() {
120  return X86_FP_REG_MASK;
121}
122
123// True if both regs single, both core or both double.
124bool X86Mir2Lir::SameRegType(int reg1, int reg2) {
125  return (X86_REGTYPE(reg1) == X86_REGTYPE(reg2));
126}
127
128/*
129 * Decode the register id.
130 */
131uint64_t X86Mir2Lir::GetRegMaskCommon(int reg) {
132  uint64_t seed;
133  int shift;
134  int reg_id;
135
136  reg_id = reg & 0xf;
137  /* Double registers in x86 are just a single FP register */
138  seed = 1;
139  /* FP register starts at bit position 16 */
140  shift = X86_FPREG(reg) ? kX86FPReg0 : 0;
141  /* Expand the double register id into single offset */
142  shift += reg_id;
143  return (seed << shift);
144}
145
146uint64_t X86Mir2Lir::GetPCUseDefEncoding() {
147  /*
148   * FIXME: might make sense to use a virtual resource encoding bit for pc.  Might be
149   * able to clean up some of the x86/Arm_Mips differences
150   */
151  LOG(FATAL) << "Unexpected call to GetPCUseDefEncoding for x86";
152  return 0ULL;
153}
154
155void X86Mir2Lir::SetupTargetResourceMasks(LIR* lir, uint64_t flags) {
156  DCHECK_EQ(cu_->instruction_set, kX86);
157  DCHECK(!lir->flags.use_def_invalid);
158
159  // X86-specific resource map setup here.
160  if (flags & REG_USE_SP) {
161    lir->u.m.use_mask |= ENCODE_X86_REG_SP;
162  }
163
164  if (flags & REG_DEF_SP) {
165    lir->u.m.def_mask |= ENCODE_X86_REG_SP;
166  }
167
168  if (flags & REG_DEFA) {
169    SetupRegMask(&lir->u.m.def_mask, rAX);
170  }
171
172  if (flags & REG_DEFD) {
173    SetupRegMask(&lir->u.m.def_mask, rDX);
174  }
175  if (flags & REG_USEA) {
176    SetupRegMask(&lir->u.m.use_mask, rAX);
177  }
178
179  if (flags & REG_USEC) {
180    SetupRegMask(&lir->u.m.use_mask, rCX);
181  }
182
183  if (flags & REG_USED) {
184    SetupRegMask(&lir->u.m.use_mask, rDX);
185  }
186
187  if (flags & REG_USEB) {
188    SetupRegMask(&lir->u.m.use_mask, rBX);
189  }
190
191  // Fixup hard to describe instruction: Uses rAX, rCX, rDI; sets rDI.
192  if (lir->opcode == kX86RepneScasw) {
193    SetupRegMask(&lir->u.m.use_mask, rAX);
194    SetupRegMask(&lir->u.m.use_mask, rCX);
195    SetupRegMask(&lir->u.m.use_mask, rDI);
196    SetupRegMask(&lir->u.m.def_mask, rDI);
197  }
198}
199
200/* For dumping instructions */
201static const char* x86RegName[] = {
202  "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
203  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
204};
205
206static const char* x86CondName[] = {
207  "O",
208  "NO",
209  "B/NAE/C",
210  "NB/AE/NC",
211  "Z/EQ",
212  "NZ/NE",
213  "BE/NA",
214  "NBE/A",
215  "S",
216  "NS",
217  "P/PE",
218  "NP/PO",
219  "L/NGE",
220  "NL/GE",
221  "LE/NG",
222  "NLE/G"
223};
224
225/*
226 * Interpret a format string and build a string no longer than size
227 * See format key in Assemble.cc.
228 */
229std::string X86Mir2Lir::BuildInsnString(const char *fmt, LIR *lir, unsigned char* base_addr) {
230  std::string buf;
231  size_t i = 0;
232  size_t fmt_len = strlen(fmt);
233  while (i < fmt_len) {
234    if (fmt[i] != '!') {
235      buf += fmt[i];
236      i++;
237    } else {
238      i++;
239      DCHECK_LT(i, fmt_len);
240      char operand_number_ch = fmt[i];
241      i++;
242      if (operand_number_ch == '!') {
243        buf += "!";
244      } else {
245        int operand_number = operand_number_ch - '0';
246        DCHECK_LT(operand_number, 6);  // Expect upto 6 LIR operands.
247        DCHECK_LT(i, fmt_len);
248        int operand = lir->operands[operand_number];
249        switch (fmt[i]) {
250          case 'c':
251            DCHECK_LT(static_cast<size_t>(operand), sizeof(x86CondName));
252            buf += x86CondName[operand];
253            break;
254          case 'd':
255            buf += StringPrintf("%d", operand);
256            break;
257          case 'p': {
258            EmbeddedData *tab_rec = reinterpret_cast<EmbeddedData*>(UnwrapPointer(operand));
259            buf += StringPrintf("0x%08x", tab_rec->offset);
260            break;
261          }
262          case 'r':
263            if (X86_FPREG(operand) || X86_DOUBLEREG(operand)) {
264              int fp_reg = operand & X86_FP_REG_MASK;
265              buf += StringPrintf("xmm%d", fp_reg);
266            } else {
267              DCHECK_LT(static_cast<size_t>(operand), sizeof(x86RegName));
268              buf += x86RegName[operand];
269            }
270            break;
271          case 't':
272            buf += StringPrintf("0x%08" PRIxPTR " (L%p)",
273                                reinterpret_cast<uintptr_t>(base_addr) + lir->offset + operand,
274                                lir->target);
275            break;
276          default:
277            buf += StringPrintf("DecodeError '%c'", fmt[i]);
278            break;
279        }
280        i++;
281      }
282    }
283  }
284  return buf;
285}
286
287void X86Mir2Lir::DumpResourceMask(LIR *x86LIR, uint64_t mask, const char *prefix) {
288  char buf[256];
289  buf[0] = 0;
290
291  if (mask == ENCODE_ALL) {
292    strcpy(buf, "all");
293  } else {
294    char num[8];
295    int i;
296
297    for (i = 0; i < kX86RegEnd; i++) {
298      if (mask & (1ULL << i)) {
299        snprintf(num, arraysize(num), "%d ", i);
300        strcat(buf, num);
301      }
302    }
303
304    if (mask & ENCODE_CCODE) {
305      strcat(buf, "cc ");
306    }
307    /* Memory bits */
308    if (x86LIR && (mask & ENCODE_DALVIK_REG)) {
309      snprintf(buf + strlen(buf), arraysize(buf) - strlen(buf), "dr%d%s",
310               DECODE_ALIAS_INFO_REG(x86LIR->flags.alias_info),
311               (DECODE_ALIAS_INFO_WIDE(x86LIR->flags.alias_info)) ? "(+1)" : "");
312    }
313    if (mask & ENCODE_LITERAL) {
314      strcat(buf, "lit ");
315    }
316
317    if (mask & ENCODE_HEAP_REF) {
318      strcat(buf, "heap ");
319    }
320    if (mask & ENCODE_MUST_NOT_ALIAS) {
321      strcat(buf, "noalias ");
322    }
323  }
324  if (buf[0]) {
325    LOG(INFO) << prefix << ": " <<  buf;
326  }
327}
328
329void X86Mir2Lir::AdjustSpillMask() {
330  // Adjustment for LR spilling, x86 has no LR so nothing to do here
331  core_spill_mask_ |= (1 << rRET);
332  num_core_spills_++;
333}
334
335/*
336 * Mark a callee-save fp register as promoted.  Note that
337 * vpush/vpop uses contiguous register lists so we must
338 * include any holes in the mask.  Associate holes with
339 * Dalvik register INVALID_VREG (0xFFFFU).
340 */
341void X86Mir2Lir::MarkPreservedSingle(int v_reg, int reg) {
342  UNIMPLEMENTED(WARNING) << "MarkPreservedSingle";
343#if 0
344  LOG(FATAL) << "No support yet for promoted FP regs";
345#endif
346}
347
348void X86Mir2Lir::FlushRegWide(int reg1, int reg2) {
349  RegisterInfo* info1 = GetRegInfo(reg1);
350  RegisterInfo* info2 = GetRegInfo(reg2);
351  DCHECK(info1 && info2 && info1->pair && info2->pair &&
352         (info1->partner == info2->reg) &&
353         (info2->partner == info1->reg));
354  if ((info1->live && info1->dirty) || (info2->live && info2->dirty)) {
355    if (!(info1->is_temp && info2->is_temp)) {
356      /* Should not happen.  If it does, there's a problem in eval_loc */
357      LOG(FATAL) << "Long half-temp, half-promoted";
358    }
359
360    info1->dirty = false;
361    info2->dirty = false;
362    if (mir_graph_->SRegToVReg(info2->s_reg) < mir_graph_->SRegToVReg(info1->s_reg))
363      info1 = info2;
364    int v_reg = mir_graph_->SRegToVReg(info1->s_reg);
365    StoreBaseDispWide(rX86_SP, VRegOffset(v_reg), info1->reg, info1->partner);
366  }
367}
368
369void X86Mir2Lir::FlushReg(int reg) {
370  RegisterInfo* info = GetRegInfo(reg);
371  if (info->live && info->dirty) {
372    info->dirty = false;
373    int v_reg = mir_graph_->SRegToVReg(info->s_reg);
374    StoreBaseDisp(rX86_SP, VRegOffset(v_reg), reg, kWord);
375  }
376}
377
378/* Give access to the target-dependent FP register encoding to common code */
379bool X86Mir2Lir::IsFpReg(int reg) {
380  return X86_FPREG(reg);
381}
382
383/* Clobber all regs that might be used by an external C call */
384void X86Mir2Lir::ClobberCallerSave() {
385  Clobber(rAX);
386  Clobber(rCX);
387  Clobber(rDX);
388  Clobber(rBX);
389}
390
391RegLocation X86Mir2Lir::GetReturnWideAlt() {
392  RegLocation res = LocCReturnWide();
393  CHECK(res.low_reg == rAX);
394  CHECK(res.high_reg == rDX);
395  Clobber(rAX);
396  Clobber(rDX);
397  MarkInUse(rAX);
398  MarkInUse(rDX);
399  MarkPair(res.low_reg, res.high_reg);
400  return res;
401}
402
403RegLocation X86Mir2Lir::GetReturnAlt() {
404  RegLocation res = LocCReturn();
405  res.low_reg = rDX;
406  Clobber(rDX);
407  MarkInUse(rDX);
408  return res;
409}
410
411/* To be used when explicitly managing register use */
412void X86Mir2Lir::LockCallTemps() {
413  LockTemp(rX86_ARG0);
414  LockTemp(rX86_ARG1);
415  LockTemp(rX86_ARG2);
416  LockTemp(rX86_ARG3);
417}
418
419/* To be used when explicitly managing register use */
420void X86Mir2Lir::FreeCallTemps() {
421  FreeTemp(rX86_ARG0);
422  FreeTemp(rX86_ARG1);
423  FreeTemp(rX86_ARG2);
424  FreeTemp(rX86_ARG3);
425}
426
427void X86Mir2Lir::GenMemBarrier(MemBarrierKind barrier_kind) {
428#if ANDROID_SMP != 0
429  // TODO: optimize fences
430  NewLIR0(kX86Mfence);
431#endif
432}
433/*
434 * Alloc a pair of core registers, or a double.  Low reg in low byte,
435 * high reg in next byte.
436 */
437int X86Mir2Lir::AllocTypedTempPair(bool fp_hint,
438                          int reg_class) {
439  int high_reg;
440  int low_reg;
441  int res = 0;
442
443  if (((reg_class == kAnyReg) && fp_hint) || (reg_class == kFPReg)) {
444    low_reg = AllocTempDouble();
445    high_reg = low_reg;  // only one allocated!
446    res = (low_reg & 0xff) | ((high_reg & 0xff) << 8);
447    return res;
448  }
449
450  low_reg = AllocTemp();
451  high_reg = AllocTemp();
452  res = (low_reg & 0xff) | ((high_reg & 0xff) << 8);
453  return res;
454}
455
456int X86Mir2Lir::AllocTypedTemp(bool fp_hint, int reg_class) {
457  if (((reg_class == kAnyReg) && fp_hint) || (reg_class == kFPReg)) {
458    return AllocTempFloat();
459  }
460  return AllocTemp();
461}
462
463void X86Mir2Lir::CompilerInitializeRegAlloc() {
464  int num_regs = sizeof(core_regs)/sizeof(*core_regs);
465  int num_reserved = sizeof(ReservedRegs)/sizeof(*ReservedRegs);
466  int num_temps = sizeof(core_temps)/sizeof(*core_temps);
467  int num_fp_regs = sizeof(FpRegs)/sizeof(*FpRegs);
468  int num_fp_temps = sizeof(fp_temps)/sizeof(*fp_temps);
469  reg_pool_ = static_cast<RegisterPool*>(arena_->Alloc(sizeof(*reg_pool_),
470                                                       ArenaAllocator::kAllocRegAlloc));
471  reg_pool_->num_core_regs = num_regs;
472  reg_pool_->core_regs =
473      static_cast<RegisterInfo*>(arena_->Alloc(num_regs * sizeof(*reg_pool_->core_regs),
474                                               ArenaAllocator::kAllocRegAlloc));
475  reg_pool_->num_fp_regs = num_fp_regs;
476  reg_pool_->FPRegs =
477      static_cast<RegisterInfo *>(arena_->Alloc(num_fp_regs * sizeof(*reg_pool_->FPRegs),
478                                                ArenaAllocator::kAllocRegAlloc));
479  CompilerInitPool(reg_pool_->core_regs, core_regs, reg_pool_->num_core_regs);
480  CompilerInitPool(reg_pool_->FPRegs, FpRegs, reg_pool_->num_fp_regs);
481  // Keep special registers from being allocated
482  for (int i = 0; i < num_reserved; i++) {
483    MarkInUse(ReservedRegs[i]);
484  }
485  // Mark temp regs - all others not in use can be used for promotion
486  for (int i = 0; i < num_temps; i++) {
487    MarkTemp(core_temps[i]);
488  }
489  for (int i = 0; i < num_fp_temps; i++) {
490    MarkTemp(fp_temps[i]);
491  }
492}
493
494void X86Mir2Lir::FreeRegLocTemps(RegLocation rl_keep,
495                     RegLocation rl_free) {
496  if ((rl_free.low_reg != rl_keep.low_reg) && (rl_free.low_reg != rl_keep.high_reg) &&
497      (rl_free.high_reg != rl_keep.low_reg) && (rl_free.high_reg != rl_keep.high_reg)) {
498    // No overlap, free both
499    FreeTemp(rl_free.low_reg);
500    FreeTemp(rl_free.high_reg);
501  }
502}
503
504void X86Mir2Lir::SpillCoreRegs() {
505  if (num_core_spills_ == 0) {
506    return;
507  }
508  // Spill mask not including fake return address register
509  uint32_t mask = core_spill_mask_ & ~(1 << rRET);
510  int offset = frame_size_ - (4 * num_core_spills_);
511  for (int reg = 0; mask; mask >>= 1, reg++) {
512    if (mask & 0x1) {
513      StoreWordDisp(rX86_SP, offset, reg);
514      offset += 4;
515    }
516  }
517}
518
519void X86Mir2Lir::UnSpillCoreRegs() {
520  if (num_core_spills_ == 0) {
521    return;
522  }
523  // Spill mask not including fake return address register
524  uint32_t mask = core_spill_mask_ & ~(1 << rRET);
525  int offset = frame_size_ - (4 * num_core_spills_);
526  for (int reg = 0; mask; mask >>= 1, reg++) {
527    if (mask & 0x1) {
528      LoadWordDisp(rX86_SP, offset, reg);
529      offset += 4;
530    }
531  }
532}
533
534bool X86Mir2Lir::IsUnconditionalBranch(LIR* lir) {
535  return (lir->opcode == kX86Jmp8 || lir->opcode == kX86Jmp32);
536}
537
538X86Mir2Lir::X86Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena)
539    : Mir2Lir(cu, mir_graph, arena),
540      method_address_insns_(arena, 100, kGrowableArrayMisc),
541      class_type_address_insns_(arena, 100, kGrowableArrayMisc),
542      call_method_insns_(arena, 100, kGrowableArrayMisc),
543      stack_decrement_(nullptr), stack_increment_(nullptr) {
544  store_method_addr_used_ = false;
545  for (int i = 0; i < kX86Last; i++) {
546    if (X86Mir2Lir::EncodingMap[i].opcode != i) {
547      LOG(FATAL) << "Encoding order for " << X86Mir2Lir::EncodingMap[i].name
548                 << " is wrong: expecting " << i << ", seeing "
549                 << static_cast<int>(X86Mir2Lir::EncodingMap[i].opcode);
550    }
551  }
552}
553
554Mir2Lir* X86CodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph,
555                          ArenaAllocator* const arena) {
556  return new X86Mir2Lir(cu, mir_graph, arena);
557}
558
559// Not used in x86
560int X86Mir2Lir::LoadHelper(ThreadOffset offset) {
561  LOG(FATAL) << "Unexpected use of LoadHelper in x86";
562  return INVALID_REG;
563}
564
565uint64_t X86Mir2Lir::GetTargetInstFlags(int opcode) {
566  DCHECK(!IsPseudoLirOp(opcode));
567  return X86Mir2Lir::EncodingMap[opcode].flags;
568}
569
570const char* X86Mir2Lir::GetTargetInstName(int opcode) {
571  DCHECK(!IsPseudoLirOp(opcode));
572  return X86Mir2Lir::EncodingMap[opcode].name;
573}
574
575const char* X86Mir2Lir::GetTargetInstFmt(int opcode) {
576  DCHECK(!IsPseudoLirOp(opcode));
577  return X86Mir2Lir::EncodingMap[opcode].fmt;
578}
579
580/*
581 * Return an updated location record with current in-register status.
582 * If the value lives in live temps, reflect that fact.  No code
583 * is generated.  If the live value is part of an older pair,
584 * clobber both low and high.
585 */
586// TODO: Reunify with common code after 'pair mess' has been fixed
587RegLocation X86Mir2Lir::UpdateLocWide(RegLocation loc) {
588  DCHECK(loc.wide);
589  DCHECK(CheckCorePoolSanity());
590  if (loc.location != kLocPhysReg) {
591    DCHECK((loc.location == kLocDalvikFrame) ||
592         (loc.location == kLocCompilerTemp));
593    // Are the dalvik regs already live in physical registers?
594    RegisterInfo* info_lo = AllocLive(loc.s_reg_low, kAnyReg);
595
596    // Handle FP registers specially on x86.
597    if (info_lo && IsFpReg(info_lo->reg)) {
598      bool match = true;
599
600      // We can't match a FP register with a pair of Core registers.
601      match = match && (info_lo->pair == 0);
602
603      if (match) {
604        // We can reuse;update the register usage info.
605        loc.low_reg = info_lo->reg;
606        loc.high_reg = info_lo->reg;  // Play nice with existing code.
607        loc.location = kLocPhysReg;
608        loc.vec_len = kVectorLength8;
609        DCHECK(IsFpReg(loc.low_reg));
610        return loc;
611      }
612      // We can't easily reuse; clobber and free any overlaps.
613      if (info_lo) {
614        Clobber(info_lo->reg);
615        FreeTemp(info_lo->reg);
616        if (info_lo->pair)
617          Clobber(info_lo->partner);
618      }
619    } else {
620      RegisterInfo* info_hi = AllocLive(GetSRegHi(loc.s_reg_low), kAnyReg);
621      bool match = true;
622      match = match && (info_lo != NULL);
623      match = match && (info_hi != NULL);
624      // Are they both core or both FP?
625      match = match && (IsFpReg(info_lo->reg) == IsFpReg(info_hi->reg));
626      // If a pair of floating point singles, are they properly aligned?
627      if (match && IsFpReg(info_lo->reg)) {
628        match &= ((info_lo->reg & 0x1) == 0);
629        match &= ((info_hi->reg - info_lo->reg) == 1);
630      }
631      // If previously used as a pair, it is the same pair?
632      if (match && (info_lo->pair || info_hi->pair)) {
633        match = (info_lo->pair == info_hi->pair);
634        match &= ((info_lo->reg == info_hi->partner) &&
635              (info_hi->reg == info_lo->partner));
636      }
637      if (match) {
638        // Can reuse - update the register usage info
639        loc.low_reg = info_lo->reg;
640        loc.high_reg = info_hi->reg;
641        loc.location = kLocPhysReg;
642        MarkPair(loc.low_reg, loc.high_reg);
643        DCHECK(!IsFpReg(loc.low_reg) || ((loc.low_reg & 0x1) == 0));
644        return loc;
645      }
646      // Can't easily reuse - clobber and free any overlaps
647      if (info_lo) {
648        Clobber(info_lo->reg);
649        FreeTemp(info_lo->reg);
650        if (info_lo->pair)
651          Clobber(info_lo->partner);
652      }
653      if (info_hi) {
654        Clobber(info_hi->reg);
655        FreeTemp(info_hi->reg);
656        if (info_hi->pair)
657          Clobber(info_hi->partner);
658      }
659    }
660  }
661  return loc;
662}
663
664// TODO: Reunify with common code after 'pair mess' has been fixed
665RegLocation X86Mir2Lir::EvalLocWide(RegLocation loc, int reg_class, bool update) {
666  DCHECK(loc.wide);
667  int32_t new_regs;
668  int32_t low_reg;
669  int32_t high_reg;
670
671  loc = UpdateLocWide(loc);
672
673  /* If it is already in a register, we can assume proper form.  Is it the right reg class? */
674  if (loc.location == kLocPhysReg) {
675    DCHECK_EQ(IsFpReg(loc.low_reg), loc.IsVectorScalar());
676    if (!RegClassMatches(reg_class, loc.low_reg)) {
677      /* It is the wrong register class.  Reallocate and copy. */
678      if (!IsFpReg(loc.low_reg)) {
679        // We want this in a FP reg, and it is in core registers.
680        DCHECK(reg_class != kCoreReg);
681        // Allocate this into any FP reg, and mark it with the right size.
682        low_reg = AllocTypedTemp(true, reg_class);
683        OpVectorRegCopyWide(low_reg, loc.low_reg, loc.high_reg);
684        CopyRegInfo(low_reg, loc.low_reg);
685        Clobber(loc.low_reg);
686        Clobber(loc.high_reg);
687        loc.low_reg = low_reg;
688        loc.high_reg = low_reg;  // Play nice with existing code.
689        loc.vec_len = kVectorLength8;
690      } else {
691        // The value is in a FP register, and we want it in a pair of core registers.
692        DCHECK_EQ(reg_class, kCoreReg);
693        DCHECK_EQ(loc.low_reg, loc.high_reg);
694        new_regs = AllocTypedTempPair(false, kCoreReg);  // Force to core registers.
695        low_reg = new_regs & 0xff;
696        high_reg = (new_regs >> 8) & 0xff;
697        DCHECK_NE(low_reg, high_reg);
698        OpRegCopyWide(low_reg, high_reg, loc.low_reg, loc.high_reg);
699        CopyRegInfo(low_reg, loc.low_reg);
700        CopyRegInfo(high_reg, loc.high_reg);
701        Clobber(loc.low_reg);
702        Clobber(loc.high_reg);
703        loc.low_reg = low_reg;
704        loc.high_reg = high_reg;
705        MarkPair(loc.low_reg, loc.high_reg);
706        DCHECK(!IsFpReg(loc.low_reg) || ((loc.low_reg & 0x1) == 0));
707      }
708    }
709    return loc;
710  }
711
712  DCHECK_NE(loc.s_reg_low, INVALID_SREG);
713  DCHECK_NE(GetSRegHi(loc.s_reg_low), INVALID_SREG);
714
715  new_regs = AllocTypedTempPair(loc.fp, reg_class);
716  loc.low_reg = new_regs & 0xff;
717  loc.high_reg = (new_regs >> 8) & 0xff;
718
719  if (loc.low_reg == loc.high_reg) {
720    DCHECK(IsFpReg(loc.low_reg));
721    loc.vec_len = kVectorLength8;
722  } else {
723    MarkPair(loc.low_reg, loc.high_reg);
724  }
725  if (update) {
726    loc.location = kLocPhysReg;
727    MarkLive(loc.low_reg, loc.s_reg_low);
728    if (loc.low_reg != loc.high_reg) {
729      MarkLive(loc.high_reg, GetSRegHi(loc.s_reg_low));
730    }
731  }
732  return loc;
733}
734
735// TODO: Reunify with common code after 'pair mess' has been fixed
736RegLocation X86Mir2Lir::EvalLoc(RegLocation loc, int reg_class, bool update) {
737  int new_reg;
738
739  if (loc.wide)
740    return EvalLocWide(loc, reg_class, update);
741
742  loc = UpdateLoc(loc);
743
744  if (loc.location == kLocPhysReg) {
745    if (!RegClassMatches(reg_class, loc.low_reg)) {
746      /* Wrong register class.  Realloc, copy and transfer ownership. */
747      new_reg = AllocTypedTemp(loc.fp, reg_class);
748      OpRegCopy(new_reg, loc.low_reg);
749      CopyRegInfo(new_reg, loc.low_reg);
750      Clobber(loc.low_reg);
751      loc.low_reg = new_reg;
752      if (IsFpReg(loc.low_reg) && reg_class != kCoreReg)
753        loc.vec_len = kVectorLength4;
754    }
755    return loc;
756  }
757
758  DCHECK_NE(loc.s_reg_low, INVALID_SREG);
759
760  new_reg = AllocTypedTemp(loc.fp, reg_class);
761  loc.low_reg = new_reg;
762  if (IsFpReg(loc.low_reg) && reg_class != kCoreReg)
763    loc.vec_len = kVectorLength4;
764
765  if (update) {
766    loc.location = kLocPhysReg;
767    MarkLive(loc.low_reg, loc.s_reg_low);
768  }
769  return loc;
770}
771
772int X86Mir2Lir::AllocTempDouble() {
773  // We really don't need a pair of registers.
774  return AllocTempFloat();
775}
776
777// TODO: Reunify with common code after 'pair mess' has been fixed
778void X86Mir2Lir::ResetDefLocWide(RegLocation rl) {
779  DCHECK(rl.wide);
780  RegisterInfo* p_low = IsTemp(rl.low_reg);
781  if (IsFpReg(rl.low_reg)) {
782    // We are using only the low register.
783    if (p_low && !(cu_->disable_opt & (1 << kSuppressLoads))) {
784      NullifyRange(p_low->def_start, p_low->def_end, p_low->s_reg, rl.s_reg_low);
785    }
786    ResetDef(rl.low_reg);
787  } else {
788    RegisterInfo* p_high = IsTemp(rl.high_reg);
789    if (p_low && !(cu_->disable_opt & (1 << kSuppressLoads))) {
790      DCHECK(p_low->pair);
791      NullifyRange(p_low->def_start, p_low->def_end, p_low->s_reg, rl.s_reg_low);
792    }
793    if (p_high && !(cu_->disable_opt & (1 << kSuppressLoads))) {
794      DCHECK(p_high->pair);
795    }
796    ResetDef(rl.low_reg);
797    ResetDef(rl.high_reg);
798  }
799}
800
801void X86Mir2Lir::GenConstWide(RegLocation rl_dest, int64_t value) {
802  // Can we do this directly to memory?
803  rl_dest = UpdateLocWide(rl_dest);
804  if ((rl_dest.location == kLocDalvikFrame) ||
805      (rl_dest.location == kLocCompilerTemp)) {
806    int32_t val_lo = Low32Bits(value);
807    int32_t val_hi = High32Bits(value);
808    int rBase = TargetReg(kSp);
809    int displacement = SRegOffset(rl_dest.s_reg_low);
810
811    LIR * store = NewLIR3(kX86Mov32MI, rBase, displacement + LOWORD_OFFSET, val_lo);
812    AnnotateDalvikRegAccess(store, (displacement + LOWORD_OFFSET) >> 2,
813                              false /* is_load */, true /* is64bit */);
814    store = NewLIR3(kX86Mov32MI, rBase, displacement + HIWORD_OFFSET, val_hi);
815    AnnotateDalvikRegAccess(store, (displacement + HIWORD_OFFSET) >> 2,
816                              false /* is_load */, true /* is64bit */);
817    return;
818  }
819
820  // Just use the standard code to do the generation.
821  Mir2Lir::GenConstWide(rl_dest, value);
822}
823
824// TODO: Merge with existing RegLocation dumper in vreg_analysis.cc
825void X86Mir2Lir::DumpRegLocation(RegLocation loc) {
826  LOG(INFO)  << "location: " << loc.location << ','
827             << (loc.wide ? " w" : "  ")
828             << (loc.defined ? " D" : "  ")
829             << (loc.is_const ? " c" : "  ")
830             << (loc.fp ? " F" : "  ")
831             << (loc.core ? " C" : "  ")
832             << (loc.ref ? " r" : "  ")
833             << (loc.high_word ? " h" : "  ")
834             << (loc.home ? " H" : "  ")
835             << " vec_len: " << loc.vec_len
836             << ", low: " << static_cast<int>(loc.low_reg)
837             << ", high: " << static_cast<int>(loc.high_reg)
838             << ", s_reg: " << loc.s_reg_low
839             << ", orig: " << loc.orig_sreg;
840}
841
842void X86Mir2Lir::Materialize() {
843  // A good place to put the analysis before starting.
844  AnalyzeMIR();
845
846  // Now continue with regular code generation.
847  Mir2Lir::Materialize();
848}
849
850void X86Mir2Lir::LoadMethodAddress(int dex_method_index, InvokeType type,
851                                   SpecialTargetRegister symbolic_reg) {
852  /*
853   * For x86, just generate a 32 bit move immediate instruction, that will be filled
854   * in at 'link time'.  For now, put a unique value based on target to ensure that
855   * code deduplication works.
856   */
857  const DexFile::MethodId& id = cu_->dex_file->GetMethodId(dex_method_index);
858  uintptr_t ptr = reinterpret_cast<uintptr_t>(&id);
859
860  // Generate the move instruction with the unique pointer and save index and type.
861  LIR *move = RawLIR(current_dalvik_offset_, kX86Mov32RI, TargetReg(symbolic_reg),
862                     static_cast<int>(ptr), dex_method_index, type);
863  AppendLIR(move);
864  method_address_insns_.Insert(move);
865}
866
867void X86Mir2Lir::LoadClassType(uint32_t type_idx, SpecialTargetRegister symbolic_reg) {
868  /*
869   * For x86, just generate a 32 bit move immediate instruction, that will be filled
870   * in at 'link time'.  For now, put a unique value based on target to ensure that
871   * code deduplication works.
872   */
873  const DexFile::TypeId& id = cu_->dex_file->GetTypeId(type_idx);
874  uintptr_t ptr = reinterpret_cast<uintptr_t>(&id);
875
876  // Generate the move instruction with the unique pointer and save index and type.
877  LIR *move = RawLIR(current_dalvik_offset_, kX86Mov32RI, TargetReg(symbolic_reg),
878                     static_cast<int>(ptr), type_idx);
879  AppendLIR(move);
880  class_type_address_insns_.Insert(move);
881}
882
883LIR *X86Mir2Lir::CallWithLinkerFixup(int dex_method_index, InvokeType type) {
884  /*
885   * For x86, just generate a 32 bit call relative instruction, that will be filled
886   * in at 'link time'.  For now, put a unique value based on target to ensure that
887   * code deduplication works.
888   */
889  const DexFile::MethodId& id = cu_->dex_file->GetMethodId(dex_method_index);
890  uintptr_t ptr = reinterpret_cast<uintptr_t>(&id);
891
892  // Generate the call instruction with the unique pointer and save index and type.
893  LIR *call = RawLIR(current_dalvik_offset_, kX86CallI, static_cast<int>(ptr), dex_method_index,
894                     type);
895  AppendLIR(call);
896  call_method_insns_.Insert(call);
897  return call;
898}
899
900void X86Mir2Lir::InstallLiteralPools() {
901  // These are handled differently for x86.
902  DCHECK(code_literal_list_ == nullptr);
903  DCHECK(method_literal_list_ == nullptr);
904  DCHECK(class_literal_list_ == nullptr);
905
906  // Handle the fixups for methods.
907  for (uint32_t i = 0; i < method_address_insns_.Size(); i++) {
908      LIR* p = method_address_insns_.Get(i);
909      DCHECK_EQ(p->opcode, kX86Mov32RI);
910      uint32_t target = p->operands[2];
911
912      // The offset to patch is the last 4 bytes of the instruction.
913      int patch_offset = p->offset + p->flags.size - 4;
914      cu_->compiler_driver->AddMethodPatch(cu_->dex_file, cu_->class_def_idx,
915                                           cu_->method_idx, cu_->invoke_type,
916                                           target, static_cast<InvokeType>(p->operands[3]),
917                                           patch_offset);
918  }
919
920  // Handle the fixups for class types.
921  for (uint32_t i = 0; i < class_type_address_insns_.Size(); i++) {
922      LIR* p = class_type_address_insns_.Get(i);
923      DCHECK_EQ(p->opcode, kX86Mov32RI);
924      uint32_t target = p->operands[2];
925
926      // The offset to patch is the last 4 bytes of the instruction.
927      int patch_offset = p->offset + p->flags.size - 4;
928      cu_->compiler_driver->AddClassPatch(cu_->dex_file, cu_->class_def_idx,
929                                          cu_->method_idx, target, patch_offset);
930  }
931
932  // And now the PC-relative calls to methods.
933  for (uint32_t i = 0; i < call_method_insns_.Size(); i++) {
934      LIR* p = call_method_insns_.Get(i);
935      DCHECK_EQ(p->opcode, kX86CallI);
936      uint32_t target = p->operands[1];
937
938      // The offset to patch is the last 4 bytes of the instruction.
939      int patch_offset = p->offset + p->flags.size - 4;
940      cu_->compiler_driver->AddRelativeCodePatch(cu_->dex_file, cu_->class_def_idx,
941                                                 cu_->method_idx, cu_->invoke_type, target,
942                                                 static_cast<InvokeType>(p->operands[2]),
943                                                 patch_offset, -4 /* offset */);
944  }
945
946  // And do the normal processing.
947  Mir2Lir::InstallLiteralPools();
948}
949
950/*
951 * Fast string.index_of(I) & (II).  Inline check for simple case of char <= 0xffff,
952 * otherwise bails to standard library code.
953 */
954bool X86Mir2Lir::GenInlinedIndexOf(CallInfo* info, bool zero_based) {
955  ClobberCallerSave();
956  LockCallTemps();  // Using fixed registers
957
958  // EAX: 16 bit character being searched.
959  // ECX: count: number of words to be searched.
960  // EDI: String being searched.
961  // EDX: temporary during execution.
962  // EBX: temporary during execution.
963
964  RegLocation rl_obj = info->args[0];
965  RegLocation rl_char = info->args[1];
966  RegLocation rl_start = info->args[2];
967
968  uint32_t char_value =
969    rl_char.is_const ? mir_graph_->ConstantValue(rl_char.orig_sreg) : 0;
970
971  if (char_value > 0xFFFF) {
972    // We have to punt to the real String.indexOf.
973    return false;
974  }
975
976  // Okay, we are commited to inlining this.
977  RegLocation rl_return = GetReturn(false);
978  RegLocation rl_dest = InlineTarget(info);
979
980  // Is the string non-NULL?
981  LoadValueDirectFixed(rl_obj, rDX);
982  GenNullCheck(rl_obj.s_reg_low, rDX, info->opt_flags);
983
984  // Record that we have inlined & null checked the object.
985  info->opt_flags |= (MIR_INLINED | MIR_IGNORE_NULL_CHECK);
986
987  // Does the character fit in 16 bits?
988  LIR* launch_pad = nullptr;
989  if (rl_char.is_const) {
990    // We need the value in EAX.
991    LoadConstantNoClobber(rAX, char_value);
992  } else {
993    // Character is not a constant; compare at runtime.
994    LoadValueDirectFixed(rl_char, rAX);
995    launch_pad = RawLIR(0, kPseudoIntrinsicRetry, WrapPointer(info));
996    intrinsic_launchpads_.Insert(launch_pad);
997    OpCmpImmBranch(kCondGt, rAX, 0xFFFF, launch_pad);
998  }
999
1000  // From here down, we know that we are looking for a char that fits in 16 bits.
1001  // Location of reference to data array within the String object.
1002  int value_offset = mirror::String::ValueOffset().Int32Value();
1003  // Location of count within the String object.
1004  int count_offset = mirror::String::CountOffset().Int32Value();
1005  // Starting offset within data array.
1006  int offset_offset = mirror::String::OffsetOffset().Int32Value();
1007  // Start of char data with array_.
1008  int data_offset = mirror::Array::DataOffset(sizeof(uint16_t)).Int32Value();
1009
1010  // Character is in EAX.
1011  // Object pointer is in EDX.
1012
1013  // We need to preserve EDI, but have no spare registers, so push it on the stack.
1014  // We have to remember that all stack addresses after this are offset by sizeof(EDI).
1015  NewLIR1(kX86Push32R, rDI);
1016
1017  // Compute the number of words to search in to rCX.
1018  LoadWordDisp(rDX, count_offset, rCX);
1019  LIR *length_compare = nullptr;
1020  int start_value = 0;
1021  if (zero_based) {
1022    // We have to handle an empty string.  Use special instruction JECXZ.
1023    length_compare = NewLIR0(kX86Jecxz8);
1024  } else {
1025    // We have to offset by the start index.
1026    if (rl_start.is_const) {
1027      start_value = mir_graph_->ConstantValue(rl_start.orig_sreg);
1028      start_value = std::max(start_value, 0);
1029
1030      // Is the start > count?
1031      length_compare = OpCmpImmBranch(kCondLe, rCX, start_value, nullptr);
1032
1033      if (start_value != 0) {
1034        OpRegImm(kOpSub, rCX, start_value);
1035      }
1036    } else {
1037      // Runtime start index.
1038      rl_start = UpdateLoc(rl_start);
1039      if (rl_start.location == kLocPhysReg) {
1040        length_compare = OpCmpBranch(kCondLe, rCX, rl_start.low_reg, nullptr);
1041        OpRegReg(kOpSub, rCX, rl_start.low_reg);
1042      } else {
1043        // Compare to memory to avoid a register load.  Handle pushed EDI.
1044        int displacement = SRegOffset(rl_start.s_reg_low) + sizeof(uint32_t);
1045        OpRegMem(kOpCmp, rDX, rX86_SP, displacement);
1046        length_compare = NewLIR2(kX86Jcc8, 0, kX86CondLe);
1047        OpRegMem(kOpSub, rCX, rX86_SP, displacement);
1048      }
1049    }
1050  }
1051  DCHECK(length_compare != nullptr);
1052
1053  // ECX now contains the count in words to be searched.
1054
1055  // Load the address of the string into EBX.
1056  // The string starts at VALUE(String) + 2 * OFFSET(String) + DATA_OFFSET.
1057  LoadWordDisp(rDX, value_offset, rDI);
1058  LoadWordDisp(rDX, offset_offset, rBX);
1059  OpLea(rBX, rDI, rBX, 1, data_offset);
1060
1061  // Now compute into EDI where the search will start.
1062  if (zero_based || rl_start.is_const) {
1063    if (start_value == 0) {
1064      OpRegCopy(rDI, rBX);
1065    } else {
1066      NewLIR3(kX86Lea32RM, rDI, rBX, 2 * start_value);
1067    }
1068  } else {
1069    if (rl_start.location == kLocPhysReg) {
1070      if (rl_start.low_reg == rDI) {
1071        // We have a slight problem here.  We are already using RDI!
1072        // Grab the value from the stack.
1073        LoadWordDisp(rX86_SP, 0, rDX);
1074        OpLea(rDI, rBX, rDX, 1, 0);
1075      } else {
1076        OpLea(rDI, rBX, rl_start.low_reg, 1, 0);
1077      }
1078    } else {
1079      OpRegCopy(rDI, rBX);
1080      // Load the start index from stack, remembering that we pushed EDI.
1081      int displacement = SRegOffset(rl_start.s_reg_low) + sizeof(uint32_t);
1082      LoadWordDisp(rX86_SP, displacement, rDX);
1083      OpLea(rDI, rBX, rDX, 1, 0);
1084    }
1085  }
1086
1087  // EDI now contains the start of the string to be searched.
1088  // We are all prepared to do the search for the character.
1089  NewLIR0(kX86RepneScasw);
1090
1091  // Did we find a match?
1092  LIR* failed_branch = OpCondBranch(kCondNe, nullptr);
1093
1094  // yes, we matched.  Compute the index of the result.
1095  // index = ((curr_ptr - orig_ptr) / 2) - 1.
1096  OpRegReg(kOpSub, rDI, rBX);
1097  OpRegImm(kOpAsr, rDI, 1);
1098  NewLIR3(kX86Lea32RM, rl_return.low_reg, rDI, -1);
1099  LIR *all_done = NewLIR1(kX86Jmp8, 0);
1100
1101  // Failed to match; return -1.
1102  LIR *not_found = NewLIR0(kPseudoTargetLabel);
1103  length_compare->target = not_found;
1104  failed_branch->target = not_found;
1105  LoadConstantNoClobber(rl_return.low_reg, -1);
1106
1107  // And join up at the end.
1108  all_done->target = NewLIR0(kPseudoTargetLabel);
1109  // Restore EDI from the stack.
1110  NewLIR1(kX86Pop32R, rDI);
1111
1112  // Out of line code returns here.
1113  if (launch_pad != nullptr) {
1114    LIR *return_point = NewLIR0(kPseudoTargetLabel);
1115    launch_pad->operands[2] = WrapPointer(return_point);
1116  }
1117
1118  StoreValue(rl_dest, rl_return);
1119  return true;
1120}
1121
1122/*
1123 * @brief Enter a 32 bit quantity into the FDE buffer
1124 * @param buf FDE buffer.
1125 * @param data Data value.
1126 */
1127static void PushWord(std::vector<uint8_t>&buf, int data) {
1128  buf.push_back(data & 0xff);
1129  buf.push_back((data >> 8) & 0xff);
1130  buf.push_back((data >> 16) & 0xff);
1131  buf.push_back((data >> 24) & 0xff);
1132}
1133
1134/*
1135 * @brief Enter an 'advance LOC' into the FDE buffer
1136 * @param buf FDE buffer.
1137 * @param increment Amount by which to increase the current location.
1138 */
1139static void AdvanceLoc(std::vector<uint8_t>&buf, uint32_t increment) {
1140  if (increment < 64) {
1141    // Encoding in opcode.
1142    buf.push_back(0x1 << 6 | increment);
1143  } else if (increment < 256) {
1144    // Single byte delta.
1145    buf.push_back(0x02);
1146    buf.push_back(increment);
1147  } else if (increment < 256 * 256) {
1148    // Two byte delta.
1149    buf.push_back(0x03);
1150    buf.push_back(increment & 0xff);
1151    buf.push_back((increment >> 8) & 0xff);
1152  } else {
1153    // Four byte delta.
1154    buf.push_back(0x04);
1155    PushWord(buf, increment);
1156  }
1157}
1158
1159
1160std::vector<uint8_t>* X86CFIInitialization() {
1161  return X86Mir2Lir::ReturnCommonCallFrameInformation();
1162}
1163
1164std::vector<uint8_t>* X86Mir2Lir::ReturnCommonCallFrameInformation() {
1165  std::vector<uint8_t>*cfi_info = new std::vector<uint8_t>;
1166
1167  // Length of the CIE (except for this field).
1168  PushWord(*cfi_info, 16);
1169
1170  // CIE id.
1171  PushWord(*cfi_info, 0xFFFFFFFFU);
1172
1173  // Version: 3.
1174  cfi_info->push_back(0x03);
1175
1176  // Augmentation: empty string.
1177  cfi_info->push_back(0x0);
1178
1179  // Code alignment: 1.
1180  cfi_info->push_back(0x01);
1181
1182  // Data alignment: -4.
1183  cfi_info->push_back(0x7C);
1184
1185  // Return address register (R8).
1186  cfi_info->push_back(0x08);
1187
1188  // Initial return PC is 4(ESP): DW_CFA_def_cfa R4 4.
1189  cfi_info->push_back(0x0C);
1190  cfi_info->push_back(0x04);
1191  cfi_info->push_back(0x04);
1192
1193  // Return address location: 0(SP): DW_CFA_offset R8 1 (* -4);.
1194  cfi_info->push_back(0x2 << 6 | 0x08);
1195  cfi_info->push_back(0x01);
1196
1197  // And 2 Noops to align to 4 byte boundary.
1198  cfi_info->push_back(0x0);
1199  cfi_info->push_back(0x0);
1200
1201  DCHECK_EQ(cfi_info->size() & 3, 0U);
1202  return cfi_info;
1203}
1204
1205static void EncodeUnsignedLeb128(std::vector<uint8_t>& buf, uint32_t value) {
1206  uint8_t buffer[12];
1207  uint8_t *ptr = EncodeUnsignedLeb128(buffer, value);
1208  for (uint8_t *p = buffer; p < ptr; p++) {
1209    buf.push_back(*p);
1210  }
1211}
1212
1213std::vector<uint8_t>* X86Mir2Lir::ReturnCallFrameInformation() {
1214  std::vector<uint8_t>*cfi_info = new std::vector<uint8_t>;
1215
1216  // Generate the FDE for the method.
1217  DCHECK_NE(data_offset_, 0U);
1218
1219  // Length (will be filled in later in this routine).
1220  PushWord(*cfi_info, 0);
1221
1222  // CIE_pointer (can be filled in by linker); might be left at 0 if there is only
1223  // one CIE for the whole debug_frame section.
1224  PushWord(*cfi_info, 0);
1225
1226  // 'initial_location' (filled in by linker).
1227  PushWord(*cfi_info, 0);
1228
1229  // 'address_range' (number of bytes in the method).
1230  PushWord(*cfi_info, data_offset_);
1231
1232  // The instructions in the FDE.
1233  if (stack_decrement_ != nullptr) {
1234    // Advance LOC to just past the stack decrement.
1235    uint32_t pc = NEXT_LIR(stack_decrement_)->offset;
1236    AdvanceLoc(*cfi_info, pc);
1237
1238    // Now update the offset to the call frame: DW_CFA_def_cfa_offset frame_size.
1239    cfi_info->push_back(0x0e);
1240    EncodeUnsignedLeb128(*cfi_info, frame_size_);
1241
1242    // We continue with that stack until the epilogue.
1243    if (stack_increment_ != nullptr) {
1244      uint32_t new_pc = NEXT_LIR(stack_increment_)->offset;
1245      AdvanceLoc(*cfi_info, new_pc - pc);
1246
1247      // We probably have code snippets after the epilogue, so save the
1248      // current state: DW_CFA_remember_state.
1249      cfi_info->push_back(0x0a);
1250
1251      // We have now popped the stack: DW_CFA_def_cfa_offset 4.  There is only the return
1252      // PC on the stack now.
1253      cfi_info->push_back(0x0e);
1254      EncodeUnsignedLeb128(*cfi_info, 4);
1255
1256      // Everything after that is the same as before the epilogue.
1257      // Stack bump was followed by RET instruction.
1258      LIR *post_ret_insn = NEXT_LIR(NEXT_LIR(stack_increment_));
1259      if (post_ret_insn != nullptr) {
1260        pc = new_pc;
1261        new_pc = post_ret_insn->offset;
1262        AdvanceLoc(*cfi_info, new_pc - pc);
1263        // Restore the state: DW_CFA_restore_state.
1264        cfi_info->push_back(0x0b);
1265      }
1266    }
1267  }
1268
1269  // Padding to a multiple of 4
1270  while ((cfi_info->size() & 3) != 0) {
1271    // DW_CFA_nop is encoded as 0.
1272    cfi_info->push_back(0);
1273  }
1274
1275  // Set the length of the FDE inside the generated bytes.
1276  uint32_t length = cfi_info->size() - 4;
1277  (*cfi_info)[0] = length;
1278  (*cfi_info)[1] = length >> 8;
1279  (*cfi_info)[2] = length >> 16;
1280  (*cfi_info)[3] = length >> 24;
1281  return cfi_info;
1282}
1283
1284}  // namespace art
1285