target_x86.cc revision b373e091eac39b1a79c11f2dcbd610af01e9e8a9
1/* 2 * Copyright (C) 2012 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#include <string> 18#include <inttypes.h> 19 20#include "codegen_x86.h" 21#include "dex/compiler_internals.h" 22#include "dex/quick/mir_to_lir-inl.h" 23#include "mirror/array.h" 24#include "mirror/string.h" 25#include "x86_lir.h" 26 27namespace art { 28 29// FIXME: restore "static" when usage uncovered 30/*static*/ int core_regs[] = { 31 rAX, rCX, rDX, rBX, rX86_SP, rBP, rSI, rDI 32#ifdef TARGET_REX_SUPPORT 33 r8, r9, r10, r11, r12, r13, r14, 15 34#endif 35}; 36/*static*/ int ReservedRegs[] = {rX86_SP}; 37/*static*/ int core_temps[] = {rAX, rCX, rDX, rBX}; 38/*static*/ int FpRegs[] = { 39 fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7, 40#ifdef TARGET_REX_SUPPORT 41 fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15 42#endif 43}; 44/*static*/ int fp_temps[] = { 45 fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7, 46#ifdef TARGET_REX_SUPPORT 47 fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15 48#endif 49}; 50 51RegLocation X86Mir2Lir::LocCReturn() { 52 return x86_loc_c_return; 53} 54 55RegLocation X86Mir2Lir::LocCReturnWide() { 56 return x86_loc_c_return_wide; 57} 58 59RegLocation X86Mir2Lir::LocCReturnFloat() { 60 return x86_loc_c_return_float; 61} 62 63RegLocation X86Mir2Lir::LocCReturnDouble() { 64 return x86_loc_c_return_double; 65} 66 67// Return a target-dependent special register. 68int X86Mir2Lir::TargetReg(SpecialTargetRegister reg) { 69 int res = INVALID_REG; 70 switch (reg) { 71 case kSelf: res = rX86_SELF; break; 72 case kSuspend: res = rX86_SUSPEND; break; 73 case kLr: res = rX86_LR; break; 74 case kPc: res = rX86_PC; break; 75 case kSp: res = rX86_SP; break; 76 case kArg0: res = rX86_ARG0; break; 77 case kArg1: res = rX86_ARG1; break; 78 case kArg2: res = rX86_ARG2; break; 79 case kArg3: res = rX86_ARG3; break; 80 case kFArg0: res = rX86_FARG0; break; 81 case kFArg1: res = rX86_FARG1; break; 82 case kFArg2: res = rX86_FARG2; break; 83 case kFArg3: res = rX86_FARG3; break; 84 case kRet0: res = rX86_RET0; break; 85 case kRet1: res = rX86_RET1; break; 86 case kInvokeTgt: res = rX86_INVOKE_TGT; break; 87 case kHiddenArg: res = rAX; break; 88 case kHiddenFpArg: res = fr0; break; 89 case kCount: res = rX86_COUNT; break; 90 } 91 return res; 92} 93 94int X86Mir2Lir::GetArgMappingToPhysicalReg(int arg_num) { 95 // For the 32-bit internal ABI, the first 3 arguments are passed in registers. 96 // TODO: This is not 64-bit compliant and depends on new internal ABI. 97 switch (arg_num) { 98 case 0: 99 return rX86_ARG1; 100 case 1: 101 return rX86_ARG2; 102 case 2: 103 return rX86_ARG3; 104 default: 105 return INVALID_REG; 106 } 107} 108 109// Create a double from a pair of singles. 110int X86Mir2Lir::S2d(int low_reg, int high_reg) { 111 return X86_S2D(low_reg, high_reg); 112} 113 114// Return mask to strip off fp reg flags and bias. 115uint32_t X86Mir2Lir::FpRegMask() { 116 return X86_FP_REG_MASK; 117} 118 119// True if both regs single, both core or both double. 120bool X86Mir2Lir::SameRegType(int reg1, int reg2) { 121 return (X86_REGTYPE(reg1) == X86_REGTYPE(reg2)); 122} 123 124/* 125 * Decode the register id. 126 */ 127uint64_t X86Mir2Lir::GetRegMaskCommon(int reg) { 128 uint64_t seed; 129 int shift; 130 int reg_id; 131 132 reg_id = reg & 0xf; 133 /* Double registers in x86 are just a single FP register */ 134 seed = 1; 135 /* FP register starts at bit position 16 */ 136 shift = X86_FPREG(reg) ? kX86FPReg0 : 0; 137 /* Expand the double register id into single offset */ 138 shift += reg_id; 139 return (seed << shift); 140} 141 142uint64_t X86Mir2Lir::GetPCUseDefEncoding() { 143 /* 144 * FIXME: might make sense to use a virtual resource encoding bit for pc. Might be 145 * able to clean up some of the x86/Arm_Mips differences 146 */ 147 LOG(FATAL) << "Unexpected call to GetPCUseDefEncoding for x86"; 148 return 0ULL; 149} 150 151void X86Mir2Lir::SetupTargetResourceMasks(LIR* lir, uint64_t flags) { 152 DCHECK_EQ(cu_->instruction_set, kX86); 153 DCHECK(!lir->flags.use_def_invalid); 154 155 // X86-specific resource map setup here. 156 if (flags & REG_USE_SP) { 157 lir->u.m.use_mask |= ENCODE_X86_REG_SP; 158 } 159 160 if (flags & REG_DEF_SP) { 161 lir->u.m.def_mask |= ENCODE_X86_REG_SP; 162 } 163 164 if (flags & REG_DEFA) { 165 SetupRegMask(&lir->u.m.def_mask, rAX); 166 } 167 168 if (flags & REG_DEFD) { 169 SetupRegMask(&lir->u.m.def_mask, rDX); 170 } 171 if (flags & REG_USEA) { 172 SetupRegMask(&lir->u.m.use_mask, rAX); 173 } 174 175 if (flags & REG_USEC) { 176 SetupRegMask(&lir->u.m.use_mask, rCX); 177 } 178 179 if (flags & REG_USED) { 180 SetupRegMask(&lir->u.m.use_mask, rDX); 181 } 182 183 if (flags & REG_USEB) { 184 SetupRegMask(&lir->u.m.use_mask, rBX); 185 } 186 187 // Fixup hard to describe instruction: Uses rAX, rCX, rDI; sets rDI. 188 if (lir->opcode == kX86RepneScasw) { 189 SetupRegMask(&lir->u.m.use_mask, rAX); 190 SetupRegMask(&lir->u.m.use_mask, rCX); 191 SetupRegMask(&lir->u.m.use_mask, rDI); 192 SetupRegMask(&lir->u.m.def_mask, rDI); 193 } 194} 195 196/* For dumping instructions */ 197static const char* x86RegName[] = { 198 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", 199 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" 200}; 201 202static const char* x86CondName[] = { 203 "O", 204 "NO", 205 "B/NAE/C", 206 "NB/AE/NC", 207 "Z/EQ", 208 "NZ/NE", 209 "BE/NA", 210 "NBE/A", 211 "S", 212 "NS", 213 "P/PE", 214 "NP/PO", 215 "L/NGE", 216 "NL/GE", 217 "LE/NG", 218 "NLE/G" 219}; 220 221/* 222 * Interpret a format string and build a string no longer than size 223 * See format key in Assemble.cc. 224 */ 225std::string X86Mir2Lir::BuildInsnString(const char *fmt, LIR *lir, unsigned char* base_addr) { 226 std::string buf; 227 size_t i = 0; 228 size_t fmt_len = strlen(fmt); 229 while (i < fmt_len) { 230 if (fmt[i] != '!') { 231 buf += fmt[i]; 232 i++; 233 } else { 234 i++; 235 DCHECK_LT(i, fmt_len); 236 char operand_number_ch = fmt[i]; 237 i++; 238 if (operand_number_ch == '!') { 239 buf += "!"; 240 } else { 241 int operand_number = operand_number_ch - '0'; 242 DCHECK_LT(operand_number, 6); // Expect upto 6 LIR operands. 243 DCHECK_LT(i, fmt_len); 244 int operand = lir->operands[operand_number]; 245 switch (fmt[i]) { 246 case 'c': 247 DCHECK_LT(static_cast<size_t>(operand), sizeof(x86CondName)); 248 buf += x86CondName[operand]; 249 break; 250 case 'd': 251 buf += StringPrintf("%d", operand); 252 break; 253 case 'p': { 254 EmbeddedData *tab_rec = reinterpret_cast<EmbeddedData*>(UnwrapPointer(operand)); 255 buf += StringPrintf("0x%08x", tab_rec->offset); 256 break; 257 } 258 case 'r': 259 if (X86_FPREG(operand) || X86_DOUBLEREG(operand)) { 260 int fp_reg = operand & X86_FP_REG_MASK; 261 buf += StringPrintf("xmm%d", fp_reg); 262 } else { 263 DCHECK_LT(static_cast<size_t>(operand), sizeof(x86RegName)); 264 buf += x86RegName[operand]; 265 } 266 break; 267 case 't': 268 buf += StringPrintf("0x%08" PRIxPTR " (L%p)", 269 reinterpret_cast<uintptr_t>(base_addr) + lir->offset + operand, 270 lir->target); 271 break; 272 default: 273 buf += StringPrintf("DecodeError '%c'", fmt[i]); 274 break; 275 } 276 i++; 277 } 278 } 279 } 280 return buf; 281} 282 283void X86Mir2Lir::DumpResourceMask(LIR *x86LIR, uint64_t mask, const char *prefix) { 284 char buf[256]; 285 buf[0] = 0; 286 287 if (mask == ENCODE_ALL) { 288 strcpy(buf, "all"); 289 } else { 290 char num[8]; 291 int i; 292 293 for (i = 0; i < kX86RegEnd; i++) { 294 if (mask & (1ULL << i)) { 295 snprintf(num, arraysize(num), "%d ", i); 296 strcat(buf, num); 297 } 298 } 299 300 if (mask & ENCODE_CCODE) { 301 strcat(buf, "cc "); 302 } 303 /* Memory bits */ 304 if (x86LIR && (mask & ENCODE_DALVIK_REG)) { 305 snprintf(buf + strlen(buf), arraysize(buf) - strlen(buf), "dr%d%s", 306 DECODE_ALIAS_INFO_REG(x86LIR->flags.alias_info), 307 (DECODE_ALIAS_INFO_WIDE(x86LIR->flags.alias_info)) ? "(+1)" : ""); 308 } 309 if (mask & ENCODE_LITERAL) { 310 strcat(buf, "lit "); 311 } 312 313 if (mask & ENCODE_HEAP_REF) { 314 strcat(buf, "heap "); 315 } 316 if (mask & ENCODE_MUST_NOT_ALIAS) { 317 strcat(buf, "noalias "); 318 } 319 } 320 if (buf[0]) { 321 LOG(INFO) << prefix << ": " << buf; 322 } 323} 324 325void X86Mir2Lir::AdjustSpillMask() { 326 // Adjustment for LR spilling, x86 has no LR so nothing to do here 327 core_spill_mask_ |= (1 << rRET); 328 num_core_spills_++; 329} 330 331/* 332 * Mark a callee-save fp register as promoted. Note that 333 * vpush/vpop uses contiguous register lists so we must 334 * include any holes in the mask. Associate holes with 335 * Dalvik register INVALID_VREG (0xFFFFU). 336 */ 337void X86Mir2Lir::MarkPreservedSingle(int v_reg, int reg) { 338 UNIMPLEMENTED(WARNING) << "MarkPreservedSingle"; 339#if 0 340 LOG(FATAL) << "No support yet for promoted FP regs"; 341#endif 342} 343 344void X86Mir2Lir::FlushRegWide(int reg1, int reg2) { 345 RegisterInfo* info1 = GetRegInfo(reg1); 346 RegisterInfo* info2 = GetRegInfo(reg2); 347 DCHECK(info1 && info2 && info1->pair && info2->pair && 348 (info1->partner == info2->reg) && 349 (info2->partner == info1->reg)); 350 if ((info1->live && info1->dirty) || (info2->live && info2->dirty)) { 351 if (!(info1->is_temp && info2->is_temp)) { 352 /* Should not happen. If it does, there's a problem in eval_loc */ 353 LOG(FATAL) << "Long half-temp, half-promoted"; 354 } 355 356 info1->dirty = false; 357 info2->dirty = false; 358 if (mir_graph_->SRegToVReg(info2->s_reg) < mir_graph_->SRegToVReg(info1->s_reg)) 359 info1 = info2; 360 int v_reg = mir_graph_->SRegToVReg(info1->s_reg); 361 StoreBaseDispWide(rX86_SP, VRegOffset(v_reg), info1->reg, info1->partner); 362 } 363} 364 365void X86Mir2Lir::FlushReg(int reg) { 366 RegisterInfo* info = GetRegInfo(reg); 367 if (info->live && info->dirty) { 368 info->dirty = false; 369 int v_reg = mir_graph_->SRegToVReg(info->s_reg); 370 StoreBaseDisp(rX86_SP, VRegOffset(v_reg), reg, kWord); 371 } 372} 373 374/* Give access to the target-dependent FP register encoding to common code */ 375bool X86Mir2Lir::IsFpReg(int reg) { 376 return X86_FPREG(reg); 377} 378 379/* Clobber all regs that might be used by an external C call */ 380void X86Mir2Lir::ClobberCallerSave() { 381 Clobber(rAX); 382 Clobber(rCX); 383 Clobber(rDX); 384 Clobber(rBX); 385} 386 387RegLocation X86Mir2Lir::GetReturnWideAlt() { 388 RegLocation res = LocCReturnWide(); 389 CHECK(res.reg.GetReg() == rAX); 390 CHECK(res.reg.GetHighReg() == rDX); 391 Clobber(rAX); 392 Clobber(rDX); 393 MarkInUse(rAX); 394 MarkInUse(rDX); 395 MarkPair(res.reg.GetReg(), res.reg.GetHighReg()); 396 return res; 397} 398 399RegLocation X86Mir2Lir::GetReturnAlt() { 400 RegLocation res = LocCReturn(); 401 res.reg.SetReg(rDX); 402 Clobber(rDX); 403 MarkInUse(rDX); 404 return res; 405} 406 407/* To be used when explicitly managing register use */ 408void X86Mir2Lir::LockCallTemps() { 409 LockTemp(rX86_ARG0); 410 LockTemp(rX86_ARG1); 411 LockTemp(rX86_ARG2); 412 LockTemp(rX86_ARG3); 413} 414 415/* To be used when explicitly managing register use */ 416void X86Mir2Lir::FreeCallTemps() { 417 FreeTemp(rX86_ARG0); 418 FreeTemp(rX86_ARG1); 419 FreeTemp(rX86_ARG2); 420 FreeTemp(rX86_ARG3); 421} 422 423void X86Mir2Lir::GenMemBarrier(MemBarrierKind barrier_kind) { 424#if ANDROID_SMP != 0 425 // TODO: optimize fences 426 NewLIR0(kX86Mfence); 427#endif 428} 429 430// Alloc a pair of core registers, or a double. 431RegStorage X86Mir2Lir::AllocTypedTempWide(bool fp_hint, int reg_class) { 432 int high_reg; 433 int low_reg; 434 435 if (((reg_class == kAnyReg) && fp_hint) || (reg_class == kFPReg)) { 436 low_reg = AllocTempDouble(); 437 high_reg = low_reg; // only one allocated! 438 // TODO: take advantage of 64-bit notation. 439 return RegStorage(RegStorage::k64BitPair, low_reg, high_reg); 440 } 441 low_reg = AllocTemp(); 442 high_reg = AllocTemp(); 443 return RegStorage(RegStorage::k64BitPair, low_reg, high_reg); 444} 445 446int X86Mir2Lir::AllocTypedTemp(bool fp_hint, int reg_class) { 447 if (((reg_class == kAnyReg) && fp_hint) || (reg_class == kFPReg)) { 448 return AllocTempFloat(); 449 } 450 return AllocTemp(); 451} 452 453void X86Mir2Lir::CompilerInitializeRegAlloc() { 454 int num_regs = sizeof(core_regs)/sizeof(*core_regs); 455 int num_reserved = sizeof(ReservedRegs)/sizeof(*ReservedRegs); 456 int num_temps = sizeof(core_temps)/sizeof(*core_temps); 457 int num_fp_regs = sizeof(FpRegs)/sizeof(*FpRegs); 458 int num_fp_temps = sizeof(fp_temps)/sizeof(*fp_temps); 459 reg_pool_ = static_cast<RegisterPool*>(arena_->Alloc(sizeof(*reg_pool_), 460 kArenaAllocRegAlloc)); 461 reg_pool_->num_core_regs = num_regs; 462 reg_pool_->core_regs = 463 static_cast<RegisterInfo*>(arena_->Alloc(num_regs * sizeof(*reg_pool_->core_regs), 464 kArenaAllocRegAlloc)); 465 reg_pool_->num_fp_regs = num_fp_regs; 466 reg_pool_->FPRegs = 467 static_cast<RegisterInfo *>(arena_->Alloc(num_fp_regs * sizeof(*reg_pool_->FPRegs), 468 kArenaAllocRegAlloc)); 469 CompilerInitPool(reg_pool_->core_regs, core_regs, reg_pool_->num_core_regs); 470 CompilerInitPool(reg_pool_->FPRegs, FpRegs, reg_pool_->num_fp_regs); 471 // Keep special registers from being allocated 472 for (int i = 0; i < num_reserved; i++) { 473 MarkInUse(ReservedRegs[i]); 474 } 475 // Mark temp regs - all others not in use can be used for promotion 476 for (int i = 0; i < num_temps; i++) { 477 MarkTemp(core_temps[i]); 478 } 479 for (int i = 0; i < num_fp_temps; i++) { 480 MarkTemp(fp_temps[i]); 481 } 482} 483 484void X86Mir2Lir::FreeRegLocTemps(RegLocation rl_keep, 485 RegLocation rl_free) { 486 if ((rl_free.reg.GetReg() != rl_keep.reg.GetReg()) && (rl_free.reg.GetReg() != rl_keep.reg.GetHighReg()) && 487 (rl_free.reg.GetHighReg() != rl_keep.reg.GetReg()) && (rl_free.reg.GetHighReg() != rl_keep.reg.GetHighReg())) { 488 // No overlap, free both 489 FreeTemp(rl_free.reg.GetReg()); 490 FreeTemp(rl_free.reg.GetHighReg()); 491 } 492} 493 494void X86Mir2Lir::SpillCoreRegs() { 495 if (num_core_spills_ == 0) { 496 return; 497 } 498 // Spill mask not including fake return address register 499 uint32_t mask = core_spill_mask_ & ~(1 << rRET); 500 int offset = frame_size_ - (4 * num_core_spills_); 501 for (int reg = 0; mask; mask >>= 1, reg++) { 502 if (mask & 0x1) { 503 StoreWordDisp(rX86_SP, offset, reg); 504 offset += 4; 505 } 506 } 507} 508 509void X86Mir2Lir::UnSpillCoreRegs() { 510 if (num_core_spills_ == 0) { 511 return; 512 } 513 // Spill mask not including fake return address register 514 uint32_t mask = core_spill_mask_ & ~(1 << rRET); 515 int offset = frame_size_ - (4 * num_core_spills_); 516 for (int reg = 0; mask; mask >>= 1, reg++) { 517 if (mask & 0x1) { 518 LoadWordDisp(rX86_SP, offset, reg); 519 offset += 4; 520 } 521 } 522} 523 524bool X86Mir2Lir::IsUnconditionalBranch(LIR* lir) { 525 return (lir->opcode == kX86Jmp8 || lir->opcode == kX86Jmp32); 526} 527 528X86Mir2Lir::X86Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena) 529 : Mir2Lir(cu, mir_graph, arena), 530 method_address_insns_(arena, 100, kGrowableArrayMisc), 531 class_type_address_insns_(arena, 100, kGrowableArrayMisc), 532 call_method_insns_(arena, 100, kGrowableArrayMisc), 533 stack_decrement_(nullptr), stack_increment_(nullptr) { 534 store_method_addr_used_ = false; 535 for (int i = 0; i < kX86Last; i++) { 536 if (X86Mir2Lir::EncodingMap[i].opcode != i) { 537 LOG(FATAL) << "Encoding order for " << X86Mir2Lir::EncodingMap[i].name 538 << " is wrong: expecting " << i << ", seeing " 539 << static_cast<int>(X86Mir2Lir::EncodingMap[i].opcode); 540 } 541 } 542} 543 544Mir2Lir* X86CodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, 545 ArenaAllocator* const arena) { 546 return new X86Mir2Lir(cu, mir_graph, arena); 547} 548 549// Not used in x86 550int X86Mir2Lir::LoadHelper(ThreadOffset offset) { 551 LOG(FATAL) << "Unexpected use of LoadHelper in x86"; 552 return INVALID_REG; 553} 554 555LIR* X86Mir2Lir::CheckSuspendUsingLoad() { 556 LOG(FATAL) << "Unexpected use of CheckSuspendUsingLoad in x86"; 557 return nullptr; 558} 559 560uint64_t X86Mir2Lir::GetTargetInstFlags(int opcode) { 561 DCHECK(!IsPseudoLirOp(opcode)); 562 return X86Mir2Lir::EncodingMap[opcode].flags; 563} 564 565const char* X86Mir2Lir::GetTargetInstName(int opcode) { 566 DCHECK(!IsPseudoLirOp(opcode)); 567 return X86Mir2Lir::EncodingMap[opcode].name; 568} 569 570const char* X86Mir2Lir::GetTargetInstFmt(int opcode) { 571 DCHECK(!IsPseudoLirOp(opcode)); 572 return X86Mir2Lir::EncodingMap[opcode].fmt; 573} 574 575/* 576 * Return an updated location record with current in-register status. 577 * If the value lives in live temps, reflect that fact. No code 578 * is generated. If the live value is part of an older pair, 579 * clobber both low and high. 580 */ 581// TODO: Reunify with common code after 'pair mess' has been fixed 582RegLocation X86Mir2Lir::UpdateLocWide(RegLocation loc) { 583 DCHECK(loc.wide); 584 DCHECK(CheckCorePoolSanity()); 585 if (loc.location != kLocPhysReg) { 586 DCHECK((loc.location == kLocDalvikFrame) || 587 (loc.location == kLocCompilerTemp)); 588 // Are the dalvik regs already live in physical registers? 589 RegisterInfo* info_lo = AllocLive(loc.s_reg_low, kAnyReg); 590 591 // Handle FP registers specially on x86. 592 if (info_lo && IsFpReg(info_lo->reg)) { 593 bool match = true; 594 595 // We can't match a FP register with a pair of Core registers. 596 match = match && (info_lo->pair == 0); 597 598 if (match) { 599 // We can reuse;update the register usage info. 600 loc.location = kLocPhysReg; 601 loc.vec_len = kVectorLength8; 602 // TODO: use k64BitVector 603 loc.reg = RegStorage(RegStorage::k64BitPair, info_lo->reg, info_lo->reg); 604 DCHECK(IsFpReg(loc.reg.GetReg())); 605 return loc; 606 } 607 // We can't easily reuse; clobber and free any overlaps. 608 if (info_lo) { 609 Clobber(info_lo->reg); 610 FreeTemp(info_lo->reg); 611 if (info_lo->pair) 612 Clobber(info_lo->partner); 613 } 614 } else { 615 RegisterInfo* info_hi = AllocLive(GetSRegHi(loc.s_reg_low), kAnyReg); 616 bool match = true; 617 match = match && (info_lo != NULL); 618 match = match && (info_hi != NULL); 619 // Are they both core or both FP? 620 match = match && (IsFpReg(info_lo->reg) == IsFpReg(info_hi->reg)); 621 // If a pair of floating point singles, are they properly aligned? 622 if (match && IsFpReg(info_lo->reg)) { 623 match &= ((info_lo->reg & 0x1) == 0); 624 match &= ((info_hi->reg - info_lo->reg) == 1); 625 } 626 // If previously used as a pair, it is the same pair? 627 if (match && (info_lo->pair || info_hi->pair)) { 628 match = (info_lo->pair == info_hi->pair); 629 match &= ((info_lo->reg == info_hi->partner) && 630 (info_hi->reg == info_lo->partner)); 631 } 632 if (match) { 633 // Can reuse - update the register usage info 634 loc.reg = RegStorage(RegStorage::k64BitPair, info_lo->reg, info_hi->reg); 635 loc.location = kLocPhysReg; 636 MarkPair(loc.reg.GetReg(), loc.reg.GetHighReg()); 637 DCHECK(!IsFpReg(loc.reg.GetReg()) || ((loc.reg.GetReg() & 0x1) == 0)); 638 return loc; 639 } 640 // Can't easily reuse - clobber and free any overlaps 641 if (info_lo) { 642 Clobber(info_lo->reg); 643 FreeTemp(info_lo->reg); 644 if (info_lo->pair) 645 Clobber(info_lo->partner); 646 } 647 if (info_hi) { 648 Clobber(info_hi->reg); 649 FreeTemp(info_hi->reg); 650 if (info_hi->pair) 651 Clobber(info_hi->partner); 652 } 653 } 654 } 655 return loc; 656} 657 658// TODO: Reunify with common code after 'pair mess' has been fixed 659RegLocation X86Mir2Lir::EvalLocWide(RegLocation loc, int reg_class, bool update) { 660 DCHECK(loc.wide); 661 int32_t low_reg; 662 int32_t high_reg; 663 664 loc = UpdateLocWide(loc); 665 666 /* If it is already in a register, we can assume proper form. Is it the right reg class? */ 667 if (loc.location == kLocPhysReg) { 668 DCHECK_EQ(IsFpReg(loc.reg.GetReg()), loc.IsVectorScalar()); 669 if (!RegClassMatches(reg_class, loc.reg.GetReg())) { 670 /* It is the wrong register class. Reallocate and copy. */ 671 if (!IsFpReg(loc.reg.GetReg())) { 672 // We want this in a FP reg, and it is in core registers. 673 DCHECK(reg_class != kCoreReg); 674 // Allocate this into any FP reg, and mark it with the right size. 675 low_reg = AllocTypedTemp(true, reg_class); 676 OpVectorRegCopyWide(low_reg, loc.reg.GetReg(), loc.reg.GetHighReg()); 677 CopyRegInfo(low_reg, loc.reg.GetReg()); 678 Clobber(loc.reg.GetReg()); 679 Clobber(loc.reg.GetHighReg()); 680 loc.reg.SetReg(low_reg); 681 loc.reg.SetHighReg(low_reg); // Play nice with existing code. 682 loc.vec_len = kVectorLength8; 683 } else { 684 // The value is in a FP register, and we want it in a pair of core registers. 685 DCHECK_EQ(reg_class, kCoreReg); 686 DCHECK_EQ(loc.reg.GetReg(), loc.reg.GetHighReg()); 687 RegStorage new_regs = AllocTypedTempWide(false, kCoreReg); // Force to core registers. 688 low_reg = new_regs.GetReg(); 689 high_reg = new_regs.GetHighReg(); 690 DCHECK_NE(low_reg, high_reg); 691 OpRegCopyWide(low_reg, high_reg, loc.reg.GetReg(), loc.reg.GetHighReg()); 692 CopyRegInfo(low_reg, loc.reg.GetReg()); 693 CopyRegInfo(high_reg, loc.reg.GetHighReg()); 694 Clobber(loc.reg.GetReg()); 695 Clobber(loc.reg.GetHighReg()); 696 loc.reg = new_regs; 697 MarkPair(loc.reg.GetReg(), loc.reg.GetHighReg()); 698 DCHECK(!IsFpReg(loc.reg.GetReg()) || ((loc.reg.GetReg() & 0x1) == 0)); 699 } 700 } 701 return loc; 702 } 703 704 DCHECK_NE(loc.s_reg_low, INVALID_SREG); 705 DCHECK_NE(GetSRegHi(loc.s_reg_low), INVALID_SREG); 706 707 loc.reg = AllocTypedTempWide(loc.fp, reg_class); 708 709 // FIXME: take advantage of RegStorage notation. 710 if (loc.reg.GetReg() == loc.reg.GetHighReg()) { 711 DCHECK(IsFpReg(loc.reg.GetReg())); 712 loc.vec_len = kVectorLength8; 713 } else { 714 MarkPair(loc.reg.GetReg(), loc.reg.GetHighReg()); 715 } 716 if (update) { 717 loc.location = kLocPhysReg; 718 MarkLive(loc.reg.GetReg(), loc.s_reg_low); 719 if (loc.reg.GetReg() != loc.reg.GetHighReg()) { 720 MarkLive(loc.reg.GetHighReg(), GetSRegHi(loc.s_reg_low)); 721 } 722 } 723 return loc; 724} 725 726// TODO: Reunify with common code after 'pair mess' has been fixed 727RegLocation X86Mir2Lir::EvalLoc(RegLocation loc, int reg_class, bool update) { 728 int new_reg; 729 730 if (loc.wide) 731 return EvalLocWide(loc, reg_class, update); 732 733 loc = UpdateLoc(loc); 734 735 if (loc.location == kLocPhysReg) { 736 if (!RegClassMatches(reg_class, loc.reg.GetReg())) { 737 /* Wrong register class. Realloc, copy and transfer ownership. */ 738 new_reg = AllocTypedTemp(loc.fp, reg_class); 739 OpRegCopy(new_reg, loc.reg.GetReg()); 740 CopyRegInfo(new_reg, loc.reg.GetReg()); 741 Clobber(loc.reg.GetReg()); 742 loc.reg.SetReg(new_reg); 743 if (IsFpReg(loc.reg.GetReg()) && reg_class != kCoreReg) 744 loc.vec_len = kVectorLength4; 745 } 746 return loc; 747 } 748 749 DCHECK_NE(loc.s_reg_low, INVALID_SREG); 750 751 loc.reg = RegStorage(RegStorage::k32BitSolo, AllocTypedTemp(loc.fp, reg_class)); 752 if (IsFpReg(loc.reg.GetReg()) && reg_class != kCoreReg) 753 loc.vec_len = kVectorLength4; 754 755 if (update) { 756 loc.location = kLocPhysReg; 757 MarkLive(loc.reg.GetReg(), loc.s_reg_low); 758 } 759 return loc; 760} 761 762int X86Mir2Lir::AllocTempDouble() { 763 // We really don't need a pair of registers. 764 return AllocTempFloat(); 765} 766 767// TODO: Reunify with common code after 'pair mess' has been fixed 768void X86Mir2Lir::ResetDefLocWide(RegLocation rl) { 769 DCHECK(rl.wide); 770 RegisterInfo* p_low = IsTemp(rl.reg.GetReg()); 771 if (IsFpReg(rl.reg.GetReg())) { 772 // We are using only the low register. 773 if (p_low && !(cu_->disable_opt & (1 << kSuppressLoads))) { 774 NullifyRange(p_low->def_start, p_low->def_end, p_low->s_reg, rl.s_reg_low); 775 } 776 ResetDef(rl.reg.GetReg()); 777 } else { 778 RegisterInfo* p_high = IsTemp(rl.reg.GetHighReg()); 779 if (p_low && !(cu_->disable_opt & (1 << kSuppressLoads))) { 780 DCHECK(p_low->pair); 781 NullifyRange(p_low->def_start, p_low->def_end, p_low->s_reg, rl.s_reg_low); 782 } 783 if (p_high && !(cu_->disable_opt & (1 << kSuppressLoads))) { 784 DCHECK(p_high->pair); 785 } 786 ResetDef(rl.reg.GetReg()); 787 ResetDef(rl.reg.GetHighReg()); 788 } 789} 790 791void X86Mir2Lir::GenConstWide(RegLocation rl_dest, int64_t value) { 792 // Can we do this directly to memory? 793 rl_dest = UpdateLocWide(rl_dest); 794 if ((rl_dest.location == kLocDalvikFrame) || 795 (rl_dest.location == kLocCompilerTemp)) { 796 int32_t val_lo = Low32Bits(value); 797 int32_t val_hi = High32Bits(value); 798 int rBase = TargetReg(kSp); 799 int displacement = SRegOffset(rl_dest.s_reg_low); 800 801 LIR * store = NewLIR3(kX86Mov32MI, rBase, displacement + LOWORD_OFFSET, val_lo); 802 AnnotateDalvikRegAccess(store, (displacement + LOWORD_OFFSET) >> 2, 803 false /* is_load */, true /* is64bit */); 804 store = NewLIR3(kX86Mov32MI, rBase, displacement + HIWORD_OFFSET, val_hi); 805 AnnotateDalvikRegAccess(store, (displacement + HIWORD_OFFSET) >> 2, 806 false /* is_load */, true /* is64bit */); 807 return; 808 } 809 810 // Just use the standard code to do the generation. 811 Mir2Lir::GenConstWide(rl_dest, value); 812} 813 814// TODO: Merge with existing RegLocation dumper in vreg_analysis.cc 815void X86Mir2Lir::DumpRegLocation(RegLocation loc) { 816 LOG(INFO) << "location: " << loc.location << ',' 817 << (loc.wide ? " w" : " ") 818 << (loc.defined ? " D" : " ") 819 << (loc.is_const ? " c" : " ") 820 << (loc.fp ? " F" : " ") 821 << (loc.core ? " C" : " ") 822 << (loc.ref ? " r" : " ") 823 << (loc.high_word ? " h" : " ") 824 << (loc.home ? " H" : " ") 825 << " vec_len: " << loc.vec_len 826 << ", low: " << static_cast<int>(loc.reg.GetReg()) 827 << ", high: " << static_cast<int>(loc.reg.GetHighReg()) 828 << ", s_reg: " << loc.s_reg_low 829 << ", orig: " << loc.orig_sreg; 830} 831 832void X86Mir2Lir::Materialize() { 833 // A good place to put the analysis before starting. 834 AnalyzeMIR(); 835 836 // Now continue with regular code generation. 837 Mir2Lir::Materialize(); 838} 839 840void X86Mir2Lir::LoadMethodAddress(const MethodReference& target_method, InvokeType type, 841 SpecialTargetRegister symbolic_reg) { 842 /* 843 * For x86, just generate a 32 bit move immediate instruction, that will be filled 844 * in at 'link time'. For now, put a unique value based on target to ensure that 845 * code deduplication works. 846 */ 847 int target_method_idx = target_method.dex_method_index; 848 const DexFile* target_dex_file = target_method.dex_file; 849 const DexFile::MethodId& target_method_id = target_dex_file->GetMethodId(target_method_idx); 850 uintptr_t target_method_id_ptr = reinterpret_cast<uintptr_t>(&target_method_id); 851 852 // Generate the move instruction with the unique pointer and save index, dex_file, and type. 853 LIR *move = RawLIR(current_dalvik_offset_, kX86Mov32RI, TargetReg(symbolic_reg), 854 static_cast<int>(target_method_id_ptr), target_method_idx, 855 WrapPointer(const_cast<DexFile*>(target_dex_file)), type); 856 AppendLIR(move); 857 method_address_insns_.Insert(move); 858} 859 860void X86Mir2Lir::LoadClassType(uint32_t type_idx, SpecialTargetRegister symbolic_reg) { 861 /* 862 * For x86, just generate a 32 bit move immediate instruction, that will be filled 863 * in at 'link time'. For now, put a unique value based on target to ensure that 864 * code deduplication works. 865 */ 866 const DexFile::TypeId& id = cu_->dex_file->GetTypeId(type_idx); 867 uintptr_t ptr = reinterpret_cast<uintptr_t>(&id); 868 869 // Generate the move instruction with the unique pointer and save index and type. 870 LIR *move = RawLIR(current_dalvik_offset_, kX86Mov32RI, TargetReg(symbolic_reg), 871 static_cast<int>(ptr), type_idx); 872 AppendLIR(move); 873 class_type_address_insns_.Insert(move); 874} 875 876LIR *X86Mir2Lir::CallWithLinkerFixup(const MethodReference& target_method, InvokeType type) { 877 /* 878 * For x86, just generate a 32 bit call relative instruction, that will be filled 879 * in at 'link time'. For now, put a unique value based on target to ensure that 880 * code deduplication works. 881 */ 882 int target_method_idx = target_method.dex_method_index; 883 const DexFile* target_dex_file = target_method.dex_file; 884 const DexFile::MethodId& target_method_id = target_dex_file->GetMethodId(target_method_idx); 885 uintptr_t target_method_id_ptr = reinterpret_cast<uintptr_t>(&target_method_id); 886 887 // Generate the call instruction with the unique pointer and save index, dex_file, and type. 888 LIR *call = RawLIR(current_dalvik_offset_, kX86CallI, static_cast<int>(target_method_id_ptr), 889 target_method_idx, WrapPointer(const_cast<DexFile*>(target_dex_file)), type); 890 AppendLIR(call); 891 call_method_insns_.Insert(call); 892 return call; 893} 894 895void X86Mir2Lir::InstallLiteralPools() { 896 // These are handled differently for x86. 897 DCHECK(code_literal_list_ == nullptr); 898 DCHECK(method_literal_list_ == nullptr); 899 DCHECK(class_literal_list_ == nullptr); 900 901 // Handle the fixups for methods. 902 for (uint32_t i = 0; i < method_address_insns_.Size(); i++) { 903 LIR* p = method_address_insns_.Get(i); 904 DCHECK_EQ(p->opcode, kX86Mov32RI); 905 uint32_t target_method_idx = p->operands[2]; 906 const DexFile* target_dex_file = 907 reinterpret_cast<const DexFile*>(UnwrapPointer(p->operands[3])); 908 909 // The offset to patch is the last 4 bytes of the instruction. 910 int patch_offset = p->offset + p->flags.size - 4; 911 cu_->compiler_driver->AddMethodPatch(cu_->dex_file, cu_->class_def_idx, 912 cu_->method_idx, cu_->invoke_type, 913 target_method_idx, target_dex_file, 914 static_cast<InvokeType>(p->operands[4]), 915 patch_offset); 916 } 917 918 // Handle the fixups for class types. 919 for (uint32_t i = 0; i < class_type_address_insns_.Size(); i++) { 920 LIR* p = class_type_address_insns_.Get(i); 921 DCHECK_EQ(p->opcode, kX86Mov32RI); 922 uint32_t target_method_idx = p->operands[2]; 923 924 // The offset to patch is the last 4 bytes of the instruction. 925 int patch_offset = p->offset + p->flags.size - 4; 926 cu_->compiler_driver->AddClassPatch(cu_->dex_file, cu_->class_def_idx, 927 cu_->method_idx, target_method_idx, patch_offset); 928 } 929 930 // And now the PC-relative calls to methods. 931 for (uint32_t i = 0; i < call_method_insns_.Size(); i++) { 932 LIR* p = call_method_insns_.Get(i); 933 DCHECK_EQ(p->opcode, kX86CallI); 934 uint32_t target_method_idx = p->operands[1]; 935 const DexFile* target_dex_file = 936 reinterpret_cast<const DexFile*>(UnwrapPointer(p->operands[2])); 937 938 // The offset to patch is the last 4 bytes of the instruction. 939 int patch_offset = p->offset + p->flags.size - 4; 940 cu_->compiler_driver->AddRelativeCodePatch(cu_->dex_file, cu_->class_def_idx, 941 cu_->method_idx, cu_->invoke_type, 942 target_method_idx, target_dex_file, 943 static_cast<InvokeType>(p->operands[3]), 944 patch_offset, -4 /* offset */); 945 } 946 947 // And do the normal processing. 948 Mir2Lir::InstallLiteralPools(); 949} 950 951/* 952 * Fast string.index_of(I) & (II). Inline check for simple case of char <= 0xffff, 953 * otherwise bails to standard library code. 954 */ 955bool X86Mir2Lir::GenInlinedIndexOf(CallInfo* info, bool zero_based) { 956 ClobberCallerSave(); 957 LockCallTemps(); // Using fixed registers 958 959 // EAX: 16 bit character being searched. 960 // ECX: count: number of words to be searched. 961 // EDI: String being searched. 962 // EDX: temporary during execution. 963 // EBX: temporary during execution. 964 965 RegLocation rl_obj = info->args[0]; 966 RegLocation rl_char = info->args[1]; 967 RegLocation rl_start; // Note: only present in III flavor or IndexOf. 968 969 uint32_t char_value = 970 rl_char.is_const ? mir_graph_->ConstantValue(rl_char.orig_sreg) : 0; 971 972 if (char_value > 0xFFFF) { 973 // We have to punt to the real String.indexOf. 974 return false; 975 } 976 977 // Okay, we are commited to inlining this. 978 RegLocation rl_return = GetReturn(false); 979 RegLocation rl_dest = InlineTarget(info); 980 981 // Is the string non-NULL? 982 LoadValueDirectFixed(rl_obj, rDX); 983 GenNullCheck(rDX, info->opt_flags); 984 info->opt_flags |= MIR_IGNORE_NULL_CHECK; // Record that we've null checked. 985 986 // Does the character fit in 16 bits? 987 LIR* launchpad_branch = nullptr; 988 if (rl_char.is_const) { 989 // We need the value in EAX. 990 LoadConstantNoClobber(rAX, char_value); 991 } else { 992 // Character is not a constant; compare at runtime. 993 LoadValueDirectFixed(rl_char, rAX); 994 launchpad_branch = OpCmpImmBranch(kCondGt, rAX, 0xFFFF, nullptr); 995 } 996 997 // From here down, we know that we are looking for a char that fits in 16 bits. 998 // Location of reference to data array within the String object. 999 int value_offset = mirror::String::ValueOffset().Int32Value(); 1000 // Location of count within the String object. 1001 int count_offset = mirror::String::CountOffset().Int32Value(); 1002 // Starting offset within data array. 1003 int offset_offset = mirror::String::OffsetOffset().Int32Value(); 1004 // Start of char data with array_. 1005 int data_offset = mirror::Array::DataOffset(sizeof(uint16_t)).Int32Value(); 1006 1007 // Character is in EAX. 1008 // Object pointer is in EDX. 1009 1010 // We need to preserve EDI, but have no spare registers, so push it on the stack. 1011 // We have to remember that all stack addresses after this are offset by sizeof(EDI). 1012 NewLIR1(kX86Push32R, rDI); 1013 1014 // Compute the number of words to search in to rCX. 1015 LoadWordDisp(rDX, count_offset, rCX); 1016 LIR *length_compare = nullptr; 1017 int start_value = 0; 1018 if (zero_based) { 1019 // We have to handle an empty string. Use special instruction JECXZ. 1020 length_compare = NewLIR0(kX86Jecxz8); 1021 } else { 1022 rl_start = info->args[2]; 1023 // We have to offset by the start index. 1024 if (rl_start.is_const) { 1025 start_value = mir_graph_->ConstantValue(rl_start.orig_sreg); 1026 start_value = std::max(start_value, 0); 1027 1028 // Is the start > count? 1029 length_compare = OpCmpImmBranch(kCondLe, rCX, start_value, nullptr); 1030 1031 if (start_value != 0) { 1032 OpRegImm(kOpSub, rCX, start_value); 1033 } 1034 } else { 1035 // Runtime start index. 1036 rl_start = UpdateLoc(rl_start); 1037 if (rl_start.location == kLocPhysReg) { 1038 length_compare = OpCmpBranch(kCondLe, rCX, rl_start.reg.GetReg(), nullptr); 1039 OpRegReg(kOpSub, rCX, rl_start.reg.GetReg()); 1040 } else { 1041 // Compare to memory to avoid a register load. Handle pushed EDI. 1042 int displacement = SRegOffset(rl_start.s_reg_low) + sizeof(uint32_t); 1043 OpRegMem(kOpCmp, rCX, rX86_SP, displacement); 1044 length_compare = NewLIR2(kX86Jcc8, 0, kX86CondLe); 1045 OpRegMem(kOpSub, rCX, rX86_SP, displacement); 1046 } 1047 } 1048 } 1049 DCHECK(length_compare != nullptr); 1050 1051 // ECX now contains the count in words to be searched. 1052 1053 // Load the address of the string into EBX. 1054 // The string starts at VALUE(String) + 2 * OFFSET(String) + DATA_OFFSET. 1055 LoadWordDisp(rDX, value_offset, rDI); 1056 LoadWordDisp(rDX, offset_offset, rBX); 1057 OpLea(rBX, rDI, rBX, 1, data_offset); 1058 1059 // Now compute into EDI where the search will start. 1060 if (zero_based || rl_start.is_const) { 1061 if (start_value == 0) { 1062 OpRegCopy(rDI, rBX); 1063 } else { 1064 NewLIR3(kX86Lea32RM, rDI, rBX, 2 * start_value); 1065 } 1066 } else { 1067 if (rl_start.location == kLocPhysReg) { 1068 if (rl_start.reg.GetReg() == rDI) { 1069 // We have a slight problem here. We are already using RDI! 1070 // Grab the value from the stack. 1071 LoadWordDisp(rX86_SP, 0, rDX); 1072 OpLea(rDI, rBX, rDX, 1, 0); 1073 } else { 1074 OpLea(rDI, rBX, rl_start.reg.GetReg(), 1, 0); 1075 } 1076 } else { 1077 OpRegCopy(rDI, rBX); 1078 // Load the start index from stack, remembering that we pushed EDI. 1079 int displacement = SRegOffset(rl_start.s_reg_low) + sizeof(uint32_t); 1080 LoadWordDisp(rX86_SP, displacement, rDX); 1081 OpLea(rDI, rBX, rDX, 1, 0); 1082 } 1083 } 1084 1085 // EDI now contains the start of the string to be searched. 1086 // We are all prepared to do the search for the character. 1087 NewLIR0(kX86RepneScasw); 1088 1089 // Did we find a match? 1090 LIR* failed_branch = OpCondBranch(kCondNe, nullptr); 1091 1092 // yes, we matched. Compute the index of the result. 1093 // index = ((curr_ptr - orig_ptr) / 2) - 1. 1094 OpRegReg(kOpSub, rDI, rBX); 1095 OpRegImm(kOpAsr, rDI, 1); 1096 NewLIR3(kX86Lea32RM, rl_return.reg.GetReg(), rDI, -1); 1097 LIR *all_done = NewLIR1(kX86Jmp8, 0); 1098 1099 // Failed to match; return -1. 1100 LIR *not_found = NewLIR0(kPseudoTargetLabel); 1101 length_compare->target = not_found; 1102 failed_branch->target = not_found; 1103 LoadConstantNoClobber(rl_return.reg.GetReg(), -1); 1104 1105 // And join up at the end. 1106 all_done->target = NewLIR0(kPseudoTargetLabel); 1107 // Restore EDI from the stack. 1108 NewLIR1(kX86Pop32R, rDI); 1109 1110 // Out of line code returns here. 1111 if (launchpad_branch != nullptr) { 1112 LIR *return_point = NewLIR0(kPseudoTargetLabel); 1113 AddIntrinsicLaunchpad(info, launchpad_branch, return_point); 1114 } 1115 1116 StoreValue(rl_dest, rl_return); 1117 return true; 1118} 1119 1120/* 1121 * @brief Enter a 32 bit quantity into the FDE buffer 1122 * @param buf FDE buffer. 1123 * @param data Data value. 1124 */ 1125static void PushWord(std::vector<uint8_t>&buf, int data) { 1126 buf.push_back(data & 0xff); 1127 buf.push_back((data >> 8) & 0xff); 1128 buf.push_back((data >> 16) & 0xff); 1129 buf.push_back((data >> 24) & 0xff); 1130} 1131 1132/* 1133 * @brief Enter an 'advance LOC' into the FDE buffer 1134 * @param buf FDE buffer. 1135 * @param increment Amount by which to increase the current location. 1136 */ 1137static void AdvanceLoc(std::vector<uint8_t>&buf, uint32_t increment) { 1138 if (increment < 64) { 1139 // Encoding in opcode. 1140 buf.push_back(0x1 << 6 | increment); 1141 } else if (increment < 256) { 1142 // Single byte delta. 1143 buf.push_back(0x02); 1144 buf.push_back(increment); 1145 } else if (increment < 256 * 256) { 1146 // Two byte delta. 1147 buf.push_back(0x03); 1148 buf.push_back(increment & 0xff); 1149 buf.push_back((increment >> 8) & 0xff); 1150 } else { 1151 // Four byte delta. 1152 buf.push_back(0x04); 1153 PushWord(buf, increment); 1154 } 1155} 1156 1157 1158std::vector<uint8_t>* X86CFIInitialization() { 1159 return X86Mir2Lir::ReturnCommonCallFrameInformation(); 1160} 1161 1162std::vector<uint8_t>* X86Mir2Lir::ReturnCommonCallFrameInformation() { 1163 std::vector<uint8_t>*cfi_info = new std::vector<uint8_t>; 1164 1165 // Length of the CIE (except for this field). 1166 PushWord(*cfi_info, 16); 1167 1168 // CIE id. 1169 PushWord(*cfi_info, 0xFFFFFFFFU); 1170 1171 // Version: 3. 1172 cfi_info->push_back(0x03); 1173 1174 // Augmentation: empty string. 1175 cfi_info->push_back(0x0); 1176 1177 // Code alignment: 1. 1178 cfi_info->push_back(0x01); 1179 1180 // Data alignment: -4. 1181 cfi_info->push_back(0x7C); 1182 1183 // Return address register (R8). 1184 cfi_info->push_back(0x08); 1185 1186 // Initial return PC is 4(ESP): DW_CFA_def_cfa R4 4. 1187 cfi_info->push_back(0x0C); 1188 cfi_info->push_back(0x04); 1189 cfi_info->push_back(0x04); 1190 1191 // Return address location: 0(SP): DW_CFA_offset R8 1 (* -4);. 1192 cfi_info->push_back(0x2 << 6 | 0x08); 1193 cfi_info->push_back(0x01); 1194 1195 // And 2 Noops to align to 4 byte boundary. 1196 cfi_info->push_back(0x0); 1197 cfi_info->push_back(0x0); 1198 1199 DCHECK_EQ(cfi_info->size() & 3, 0U); 1200 return cfi_info; 1201} 1202 1203static void EncodeUnsignedLeb128(std::vector<uint8_t>& buf, uint32_t value) { 1204 uint8_t buffer[12]; 1205 uint8_t *ptr = EncodeUnsignedLeb128(buffer, value); 1206 for (uint8_t *p = buffer; p < ptr; p++) { 1207 buf.push_back(*p); 1208 } 1209} 1210 1211std::vector<uint8_t>* X86Mir2Lir::ReturnCallFrameInformation() { 1212 std::vector<uint8_t>*cfi_info = new std::vector<uint8_t>; 1213 1214 // Generate the FDE for the method. 1215 DCHECK_NE(data_offset_, 0U); 1216 1217 // Length (will be filled in later in this routine). 1218 PushWord(*cfi_info, 0); 1219 1220 // CIE_pointer (can be filled in by linker); might be left at 0 if there is only 1221 // one CIE for the whole debug_frame section. 1222 PushWord(*cfi_info, 0); 1223 1224 // 'initial_location' (filled in by linker). 1225 PushWord(*cfi_info, 0); 1226 1227 // 'address_range' (number of bytes in the method). 1228 PushWord(*cfi_info, data_offset_); 1229 1230 // The instructions in the FDE. 1231 if (stack_decrement_ != nullptr) { 1232 // Advance LOC to just past the stack decrement. 1233 uint32_t pc = NEXT_LIR(stack_decrement_)->offset; 1234 AdvanceLoc(*cfi_info, pc); 1235 1236 // Now update the offset to the call frame: DW_CFA_def_cfa_offset frame_size. 1237 cfi_info->push_back(0x0e); 1238 EncodeUnsignedLeb128(*cfi_info, frame_size_); 1239 1240 // We continue with that stack until the epilogue. 1241 if (stack_increment_ != nullptr) { 1242 uint32_t new_pc = NEXT_LIR(stack_increment_)->offset; 1243 AdvanceLoc(*cfi_info, new_pc - pc); 1244 1245 // We probably have code snippets after the epilogue, so save the 1246 // current state: DW_CFA_remember_state. 1247 cfi_info->push_back(0x0a); 1248 1249 // We have now popped the stack: DW_CFA_def_cfa_offset 4. There is only the return 1250 // PC on the stack now. 1251 cfi_info->push_back(0x0e); 1252 EncodeUnsignedLeb128(*cfi_info, 4); 1253 1254 // Everything after that is the same as before the epilogue. 1255 // Stack bump was followed by RET instruction. 1256 LIR *post_ret_insn = NEXT_LIR(NEXT_LIR(stack_increment_)); 1257 if (post_ret_insn != nullptr) { 1258 pc = new_pc; 1259 new_pc = post_ret_insn->offset; 1260 AdvanceLoc(*cfi_info, new_pc - pc); 1261 // Restore the state: DW_CFA_restore_state. 1262 cfi_info->push_back(0x0b); 1263 } 1264 } 1265 } 1266 1267 // Padding to a multiple of 4 1268 while ((cfi_info->size() & 3) != 0) { 1269 // DW_CFA_nop is encoded as 0. 1270 cfi_info->push_back(0); 1271 } 1272 1273 // Set the length of the FDE inside the generated bytes. 1274 uint32_t length = cfi_info->size() - 4; 1275 (*cfi_info)[0] = length; 1276 (*cfi_info)[1] = length >> 8; 1277 (*cfi_info)[2] = length >> 16; 1278 (*cfi_info)[3] = length >> 24; 1279 return cfi_info; 1280} 1281 1282} // namespace art 1283