target_x86.cc revision c5e4ce116e4d44bfdf162f0c949e77772d7e0654
1/* 2 * Copyright (C) 2012 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#include <string> 18#include <inttypes.h> 19 20#include "codegen_x86.h" 21#include "dex/compiler_internals.h" 22#include "dex/quick/mir_to_lir-inl.h" 23#include "dex/reg_storage_eq.h" 24#include "mirror/array.h" 25#include "mirror/string.h" 26#include "x86_lir.h" 27 28namespace art { 29 30static constexpr RegStorage core_regs_arr_32[] = { 31 rs_rAX, rs_rCX, rs_rDX, rs_rBX, rs_rX86_SP_32, rs_rBP, rs_rSI, rs_rDI, 32}; 33static constexpr RegStorage core_regs_arr_64[] = { 34 rs_rAX, rs_rCX, rs_rDX, rs_rBX, rs_rX86_SP_32, rs_rBP, rs_rSI, rs_rDI, 35 rs_r8, rs_r9, rs_r10, rs_r11, rs_r12, rs_r13, rs_r14, rs_r15 36}; 37static constexpr RegStorage core_regs_arr_64q[] = { 38 rs_r0q, rs_r1q, rs_r2q, rs_r3q, rs_rX86_SP_64, rs_r5q, rs_r6q, rs_r7q, 39 rs_r8q, rs_r9q, rs_r10q, rs_r11q, rs_r12q, rs_r13q, rs_r14q, rs_r15q 40}; 41static constexpr RegStorage sp_regs_arr_32[] = { 42 rs_fr0, rs_fr1, rs_fr2, rs_fr3, rs_fr4, rs_fr5, rs_fr6, rs_fr7, 43}; 44static constexpr RegStorage sp_regs_arr_64[] = { 45 rs_fr0, rs_fr1, rs_fr2, rs_fr3, rs_fr4, rs_fr5, rs_fr6, rs_fr7, 46 rs_fr8, rs_fr9, rs_fr10, rs_fr11, rs_fr12, rs_fr13, rs_fr14, rs_fr15 47}; 48static constexpr RegStorage dp_regs_arr_32[] = { 49 rs_dr0, rs_dr1, rs_dr2, rs_dr3, rs_dr4, rs_dr5, rs_dr6, rs_dr7, 50}; 51static constexpr RegStorage dp_regs_arr_64[] = { 52 rs_dr0, rs_dr1, rs_dr2, rs_dr3, rs_dr4, rs_dr5, rs_dr6, rs_dr7, 53 rs_dr8, rs_dr9, rs_dr10, rs_dr11, rs_dr12, rs_dr13, rs_dr14, rs_dr15 54}; 55static constexpr RegStorage reserved_regs_arr_32[] = {rs_rX86_SP_32}; 56static constexpr RegStorage reserved_regs_arr_64[] = {rs_rX86_SP_32}; 57static constexpr RegStorage reserved_regs_arr_64q[] = {rs_rX86_SP_64}; 58static constexpr RegStorage core_temps_arr_32[] = {rs_rAX, rs_rCX, rs_rDX, rs_rBX}; 59static constexpr RegStorage core_temps_arr_64[] = { 60 rs_rAX, rs_rCX, rs_rDX, rs_rSI, rs_rDI, 61 rs_r8, rs_r9, rs_r10, rs_r11 62}; 63static constexpr RegStorage core_temps_arr_64q[] = { 64 rs_r0q, rs_r1q, rs_r2q, rs_r6q, rs_r7q, 65 rs_r8q, rs_r9q, rs_r10q, rs_r11q 66}; 67static constexpr RegStorage sp_temps_arr_32[] = { 68 rs_fr0, rs_fr1, rs_fr2, rs_fr3, rs_fr4, rs_fr5, rs_fr6, rs_fr7, 69}; 70static constexpr RegStorage sp_temps_arr_64[] = { 71 rs_fr0, rs_fr1, rs_fr2, rs_fr3, rs_fr4, rs_fr5, rs_fr6, rs_fr7, 72 rs_fr8, rs_fr9, rs_fr10, rs_fr11, rs_fr12, rs_fr13, rs_fr14, rs_fr15 73}; 74static constexpr RegStorage dp_temps_arr_32[] = { 75 rs_dr0, rs_dr1, rs_dr2, rs_dr3, rs_dr4, rs_dr5, rs_dr6, rs_dr7, 76}; 77static constexpr RegStorage dp_temps_arr_64[] = { 78 rs_dr0, rs_dr1, rs_dr2, rs_dr3, rs_dr4, rs_dr5, rs_dr6, rs_dr7, 79 rs_dr8, rs_dr9, rs_dr10, rs_dr11, rs_dr12, rs_dr13, rs_dr14, rs_dr15 80}; 81 82static constexpr RegStorage xp_temps_arr_32[] = { 83 rs_xr0, rs_xr1, rs_xr2, rs_xr3, rs_xr4, rs_xr5, rs_xr6, rs_xr7, 84}; 85static constexpr RegStorage xp_temps_arr_64[] = { 86 rs_xr0, rs_xr1, rs_xr2, rs_xr3, rs_xr4, rs_xr5, rs_xr6, rs_xr7, 87 rs_xr8, rs_xr9, rs_xr10, rs_xr11, rs_xr12, rs_xr13, rs_xr14, rs_xr15 88}; 89 90static constexpr ArrayRef<const RegStorage> empty_pool; 91static constexpr ArrayRef<const RegStorage> core_regs_32(core_regs_arr_32); 92static constexpr ArrayRef<const RegStorage> core_regs_64(core_regs_arr_64); 93static constexpr ArrayRef<const RegStorage> core_regs_64q(core_regs_arr_64q); 94static constexpr ArrayRef<const RegStorage> sp_regs_32(sp_regs_arr_32); 95static constexpr ArrayRef<const RegStorage> sp_regs_64(sp_regs_arr_64); 96static constexpr ArrayRef<const RegStorage> dp_regs_32(dp_regs_arr_32); 97static constexpr ArrayRef<const RegStorage> dp_regs_64(dp_regs_arr_64); 98static constexpr ArrayRef<const RegStorage> reserved_regs_32(reserved_regs_arr_32); 99static constexpr ArrayRef<const RegStorage> reserved_regs_64(reserved_regs_arr_64); 100static constexpr ArrayRef<const RegStorage> reserved_regs_64q(reserved_regs_arr_64q); 101static constexpr ArrayRef<const RegStorage> core_temps_32(core_temps_arr_32); 102static constexpr ArrayRef<const RegStorage> core_temps_64(core_temps_arr_64); 103static constexpr ArrayRef<const RegStorage> core_temps_64q(core_temps_arr_64q); 104static constexpr ArrayRef<const RegStorage> sp_temps_32(sp_temps_arr_32); 105static constexpr ArrayRef<const RegStorage> sp_temps_64(sp_temps_arr_64); 106static constexpr ArrayRef<const RegStorage> dp_temps_32(dp_temps_arr_32); 107static constexpr ArrayRef<const RegStorage> dp_temps_64(dp_temps_arr_64); 108 109static constexpr ArrayRef<const RegStorage> xp_temps_32(xp_temps_arr_32); 110static constexpr ArrayRef<const RegStorage> xp_temps_64(xp_temps_arr_64); 111 112RegStorage rs_rX86_SP; 113 114X86NativeRegisterPool rX86_ARG0; 115X86NativeRegisterPool rX86_ARG1; 116X86NativeRegisterPool rX86_ARG2; 117X86NativeRegisterPool rX86_ARG3; 118X86NativeRegisterPool rX86_ARG4; 119X86NativeRegisterPool rX86_ARG5; 120X86NativeRegisterPool rX86_FARG0; 121X86NativeRegisterPool rX86_FARG1; 122X86NativeRegisterPool rX86_FARG2; 123X86NativeRegisterPool rX86_FARG3; 124X86NativeRegisterPool rX86_FARG4; 125X86NativeRegisterPool rX86_FARG5; 126X86NativeRegisterPool rX86_FARG6; 127X86NativeRegisterPool rX86_FARG7; 128X86NativeRegisterPool rX86_RET0; 129X86NativeRegisterPool rX86_RET1; 130X86NativeRegisterPool rX86_INVOKE_TGT; 131X86NativeRegisterPool rX86_COUNT; 132 133RegStorage rs_rX86_ARG0; 134RegStorage rs_rX86_ARG1; 135RegStorage rs_rX86_ARG2; 136RegStorage rs_rX86_ARG3; 137RegStorage rs_rX86_ARG4; 138RegStorage rs_rX86_ARG5; 139RegStorage rs_rX86_FARG0; 140RegStorage rs_rX86_FARG1; 141RegStorage rs_rX86_FARG2; 142RegStorage rs_rX86_FARG3; 143RegStorage rs_rX86_FARG4; 144RegStorage rs_rX86_FARG5; 145RegStorage rs_rX86_FARG6; 146RegStorage rs_rX86_FARG7; 147RegStorage rs_rX86_RET0; 148RegStorage rs_rX86_RET1; 149RegStorage rs_rX86_INVOKE_TGT; 150RegStorage rs_rX86_COUNT; 151 152RegLocation X86Mir2Lir::LocCReturn() { 153 return x86_loc_c_return; 154} 155 156RegLocation X86Mir2Lir::LocCReturnRef() { 157 return cu_->target64 ? x86_64_loc_c_return_ref : x86_loc_c_return_ref; 158} 159 160RegLocation X86Mir2Lir::LocCReturnWide() { 161 return cu_->target64 ? x86_64_loc_c_return_wide : x86_loc_c_return_wide; 162} 163 164RegLocation X86Mir2Lir::LocCReturnFloat() { 165 return x86_loc_c_return_float; 166} 167 168RegLocation X86Mir2Lir::LocCReturnDouble() { 169 return x86_loc_c_return_double; 170} 171 172// Return a target-dependent special register for 32-bit. 173RegStorage X86Mir2Lir::TargetReg32(SpecialTargetRegister reg) { 174 RegStorage res_reg = RegStorage::InvalidReg(); 175 switch (reg) { 176 case kSelf: res_reg = RegStorage::InvalidReg(); break; 177 case kSuspend: res_reg = RegStorage::InvalidReg(); break; 178 case kLr: res_reg = RegStorage::InvalidReg(); break; 179 case kPc: res_reg = RegStorage::InvalidReg(); break; 180 case kSp: res_reg = rs_rX86_SP; break; 181 case kArg0: res_reg = rs_rX86_ARG0; break; 182 case kArg1: res_reg = rs_rX86_ARG1; break; 183 case kArg2: res_reg = rs_rX86_ARG2; break; 184 case kArg3: res_reg = rs_rX86_ARG3; break; 185 case kArg4: res_reg = rs_rX86_ARG4; break; 186 case kArg5: res_reg = rs_rX86_ARG5; break; 187 case kFArg0: res_reg = rs_rX86_FARG0; break; 188 case kFArg1: res_reg = rs_rX86_FARG1; break; 189 case kFArg2: res_reg = rs_rX86_FARG2; break; 190 case kFArg3: res_reg = rs_rX86_FARG3; break; 191 case kFArg4: res_reg = rs_rX86_FARG4; break; 192 case kFArg5: res_reg = rs_rX86_FARG5; break; 193 case kFArg6: res_reg = rs_rX86_FARG6; break; 194 case kFArg7: res_reg = rs_rX86_FARG7; break; 195 case kRet0: res_reg = rs_rX86_RET0; break; 196 case kRet1: res_reg = rs_rX86_RET1; break; 197 case kInvokeTgt: res_reg = rs_rX86_INVOKE_TGT; break; 198 case kHiddenArg: res_reg = rs_rAX; break; 199 case kHiddenFpArg: DCHECK(!cu_->target64); res_reg = rs_fr0; break; 200 case kCount: res_reg = rs_rX86_COUNT; break; 201 default: res_reg = RegStorage::InvalidReg(); 202 } 203 return res_reg; 204} 205 206RegStorage X86Mir2Lir::TargetReg(SpecialTargetRegister reg) { 207 LOG(FATAL) << "Do not use this function!!!"; 208 return RegStorage::InvalidReg(); 209} 210 211/* 212 * Decode the register id. 213 */ 214ResourceMask X86Mir2Lir::GetRegMaskCommon(const RegStorage& reg) const { 215 /* Double registers in x86 are just a single FP register. This is always just a single bit. */ 216 return ResourceMask::Bit( 217 /* FP register starts at bit position 16 */ 218 ((reg.IsFloat() || reg.StorageSize() > 8) ? kX86FPReg0 : 0) + reg.GetRegNum()); 219} 220 221ResourceMask X86Mir2Lir::GetPCUseDefEncoding() const { 222 /* 223 * FIXME: might make sense to use a virtual resource encoding bit for pc. Might be 224 * able to clean up some of the x86/Arm_Mips differences 225 */ 226 LOG(FATAL) << "Unexpected call to GetPCUseDefEncoding for x86"; 227 return kEncodeNone; 228} 229 230void X86Mir2Lir::SetupTargetResourceMasks(LIR* lir, uint64_t flags, 231 ResourceMask* use_mask, ResourceMask* def_mask) { 232 DCHECK(cu_->instruction_set == kX86 || cu_->instruction_set == kX86_64); 233 DCHECK(!lir->flags.use_def_invalid); 234 235 // X86-specific resource map setup here. 236 if (flags & REG_USE_SP) { 237 use_mask->SetBit(kX86RegSP); 238 } 239 240 if (flags & REG_DEF_SP) { 241 def_mask->SetBit(kX86RegSP); 242 } 243 244 if (flags & REG_DEFA) { 245 SetupRegMask(def_mask, rs_rAX.GetReg()); 246 } 247 248 if (flags & REG_DEFD) { 249 SetupRegMask(def_mask, rs_rDX.GetReg()); 250 } 251 if (flags & REG_USEA) { 252 SetupRegMask(use_mask, rs_rAX.GetReg()); 253 } 254 255 if (flags & REG_USEC) { 256 SetupRegMask(use_mask, rs_rCX.GetReg()); 257 } 258 259 if (flags & REG_USED) { 260 SetupRegMask(use_mask, rs_rDX.GetReg()); 261 } 262 263 if (flags & REG_USEB) { 264 SetupRegMask(use_mask, rs_rBX.GetReg()); 265 } 266 267 // Fixup hard to describe instruction: Uses rAX, rCX, rDI; sets rDI. 268 if (lir->opcode == kX86RepneScasw) { 269 SetupRegMask(use_mask, rs_rAX.GetReg()); 270 SetupRegMask(use_mask, rs_rCX.GetReg()); 271 SetupRegMask(use_mask, rs_rDI.GetReg()); 272 SetupRegMask(def_mask, rs_rDI.GetReg()); 273 } 274 275 if (flags & USE_FP_STACK) { 276 use_mask->SetBit(kX86FPStack); 277 def_mask->SetBit(kX86FPStack); 278 } 279} 280 281/* For dumping instructions */ 282static const char* x86RegName[] = { 283 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", 284 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" 285}; 286 287static const char* x86CondName[] = { 288 "O", 289 "NO", 290 "B/NAE/C", 291 "NB/AE/NC", 292 "Z/EQ", 293 "NZ/NE", 294 "BE/NA", 295 "NBE/A", 296 "S", 297 "NS", 298 "P/PE", 299 "NP/PO", 300 "L/NGE", 301 "NL/GE", 302 "LE/NG", 303 "NLE/G" 304}; 305 306/* 307 * Interpret a format string and build a string no longer than size 308 * See format key in Assemble.cc. 309 */ 310std::string X86Mir2Lir::BuildInsnString(const char *fmt, LIR *lir, unsigned char* base_addr) { 311 std::string buf; 312 size_t i = 0; 313 size_t fmt_len = strlen(fmt); 314 while (i < fmt_len) { 315 if (fmt[i] != '!') { 316 buf += fmt[i]; 317 i++; 318 } else { 319 i++; 320 DCHECK_LT(i, fmt_len); 321 char operand_number_ch = fmt[i]; 322 i++; 323 if (operand_number_ch == '!') { 324 buf += "!"; 325 } else { 326 int operand_number = operand_number_ch - '0'; 327 DCHECK_LT(operand_number, 6); // Expect upto 6 LIR operands. 328 DCHECK_LT(i, fmt_len); 329 int operand = lir->operands[operand_number]; 330 switch (fmt[i]) { 331 case 'c': 332 DCHECK_LT(static_cast<size_t>(operand), sizeof(x86CondName)); 333 buf += x86CondName[operand]; 334 break; 335 case 'd': 336 buf += StringPrintf("%d", operand); 337 break; 338 case 'q': { 339 int64_t value = static_cast<int64_t>(static_cast<int64_t>(operand) << 32 | 340 static_cast<uint32_t>(lir->operands[operand_number+1])); 341 buf +=StringPrintf("%" PRId64, value); 342 } 343 case 'p': { 344 EmbeddedData *tab_rec = reinterpret_cast<EmbeddedData*>(UnwrapPointer(operand)); 345 buf += StringPrintf("0x%08x", tab_rec->offset); 346 break; 347 } 348 case 'r': 349 if (RegStorage::IsFloat(operand)) { 350 int fp_reg = RegStorage::RegNum(operand); 351 buf += StringPrintf("xmm%d", fp_reg); 352 } else { 353 int reg_num = RegStorage::RegNum(operand); 354 DCHECK_LT(static_cast<size_t>(reg_num), sizeof(x86RegName)); 355 buf += x86RegName[reg_num]; 356 } 357 break; 358 case 't': 359 buf += StringPrintf("0x%08" PRIxPTR " (L%p)", 360 reinterpret_cast<uintptr_t>(base_addr) + lir->offset + operand, 361 lir->target); 362 break; 363 default: 364 buf += StringPrintf("DecodeError '%c'", fmt[i]); 365 break; 366 } 367 i++; 368 } 369 } 370 } 371 return buf; 372} 373 374void X86Mir2Lir::DumpResourceMask(LIR *x86LIR, const ResourceMask& mask, const char *prefix) { 375 char buf[256]; 376 buf[0] = 0; 377 378 if (mask.Equals(kEncodeAll)) { 379 strcpy(buf, "all"); 380 } else { 381 char num[8]; 382 int i; 383 384 for (i = 0; i < kX86RegEnd; i++) { 385 if (mask.HasBit(i)) { 386 snprintf(num, arraysize(num), "%d ", i); 387 strcat(buf, num); 388 } 389 } 390 391 if (mask.HasBit(ResourceMask::kCCode)) { 392 strcat(buf, "cc "); 393 } 394 /* Memory bits */ 395 if (x86LIR && (mask.HasBit(ResourceMask::kDalvikReg))) { 396 snprintf(buf + strlen(buf), arraysize(buf) - strlen(buf), "dr%d%s", 397 DECODE_ALIAS_INFO_REG(x86LIR->flags.alias_info), 398 (DECODE_ALIAS_INFO_WIDE(x86LIR->flags.alias_info)) ? "(+1)" : ""); 399 } 400 if (mask.HasBit(ResourceMask::kLiteral)) { 401 strcat(buf, "lit "); 402 } 403 404 if (mask.HasBit(ResourceMask::kHeapRef)) { 405 strcat(buf, "heap "); 406 } 407 if (mask.HasBit(ResourceMask::kMustNotAlias)) { 408 strcat(buf, "noalias "); 409 } 410 } 411 if (buf[0]) { 412 LOG(INFO) << prefix << ": " << buf; 413 } 414} 415 416void X86Mir2Lir::AdjustSpillMask() { 417 // Adjustment for LR spilling, x86 has no LR so nothing to do here 418 core_spill_mask_ |= (1 << rs_rRET.GetRegNum()); 419 num_core_spills_++; 420} 421 422RegStorage X86Mir2Lir::AllocateByteRegister() { 423 RegStorage reg = AllocTypedTemp(false, kCoreReg); 424 if (!cu_->target64) { 425 DCHECK_LT(reg.GetRegNum(), rs_rX86_SP.GetRegNum()); 426 } 427 return reg; 428} 429 430bool X86Mir2Lir::IsByteRegister(RegStorage reg) { 431 return cu_->target64 || reg.GetRegNum() < rs_rX86_SP.GetRegNum(); 432} 433 434/* Clobber all regs that might be used by an external C call */ 435void X86Mir2Lir::ClobberCallerSave() { 436 Clobber(rs_rAX); 437 Clobber(rs_rCX); 438 Clobber(rs_rDX); 439 Clobber(rs_rBX); 440 441 Clobber(rs_fr0); 442 Clobber(rs_fr1); 443 Clobber(rs_fr2); 444 Clobber(rs_fr3); 445 Clobber(rs_fr4); 446 Clobber(rs_fr5); 447 Clobber(rs_fr6); 448 Clobber(rs_fr7); 449 450 if (cu_->target64) { 451 Clobber(rs_r8); 452 Clobber(rs_r9); 453 Clobber(rs_r10); 454 Clobber(rs_r11); 455 456 Clobber(rs_fr8); 457 Clobber(rs_fr9); 458 Clobber(rs_fr10); 459 Clobber(rs_fr11); 460 Clobber(rs_fr12); 461 Clobber(rs_fr13); 462 Clobber(rs_fr14); 463 Clobber(rs_fr15); 464 } 465} 466 467RegLocation X86Mir2Lir::GetReturnWideAlt() { 468 RegLocation res = LocCReturnWide(); 469 DCHECK(res.reg.GetLowReg() == rs_rAX.GetReg()); 470 DCHECK(res.reg.GetHighReg() == rs_rDX.GetReg()); 471 Clobber(rs_rAX); 472 Clobber(rs_rDX); 473 MarkInUse(rs_rAX); 474 MarkInUse(rs_rDX); 475 MarkWide(res.reg); 476 return res; 477} 478 479RegLocation X86Mir2Lir::GetReturnAlt() { 480 RegLocation res = LocCReturn(); 481 res.reg.SetReg(rs_rDX.GetReg()); 482 Clobber(rs_rDX); 483 MarkInUse(rs_rDX); 484 return res; 485} 486 487/* To be used when explicitly managing register use */ 488void X86Mir2Lir::LockCallTemps() { 489 LockTemp(rs_rX86_ARG0); 490 LockTemp(rs_rX86_ARG1); 491 LockTemp(rs_rX86_ARG2); 492 LockTemp(rs_rX86_ARG3); 493 if (cu_->target64) { 494 LockTemp(rs_rX86_ARG4); 495 LockTemp(rs_rX86_ARG5); 496 LockTemp(rs_rX86_FARG0); 497 LockTemp(rs_rX86_FARG1); 498 LockTemp(rs_rX86_FARG2); 499 LockTemp(rs_rX86_FARG3); 500 LockTemp(rs_rX86_FARG4); 501 LockTemp(rs_rX86_FARG5); 502 LockTemp(rs_rX86_FARG6); 503 LockTemp(rs_rX86_FARG7); 504 } 505} 506 507/* To be used when explicitly managing register use */ 508void X86Mir2Lir::FreeCallTemps() { 509 FreeTemp(rs_rX86_ARG0); 510 FreeTemp(rs_rX86_ARG1); 511 FreeTemp(rs_rX86_ARG2); 512 FreeTemp(rs_rX86_ARG3); 513 if (cu_->target64) { 514 FreeTemp(rs_rX86_ARG4); 515 FreeTemp(rs_rX86_ARG5); 516 FreeTemp(rs_rX86_FARG0); 517 FreeTemp(rs_rX86_FARG1); 518 FreeTemp(rs_rX86_FARG2); 519 FreeTemp(rs_rX86_FARG3); 520 FreeTemp(rs_rX86_FARG4); 521 FreeTemp(rs_rX86_FARG5); 522 FreeTemp(rs_rX86_FARG6); 523 FreeTemp(rs_rX86_FARG7); 524 } 525} 526 527bool X86Mir2Lir::ProvidesFullMemoryBarrier(X86OpCode opcode) { 528 switch (opcode) { 529 case kX86LockCmpxchgMR: 530 case kX86LockCmpxchgAR: 531 case kX86LockCmpxchg64M: 532 case kX86LockCmpxchg64A: 533 case kX86XchgMR: 534 case kX86Mfence: 535 // Atomic memory instructions provide full barrier. 536 return true; 537 default: 538 break; 539 } 540 541 // Conservative if cannot prove it provides full barrier. 542 return false; 543} 544 545bool X86Mir2Lir::GenMemBarrier(MemBarrierKind barrier_kind) { 546#if ANDROID_SMP != 0 547 // Start off with using the last LIR as the barrier. If it is not enough, then we will update it. 548 LIR* mem_barrier = last_lir_insn_; 549 550 bool ret = false; 551 /* 552 * According to the JSR-133 Cookbook, for x86 only StoreLoad barriers need memory fence. All other barriers 553 * (LoadLoad, LoadStore, StoreStore) are nops due to the x86 memory model. For those cases, all we need 554 * to ensure is that there is a scheduling barrier in place. 555 */ 556 if (barrier_kind == kStoreLoad) { 557 // If no LIR exists already that can be used a barrier, then generate an mfence. 558 if (mem_barrier == nullptr) { 559 mem_barrier = NewLIR0(kX86Mfence); 560 ret = true; 561 } 562 563 // If last instruction does not provide full barrier, then insert an mfence. 564 if (ProvidesFullMemoryBarrier(static_cast<X86OpCode>(mem_barrier->opcode)) == false) { 565 mem_barrier = NewLIR0(kX86Mfence); 566 ret = true; 567 } 568 } 569 570 // Now ensure that a scheduling barrier is in place. 571 if (mem_barrier == nullptr) { 572 GenBarrier(); 573 } else { 574 // Mark as a scheduling barrier. 575 DCHECK(!mem_barrier->flags.use_def_invalid); 576 mem_barrier->u.m.def_mask = &kEncodeAll; 577 } 578 return ret; 579#else 580 return false; 581#endif 582} 583 584void X86Mir2Lir::CompilerInitializeRegAlloc() { 585 if (cu_->target64) { 586 reg_pool_ = new (arena_) RegisterPool(this, arena_, core_regs_64, core_regs_64q, sp_regs_64, 587 dp_regs_64, reserved_regs_64, reserved_regs_64q, 588 core_temps_64, core_temps_64q, sp_temps_64, dp_temps_64); 589 } else { 590 reg_pool_ = new (arena_) RegisterPool(this, arena_, core_regs_32, empty_pool, sp_regs_32, 591 dp_regs_32, reserved_regs_32, empty_pool, 592 core_temps_32, empty_pool, sp_temps_32, dp_temps_32); 593 } 594 595 // Target-specific adjustments. 596 597 // Add in XMM registers. 598 const ArrayRef<const RegStorage> *xp_temps = cu_->target64 ? &xp_temps_64 : &xp_temps_32; 599 for (RegStorage reg : *xp_temps) { 600 RegisterInfo* info = new (arena_) RegisterInfo(reg, GetRegMaskCommon(reg)); 601 reginfo_map_.Put(reg.GetReg(), info); 602 info->SetIsTemp(true); 603 } 604 605 // Alias single precision xmm to double xmms. 606 // TODO: as needed, add larger vector sizes - alias all to the largest. 607 GrowableArray<RegisterInfo*>::Iterator it(®_pool_->sp_regs_); 608 for (RegisterInfo* info = it.Next(); info != nullptr; info = it.Next()) { 609 int sp_reg_num = info->GetReg().GetRegNum(); 610 RegStorage xp_reg = RegStorage::Solo128(sp_reg_num); 611 RegisterInfo* xp_reg_info = GetRegInfo(xp_reg); 612 // 128-bit xmm vector register's master storage should refer to itself. 613 DCHECK_EQ(xp_reg_info, xp_reg_info->Master()); 614 615 // Redirect 32-bit vector's master storage to 128-bit vector. 616 info->SetMaster(xp_reg_info); 617 618 RegStorage dp_reg = RegStorage::FloatSolo64(sp_reg_num); 619 RegisterInfo* dp_reg_info = GetRegInfo(dp_reg); 620 // Redirect 64-bit vector's master storage to 128-bit vector. 621 dp_reg_info->SetMaster(xp_reg_info); 622 // Singles should show a single 32-bit mask bit, at first referring to the low half. 623 DCHECK_EQ(info->StorageMask(), 0x1U); 624 } 625 626 if (cu_->target64) { 627 // Alias 32bit W registers to corresponding 64bit X registers. 628 GrowableArray<RegisterInfo*>::Iterator w_it(®_pool_->core_regs_); 629 for (RegisterInfo* info = w_it.Next(); info != nullptr; info = w_it.Next()) { 630 int x_reg_num = info->GetReg().GetRegNum(); 631 RegStorage x_reg = RegStorage::Solo64(x_reg_num); 632 RegisterInfo* x_reg_info = GetRegInfo(x_reg); 633 // 64bit X register's master storage should refer to itself. 634 DCHECK_EQ(x_reg_info, x_reg_info->Master()); 635 // Redirect 32bit W master storage to 64bit X. 636 info->SetMaster(x_reg_info); 637 // 32bit W should show a single 32-bit mask bit, at first referring to the low half. 638 DCHECK_EQ(info->StorageMask(), 0x1U); 639 } 640 } 641 642 // Don't start allocating temps at r0/s0/d0 or you may clobber return regs in early-exit methods. 643 // TODO: adjust for x86/hard float calling convention. 644 reg_pool_->next_core_reg_ = 2; 645 reg_pool_->next_sp_reg_ = 2; 646 reg_pool_->next_dp_reg_ = 1; 647} 648 649void X86Mir2Lir::SpillCoreRegs() { 650 if (num_core_spills_ == 0) { 651 return; 652 } 653 // Spill mask not including fake return address register 654 uint32_t mask = core_spill_mask_ & ~(1 << rs_rRET.GetRegNum()); 655 int offset = frame_size_ - (GetInstructionSetPointerSize(cu_->instruction_set) * num_core_spills_); 656 for (int reg = 0; mask; mask >>= 1, reg++) { 657 if (mask & 0x1) { 658 StoreWordDisp(rs_rX86_SP, offset, RegStorage::Solo32(reg)); 659 offset += GetInstructionSetPointerSize(cu_->instruction_set); 660 } 661 } 662} 663 664void X86Mir2Lir::UnSpillCoreRegs() { 665 if (num_core_spills_ == 0) { 666 return; 667 } 668 // Spill mask not including fake return address register 669 uint32_t mask = core_spill_mask_ & ~(1 << rs_rRET.GetRegNum()); 670 int offset = frame_size_ - (GetInstructionSetPointerSize(cu_->instruction_set) * num_core_spills_); 671 for (int reg = 0; mask; mask >>= 1, reg++) { 672 if (mask & 0x1) { 673 LoadWordDisp(rs_rX86_SP, offset, RegStorage::Solo32(reg)); 674 offset += GetInstructionSetPointerSize(cu_->instruction_set); 675 } 676 } 677} 678 679bool X86Mir2Lir::IsUnconditionalBranch(LIR* lir) { 680 return (lir->opcode == kX86Jmp8 || lir->opcode == kX86Jmp32); 681} 682 683bool X86Mir2Lir::SupportsVolatileLoadStore(OpSize size) { 684 return true; 685} 686 687RegisterClass X86Mir2Lir::RegClassForFieldLoadStore(OpSize size, bool is_volatile) { 688 // X86_64 can handle any size. 689 if (cu_->target64) { 690 if (size == kReference) { 691 return kRefReg; 692 } 693 return kCoreReg; 694 } 695 696 if (UNLIKELY(is_volatile)) { 697 // On x86, atomic 64-bit load/store requires an fp register. 698 // Smaller aligned load/store is atomic for both core and fp registers. 699 if (size == k64 || size == kDouble) { 700 return kFPReg; 701 } 702 } 703 return RegClassBySize(size); 704} 705 706X86Mir2Lir::X86Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena) 707 : Mir2Lir(cu, mir_graph, arena), 708 base_of_code_(nullptr), store_method_addr_(false), store_method_addr_used_(false), 709 method_address_insns_(arena, 100, kGrowableArrayMisc), 710 class_type_address_insns_(arena, 100, kGrowableArrayMisc), 711 call_method_insns_(arena, 100, kGrowableArrayMisc), 712 stack_decrement_(nullptr), stack_increment_(nullptr), 713 const_vectors_(nullptr) { 714 store_method_addr_used_ = false; 715 if (kIsDebugBuild) { 716 for (int i = 0; i < kX86Last; i++) { 717 if (X86Mir2Lir::EncodingMap[i].opcode != i) { 718 LOG(FATAL) << "Encoding order for " << X86Mir2Lir::EncodingMap[i].name 719 << " is wrong: expecting " << i << ", seeing " 720 << static_cast<int>(X86Mir2Lir::EncodingMap[i].opcode); 721 } 722 } 723 } 724 if (cu_->target64) { 725 rs_rX86_SP = rs_rX86_SP_64; 726 727 rs_rX86_ARG0 = rs_rDI; 728 rs_rX86_ARG1 = rs_rSI; 729 rs_rX86_ARG2 = rs_rDX; 730 rs_rX86_ARG3 = rs_rCX; 731 rs_rX86_ARG4 = rs_r8; 732 rs_rX86_ARG5 = rs_r9; 733 rs_rX86_FARG0 = rs_fr0; 734 rs_rX86_FARG1 = rs_fr1; 735 rs_rX86_FARG2 = rs_fr2; 736 rs_rX86_FARG3 = rs_fr3; 737 rs_rX86_FARG4 = rs_fr4; 738 rs_rX86_FARG5 = rs_fr5; 739 rs_rX86_FARG6 = rs_fr6; 740 rs_rX86_FARG7 = rs_fr7; 741 rX86_ARG0 = rDI; 742 rX86_ARG1 = rSI; 743 rX86_ARG2 = rDX; 744 rX86_ARG3 = rCX; 745 rX86_ARG4 = r8; 746 rX86_ARG5 = r9; 747 rX86_FARG0 = fr0; 748 rX86_FARG1 = fr1; 749 rX86_FARG2 = fr2; 750 rX86_FARG3 = fr3; 751 rX86_FARG4 = fr4; 752 rX86_FARG5 = fr5; 753 rX86_FARG6 = fr6; 754 rX86_FARG7 = fr7; 755 rs_rX86_INVOKE_TGT = rs_rDI; 756 } else { 757 rs_rX86_SP = rs_rX86_SP_32; 758 759 rs_rX86_ARG0 = rs_rAX; 760 rs_rX86_ARG1 = rs_rCX; 761 rs_rX86_ARG2 = rs_rDX; 762 rs_rX86_ARG3 = rs_rBX; 763 rs_rX86_ARG4 = RegStorage::InvalidReg(); 764 rs_rX86_ARG5 = RegStorage::InvalidReg(); 765 rs_rX86_FARG0 = rs_rAX; 766 rs_rX86_FARG1 = rs_rCX; 767 rs_rX86_FARG2 = rs_rDX; 768 rs_rX86_FARG3 = rs_rBX; 769 rs_rX86_FARG4 = RegStorage::InvalidReg(); 770 rs_rX86_FARG5 = RegStorage::InvalidReg(); 771 rs_rX86_FARG6 = RegStorage::InvalidReg(); 772 rs_rX86_FARG7 = RegStorage::InvalidReg(); 773 rX86_ARG0 = rAX; 774 rX86_ARG1 = rCX; 775 rX86_ARG2 = rDX; 776 rX86_ARG3 = rBX; 777 rX86_FARG0 = rAX; 778 rX86_FARG1 = rCX; 779 rX86_FARG2 = rDX; 780 rX86_FARG3 = rBX; 781 rs_rX86_INVOKE_TGT = rs_rAX; 782 // TODO(64): Initialize with invalid reg 783// rX86_ARG4 = RegStorage::InvalidReg(); 784// rX86_ARG5 = RegStorage::InvalidReg(); 785 } 786 rs_rX86_RET0 = rs_rAX; 787 rs_rX86_RET1 = rs_rDX; 788 rs_rX86_COUNT = rs_rCX; 789 rX86_RET0 = rAX; 790 rX86_RET1 = rDX; 791 rX86_INVOKE_TGT = rAX; 792 rX86_COUNT = rCX; 793} 794 795Mir2Lir* X86CodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, 796 ArenaAllocator* const arena) { 797 return new X86Mir2Lir(cu, mir_graph, arena); 798} 799 800// Not used in x86 801RegStorage X86Mir2Lir::LoadHelper(ThreadOffset<4> offset) { 802 LOG(FATAL) << "Unexpected use of LoadHelper in x86"; 803 return RegStorage::InvalidReg(); 804} 805 806// Not used in x86 807RegStorage X86Mir2Lir::LoadHelper(ThreadOffset<8> offset) { 808 LOG(FATAL) << "Unexpected use of LoadHelper in x86"; 809 return RegStorage::InvalidReg(); 810} 811 812LIR* X86Mir2Lir::CheckSuspendUsingLoad() { 813 LOG(FATAL) << "Unexpected use of CheckSuspendUsingLoad in x86"; 814 return nullptr; 815} 816 817uint64_t X86Mir2Lir::GetTargetInstFlags(int opcode) { 818 DCHECK(!IsPseudoLirOp(opcode)); 819 return X86Mir2Lir::EncodingMap[opcode].flags; 820} 821 822const char* X86Mir2Lir::GetTargetInstName(int opcode) { 823 DCHECK(!IsPseudoLirOp(opcode)); 824 return X86Mir2Lir::EncodingMap[opcode].name; 825} 826 827const char* X86Mir2Lir::GetTargetInstFmt(int opcode) { 828 DCHECK(!IsPseudoLirOp(opcode)); 829 return X86Mir2Lir::EncodingMap[opcode].fmt; 830} 831 832void X86Mir2Lir::GenConstWide(RegLocation rl_dest, int64_t value) { 833 // Can we do this directly to memory? 834 rl_dest = UpdateLocWide(rl_dest); 835 if ((rl_dest.location == kLocDalvikFrame) || 836 (rl_dest.location == kLocCompilerTemp)) { 837 int32_t val_lo = Low32Bits(value); 838 int32_t val_hi = High32Bits(value); 839 int r_base = rs_rX86_SP.GetReg(); 840 int displacement = SRegOffset(rl_dest.s_reg_low); 841 842 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); 843 LIR * store = NewLIR3(kX86Mov32MI, r_base, displacement + LOWORD_OFFSET, val_lo); 844 AnnotateDalvikRegAccess(store, (displacement + LOWORD_OFFSET) >> 2, 845 false /* is_load */, true /* is64bit */); 846 store = NewLIR3(kX86Mov32MI, r_base, displacement + HIWORD_OFFSET, val_hi); 847 AnnotateDalvikRegAccess(store, (displacement + HIWORD_OFFSET) >> 2, 848 false /* is_load */, true /* is64bit */); 849 return; 850 } 851 852 // Just use the standard code to do the generation. 853 Mir2Lir::GenConstWide(rl_dest, value); 854} 855 856// TODO: Merge with existing RegLocation dumper in vreg_analysis.cc 857void X86Mir2Lir::DumpRegLocation(RegLocation loc) { 858 LOG(INFO) << "location: " << loc.location << ',' 859 << (loc.wide ? " w" : " ") 860 << (loc.defined ? " D" : " ") 861 << (loc.is_const ? " c" : " ") 862 << (loc.fp ? " F" : " ") 863 << (loc.core ? " C" : " ") 864 << (loc.ref ? " r" : " ") 865 << (loc.high_word ? " h" : " ") 866 << (loc.home ? " H" : " ") 867 << ", low: " << static_cast<int>(loc.reg.GetLowReg()) 868 << ", high: " << static_cast<int>(loc.reg.GetHighReg()) 869 << ", s_reg: " << loc.s_reg_low 870 << ", orig: " << loc.orig_sreg; 871} 872 873void X86Mir2Lir::Materialize() { 874 // A good place to put the analysis before starting. 875 AnalyzeMIR(); 876 877 // Now continue with regular code generation. 878 Mir2Lir::Materialize(); 879} 880 881void X86Mir2Lir::LoadMethodAddress(const MethodReference& target_method, InvokeType type, 882 SpecialTargetRegister symbolic_reg) { 883 /* 884 * For x86, just generate a 32 bit move immediate instruction, that will be filled 885 * in at 'link time'. For now, put a unique value based on target to ensure that 886 * code deduplication works. 887 */ 888 int target_method_idx = target_method.dex_method_index; 889 const DexFile* target_dex_file = target_method.dex_file; 890 const DexFile::MethodId& target_method_id = target_dex_file->GetMethodId(target_method_idx); 891 uintptr_t target_method_id_ptr = reinterpret_cast<uintptr_t>(&target_method_id); 892 893 // Generate the move instruction with the unique pointer and save index, dex_file, and type. 894 LIR *move = RawLIR(current_dalvik_offset_, kX86Mov32RI, TargetReg(symbolic_reg, false).GetReg(), 895 static_cast<int>(target_method_id_ptr), target_method_idx, 896 WrapPointer(const_cast<DexFile*>(target_dex_file)), type); 897 AppendLIR(move); 898 method_address_insns_.Insert(move); 899} 900 901void X86Mir2Lir::LoadClassType(uint32_t type_idx, SpecialTargetRegister symbolic_reg) { 902 /* 903 * For x86, just generate a 32 bit move immediate instruction, that will be filled 904 * in at 'link time'. For now, put a unique value based on target to ensure that 905 * code deduplication works. 906 */ 907 const DexFile::TypeId& id = cu_->dex_file->GetTypeId(type_idx); 908 uintptr_t ptr = reinterpret_cast<uintptr_t>(&id); 909 910 // Generate the move instruction with the unique pointer and save index and type. 911 LIR *move = RawLIR(current_dalvik_offset_, kX86Mov32RI, TargetReg(symbolic_reg, false).GetReg(), 912 static_cast<int>(ptr), type_idx); 913 AppendLIR(move); 914 class_type_address_insns_.Insert(move); 915} 916 917LIR *X86Mir2Lir::CallWithLinkerFixup(const MethodReference& target_method, InvokeType type) { 918 /* 919 * For x86, just generate a 32 bit call relative instruction, that will be filled 920 * in at 'link time'. For now, put a unique value based on target to ensure that 921 * code deduplication works. 922 */ 923 int target_method_idx = target_method.dex_method_index; 924 const DexFile* target_dex_file = target_method.dex_file; 925 const DexFile::MethodId& target_method_id = target_dex_file->GetMethodId(target_method_idx); 926 uintptr_t target_method_id_ptr = reinterpret_cast<uintptr_t>(&target_method_id); 927 928 // Generate the call instruction with the unique pointer and save index, dex_file, and type. 929 LIR *call = RawLIR(current_dalvik_offset_, kX86CallI, static_cast<int>(target_method_id_ptr), 930 target_method_idx, WrapPointer(const_cast<DexFile*>(target_dex_file)), type); 931 AppendLIR(call); 932 call_method_insns_.Insert(call); 933 return call; 934} 935 936/* 937 * @brief Enter a 32 bit quantity into a buffer 938 * @param buf buffer. 939 * @param data Data value. 940 */ 941 942static void PushWord(std::vector<uint8_t>&buf, int32_t data) { 943 buf.push_back(data & 0xff); 944 buf.push_back((data >> 8) & 0xff); 945 buf.push_back((data >> 16) & 0xff); 946 buf.push_back((data >> 24) & 0xff); 947} 948 949void X86Mir2Lir::InstallLiteralPools() { 950 // These are handled differently for x86. 951 DCHECK(code_literal_list_ == nullptr); 952 DCHECK(method_literal_list_ == nullptr); 953 DCHECK(class_literal_list_ == nullptr); 954 955 // Align to 16 byte boundary. We have implicit knowledge that the start of the method is 956 // on a 4 byte boundary. How can I check this if it changes (other than aligned loads 957 // will fail at runtime)? 958 if (const_vectors_ != nullptr) { 959 int align_size = (16-4) - (code_buffer_.size() & 0xF); 960 if (align_size < 0) { 961 align_size += 16; 962 } 963 964 while (align_size > 0) { 965 code_buffer_.push_back(0); 966 align_size--; 967 } 968 for (LIR *p = const_vectors_; p != nullptr; p = p->next) { 969 PushWord(code_buffer_, p->operands[0]); 970 PushWord(code_buffer_, p->operands[1]); 971 PushWord(code_buffer_, p->operands[2]); 972 PushWord(code_buffer_, p->operands[3]); 973 } 974 } 975 976 // Handle the fixups for methods. 977 for (uint32_t i = 0; i < method_address_insns_.Size(); i++) { 978 LIR* p = method_address_insns_.Get(i); 979 DCHECK_EQ(p->opcode, kX86Mov32RI); 980 uint32_t target_method_idx = p->operands[2]; 981 const DexFile* target_dex_file = 982 reinterpret_cast<const DexFile*>(UnwrapPointer(p->operands[3])); 983 984 // The offset to patch is the last 4 bytes of the instruction. 985 int patch_offset = p->offset + p->flags.size - 4; 986 cu_->compiler_driver->AddMethodPatch(cu_->dex_file, cu_->class_def_idx, 987 cu_->method_idx, cu_->invoke_type, 988 target_method_idx, target_dex_file, 989 static_cast<InvokeType>(p->operands[4]), 990 patch_offset); 991 } 992 993 // Handle the fixups for class types. 994 for (uint32_t i = 0; i < class_type_address_insns_.Size(); i++) { 995 LIR* p = class_type_address_insns_.Get(i); 996 DCHECK_EQ(p->opcode, kX86Mov32RI); 997 uint32_t target_method_idx = p->operands[2]; 998 999 // The offset to patch is the last 4 bytes of the instruction. 1000 int patch_offset = p->offset + p->flags.size - 4; 1001 cu_->compiler_driver->AddClassPatch(cu_->dex_file, cu_->class_def_idx, 1002 cu_->method_idx, target_method_idx, patch_offset); 1003 } 1004 1005 // And now the PC-relative calls to methods. 1006 for (uint32_t i = 0; i < call_method_insns_.Size(); i++) { 1007 LIR* p = call_method_insns_.Get(i); 1008 DCHECK_EQ(p->opcode, kX86CallI); 1009 uint32_t target_method_idx = p->operands[1]; 1010 const DexFile* target_dex_file = 1011 reinterpret_cast<const DexFile*>(UnwrapPointer(p->operands[2])); 1012 1013 // The offset to patch is the last 4 bytes of the instruction. 1014 int patch_offset = p->offset + p->flags.size - 4; 1015 cu_->compiler_driver->AddRelativeCodePatch(cu_->dex_file, cu_->class_def_idx, 1016 cu_->method_idx, cu_->invoke_type, 1017 target_method_idx, target_dex_file, 1018 static_cast<InvokeType>(p->operands[3]), 1019 patch_offset, -4 /* offset */); 1020 } 1021 1022 // And do the normal processing. 1023 Mir2Lir::InstallLiteralPools(); 1024} 1025 1026/* 1027 * Fast string.index_of(I) & (II). Inline check for simple case of char <= 0xffff, 1028 * otherwise bails to standard library code. 1029 */ 1030bool X86Mir2Lir::GenInlinedIndexOf(CallInfo* info, bool zero_based) { 1031 ClobberCallerSave(); 1032 LockCallTemps(); // Using fixed registers 1033 1034 // EAX: 16 bit character being searched. 1035 // ECX: count: number of words to be searched. 1036 // EDI: String being searched. 1037 // EDX: temporary during execution. 1038 // EBX or R11: temporary during execution (depending on mode). 1039 1040 RegLocation rl_obj = info->args[0]; 1041 RegLocation rl_char = info->args[1]; 1042 RegLocation rl_start; // Note: only present in III flavor or IndexOf. 1043 RegStorage tmpReg = cu_->target64 ? rs_r11 : rs_rBX; 1044 1045 uint32_t char_value = 1046 rl_char.is_const ? mir_graph_->ConstantValue(rl_char.orig_sreg) : 0; 1047 1048 if (char_value > 0xFFFF) { 1049 // We have to punt to the real String.indexOf. 1050 return false; 1051 } 1052 1053 // Okay, we are commited to inlining this. 1054 RegLocation rl_return = GetReturn(kCoreReg); 1055 RegLocation rl_dest = InlineTarget(info); 1056 1057 // Is the string non-NULL? 1058 LoadValueDirectFixed(rl_obj, rs_rDX); 1059 GenNullCheck(rs_rDX, info->opt_flags); 1060 info->opt_flags |= MIR_IGNORE_NULL_CHECK; // Record that we've null checked. 1061 1062 // Does the character fit in 16 bits? 1063 LIR* slowpath_branch = nullptr; 1064 if (rl_char.is_const) { 1065 // We need the value in EAX. 1066 LoadConstantNoClobber(rs_rAX, char_value); 1067 } else { 1068 // Character is not a constant; compare at runtime. 1069 LoadValueDirectFixed(rl_char, rs_rAX); 1070 slowpath_branch = OpCmpImmBranch(kCondGt, rs_rAX, 0xFFFF, nullptr); 1071 } 1072 1073 // From here down, we know that we are looking for a char that fits in 16 bits. 1074 // Location of reference to data array within the String object. 1075 int value_offset = mirror::String::ValueOffset().Int32Value(); 1076 // Location of count within the String object. 1077 int count_offset = mirror::String::CountOffset().Int32Value(); 1078 // Starting offset within data array. 1079 int offset_offset = mirror::String::OffsetOffset().Int32Value(); 1080 // Start of char data with array_. 1081 int data_offset = mirror::Array::DataOffset(sizeof(uint16_t)).Int32Value(); 1082 1083 // Character is in EAX. 1084 // Object pointer is in EDX. 1085 1086 // We need to preserve EDI, but have no spare registers, so push it on the stack. 1087 // We have to remember that all stack addresses after this are offset by sizeof(EDI). 1088 NewLIR1(kX86Push32R, rs_rDI.GetReg()); 1089 1090 // Compute the number of words to search in to rCX. 1091 Load32Disp(rs_rDX, count_offset, rs_rCX); 1092 LIR *length_compare = nullptr; 1093 int start_value = 0; 1094 bool is_index_on_stack = false; 1095 if (zero_based) { 1096 // We have to handle an empty string. Use special instruction JECXZ. 1097 length_compare = NewLIR0(kX86Jecxz8); 1098 } else { 1099 rl_start = info->args[2]; 1100 // We have to offset by the start index. 1101 if (rl_start.is_const) { 1102 start_value = mir_graph_->ConstantValue(rl_start.orig_sreg); 1103 start_value = std::max(start_value, 0); 1104 1105 // Is the start > count? 1106 length_compare = OpCmpImmBranch(kCondLe, rs_rCX, start_value, nullptr); 1107 1108 if (start_value != 0) { 1109 OpRegImm(kOpSub, rs_rCX, start_value); 1110 } 1111 } else { 1112 // Runtime start index. 1113 rl_start = UpdateLocTyped(rl_start, kCoreReg); 1114 if (rl_start.location == kLocPhysReg) { 1115 // Handle "start index < 0" case. 1116 OpRegReg(kOpXor, tmpReg, tmpReg); 1117 OpRegReg(kOpCmp, rl_start.reg, tmpReg); 1118 OpCondRegReg(kOpCmov, kCondLt, rl_start.reg, tmpReg); 1119 1120 // The length of the string should be greater than the start index. 1121 length_compare = OpCmpBranch(kCondLe, rs_rCX, rl_start.reg, nullptr); 1122 OpRegReg(kOpSub, rs_rCX, rl_start.reg); 1123 if (rl_start.reg == rs_rDI) { 1124 // The special case. We will use EDI further, so lets put start index to stack. 1125 NewLIR1(kX86Push32R, rs_rDI.GetReg()); 1126 is_index_on_stack = true; 1127 } 1128 } else { 1129 // Load the start index from stack, remembering that we pushed EDI. 1130 int displacement = SRegOffset(rl_start.s_reg_low) + (cu_->target64 ? 2 : 1) * sizeof(uint32_t); 1131 { 1132 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); 1133 Load32Disp(rs_rX86_SP, displacement, tmpReg); 1134 } 1135 OpRegReg(kOpXor, rs_rDI, rs_rDI); 1136 OpRegReg(kOpCmp, tmpReg, rs_rDI); 1137 OpCondRegReg(kOpCmov, kCondLt, tmpReg, rs_rDI); 1138 1139 length_compare = OpCmpBranch(kCondLe, rs_rCX, tmpReg, nullptr); 1140 OpRegReg(kOpSub, rs_rCX, tmpReg); 1141 // Put the start index to stack. 1142 NewLIR1(kX86Push32R, tmpReg.GetReg()); 1143 is_index_on_stack = true; 1144 } 1145 } 1146 } 1147 DCHECK(length_compare != nullptr); 1148 1149 // ECX now contains the count in words to be searched. 1150 1151 // Load the address of the string into R11 or EBX (depending on mode). 1152 // The string starts at VALUE(String) + 2 * OFFSET(String) + DATA_OFFSET. 1153 Load32Disp(rs_rDX, value_offset, rs_rDI); 1154 Load32Disp(rs_rDX, offset_offset, tmpReg); 1155 OpLea(tmpReg, rs_rDI, tmpReg, 1, data_offset); 1156 1157 // Now compute into EDI where the search will start. 1158 if (zero_based || rl_start.is_const) { 1159 if (start_value == 0) { 1160 OpRegCopy(rs_rDI, tmpReg); 1161 } else { 1162 NewLIR3(kX86Lea32RM, rs_rDI.GetReg(), tmpReg.GetReg(), 2 * start_value); 1163 } 1164 } else { 1165 if (is_index_on_stack == true) { 1166 // Load the start index from stack. 1167 NewLIR1(kX86Pop32R, rs_rDX.GetReg()); 1168 OpLea(rs_rDI, tmpReg, rs_rDX, 1, 0); 1169 } else { 1170 OpLea(rs_rDI, tmpReg, rl_start.reg, 1, 0); 1171 } 1172 } 1173 1174 // EDI now contains the start of the string to be searched. 1175 // We are all prepared to do the search for the character. 1176 NewLIR0(kX86RepneScasw); 1177 1178 // Did we find a match? 1179 LIR* failed_branch = OpCondBranch(kCondNe, nullptr); 1180 1181 // yes, we matched. Compute the index of the result. 1182 // index = ((curr_ptr - orig_ptr) / 2) - 1. 1183 OpRegReg(kOpSub, rs_rDI, tmpReg); 1184 OpRegImm(kOpAsr, rs_rDI, 1); 1185 NewLIR3(kX86Lea32RM, rl_return.reg.GetReg(), rs_rDI.GetReg(), -1); 1186 LIR *all_done = NewLIR1(kX86Jmp8, 0); 1187 1188 // Failed to match; return -1. 1189 LIR *not_found = NewLIR0(kPseudoTargetLabel); 1190 length_compare->target = not_found; 1191 failed_branch->target = not_found; 1192 LoadConstantNoClobber(rl_return.reg, -1); 1193 1194 // And join up at the end. 1195 all_done->target = NewLIR0(kPseudoTargetLabel); 1196 // Restore EDI from the stack. 1197 NewLIR1(kX86Pop32R, rs_rDI.GetReg()); 1198 1199 // Out of line code returns here. 1200 if (slowpath_branch != nullptr) { 1201 LIR *return_point = NewLIR0(kPseudoTargetLabel); 1202 AddIntrinsicSlowPath(info, slowpath_branch, return_point); 1203 } 1204 1205 StoreValue(rl_dest, rl_return); 1206 return true; 1207} 1208 1209/* 1210 * @brief Enter an 'advance LOC' into the FDE buffer 1211 * @param buf FDE buffer. 1212 * @param increment Amount by which to increase the current location. 1213 */ 1214static void AdvanceLoc(std::vector<uint8_t>&buf, uint32_t increment) { 1215 if (increment < 64) { 1216 // Encoding in opcode. 1217 buf.push_back(0x1 << 6 | increment); 1218 } else if (increment < 256) { 1219 // Single byte delta. 1220 buf.push_back(0x02); 1221 buf.push_back(increment); 1222 } else if (increment < 256 * 256) { 1223 // Two byte delta. 1224 buf.push_back(0x03); 1225 buf.push_back(increment & 0xff); 1226 buf.push_back((increment >> 8) & 0xff); 1227 } else { 1228 // Four byte delta. 1229 buf.push_back(0x04); 1230 PushWord(buf, increment); 1231 } 1232} 1233 1234 1235std::vector<uint8_t>* X86CFIInitialization() { 1236 return X86Mir2Lir::ReturnCommonCallFrameInformation(); 1237} 1238 1239std::vector<uint8_t>* X86Mir2Lir::ReturnCommonCallFrameInformation() { 1240 std::vector<uint8_t>*cfi_info = new std::vector<uint8_t>; 1241 1242 // Length of the CIE (except for this field). 1243 PushWord(*cfi_info, 16); 1244 1245 // CIE id. 1246 PushWord(*cfi_info, 0xFFFFFFFFU); 1247 1248 // Version: 3. 1249 cfi_info->push_back(0x03); 1250 1251 // Augmentation: empty string. 1252 cfi_info->push_back(0x0); 1253 1254 // Code alignment: 1. 1255 cfi_info->push_back(0x01); 1256 1257 // Data alignment: -4. 1258 cfi_info->push_back(0x7C); 1259 1260 // Return address register (R8). 1261 cfi_info->push_back(0x08); 1262 1263 // Initial return PC is 4(ESP): DW_CFA_def_cfa R4 4. 1264 cfi_info->push_back(0x0C); 1265 cfi_info->push_back(0x04); 1266 cfi_info->push_back(0x04); 1267 1268 // Return address location: 0(SP): DW_CFA_offset R8 1 (* -4);. 1269 cfi_info->push_back(0x2 << 6 | 0x08); 1270 cfi_info->push_back(0x01); 1271 1272 // And 2 Noops to align to 4 byte boundary. 1273 cfi_info->push_back(0x0); 1274 cfi_info->push_back(0x0); 1275 1276 DCHECK_EQ(cfi_info->size() & 3, 0U); 1277 return cfi_info; 1278} 1279 1280static void EncodeUnsignedLeb128(std::vector<uint8_t>& buf, uint32_t value) { 1281 uint8_t buffer[12]; 1282 uint8_t *ptr = EncodeUnsignedLeb128(buffer, value); 1283 for (uint8_t *p = buffer; p < ptr; p++) { 1284 buf.push_back(*p); 1285 } 1286} 1287 1288std::vector<uint8_t>* X86Mir2Lir::ReturnCallFrameInformation() { 1289 std::vector<uint8_t>*cfi_info = new std::vector<uint8_t>; 1290 1291 // Generate the FDE for the method. 1292 DCHECK_NE(data_offset_, 0U); 1293 1294 // Length (will be filled in later in this routine). 1295 PushWord(*cfi_info, 0); 1296 1297 // CIE_pointer (can be filled in by linker); might be left at 0 if there is only 1298 // one CIE for the whole debug_frame section. 1299 PushWord(*cfi_info, 0); 1300 1301 // 'initial_location' (filled in by linker). 1302 PushWord(*cfi_info, 0); 1303 1304 // 'address_range' (number of bytes in the method). 1305 PushWord(*cfi_info, data_offset_); 1306 1307 // The instructions in the FDE. 1308 if (stack_decrement_ != nullptr) { 1309 // Advance LOC to just past the stack decrement. 1310 uint32_t pc = NEXT_LIR(stack_decrement_)->offset; 1311 AdvanceLoc(*cfi_info, pc); 1312 1313 // Now update the offset to the call frame: DW_CFA_def_cfa_offset frame_size. 1314 cfi_info->push_back(0x0e); 1315 EncodeUnsignedLeb128(*cfi_info, frame_size_); 1316 1317 // We continue with that stack until the epilogue. 1318 if (stack_increment_ != nullptr) { 1319 uint32_t new_pc = NEXT_LIR(stack_increment_)->offset; 1320 AdvanceLoc(*cfi_info, new_pc - pc); 1321 1322 // We probably have code snippets after the epilogue, so save the 1323 // current state: DW_CFA_remember_state. 1324 cfi_info->push_back(0x0a); 1325 1326 // We have now popped the stack: DW_CFA_def_cfa_offset 4. There is only the return 1327 // PC on the stack now. 1328 cfi_info->push_back(0x0e); 1329 EncodeUnsignedLeb128(*cfi_info, 4); 1330 1331 // Everything after that is the same as before the epilogue. 1332 // Stack bump was followed by RET instruction. 1333 LIR *post_ret_insn = NEXT_LIR(NEXT_LIR(stack_increment_)); 1334 if (post_ret_insn != nullptr) { 1335 pc = new_pc; 1336 new_pc = post_ret_insn->offset; 1337 AdvanceLoc(*cfi_info, new_pc - pc); 1338 // Restore the state: DW_CFA_restore_state. 1339 cfi_info->push_back(0x0b); 1340 } 1341 } 1342 } 1343 1344 // Padding to a multiple of 4 1345 while ((cfi_info->size() & 3) != 0) { 1346 // DW_CFA_nop is encoded as 0. 1347 cfi_info->push_back(0); 1348 } 1349 1350 // Set the length of the FDE inside the generated bytes. 1351 uint32_t length = cfi_info->size() - 4; 1352 (*cfi_info)[0] = length; 1353 (*cfi_info)[1] = length >> 8; 1354 (*cfi_info)[2] = length >> 16; 1355 (*cfi_info)[3] = length >> 24; 1356 return cfi_info; 1357} 1358 1359void X86Mir2Lir::GenMachineSpecificExtendedMethodMIR(BasicBlock* bb, MIR* mir) { 1360 switch (static_cast<ExtendedMIROpcode>(mir->dalvikInsn.opcode)) { 1361 case kMirOpConstVector: 1362 GenConst128(bb, mir); 1363 break; 1364 case kMirOpMoveVector: 1365 GenMoveVector(bb, mir); 1366 break; 1367 case kMirOpPackedMultiply: 1368 GenMultiplyVector(bb, mir); 1369 break; 1370 case kMirOpPackedAddition: 1371 GenAddVector(bb, mir); 1372 break; 1373 case kMirOpPackedSubtract: 1374 GenSubtractVector(bb, mir); 1375 break; 1376 case kMirOpPackedShiftLeft: 1377 GenShiftLeftVector(bb, mir); 1378 break; 1379 case kMirOpPackedSignedShiftRight: 1380 GenSignedShiftRightVector(bb, mir); 1381 break; 1382 case kMirOpPackedUnsignedShiftRight: 1383 GenUnsignedShiftRightVector(bb, mir); 1384 break; 1385 case kMirOpPackedAnd: 1386 GenAndVector(bb, mir); 1387 break; 1388 case kMirOpPackedOr: 1389 GenOrVector(bb, mir); 1390 break; 1391 case kMirOpPackedXor: 1392 GenXorVector(bb, mir); 1393 break; 1394 case kMirOpPackedAddReduce: 1395 GenAddReduceVector(bb, mir); 1396 break; 1397 case kMirOpPackedReduce: 1398 GenReduceVector(bb, mir); 1399 break; 1400 case kMirOpPackedSet: 1401 GenSetVector(bb, mir); 1402 break; 1403 default: 1404 break; 1405 } 1406} 1407 1408void X86Mir2Lir::GenConst128(BasicBlock* bb, MIR* mir) { 1409 int type_size = mir->dalvikInsn.vA; 1410 // We support 128 bit vectors. 1411 DCHECK_EQ(type_size & 0xFFFF, 128); 1412 RegStorage rs_dest = RegStorage::Solo128(mir->dalvikInsn.vB); 1413 uint32_t *args = mir->dalvikInsn.arg; 1414 int reg = rs_dest.GetReg(); 1415 // Check for all 0 case. 1416 if (args[0] == 0 && args[1] == 0 && args[2] == 0 && args[3] == 0) { 1417 NewLIR2(kX86XorpsRR, reg, reg); 1418 return; 1419 } 1420 // Okay, load it from the constant vector area. 1421 LIR *data_target = ScanVectorLiteral(mir); 1422 if (data_target == nullptr) { 1423 data_target = AddVectorLiteral(mir); 1424 } 1425 1426 // Address the start of the method. 1427 RegLocation rl_method = mir_graph_->GetRegLocation(base_of_code_->s_reg_low); 1428 if (rl_method.wide) { 1429 rl_method = LoadValueWide(rl_method, kCoreReg); 1430 } else { 1431 rl_method = LoadValue(rl_method, kCoreReg); 1432 } 1433 1434 // Load the proper value from the literal area. 1435 // We don't know the proper offset for the value, so pick one that will force 1436 // 4 byte offset. We will fix this up in the assembler later to have the right 1437 // value. 1438 ScopedMemRefType mem_ref_type(this, ResourceMask::kLiteral); 1439 LIR *load = NewLIR3(kX86Mova128RM, reg, rl_method.reg.GetReg(), 256 /* bogus */); 1440 load->flags.fixup = kFixupLoad; 1441 load->target = data_target; 1442} 1443 1444void X86Mir2Lir::GenMoveVector(BasicBlock *bb, MIR *mir) { 1445 // We only support 128 bit registers. 1446 DCHECK_EQ(mir->dalvikInsn.vA & 0xFFFF, 128U); 1447 RegStorage rs_dest = RegStorage::Solo128(mir->dalvikInsn.vB); 1448 RegStorage rs_src = RegStorage::Solo128(mir->dalvikInsn.vC); 1449 NewLIR2(kX86Mova128RR, rs_dest.GetReg(), rs_src.GetReg()); 1450} 1451 1452void X86Mir2Lir::GenMultiplyVector(BasicBlock *bb, MIR *mir) { 1453 DCHECK_EQ(mir->dalvikInsn.vA & 0xFFFF, 128U); 1454 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vA >> 16); 1455 RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vB); 1456 RegStorage rs_src2 = RegStorage::Solo128(mir->dalvikInsn.vC); 1457 int opcode = 0; 1458 switch (opsize) { 1459 case k32: 1460 opcode = kX86PmulldRR; 1461 break; 1462 case kSignedHalf: 1463 opcode = kX86PmullwRR; 1464 break; 1465 case kSingle: 1466 opcode = kX86MulpsRR; 1467 break; 1468 case kDouble: 1469 opcode = kX86MulpdRR; 1470 break; 1471 default: 1472 LOG(FATAL) << "Unsupported vector multiply " << opsize; 1473 break; 1474 } 1475 NewLIR2(opcode, rs_dest_src1.GetReg(), rs_src2.GetReg()); 1476} 1477 1478void X86Mir2Lir::GenAddVector(BasicBlock *bb, MIR *mir) { 1479 DCHECK_EQ(mir->dalvikInsn.vA & 0xFFFF, 128U); 1480 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vA >> 16); 1481 RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vB); 1482 RegStorage rs_src2 = RegStorage::Solo128(mir->dalvikInsn.vC); 1483 int opcode = 0; 1484 switch (opsize) { 1485 case k32: 1486 opcode = kX86PadddRR; 1487 break; 1488 case kSignedHalf: 1489 case kUnsignedHalf: 1490 opcode = kX86PaddwRR; 1491 break; 1492 case kUnsignedByte: 1493 case kSignedByte: 1494 opcode = kX86PaddbRR; 1495 break; 1496 case kSingle: 1497 opcode = kX86AddpsRR; 1498 break; 1499 case kDouble: 1500 opcode = kX86AddpdRR; 1501 break; 1502 default: 1503 LOG(FATAL) << "Unsupported vector addition " << opsize; 1504 break; 1505 } 1506 NewLIR2(opcode, rs_dest_src1.GetReg(), rs_src2.GetReg()); 1507} 1508 1509void X86Mir2Lir::GenSubtractVector(BasicBlock *bb, MIR *mir) { 1510 DCHECK_EQ(mir->dalvikInsn.vA & 0xFFFF, 128U); 1511 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vA >> 16); 1512 RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vB); 1513 RegStorage rs_src2 = RegStorage::Solo128(mir->dalvikInsn.vC); 1514 int opcode = 0; 1515 switch (opsize) { 1516 case k32: 1517 opcode = kX86PsubdRR; 1518 break; 1519 case kSignedHalf: 1520 case kUnsignedHalf: 1521 opcode = kX86PsubwRR; 1522 break; 1523 case kUnsignedByte: 1524 case kSignedByte: 1525 opcode = kX86PsubbRR; 1526 break; 1527 case kSingle: 1528 opcode = kX86SubpsRR; 1529 break; 1530 case kDouble: 1531 opcode = kX86SubpdRR; 1532 break; 1533 default: 1534 LOG(FATAL) << "Unsupported vector subtraction " << opsize; 1535 break; 1536 } 1537 NewLIR2(opcode, rs_dest_src1.GetReg(), rs_src2.GetReg()); 1538} 1539 1540void X86Mir2Lir::GenShiftLeftVector(BasicBlock *bb, MIR *mir) { 1541 DCHECK_EQ(mir->dalvikInsn.vA & 0xFFFF, 128U); 1542 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vA >> 16); 1543 RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vB); 1544 int imm = mir->dalvikInsn.vC; 1545 int opcode = 0; 1546 switch (opsize) { 1547 case k32: 1548 opcode = kX86PslldRI; 1549 break; 1550 case k64: 1551 opcode = kX86PsllqRI; 1552 break; 1553 case kSignedHalf: 1554 case kUnsignedHalf: 1555 opcode = kX86PsllwRI; 1556 break; 1557 default: 1558 LOG(FATAL) << "Unsupported vector shift left " << opsize; 1559 break; 1560 } 1561 NewLIR2(opcode, rs_dest_src1.GetReg(), imm); 1562} 1563 1564void X86Mir2Lir::GenSignedShiftRightVector(BasicBlock *bb, MIR *mir) { 1565 DCHECK_EQ(mir->dalvikInsn.vA & 0xFFFF, 128U); 1566 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vA >> 16); 1567 RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vB); 1568 int imm = mir->dalvikInsn.vC; 1569 int opcode = 0; 1570 switch (opsize) { 1571 case k32: 1572 opcode = kX86PsradRI; 1573 break; 1574 case kSignedHalf: 1575 case kUnsignedHalf: 1576 opcode = kX86PsrawRI; 1577 break; 1578 default: 1579 LOG(FATAL) << "Unsupported vector signed shift right " << opsize; 1580 break; 1581 } 1582 NewLIR2(opcode, rs_dest_src1.GetReg(), imm); 1583} 1584 1585void X86Mir2Lir::GenUnsignedShiftRightVector(BasicBlock *bb, MIR *mir) { 1586 DCHECK_EQ(mir->dalvikInsn.vA & 0xFFFF, 128U); 1587 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vA >> 16); 1588 RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vB); 1589 int imm = mir->dalvikInsn.vC; 1590 int opcode = 0; 1591 switch (opsize) { 1592 case k32: 1593 opcode = kX86PsrldRI; 1594 break; 1595 case k64: 1596 opcode = kX86PsrlqRI; 1597 break; 1598 case kSignedHalf: 1599 case kUnsignedHalf: 1600 opcode = kX86PsrlwRI; 1601 break; 1602 default: 1603 LOG(FATAL) << "Unsupported vector unsigned shift right " << opsize; 1604 break; 1605 } 1606 NewLIR2(opcode, rs_dest_src1.GetReg(), imm); 1607} 1608 1609void X86Mir2Lir::GenAndVector(BasicBlock *bb, MIR *mir) { 1610 // We only support 128 bit registers. 1611 DCHECK_EQ(mir->dalvikInsn.vA & 0xFFFF, 128U); 1612 RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vB); 1613 RegStorage rs_src2 = RegStorage::Solo128(mir->dalvikInsn.vC); 1614 NewLIR2(kX86PandRR, rs_dest_src1.GetReg(), rs_src2.GetReg()); 1615} 1616 1617void X86Mir2Lir::GenOrVector(BasicBlock *bb, MIR *mir) { 1618 // We only support 128 bit registers. 1619 DCHECK_EQ(mir->dalvikInsn.vA & 0xFFFF, 128U); 1620 RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vB); 1621 RegStorage rs_src2 = RegStorage::Solo128(mir->dalvikInsn.vC); 1622 NewLIR2(kX86PorRR, rs_dest_src1.GetReg(), rs_src2.GetReg()); 1623} 1624 1625void X86Mir2Lir::GenXorVector(BasicBlock *bb, MIR *mir) { 1626 // We only support 128 bit registers. 1627 DCHECK_EQ(mir->dalvikInsn.vA & 0xFFFF, 128U); 1628 RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vB); 1629 RegStorage rs_src2 = RegStorage::Solo128(mir->dalvikInsn.vC); 1630 NewLIR2(kX86PxorRR, rs_dest_src1.GetReg(), rs_src2.GetReg()); 1631} 1632 1633void X86Mir2Lir::GenAddReduceVector(BasicBlock *bb, MIR *mir) { 1634 DCHECK_EQ(mir->dalvikInsn.vA & 0xFFFF, 128U); 1635 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vA >> 16); 1636 RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vB); 1637 int imm = mir->dalvikInsn.vC; 1638 int opcode = 0; 1639 switch (opsize) { 1640 case k32: 1641 opcode = kX86PhadddRR; 1642 break; 1643 case kSignedHalf: 1644 case kUnsignedHalf: 1645 opcode = kX86PhaddwRR; 1646 break; 1647 default: 1648 LOG(FATAL) << "Unsupported vector add reduce " << opsize; 1649 break; 1650 } 1651 NewLIR2(opcode, rs_dest_src1.GetReg(), imm); 1652} 1653 1654void X86Mir2Lir::GenReduceVector(BasicBlock *bb, MIR *mir) { 1655 DCHECK_EQ(mir->dalvikInsn.vA & 0xFFFF, 128U); 1656 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vA >> 16); 1657 RegStorage rs_src = RegStorage::Solo128(mir->dalvikInsn.vB); 1658 int index = mir->dalvikInsn.arg[0]; 1659 int opcode = 0; 1660 switch (opsize) { 1661 case k32: 1662 opcode = kX86PextrdRRI; 1663 break; 1664 case kSignedHalf: 1665 case kUnsignedHalf: 1666 opcode = kX86PextrwRRI; 1667 break; 1668 case kUnsignedByte: 1669 case kSignedByte: 1670 opcode = kX86PextrbRRI; 1671 break; 1672 default: 1673 LOG(FATAL) << "Unsupported vector reduce " << opsize; 1674 break; 1675 } 1676 // We need to extract to a GPR. 1677 RegStorage temp = AllocTemp(); 1678 NewLIR3(opcode, temp.GetReg(), rs_src.GetReg(), index); 1679 1680 // Assume that the destination VR is in the def for the mir. 1681 RegLocation rl_dest = mir_graph_->GetDest(mir); 1682 RegLocation rl_temp = 1683 {kLocPhysReg, 0, 0, 0, 0, 0, 0, 0, 1, temp, INVALID_SREG, INVALID_SREG}; 1684 StoreValue(rl_dest, rl_temp); 1685} 1686 1687void X86Mir2Lir::GenSetVector(BasicBlock *bb, MIR *mir) { 1688 DCHECK_EQ(mir->dalvikInsn.vA & 0xFFFF, 128U); 1689 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vA >> 16); 1690 RegStorage rs_dest = RegStorage::Solo128(mir->dalvikInsn.vB); 1691 int op_low = 0, op_high = 0; 1692 switch (opsize) { 1693 case k32: 1694 op_low = kX86PshufdRRI; 1695 break; 1696 case kSignedHalf: 1697 case kUnsignedHalf: 1698 // Handles low quadword. 1699 op_low = kX86PshuflwRRI; 1700 // Handles upper quadword. 1701 op_high = kX86PshufdRRI; 1702 break; 1703 default: 1704 LOG(FATAL) << "Unsupported vector set " << opsize; 1705 break; 1706 } 1707 1708 // Load the value from the VR into a GPR. 1709 RegLocation rl_src = mir_graph_->GetSrc(mir, 0); 1710 rl_src = LoadValue(rl_src, kCoreReg); 1711 1712 // Load the value into the XMM register. 1713 NewLIR2(kX86MovdxrRR, rs_dest.GetReg(), rl_src.reg.GetReg()); 1714 1715 // Now shuffle the value across the destination. 1716 NewLIR3(op_low, rs_dest.GetReg(), rs_dest.GetReg(), 0); 1717 1718 // And then repeat as needed. 1719 if (op_high != 0) { 1720 NewLIR3(op_high, rs_dest.GetReg(), rs_dest.GetReg(), 0); 1721 } 1722} 1723 1724 1725LIR *X86Mir2Lir::ScanVectorLiteral(MIR *mir) { 1726 int *args = reinterpret_cast<int*>(mir->dalvikInsn.arg); 1727 for (LIR *p = const_vectors_; p != nullptr; p = p->next) { 1728 if (args[0] == p->operands[0] && args[1] == p->operands[1] && 1729 args[2] == p->operands[2] && args[3] == p->operands[3]) { 1730 return p; 1731 } 1732 } 1733 return nullptr; 1734} 1735 1736LIR *X86Mir2Lir::AddVectorLiteral(MIR *mir) { 1737 LIR* new_value = static_cast<LIR*>(arena_->Alloc(sizeof(LIR), kArenaAllocData)); 1738 int *args = reinterpret_cast<int*>(mir->dalvikInsn.arg); 1739 new_value->operands[0] = args[0]; 1740 new_value->operands[1] = args[1]; 1741 new_value->operands[2] = args[2]; 1742 new_value->operands[3] = args[3]; 1743 new_value->next = const_vectors_; 1744 if (const_vectors_ == nullptr) { 1745 estimated_native_code_size_ += 12; // Amount needed to align to 16 byte boundary. 1746 } 1747 estimated_native_code_size_ += 16; // Space for one vector. 1748 const_vectors_ = new_value; 1749 return new_value; 1750} 1751 1752// ------------ ABI support: mapping of args to physical registers ------------- 1753RegStorage X86Mir2Lir::InToRegStorageX86_64Mapper::GetNextReg(bool is_double_or_float, bool is_wide) { 1754 const SpecialTargetRegister coreArgMappingToPhysicalReg[] = {kArg1, kArg2, kArg3, kArg4, kArg5}; 1755 const int coreArgMappingToPhysicalRegSize = sizeof(coreArgMappingToPhysicalReg) / sizeof(SpecialTargetRegister); 1756 const SpecialTargetRegister fpArgMappingToPhysicalReg[] = {kFArg0, kFArg1, kFArg2, kFArg3, 1757 kFArg4, kFArg5, kFArg6, kFArg7}; 1758 const int fpArgMappingToPhysicalRegSize = sizeof(fpArgMappingToPhysicalReg) / sizeof(SpecialTargetRegister); 1759 1760 if (is_double_or_float) { 1761 if (cur_fp_reg_ < fpArgMappingToPhysicalRegSize) { 1762 return ml_->TargetReg(fpArgMappingToPhysicalReg[cur_fp_reg_++], is_wide); 1763 } 1764 } else { 1765 if (cur_core_reg_ < coreArgMappingToPhysicalRegSize) { 1766 return ml_->TargetReg(coreArgMappingToPhysicalReg[cur_core_reg_++], is_wide); 1767 } 1768 } 1769 return RegStorage::InvalidReg(); 1770} 1771 1772RegStorage X86Mir2Lir::InToRegStorageMapping::Get(int in_position) { 1773 DCHECK(IsInitialized()); 1774 auto res = mapping_.find(in_position); 1775 return res != mapping_.end() ? res->second : RegStorage::InvalidReg(); 1776} 1777 1778void X86Mir2Lir::InToRegStorageMapping::Initialize(RegLocation* arg_locs, int count, InToRegStorageMapper* mapper) { 1779 DCHECK(mapper != nullptr); 1780 max_mapped_in_ = -1; 1781 is_there_stack_mapped_ = false; 1782 for (int in_position = 0; in_position < count; in_position++) { 1783 RegStorage reg = mapper->GetNextReg(arg_locs[in_position].fp, arg_locs[in_position].wide); 1784 if (reg.Valid()) { 1785 mapping_[in_position] = reg; 1786 max_mapped_in_ = std::max(max_mapped_in_, in_position); 1787 if (reg.Is64BitSolo()) { 1788 // We covered 2 args, so skip the next one 1789 in_position++; 1790 } 1791 } else { 1792 is_there_stack_mapped_ = true; 1793 } 1794 } 1795 initialized_ = true; 1796} 1797 1798RegStorage X86Mir2Lir::GetArgMappingToPhysicalReg(int arg_num) { 1799 if (!cu_->target64) { 1800 return GetCoreArgMappingToPhysicalReg(arg_num); 1801 } 1802 1803 if (!in_to_reg_storage_mapping_.IsInitialized()) { 1804 int start_vreg = cu_->num_dalvik_registers - cu_->num_ins; 1805 RegLocation* arg_locs = &mir_graph_->reg_location_[start_vreg]; 1806 1807 InToRegStorageX86_64Mapper mapper(this); 1808 in_to_reg_storage_mapping_.Initialize(arg_locs, cu_->num_ins, &mapper); 1809 } 1810 return in_to_reg_storage_mapping_.Get(arg_num); 1811} 1812 1813RegStorage X86Mir2Lir::GetCoreArgMappingToPhysicalReg(int core_arg_num) { 1814 // For the 32-bit internal ABI, the first 3 arguments are passed in registers. 1815 // Not used for 64-bit, TODO: Move X86_32 to the same framework 1816 switch (core_arg_num) { 1817 case 0: 1818 return rs_rX86_ARG1; 1819 case 1: 1820 return rs_rX86_ARG2; 1821 case 2: 1822 return rs_rX86_ARG3; 1823 default: 1824 return RegStorage::InvalidReg(); 1825 } 1826} 1827 1828// ---------End of ABI support: mapping of args to physical registers ------------- 1829 1830/* 1831 * If there are any ins passed in registers that have not been promoted 1832 * to a callee-save register, flush them to the frame. Perform initial 1833 * assignment of promoted arguments. 1834 * 1835 * ArgLocs is an array of location records describing the incoming arguments 1836 * with one location record per word of argument. 1837 */ 1838void X86Mir2Lir::FlushIns(RegLocation* ArgLocs, RegLocation rl_method) { 1839 if (!cu_->target64) return Mir2Lir::FlushIns(ArgLocs, rl_method); 1840 /* 1841 * Dummy up a RegLocation for the incoming Method* 1842 * It will attempt to keep kArg0 live (or copy it to home location 1843 * if promoted). 1844 */ 1845 1846 RegLocation rl_src = rl_method; 1847 rl_src.location = kLocPhysReg; 1848 rl_src.reg = TargetRefReg(kArg0); 1849 rl_src.home = false; 1850 MarkLive(rl_src); 1851 StoreValue(rl_method, rl_src); 1852 // If Method* has been promoted, explicitly flush 1853 if (rl_method.location == kLocPhysReg) { 1854 StoreRefDisp(rs_rX86_SP, 0, As32BitReg(TargetRefReg(kArg0)), kNotVolatile); 1855 } 1856 1857 if (cu_->num_ins == 0) { 1858 return; 1859 } 1860 1861 int start_vreg = cu_->num_dalvik_registers - cu_->num_ins; 1862 /* 1863 * Copy incoming arguments to their proper home locations. 1864 * NOTE: an older version of dx had an issue in which 1865 * it would reuse static method argument registers. 1866 * This could result in the same Dalvik virtual register 1867 * being promoted to both core and fp regs. To account for this, 1868 * we only copy to the corresponding promoted physical register 1869 * if it matches the type of the SSA name for the incoming 1870 * argument. It is also possible that long and double arguments 1871 * end up half-promoted. In those cases, we must flush the promoted 1872 * half to memory as well. 1873 */ 1874 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); 1875 for (int i = 0; i < cu_->num_ins; i++) { 1876 // get reg corresponding to input 1877 RegStorage reg = GetArgMappingToPhysicalReg(i); 1878 1879 RegLocation* t_loc = &ArgLocs[i]; 1880 if (reg.Valid()) { 1881 // If arriving in register. 1882 1883 // We have already updated the arg location with promoted info 1884 // so we can be based on it. 1885 if (t_loc->location == kLocPhysReg) { 1886 // Just copy it. 1887 OpRegCopy(t_loc->reg, reg); 1888 } else { 1889 // Needs flush. 1890 if (t_loc->ref) { 1891 StoreRefDisp(rs_rX86_SP, SRegOffset(start_vreg + i), reg, kNotVolatile); 1892 } else { 1893 StoreBaseDisp(rs_rX86_SP, SRegOffset(start_vreg + i), reg, t_loc->wide ? k64 : k32, 1894 kNotVolatile); 1895 } 1896 } 1897 } else { 1898 // If arriving in frame & promoted. 1899 if (t_loc->location == kLocPhysReg) { 1900 if (t_loc->ref) { 1901 LoadRefDisp(rs_rX86_SP, SRegOffset(start_vreg + i), t_loc->reg, kNotVolatile); 1902 } else { 1903 LoadBaseDisp(rs_rX86_SP, SRegOffset(start_vreg + i), t_loc->reg, 1904 t_loc->wide ? k64 : k32, kNotVolatile); 1905 } 1906 } 1907 } 1908 if (t_loc->wide) { 1909 // Increment i to skip the next one. 1910 i++; 1911 } 1912 } 1913} 1914 1915/* 1916 * Load up to 5 arguments, the first three of which will be in 1917 * kArg1 .. kArg3. On entry kArg0 contains the current method pointer, 1918 * and as part of the load sequence, it must be replaced with 1919 * the target method pointer. Note, this may also be called 1920 * for "range" variants if the number of arguments is 5 or fewer. 1921 */ 1922int X86Mir2Lir::GenDalvikArgsNoRange(CallInfo* info, 1923 int call_state, LIR** pcrLabel, NextCallInsn next_call_insn, 1924 const MethodReference& target_method, 1925 uint32_t vtable_idx, uintptr_t direct_code, 1926 uintptr_t direct_method, InvokeType type, bool skip_this) { 1927 if (!cu_->target64) { 1928 return Mir2Lir::GenDalvikArgsNoRange(info, 1929 call_state, pcrLabel, next_call_insn, 1930 target_method, 1931 vtable_idx, direct_code, 1932 direct_method, type, skip_this); 1933 } 1934 return GenDalvikArgsRange(info, 1935 call_state, pcrLabel, next_call_insn, 1936 target_method, 1937 vtable_idx, direct_code, 1938 direct_method, type, skip_this); 1939} 1940 1941/* 1942 * May have 0+ arguments (also used for jumbo). Note that 1943 * source virtual registers may be in physical registers, so may 1944 * need to be flushed to home location before copying. This 1945 * applies to arg3 and above (see below). 1946 * 1947 * Two general strategies: 1948 * If < 20 arguments 1949 * Pass args 3-18 using vldm/vstm block copy 1950 * Pass arg0, arg1 & arg2 in kArg1-kArg3 1951 * If 20+ arguments 1952 * Pass args arg19+ using memcpy block copy 1953 * Pass arg0, arg1 & arg2 in kArg1-kArg3 1954 * 1955 */ 1956int X86Mir2Lir::GenDalvikArgsRange(CallInfo* info, int call_state, 1957 LIR** pcrLabel, NextCallInsn next_call_insn, 1958 const MethodReference& target_method, 1959 uint32_t vtable_idx, uintptr_t direct_code, uintptr_t direct_method, 1960 InvokeType type, bool skip_this) { 1961 if (!cu_->target64) { 1962 return Mir2Lir::GenDalvikArgsRange(info, call_state, 1963 pcrLabel, next_call_insn, 1964 target_method, 1965 vtable_idx, direct_code, direct_method, 1966 type, skip_this); 1967 } 1968 1969 /* If no arguments, just return */ 1970 if (info->num_arg_words == 0) 1971 return call_state; 1972 1973 const int start_index = skip_this ? 1 : 0; 1974 1975 InToRegStorageX86_64Mapper mapper(this); 1976 InToRegStorageMapping in_to_reg_storage_mapping; 1977 in_to_reg_storage_mapping.Initialize(info->args, info->num_arg_words, &mapper); 1978 const int last_mapped_in = in_to_reg_storage_mapping.GetMaxMappedIn(); 1979 const int size_of_the_last_mapped = last_mapped_in == -1 ? 1 : 1980 in_to_reg_storage_mapping.Get(last_mapped_in).Is64BitSolo() ? 2 : 1; 1981 int regs_left_to_pass_via_stack = info->num_arg_words - (last_mapped_in + size_of_the_last_mapped); 1982 1983 // Fisrt of all, check whether it make sense to use bulk copying 1984 // Optimization is aplicable only for range case 1985 // TODO: make a constant instead of 2 1986 if (info->is_range && regs_left_to_pass_via_stack >= 2) { 1987 // Scan the rest of the args - if in phys_reg flush to memory 1988 for (int next_arg = last_mapped_in + size_of_the_last_mapped; next_arg < info->num_arg_words;) { 1989 RegLocation loc = info->args[next_arg]; 1990 if (loc.wide) { 1991 loc = UpdateLocWide(loc); 1992 if (loc.location == kLocPhysReg) { 1993 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); 1994 StoreBaseDisp(rs_rX86_SP, SRegOffset(loc.s_reg_low), loc.reg, k64, kNotVolatile); 1995 } 1996 next_arg += 2; 1997 } else { 1998 loc = UpdateLoc(loc); 1999 if (loc.location == kLocPhysReg) { 2000 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); 2001 StoreBaseDisp(rs_rX86_SP, SRegOffset(loc.s_reg_low), loc.reg, k32, kNotVolatile); 2002 } 2003 next_arg++; 2004 } 2005 } 2006 2007 // Logic below assumes that Method pointer is at offset zero from SP. 2008 DCHECK_EQ(VRegOffset(static_cast<int>(kVRegMethodPtrBaseReg)), 0); 2009 2010 // The rest can be copied together 2011 int start_offset = SRegOffset(info->args[last_mapped_in + size_of_the_last_mapped].s_reg_low); 2012 int outs_offset = StackVisitor::GetOutVROffset(last_mapped_in + size_of_the_last_mapped, cu_->instruction_set); 2013 2014 int current_src_offset = start_offset; 2015 int current_dest_offset = outs_offset; 2016 2017 // Only davik regs are accessed in this loop; no next_call_insn() calls. 2018 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); 2019 while (regs_left_to_pass_via_stack > 0) { 2020 // This is based on the knowledge that the stack itself is 16-byte aligned. 2021 bool src_is_16b_aligned = (current_src_offset & 0xF) == 0; 2022 bool dest_is_16b_aligned = (current_dest_offset & 0xF) == 0; 2023 size_t bytes_to_move; 2024 2025 /* 2026 * The amount to move defaults to 32-bit. If there are 4 registers left to move, then do a 2027 * a 128-bit move because we won't get the chance to try to aligned. If there are more than 2028 * 4 registers left to move, consider doing a 128-bit only if either src or dest are aligned. 2029 * We do this because we could potentially do a smaller move to align. 2030 */ 2031 if (regs_left_to_pass_via_stack == 4 || 2032 (regs_left_to_pass_via_stack > 4 && (src_is_16b_aligned || dest_is_16b_aligned))) { 2033 // Moving 128-bits via xmm register. 2034 bytes_to_move = sizeof(uint32_t) * 4; 2035 2036 // Allocate a free xmm temp. Since we are working through the calling sequence, 2037 // we expect to have an xmm temporary available. AllocTempDouble will abort if 2038 // there are no free registers. 2039 RegStorage temp = AllocTempDouble(); 2040 2041 LIR* ld1 = nullptr; 2042 LIR* ld2 = nullptr; 2043 LIR* st1 = nullptr; 2044 LIR* st2 = nullptr; 2045 2046 /* 2047 * The logic is similar for both loads and stores. If we have 16-byte alignment, 2048 * do an aligned move. If we have 8-byte alignment, then do the move in two 2049 * parts. This approach prevents possible cache line splits. Finally, fall back 2050 * to doing an unaligned move. In most cases we likely won't split the cache 2051 * line but we cannot prove it and thus take a conservative approach. 2052 */ 2053 bool src_is_8b_aligned = (current_src_offset & 0x7) == 0; 2054 bool dest_is_8b_aligned = (current_dest_offset & 0x7) == 0; 2055 2056 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); 2057 if (src_is_16b_aligned) { 2058 ld1 = OpMovRegMem(temp, rs_rX86_SP, current_src_offset, kMovA128FP); 2059 } else if (src_is_8b_aligned) { 2060 ld1 = OpMovRegMem(temp, rs_rX86_SP, current_src_offset, kMovLo128FP); 2061 ld2 = OpMovRegMem(temp, rs_rX86_SP, current_src_offset + (bytes_to_move >> 1), 2062 kMovHi128FP); 2063 } else { 2064 ld1 = OpMovRegMem(temp, rs_rX86_SP, current_src_offset, kMovU128FP); 2065 } 2066 2067 if (dest_is_16b_aligned) { 2068 st1 = OpMovMemReg(rs_rX86_SP, current_dest_offset, temp, kMovA128FP); 2069 } else if (dest_is_8b_aligned) { 2070 st1 = OpMovMemReg(rs_rX86_SP, current_dest_offset, temp, kMovLo128FP); 2071 st2 = OpMovMemReg(rs_rX86_SP, current_dest_offset + (bytes_to_move >> 1), 2072 temp, kMovHi128FP); 2073 } else { 2074 st1 = OpMovMemReg(rs_rX86_SP, current_dest_offset, temp, kMovU128FP); 2075 } 2076 2077 // TODO If we could keep track of aliasing information for memory accesses that are wider 2078 // than 64-bit, we wouldn't need to set up a barrier. 2079 if (ld1 != nullptr) { 2080 if (ld2 != nullptr) { 2081 // For 64-bit load we can actually set up the aliasing information. 2082 AnnotateDalvikRegAccess(ld1, current_src_offset >> 2, true, true); 2083 AnnotateDalvikRegAccess(ld2, (current_src_offset + (bytes_to_move >> 1)) >> 2, true, true); 2084 } else { 2085 // Set barrier for 128-bit load. 2086 ld1->u.m.def_mask = &kEncodeAll; 2087 } 2088 } 2089 if (st1 != nullptr) { 2090 if (st2 != nullptr) { 2091 // For 64-bit store we can actually set up the aliasing information. 2092 AnnotateDalvikRegAccess(st1, current_dest_offset >> 2, false, true); 2093 AnnotateDalvikRegAccess(st2, (current_dest_offset + (bytes_to_move >> 1)) >> 2, false, true); 2094 } else { 2095 // Set barrier for 128-bit store. 2096 st1->u.m.def_mask = &kEncodeAll; 2097 } 2098 } 2099 2100 // Free the temporary used for the data movement. 2101 FreeTemp(temp); 2102 } else { 2103 // Moving 32-bits via general purpose register. 2104 bytes_to_move = sizeof(uint32_t); 2105 2106 // Instead of allocating a new temp, simply reuse one of the registers being used 2107 // for argument passing. 2108 RegStorage temp = TargetReg(kArg3, false); 2109 2110 // Now load the argument VR and store to the outs. 2111 Load32Disp(rs_rX86_SP, current_src_offset, temp); 2112 Store32Disp(rs_rX86_SP, current_dest_offset, temp); 2113 } 2114 2115 current_src_offset += bytes_to_move; 2116 current_dest_offset += bytes_to_move; 2117 regs_left_to_pass_via_stack -= (bytes_to_move >> 2); 2118 } 2119 DCHECK_EQ(regs_left_to_pass_via_stack, 0); 2120 } 2121 2122 // Now handle rest not registers if they are 2123 if (in_to_reg_storage_mapping.IsThereStackMapped()) { 2124 RegStorage regSingle = TargetReg(kArg2, false); 2125 RegStorage regWide = TargetReg(kArg3, true); 2126 for (int i = start_index; 2127 i < last_mapped_in + size_of_the_last_mapped + regs_left_to_pass_via_stack; i++) { 2128 RegLocation rl_arg = info->args[i]; 2129 rl_arg = UpdateRawLoc(rl_arg); 2130 RegStorage reg = in_to_reg_storage_mapping.Get(i); 2131 if (!reg.Valid()) { 2132 int out_offset = StackVisitor::GetOutVROffset(i, cu_->instruction_set); 2133 2134 { 2135 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); 2136 if (rl_arg.wide) { 2137 if (rl_arg.location == kLocPhysReg) { 2138 StoreBaseDisp(rs_rX86_SP, out_offset, rl_arg.reg, k64, kNotVolatile); 2139 } else { 2140 LoadValueDirectWideFixed(rl_arg, regWide); 2141 StoreBaseDisp(rs_rX86_SP, out_offset, regWide, k64, kNotVolatile); 2142 } 2143 } else { 2144 if (rl_arg.location == kLocPhysReg) { 2145 StoreBaseDisp(rs_rX86_SP, out_offset, rl_arg.reg, k32, kNotVolatile); 2146 } else { 2147 LoadValueDirectFixed(rl_arg, regSingle); 2148 StoreBaseDisp(rs_rX86_SP, out_offset, regSingle, k32, kNotVolatile); 2149 } 2150 } 2151 } 2152 call_state = next_call_insn(cu_, info, call_state, target_method, 2153 vtable_idx, direct_code, direct_method, type); 2154 } 2155 if (rl_arg.wide) { 2156 i++; 2157 } 2158 } 2159 } 2160 2161 // Finish with mapped registers 2162 for (int i = start_index; i <= last_mapped_in; i++) { 2163 RegLocation rl_arg = info->args[i]; 2164 rl_arg = UpdateRawLoc(rl_arg); 2165 RegStorage reg = in_to_reg_storage_mapping.Get(i); 2166 if (reg.Valid()) { 2167 if (rl_arg.wide) { 2168 LoadValueDirectWideFixed(rl_arg, reg); 2169 } else { 2170 LoadValueDirectFixed(rl_arg, reg); 2171 } 2172 call_state = next_call_insn(cu_, info, call_state, target_method, vtable_idx, 2173 direct_code, direct_method, type); 2174 } 2175 if (rl_arg.wide) { 2176 i++; 2177 } 2178 } 2179 2180 call_state = next_call_insn(cu_, info, call_state, target_method, vtable_idx, 2181 direct_code, direct_method, type); 2182 if (pcrLabel) { 2183 if (cu_->compiler_driver->GetCompilerOptions().GetExplicitNullChecks()) { 2184 *pcrLabel = GenExplicitNullCheck(TargetRefReg(kArg1), info->opt_flags); 2185 } else { 2186 *pcrLabel = nullptr; 2187 // In lieu of generating a check for kArg1 being null, we need to 2188 // perform a load when doing implicit checks. 2189 RegStorage tmp = AllocTemp(); 2190 Load32Disp(TargetRefReg(kArg1), 0, tmp); 2191 MarkPossibleNullPointerException(info->opt_flags); 2192 FreeTemp(tmp); 2193 } 2194 } 2195 return call_state; 2196} 2197 2198} // namespace art 2199