target_x86.cc revision e90501da0222717d75c126ebf89569db3976927e
1/* 2 * Copyright (C) 2012 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#include <string> 18#include <inttypes.h> 19 20#include "codegen_x86.h" 21#include "dex/compiler_internals.h" 22#include "dex/quick/mir_to_lir-inl.h" 23#include "mirror/array.h" 24#include "mirror/string.h" 25#include "x86_lir.h" 26 27namespace art { 28 29// FIXME: restore "static" when usage uncovered 30/*static*/ int core_regs[] = { 31 rAX, rCX, rDX, rBX, rX86_SP, rBP, rSI, rDI 32#ifdef TARGET_REX_SUPPORT 33 r8, r9, r10, r11, r12, r13, r14, 15 34#endif 35}; 36/*static*/ int ReservedRegs[] = {rX86_SP}; 37/*static*/ int core_temps[] = {rAX, rCX, rDX, rBX}; 38/*static*/ int FpRegs[] = { 39 fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7, 40#ifdef TARGET_REX_SUPPORT 41 fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15 42#endif 43}; 44/*static*/ int fp_temps[] = { 45 fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7, 46#ifdef TARGET_REX_SUPPORT 47 fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15 48#endif 49}; 50 51RegLocation X86Mir2Lir::LocCReturn() { 52 return x86_loc_c_return; 53} 54 55RegLocation X86Mir2Lir::LocCReturnWide() { 56 return x86_loc_c_return_wide; 57} 58 59RegLocation X86Mir2Lir::LocCReturnFloat() { 60 return x86_loc_c_return_float; 61} 62 63RegLocation X86Mir2Lir::LocCReturnDouble() { 64 return x86_loc_c_return_double; 65} 66 67// Return a target-dependent special register. 68int X86Mir2Lir::TargetReg(SpecialTargetRegister reg) { 69 int res = INVALID_REG; 70 switch (reg) { 71 case kSelf: res = rX86_SELF; break; 72 case kSuspend: res = rX86_SUSPEND; break; 73 case kLr: res = rX86_LR; break; 74 case kPc: res = rX86_PC; break; 75 case kSp: res = rX86_SP; break; 76 case kArg0: res = rX86_ARG0; break; 77 case kArg1: res = rX86_ARG1; break; 78 case kArg2: res = rX86_ARG2; break; 79 case kArg3: res = rX86_ARG3; break; 80 case kFArg0: res = rX86_FARG0; break; 81 case kFArg1: res = rX86_FARG1; break; 82 case kFArg2: res = rX86_FARG2; break; 83 case kFArg3: res = rX86_FARG3; break; 84 case kRet0: res = rX86_RET0; break; 85 case kRet1: res = rX86_RET1; break; 86 case kInvokeTgt: res = rX86_INVOKE_TGT; break; 87 case kHiddenArg: res = rAX; break; 88 case kHiddenFpArg: res = fr0; break; 89 case kCount: res = rX86_COUNT; break; 90 } 91 return res; 92} 93 94int X86Mir2Lir::GetArgMappingToPhysicalReg(int arg_num) { 95 // For the 32-bit internal ABI, the first 3 arguments are passed in registers. 96 // TODO: This is not 64-bit compliant and depends on new internal ABI. 97 switch (arg_num) { 98 case 0: 99 return rX86_ARG1; 100 case 1: 101 return rX86_ARG2; 102 case 2: 103 return rX86_ARG3; 104 default: 105 return INVALID_REG; 106 } 107} 108 109// Create a double from a pair of singles. 110int X86Mir2Lir::S2d(int low_reg, int high_reg) { 111 return X86_S2D(low_reg, high_reg); 112} 113 114// Return mask to strip off fp reg flags and bias. 115uint32_t X86Mir2Lir::FpRegMask() { 116 return X86_FP_REG_MASK; 117} 118 119// True if both regs single, both core or both double. 120bool X86Mir2Lir::SameRegType(int reg1, int reg2) { 121 return (X86_REGTYPE(reg1) == X86_REGTYPE(reg2)); 122} 123 124/* 125 * Decode the register id. 126 */ 127uint64_t X86Mir2Lir::GetRegMaskCommon(int reg) { 128 uint64_t seed; 129 int shift; 130 int reg_id; 131 132 reg_id = reg & 0xf; 133 /* Double registers in x86 are just a single FP register */ 134 seed = 1; 135 /* FP register starts at bit position 16 */ 136 shift = X86_FPREG(reg) ? kX86FPReg0 : 0; 137 /* Expand the double register id into single offset */ 138 shift += reg_id; 139 return (seed << shift); 140} 141 142uint64_t X86Mir2Lir::GetPCUseDefEncoding() { 143 /* 144 * FIXME: might make sense to use a virtual resource encoding bit for pc. Might be 145 * able to clean up some of the x86/Arm_Mips differences 146 */ 147 LOG(FATAL) << "Unexpected call to GetPCUseDefEncoding for x86"; 148 return 0ULL; 149} 150 151void X86Mir2Lir::SetupTargetResourceMasks(LIR* lir, uint64_t flags) { 152 DCHECK_EQ(cu_->instruction_set, kX86); 153 DCHECK(!lir->flags.use_def_invalid); 154 155 // X86-specific resource map setup here. 156 if (flags & REG_USE_SP) { 157 lir->u.m.use_mask |= ENCODE_X86_REG_SP; 158 } 159 160 if (flags & REG_DEF_SP) { 161 lir->u.m.def_mask |= ENCODE_X86_REG_SP; 162 } 163 164 if (flags & REG_DEFA) { 165 SetupRegMask(&lir->u.m.def_mask, rAX); 166 } 167 168 if (flags & REG_DEFD) { 169 SetupRegMask(&lir->u.m.def_mask, rDX); 170 } 171 if (flags & REG_USEA) { 172 SetupRegMask(&lir->u.m.use_mask, rAX); 173 } 174 175 if (flags & REG_USEC) { 176 SetupRegMask(&lir->u.m.use_mask, rCX); 177 } 178 179 if (flags & REG_USED) { 180 SetupRegMask(&lir->u.m.use_mask, rDX); 181 } 182 183 if (flags & REG_USEB) { 184 SetupRegMask(&lir->u.m.use_mask, rBX); 185 } 186 187 // Fixup hard to describe instruction: Uses rAX, rCX, rDI; sets rDI. 188 if (lir->opcode == kX86RepneScasw) { 189 SetupRegMask(&lir->u.m.use_mask, rAX); 190 SetupRegMask(&lir->u.m.use_mask, rCX); 191 SetupRegMask(&lir->u.m.use_mask, rDI); 192 SetupRegMask(&lir->u.m.def_mask, rDI); 193 } 194 195 if (flags & USE_FP_STACK) { 196 lir->u.m.use_mask |= ENCODE_X86_FP_STACK; 197 lir->u.m.def_mask |= ENCODE_X86_FP_STACK; 198 } 199} 200 201/* For dumping instructions */ 202static const char* x86RegName[] = { 203 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", 204 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" 205}; 206 207static const char* x86CondName[] = { 208 "O", 209 "NO", 210 "B/NAE/C", 211 "NB/AE/NC", 212 "Z/EQ", 213 "NZ/NE", 214 "BE/NA", 215 "NBE/A", 216 "S", 217 "NS", 218 "P/PE", 219 "NP/PO", 220 "L/NGE", 221 "NL/GE", 222 "LE/NG", 223 "NLE/G" 224}; 225 226/* 227 * Interpret a format string and build a string no longer than size 228 * See format key in Assemble.cc. 229 */ 230std::string X86Mir2Lir::BuildInsnString(const char *fmt, LIR *lir, unsigned char* base_addr) { 231 std::string buf; 232 size_t i = 0; 233 size_t fmt_len = strlen(fmt); 234 while (i < fmt_len) { 235 if (fmt[i] != '!') { 236 buf += fmt[i]; 237 i++; 238 } else { 239 i++; 240 DCHECK_LT(i, fmt_len); 241 char operand_number_ch = fmt[i]; 242 i++; 243 if (operand_number_ch == '!') { 244 buf += "!"; 245 } else { 246 int operand_number = operand_number_ch - '0'; 247 DCHECK_LT(operand_number, 6); // Expect upto 6 LIR operands. 248 DCHECK_LT(i, fmt_len); 249 int operand = lir->operands[operand_number]; 250 switch (fmt[i]) { 251 case 'c': 252 DCHECK_LT(static_cast<size_t>(operand), sizeof(x86CondName)); 253 buf += x86CondName[operand]; 254 break; 255 case 'd': 256 buf += StringPrintf("%d", operand); 257 break; 258 case 'p': { 259 EmbeddedData *tab_rec = reinterpret_cast<EmbeddedData*>(UnwrapPointer(operand)); 260 buf += StringPrintf("0x%08x", tab_rec->offset); 261 break; 262 } 263 case 'r': 264 if (X86_FPREG(operand) || X86_DOUBLEREG(operand)) { 265 int fp_reg = operand & X86_FP_REG_MASK; 266 buf += StringPrintf("xmm%d", fp_reg); 267 } else { 268 DCHECK_LT(static_cast<size_t>(operand), sizeof(x86RegName)); 269 buf += x86RegName[operand]; 270 } 271 break; 272 case 't': 273 buf += StringPrintf("0x%08" PRIxPTR " (L%p)", 274 reinterpret_cast<uintptr_t>(base_addr) + lir->offset + operand, 275 lir->target); 276 break; 277 default: 278 buf += StringPrintf("DecodeError '%c'", fmt[i]); 279 break; 280 } 281 i++; 282 } 283 } 284 } 285 return buf; 286} 287 288void X86Mir2Lir::DumpResourceMask(LIR *x86LIR, uint64_t mask, const char *prefix) { 289 char buf[256]; 290 buf[0] = 0; 291 292 if (mask == ENCODE_ALL) { 293 strcpy(buf, "all"); 294 } else { 295 char num[8]; 296 int i; 297 298 for (i = 0; i < kX86RegEnd; i++) { 299 if (mask & (1ULL << i)) { 300 snprintf(num, arraysize(num), "%d ", i); 301 strcat(buf, num); 302 } 303 } 304 305 if (mask & ENCODE_CCODE) { 306 strcat(buf, "cc "); 307 } 308 /* Memory bits */ 309 if (x86LIR && (mask & ENCODE_DALVIK_REG)) { 310 snprintf(buf + strlen(buf), arraysize(buf) - strlen(buf), "dr%d%s", 311 DECODE_ALIAS_INFO_REG(x86LIR->flags.alias_info), 312 (DECODE_ALIAS_INFO_WIDE(x86LIR->flags.alias_info)) ? "(+1)" : ""); 313 } 314 if (mask & ENCODE_LITERAL) { 315 strcat(buf, "lit "); 316 } 317 318 if (mask & ENCODE_HEAP_REF) { 319 strcat(buf, "heap "); 320 } 321 if (mask & ENCODE_MUST_NOT_ALIAS) { 322 strcat(buf, "noalias "); 323 } 324 } 325 if (buf[0]) { 326 LOG(INFO) << prefix << ": " << buf; 327 } 328} 329 330void X86Mir2Lir::AdjustSpillMask() { 331 // Adjustment for LR spilling, x86 has no LR so nothing to do here 332 core_spill_mask_ |= (1 << rRET); 333 num_core_spills_++; 334} 335 336/* 337 * Mark a callee-save fp register as promoted. Note that 338 * vpush/vpop uses contiguous register lists so we must 339 * include any holes in the mask. Associate holes with 340 * Dalvik register INVALID_VREG (0xFFFFU). 341 */ 342void X86Mir2Lir::MarkPreservedSingle(int v_reg, int reg) { 343 UNIMPLEMENTED(WARNING) << "MarkPreservedSingle"; 344#if 0 345 LOG(FATAL) << "No support yet for promoted FP regs"; 346#endif 347} 348 349void X86Mir2Lir::FlushRegWide(int reg1, int reg2) { 350 RegisterInfo* info1 = GetRegInfo(reg1); 351 RegisterInfo* info2 = GetRegInfo(reg2); 352 DCHECK(info1 && info2 && info1->pair && info2->pair && 353 (info1->partner == info2->reg) && 354 (info2->partner == info1->reg)); 355 if ((info1->live && info1->dirty) || (info2->live && info2->dirty)) { 356 if (!(info1->is_temp && info2->is_temp)) { 357 /* Should not happen. If it does, there's a problem in eval_loc */ 358 LOG(FATAL) << "Long half-temp, half-promoted"; 359 } 360 361 info1->dirty = false; 362 info2->dirty = false; 363 if (mir_graph_->SRegToVReg(info2->s_reg) < mir_graph_->SRegToVReg(info1->s_reg)) 364 info1 = info2; 365 int v_reg = mir_graph_->SRegToVReg(info1->s_reg); 366 StoreBaseDispWide(rX86_SP, VRegOffset(v_reg), info1->reg, info1->partner); 367 } 368} 369 370void X86Mir2Lir::FlushReg(int reg) { 371 RegisterInfo* info = GetRegInfo(reg); 372 if (info->live && info->dirty) { 373 info->dirty = false; 374 int v_reg = mir_graph_->SRegToVReg(info->s_reg); 375 StoreBaseDisp(rX86_SP, VRegOffset(v_reg), reg, kWord); 376 } 377} 378 379/* Give access to the target-dependent FP register encoding to common code */ 380bool X86Mir2Lir::IsFpReg(int reg) { 381 return X86_FPREG(reg); 382} 383 384/* Clobber all regs that might be used by an external C call */ 385void X86Mir2Lir::ClobberCallerSave() { 386 Clobber(rAX); 387 Clobber(rCX); 388 Clobber(rDX); 389 Clobber(rBX); 390} 391 392RegLocation X86Mir2Lir::GetReturnWideAlt() { 393 RegLocation res = LocCReturnWide(); 394 CHECK(res.reg.GetReg() == rAX); 395 CHECK(res.reg.GetHighReg() == rDX); 396 Clobber(rAX); 397 Clobber(rDX); 398 MarkInUse(rAX); 399 MarkInUse(rDX); 400 MarkPair(res.reg.GetReg(), res.reg.GetHighReg()); 401 return res; 402} 403 404RegLocation X86Mir2Lir::GetReturnAlt() { 405 RegLocation res = LocCReturn(); 406 res.reg.SetReg(rDX); 407 Clobber(rDX); 408 MarkInUse(rDX); 409 return res; 410} 411 412/* To be used when explicitly managing register use */ 413void X86Mir2Lir::LockCallTemps() { 414 LockTemp(rX86_ARG0); 415 LockTemp(rX86_ARG1); 416 LockTemp(rX86_ARG2); 417 LockTemp(rX86_ARG3); 418} 419 420/* To be used when explicitly managing register use */ 421void X86Mir2Lir::FreeCallTemps() { 422 FreeTemp(rX86_ARG0); 423 FreeTemp(rX86_ARG1); 424 FreeTemp(rX86_ARG2); 425 FreeTemp(rX86_ARG3); 426} 427 428void X86Mir2Lir::GenMemBarrier(MemBarrierKind barrier_kind) { 429#if ANDROID_SMP != 0 430 // TODO: optimize fences 431 NewLIR0(kX86Mfence); 432#endif 433} 434 435// Alloc a pair of core registers, or a double. 436RegStorage X86Mir2Lir::AllocTypedTempWide(bool fp_hint, int reg_class) { 437 int high_reg; 438 int low_reg; 439 440 if (((reg_class == kAnyReg) && fp_hint) || (reg_class == kFPReg)) { 441 low_reg = AllocTempDouble(); 442 high_reg = low_reg; // only one allocated! 443 // TODO: take advantage of 64-bit notation. 444 return RegStorage(RegStorage::k64BitPair, low_reg, high_reg); 445 } 446 low_reg = AllocTemp(); 447 high_reg = AllocTemp(); 448 return RegStorage(RegStorage::k64BitPair, low_reg, high_reg); 449} 450 451int X86Mir2Lir::AllocTypedTemp(bool fp_hint, int reg_class) { 452 if (((reg_class == kAnyReg) && fp_hint) || (reg_class == kFPReg)) { 453 return AllocTempFloat(); 454 } 455 return AllocTemp(); 456} 457 458void X86Mir2Lir::CompilerInitializeRegAlloc() { 459 int num_regs = sizeof(core_regs)/sizeof(*core_regs); 460 int num_reserved = sizeof(ReservedRegs)/sizeof(*ReservedRegs); 461 int num_temps = sizeof(core_temps)/sizeof(*core_temps); 462 int num_fp_regs = sizeof(FpRegs)/sizeof(*FpRegs); 463 int num_fp_temps = sizeof(fp_temps)/sizeof(*fp_temps); 464 reg_pool_ = static_cast<RegisterPool*>(arena_->Alloc(sizeof(*reg_pool_), 465 kArenaAllocRegAlloc)); 466 reg_pool_->num_core_regs = num_regs; 467 reg_pool_->core_regs = 468 static_cast<RegisterInfo*>(arena_->Alloc(num_regs * sizeof(*reg_pool_->core_regs), 469 kArenaAllocRegAlloc)); 470 reg_pool_->num_fp_regs = num_fp_regs; 471 reg_pool_->FPRegs = 472 static_cast<RegisterInfo *>(arena_->Alloc(num_fp_regs * sizeof(*reg_pool_->FPRegs), 473 kArenaAllocRegAlloc)); 474 CompilerInitPool(reg_pool_->core_regs, core_regs, reg_pool_->num_core_regs); 475 CompilerInitPool(reg_pool_->FPRegs, FpRegs, reg_pool_->num_fp_regs); 476 // Keep special registers from being allocated 477 for (int i = 0; i < num_reserved; i++) { 478 MarkInUse(ReservedRegs[i]); 479 } 480 // Mark temp regs - all others not in use can be used for promotion 481 for (int i = 0; i < num_temps; i++) { 482 MarkTemp(core_temps[i]); 483 } 484 for (int i = 0; i < num_fp_temps; i++) { 485 MarkTemp(fp_temps[i]); 486 } 487} 488 489void X86Mir2Lir::FreeRegLocTemps(RegLocation rl_keep, 490 RegLocation rl_free) { 491 if ((rl_free.reg.GetReg() != rl_keep.reg.GetReg()) && (rl_free.reg.GetReg() != rl_keep.reg.GetHighReg()) && 492 (rl_free.reg.GetHighReg() != rl_keep.reg.GetReg()) && (rl_free.reg.GetHighReg() != rl_keep.reg.GetHighReg())) { 493 // No overlap, free both 494 FreeTemp(rl_free.reg.GetReg()); 495 FreeTemp(rl_free.reg.GetHighReg()); 496 } 497} 498 499void X86Mir2Lir::SpillCoreRegs() { 500 if (num_core_spills_ == 0) { 501 return; 502 } 503 // Spill mask not including fake return address register 504 uint32_t mask = core_spill_mask_ & ~(1 << rRET); 505 int offset = frame_size_ - (4 * num_core_spills_); 506 for (int reg = 0; mask; mask >>= 1, reg++) { 507 if (mask & 0x1) { 508 StoreWordDisp(rX86_SP, offset, reg); 509 offset += 4; 510 } 511 } 512} 513 514void X86Mir2Lir::UnSpillCoreRegs() { 515 if (num_core_spills_ == 0) { 516 return; 517 } 518 // Spill mask not including fake return address register 519 uint32_t mask = core_spill_mask_ & ~(1 << rRET); 520 int offset = frame_size_ - (4 * num_core_spills_); 521 for (int reg = 0; mask; mask >>= 1, reg++) { 522 if (mask & 0x1) { 523 LoadWordDisp(rX86_SP, offset, reg); 524 offset += 4; 525 } 526 } 527} 528 529bool X86Mir2Lir::IsUnconditionalBranch(LIR* lir) { 530 return (lir->opcode == kX86Jmp8 || lir->opcode == kX86Jmp32); 531} 532 533X86Mir2Lir::X86Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena) 534 : Mir2Lir(cu, mir_graph, arena), 535 method_address_insns_(arena, 100, kGrowableArrayMisc), 536 class_type_address_insns_(arena, 100, kGrowableArrayMisc), 537 call_method_insns_(arena, 100, kGrowableArrayMisc), 538 stack_decrement_(nullptr), stack_increment_(nullptr) { 539 store_method_addr_used_ = false; 540 for (int i = 0; i < kX86Last; i++) { 541 if (X86Mir2Lir::EncodingMap[i].opcode != i) { 542 LOG(FATAL) << "Encoding order for " << X86Mir2Lir::EncodingMap[i].name 543 << " is wrong: expecting " << i << ", seeing " 544 << static_cast<int>(X86Mir2Lir::EncodingMap[i].opcode); 545 } 546 } 547} 548 549Mir2Lir* X86CodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, 550 ArenaAllocator* const arena) { 551 return new X86Mir2Lir(cu, mir_graph, arena); 552} 553 554// Not used in x86 555int X86Mir2Lir::LoadHelper(ThreadOffset offset) { 556 LOG(FATAL) << "Unexpected use of LoadHelper in x86"; 557 return INVALID_REG; 558} 559 560LIR* X86Mir2Lir::CheckSuspendUsingLoad() { 561 LOG(FATAL) << "Unexpected use of CheckSuspendUsingLoad in x86"; 562 return nullptr; 563} 564 565uint64_t X86Mir2Lir::GetTargetInstFlags(int opcode) { 566 DCHECK(!IsPseudoLirOp(opcode)); 567 return X86Mir2Lir::EncodingMap[opcode].flags; 568} 569 570const char* X86Mir2Lir::GetTargetInstName(int opcode) { 571 DCHECK(!IsPseudoLirOp(opcode)); 572 return X86Mir2Lir::EncodingMap[opcode].name; 573} 574 575const char* X86Mir2Lir::GetTargetInstFmt(int opcode) { 576 DCHECK(!IsPseudoLirOp(opcode)); 577 return X86Mir2Lir::EncodingMap[opcode].fmt; 578} 579 580/* 581 * Return an updated location record with current in-register status. 582 * If the value lives in live temps, reflect that fact. No code 583 * is generated. If the live value is part of an older pair, 584 * clobber both low and high. 585 */ 586// TODO: Reunify with common code after 'pair mess' has been fixed 587RegLocation X86Mir2Lir::UpdateLocWide(RegLocation loc) { 588 DCHECK(loc.wide); 589 DCHECK(CheckCorePoolSanity()); 590 if (loc.location != kLocPhysReg) { 591 DCHECK((loc.location == kLocDalvikFrame) || 592 (loc.location == kLocCompilerTemp)); 593 // Are the dalvik regs already live in physical registers? 594 RegisterInfo* info_lo = AllocLive(loc.s_reg_low, kAnyReg); 595 596 // Handle FP registers specially on x86. 597 if (info_lo && IsFpReg(info_lo->reg)) { 598 bool match = true; 599 600 // We can't match a FP register with a pair of Core registers. 601 match = match && (info_lo->pair == 0); 602 603 if (match) { 604 // We can reuse;update the register usage info. 605 loc.location = kLocPhysReg; 606 loc.vec_len = kVectorLength8; 607 // TODO: use k64BitVector 608 loc.reg = RegStorage(RegStorage::k64BitPair, info_lo->reg, info_lo->reg); 609 DCHECK(IsFpReg(loc.reg.GetReg())); 610 return loc; 611 } 612 // We can't easily reuse; clobber and free any overlaps. 613 if (info_lo) { 614 Clobber(info_lo->reg); 615 FreeTemp(info_lo->reg); 616 if (info_lo->pair) 617 Clobber(info_lo->partner); 618 } 619 } else { 620 RegisterInfo* info_hi = AllocLive(GetSRegHi(loc.s_reg_low), kAnyReg); 621 bool match = true; 622 match = match && (info_lo != NULL); 623 match = match && (info_hi != NULL); 624 // Are they both core or both FP? 625 match = match && (IsFpReg(info_lo->reg) == IsFpReg(info_hi->reg)); 626 // If a pair of floating point singles, are they properly aligned? 627 if (match && IsFpReg(info_lo->reg)) { 628 match &= ((info_lo->reg & 0x1) == 0); 629 match &= ((info_hi->reg - info_lo->reg) == 1); 630 } 631 // If previously used as a pair, it is the same pair? 632 if (match && (info_lo->pair || info_hi->pair)) { 633 match = (info_lo->pair == info_hi->pair); 634 match &= ((info_lo->reg == info_hi->partner) && 635 (info_hi->reg == info_lo->partner)); 636 } 637 if (match) { 638 // Can reuse - update the register usage info 639 loc.reg = RegStorage(RegStorage::k64BitPair, info_lo->reg, info_hi->reg); 640 loc.location = kLocPhysReg; 641 MarkPair(loc.reg.GetReg(), loc.reg.GetHighReg()); 642 DCHECK(!IsFpReg(loc.reg.GetReg()) || ((loc.reg.GetReg() & 0x1) == 0)); 643 return loc; 644 } 645 // Can't easily reuse - clobber and free any overlaps 646 if (info_lo) { 647 Clobber(info_lo->reg); 648 FreeTemp(info_lo->reg); 649 if (info_lo->pair) 650 Clobber(info_lo->partner); 651 } 652 if (info_hi) { 653 Clobber(info_hi->reg); 654 FreeTemp(info_hi->reg); 655 if (info_hi->pair) 656 Clobber(info_hi->partner); 657 } 658 } 659 } 660 return loc; 661} 662 663// TODO: Reunify with common code after 'pair mess' has been fixed 664RegLocation X86Mir2Lir::EvalLocWide(RegLocation loc, int reg_class, bool update) { 665 DCHECK(loc.wide); 666 int32_t low_reg; 667 int32_t high_reg; 668 669 loc = UpdateLocWide(loc); 670 671 /* If it is already in a register, we can assume proper form. Is it the right reg class? */ 672 if (loc.location == kLocPhysReg) { 673 DCHECK_EQ(IsFpReg(loc.reg.GetReg()), loc.IsVectorScalar()); 674 if (!RegClassMatches(reg_class, loc.reg.GetReg())) { 675 /* It is the wrong register class. Reallocate and copy. */ 676 if (!IsFpReg(loc.reg.GetReg())) { 677 // We want this in a FP reg, and it is in core registers. 678 DCHECK(reg_class != kCoreReg); 679 // Allocate this into any FP reg, and mark it with the right size. 680 low_reg = AllocTypedTemp(true, reg_class); 681 OpVectorRegCopyWide(low_reg, loc.reg.GetReg(), loc.reg.GetHighReg()); 682 CopyRegInfo(low_reg, loc.reg.GetReg()); 683 Clobber(loc.reg.GetReg()); 684 Clobber(loc.reg.GetHighReg()); 685 loc.reg.SetReg(low_reg); 686 loc.reg.SetHighReg(low_reg); // Play nice with existing code. 687 loc.vec_len = kVectorLength8; 688 } else { 689 // The value is in a FP register, and we want it in a pair of core registers. 690 DCHECK_EQ(reg_class, kCoreReg); 691 DCHECK_EQ(loc.reg.GetReg(), loc.reg.GetHighReg()); 692 RegStorage new_regs = AllocTypedTempWide(false, kCoreReg); // Force to core registers. 693 low_reg = new_regs.GetReg(); 694 high_reg = new_regs.GetHighReg(); 695 DCHECK_NE(low_reg, high_reg); 696 OpRegCopyWide(low_reg, high_reg, loc.reg.GetReg(), loc.reg.GetHighReg()); 697 CopyRegInfo(low_reg, loc.reg.GetReg()); 698 CopyRegInfo(high_reg, loc.reg.GetHighReg()); 699 Clobber(loc.reg.GetReg()); 700 Clobber(loc.reg.GetHighReg()); 701 loc.reg = new_regs; 702 MarkPair(loc.reg.GetReg(), loc.reg.GetHighReg()); 703 DCHECK(!IsFpReg(loc.reg.GetReg()) || ((loc.reg.GetReg() & 0x1) == 0)); 704 } 705 } 706 return loc; 707 } 708 709 DCHECK_NE(loc.s_reg_low, INVALID_SREG); 710 DCHECK_NE(GetSRegHi(loc.s_reg_low), INVALID_SREG); 711 712 loc.reg = AllocTypedTempWide(loc.fp, reg_class); 713 714 // FIXME: take advantage of RegStorage notation. 715 if (loc.reg.GetReg() == loc.reg.GetHighReg()) { 716 DCHECK(IsFpReg(loc.reg.GetReg())); 717 loc.vec_len = kVectorLength8; 718 } else { 719 MarkPair(loc.reg.GetReg(), loc.reg.GetHighReg()); 720 } 721 if (update) { 722 loc.location = kLocPhysReg; 723 MarkLive(loc.reg.GetReg(), loc.s_reg_low); 724 if (loc.reg.GetReg() != loc.reg.GetHighReg()) { 725 MarkLive(loc.reg.GetHighReg(), GetSRegHi(loc.s_reg_low)); 726 } 727 } 728 return loc; 729} 730 731// TODO: Reunify with common code after 'pair mess' has been fixed 732RegLocation X86Mir2Lir::EvalLoc(RegLocation loc, int reg_class, bool update) { 733 int new_reg; 734 735 if (loc.wide) 736 return EvalLocWide(loc, reg_class, update); 737 738 loc = UpdateLoc(loc); 739 740 if (loc.location == kLocPhysReg) { 741 if (!RegClassMatches(reg_class, loc.reg.GetReg())) { 742 /* Wrong register class. Realloc, copy and transfer ownership. */ 743 new_reg = AllocTypedTemp(loc.fp, reg_class); 744 OpRegCopy(new_reg, loc.reg.GetReg()); 745 CopyRegInfo(new_reg, loc.reg.GetReg()); 746 Clobber(loc.reg.GetReg()); 747 loc.reg.SetReg(new_reg); 748 if (IsFpReg(loc.reg.GetReg()) && reg_class != kCoreReg) 749 loc.vec_len = kVectorLength4; 750 } 751 return loc; 752 } 753 754 DCHECK_NE(loc.s_reg_low, INVALID_SREG); 755 756 loc.reg = RegStorage(RegStorage::k32BitSolo, AllocTypedTemp(loc.fp, reg_class)); 757 if (IsFpReg(loc.reg.GetReg()) && reg_class != kCoreReg) 758 loc.vec_len = kVectorLength4; 759 760 if (update) { 761 loc.location = kLocPhysReg; 762 MarkLive(loc.reg.GetReg(), loc.s_reg_low); 763 } 764 return loc; 765} 766 767int X86Mir2Lir::AllocTempDouble() { 768 // We really don't need a pair of registers. 769 return AllocTempFloat(); 770} 771 772// TODO: Reunify with common code after 'pair mess' has been fixed 773void X86Mir2Lir::ResetDefLocWide(RegLocation rl) { 774 DCHECK(rl.wide); 775 RegisterInfo* p_low = IsTemp(rl.reg.GetReg()); 776 if (IsFpReg(rl.reg.GetReg())) { 777 // We are using only the low register. 778 if (p_low && !(cu_->disable_opt & (1 << kSuppressLoads))) { 779 NullifyRange(p_low->def_start, p_low->def_end, p_low->s_reg, rl.s_reg_low); 780 } 781 ResetDef(rl.reg.GetReg()); 782 } else { 783 RegisterInfo* p_high = IsTemp(rl.reg.GetHighReg()); 784 if (p_low && !(cu_->disable_opt & (1 << kSuppressLoads))) { 785 DCHECK(p_low->pair); 786 NullifyRange(p_low->def_start, p_low->def_end, p_low->s_reg, rl.s_reg_low); 787 } 788 if (p_high && !(cu_->disable_opt & (1 << kSuppressLoads))) { 789 DCHECK(p_high->pair); 790 } 791 ResetDef(rl.reg.GetReg()); 792 ResetDef(rl.reg.GetHighReg()); 793 } 794} 795 796void X86Mir2Lir::GenConstWide(RegLocation rl_dest, int64_t value) { 797 // Can we do this directly to memory? 798 rl_dest = UpdateLocWide(rl_dest); 799 if ((rl_dest.location == kLocDalvikFrame) || 800 (rl_dest.location == kLocCompilerTemp)) { 801 int32_t val_lo = Low32Bits(value); 802 int32_t val_hi = High32Bits(value); 803 int rBase = TargetReg(kSp); 804 int displacement = SRegOffset(rl_dest.s_reg_low); 805 806 LIR * store = NewLIR3(kX86Mov32MI, rBase, displacement + LOWORD_OFFSET, val_lo); 807 AnnotateDalvikRegAccess(store, (displacement + LOWORD_OFFSET) >> 2, 808 false /* is_load */, true /* is64bit */); 809 store = NewLIR3(kX86Mov32MI, rBase, displacement + HIWORD_OFFSET, val_hi); 810 AnnotateDalvikRegAccess(store, (displacement + HIWORD_OFFSET) >> 2, 811 false /* is_load */, true /* is64bit */); 812 return; 813 } 814 815 // Just use the standard code to do the generation. 816 Mir2Lir::GenConstWide(rl_dest, value); 817} 818 819// TODO: Merge with existing RegLocation dumper in vreg_analysis.cc 820void X86Mir2Lir::DumpRegLocation(RegLocation loc) { 821 LOG(INFO) << "location: " << loc.location << ',' 822 << (loc.wide ? " w" : " ") 823 << (loc.defined ? " D" : " ") 824 << (loc.is_const ? " c" : " ") 825 << (loc.fp ? " F" : " ") 826 << (loc.core ? " C" : " ") 827 << (loc.ref ? " r" : " ") 828 << (loc.high_word ? " h" : " ") 829 << (loc.home ? " H" : " ") 830 << " vec_len: " << loc.vec_len 831 << ", low: " << static_cast<int>(loc.reg.GetReg()) 832 << ", high: " << static_cast<int>(loc.reg.GetHighReg()) 833 << ", s_reg: " << loc.s_reg_low 834 << ", orig: " << loc.orig_sreg; 835} 836 837void X86Mir2Lir::Materialize() { 838 // A good place to put the analysis before starting. 839 AnalyzeMIR(); 840 841 // Now continue with regular code generation. 842 Mir2Lir::Materialize(); 843} 844 845void X86Mir2Lir::LoadMethodAddress(const MethodReference& target_method, InvokeType type, 846 SpecialTargetRegister symbolic_reg) { 847 /* 848 * For x86, just generate a 32 bit move immediate instruction, that will be filled 849 * in at 'link time'. For now, put a unique value based on target to ensure that 850 * code deduplication works. 851 */ 852 int target_method_idx = target_method.dex_method_index; 853 const DexFile* target_dex_file = target_method.dex_file; 854 const DexFile::MethodId& target_method_id = target_dex_file->GetMethodId(target_method_idx); 855 uintptr_t target_method_id_ptr = reinterpret_cast<uintptr_t>(&target_method_id); 856 857 // Generate the move instruction with the unique pointer and save index, dex_file, and type. 858 LIR *move = RawLIR(current_dalvik_offset_, kX86Mov32RI, TargetReg(symbolic_reg), 859 static_cast<int>(target_method_id_ptr), target_method_idx, 860 WrapPointer(const_cast<DexFile*>(target_dex_file)), type); 861 AppendLIR(move); 862 method_address_insns_.Insert(move); 863} 864 865void X86Mir2Lir::LoadClassType(uint32_t type_idx, SpecialTargetRegister symbolic_reg) { 866 /* 867 * For x86, just generate a 32 bit move immediate instruction, that will be filled 868 * in at 'link time'. For now, put a unique value based on target to ensure that 869 * code deduplication works. 870 */ 871 const DexFile::TypeId& id = cu_->dex_file->GetTypeId(type_idx); 872 uintptr_t ptr = reinterpret_cast<uintptr_t>(&id); 873 874 // Generate the move instruction with the unique pointer and save index and type. 875 LIR *move = RawLIR(current_dalvik_offset_, kX86Mov32RI, TargetReg(symbolic_reg), 876 static_cast<int>(ptr), type_idx); 877 AppendLIR(move); 878 class_type_address_insns_.Insert(move); 879} 880 881LIR *X86Mir2Lir::CallWithLinkerFixup(const MethodReference& target_method, InvokeType type) { 882 /* 883 * For x86, just generate a 32 bit call relative instruction, that will be filled 884 * in at 'link time'. For now, put a unique value based on target to ensure that 885 * code deduplication works. 886 */ 887 int target_method_idx = target_method.dex_method_index; 888 const DexFile* target_dex_file = target_method.dex_file; 889 const DexFile::MethodId& target_method_id = target_dex_file->GetMethodId(target_method_idx); 890 uintptr_t target_method_id_ptr = reinterpret_cast<uintptr_t>(&target_method_id); 891 892 // Generate the call instruction with the unique pointer and save index, dex_file, and type. 893 LIR *call = RawLIR(current_dalvik_offset_, kX86CallI, static_cast<int>(target_method_id_ptr), 894 target_method_idx, WrapPointer(const_cast<DexFile*>(target_dex_file)), type); 895 AppendLIR(call); 896 call_method_insns_.Insert(call); 897 return call; 898} 899 900void X86Mir2Lir::InstallLiteralPools() { 901 // These are handled differently for x86. 902 DCHECK(code_literal_list_ == nullptr); 903 DCHECK(method_literal_list_ == nullptr); 904 DCHECK(class_literal_list_ == nullptr); 905 906 // Handle the fixups for methods. 907 for (uint32_t i = 0; i < method_address_insns_.Size(); i++) { 908 LIR* p = method_address_insns_.Get(i); 909 DCHECK_EQ(p->opcode, kX86Mov32RI); 910 uint32_t target_method_idx = p->operands[2]; 911 const DexFile* target_dex_file = 912 reinterpret_cast<const DexFile*>(UnwrapPointer(p->operands[3])); 913 914 // The offset to patch is the last 4 bytes of the instruction. 915 int patch_offset = p->offset + p->flags.size - 4; 916 cu_->compiler_driver->AddMethodPatch(cu_->dex_file, cu_->class_def_idx, 917 cu_->method_idx, cu_->invoke_type, 918 target_method_idx, target_dex_file, 919 static_cast<InvokeType>(p->operands[4]), 920 patch_offset); 921 } 922 923 // Handle the fixups for class types. 924 for (uint32_t i = 0; i < class_type_address_insns_.Size(); i++) { 925 LIR* p = class_type_address_insns_.Get(i); 926 DCHECK_EQ(p->opcode, kX86Mov32RI); 927 uint32_t target_method_idx = p->operands[2]; 928 929 // The offset to patch is the last 4 bytes of the instruction. 930 int patch_offset = p->offset + p->flags.size - 4; 931 cu_->compiler_driver->AddClassPatch(cu_->dex_file, cu_->class_def_idx, 932 cu_->method_idx, target_method_idx, patch_offset); 933 } 934 935 // And now the PC-relative calls to methods. 936 for (uint32_t i = 0; i < call_method_insns_.Size(); i++) { 937 LIR* p = call_method_insns_.Get(i); 938 DCHECK_EQ(p->opcode, kX86CallI); 939 uint32_t target_method_idx = p->operands[1]; 940 const DexFile* target_dex_file = 941 reinterpret_cast<const DexFile*>(UnwrapPointer(p->operands[2])); 942 943 // The offset to patch is the last 4 bytes of the instruction. 944 int patch_offset = p->offset + p->flags.size - 4; 945 cu_->compiler_driver->AddRelativeCodePatch(cu_->dex_file, cu_->class_def_idx, 946 cu_->method_idx, cu_->invoke_type, 947 target_method_idx, target_dex_file, 948 static_cast<InvokeType>(p->operands[3]), 949 patch_offset, -4 /* offset */); 950 } 951 952 // And do the normal processing. 953 Mir2Lir::InstallLiteralPools(); 954} 955 956/* 957 * Fast string.index_of(I) & (II). Inline check for simple case of char <= 0xffff, 958 * otherwise bails to standard library code. 959 */ 960bool X86Mir2Lir::GenInlinedIndexOf(CallInfo* info, bool zero_based) { 961 ClobberCallerSave(); 962 LockCallTemps(); // Using fixed registers 963 964 // EAX: 16 bit character being searched. 965 // ECX: count: number of words to be searched. 966 // EDI: String being searched. 967 // EDX: temporary during execution. 968 // EBX: temporary during execution. 969 970 RegLocation rl_obj = info->args[0]; 971 RegLocation rl_char = info->args[1]; 972 RegLocation rl_start; // Note: only present in III flavor or IndexOf. 973 974 uint32_t char_value = 975 rl_char.is_const ? mir_graph_->ConstantValue(rl_char.orig_sreg) : 0; 976 977 if (char_value > 0xFFFF) { 978 // We have to punt to the real String.indexOf. 979 return false; 980 } 981 982 // Okay, we are commited to inlining this. 983 RegLocation rl_return = GetReturn(false); 984 RegLocation rl_dest = InlineTarget(info); 985 986 // Is the string non-NULL? 987 LoadValueDirectFixed(rl_obj, rDX); 988 GenNullCheck(rDX, info->opt_flags); 989 info->opt_flags |= MIR_IGNORE_NULL_CHECK; // Record that we've null checked. 990 991 // Does the character fit in 16 bits? 992 LIR* launchpad_branch = nullptr; 993 if (rl_char.is_const) { 994 // We need the value in EAX. 995 LoadConstantNoClobber(rAX, char_value); 996 } else { 997 // Character is not a constant; compare at runtime. 998 LoadValueDirectFixed(rl_char, rAX); 999 launchpad_branch = OpCmpImmBranch(kCondGt, rAX, 0xFFFF, nullptr); 1000 } 1001 1002 // From here down, we know that we are looking for a char that fits in 16 bits. 1003 // Location of reference to data array within the String object. 1004 int value_offset = mirror::String::ValueOffset().Int32Value(); 1005 // Location of count within the String object. 1006 int count_offset = mirror::String::CountOffset().Int32Value(); 1007 // Starting offset within data array. 1008 int offset_offset = mirror::String::OffsetOffset().Int32Value(); 1009 // Start of char data with array_. 1010 int data_offset = mirror::Array::DataOffset(sizeof(uint16_t)).Int32Value(); 1011 1012 // Character is in EAX. 1013 // Object pointer is in EDX. 1014 1015 // We need to preserve EDI, but have no spare registers, so push it on the stack. 1016 // We have to remember that all stack addresses after this are offset by sizeof(EDI). 1017 NewLIR1(kX86Push32R, rDI); 1018 1019 // Compute the number of words to search in to rCX. 1020 LoadWordDisp(rDX, count_offset, rCX); 1021 LIR *length_compare = nullptr; 1022 int start_value = 0; 1023 if (zero_based) { 1024 // We have to handle an empty string. Use special instruction JECXZ. 1025 length_compare = NewLIR0(kX86Jecxz8); 1026 } else { 1027 rl_start = info->args[2]; 1028 // We have to offset by the start index. 1029 if (rl_start.is_const) { 1030 start_value = mir_graph_->ConstantValue(rl_start.orig_sreg); 1031 start_value = std::max(start_value, 0); 1032 1033 // Is the start > count? 1034 length_compare = OpCmpImmBranch(kCondLe, rCX, start_value, nullptr); 1035 1036 if (start_value != 0) { 1037 OpRegImm(kOpSub, rCX, start_value); 1038 } 1039 } else { 1040 // Runtime start index. 1041 rl_start = UpdateLoc(rl_start); 1042 if (rl_start.location == kLocPhysReg) { 1043 length_compare = OpCmpBranch(kCondLe, rCX, rl_start.reg.GetReg(), nullptr); 1044 OpRegReg(kOpSub, rCX, rl_start.reg.GetReg()); 1045 } else { 1046 // Compare to memory to avoid a register load. Handle pushed EDI. 1047 int displacement = SRegOffset(rl_start.s_reg_low) + sizeof(uint32_t); 1048 OpRegMem(kOpCmp, rCX, rX86_SP, displacement); 1049 length_compare = NewLIR2(kX86Jcc8, 0, kX86CondLe); 1050 OpRegMem(kOpSub, rCX, rX86_SP, displacement); 1051 } 1052 } 1053 } 1054 DCHECK(length_compare != nullptr); 1055 1056 // ECX now contains the count in words to be searched. 1057 1058 // Load the address of the string into EBX. 1059 // The string starts at VALUE(String) + 2 * OFFSET(String) + DATA_OFFSET. 1060 LoadWordDisp(rDX, value_offset, rDI); 1061 LoadWordDisp(rDX, offset_offset, rBX); 1062 OpLea(rBX, rDI, rBX, 1, data_offset); 1063 1064 // Now compute into EDI where the search will start. 1065 if (zero_based || rl_start.is_const) { 1066 if (start_value == 0) { 1067 OpRegCopy(rDI, rBX); 1068 } else { 1069 NewLIR3(kX86Lea32RM, rDI, rBX, 2 * start_value); 1070 } 1071 } else { 1072 if (rl_start.location == kLocPhysReg) { 1073 if (rl_start.reg.GetReg() == rDI) { 1074 // We have a slight problem here. We are already using RDI! 1075 // Grab the value from the stack. 1076 LoadWordDisp(rX86_SP, 0, rDX); 1077 OpLea(rDI, rBX, rDX, 1, 0); 1078 } else { 1079 OpLea(rDI, rBX, rl_start.reg.GetReg(), 1, 0); 1080 } 1081 } else { 1082 OpRegCopy(rDI, rBX); 1083 // Load the start index from stack, remembering that we pushed EDI. 1084 int displacement = SRegOffset(rl_start.s_reg_low) + sizeof(uint32_t); 1085 LoadWordDisp(rX86_SP, displacement, rDX); 1086 OpLea(rDI, rBX, rDX, 1, 0); 1087 } 1088 } 1089 1090 // EDI now contains the start of the string to be searched. 1091 // We are all prepared to do the search for the character. 1092 NewLIR0(kX86RepneScasw); 1093 1094 // Did we find a match? 1095 LIR* failed_branch = OpCondBranch(kCondNe, nullptr); 1096 1097 // yes, we matched. Compute the index of the result. 1098 // index = ((curr_ptr - orig_ptr) / 2) - 1. 1099 OpRegReg(kOpSub, rDI, rBX); 1100 OpRegImm(kOpAsr, rDI, 1); 1101 NewLIR3(kX86Lea32RM, rl_return.reg.GetReg(), rDI, -1); 1102 LIR *all_done = NewLIR1(kX86Jmp8, 0); 1103 1104 // Failed to match; return -1. 1105 LIR *not_found = NewLIR0(kPseudoTargetLabel); 1106 length_compare->target = not_found; 1107 failed_branch->target = not_found; 1108 LoadConstantNoClobber(rl_return.reg.GetReg(), -1); 1109 1110 // And join up at the end. 1111 all_done->target = NewLIR0(kPseudoTargetLabel); 1112 // Restore EDI from the stack. 1113 NewLIR1(kX86Pop32R, rDI); 1114 1115 // Out of line code returns here. 1116 if (launchpad_branch != nullptr) { 1117 LIR *return_point = NewLIR0(kPseudoTargetLabel); 1118 AddIntrinsicLaunchpad(info, launchpad_branch, return_point); 1119 } 1120 1121 StoreValue(rl_dest, rl_return); 1122 return true; 1123} 1124 1125/* 1126 * @brief Enter a 32 bit quantity into the FDE buffer 1127 * @param buf FDE buffer. 1128 * @param data Data value. 1129 */ 1130static void PushWord(std::vector<uint8_t>&buf, int data) { 1131 buf.push_back(data & 0xff); 1132 buf.push_back((data >> 8) & 0xff); 1133 buf.push_back((data >> 16) & 0xff); 1134 buf.push_back((data >> 24) & 0xff); 1135} 1136 1137/* 1138 * @brief Enter an 'advance LOC' into the FDE buffer 1139 * @param buf FDE buffer. 1140 * @param increment Amount by which to increase the current location. 1141 */ 1142static void AdvanceLoc(std::vector<uint8_t>&buf, uint32_t increment) { 1143 if (increment < 64) { 1144 // Encoding in opcode. 1145 buf.push_back(0x1 << 6 | increment); 1146 } else if (increment < 256) { 1147 // Single byte delta. 1148 buf.push_back(0x02); 1149 buf.push_back(increment); 1150 } else if (increment < 256 * 256) { 1151 // Two byte delta. 1152 buf.push_back(0x03); 1153 buf.push_back(increment & 0xff); 1154 buf.push_back((increment >> 8) & 0xff); 1155 } else { 1156 // Four byte delta. 1157 buf.push_back(0x04); 1158 PushWord(buf, increment); 1159 } 1160} 1161 1162 1163std::vector<uint8_t>* X86CFIInitialization() { 1164 return X86Mir2Lir::ReturnCommonCallFrameInformation(); 1165} 1166 1167std::vector<uint8_t>* X86Mir2Lir::ReturnCommonCallFrameInformation() { 1168 std::vector<uint8_t>*cfi_info = new std::vector<uint8_t>; 1169 1170 // Length of the CIE (except for this field). 1171 PushWord(*cfi_info, 16); 1172 1173 // CIE id. 1174 PushWord(*cfi_info, 0xFFFFFFFFU); 1175 1176 // Version: 3. 1177 cfi_info->push_back(0x03); 1178 1179 // Augmentation: empty string. 1180 cfi_info->push_back(0x0); 1181 1182 // Code alignment: 1. 1183 cfi_info->push_back(0x01); 1184 1185 // Data alignment: -4. 1186 cfi_info->push_back(0x7C); 1187 1188 // Return address register (R8). 1189 cfi_info->push_back(0x08); 1190 1191 // Initial return PC is 4(ESP): DW_CFA_def_cfa R4 4. 1192 cfi_info->push_back(0x0C); 1193 cfi_info->push_back(0x04); 1194 cfi_info->push_back(0x04); 1195 1196 // Return address location: 0(SP): DW_CFA_offset R8 1 (* -4);. 1197 cfi_info->push_back(0x2 << 6 | 0x08); 1198 cfi_info->push_back(0x01); 1199 1200 // And 2 Noops to align to 4 byte boundary. 1201 cfi_info->push_back(0x0); 1202 cfi_info->push_back(0x0); 1203 1204 DCHECK_EQ(cfi_info->size() & 3, 0U); 1205 return cfi_info; 1206} 1207 1208static void EncodeUnsignedLeb128(std::vector<uint8_t>& buf, uint32_t value) { 1209 uint8_t buffer[12]; 1210 uint8_t *ptr = EncodeUnsignedLeb128(buffer, value); 1211 for (uint8_t *p = buffer; p < ptr; p++) { 1212 buf.push_back(*p); 1213 } 1214} 1215 1216std::vector<uint8_t>* X86Mir2Lir::ReturnCallFrameInformation() { 1217 std::vector<uint8_t>*cfi_info = new std::vector<uint8_t>; 1218 1219 // Generate the FDE for the method. 1220 DCHECK_NE(data_offset_, 0U); 1221 1222 // Length (will be filled in later in this routine). 1223 PushWord(*cfi_info, 0); 1224 1225 // CIE_pointer (can be filled in by linker); might be left at 0 if there is only 1226 // one CIE for the whole debug_frame section. 1227 PushWord(*cfi_info, 0); 1228 1229 // 'initial_location' (filled in by linker). 1230 PushWord(*cfi_info, 0); 1231 1232 // 'address_range' (number of bytes in the method). 1233 PushWord(*cfi_info, data_offset_); 1234 1235 // The instructions in the FDE. 1236 if (stack_decrement_ != nullptr) { 1237 // Advance LOC to just past the stack decrement. 1238 uint32_t pc = NEXT_LIR(stack_decrement_)->offset; 1239 AdvanceLoc(*cfi_info, pc); 1240 1241 // Now update the offset to the call frame: DW_CFA_def_cfa_offset frame_size. 1242 cfi_info->push_back(0x0e); 1243 EncodeUnsignedLeb128(*cfi_info, frame_size_); 1244 1245 // We continue with that stack until the epilogue. 1246 if (stack_increment_ != nullptr) { 1247 uint32_t new_pc = NEXT_LIR(stack_increment_)->offset; 1248 AdvanceLoc(*cfi_info, new_pc - pc); 1249 1250 // We probably have code snippets after the epilogue, so save the 1251 // current state: DW_CFA_remember_state. 1252 cfi_info->push_back(0x0a); 1253 1254 // We have now popped the stack: DW_CFA_def_cfa_offset 4. There is only the return 1255 // PC on the stack now. 1256 cfi_info->push_back(0x0e); 1257 EncodeUnsignedLeb128(*cfi_info, 4); 1258 1259 // Everything after that is the same as before the epilogue. 1260 // Stack bump was followed by RET instruction. 1261 LIR *post_ret_insn = NEXT_LIR(NEXT_LIR(stack_increment_)); 1262 if (post_ret_insn != nullptr) { 1263 pc = new_pc; 1264 new_pc = post_ret_insn->offset; 1265 AdvanceLoc(*cfi_info, new_pc - pc); 1266 // Restore the state: DW_CFA_restore_state. 1267 cfi_info->push_back(0x0b); 1268 } 1269 } 1270 } 1271 1272 // Padding to a multiple of 4 1273 while ((cfi_info->size() & 3) != 0) { 1274 // DW_CFA_nop is encoded as 0. 1275 cfi_info->push_back(0); 1276 } 1277 1278 // Set the length of the FDE inside the generated bytes. 1279 uint32_t length = cfi_info->size() - 4; 1280 (*cfi_info)[0] = length; 1281 (*cfi_info)[1] = length >> 8; 1282 (*cfi_info)[2] = length >> 16; 1283 (*cfi_info)[3] = length >> 24; 1284 return cfi_info; 1285} 1286 1287} // namespace art 1288