target_x86.cc revision f3e2cc4a38389aa75eb8ee3973a535254bf1c8d2 
1/*
2 * Copyright (C) 2012 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 *      http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#include <string>
18#include <inttypes.h>
19
20#include "codegen_x86.h"
21#include "dex/compiler_internals.h"
22#include "dex/quick/mir_to_lir-inl.h"
23#include "x86_lir.h"
24
25namespace art {
26
27// FIXME: restore "static" when usage uncovered
28/*static*/ int core_regs[] = {
29  rAX, rCX, rDX, rBX, rX86_SP, rBP, rSI, rDI
30#ifdef TARGET_REX_SUPPORT
31  r8, r9, r10, r11, r12, r13, r14, 15
32#endif
33};
34/*static*/ int ReservedRegs[] = {rX86_SP};
35/*static*/ int core_temps[] = {rAX, rCX, rDX, rBX};
36/*static*/ int FpRegs[] = {
37  fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7,
38#ifdef TARGET_REX_SUPPORT
39  fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15
40#endif
41};
42/*static*/ int fp_temps[] = {
43  fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7,
44#ifdef TARGET_REX_SUPPORT
45  fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15
46#endif
47};
48
49RegLocation X86Mir2Lir::LocCReturn() {
50  RegLocation res = X86_LOC_C_RETURN;
51  return res;
52}
53
54RegLocation X86Mir2Lir::LocCReturnWide() {
55  RegLocation res = X86_LOC_C_RETURN_WIDE;
56  return res;
57}
58
59RegLocation X86Mir2Lir::LocCReturnFloat() {
60  RegLocation res = X86_LOC_C_RETURN_FLOAT;
61  return res;
62}
63
64RegLocation X86Mir2Lir::LocCReturnDouble() {
65  RegLocation res = X86_LOC_C_RETURN_DOUBLE;
66  return res;
67}
68
69// Return a target-dependent special register.
70int X86Mir2Lir::TargetReg(SpecialTargetRegister reg) {
71  int res = INVALID_REG;
72  switch (reg) {
73    case kSelf: res = rX86_SELF; break;
74    case kSuspend: res =  rX86_SUSPEND; break;
75    case kLr: res =  rX86_LR; break;
76    case kPc: res =  rX86_PC; break;
77    case kSp: res =  rX86_SP; break;
78    case kArg0: res = rX86_ARG0; break;
79    case kArg1: res = rX86_ARG1; break;
80    case kArg2: res = rX86_ARG2; break;
81    case kArg3: res = rX86_ARG3; break;
82    case kFArg0: res = rX86_FARG0; break;
83    case kFArg1: res = rX86_FARG1; break;
84    case kFArg2: res = rX86_FARG2; break;
85    case kFArg3: res = rX86_FARG3; break;
86    case kRet0: res = rX86_RET0; break;
87    case kRet1: res = rX86_RET1; break;
88    case kInvokeTgt: res = rX86_INVOKE_TGT; break;
89    case kHiddenArg: res = rAX; break;
90    case kHiddenFpArg: res = fr0; break;
91    case kCount: res = rX86_COUNT; break;
92  }
93  return res;
94}
95
96int X86Mir2Lir::GetArgMappingToPhysicalReg(int arg_num) {
97  // For the 32-bit internal ABI, the first 3 arguments are passed in registers.
98  // TODO: This is not 64-bit compliant and depends on new internal ABI.
99  switch (arg_num) {
100    case 0:
101      return rX86_ARG1;
102    case 1:
103      return rX86_ARG2;
104    case 2:
105      return rX86_ARG3;
106    default:
107      return INVALID_REG;
108  }
109}
110
111// Create a double from a pair of singles.
112int X86Mir2Lir::S2d(int low_reg, int high_reg) {
113  return X86_S2D(low_reg, high_reg);
114}
115
116// Return mask to strip off fp reg flags and bias.
117uint32_t X86Mir2Lir::FpRegMask() {
118  return X86_FP_REG_MASK;
119}
120
121// True if both regs single, both core or both double.
122bool X86Mir2Lir::SameRegType(int reg1, int reg2) {
123  return (X86_REGTYPE(reg1) == X86_REGTYPE(reg2));
124}
125
126/*
127 * Decode the register id.
128 */
129uint64_t X86Mir2Lir::GetRegMaskCommon(int reg) {
130  uint64_t seed;
131  int shift;
132  int reg_id;
133
134  reg_id = reg & 0xf;
135  /* Double registers in x86 are just a single FP register */
136  seed = 1;
137  /* FP register starts at bit position 16 */
138  shift = X86_FPREG(reg) ? kX86FPReg0 : 0;
139  /* Expand the double register id into single offset */
140  shift += reg_id;
141  return (seed << shift);
142}
143
144uint64_t X86Mir2Lir::GetPCUseDefEncoding() {
145  /*
146   * FIXME: might make sense to use a virtual resource encoding bit for pc.  Might be
147   * able to clean up some of the x86/Arm_Mips differences
148   */
149  LOG(FATAL) << "Unexpected call to GetPCUseDefEncoding for x86";
150  return 0ULL;
151}
152
153void X86Mir2Lir::SetupTargetResourceMasks(LIR* lir, uint64_t flags) {
154  DCHECK_EQ(cu_->instruction_set, kX86);
155  DCHECK(!lir->flags.use_def_invalid);
156
157  // X86-specific resource map setup here.
158  if (flags & REG_USE_SP) {
159    lir->u.m.use_mask |= ENCODE_X86_REG_SP;
160  }
161
162  if (flags & REG_DEF_SP) {
163    lir->u.m.def_mask |= ENCODE_X86_REG_SP;
164  }
165
166  if (flags & REG_DEFA) {
167    SetupRegMask(&lir->u.m.def_mask, rAX);
168  }
169
170  if (flags & REG_DEFD) {
171    SetupRegMask(&lir->u.m.def_mask, rDX);
172  }
173  if (flags & REG_USEA) {
174    SetupRegMask(&lir->u.m.use_mask, rAX);
175  }
176
177  if (flags & REG_USEC) {
178    SetupRegMask(&lir->u.m.use_mask, rCX);
179  }
180
181  if (flags & REG_USED) {
182    SetupRegMask(&lir->u.m.use_mask, rDX);
183  }
184
185  if (flags & REG_USEB) {
186    SetupRegMask(&lir->u.m.use_mask, rBX);
187  }
188}
189
190/* For dumping instructions */
191static const char* x86RegName[] = {
192  "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
193  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
194};
195
196static const char* x86CondName[] = {
197  "O",
198  "NO",
199  "B/NAE/C",
200  "NB/AE/NC",
201  "Z/EQ",
202  "NZ/NE",
203  "BE/NA",
204  "NBE/A",
205  "S",
206  "NS",
207  "P/PE",
208  "NP/PO",
209  "L/NGE",
210  "NL/GE",
211  "LE/NG",
212  "NLE/G"
213};
214
215/*
216 * Interpret a format string and build a string no longer than size
217 * See format key in Assemble.cc.
218 */
219std::string X86Mir2Lir::BuildInsnString(const char *fmt, LIR *lir, unsigned char* base_addr) {
220  std::string buf;
221  size_t i = 0;
222  size_t fmt_len = strlen(fmt);
223  while (i < fmt_len) {
224    if (fmt[i] != '!') {
225      buf += fmt[i];
226      i++;
227    } else {
228      i++;
229      DCHECK_LT(i, fmt_len);
230      char operand_number_ch = fmt[i];
231      i++;
232      if (operand_number_ch == '!') {
233        buf += "!";
234      } else {
235        int operand_number = operand_number_ch - '0';
236        DCHECK_LT(operand_number, 6);  // Expect upto 6 LIR operands.
237        DCHECK_LT(i, fmt_len);
238        int operand = lir->operands[operand_number];
239        switch (fmt[i]) {
240          case 'c':
241            DCHECK_LT(static_cast<size_t>(operand), sizeof(x86CondName));
242            buf += x86CondName[operand];
243            break;
244          case 'd':
245            buf += StringPrintf("%d", operand);
246            break;
247          case 'p': {
248            EmbeddedData *tab_rec = reinterpret_cast<EmbeddedData*>(UnwrapPointer(operand));
249            buf += StringPrintf("0x%08x", tab_rec->offset);
250            break;
251          }
252          case 'r':
253            if (X86_FPREG(operand) || X86_DOUBLEREG(operand)) {
254              int fp_reg = operand & X86_FP_REG_MASK;
255              buf += StringPrintf("xmm%d", fp_reg);
256            } else {
257              DCHECK_LT(static_cast<size_t>(operand), sizeof(x86RegName));
258              buf += x86RegName[operand];
259            }
260            break;
261          case 't':
262            buf += StringPrintf("0x%08" PRIxPTR " (L%p)",
263                                reinterpret_cast<uintptr_t>(base_addr) + lir->offset + operand,
264                                lir->target);
265            break;
266          default:
267            buf += StringPrintf("DecodeError '%c'", fmt[i]);
268            break;
269        }
270        i++;
271      }
272    }
273  }
274  return buf;
275}
276
277void X86Mir2Lir::DumpResourceMask(LIR *x86LIR, uint64_t mask, const char *prefix) {
278  char buf[256];
279  buf[0] = 0;
280
281  if (mask == ENCODE_ALL) {
282    strcpy(buf, "all");
283  } else {
284    char num[8];
285    int i;
286
287    for (i = 0; i < kX86RegEnd; i++) {
288      if (mask & (1ULL << i)) {
289        snprintf(num, arraysize(num), "%d ", i);
290        strcat(buf, num);
291      }
292    }
293
294    if (mask & ENCODE_CCODE) {
295      strcat(buf, "cc ");
296    }
297    /* Memory bits */
298    if (x86LIR && (mask & ENCODE_DALVIK_REG)) {
299      snprintf(buf + strlen(buf), arraysize(buf) - strlen(buf), "dr%d%s",
300               DECODE_ALIAS_INFO_REG(x86LIR->flags.alias_info),
301               (DECODE_ALIAS_INFO_WIDE(x86LIR->flags.alias_info)) ? "(+1)" : "");
302    }
303    if (mask & ENCODE_LITERAL) {
304      strcat(buf, "lit ");
305    }
306
307    if (mask & ENCODE_HEAP_REF) {
308      strcat(buf, "heap ");
309    }
310    if (mask & ENCODE_MUST_NOT_ALIAS) {
311      strcat(buf, "noalias ");
312    }
313  }
314  if (buf[0]) {
315    LOG(INFO) << prefix << ": " <<  buf;
316  }
317}
318
319void X86Mir2Lir::AdjustSpillMask() {
320  // Adjustment for LR spilling, x86 has no LR so nothing to do here
321  core_spill_mask_ |= (1 << rRET);
322  num_core_spills_++;
323}
324
325/*
326 * Mark a callee-save fp register as promoted.  Note that
327 * vpush/vpop uses contiguous register lists so we must
328 * include any holes in the mask.  Associate holes with
329 * Dalvik register INVALID_VREG (0xFFFFU).
330 */
331void X86Mir2Lir::MarkPreservedSingle(int v_reg, int reg) {
332  UNIMPLEMENTED(WARNING) << "MarkPreservedSingle";
333#if 0
334  LOG(FATAL) << "No support yet for promoted FP regs";
335#endif
336}
337
338void X86Mir2Lir::FlushRegWide(int reg1, int reg2) {
339  RegisterInfo* info1 = GetRegInfo(reg1);
340  RegisterInfo* info2 = GetRegInfo(reg2);
341  DCHECK(info1 && info2 && info1->pair && info2->pair &&
342         (info1->partner == info2->reg) &&
343         (info2->partner == info1->reg));
344  if ((info1->live && info1->dirty) || (info2->live && info2->dirty)) {
345    if (!(info1->is_temp && info2->is_temp)) {
346      /* Should not happen.  If it does, there's a problem in eval_loc */
347      LOG(FATAL) << "Long half-temp, half-promoted";
348    }
349
350    info1->dirty = false;
351    info2->dirty = false;
352    if (mir_graph_->SRegToVReg(info2->s_reg) < mir_graph_->SRegToVReg(info1->s_reg))
353      info1 = info2;
354    int v_reg = mir_graph_->SRegToVReg(info1->s_reg);
355    StoreBaseDispWide(rX86_SP, VRegOffset(v_reg), info1->reg, info1->partner);
356  }
357}
358
359void X86Mir2Lir::FlushReg(int reg) {
360  RegisterInfo* info = GetRegInfo(reg);
361  if (info->live && info->dirty) {
362    info->dirty = false;
363    int v_reg = mir_graph_->SRegToVReg(info->s_reg);
364    StoreBaseDisp(rX86_SP, VRegOffset(v_reg), reg, kWord);
365  }
366}
367
368/* Give access to the target-dependent FP register encoding to common code */
369bool X86Mir2Lir::IsFpReg(int reg) {
370  return X86_FPREG(reg);
371}
372
373/* Clobber all regs that might be used by an external C call */
374void X86Mir2Lir::ClobberCallerSave() {
375  Clobber(rAX);
376  Clobber(rCX);
377  Clobber(rDX);
378  Clobber(rBX);
379}
380
381RegLocation X86Mir2Lir::GetReturnWideAlt() {
382  RegLocation res = LocCReturnWide();
383  CHECK(res.low_reg == rAX);
384  CHECK(res.high_reg == rDX);
385  Clobber(rAX);
386  Clobber(rDX);
387  MarkInUse(rAX);
388  MarkInUse(rDX);
389  MarkPair(res.low_reg, res.high_reg);
390  return res;
391}
392
393RegLocation X86Mir2Lir::GetReturnAlt() {
394  RegLocation res = LocCReturn();
395  res.low_reg = rDX;
396  Clobber(rDX);
397  MarkInUse(rDX);
398  return res;
399}
400
401/* To be used when explicitly managing register use */
402void X86Mir2Lir::LockCallTemps() {
403  LockTemp(rX86_ARG0);
404  LockTemp(rX86_ARG1);
405  LockTemp(rX86_ARG2);
406  LockTemp(rX86_ARG3);
407}
408
409/* To be used when explicitly managing register use */
410void X86Mir2Lir::FreeCallTemps() {
411  FreeTemp(rX86_ARG0);
412  FreeTemp(rX86_ARG1);
413  FreeTemp(rX86_ARG2);
414  FreeTemp(rX86_ARG3);
415}
416
417void X86Mir2Lir::GenMemBarrier(MemBarrierKind barrier_kind) {
418#if ANDROID_SMP != 0
419  // TODO: optimize fences
420  NewLIR0(kX86Mfence);
421#endif
422}
423/*
424 * Alloc a pair of core registers, or a double.  Low reg in low byte,
425 * high reg in next byte.
426 */
427int X86Mir2Lir::AllocTypedTempPair(bool fp_hint,
428                          int reg_class) {
429  int high_reg;
430  int low_reg;
431  int res = 0;
432
433  if (((reg_class == kAnyReg) && fp_hint) || (reg_class == kFPReg)) {
434    low_reg = AllocTempDouble();
435    high_reg = low_reg;  // only one allocated!
436    res = (low_reg & 0xff) | ((high_reg & 0xff) << 8);
437    return res;
438  }
439
440  low_reg = AllocTemp();
441  high_reg = AllocTemp();
442  res = (low_reg & 0xff) | ((high_reg & 0xff) << 8);
443  return res;
444}
445
446int X86Mir2Lir::AllocTypedTemp(bool fp_hint, int reg_class) {
447  if (((reg_class == kAnyReg) && fp_hint) || (reg_class == kFPReg)) {
448    return AllocTempFloat();
449  }
450  return AllocTemp();
451}
452
453void X86Mir2Lir::CompilerInitializeRegAlloc() {
454  int num_regs = sizeof(core_regs)/sizeof(*core_regs);
455  int num_reserved = sizeof(ReservedRegs)/sizeof(*ReservedRegs);
456  int num_temps = sizeof(core_temps)/sizeof(*core_temps);
457  int num_fp_regs = sizeof(FpRegs)/sizeof(*FpRegs);
458  int num_fp_temps = sizeof(fp_temps)/sizeof(*fp_temps);
459  reg_pool_ = static_cast<RegisterPool*>(arena_->Alloc(sizeof(*reg_pool_),
460                                                       ArenaAllocator::kAllocRegAlloc));
461  reg_pool_->num_core_regs = num_regs;
462  reg_pool_->core_regs =
463      static_cast<RegisterInfo*>(arena_->Alloc(num_regs * sizeof(*reg_pool_->core_regs),
464                                               ArenaAllocator::kAllocRegAlloc));
465  reg_pool_->num_fp_regs = num_fp_regs;
466  reg_pool_->FPRegs =
467      static_cast<RegisterInfo *>(arena_->Alloc(num_fp_regs * sizeof(*reg_pool_->FPRegs),
468                                                ArenaAllocator::kAllocRegAlloc));
469  CompilerInitPool(reg_pool_->core_regs, core_regs, reg_pool_->num_core_regs);
470  CompilerInitPool(reg_pool_->FPRegs, FpRegs, reg_pool_->num_fp_regs);
471  // Keep special registers from being allocated
472  for (int i = 0; i < num_reserved; i++) {
473    MarkInUse(ReservedRegs[i]);
474  }
475  // Mark temp regs - all others not in use can be used for promotion
476  for (int i = 0; i < num_temps; i++) {
477    MarkTemp(core_temps[i]);
478  }
479  for (int i = 0; i < num_fp_temps; i++) {
480    MarkTemp(fp_temps[i]);
481  }
482}
483
484void X86Mir2Lir::FreeRegLocTemps(RegLocation rl_keep,
485                     RegLocation rl_free) {
486  if ((rl_free.low_reg != rl_keep.low_reg) && (rl_free.low_reg != rl_keep.high_reg) &&
487      (rl_free.high_reg != rl_keep.low_reg) && (rl_free.high_reg != rl_keep.high_reg)) {
488    // No overlap, free both
489    FreeTemp(rl_free.low_reg);
490    FreeTemp(rl_free.high_reg);
491  }
492}
493
494void X86Mir2Lir::SpillCoreRegs() {
495  if (num_core_spills_ == 0) {
496    return;
497  }
498  // Spill mask not including fake return address register
499  uint32_t mask = core_spill_mask_ & ~(1 << rRET);
500  int offset = frame_size_ - (4 * num_core_spills_);
501  for (int reg = 0; mask; mask >>= 1, reg++) {
502    if (mask & 0x1) {
503      StoreWordDisp(rX86_SP, offset, reg);
504      offset += 4;
505    }
506  }
507}
508
509void X86Mir2Lir::UnSpillCoreRegs() {
510  if (num_core_spills_ == 0) {
511    return;
512  }
513  // Spill mask not including fake return address register
514  uint32_t mask = core_spill_mask_ & ~(1 << rRET);
515  int offset = frame_size_ - (4 * num_core_spills_);
516  for (int reg = 0; mask; mask >>= 1, reg++) {
517    if (mask & 0x1) {
518      LoadWordDisp(rX86_SP, offset, reg);
519      offset += 4;
520    }
521  }
522}
523
524bool X86Mir2Lir::IsUnconditionalBranch(LIR* lir) {
525  return (lir->opcode == kX86Jmp8 || lir->opcode == kX86Jmp32);
526}
527
528X86Mir2Lir::X86Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena)
529    : Mir2Lir(cu, mir_graph, arena),
530      method_address_insns_(arena, 100, kGrowableArrayMisc),
531      class_type_address_insns_(arena, 100, kGrowableArrayMisc),
532      call_method_insns_(arena, 100, kGrowableArrayMisc) {
533  store_method_addr_used_ = false;
534  for (int i = 0; i < kX86Last; i++) {
535    if (X86Mir2Lir::EncodingMap[i].opcode != i) {
536      LOG(FATAL) << "Encoding order for " << X86Mir2Lir::EncodingMap[i].name
537                 << " is wrong: expecting " << i << ", seeing "
538                 << static_cast<int>(X86Mir2Lir::EncodingMap[i].opcode);
539    }
540  }
541}
542
543Mir2Lir* X86CodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph,
544                          ArenaAllocator* const arena) {
545  return new X86Mir2Lir(cu, mir_graph, arena);
546}
547
548// Not used in x86
549int X86Mir2Lir::LoadHelper(ThreadOffset offset) {
550  LOG(FATAL) << "Unexpected use of LoadHelper in x86";
551  return INVALID_REG;
552}
553
554uint64_t X86Mir2Lir::GetTargetInstFlags(int opcode) {
555  DCHECK(!IsPseudoLirOp(opcode));
556  return X86Mir2Lir::EncodingMap[opcode].flags;
557}
558
559const char* X86Mir2Lir::GetTargetInstName(int opcode) {
560  DCHECK(!IsPseudoLirOp(opcode));
561  return X86Mir2Lir::EncodingMap[opcode].name;
562}
563
564const char* X86Mir2Lir::GetTargetInstFmt(int opcode) {
565  DCHECK(!IsPseudoLirOp(opcode));
566  return X86Mir2Lir::EncodingMap[opcode].fmt;
567}
568
569/*
570 * Return an updated location record with current in-register status.
571 * If the value lives in live temps, reflect that fact.  No code
572 * is generated.  If the live value is part of an older pair,
573 * clobber both low and high.
574 */
575// TODO: Reunify with common code after 'pair mess' has been fixed
576RegLocation X86Mir2Lir::UpdateLocWide(RegLocation loc) {
577  DCHECK(loc.wide);
578  DCHECK(CheckCorePoolSanity());
579  if (loc.location != kLocPhysReg) {
580    DCHECK((loc.location == kLocDalvikFrame) ||
581         (loc.location == kLocCompilerTemp));
582    // Are the dalvik regs already live in physical registers?
583    RegisterInfo* info_lo = AllocLive(loc.s_reg_low, kAnyReg);
584
585    // Handle FP registers specially on x86.
586    if (info_lo && IsFpReg(info_lo->reg)) {
587      bool match = true;
588
589      // We can't match a FP register with a pair of Core registers.
590      match = match && (info_lo->pair == 0);
591
592      if (match) {
593        // We can reuse;update the register usage info.
594        loc.low_reg = info_lo->reg;
595        loc.high_reg = info_lo->reg;  // Play nice with existing code.
596        loc.location = kLocPhysReg;
597        loc.vec_len = kVectorLength8;
598        DCHECK(IsFpReg(loc.low_reg));
599        return loc;
600      }
601      // We can't easily reuse; clobber and free any overlaps.
602      if (info_lo) {
603        Clobber(info_lo->reg);
604        FreeTemp(info_lo->reg);
605        if (info_lo->pair)
606          Clobber(info_lo->partner);
607      }
608    } else {
609      RegisterInfo* info_hi = AllocLive(GetSRegHi(loc.s_reg_low), kAnyReg);
610      bool match = true;
611      match = match && (info_lo != NULL);
612      match = match && (info_hi != NULL);
613      // Are they both core or both FP?
614      match = match && (IsFpReg(info_lo->reg) == IsFpReg(info_hi->reg));
615      // If a pair of floating point singles, are they properly aligned?
616      if (match && IsFpReg(info_lo->reg)) {
617        match &= ((info_lo->reg & 0x1) == 0);
618        match &= ((info_hi->reg - info_lo->reg) == 1);
619      }
620      // If previously used as a pair, it is the same pair?
621      if (match && (info_lo->pair || info_hi->pair)) {
622        match = (info_lo->pair == info_hi->pair);
623        match &= ((info_lo->reg == info_hi->partner) &&
624              (info_hi->reg == info_lo->partner));
625      }
626      if (match) {
627        // Can reuse - update the register usage info
628        loc.low_reg = info_lo->reg;
629        loc.high_reg = info_hi->reg;
630        loc.location = kLocPhysReg;
631        MarkPair(loc.low_reg, loc.high_reg);
632        DCHECK(!IsFpReg(loc.low_reg) || ((loc.low_reg & 0x1) == 0));
633        return loc;
634      }
635      // Can't easily reuse - clobber and free any overlaps
636      if (info_lo) {
637        Clobber(info_lo->reg);
638        FreeTemp(info_lo->reg);
639        if (info_lo->pair)
640          Clobber(info_lo->partner);
641      }
642      if (info_hi) {
643        Clobber(info_hi->reg);
644        FreeTemp(info_hi->reg);
645        if (info_hi->pair)
646          Clobber(info_hi->partner);
647      }
648    }
649  }
650  return loc;
651}
652
653// TODO: Reunify with common code after 'pair mess' has been fixed
654RegLocation X86Mir2Lir::EvalLocWide(RegLocation loc, int reg_class, bool update) {
655  DCHECK(loc.wide);
656  int32_t new_regs;
657  int32_t low_reg;
658  int32_t high_reg;
659
660  loc = UpdateLocWide(loc);
661
662  /* If it is already in a register, we can assume proper form.  Is it the right reg class? */
663  if (loc.location == kLocPhysReg) {
664    DCHECK_EQ(IsFpReg(loc.low_reg), loc.IsVectorScalar());
665    if (!RegClassMatches(reg_class, loc.low_reg)) {
666      /* It is the wrong register class.  Reallocate and copy. */
667      if (!IsFpReg(loc.low_reg)) {
668        // We want this in a FP reg, and it is in core registers.
669        DCHECK(reg_class != kCoreReg);
670        // Allocate this into any FP reg, and mark it with the right size.
671        low_reg = AllocTypedTemp(true, reg_class);
672        OpVectorRegCopyWide(low_reg, loc.low_reg, loc.high_reg);
673        CopyRegInfo(low_reg, loc.low_reg);
674        Clobber(loc.low_reg);
675        Clobber(loc.high_reg);
676        loc.low_reg = low_reg;
677        loc.high_reg = low_reg;  // Play nice with existing code.
678        loc.vec_len = kVectorLength8;
679      } else {
680        // The value is in a FP register, and we want it in a pair of core registers.
681        DCHECK_EQ(reg_class, kCoreReg);
682        DCHECK_EQ(loc.low_reg, loc.high_reg);
683        new_regs = AllocTypedTempPair(false, kCoreReg);  // Force to core registers.
684        low_reg = new_regs & 0xff;
685        high_reg = (new_regs >> 8) & 0xff;
686        DCHECK_NE(low_reg, high_reg);
687        OpRegCopyWide(low_reg, high_reg, loc.low_reg, loc.high_reg);
688        CopyRegInfo(low_reg, loc.low_reg);
689        CopyRegInfo(high_reg, loc.high_reg);
690        Clobber(loc.low_reg);
691        Clobber(loc.high_reg);
692        loc.low_reg = low_reg;
693        loc.high_reg = high_reg;
694        MarkPair(loc.low_reg, loc.high_reg);
695        DCHECK(!IsFpReg(loc.low_reg) || ((loc.low_reg & 0x1) == 0));
696      }
697    }
698    return loc;
699  }
700
701  DCHECK_NE(loc.s_reg_low, INVALID_SREG);
702  DCHECK_NE(GetSRegHi(loc.s_reg_low), INVALID_SREG);
703
704  new_regs = AllocTypedTempPair(loc.fp, reg_class);
705  loc.low_reg = new_regs & 0xff;
706  loc.high_reg = (new_regs >> 8) & 0xff;
707
708  if (loc.low_reg == loc.high_reg) {
709    DCHECK(IsFpReg(loc.low_reg));
710    loc.vec_len = kVectorLength8;
711  } else {
712    MarkPair(loc.low_reg, loc.high_reg);
713  }
714  if (update) {
715    loc.location = kLocPhysReg;
716    MarkLive(loc.low_reg, loc.s_reg_low);
717    if (loc.low_reg != loc.high_reg) {
718      MarkLive(loc.high_reg, GetSRegHi(loc.s_reg_low));
719    }
720  }
721  return loc;
722}
723
724// TODO: Reunify with common code after 'pair mess' has been fixed
725RegLocation X86Mir2Lir::EvalLoc(RegLocation loc, int reg_class, bool update) {
726  int new_reg;
727
728  if (loc.wide)
729    return EvalLocWide(loc, reg_class, update);
730
731  loc = UpdateLoc(loc);
732
733  if (loc.location == kLocPhysReg) {
734    if (!RegClassMatches(reg_class, loc.low_reg)) {
735      /* Wrong register class.  Realloc, copy and transfer ownership. */
736      new_reg = AllocTypedTemp(loc.fp, reg_class);
737      OpRegCopy(new_reg, loc.low_reg);
738      CopyRegInfo(new_reg, loc.low_reg);
739      Clobber(loc.low_reg);
740      loc.low_reg = new_reg;
741      if (IsFpReg(loc.low_reg) && reg_class != kCoreReg)
742        loc.vec_len = kVectorLength4;
743    }
744    return loc;
745  }
746
747  DCHECK_NE(loc.s_reg_low, INVALID_SREG);
748
749  new_reg = AllocTypedTemp(loc.fp, reg_class);
750  loc.low_reg = new_reg;
751  if (IsFpReg(loc.low_reg) && reg_class != kCoreReg)
752    loc.vec_len = kVectorLength4;
753
754  if (update) {
755    loc.location = kLocPhysReg;
756    MarkLive(loc.low_reg, loc.s_reg_low);
757  }
758  return loc;
759}
760
761int X86Mir2Lir::AllocTempDouble() {
762  // We really don't need a pair of registers.
763  return AllocTempFloat();
764}
765
766// TODO: Reunify with common code after 'pair mess' has been fixed
767void X86Mir2Lir::ResetDefLocWide(RegLocation rl) {
768  DCHECK(rl.wide);
769  RegisterInfo* p_low = IsTemp(rl.low_reg);
770  if (IsFpReg(rl.low_reg)) {
771    // We are using only the low register.
772    if (p_low && !(cu_->disable_opt & (1 << kSuppressLoads))) {
773      NullifyRange(p_low->def_start, p_low->def_end, p_low->s_reg, rl.s_reg_low);
774    }
775    ResetDef(rl.low_reg);
776  } else {
777    RegisterInfo* p_high = IsTemp(rl.high_reg);
778    if (p_low && !(cu_->disable_opt & (1 << kSuppressLoads))) {
779      DCHECK(p_low->pair);
780      NullifyRange(p_low->def_start, p_low->def_end, p_low->s_reg, rl.s_reg_low);
781    }
782    if (p_high && !(cu_->disable_opt & (1 << kSuppressLoads))) {
783      DCHECK(p_high->pair);
784    }
785    ResetDef(rl.low_reg);
786    ResetDef(rl.high_reg);
787  }
788}
789
790void X86Mir2Lir::GenConstWide(RegLocation rl_dest, int64_t value) {
791  // Can we do this directly to memory?
792  rl_dest = UpdateLocWide(rl_dest);
793  if ((rl_dest.location == kLocDalvikFrame) ||
794      (rl_dest.location == kLocCompilerTemp)) {
795    int32_t val_lo = Low32Bits(value);
796    int32_t val_hi = High32Bits(value);
797    int rBase = TargetReg(kSp);
798    int displacement = SRegOffset(rl_dest.s_reg_low);
799
800    LIR * store = NewLIR3(kX86Mov32MI, rBase, displacement + LOWORD_OFFSET, val_lo);
801    AnnotateDalvikRegAccess(store, (displacement + LOWORD_OFFSET) >> 2,
802                              false /* is_load */, true /* is64bit */);
803    store = NewLIR3(kX86Mov32MI, rBase, displacement + HIWORD_OFFSET, val_hi);
804    AnnotateDalvikRegAccess(store, (displacement + HIWORD_OFFSET) >> 2,
805                              false /* is_load */, true /* is64bit */);
806    return;
807  }
808
809  // Just use the standard code to do the generation.
810  Mir2Lir::GenConstWide(rl_dest, value);
811}
812
813// TODO: Merge with existing RegLocation dumper in vreg_analysis.cc
814void X86Mir2Lir::DumpRegLocation(RegLocation loc) {
815  LOG(INFO)  << "location: " << loc.location << ','
816             << (loc.wide ? " w" : "  ")
817             << (loc.defined ? " D" : "  ")
818             << (loc.is_const ? " c" : "  ")
819             << (loc.fp ? " F" : "  ")
820             << (loc.core ? " C" : "  ")
821             << (loc.ref ? " r" : "  ")
822             << (loc.high_word ? " h" : "  ")
823             << (loc.home ? " H" : "  ")
824             << " vec_len: " << loc.vec_len
825             << ", low: " << static_cast<int>(loc.low_reg)
826             << ", high: " << static_cast<int>(loc.high_reg)
827             << ", s_reg: " << loc.s_reg_low
828             << ", orig: " << loc.orig_sreg;
829}
830
831void X86Mir2Lir::Materialize() {
832  // A good place to put the analysis before starting.
833  AnalyzeMIR();
834
835  // Now continue with regular code generation.
836  Mir2Lir::Materialize();
837}
838
839void X86Mir2Lir::LoadMethodAddress(int dex_method_index, InvokeType type,
840                                   SpecialTargetRegister symbolic_reg) {
841  /*
842   * For x86, just generate a 32 bit move immediate instruction, that will be filled
843   * in at 'link time'.  For now, put a unique value based on target to ensure that
844   * code deduplication works.
845   */
846  const DexFile::MethodId& id = cu_->dex_file->GetMethodId(dex_method_index);
847  uintptr_t ptr = reinterpret_cast<uintptr_t>(&id);
848
849  // Generate the move instruction with the unique pointer and save index and type.
850  LIR *move = RawLIR(current_dalvik_offset_, kX86Mov32RI, TargetReg(symbolic_reg),
851                     static_cast<int>(ptr), dex_method_index, type);
852  AppendLIR(move);
853  method_address_insns_.Insert(move);
854}
855
856void X86Mir2Lir::LoadClassType(uint32_t type_idx, SpecialTargetRegister symbolic_reg) {
857  /*
858   * For x86, just generate a 32 bit move immediate instruction, that will be filled
859   * in at 'link time'.  For now, put a unique value based on target to ensure that
860   * code deduplication works.
861   */
862  const DexFile::TypeId& id = cu_->dex_file->GetTypeId(type_idx);
863  uintptr_t ptr = reinterpret_cast<uintptr_t>(&id);
864
865  // Generate the move instruction with the unique pointer and save index and type.
866  LIR *move = RawLIR(current_dalvik_offset_, kX86Mov32RI, TargetReg(symbolic_reg),
867                     static_cast<int>(ptr), type_idx);
868  AppendLIR(move);
869  class_type_address_insns_.Insert(move);
870}
871
872LIR *X86Mir2Lir::CallWithLinkerFixup(int dex_method_index, InvokeType type) {
873  /*
874   * For x86, just generate a 32 bit call relative instruction, that will be filled
875   * in at 'link time'.  For now, put a unique value based on target to ensure that
876   * code deduplication works.
877   */
878  const DexFile::MethodId& id = cu_->dex_file->GetMethodId(dex_method_index);
879  uintptr_t ptr = reinterpret_cast<uintptr_t>(&id);
880
881  // Generate the call instruction with the unique pointer and save index and type.
882  LIR *call = RawLIR(current_dalvik_offset_, kX86CallI, static_cast<int>(ptr), dex_method_index,
883                     type);
884  AppendLIR(call);
885  call_method_insns_.Insert(call);
886  return call;
887}
888
889void X86Mir2Lir::InstallLiteralPools() {
890  // These are handled differently for x86.
891  DCHECK(code_literal_list_ == nullptr);
892  DCHECK(method_literal_list_ == nullptr);
893  DCHECK(class_literal_list_ == nullptr);
894
895  // Handle the fixups for methods.
896  for (uint32_t i = 0; i < method_address_insns_.Size(); i++) {
897      LIR* p = method_address_insns_.Get(i);
898      DCHECK_EQ(p->opcode, kX86Mov32RI);
899      uint32_t target = p->operands[2];
900
901      // The offset to patch is the last 4 bytes of the instruction.
902      int patch_offset = p->offset + p->flags.size - 4;
903      cu_->compiler_driver->AddMethodPatch(cu_->dex_file, cu_->class_def_idx,
904                                           cu_->method_idx, cu_->invoke_type,
905                                           target, static_cast<InvokeType>(p->operands[3]),
906                                           patch_offset);
907  }
908
909  // Handle the fixups for class types.
910  for (uint32_t i = 0; i < class_type_address_insns_.Size(); i++) {
911      LIR* p = class_type_address_insns_.Get(i);
912      DCHECK_EQ(p->opcode, kX86Mov32RI);
913      uint32_t target = p->operands[2];
914
915      // The offset to patch is the last 4 bytes of the instruction.
916      int patch_offset = p->offset + p->flags.size - 4;
917      cu_->compiler_driver->AddClassPatch(cu_->dex_file, cu_->class_def_idx,
918                                          cu_->method_idx, target, patch_offset);
919  }
920
921  // And now the PC-relative calls to methods.
922  for (uint32_t i = 0; i < call_method_insns_.Size(); i++) {
923      LIR* p = call_method_insns_.Get(i);
924      DCHECK_EQ(p->opcode, kX86CallI);
925      uint32_t target = p->operands[1];
926
927      // The offset to patch is the last 4 bytes of the instruction.
928      int patch_offset = p->offset + p->flags.size - 4;
929      cu_->compiler_driver->AddRelativeCodePatch(cu_->dex_file, cu_->class_def_idx,
930                                                 cu_->method_idx, cu_->invoke_type, target,
931                                                 static_cast<InvokeType>(p->operands[2]),
932                                                 patch_offset, -4 /* offset */);
933  }
934
935  // And do the normal processing.
936  Mir2Lir::InstallLiteralPools();
937}
938
939}  // namespace art
940