assembler_x86_64.cc revision 1a43dd78d054dbad8d7af9ba4829ea2f1cb70b53 
1/*
2 * Copyright (C) 2014 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 *      http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#include "assembler_x86_64.h"
18
19#include "base/casts.h"
20#include "entrypoints/quick/quick_entrypoints.h"
21#include "memory_region.h"
22#include "thread.h"
23
24namespace art {
25namespace x86_64 {
26
27std::ostream& operator<<(std::ostream& os, const CpuRegister& reg) {
28  return os << reg.AsRegister();
29}
30
31std::ostream& operator<<(std::ostream& os, const XmmRegister& reg) {
32  return os << reg.AsFloatRegister();
33}
34
35std::ostream& operator<<(std::ostream& os, const X87Register& reg) {
36  return os << "ST" << static_cast<int>(reg);
37}
38
39void X86_64Assembler::call(CpuRegister reg) {
40  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
41  EmitOptionalRex32(reg);
42  EmitUint8(0xFF);
43  EmitRegisterOperand(2, reg.LowBits());
44}
45
46
47void X86_64Assembler::call(const Address& address) {
48  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
49  EmitOptionalRex32(address);
50  EmitUint8(0xFF);
51  EmitOperand(2, address);
52}
53
54
55void X86_64Assembler::call(Label* label) {
56  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
57  EmitUint8(0xE8);
58  static const int kSize = 5;
59  EmitLabel(label, kSize);
60}
61
62void X86_64Assembler::pushq(CpuRegister reg) {
63  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
64  EmitOptionalRex32(reg);
65  EmitUint8(0x50 + reg.LowBits());
66}
67
68
69void X86_64Assembler::pushq(const Address& address) {
70  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
71  EmitOptionalRex32(address);
72  EmitUint8(0xFF);
73  EmitOperand(6, address);
74}
75
76
77void X86_64Assembler::pushq(const Immediate& imm) {
78  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
79  CHECK(imm.is_int32());  // pushq only supports 32b immediate.
80  if (imm.is_int8()) {
81    EmitUint8(0x6A);
82    EmitUint8(imm.value() & 0xFF);
83  } else {
84    EmitUint8(0x68);
85    EmitImmediate(imm);
86  }
87}
88
89
90void X86_64Assembler::popq(CpuRegister reg) {
91  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
92  EmitOptionalRex32(reg);
93  EmitUint8(0x58 + reg.LowBits());
94}
95
96
97void X86_64Assembler::popq(const Address& address) {
98  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
99  EmitOptionalRex32(address);
100  EmitUint8(0x8F);
101  EmitOperand(0, address);
102}
103
104
105void X86_64Assembler::movq(CpuRegister dst, const Immediate& imm) {
106  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
107  if (imm.is_int32()) {
108    // 32 bit. Note: sign-extends.
109    EmitRex64(dst);
110    EmitUint8(0xC7);
111    EmitRegisterOperand(0, dst.LowBits());
112    EmitInt32(static_cast<int32_t>(imm.value()));
113  } else {
114    EmitRex64(dst);
115    EmitUint8(0xB8 + dst.LowBits());
116    EmitInt64(imm.value());
117  }
118}
119
120
121void X86_64Assembler::movl(CpuRegister dst, const Immediate& imm) {
122  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
123  EmitOptionalRex32(dst);
124  EmitUint8(0xB8 + dst.LowBits());
125  EmitImmediate(imm);
126}
127
128
129void X86_64Assembler::movq(CpuRegister dst, CpuRegister src) {
130  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
131  // 0x89 is movq r/m64 <- r64, with op1 in r/m and op2 in reg: so reverse EmitRex64
132  EmitRex64(src, dst);
133  EmitUint8(0x89);
134  EmitRegisterOperand(src.LowBits(), dst.LowBits());
135}
136
137
138void X86_64Assembler::movl(CpuRegister dst, CpuRegister src) {
139  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
140  EmitOptionalRex32(dst, src);
141  EmitUint8(0x8B);
142  EmitRegisterOperand(dst.LowBits(), src.LowBits());
143}
144
145
146void X86_64Assembler::movq(CpuRegister dst, const Address& src) {
147  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
148  EmitRex64(dst, src);
149  EmitUint8(0x8B);
150  EmitOperand(dst.LowBits(), src);
151}
152
153
154void X86_64Assembler::movl(CpuRegister dst, const Address& src) {
155  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
156  EmitOptionalRex32(dst, src);
157  EmitUint8(0x8B);
158  EmitOperand(dst.LowBits(), src);
159}
160
161
162void X86_64Assembler::movq(const Address& dst, CpuRegister src) {
163  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
164  EmitRex64(src, dst);
165  EmitUint8(0x89);
166  EmitOperand(src.LowBits(), dst);
167}
168
169
170void X86_64Assembler::movl(const Address& dst, CpuRegister src) {
171  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
172  EmitOptionalRex32(src, dst);
173  EmitUint8(0x89);
174  EmitOperand(src.LowBits(), dst);
175}
176
177void X86_64Assembler::movl(const Address& dst, const Immediate& imm) {
178  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
179  EmitOptionalRex32(dst);
180  EmitUint8(0xC7);
181  EmitOperand(0, dst);
182  EmitImmediate(imm);
183}
184
185void X86_64Assembler::movzxb(CpuRegister dst, CpuRegister src) {
186  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
187  EmitOptionalByteRegNormalizingRex32(dst, src);
188  EmitUint8(0x0F);
189  EmitUint8(0xB6);
190  EmitRegisterOperand(dst.LowBits(), src.LowBits());
191}
192
193
194void X86_64Assembler::movzxb(CpuRegister dst, const Address& src) {
195  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
196  EmitOptionalByteRegNormalizingRex32(dst, src);
197  EmitUint8(0x0F);
198  EmitUint8(0xB6);
199  EmitOperand(dst.LowBits(), src);
200}
201
202
203void X86_64Assembler::movsxb(CpuRegister dst, CpuRegister src) {
204  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
205  EmitOptionalByteRegNormalizingRex32(dst, src);
206  EmitUint8(0x0F);
207  EmitUint8(0xBE);
208  EmitRegisterOperand(dst.LowBits(), src.LowBits());
209}
210
211
212void X86_64Assembler::movsxb(CpuRegister dst, const Address& src) {
213  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
214  EmitOptionalByteRegNormalizingRex32(dst, src);
215  EmitUint8(0x0F);
216  EmitUint8(0xBE);
217  EmitOperand(dst.LowBits(), src);
218}
219
220
221void X86_64Assembler::movb(CpuRegister /*dst*/, const Address& /*src*/) {
222  LOG(FATAL) << "Use movzxb or movsxb instead.";
223}
224
225
226void X86_64Assembler::movb(const Address& dst, CpuRegister src) {
227  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
228  EmitOptionalByteRegNormalizingRex32(src, dst);
229  EmitUint8(0x88);
230  EmitOperand(src.LowBits(), dst);
231}
232
233
234void X86_64Assembler::movb(const Address& dst, const Immediate& imm) {
235  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
236  EmitUint8(0xC6);
237  EmitOperand(Register::RAX, dst);
238  CHECK(imm.is_int8());
239  EmitUint8(imm.value() & 0xFF);
240}
241
242
243void X86_64Assembler::movzxw(CpuRegister dst, CpuRegister src) {
244  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
245  EmitOptionalRex32(dst, src);
246  EmitUint8(0x0F);
247  EmitUint8(0xB7);
248  EmitRegisterOperand(dst.LowBits(), src.LowBits());
249}
250
251
252void X86_64Assembler::movzxw(CpuRegister dst, const Address& src) {
253  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
254  EmitOptionalRex32(dst, src);
255  EmitUint8(0x0F);
256  EmitUint8(0xB7);
257  EmitOperand(dst.LowBits(), src);
258}
259
260
261void X86_64Assembler::movsxw(CpuRegister dst, CpuRegister src) {
262  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
263  EmitOptionalRex32(dst, src);
264  EmitUint8(0x0F);
265  EmitUint8(0xBF);
266  EmitRegisterOperand(dst.LowBits(), src.LowBits());
267}
268
269
270void X86_64Assembler::movsxw(CpuRegister dst, const Address& src) {
271  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
272  EmitOptionalRex32(dst, src);
273  EmitUint8(0x0F);
274  EmitUint8(0xBF);
275  EmitOperand(dst.LowBits(), src);
276}
277
278
279void X86_64Assembler::movw(CpuRegister /*dst*/, const Address& /*src*/) {
280  LOG(FATAL) << "Use movzxw or movsxw instead.";
281}
282
283
284void X86_64Assembler::movw(const Address& dst, CpuRegister src) {
285  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
286  EmitOptionalRex32(src, dst);
287  EmitOperandSizeOverride();
288  EmitUint8(0x89);
289  EmitOperand(src.LowBits(), dst);
290}
291
292
293void X86_64Assembler::leaq(CpuRegister dst, const Address& src) {
294  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
295  EmitRex64(dst, src);
296  EmitUint8(0x8D);
297  EmitOperand(dst.LowBits(), src);
298}
299
300
301void X86_64Assembler::movss(XmmRegister dst, const Address& src) {
302  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
303  EmitUint8(0xF3);
304  EmitOptionalRex32(dst, src);
305  EmitUint8(0x0F);
306  EmitUint8(0x10);
307  EmitOperand(dst.LowBits(), src);
308}
309
310
311void X86_64Assembler::movss(const Address& dst, XmmRegister src) {
312  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
313  EmitUint8(0xF3);
314  EmitOptionalRex32(src, dst);
315  EmitUint8(0x0F);
316  EmitUint8(0x11);
317  EmitOperand(src.LowBits(), dst);
318}
319
320
321void X86_64Assembler::movss(XmmRegister dst, XmmRegister src) {
322  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
323  EmitUint8(0xF3);
324  EmitOptionalRex32(dst, src);
325  EmitUint8(0x0F);
326  EmitUint8(0x11);
327  EmitXmmRegisterOperand(src.LowBits(), dst);
328}
329
330
331void X86_64Assembler::movd(XmmRegister dst, CpuRegister src) {
332  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
333  EmitUint8(0x66);
334  EmitOptionalRex32(dst, src);
335  EmitUint8(0x0F);
336  EmitUint8(0x6E);
337  EmitOperand(dst.LowBits(), Operand(src));
338}
339
340
341void X86_64Assembler::movd(CpuRegister dst, XmmRegister src) {
342  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
343  EmitUint8(0x66);
344  EmitOptionalRex32(src, dst);
345  EmitUint8(0x0F);
346  EmitUint8(0x7E);
347  EmitOperand(src.LowBits(), Operand(dst));
348}
349
350
351void X86_64Assembler::addss(XmmRegister dst, XmmRegister src) {
352  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
353  EmitUint8(0xF3);
354  EmitOptionalRex32(dst, src);
355  EmitUint8(0x0F);
356  EmitUint8(0x58);
357  EmitXmmRegisterOperand(dst.LowBits(), src);
358}
359
360
361void X86_64Assembler::addss(XmmRegister dst, const Address& src) {
362  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
363  EmitUint8(0xF3);
364  EmitOptionalRex32(dst, src);
365  EmitUint8(0x0F);
366  EmitUint8(0x58);
367  EmitOperand(dst.LowBits(), src);
368}
369
370
371void X86_64Assembler::subss(XmmRegister dst, XmmRegister src) {
372  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
373  EmitUint8(0xF3);
374  EmitOptionalRex32(dst, src);
375  EmitUint8(0x0F);
376  EmitUint8(0x5C);
377  EmitXmmRegisterOperand(dst.LowBits(), src);
378}
379
380
381void X86_64Assembler::subss(XmmRegister dst, const Address& src) {
382  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
383  EmitUint8(0xF3);
384  EmitOptionalRex32(dst, src);
385  EmitUint8(0x0F);
386  EmitUint8(0x5C);
387  EmitOperand(dst.LowBits(), src);
388}
389
390
391void X86_64Assembler::mulss(XmmRegister dst, XmmRegister src) {
392  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
393  EmitUint8(0xF3);
394  EmitOptionalRex32(dst, src);
395  EmitUint8(0x0F);
396  EmitUint8(0x59);
397  EmitXmmRegisterOperand(dst.LowBits(), src);
398}
399
400
401void X86_64Assembler::mulss(XmmRegister dst, const Address& src) {
402  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
403  EmitUint8(0xF3);
404  EmitOptionalRex32(dst, src);
405  EmitUint8(0x0F);
406  EmitUint8(0x59);
407  EmitOperand(dst.LowBits(), src);
408}
409
410
411void X86_64Assembler::divss(XmmRegister dst, XmmRegister src) {
412  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
413  EmitUint8(0xF3);
414  EmitOptionalRex32(dst, src);
415  EmitUint8(0x0F);
416  EmitUint8(0x5E);
417  EmitXmmRegisterOperand(dst.LowBits(), src);
418}
419
420
421void X86_64Assembler::divss(XmmRegister dst, const Address& src) {
422  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
423  EmitUint8(0xF3);
424  EmitOptionalRex32(dst, src);
425  EmitUint8(0x0F);
426  EmitUint8(0x5E);
427  EmitOperand(dst.LowBits(), src);
428}
429
430
431void X86_64Assembler::flds(const Address& src) {
432  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
433  EmitUint8(0xD9);
434  EmitOperand(0, src);
435}
436
437
438void X86_64Assembler::fstps(const Address& dst) {
439  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
440  EmitUint8(0xD9);
441  EmitOperand(3, dst);
442}
443
444
445void X86_64Assembler::movsd(XmmRegister dst, const Address& src) {
446  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
447  EmitUint8(0xF2);
448  EmitOptionalRex32(dst, src);
449  EmitUint8(0x0F);
450  EmitUint8(0x10);
451  EmitOperand(dst.LowBits(), src);
452}
453
454
455void X86_64Assembler::movsd(const Address& dst, XmmRegister src) {
456  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
457  EmitUint8(0xF2);
458  EmitOptionalRex32(src, dst);
459  EmitUint8(0x0F);
460  EmitUint8(0x11);
461  EmitOperand(src.LowBits(), dst);
462}
463
464
465void X86_64Assembler::movsd(XmmRegister dst, XmmRegister src) {
466  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
467  EmitUint8(0xF2);
468  EmitOptionalRex32(dst, src);
469  EmitUint8(0x0F);
470  EmitUint8(0x11);
471  EmitXmmRegisterOperand(src.LowBits(), dst);
472}
473
474
475void X86_64Assembler::addsd(XmmRegister dst, XmmRegister src) {
476  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
477  EmitUint8(0xF2);
478  EmitOptionalRex32(dst, src);
479  EmitUint8(0x0F);
480  EmitUint8(0x58);
481  EmitXmmRegisterOperand(dst.LowBits(), src);
482}
483
484
485void X86_64Assembler::addsd(XmmRegister dst, const Address& src) {
486  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
487  EmitUint8(0xF2);
488  EmitOptionalRex32(dst, src);
489  EmitUint8(0x0F);
490  EmitUint8(0x58);
491  EmitOperand(dst.LowBits(), src);
492}
493
494
495void X86_64Assembler::subsd(XmmRegister dst, XmmRegister src) {
496  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
497  EmitUint8(0xF2);
498  EmitOptionalRex32(dst, src);
499  EmitUint8(0x0F);
500  EmitUint8(0x5C);
501  EmitXmmRegisterOperand(dst.LowBits(), src);
502}
503
504
505void X86_64Assembler::subsd(XmmRegister dst, const Address& src) {
506  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
507  EmitUint8(0xF2);
508  EmitOptionalRex32(dst, src);
509  EmitUint8(0x0F);
510  EmitUint8(0x5C);
511  EmitOperand(dst.LowBits(), src);
512}
513
514
515void X86_64Assembler::mulsd(XmmRegister dst, XmmRegister src) {
516  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
517  EmitUint8(0xF2);
518  EmitOptionalRex32(dst, src);
519  EmitUint8(0x0F);
520  EmitUint8(0x59);
521  EmitXmmRegisterOperand(dst.LowBits(), src);
522}
523
524
525void X86_64Assembler::mulsd(XmmRegister dst, const Address& src) {
526  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
527  EmitUint8(0xF2);
528  EmitOptionalRex32(dst, src);
529  EmitUint8(0x0F);
530  EmitUint8(0x59);
531  EmitOperand(dst.LowBits(), src);
532}
533
534
535void X86_64Assembler::divsd(XmmRegister dst, XmmRegister src) {
536  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
537  EmitUint8(0xF2);
538  EmitOptionalRex32(dst, src);
539  EmitUint8(0x0F);
540  EmitUint8(0x5E);
541  EmitXmmRegisterOperand(dst.LowBits(), src);
542}
543
544
545void X86_64Assembler::divsd(XmmRegister dst, const Address& src) {
546  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
547  EmitUint8(0xF2);
548  EmitOptionalRex32(dst, src);
549  EmitUint8(0x0F);
550  EmitUint8(0x5E);
551  EmitOperand(dst.LowBits(), src);
552}
553
554
555void X86_64Assembler::cvtsi2ss(XmmRegister dst, CpuRegister src) {
556  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
557  EmitUint8(0xF3);
558  EmitOptionalRex32(dst, src);
559  EmitUint8(0x0F);
560  EmitUint8(0x2A);
561  EmitOperand(dst.LowBits(), Operand(src));
562}
563
564
565void X86_64Assembler::cvtsi2sd(XmmRegister dst, CpuRegister src) {
566  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
567  EmitUint8(0xF2);
568  EmitOptionalRex32(dst, src);
569  EmitUint8(0x0F);
570  EmitUint8(0x2A);
571  EmitOperand(dst.LowBits(), Operand(src));
572}
573
574
575void X86_64Assembler::cvtss2si(CpuRegister dst, XmmRegister src) {
576  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
577  EmitUint8(0xF3);
578  EmitOptionalRex32(dst, src);
579  EmitUint8(0x0F);
580  EmitUint8(0x2D);
581  EmitXmmRegisterOperand(dst.LowBits(), src);
582}
583
584
585void X86_64Assembler::cvtss2sd(XmmRegister dst, XmmRegister src) {
586  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
587  EmitUint8(0xF3);
588  EmitOptionalRex32(dst, src);
589  EmitUint8(0x0F);
590  EmitUint8(0x5A);
591  EmitXmmRegisterOperand(dst.LowBits(), src);
592}
593
594
595void X86_64Assembler::cvtsd2si(CpuRegister dst, XmmRegister src) {
596  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
597  EmitUint8(0xF2);
598  EmitOptionalRex32(dst, src);
599  EmitUint8(0x0F);
600  EmitUint8(0x2D);
601  EmitXmmRegisterOperand(dst.LowBits(), src);
602}
603
604
605void X86_64Assembler::cvttss2si(CpuRegister dst, XmmRegister src) {
606  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
607  EmitUint8(0xF3);
608  EmitOptionalRex32(dst, src);
609  EmitUint8(0x0F);
610  EmitUint8(0x2C);
611  EmitXmmRegisterOperand(dst.LowBits(), src);
612}
613
614
615void X86_64Assembler::cvttsd2si(CpuRegister dst, XmmRegister src) {
616  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
617  EmitUint8(0xF2);
618  EmitOptionalRex32(dst, src);
619  EmitUint8(0x0F);
620  EmitUint8(0x2C);
621  EmitXmmRegisterOperand(dst.LowBits(), src);
622}
623
624
625void X86_64Assembler::cvtsd2ss(XmmRegister dst, XmmRegister src) {
626  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
627  EmitUint8(0xF2);
628  EmitOptionalRex32(dst, src);
629  EmitUint8(0x0F);
630  EmitUint8(0x5A);
631  EmitXmmRegisterOperand(dst.LowBits(), src);
632}
633
634
635void X86_64Assembler::cvtdq2pd(XmmRegister dst, XmmRegister src) {
636  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
637  EmitUint8(0xF3);
638  EmitOptionalRex32(dst, src);
639  EmitUint8(0x0F);
640  EmitUint8(0xE6);
641  EmitXmmRegisterOperand(dst.LowBits(), src);
642}
643
644
645void X86_64Assembler::comiss(XmmRegister a, XmmRegister b) {
646  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
647  EmitOptionalRex32(a, b);
648  EmitUint8(0x0F);
649  EmitUint8(0x2F);
650  EmitXmmRegisterOperand(a.LowBits(), b);
651}
652
653
654void X86_64Assembler::comisd(XmmRegister a, XmmRegister b) {
655  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
656  EmitUint8(0x66);
657  EmitOptionalRex32(a, b);
658  EmitUint8(0x0F);
659  EmitUint8(0x2F);
660  EmitXmmRegisterOperand(a.LowBits(), b);
661}
662
663
664void X86_64Assembler::sqrtsd(XmmRegister dst, XmmRegister src) {
665  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
666  EmitUint8(0xF2);
667  EmitOptionalRex32(dst, src);
668  EmitUint8(0x0F);
669  EmitUint8(0x51);
670  EmitXmmRegisterOperand(dst.LowBits(), src);
671}
672
673
674void X86_64Assembler::sqrtss(XmmRegister dst, XmmRegister src) {
675  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
676  EmitUint8(0xF3);
677  EmitOptionalRex32(dst, src);
678  EmitUint8(0x0F);
679  EmitUint8(0x51);
680  EmitXmmRegisterOperand(dst.LowBits(), src);
681}
682
683
684void X86_64Assembler::xorpd(XmmRegister dst, const Address& src) {
685  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
686  EmitUint8(0x66);
687  EmitOptionalRex32(dst, src);
688  EmitUint8(0x0F);
689  EmitUint8(0x57);
690  EmitOperand(dst.LowBits(), src);
691}
692
693
694void X86_64Assembler::xorpd(XmmRegister dst, XmmRegister src) {
695  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
696  EmitUint8(0x66);
697  EmitOptionalRex32(dst, src);
698  EmitUint8(0x0F);
699  EmitUint8(0x57);
700  EmitXmmRegisterOperand(dst.LowBits(), src);
701}
702
703
704void X86_64Assembler::xorps(XmmRegister dst, const Address& src) {
705  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
706  EmitOptionalRex32(dst, src);
707  EmitUint8(0x0F);
708  EmitUint8(0x57);
709  EmitOperand(dst.LowBits(), src);
710}
711
712
713void X86_64Assembler::xorps(XmmRegister dst, XmmRegister src) {
714  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
715  EmitOptionalRex32(dst, src);
716  EmitUint8(0x0F);
717  EmitUint8(0x57);
718  EmitXmmRegisterOperand(dst.LowBits(), src);
719}
720
721
722void X86_64Assembler::andpd(XmmRegister dst, const Address& src) {
723  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
724  EmitUint8(0x66);
725  EmitOptionalRex32(dst, src);
726  EmitUint8(0x0F);
727  EmitUint8(0x54);
728  EmitOperand(dst.LowBits(), src);
729}
730
731
732void X86_64Assembler::fldl(const Address& src) {
733  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
734  EmitUint8(0xDD);
735  EmitOperand(0, src);
736}
737
738
739void X86_64Assembler::fstpl(const Address& dst) {
740  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
741  EmitUint8(0xDD);
742  EmitOperand(3, dst);
743}
744
745
746void X86_64Assembler::fnstcw(const Address& dst) {
747  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
748  EmitUint8(0xD9);
749  EmitOperand(7, dst);
750}
751
752
753void X86_64Assembler::fldcw(const Address& src) {
754  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
755  EmitUint8(0xD9);
756  EmitOperand(5, src);
757}
758
759
760void X86_64Assembler::fistpl(const Address& dst) {
761  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
762  EmitUint8(0xDF);
763  EmitOperand(7, dst);
764}
765
766
767void X86_64Assembler::fistps(const Address& dst) {
768  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
769  EmitUint8(0xDB);
770  EmitOperand(3, dst);
771}
772
773
774void X86_64Assembler::fildl(const Address& src) {
775  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
776  EmitUint8(0xDF);
777  EmitOperand(5, src);
778}
779
780
781void X86_64Assembler::fincstp() {
782  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
783  EmitUint8(0xD9);
784  EmitUint8(0xF7);
785}
786
787
788void X86_64Assembler::ffree(const Immediate& index) {
789  CHECK_LT(index.value(), 7);
790  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
791  EmitUint8(0xDD);
792  EmitUint8(0xC0 + index.value());
793}
794
795
796void X86_64Assembler::fsin() {
797  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
798  EmitUint8(0xD9);
799  EmitUint8(0xFE);
800}
801
802
803void X86_64Assembler::fcos() {
804  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
805  EmitUint8(0xD9);
806  EmitUint8(0xFF);
807}
808
809
810void X86_64Assembler::fptan() {
811  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
812  EmitUint8(0xD9);
813  EmitUint8(0xF2);
814}
815
816
817void X86_64Assembler::xchgl(CpuRegister dst, CpuRegister src) {
818  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
819  EmitOptionalRex32(dst, src);
820  EmitUint8(0x87);
821  EmitRegisterOperand(dst.LowBits(), src.LowBits());
822}
823
824
825void X86_64Assembler::xchgq(CpuRegister dst, CpuRegister src) {
826  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
827  EmitRex64(dst, src);
828  EmitUint8(0x87);
829  EmitOperand(dst.LowBits(), Operand(src));
830}
831
832
833void X86_64Assembler::xchgl(CpuRegister reg, const Address& address) {
834  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
835  EmitOptionalRex32(reg, address);
836  EmitUint8(0x87);
837  EmitOperand(reg.LowBits(), address);
838}
839
840
841void X86_64Assembler::cmpl(CpuRegister reg, const Immediate& imm) {
842  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
843  EmitOptionalRex32(reg);
844  EmitComplex(7, Operand(reg), imm);
845}
846
847
848void X86_64Assembler::cmpl(CpuRegister reg0, CpuRegister reg1) {
849  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
850  EmitOptionalRex32(reg0, reg1);
851  EmitUint8(0x3B);
852  EmitOperand(reg0.LowBits(), Operand(reg1));
853}
854
855
856void X86_64Assembler::cmpl(CpuRegister reg, const Address& address) {
857  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
858  EmitOptionalRex32(reg, address);
859  EmitUint8(0x3B);
860  EmitOperand(reg.LowBits(), address);
861}
862
863
864void X86_64Assembler::cmpq(CpuRegister reg0, CpuRegister reg1) {
865  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
866  EmitRex64(reg0, reg1);
867  EmitUint8(0x3B);
868  EmitOperand(reg0.LowBits(), Operand(reg1));
869}
870
871
872void X86_64Assembler::cmpq(CpuRegister reg, const Immediate& imm) {
873  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
874  CHECK(imm.is_int32());  // cmpq only supports 32b immediate.
875  EmitRex64(reg);
876  EmitComplex(7, Operand(reg), imm);
877}
878
879
880void X86_64Assembler::cmpq(CpuRegister reg, const Address& address) {
881  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
882  EmitRex64(reg);
883  EmitUint8(0x3B);
884  EmitOperand(reg.LowBits(), address);
885}
886
887
888void X86_64Assembler::addl(CpuRegister dst, CpuRegister src) {
889  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
890  EmitOptionalRex32(dst, src);
891  EmitUint8(0x03);
892  EmitRegisterOperand(dst.LowBits(), src.LowBits());
893}
894
895
896void X86_64Assembler::addl(CpuRegister reg, const Address& address) {
897  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
898  EmitOptionalRex32(reg, address);
899  EmitUint8(0x03);
900  EmitOperand(reg.LowBits(), address);
901}
902
903
904void X86_64Assembler::cmpl(const Address& address, CpuRegister reg) {
905  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
906  EmitOptionalRex32(reg, address);
907  EmitUint8(0x39);
908  EmitOperand(reg.LowBits(), address);
909}
910
911
912void X86_64Assembler::cmpl(const Address& address, const Immediate& imm) {
913  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
914  EmitOptionalRex32(address);
915  EmitComplex(7, address, imm);
916}
917
918
919void X86_64Assembler::testl(CpuRegister reg1, CpuRegister reg2) {
920  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
921  EmitOptionalRex32(reg1, reg2);
922  EmitUint8(0x85);
923  EmitRegisterOperand(reg1.LowBits(), reg2.LowBits());
924}
925
926
927void X86_64Assembler::testl(CpuRegister reg, const Immediate& immediate) {
928  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
929  // For registers that have a byte variant (RAX, RBX, RCX, and RDX)
930  // we only test the byte CpuRegister to keep the encoding short.
931  if (immediate.is_uint8() && reg.AsRegister() < 4) {
932    // Use zero-extended 8-bit immediate.
933    if (reg.AsRegister() == RAX) {
934      EmitUint8(0xA8);
935    } else {
936      EmitUint8(0xF6);
937      EmitUint8(0xC0 + reg.AsRegister());
938    }
939    EmitUint8(immediate.value() & 0xFF);
940  } else if (reg.AsRegister() == RAX) {
941    // Use short form if the destination is RAX.
942    EmitUint8(0xA9);
943    EmitImmediate(immediate);
944  } else {
945    EmitOptionalRex32(reg);
946    EmitUint8(0xF7);
947    EmitOperand(0, Operand(reg));
948    EmitImmediate(immediate);
949  }
950}
951
952
953void X86_64Assembler::andl(CpuRegister dst, CpuRegister src) {
954  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
955  EmitOptionalRex32(dst, src);
956  EmitUint8(0x23);
957  EmitOperand(dst.LowBits(), Operand(src));
958}
959
960
961void X86_64Assembler::andl(CpuRegister dst, const Immediate& imm) {
962  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
963  EmitOptionalRex32(dst);
964  EmitComplex(4, Operand(dst), imm);
965}
966
967
968void X86_64Assembler::andq(CpuRegister reg, const Immediate& imm) {
969  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
970  CHECK(imm.is_int32());  // andq only supports 32b immediate.
971  EmitRex64(reg);
972  EmitComplex(4, Operand(reg), imm);
973}
974
975
976void X86_64Assembler::orl(CpuRegister dst, CpuRegister src) {
977  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
978  EmitOptionalRex32(dst, src);
979  EmitUint8(0x0B);
980  EmitOperand(dst.LowBits(), Operand(src));
981}
982
983
984void X86_64Assembler::orl(CpuRegister dst, const Immediate& imm) {
985  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
986  EmitOptionalRex32(dst);
987  EmitComplex(1, Operand(dst), imm);
988}
989
990
991void X86_64Assembler::xorl(CpuRegister dst, CpuRegister src) {
992  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
993  EmitOptionalRex32(dst, src);
994  EmitUint8(0x33);
995  EmitOperand(dst.LowBits(), Operand(src));
996}
997
998
999void X86_64Assembler::xorq(CpuRegister dst, CpuRegister src) {
1000  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1001  EmitRex64(dst, src);
1002  EmitUint8(0x33);
1003  EmitOperand(dst.LowBits(), Operand(src));
1004}
1005
1006
1007void X86_64Assembler::xorq(CpuRegister dst, const Immediate& imm) {
1008  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1009  CHECK(imm.is_int32());  // xorq only supports 32b immediate.
1010  EmitRex64(dst);
1011  EmitComplex(6, Operand(dst), imm);
1012}
1013
1014#if 0
1015void X86_64Assembler::rex(bool force, bool w, Register* r, Register* x, Register* b) {
1016  // REX.WRXB
1017  // W - 64-bit operand
1018  // R - MODRM.reg
1019  // X - SIB.index
1020  // B - MODRM.rm/SIB.base
1021  uint8_t rex = force ? 0x40 : 0;
1022  if (w) {
1023    rex |= 0x48;  // REX.W000
1024  }
1025  if (r != nullptr && *r >= Register::R8 && *r < Register::kNumberOfCpuRegisters) {
1026    rex |= 0x44;  // REX.0R00
1027    *r = static_cast<Register>(*r - 8);
1028  }
1029  if (x != nullptr && *x >= Register::R8 && *x < Register::kNumberOfCpuRegisters) {
1030    rex |= 0x42;  // REX.00X0
1031    *x = static_cast<Register>(*x - 8);
1032  }
1033  if (b != nullptr && *b >= Register::R8 && *b < Register::kNumberOfCpuRegisters) {
1034    rex |= 0x41;  // REX.000B
1035    *b = static_cast<Register>(*b - 8);
1036  }
1037  if (rex != 0) {
1038    EmitUint8(rex);
1039  }
1040}
1041
1042void X86_64Assembler::rex_reg_mem(bool force, bool w, Register* dst, const Address& mem) {
1043  // REX.WRXB
1044  // W - 64-bit operand
1045  // R - MODRM.reg
1046  // X - SIB.index
1047  // B - MODRM.rm/SIB.base
1048  uint8_t rex = mem->rex();
1049  if (force) {
1050    rex |= 0x40;  // REX.0000
1051  }
1052  if (w) {
1053    rex |= 0x48;  // REX.W000
1054  }
1055  if (dst != nullptr && *dst >= Register::R8 && *dst < Register::kNumberOfCpuRegisters) {
1056    rex |= 0x44;  // REX.0R00
1057    *dst = static_cast<Register>(*dst - 8);
1058  }
1059  if (rex != 0) {
1060    EmitUint8(rex);
1061  }
1062}
1063
1064void rex_mem_reg(bool force, bool w, Address* mem, Register* src);
1065#endif
1066
1067void X86_64Assembler::addl(CpuRegister reg, const Immediate& imm) {
1068  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1069  EmitOptionalRex32(reg);
1070  EmitComplex(0, Operand(reg), imm);
1071}
1072
1073
1074void X86_64Assembler::addq(CpuRegister reg, const Immediate& imm) {
1075  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1076  CHECK(imm.is_int32());  // addq only supports 32b immediate.
1077  EmitRex64(reg);
1078  EmitComplex(0, Operand(reg), imm);
1079}
1080
1081
1082void X86_64Assembler::addq(CpuRegister dst, const Address& address) {
1083  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1084  EmitRex64(dst);
1085  EmitUint8(0x03);
1086  EmitOperand(dst.LowBits(), address);
1087}
1088
1089
1090void X86_64Assembler::addq(CpuRegister dst, CpuRegister src) {
1091  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1092  // 0x01 is addq r/m64 <- r/m64 + r64, with op1 in r/m and op2 in reg: so reverse EmitRex64
1093  EmitRex64(src, dst);
1094  EmitUint8(0x01);
1095  EmitRegisterOperand(src.LowBits(), dst.LowBits());
1096}
1097
1098
1099void X86_64Assembler::addl(const Address& address, CpuRegister reg) {
1100  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1101  EmitOptionalRex32(reg, address);
1102  EmitUint8(0x01);
1103  EmitOperand(reg.LowBits(), address);
1104}
1105
1106
1107void X86_64Assembler::addl(const Address& address, const Immediate& imm) {
1108  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1109  EmitOptionalRex32(address);
1110  EmitComplex(0, address, imm);
1111}
1112
1113
1114void X86_64Assembler::subl(CpuRegister dst, CpuRegister src) {
1115  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1116  EmitOptionalRex32(dst, src);
1117  EmitUint8(0x2B);
1118  EmitOperand(dst.LowBits(), Operand(src));
1119}
1120
1121
1122void X86_64Assembler::subl(CpuRegister reg, const Immediate& imm) {
1123  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1124  EmitOptionalRex32(reg);
1125  EmitComplex(5, Operand(reg), imm);
1126}
1127
1128
1129void X86_64Assembler::subq(CpuRegister reg, const Immediate& imm) {
1130  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1131  CHECK(imm.is_int32());  // subq only supports 32b immediate.
1132  EmitRex64(reg);
1133  EmitComplex(5, Operand(reg), imm);
1134}
1135
1136
1137void X86_64Assembler::subq(CpuRegister dst, CpuRegister src) {
1138  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1139  EmitRex64(dst, src);
1140  EmitUint8(0x2B);
1141  EmitRegisterOperand(dst.LowBits(), src.LowBits());
1142}
1143
1144
1145void X86_64Assembler::subq(CpuRegister reg, const Address& address) {
1146  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1147  EmitRex64(reg);
1148  EmitUint8(0x2B);
1149  EmitOperand(reg.LowBits() & 7, address);
1150}
1151
1152
1153void X86_64Assembler::subl(CpuRegister reg, const Address& address) {
1154  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1155  EmitOptionalRex32(reg, address);
1156  EmitUint8(0x2B);
1157  EmitOperand(reg.LowBits(), address);
1158}
1159
1160
1161void X86_64Assembler::cdq() {
1162  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1163  EmitUint8(0x99);
1164}
1165
1166
1167void X86_64Assembler::idivl(CpuRegister reg) {
1168  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1169  EmitOptionalRex32(reg);
1170  EmitUint8(0xF7);
1171  EmitUint8(0xF8 | reg.LowBits());
1172}
1173
1174
1175void X86_64Assembler::imull(CpuRegister dst, CpuRegister src) {
1176  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1177  EmitOptionalRex32(dst, src);
1178  EmitUint8(0x0F);
1179  EmitUint8(0xAF);
1180  EmitOperand(dst.LowBits(), Operand(src));
1181}
1182
1183
1184void X86_64Assembler::imull(CpuRegister reg, const Immediate& imm) {
1185  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1186  EmitOptionalRex32(reg);
1187  EmitUint8(0x69);
1188  EmitOperand(reg.LowBits(), Operand(reg));
1189  EmitImmediate(imm);
1190}
1191
1192
1193void X86_64Assembler::imull(CpuRegister reg, const Address& address) {
1194  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1195  EmitOptionalRex32(reg, address);
1196  EmitUint8(0x0F);
1197  EmitUint8(0xAF);
1198  EmitOperand(reg.LowBits(), address);
1199}
1200
1201
1202void X86_64Assembler::imull(CpuRegister reg) {
1203  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1204  EmitOptionalRex32(reg);
1205  EmitUint8(0xF7);
1206  EmitOperand(5, Operand(reg));
1207}
1208
1209
1210void X86_64Assembler::imull(const Address& address) {
1211  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1212  EmitOptionalRex32(address);
1213  EmitUint8(0xF7);
1214  EmitOperand(5, address);
1215}
1216
1217
1218void X86_64Assembler::mull(CpuRegister reg) {
1219  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1220  EmitOptionalRex32(reg);
1221  EmitUint8(0xF7);
1222  EmitOperand(4, Operand(reg));
1223}
1224
1225
1226void X86_64Assembler::mull(const Address& address) {
1227  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1228  EmitOptionalRex32(address);
1229  EmitUint8(0xF7);
1230  EmitOperand(4, address);
1231}
1232
1233
1234
1235void X86_64Assembler::shll(CpuRegister reg, const Immediate& imm) {
1236  EmitGenericShift(false, 4, reg, imm);
1237}
1238
1239
1240void X86_64Assembler::shll(CpuRegister operand, CpuRegister shifter) {
1241  EmitGenericShift(4, operand, shifter);
1242}
1243
1244
1245void X86_64Assembler::shrl(CpuRegister reg, const Immediate& imm) {
1246  EmitGenericShift(false, 5, reg, imm);
1247}
1248
1249
1250void X86_64Assembler::shrq(CpuRegister reg, const Immediate& imm) {
1251  EmitGenericShift(true, 5, reg, imm);
1252}
1253
1254
1255void X86_64Assembler::shrl(CpuRegister operand, CpuRegister shifter) {
1256  EmitGenericShift(5, operand, shifter);
1257}
1258
1259
1260void X86_64Assembler::sarl(CpuRegister reg, const Immediate& imm) {
1261  EmitGenericShift(false, 7, reg, imm);
1262}
1263
1264
1265void X86_64Assembler::sarl(CpuRegister operand, CpuRegister shifter) {
1266  EmitGenericShift(7, operand, shifter);
1267}
1268
1269
1270void X86_64Assembler::negl(CpuRegister reg) {
1271  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1272  EmitOptionalRex32(reg);
1273  EmitUint8(0xF7);
1274  EmitOperand(3, Operand(reg));
1275}
1276
1277
1278void X86_64Assembler::notl(CpuRegister reg) {
1279  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1280  EmitOptionalRex32(reg);
1281  EmitUint8(0xF7);
1282  EmitUint8(0xD0 | reg.LowBits());
1283}
1284
1285
1286void X86_64Assembler::enter(const Immediate& imm) {
1287  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1288  EmitUint8(0xC8);
1289  CHECK(imm.is_uint16());
1290  EmitUint8(imm.value() & 0xFF);
1291  EmitUint8((imm.value() >> 8) & 0xFF);
1292  EmitUint8(0x00);
1293}
1294
1295
1296void X86_64Assembler::leave() {
1297  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1298  EmitUint8(0xC9);
1299}
1300
1301
1302void X86_64Assembler::ret() {
1303  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1304  EmitUint8(0xC3);
1305}
1306
1307
1308void X86_64Assembler::ret(const Immediate& imm) {
1309  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1310  EmitUint8(0xC2);
1311  CHECK(imm.is_uint16());
1312  EmitUint8(imm.value() & 0xFF);
1313  EmitUint8((imm.value() >> 8) & 0xFF);
1314}
1315
1316
1317
1318void X86_64Assembler::nop() {
1319  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1320  EmitUint8(0x90);
1321}
1322
1323
1324void X86_64Assembler::int3() {
1325  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1326  EmitUint8(0xCC);
1327}
1328
1329
1330void X86_64Assembler::hlt() {
1331  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1332  EmitUint8(0xF4);
1333}
1334
1335
1336void X86_64Assembler::j(Condition condition, Label* label) {
1337  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1338  if (label->IsBound()) {
1339    static const int kShortSize = 2;
1340    static const int kLongSize = 6;
1341    int offset = label->Position() - buffer_.Size();
1342    CHECK_LE(offset, 0);
1343    if (IsInt(8, offset - kShortSize)) {
1344      EmitUint8(0x70 + condition);
1345      EmitUint8((offset - kShortSize) & 0xFF);
1346    } else {
1347      EmitUint8(0x0F);
1348      EmitUint8(0x80 + condition);
1349      EmitInt32(offset - kLongSize);
1350    }
1351  } else {
1352    EmitUint8(0x0F);
1353    EmitUint8(0x80 + condition);
1354    EmitLabelLink(label);
1355  }
1356}
1357
1358
1359void X86_64Assembler::jmp(CpuRegister reg) {
1360  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1361  EmitOptionalRex32(reg);
1362  EmitUint8(0xFF);
1363  EmitRegisterOperand(4, reg.LowBits());
1364}
1365
1366void X86_64Assembler::jmp(const Address& address) {
1367  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1368  EmitOptionalRex32(address);
1369  EmitUint8(0xFF);
1370  EmitOperand(4, address);
1371}
1372
1373void X86_64Assembler::jmp(Label* label) {
1374  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1375  if (label->IsBound()) {
1376    static const int kShortSize = 2;
1377    static const int kLongSize = 5;
1378    int offset = label->Position() - buffer_.Size();
1379    CHECK_LE(offset, 0);
1380    if (IsInt(8, offset - kShortSize)) {
1381      EmitUint8(0xEB);
1382      EmitUint8((offset - kShortSize) & 0xFF);
1383    } else {
1384      EmitUint8(0xE9);
1385      EmitInt32(offset - kLongSize);
1386    }
1387  } else {
1388    EmitUint8(0xE9);
1389    EmitLabelLink(label);
1390  }
1391}
1392
1393
1394X86_64Assembler* X86_64Assembler::lock() {
1395  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1396  EmitUint8(0xF0);
1397  return this;
1398}
1399
1400
1401void X86_64Assembler::cmpxchgl(const Address& address, CpuRegister reg) {
1402  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1403  EmitUint8(0x0F);
1404  EmitUint8(0xB1);
1405  EmitOperand(reg.LowBits(), address);
1406}
1407
1408void X86_64Assembler::mfence() {
1409  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1410  EmitUint8(0x0F);
1411  EmitUint8(0xAE);
1412  EmitUint8(0xF0);
1413}
1414
1415
1416X86_64Assembler* X86_64Assembler::gs() {
1417  // TODO: gs is a prefix and not an instruction
1418  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1419  EmitUint8(0x65);
1420  return this;
1421}
1422
1423
1424void X86_64Assembler::AddImmediate(CpuRegister reg, const Immediate& imm) {
1425  int value = imm.value();
1426  if (value != 0) {
1427    if (value > 0) {
1428      addl(reg, imm);
1429    } else {
1430      subl(reg, Immediate(value));
1431    }
1432  }
1433}
1434
1435
1436void X86_64Assembler::setcc(Condition condition, CpuRegister dst) {
1437  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1438  // RSP, RBP, RDI, RSI need rex prefix (else the pattern encodes ah/bh/ch/dh).
1439  if (dst.NeedsRex() || dst.AsRegister() > 3) {
1440    EmitOptionalRex(true, false, false, false, dst.NeedsRex());
1441  }
1442  EmitUint8(0x0F);
1443  EmitUint8(0x90 + condition);
1444  EmitUint8(0xC0 + dst.LowBits());
1445}
1446
1447
1448void X86_64Assembler::LoadDoubleConstant(XmmRegister dst, double value) {
1449  // TODO: Need to have a code constants table.
1450  int64_t constant = bit_cast<int64_t, double>(value);
1451  pushq(Immediate(High32Bits(constant)));
1452  pushq(Immediate(Low32Bits(constant)));
1453  movsd(dst, Address(CpuRegister(RSP), 0));
1454  addq(CpuRegister(RSP), Immediate(2 * kWordSize));
1455}
1456
1457
1458void X86_64Assembler::FloatNegate(XmmRegister f) {
1459  static const struct {
1460    uint32_t a;
1461    uint32_t b;
1462    uint32_t c;
1463    uint32_t d;
1464  } float_negate_constant __attribute__((aligned(16))) =
1465      { 0x80000000, 0x00000000, 0x80000000, 0x00000000 };
1466  xorps(f, Address::Absolute(reinterpret_cast<uword>(&float_negate_constant)));
1467}
1468
1469
1470void X86_64Assembler::DoubleNegate(XmmRegister d) {
1471  static const struct {
1472    uint64_t a;
1473    uint64_t b;
1474  } double_negate_constant __attribute__((aligned(16))) =
1475      {0x8000000000000000LL, 0x8000000000000000LL};
1476  xorpd(d, Address::Absolute(reinterpret_cast<uword>(&double_negate_constant)));
1477}
1478
1479
1480void X86_64Assembler::DoubleAbs(XmmRegister reg) {
1481  static const struct {
1482    uint64_t a;
1483    uint64_t b;
1484  } double_abs_constant __attribute__((aligned(16))) =
1485      {0x7FFFFFFFFFFFFFFFLL, 0x7FFFFFFFFFFFFFFFLL};
1486  andpd(reg, Address::Absolute(reinterpret_cast<uword>(&double_abs_constant)));
1487}
1488
1489
1490void X86_64Assembler::Align(int alignment, int offset) {
1491  CHECK(IsPowerOfTwo(alignment));
1492  // Emit nop instruction until the real position is aligned.
1493  while (((offset + buffer_.GetPosition()) & (alignment-1)) != 0) {
1494    nop();
1495  }
1496}
1497
1498
1499void X86_64Assembler::Bind(Label* label) {
1500  int bound = buffer_.Size();
1501  CHECK(!label->IsBound());  // Labels can only be bound once.
1502  while (label->IsLinked()) {
1503    int position = label->LinkPosition();
1504    int next = buffer_.Load<int32_t>(position);
1505    buffer_.Store<int32_t>(position, bound - (position + 4));
1506    label->position_ = next;
1507  }
1508  label->BindTo(bound);
1509}
1510
1511
1512void X86_64Assembler::EmitOperand(uint8_t reg_or_opcode, const Operand& operand) {
1513  CHECK_GE(reg_or_opcode, 0);
1514  CHECK_LT(reg_or_opcode, 8);
1515  const int length = operand.length_;
1516  CHECK_GT(length, 0);
1517  // Emit the ModRM byte updated with the given reg value.
1518  CHECK_EQ(operand.encoding_[0] & 0x38, 0);
1519  EmitUint8(operand.encoding_[0] + (reg_or_opcode << 3));
1520  // Emit the rest of the encoded operand.
1521  for (int i = 1; i < length; i++) {
1522    EmitUint8(operand.encoding_[i]);
1523  }
1524}
1525
1526
1527void X86_64Assembler::EmitImmediate(const Immediate& imm) {
1528  if (imm.is_int32()) {
1529    EmitInt32(static_cast<int32_t>(imm.value()));
1530  } else {
1531    EmitInt64(imm.value());
1532  }
1533}
1534
1535
1536void X86_64Assembler::EmitComplex(uint8_t reg_or_opcode,
1537                                  const Operand& operand,
1538                                  const Immediate& immediate) {
1539  CHECK_GE(reg_or_opcode, 0);
1540  CHECK_LT(reg_or_opcode, 8);
1541  if (immediate.is_int8()) {
1542    // Use sign-extended 8-bit immediate.
1543    EmitUint8(0x83);
1544    EmitOperand(reg_or_opcode, operand);
1545    EmitUint8(immediate.value() & 0xFF);
1546  } else if (operand.IsRegister(CpuRegister(RAX))) {
1547    // Use short form if the destination is eax.
1548    EmitUint8(0x05 + (reg_or_opcode << 3));
1549    EmitImmediate(immediate);
1550  } else {
1551    EmitUint8(0x81);
1552    EmitOperand(reg_or_opcode, operand);
1553    EmitImmediate(immediate);
1554  }
1555}
1556
1557
1558void X86_64Assembler::EmitLabel(Label* label, int instruction_size) {
1559  if (label->IsBound()) {
1560    int offset = label->Position() - buffer_.Size();
1561    CHECK_LE(offset, 0);
1562    EmitInt32(offset - instruction_size);
1563  } else {
1564    EmitLabelLink(label);
1565  }
1566}
1567
1568
1569void X86_64Assembler::EmitLabelLink(Label* label) {
1570  CHECK(!label->IsBound());
1571  int position = buffer_.Size();
1572  EmitInt32(label->position_);
1573  label->LinkTo(position);
1574}
1575
1576
1577void X86_64Assembler::EmitGenericShift(bool wide,
1578                                       int reg_or_opcode,
1579                                       CpuRegister reg,
1580                                       const Immediate& imm) {
1581  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1582  CHECK(imm.is_int8());
1583  if (wide) {
1584    EmitRex64(reg);
1585  }
1586  if (imm.value() == 1) {
1587    EmitUint8(0xD1);
1588    EmitOperand(reg_or_opcode, Operand(reg));
1589  } else {
1590    EmitUint8(0xC1);
1591    EmitOperand(reg_or_opcode, Operand(reg));
1592    EmitUint8(imm.value() & 0xFF);
1593  }
1594}
1595
1596
1597void X86_64Assembler::EmitGenericShift(int reg_or_opcode,
1598                                       CpuRegister operand,
1599                                       CpuRegister shifter) {
1600  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1601  CHECK_EQ(shifter.AsRegister(), RCX);
1602  EmitUint8(0xD3);
1603  EmitOperand(reg_or_opcode, Operand(operand));
1604}
1605
1606void X86_64Assembler::EmitOptionalRex(bool force, bool w, bool r, bool x, bool b) {
1607  // REX.WRXB
1608  // W - 64-bit operand
1609  // R - MODRM.reg
1610  // X - SIB.index
1611  // B - MODRM.rm/SIB.base
1612  uint8_t rex = force ? 0x40 : 0;
1613  if (w) {
1614    rex |= 0x48;  // REX.W000
1615  }
1616  if (r) {
1617    rex |= 0x44;  // REX.0R00
1618  }
1619  if (x) {
1620    rex |= 0x42;  // REX.00X0
1621  }
1622  if (b) {
1623    rex |= 0x41;  // REX.000B
1624  }
1625  if (rex != 0) {
1626    EmitUint8(rex);
1627  }
1628}
1629
1630void X86_64Assembler::EmitOptionalRex32(CpuRegister reg) {
1631  EmitOptionalRex(false, false, false, false, reg.NeedsRex());
1632}
1633
1634void X86_64Assembler::EmitOptionalRex32(CpuRegister dst, CpuRegister src) {
1635  EmitOptionalRex(false, false, dst.NeedsRex(), false, src.NeedsRex());
1636}
1637
1638void X86_64Assembler::EmitOptionalRex32(XmmRegister dst, XmmRegister src) {
1639  EmitOptionalRex(false, false, dst.NeedsRex(), false, src.NeedsRex());
1640}
1641
1642void X86_64Assembler::EmitOptionalRex32(CpuRegister dst, XmmRegister src) {
1643  EmitOptionalRex(false, false, dst.NeedsRex(), false, src.NeedsRex());
1644}
1645
1646void X86_64Assembler::EmitOptionalRex32(XmmRegister dst, CpuRegister src) {
1647  EmitOptionalRex(false, false, dst.NeedsRex(), false, src.NeedsRex());
1648}
1649
1650void X86_64Assembler::EmitOptionalRex32(const Operand& operand) {
1651  uint8_t rex = operand.rex();
1652  if (rex != 0) {
1653    EmitUint8(rex);
1654  }
1655}
1656
1657void X86_64Assembler::EmitOptionalRex32(CpuRegister dst, const Operand& operand) {
1658  uint8_t rex = operand.rex();
1659  if (dst.NeedsRex()) {
1660    rex |= 0x44;  // REX.0R00
1661  }
1662  if (rex != 0) {
1663    EmitUint8(rex);
1664  }
1665}
1666
1667void X86_64Assembler::EmitOptionalRex32(XmmRegister dst, const Operand& operand) {
1668  uint8_t rex = operand.rex();
1669  if (dst.NeedsRex()) {
1670    rex |= 0x44;  // REX.0R00
1671  }
1672  if (rex != 0) {
1673    EmitUint8(rex);
1674  }
1675}
1676
1677void X86_64Assembler::EmitRex64(CpuRegister reg) {
1678  EmitOptionalRex(false, true, false, false, reg.NeedsRex());
1679}
1680
1681void X86_64Assembler::EmitRex64(CpuRegister dst, CpuRegister src) {
1682  EmitOptionalRex(false, true, dst.NeedsRex(), false, src.NeedsRex());
1683}
1684
1685void X86_64Assembler::EmitRex64(CpuRegister dst, const Operand& operand) {
1686  uint8_t rex = 0x48 | operand.rex();  // REX.W000
1687  if (dst.NeedsRex()) {
1688    rex |= 0x44;  // REX.0R00
1689  }
1690  if (rex != 0) {
1691    EmitUint8(rex);
1692  }
1693}
1694
1695void X86_64Assembler::EmitOptionalByteRegNormalizingRex32(CpuRegister dst, CpuRegister src) {
1696  EmitOptionalRex(true, false, dst.NeedsRex(), false, src.NeedsRex());
1697}
1698
1699void X86_64Assembler::EmitOptionalByteRegNormalizingRex32(CpuRegister dst, const Operand& operand) {
1700  uint8_t rex = 0x40 | operand.rex();  // REX.0000
1701  if (dst.NeedsRex()) {
1702    rex |= 0x44;  // REX.0R00
1703  }
1704  if (rex != 0) {
1705    EmitUint8(rex);
1706  }
1707}
1708
1709constexpr size_t kFramePointerSize = 8;
1710
1711void X86_64Assembler::BuildFrame(size_t frame_size, ManagedRegister method_reg,
1712                                 const std::vector<ManagedRegister>& spill_regs,
1713                                 const ManagedRegisterEntrySpills& entry_spills) {
1714  CHECK_ALIGNED(frame_size, kStackAlignment);
1715  int gpr_count = 0;
1716  for (int i = spill_regs.size() - 1; i >= 0; --i) {
1717    x86_64::X86_64ManagedRegister spill = spill_regs.at(i).AsX86_64();
1718    if (spill.IsCpuRegister()) {
1719      pushq(spill.AsCpuRegister());
1720      gpr_count++;
1721    }
1722  }
1723  // return address then method on stack
1724  int64_t rest_of_frame = static_cast<int64_t>(frame_size)
1725                          - (gpr_count * kFramePointerSize)
1726                          - kFramePointerSize /*return address*/;
1727  subq(CpuRegister(RSP), Immediate(rest_of_frame));
1728  // spill xmms
1729  int64_t offset = rest_of_frame;
1730  for (int i = spill_regs.size() - 1; i >= 0; --i) {
1731    x86_64::X86_64ManagedRegister spill = spill_regs.at(i).AsX86_64();
1732    if (spill.IsXmmRegister()) {
1733      offset -= sizeof(double);
1734      movsd(Address(CpuRegister(RSP), offset), spill.AsXmmRegister());
1735    }
1736  }
1737
1738  DCHECK_EQ(4U, sizeof(StackReference<mirror::ArtMethod>));
1739
1740  movl(Address(CpuRegister(RSP), 0), method_reg.AsX86_64().AsCpuRegister());
1741
1742  for (size_t i = 0; i < entry_spills.size(); ++i) {
1743    ManagedRegisterSpill spill = entry_spills.at(i);
1744    if (spill.AsX86_64().IsCpuRegister()) {
1745      if (spill.getSize() == 8) {
1746        movq(Address(CpuRegister(RSP), frame_size + spill.getSpillOffset()),
1747             spill.AsX86_64().AsCpuRegister());
1748      } else {
1749        CHECK_EQ(spill.getSize(), 4);
1750        movl(Address(CpuRegister(RSP), frame_size + spill.getSpillOffset()), spill.AsX86_64().AsCpuRegister());
1751      }
1752    } else {
1753      if (spill.getSize() == 8) {
1754        movsd(Address(CpuRegister(RSP), frame_size + spill.getSpillOffset()), spill.AsX86_64().AsXmmRegister());
1755      } else {
1756        CHECK_EQ(spill.getSize(), 4);
1757        movss(Address(CpuRegister(RSP), frame_size + spill.getSpillOffset()), spill.AsX86_64().AsXmmRegister());
1758      }
1759    }
1760  }
1761}
1762
1763void X86_64Assembler::RemoveFrame(size_t frame_size,
1764                            const std::vector<ManagedRegister>& spill_regs) {
1765  CHECK_ALIGNED(frame_size, kStackAlignment);
1766  int gpr_count = 0;
1767  // unspill xmms
1768  int64_t offset = static_cast<int64_t>(frame_size) - (spill_regs.size() * kFramePointerSize) - 2 * kFramePointerSize;
1769  for (size_t i = 0; i < spill_regs.size(); ++i) {
1770    x86_64::X86_64ManagedRegister spill = spill_regs.at(i).AsX86_64();
1771    if (spill.IsXmmRegister()) {
1772      offset += sizeof(double);
1773      movsd(spill.AsXmmRegister(), Address(CpuRegister(RSP), offset));
1774    } else {
1775      gpr_count++;
1776    }
1777  }
1778  addq(CpuRegister(RSP), Immediate(static_cast<int64_t>(frame_size) - (gpr_count * kFramePointerSize) - kFramePointerSize));
1779  for (size_t i = 0; i < spill_regs.size(); ++i) {
1780    x86_64::X86_64ManagedRegister spill = spill_regs.at(i).AsX86_64();
1781    if (spill.IsCpuRegister()) {
1782      popq(spill.AsCpuRegister());
1783    }
1784  }
1785  ret();
1786}
1787
1788void X86_64Assembler::IncreaseFrameSize(size_t adjust) {
1789  CHECK_ALIGNED(adjust, kStackAlignment);
1790  addq(CpuRegister(RSP), Immediate(-static_cast<int64_t>(adjust)));
1791}
1792
1793void X86_64Assembler::DecreaseFrameSize(size_t adjust) {
1794  CHECK_ALIGNED(adjust, kStackAlignment);
1795  addq(CpuRegister(RSP), Immediate(adjust));
1796}
1797
1798void X86_64Assembler::Store(FrameOffset offs, ManagedRegister msrc, size_t size) {
1799  X86_64ManagedRegister src = msrc.AsX86_64();
1800  if (src.IsNoRegister()) {
1801    CHECK_EQ(0u, size);
1802  } else if (src.IsCpuRegister()) {
1803    if (size == 4) {
1804      CHECK_EQ(4u, size);
1805      movl(Address(CpuRegister(RSP), offs), src.AsCpuRegister());
1806    } else {
1807      CHECK_EQ(8u, size);
1808      movq(Address(CpuRegister(RSP), offs), src.AsCpuRegister());
1809    }
1810  } else if (src.IsRegisterPair()) {
1811    CHECK_EQ(0u, size);
1812    movq(Address(CpuRegister(RSP), offs), src.AsRegisterPairLow());
1813    movq(Address(CpuRegister(RSP), FrameOffset(offs.Int32Value()+4)),
1814         src.AsRegisterPairHigh());
1815  } else if (src.IsX87Register()) {
1816    if (size == 4) {
1817      fstps(Address(CpuRegister(RSP), offs));
1818    } else {
1819      fstpl(Address(CpuRegister(RSP), offs));
1820    }
1821  } else {
1822    CHECK(src.IsXmmRegister());
1823    if (size == 4) {
1824      movss(Address(CpuRegister(RSP), offs), src.AsXmmRegister());
1825    } else {
1826      movsd(Address(CpuRegister(RSP), offs), src.AsXmmRegister());
1827    }
1828  }
1829}
1830
1831void X86_64Assembler::StoreRef(FrameOffset dest, ManagedRegister msrc) {
1832  X86_64ManagedRegister src = msrc.AsX86_64();
1833  CHECK(src.IsCpuRegister());
1834  movl(Address(CpuRegister(RSP), dest), src.AsCpuRegister());
1835}
1836
1837void X86_64Assembler::StoreRawPtr(FrameOffset dest, ManagedRegister msrc) {
1838  X86_64ManagedRegister src = msrc.AsX86_64();
1839  CHECK(src.IsCpuRegister());
1840  movq(Address(CpuRegister(RSP), dest), src.AsCpuRegister());
1841}
1842
1843void X86_64Assembler::StoreImmediateToFrame(FrameOffset dest, uint32_t imm,
1844                                            ManagedRegister) {
1845  movl(Address(CpuRegister(RSP), dest), Immediate(imm));  // TODO(64) movq?
1846}
1847
1848void X86_64Assembler::StoreImmediateToThread64(ThreadOffset<8> dest, uint32_t imm,
1849                                               ManagedRegister) {
1850  gs()->movl(Address::Absolute(dest, true), Immediate(imm));  // TODO(64) movq?
1851}
1852
1853void X86_64Assembler::StoreStackOffsetToThread64(ThreadOffset<8> thr_offs,
1854                                                 FrameOffset fr_offs,
1855                                                 ManagedRegister mscratch) {
1856  X86_64ManagedRegister scratch = mscratch.AsX86_64();
1857  CHECK(scratch.IsCpuRegister());
1858  leaq(scratch.AsCpuRegister(), Address(CpuRegister(RSP), fr_offs));
1859  gs()->movq(Address::Absolute(thr_offs, true), scratch.AsCpuRegister());
1860}
1861
1862void X86_64Assembler::StoreStackPointerToThread64(ThreadOffset<8> thr_offs) {
1863  gs()->movq(Address::Absolute(thr_offs, true), CpuRegister(RSP));
1864}
1865
1866void X86_64Assembler::StoreSpanning(FrameOffset /*dst*/, ManagedRegister /*src*/,
1867                                 FrameOffset /*in_off*/, ManagedRegister /*scratch*/) {
1868  UNIMPLEMENTED(FATAL);  // this case only currently exists for ARM
1869}
1870
1871void X86_64Assembler::Load(ManagedRegister mdest, FrameOffset src, size_t size) {
1872  X86_64ManagedRegister dest = mdest.AsX86_64();
1873  if (dest.IsNoRegister()) {
1874    CHECK_EQ(0u, size);
1875  } else if (dest.IsCpuRegister()) {
1876    if (size == 4) {
1877      CHECK_EQ(4u, size);
1878      movl(dest.AsCpuRegister(), Address(CpuRegister(RSP), src));
1879    } else {
1880      CHECK_EQ(8u, size);
1881      movq(dest.AsCpuRegister(), Address(CpuRegister(RSP), src));
1882    }
1883  } else if (dest.IsRegisterPair()) {
1884    CHECK_EQ(0u, size);
1885    movq(dest.AsRegisterPairLow(), Address(CpuRegister(RSP), src));
1886    movq(dest.AsRegisterPairHigh(), Address(CpuRegister(RSP), FrameOffset(src.Int32Value()+4)));
1887  } else if (dest.IsX87Register()) {
1888    if (size == 4) {
1889      flds(Address(CpuRegister(RSP), src));
1890    } else {
1891      fldl(Address(CpuRegister(RSP), src));
1892    }
1893  } else {
1894    CHECK(dest.IsXmmRegister());
1895    if (size == 4) {
1896      movss(dest.AsXmmRegister(), Address(CpuRegister(RSP), src));
1897    } else {
1898      movsd(dest.AsXmmRegister(), Address(CpuRegister(RSP), src));
1899    }
1900  }
1901}
1902
1903void X86_64Assembler::LoadFromThread64(ManagedRegister mdest, ThreadOffset<8> src, size_t size) {
1904  X86_64ManagedRegister dest = mdest.AsX86_64();
1905  if (dest.IsNoRegister()) {
1906    CHECK_EQ(0u, size);
1907  } else if (dest.IsCpuRegister()) {
1908    CHECK_EQ(4u, size);
1909    gs()->movl(dest.AsCpuRegister(), Address::Absolute(src, true));
1910  } else if (dest.IsRegisterPair()) {
1911    CHECK_EQ(8u, size);
1912    gs()->movq(dest.AsRegisterPairLow(), Address::Absolute(src, true));
1913  } else if (dest.IsX87Register()) {
1914    if (size == 4) {
1915      gs()->flds(Address::Absolute(src, true));
1916    } else {
1917      gs()->fldl(Address::Absolute(src, true));
1918    }
1919  } else {
1920    CHECK(dest.IsXmmRegister());
1921    if (size == 4) {
1922      gs()->movss(dest.AsXmmRegister(), Address::Absolute(src, true));
1923    } else {
1924      gs()->movsd(dest.AsXmmRegister(), Address::Absolute(src, true));
1925    }
1926  }
1927}
1928
1929void X86_64Assembler::LoadRef(ManagedRegister mdest, FrameOffset  src) {
1930  X86_64ManagedRegister dest = mdest.AsX86_64();
1931  CHECK(dest.IsCpuRegister());
1932  movq(dest.AsCpuRegister(), Address(CpuRegister(RSP), src));
1933}
1934
1935void X86_64Assembler::LoadRef(ManagedRegister mdest, ManagedRegister base,
1936                           MemberOffset offs) {
1937  X86_64ManagedRegister dest = mdest.AsX86_64();
1938  CHECK(dest.IsCpuRegister() && dest.IsCpuRegister());
1939  movq(dest.AsCpuRegister(), Address(base.AsX86_64().AsCpuRegister(), offs));
1940}
1941
1942void X86_64Assembler::LoadRawPtr(ManagedRegister mdest, ManagedRegister base,
1943                              Offset offs) {
1944  X86_64ManagedRegister dest = mdest.AsX86_64();
1945  CHECK(dest.IsCpuRegister() && dest.IsCpuRegister());
1946  movq(dest.AsCpuRegister(), Address(base.AsX86_64().AsCpuRegister(), offs));
1947}
1948
1949void X86_64Assembler::LoadRawPtrFromThread64(ManagedRegister mdest, ThreadOffset<8> offs) {
1950  X86_64ManagedRegister dest = mdest.AsX86_64();
1951  CHECK(dest.IsCpuRegister());
1952  gs()->movq(dest.AsCpuRegister(), Address::Absolute(offs, true));
1953}
1954
1955void X86_64Assembler::SignExtend(ManagedRegister mreg, size_t size) {
1956  X86_64ManagedRegister reg = mreg.AsX86_64();
1957  CHECK(size == 1 || size == 2) << size;
1958  CHECK(reg.IsCpuRegister()) << reg;
1959  if (size == 1) {
1960    movsxb(reg.AsCpuRegister(), reg.AsCpuRegister());
1961  } else {
1962    movsxw(reg.AsCpuRegister(), reg.AsCpuRegister());
1963  }
1964}
1965
1966void X86_64Assembler::ZeroExtend(ManagedRegister mreg, size_t size) {
1967  X86_64ManagedRegister reg = mreg.AsX86_64();
1968  CHECK(size == 1 || size == 2) << size;
1969  CHECK(reg.IsCpuRegister()) << reg;
1970  if (size == 1) {
1971    movzxb(reg.AsCpuRegister(), reg.AsCpuRegister());
1972  } else {
1973    movzxw(reg.AsCpuRegister(), reg.AsCpuRegister());
1974  }
1975}
1976
1977void X86_64Assembler::Move(ManagedRegister mdest, ManagedRegister msrc, size_t size) {
1978  X86_64ManagedRegister dest = mdest.AsX86_64();
1979  X86_64ManagedRegister src = msrc.AsX86_64();
1980  if (!dest.Equals(src)) {
1981    if (dest.IsCpuRegister() && src.IsCpuRegister()) {
1982      movq(dest.AsCpuRegister(), src.AsCpuRegister());
1983    } else if (src.IsX87Register() && dest.IsXmmRegister()) {
1984      // Pass via stack and pop X87 register
1985      subl(CpuRegister(RSP), Immediate(16));
1986      if (size == 4) {
1987        CHECK_EQ(src.AsX87Register(), ST0);
1988        fstps(Address(CpuRegister(RSP), 0));
1989        movss(dest.AsXmmRegister(), Address(CpuRegister(RSP), 0));
1990      } else {
1991        CHECK_EQ(src.AsX87Register(), ST0);
1992        fstpl(Address(CpuRegister(RSP), 0));
1993        movsd(dest.AsXmmRegister(), Address(CpuRegister(RSP), 0));
1994      }
1995      addq(CpuRegister(RSP), Immediate(16));
1996    } else {
1997      // TODO: x87, SSE
1998      UNIMPLEMENTED(FATAL) << ": Move " << dest << ", " << src;
1999    }
2000  }
2001}
2002
2003void X86_64Assembler::CopyRef(FrameOffset dest, FrameOffset src,
2004                           ManagedRegister mscratch) {
2005  X86_64ManagedRegister scratch = mscratch.AsX86_64();
2006  CHECK(scratch.IsCpuRegister());
2007  movl(scratch.AsCpuRegister(), Address(CpuRegister(RSP), src));
2008  movl(Address(CpuRegister(RSP), dest), scratch.AsCpuRegister());
2009}
2010
2011void X86_64Assembler::CopyRawPtrFromThread64(FrameOffset fr_offs,
2012                                             ThreadOffset<8> thr_offs,
2013                                             ManagedRegister mscratch) {
2014  X86_64ManagedRegister scratch = mscratch.AsX86_64();
2015  CHECK(scratch.IsCpuRegister());
2016  gs()->movq(scratch.AsCpuRegister(), Address::Absolute(thr_offs, true));
2017  Store(fr_offs, scratch, 8);
2018}
2019
2020void X86_64Assembler::CopyRawPtrToThread64(ThreadOffset<8> thr_offs,
2021                                           FrameOffset fr_offs,
2022                                           ManagedRegister mscratch) {
2023  X86_64ManagedRegister scratch = mscratch.AsX86_64();
2024  CHECK(scratch.IsCpuRegister());
2025  Load(scratch, fr_offs, 8);
2026  gs()->movq(Address::Absolute(thr_offs, true), scratch.AsCpuRegister());
2027}
2028
2029void X86_64Assembler::Copy(FrameOffset dest, FrameOffset src,
2030                        ManagedRegister mscratch,
2031                        size_t size) {
2032  X86_64ManagedRegister scratch = mscratch.AsX86_64();
2033  if (scratch.IsCpuRegister() && size == 8) {
2034    Load(scratch, src, 4);
2035    Store(dest, scratch, 4);
2036    Load(scratch, FrameOffset(src.Int32Value() + 4), 4);
2037    Store(FrameOffset(dest.Int32Value() + 4), scratch, 4);
2038  } else {
2039    Load(scratch, src, size);
2040    Store(dest, scratch, size);
2041  }
2042}
2043
2044void X86_64Assembler::Copy(FrameOffset /*dst*/, ManagedRegister /*src_base*/, Offset /*src_offset*/,
2045                        ManagedRegister /*scratch*/, size_t /*size*/) {
2046  UNIMPLEMENTED(FATAL);
2047}
2048
2049void X86_64Assembler::Copy(ManagedRegister dest_base, Offset dest_offset, FrameOffset src,
2050                        ManagedRegister scratch, size_t size) {
2051  CHECK(scratch.IsNoRegister());
2052  CHECK_EQ(size, 4u);
2053  pushq(Address(CpuRegister(RSP), src));
2054  popq(Address(dest_base.AsX86_64().AsCpuRegister(), dest_offset));
2055}
2056
2057void X86_64Assembler::Copy(FrameOffset dest, FrameOffset src_base, Offset src_offset,
2058                        ManagedRegister mscratch, size_t size) {
2059  CpuRegister scratch = mscratch.AsX86_64().AsCpuRegister();
2060  CHECK_EQ(size, 4u);
2061  movq(scratch, Address(CpuRegister(RSP), src_base));
2062  movq(scratch, Address(scratch, src_offset));
2063  movq(Address(CpuRegister(RSP), dest), scratch);
2064}
2065
2066void X86_64Assembler::Copy(ManagedRegister dest, Offset dest_offset,
2067                        ManagedRegister src, Offset src_offset,
2068                        ManagedRegister scratch, size_t size) {
2069  CHECK_EQ(size, 4u);
2070  CHECK(scratch.IsNoRegister());
2071  pushq(Address(src.AsX86_64().AsCpuRegister(), src_offset));
2072  popq(Address(dest.AsX86_64().AsCpuRegister(), dest_offset));
2073}
2074
2075void X86_64Assembler::Copy(FrameOffset dest, Offset dest_offset, FrameOffset src, Offset src_offset,
2076                        ManagedRegister mscratch, size_t size) {
2077  CpuRegister scratch = mscratch.AsX86_64().AsCpuRegister();
2078  CHECK_EQ(size, 4u);
2079  CHECK_EQ(dest.Int32Value(), src.Int32Value());
2080  movq(scratch, Address(CpuRegister(RSP), src));
2081  pushq(Address(scratch, src_offset));
2082  popq(Address(scratch, dest_offset));
2083}
2084
2085void X86_64Assembler::MemoryBarrier(ManagedRegister) {
2086#if ANDROID_SMP != 0
2087  mfence();
2088#endif
2089}
2090
2091void X86_64Assembler::CreateHandleScopeEntry(ManagedRegister mout_reg,
2092                                   FrameOffset handle_scope_offset,
2093                                   ManagedRegister min_reg, bool null_allowed) {
2094  X86_64ManagedRegister out_reg = mout_reg.AsX86_64();
2095  X86_64ManagedRegister in_reg = min_reg.AsX86_64();
2096  if (in_reg.IsNoRegister()) {  // TODO(64): && null_allowed
2097    // Use out_reg as indicator of NULL
2098    in_reg = out_reg;
2099    // TODO: movzwl
2100    movl(in_reg.AsCpuRegister(), Address(CpuRegister(RSP), handle_scope_offset));
2101  }
2102  CHECK(in_reg.IsCpuRegister());
2103  CHECK(out_reg.IsCpuRegister());
2104  VerifyObject(in_reg, null_allowed);
2105  if (null_allowed) {
2106    Label null_arg;
2107    if (!out_reg.Equals(in_reg)) {
2108      xorl(out_reg.AsCpuRegister(), out_reg.AsCpuRegister());
2109    }
2110    testl(in_reg.AsCpuRegister(), in_reg.AsCpuRegister());
2111    j(kZero, &null_arg);
2112    leaq(out_reg.AsCpuRegister(), Address(CpuRegister(RSP), handle_scope_offset));
2113    Bind(&null_arg);
2114  } else {
2115    leaq(out_reg.AsCpuRegister(), Address(CpuRegister(RSP), handle_scope_offset));
2116  }
2117}
2118
2119void X86_64Assembler::CreateHandleScopeEntry(FrameOffset out_off,
2120                                   FrameOffset handle_scope_offset,
2121                                   ManagedRegister mscratch,
2122                                   bool null_allowed) {
2123  X86_64ManagedRegister scratch = mscratch.AsX86_64();
2124  CHECK(scratch.IsCpuRegister());
2125  if (null_allowed) {
2126    Label null_arg;
2127    movl(scratch.AsCpuRegister(), Address(CpuRegister(RSP), handle_scope_offset));
2128    testl(scratch.AsCpuRegister(), scratch.AsCpuRegister());
2129    j(kZero, &null_arg);
2130    leaq(scratch.AsCpuRegister(), Address(CpuRegister(RSP), handle_scope_offset));
2131    Bind(&null_arg);
2132  } else {
2133    leaq(scratch.AsCpuRegister(), Address(CpuRegister(RSP), handle_scope_offset));
2134  }
2135  Store(out_off, scratch, 8);
2136}
2137
2138// Given a handle scope entry, load the associated reference.
2139void X86_64Assembler::LoadReferenceFromHandleScope(ManagedRegister mout_reg,
2140                                         ManagedRegister min_reg) {
2141  X86_64ManagedRegister out_reg = mout_reg.AsX86_64();
2142  X86_64ManagedRegister in_reg = min_reg.AsX86_64();
2143  CHECK(out_reg.IsCpuRegister());
2144  CHECK(in_reg.IsCpuRegister());
2145  Label null_arg;
2146  if (!out_reg.Equals(in_reg)) {
2147    xorl(out_reg.AsCpuRegister(), out_reg.AsCpuRegister());
2148  }
2149  testl(in_reg.AsCpuRegister(), in_reg.AsCpuRegister());
2150  j(kZero, &null_arg);
2151  movq(out_reg.AsCpuRegister(), Address(in_reg.AsCpuRegister(), 0));
2152  Bind(&null_arg);
2153}
2154
2155void X86_64Assembler::VerifyObject(ManagedRegister /*src*/, bool /*could_be_null*/) {
2156  // TODO: not validating references
2157}
2158
2159void X86_64Assembler::VerifyObject(FrameOffset /*src*/, bool /*could_be_null*/) {
2160  // TODO: not validating references
2161}
2162
2163void X86_64Assembler::Call(ManagedRegister mbase, Offset offset, ManagedRegister) {
2164  X86_64ManagedRegister base = mbase.AsX86_64();
2165  CHECK(base.IsCpuRegister());
2166  call(Address(base.AsCpuRegister(), offset.Int32Value()));
2167  // TODO: place reference map on call
2168}
2169
2170void X86_64Assembler::Call(FrameOffset base, Offset offset, ManagedRegister mscratch) {
2171  CpuRegister scratch = mscratch.AsX86_64().AsCpuRegister();
2172  movl(scratch, Address(CpuRegister(RSP), base));
2173  call(Address(scratch, offset));
2174}
2175
2176void X86_64Assembler::CallFromThread64(ThreadOffset<8> offset, ManagedRegister /*mscratch*/) {
2177  gs()->call(Address::Absolute(offset, true));
2178}
2179
2180void X86_64Assembler::GetCurrentThread(ManagedRegister tr) {
2181  gs()->movq(tr.AsX86_64().AsCpuRegister(), Address::Absolute(Thread::SelfOffset<8>(), true));
2182}
2183
2184void X86_64Assembler::GetCurrentThread(FrameOffset offset, ManagedRegister mscratch) {
2185  X86_64ManagedRegister scratch = mscratch.AsX86_64();
2186  gs()->movq(scratch.AsCpuRegister(), Address::Absolute(Thread::SelfOffset<8>(), true));
2187  movq(Address(CpuRegister(RSP), offset), scratch.AsCpuRegister());
2188}
2189
2190// Slowpath entered when Thread::Current()->_exception is non-null
2191class X86_64ExceptionSlowPath FINAL : public SlowPath {
2192 public:
2193  explicit X86_64ExceptionSlowPath(size_t stack_adjust) : stack_adjust_(stack_adjust) {}
2194  virtual void Emit(Assembler *sp_asm) OVERRIDE;
2195 private:
2196  const size_t stack_adjust_;
2197};
2198
2199void X86_64Assembler::ExceptionPoll(ManagedRegister /*scratch*/, size_t stack_adjust) {
2200  X86_64ExceptionSlowPath* slow = new X86_64ExceptionSlowPath(stack_adjust);
2201  buffer_.EnqueueSlowPath(slow);
2202  gs()->cmpl(Address::Absolute(Thread::ExceptionOffset<8>(), true), Immediate(0));
2203  j(kNotEqual, slow->Entry());
2204}
2205
2206void X86_64ExceptionSlowPath::Emit(Assembler *sasm) {
2207  X86_64Assembler* sp_asm = down_cast<X86_64Assembler*>(sasm);
2208#define __ sp_asm->
2209  __ Bind(&entry_);
2210  // Note: the return value is dead
2211  if (stack_adjust_ != 0) {  // Fix up the frame.
2212    __ DecreaseFrameSize(stack_adjust_);
2213  }
2214  // Pass exception as argument in RDI
2215  __ gs()->movq(CpuRegister(RDI), Address::Absolute(Thread::ExceptionOffset<8>(), true));
2216  __ gs()->call(Address::Absolute(QUICK_ENTRYPOINT_OFFSET(8, pDeliverException), true));
2217  // this call should never return
2218  __ int3();
2219#undef __
2220}
2221
2222}  // namespace x86_64
2223}  // namespace art
2224
2225