assembler_x86_64.h revision 96f89a290eb67d7bf4b1636798fa28df14309cc7 
1/*
2 * Copyright (C) 2014 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 *      http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#ifndef ART_COMPILER_UTILS_X86_64_ASSEMBLER_X86_64_H_
18#define ART_COMPILER_UTILS_X86_64_ASSEMBLER_X86_64_H_
19
20#include <vector>
21#include "base/macros.h"
22#include "constants_x86_64.h"
23#include "globals.h"
24#include "managed_register_x86_64.h"
25#include "offsets.h"
26#include "utils/assembler.h"
27#include "utils.h"
28
29namespace art {
30namespace x86_64 {
31
32// Encodes an immediate value for operands.
33//
34// Note: Immediates can be 64b on x86-64 for certain instructions, but are often restricted
35// to 32b.
36//
37// Note: As we support cross-compilation, the value type must be int64_t. Please be aware of
38// conversion rules in expressions regarding negation, especially size_t on 32b.
39class Immediate {
40 public:
41  explicit Immediate(int64_t value) : value_(value) {}
42
43  int64_t value() const { return value_; }
44
45  bool is_int8() const { return IsInt(8, value_); }
46  bool is_uint8() const { return IsUint(8, value_); }
47  bool is_uint16() const { return IsUint(16, value_); }
48  bool is_int32() const {
49    // This does not work on 32b machines: return IsInt(32, value_);
50    int64_t limit = static_cast<int64_t>(1) << 31;
51    return (-limit <= value_) && (value_ < limit);
52  }
53
54 private:
55  const int64_t value_;
56
57  DISALLOW_COPY_AND_ASSIGN(Immediate);
58};
59
60
61class Operand {
62 public:
63  uint8_t mod() const {
64    return (encoding_at(0) >> 6) & 3;
65  }
66
67  Register rm() const {
68    return static_cast<Register>(encoding_at(0) & 7);
69  }
70
71  ScaleFactor scale() const {
72    return static_cast<ScaleFactor>((encoding_at(1) >> 6) & 3);
73  }
74
75  Register index() const {
76    return static_cast<Register>((encoding_at(1) >> 3) & 7);
77  }
78
79  Register base() const {
80    return static_cast<Register>(encoding_at(1) & 7);
81  }
82
83  uint8_t rex() const {
84    return rex_;
85  }
86
87  int8_t disp8() const {
88    CHECK_GE(length_, 2);
89    return static_cast<int8_t>(encoding_[length_ - 1]);
90  }
91
92  int32_t disp32() const {
93    CHECK_GE(length_, 5);
94    int32_t value;
95    memcpy(&value, &encoding_[length_ - 4], sizeof(value));
96    return value;
97  }
98
99  bool IsRegister(CpuRegister reg) const {
100    return ((encoding_[0] & 0xF8) == 0xC0)  // Addressing mode is register only.
101        && ((encoding_[0] & 0x07) == reg.LowBits())  // Register codes match.
102        && (reg.NeedsRex() == ((rex_ & 1) != 0));  // REX.000B bits match.
103  }
104
105 protected:
106  // Operand can be sub classed (e.g: Address).
107  Operand() : rex_(0), length_(0) { }
108
109  void SetModRM(uint8_t mod, CpuRegister rm) {
110    CHECK_EQ(mod & ~3, 0);
111    if (rm.NeedsRex()) {
112      rex_ |= 0x41;  // REX.000B
113    }
114    encoding_[0] = (mod << 6) | rm.LowBits();
115    length_ = 1;
116  }
117
118  void SetSIB(ScaleFactor scale, CpuRegister index, CpuRegister base) {
119    CHECK_EQ(length_, 1);
120    CHECK_EQ(scale & ~3, 0);
121    if (base.NeedsRex()) {
122      rex_ |= 0x41;  // REX.000B
123    }
124    if (index.NeedsRex()) {
125      rex_ |= 0x42;  // REX.00X0
126    }
127    encoding_[1] = (scale << 6) | (static_cast<uint8_t>(index.AsRegister()) << 3) |
128        static_cast<uint8_t>(base.AsRegister());
129    length_ = 2;
130  }
131
132  void SetDisp8(int8_t disp) {
133    CHECK(length_ == 1 || length_ == 2);
134    encoding_[length_++] = static_cast<uint8_t>(disp);
135  }
136
137  void SetDisp32(int32_t disp) {
138    CHECK(length_ == 1 || length_ == 2);
139    int disp_size = sizeof(disp);
140    memmove(&encoding_[length_], &disp, disp_size);
141    length_ += disp_size;
142  }
143
144 private:
145  uint8_t rex_;
146  uint8_t length_;
147  uint8_t encoding_[6];
148
149  explicit Operand(CpuRegister reg) { SetModRM(3, reg); }
150
151  // Get the operand encoding byte at the given index.
152  uint8_t encoding_at(int index) const {
153    CHECK_GE(index, 0);
154    CHECK_LT(index, length_);
155    return encoding_[index];
156  }
157
158  friend class X86_64Assembler;
159
160  DISALLOW_COPY_AND_ASSIGN(Operand);
161};
162
163
164class Address : public Operand {
165 public:
166  Address(CpuRegister base, int32_t disp) {
167    Init(base, disp);
168  }
169
170  Address(CpuRegister base, Offset disp) {
171    Init(base, disp.Int32Value());
172  }
173
174  Address(CpuRegister base, FrameOffset disp) {
175    CHECK_EQ(base.AsRegister(), RSP);
176    Init(CpuRegister(RSP), disp.Int32Value());
177  }
178
179  Address(CpuRegister base, MemberOffset disp) {
180    Init(base, disp.Int32Value());
181  }
182
183  void Init(CpuRegister base, int32_t disp) {
184    if (disp == 0 && base.AsRegister() != RBP) {
185      SetModRM(0, base);
186      if (base.AsRegister() == RSP) {
187        SetSIB(TIMES_1, CpuRegister(RSP), base);
188      }
189    } else if (disp >= -128 && disp <= 127) {
190      SetModRM(1, base);
191      if (base.AsRegister() == RSP) {
192        SetSIB(TIMES_1, CpuRegister(RSP), base);
193      }
194      SetDisp8(disp);
195    } else {
196      SetModRM(2, base);
197      if (base.AsRegister() == RSP) {
198        SetSIB(TIMES_1, CpuRegister(RSP), base);
199      }
200      SetDisp32(disp);
201    }
202  }
203
204
205  Address(CpuRegister index, ScaleFactor scale, int32_t disp) {
206    CHECK_NE(index.AsRegister(), RSP);  // Illegal addressing mode.
207    SetModRM(0, CpuRegister(RSP));
208    SetSIB(scale, index, CpuRegister(RBP));
209    SetDisp32(disp);
210  }
211
212  Address(CpuRegister base, CpuRegister index, ScaleFactor scale, int32_t disp) {
213    CHECK_NE(index.AsRegister(), RSP);  // Illegal addressing mode.
214    if (disp == 0 && base.AsRegister() != RBP) {
215      SetModRM(0, CpuRegister(RSP));
216      SetSIB(scale, index, base);
217    } else if (disp >= -128 && disp <= 127) {
218      SetModRM(1, CpuRegister(RSP));
219      SetSIB(scale, index, base);
220      SetDisp8(disp);
221    } else {
222      SetModRM(2, CpuRegister(RSP));
223      SetSIB(scale, index, base);
224      SetDisp32(disp);
225    }
226  }
227
228  // If no_rip is true then the Absolute address isn't RIP relative.
229  static Address Absolute(uword addr, bool no_rip = false) {
230    Address result;
231    if (no_rip) {
232      result.SetModRM(0, CpuRegister(RSP));
233      result.SetSIB(TIMES_1, CpuRegister(RSP), CpuRegister(RBP));
234      result.SetDisp32(addr);
235    } else {
236      result.SetModRM(0, CpuRegister(RBP));
237      result.SetDisp32(addr);
238    }
239    return result;
240  }
241
242  // If no_rip is true then the Absolute address isn't RIP relative.
243  static Address Absolute(ThreadOffset<8> addr, bool no_rip = false) {
244    return Absolute(addr.Int32Value(), no_rip);
245  }
246
247 private:
248  Address() {}
249
250  DISALLOW_COPY_AND_ASSIGN(Address);
251};
252
253
254class X86_64Assembler FINAL : public Assembler {
255 public:
256  X86_64Assembler() {}
257  virtual ~X86_64Assembler() {}
258
259  /*
260   * Emit Machine Instructions.
261   */
262  void call(CpuRegister reg);
263  void call(const Address& address);
264  void call(Label* label);
265
266  void pushq(CpuRegister reg);
267  void pushq(const Address& address);
268  void pushq(const Immediate& imm);
269
270  void popq(CpuRegister reg);
271  void popq(const Address& address);
272
273  void movq(CpuRegister dst, const Immediate& src);
274  void movl(CpuRegister dst, const Immediate& src);
275  void movq(CpuRegister dst, CpuRegister src);
276  void movl(CpuRegister dst, CpuRegister src);
277
278  void movq(CpuRegister dst, const Address& src);
279  void movl(CpuRegister dst, const Address& src);
280  void movq(const Address& dst, CpuRegister src);
281  void movl(const Address& dst, CpuRegister src);
282  void movl(const Address& dst, const Immediate& imm);
283
284  void movzxb(CpuRegister dst, CpuRegister src);
285  void movzxb(CpuRegister dst, const Address& src);
286  void movsxb(CpuRegister dst, CpuRegister src);
287  void movsxb(CpuRegister dst, const Address& src);
288  void movb(CpuRegister dst, const Address& src);
289  void movb(const Address& dst, CpuRegister src);
290  void movb(const Address& dst, const Immediate& imm);
291
292  void movzxw(CpuRegister dst, CpuRegister src);
293  void movzxw(CpuRegister dst, const Address& src);
294  void movsxw(CpuRegister dst, CpuRegister src);
295  void movsxw(CpuRegister dst, const Address& src);
296  void movw(CpuRegister dst, const Address& src);
297  void movw(const Address& dst, CpuRegister src);
298
299  void leaq(CpuRegister dst, const Address& src);
300
301  void movss(XmmRegister dst, const Address& src);
302  void movss(const Address& dst, XmmRegister src);
303  void movss(XmmRegister dst, XmmRegister src);
304
305  void movd(XmmRegister dst, CpuRegister src);
306  void movd(CpuRegister dst, XmmRegister src);
307
308  void addss(XmmRegister dst, XmmRegister src);
309  void addss(XmmRegister dst, const Address& src);
310  void subss(XmmRegister dst, XmmRegister src);
311  void subss(XmmRegister dst, const Address& src);
312  void mulss(XmmRegister dst, XmmRegister src);
313  void mulss(XmmRegister dst, const Address& src);
314  void divss(XmmRegister dst, XmmRegister src);
315  void divss(XmmRegister dst, const Address& src);
316
317  void movsd(XmmRegister dst, const Address& src);
318  void movsd(const Address& dst, XmmRegister src);
319  void movsd(XmmRegister dst, XmmRegister src);
320
321  void addsd(XmmRegister dst, XmmRegister src);
322  void addsd(XmmRegister dst, const Address& src);
323  void subsd(XmmRegister dst, XmmRegister src);
324  void subsd(XmmRegister dst, const Address& src);
325  void mulsd(XmmRegister dst, XmmRegister src);
326  void mulsd(XmmRegister dst, const Address& src);
327  void divsd(XmmRegister dst, XmmRegister src);
328  void divsd(XmmRegister dst, const Address& src);
329
330  void cvtsi2ss(XmmRegister dst, CpuRegister src);
331  void cvtsi2sd(XmmRegister dst, CpuRegister src);
332
333  void cvtss2si(CpuRegister dst, XmmRegister src);
334  void cvtss2sd(XmmRegister dst, XmmRegister src);
335
336  void cvtsd2si(CpuRegister dst, XmmRegister src);
337  void cvtsd2ss(XmmRegister dst, XmmRegister src);
338
339  void cvttss2si(CpuRegister dst, XmmRegister src);
340  void cvttsd2si(CpuRegister dst, XmmRegister src);
341
342  void cvtdq2pd(XmmRegister dst, XmmRegister src);
343
344  void comiss(XmmRegister a, XmmRegister b);
345  void comisd(XmmRegister a, XmmRegister b);
346
347  void sqrtsd(XmmRegister dst, XmmRegister src);
348  void sqrtss(XmmRegister dst, XmmRegister src);
349
350  void xorpd(XmmRegister dst, const Address& src);
351  void xorpd(XmmRegister dst, XmmRegister src);
352  void xorps(XmmRegister dst, const Address& src);
353  void xorps(XmmRegister dst, XmmRegister src);
354
355  void andpd(XmmRegister dst, const Address& src);
356
357  void flds(const Address& src);
358  void fstps(const Address& dst);
359
360  void fldl(const Address& src);
361  void fstpl(const Address& dst);
362
363  void fnstcw(const Address& dst);
364  void fldcw(const Address& src);
365
366  void fistpl(const Address& dst);
367  void fistps(const Address& dst);
368  void fildl(const Address& src);
369
370  void fincstp();
371  void ffree(const Immediate& index);
372
373  void fsin();
374  void fcos();
375  void fptan();
376
377  void xchgl(CpuRegister dst, CpuRegister src);
378  void xchgq(CpuRegister dst, CpuRegister src);
379  void xchgl(CpuRegister reg, const Address& address);
380
381  void cmpl(CpuRegister reg, const Immediate& imm);
382  void cmpl(CpuRegister reg0, CpuRegister reg1);
383  void cmpl(CpuRegister reg, const Address& address);
384  void cmpl(const Address& address, CpuRegister reg);
385  void cmpl(const Address& address, const Immediate& imm);
386
387  void cmpq(CpuRegister reg0, CpuRegister reg1);
388  void cmpq(CpuRegister reg0, const Immediate& imm);
389  void cmpq(CpuRegister reg0, const Address& address);
390
391  void testl(CpuRegister reg1, CpuRegister reg2);
392  void testl(CpuRegister reg, const Immediate& imm);
393
394  void andl(CpuRegister dst, const Immediate& imm);
395  void andl(CpuRegister dst, CpuRegister src);
396  void andq(CpuRegister dst, const Immediate& imm);
397
398  void orl(CpuRegister dst, const Immediate& imm);
399  void orl(CpuRegister dst, CpuRegister src);
400
401  void xorl(CpuRegister dst, CpuRegister src);
402  void xorq(CpuRegister dst, const Immediate& imm);
403  void xorq(CpuRegister dst, CpuRegister src);
404
405  void addl(CpuRegister dst, CpuRegister src);
406  void addl(CpuRegister reg, const Immediate& imm);
407  void addl(CpuRegister reg, const Address& address);
408  void addl(const Address& address, CpuRegister reg);
409  void addl(const Address& address, const Immediate& imm);
410
411  void addq(CpuRegister reg, const Immediate& imm);
412  void addq(CpuRegister dst, CpuRegister src);
413  void addq(CpuRegister dst, const Address& address);
414
415  void subl(CpuRegister dst, CpuRegister src);
416  void subl(CpuRegister reg, const Immediate& imm);
417  void subl(CpuRegister reg, const Address& address);
418
419  void subq(CpuRegister reg, const Immediate& imm);
420  void subq(CpuRegister dst, CpuRegister src);
421  void subq(CpuRegister dst, const Address& address);
422
423  void cdq();
424
425  void idivl(CpuRegister reg);
426
427  void imull(CpuRegister dst, CpuRegister src);
428  void imull(CpuRegister reg, const Immediate& imm);
429  void imull(CpuRegister reg, const Address& address);
430
431  void imull(CpuRegister reg);
432  void imull(const Address& address);
433
434  void mull(CpuRegister reg);
435  void mull(const Address& address);
436
437  void shll(CpuRegister reg, const Immediate& imm);
438  void shll(CpuRegister operand, CpuRegister shifter);
439  void shrl(CpuRegister reg, const Immediate& imm);
440  void shrl(CpuRegister operand, CpuRegister shifter);
441  void sarl(CpuRegister reg, const Immediate& imm);
442  void sarl(CpuRegister operand, CpuRegister shifter);
443
444  void negl(CpuRegister reg);
445  void notl(CpuRegister reg);
446
447  void enter(const Immediate& imm);
448  void leave();
449
450  void ret();
451  void ret(const Immediate& imm);
452
453  void nop();
454  void int3();
455  void hlt();
456
457  void j(Condition condition, Label* label);
458
459  void jmp(CpuRegister reg);
460  void jmp(const Address& address);
461  void jmp(Label* label);
462
463  X86_64Assembler* lock();
464  void cmpxchgl(const Address& address, CpuRegister reg);
465
466  void mfence();
467
468  X86_64Assembler* gs();
469
470  void setcc(Condition condition, CpuRegister dst);
471
472  //
473  // Macros for High-level operations.
474  //
475
476  void AddImmediate(CpuRegister reg, const Immediate& imm);
477
478  void LoadDoubleConstant(XmmRegister dst, double value);
479
480  void DoubleNegate(XmmRegister d);
481  void FloatNegate(XmmRegister f);
482
483  void DoubleAbs(XmmRegister reg);
484
485  void LockCmpxchgl(const Address& address, CpuRegister reg) {
486    lock()->cmpxchgl(address, reg);
487  }
488
489  //
490  // Misc. functionality
491  //
492  int PreferredLoopAlignment() { return 16; }
493  void Align(int alignment, int offset);
494  void Bind(Label* label);
495
496  //
497  // Overridden common assembler high-level functionality
498  //
499
500  // Emit code that will create an activation on the stack
501  void BuildFrame(size_t frame_size, ManagedRegister method_reg,
502                  const std::vector<ManagedRegister>& callee_save_regs,
503                  const ManagedRegisterEntrySpills& entry_spills) OVERRIDE;
504
505  // Emit code that will remove an activation from the stack
506  void RemoveFrame(size_t frame_size, const std::vector<ManagedRegister>& callee_save_regs)
507      OVERRIDE;
508
509  void IncreaseFrameSize(size_t adjust) OVERRIDE;
510  void DecreaseFrameSize(size_t adjust) OVERRIDE;
511
512  // Store routines
513  void Store(FrameOffset offs, ManagedRegister src, size_t size) OVERRIDE;
514  void StoreRef(FrameOffset dest, ManagedRegister src) OVERRIDE;
515  void StoreRawPtr(FrameOffset dest, ManagedRegister src) OVERRIDE;
516
517  void StoreImmediateToFrame(FrameOffset dest, uint32_t imm, ManagedRegister scratch) OVERRIDE;
518
519  void StoreImmediateToThread64(ThreadOffset<8> dest, uint32_t imm, ManagedRegister scratch)
520      OVERRIDE;
521
522  void StoreStackOffsetToThread64(ThreadOffset<8> thr_offs, FrameOffset fr_offs,
523                                  ManagedRegister scratch) OVERRIDE;
524
525  void StoreStackPointerToThread64(ThreadOffset<8> thr_offs) OVERRIDE;
526
527  void StoreSpanning(FrameOffset dest, ManagedRegister src, FrameOffset in_off,
528                     ManagedRegister scratch) OVERRIDE;
529
530  // Load routines
531  void Load(ManagedRegister dest, FrameOffset src, size_t size) OVERRIDE;
532
533  void LoadFromThread64(ManagedRegister dest, ThreadOffset<8> src, size_t size) OVERRIDE;
534
535  void LoadRef(ManagedRegister dest, FrameOffset  src) OVERRIDE;
536
537  void LoadRef(ManagedRegister dest, ManagedRegister base, MemberOffset offs) OVERRIDE;
538
539  void LoadRawPtr(ManagedRegister dest, ManagedRegister base, Offset offs) OVERRIDE;
540
541  void LoadRawPtrFromThread64(ManagedRegister dest, ThreadOffset<8> offs) OVERRIDE;
542
543  // Copying routines
544  void Move(ManagedRegister dest, ManagedRegister src, size_t size);
545
546  void CopyRawPtrFromThread64(FrameOffset fr_offs, ThreadOffset<8> thr_offs,
547                              ManagedRegister scratch) OVERRIDE;
548
549  void CopyRawPtrToThread64(ThreadOffset<8> thr_offs, FrameOffset fr_offs, ManagedRegister scratch)
550      OVERRIDE;
551
552  void CopyRef(FrameOffset dest, FrameOffset src, ManagedRegister scratch) OVERRIDE;
553
554  void Copy(FrameOffset dest, FrameOffset src, ManagedRegister scratch, size_t size) OVERRIDE;
555
556  void Copy(FrameOffset dest, ManagedRegister src_base, Offset src_offset, ManagedRegister scratch,
557            size_t size) OVERRIDE;
558
559  void Copy(ManagedRegister dest_base, Offset dest_offset, FrameOffset src, ManagedRegister scratch,
560            size_t size) OVERRIDE;
561
562  void Copy(FrameOffset dest, FrameOffset src_base, Offset src_offset, ManagedRegister scratch,
563            size_t size) OVERRIDE;
564
565  void Copy(ManagedRegister dest, Offset dest_offset, ManagedRegister src, Offset src_offset,
566            ManagedRegister scratch, size_t size) OVERRIDE;
567
568  void Copy(FrameOffset dest, Offset dest_offset, FrameOffset src, Offset src_offset,
569            ManagedRegister scratch, size_t size) OVERRIDE;
570
571  void MemoryBarrier(ManagedRegister) OVERRIDE;
572
573  // Sign extension
574  void SignExtend(ManagedRegister mreg, size_t size) OVERRIDE;
575
576  // Zero extension
577  void ZeroExtend(ManagedRegister mreg, size_t size) OVERRIDE;
578
579  // Exploit fast access in managed code to Thread::Current()
580  void GetCurrentThread(ManagedRegister tr) OVERRIDE;
581  void GetCurrentThread(FrameOffset dest_offset, ManagedRegister scratch) OVERRIDE;
582
583  // Set up out_reg to hold a Object** into the handle scope, or to be NULL if the
584  // value is null and null_allowed. in_reg holds a possibly stale reference
585  // that can be used to avoid loading the handle scope entry to see if the value is
586  // NULL.
587  void CreateHandleScopeEntry(ManagedRegister out_reg, FrameOffset handlescope_offset, ManagedRegister in_reg,
588                       bool null_allowed) OVERRIDE;
589
590  // Set up out_off to hold a Object** into the handle scope, or to be NULL if the
591  // value is null and null_allowed.
592  void CreateHandleScopeEntry(FrameOffset out_off, FrameOffset handlescope_offset, ManagedRegister scratch,
593                       bool null_allowed) OVERRIDE;
594
595  // src holds a handle scope entry (Object**) load this into dst
596  virtual void LoadReferenceFromHandleScope(ManagedRegister dst,
597                                     ManagedRegister src);
598
599  // Heap::VerifyObject on src. In some cases (such as a reference to this) we
600  // know that src may not be null.
601  void VerifyObject(ManagedRegister src, bool could_be_null) OVERRIDE;
602  void VerifyObject(FrameOffset src, bool could_be_null) OVERRIDE;
603
604  // Call to address held at [base+offset]
605  void Call(ManagedRegister base, Offset offset, ManagedRegister scratch) OVERRIDE;
606  void Call(FrameOffset base, Offset offset, ManagedRegister scratch) OVERRIDE;
607  void CallFromThread64(ThreadOffset<8> offset, ManagedRegister scratch) OVERRIDE;
608
609  // Generate code to check if Thread::Current()->exception_ is non-null
610  // and branch to a ExceptionSlowPath if it is.
611  void ExceptionPoll(ManagedRegister scratch, size_t stack_adjust) OVERRIDE;
612
613 private:
614  void EmitUint8(uint8_t value);
615  void EmitInt32(int32_t value);
616  void EmitInt64(int64_t value);
617  void EmitRegisterOperand(uint8_t rm, uint8_t reg);
618  void EmitXmmRegisterOperand(uint8_t rm, XmmRegister reg);
619  void EmitFixup(AssemblerFixup* fixup);
620  void EmitOperandSizeOverride();
621
622  void EmitOperand(uint8_t rm, const Operand& operand);
623  void EmitImmediate(const Immediate& imm);
624  void EmitComplex(uint8_t rm, const Operand& operand, const Immediate& immediate);
625  void EmitLabel(Label* label, int instruction_size);
626  void EmitLabelLink(Label* label);
627  void EmitNearLabelLink(Label* label);
628
629  void EmitGenericShift(int rm, CpuRegister reg, const Immediate& imm);
630  void EmitGenericShift(int rm, CpuRegister operand, CpuRegister shifter);
631
632  // If any input is not false, output the necessary rex prefix.
633  void EmitOptionalRex(bool force, bool w, bool r, bool x, bool b);
634
635  // Emit a rex prefix byte if necessary for reg. ie if reg is a register in the range R8 to R15.
636  void EmitOptionalRex32(CpuRegister reg);
637  void EmitOptionalRex32(CpuRegister dst, CpuRegister src);
638  void EmitOptionalRex32(XmmRegister dst, XmmRegister src);
639  void EmitOptionalRex32(CpuRegister dst, XmmRegister src);
640  void EmitOptionalRex32(XmmRegister dst, CpuRegister src);
641  void EmitOptionalRex32(const Operand& operand);
642  void EmitOptionalRex32(CpuRegister dst, const Operand& operand);
643  void EmitOptionalRex32(XmmRegister dst, const Operand& operand);
644
645  // Emit a REX.W prefix plus necessary register bit encodings.
646  void EmitRex64(CpuRegister reg);
647  void EmitRex64(CpuRegister dst, CpuRegister src);
648  void EmitRex64(CpuRegister dst, const Operand& operand);
649
650  // Emit a REX prefix to normalize byte registers plus necessary register bit encodings.
651  void EmitOptionalByteRegNormalizingRex32(CpuRegister dst, CpuRegister src);
652  void EmitOptionalByteRegNormalizingRex32(CpuRegister dst, const Operand& operand);
653
654  DISALLOW_COPY_AND_ASSIGN(X86_64Assembler);
655};
656
657inline void X86_64Assembler::EmitUint8(uint8_t value) {
658  buffer_.Emit<uint8_t>(value);
659}
660
661inline void X86_64Assembler::EmitInt32(int32_t value) {
662  buffer_.Emit<int32_t>(value);
663}
664
665inline void X86_64Assembler::EmitInt64(int64_t value) {
666  buffer_.Emit<int64_t>(value);
667}
668
669inline void X86_64Assembler::EmitRegisterOperand(uint8_t rm, uint8_t reg) {
670  CHECK_GE(rm, 0);
671  CHECK_LT(rm, 8);
672  buffer_.Emit<uint8_t>(0xC0 + (rm << 3) + reg);
673}
674
675inline void X86_64Assembler::EmitXmmRegisterOperand(uint8_t rm, XmmRegister reg) {
676  EmitRegisterOperand(rm, static_cast<uint8_t>(reg.AsFloatRegister()));
677}
678
679inline void X86_64Assembler::EmitFixup(AssemblerFixup* fixup) {
680  buffer_.EmitFixup(fixup);
681}
682
683inline void X86_64Assembler::EmitOperandSizeOverride() {
684  EmitUint8(0x66);
685}
686
687}  // namespace x86_64
688}  // namespace art
689
690#endif  // ART_COMPILER_UTILS_X86_64_ASSEMBLER_X86_64_H_
691