1/*
2 * Copyright (C) 2012 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 *      http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#include "disassembler_mips.h"
18
19#include <iostream>
20
21#include "base/logging.h"
22#include "base/stringprintf.h"
23#include "thread.h"
24
25namespace art {
26namespace mips {
27
28struct MipsInstruction {
29  uint32_t mask;
30  uint32_t value;
31  const char* name;
32  const char* args_fmt;
33
34  bool Matches(uint32_t instruction) const {
35    return (instruction & mask) == value;
36  }
37};
38
39static const uint32_t kOpcodeShift = 26;
40
41static const uint32_t kCop1 = (17 << kOpcodeShift);
42
43static const uint32_t kITypeMask = (0x3f << kOpcodeShift);
44static const uint32_t kJTypeMask = (0x3f << kOpcodeShift);
45static const uint32_t kRTypeMask = ((0x3f << kOpcodeShift) | (0x3f));
46static const uint32_t kSpecial2Mask = (0x3f << kOpcodeShift);
47static const uint32_t kFpMask = kRTypeMask;
48
49static const MipsInstruction gMipsInstructions[] = {
50  // "sll r0, r0, 0" is the canonical "nop", used in delay slots.
51  { 0xffffffff, 0, "nop", "" },
52
53  // R-type instructions.
54  { kRTypeMask, 0, "sll", "DTA", },
55  // 0, 1, movci
56  { kRTypeMask, 2, "srl", "DTA", },
57  { kRTypeMask, 3, "sra", "DTA", },
58  { kRTypeMask, 4, "sllv", "DTS", },
59  { kRTypeMask, 6, "srlv", "DTS", },
60  { kRTypeMask, 7, "srav", "DTS", },
61  { kRTypeMask, 8, "jr", "S", },
62  { kRTypeMask | (0x1f << 11), 9 | (31 << 11), "jalr", "S", },  // rd = 31 is implicit.
63  { kRTypeMask, 9, "jalr", "DS", },  // General case.
64  { kRTypeMask | (0x1f << 6), 10, "movz", "DST", },
65  { kRTypeMask | (0x1f << 6), 11, "movn", "DST", },
66  { kRTypeMask, 12, "syscall", "", },  // TODO: code
67  { kRTypeMask, 13, "break", "", },  // TODO: code
68  { kRTypeMask, 15, "sync", "", },  // TODO: type
69  { kRTypeMask, 16, "mfhi", "D", },
70  { kRTypeMask, 17, "mthi", "S", },
71  { kRTypeMask, 18, "mflo", "D", },
72  { kRTypeMask, 19, "mtlo", "S", },
73  { kRTypeMask, 24, "mult", "ST", },
74  { kRTypeMask, 25, "multu", "ST", },
75  { kRTypeMask, 26, "div", "ST", },
76  { kRTypeMask, 27, "divu", "ST", },
77  { kRTypeMask, 32, "add", "DST", },
78  { kRTypeMask, 33, "addu", "DST", },
79  { kRTypeMask, 34, "sub", "DST", },
80  { kRTypeMask, 35, "subu", "DST", },
81  { kRTypeMask, 36, "and", "DST", },
82  { kRTypeMask, 37, "or", "DST", },
83  { kRTypeMask, 38, "xor", "DST", },
84  { kRTypeMask, 39, "nor", "DST", },
85  { kRTypeMask, 42, "slt", "DST", },
86  { kRTypeMask, 43, "sltu", "DST", },
87  // 0, 48, tge
88  // 0, 49, tgeu
89  // 0, 50, tlt
90  // 0, 51, tltu
91  // 0, 52, teq
92  // 0, 54, tne
93
94  // SPECIAL2
95  { kSpecial2Mask | 0x7ff, (28 << kOpcodeShift) | 2, "mul", "DST" },
96  { kSpecial2Mask | 0x7ff, (28 << kOpcodeShift) | 32, "clz", "DS" },
97  { kSpecial2Mask | 0xffff, (28 << kOpcodeShift) | 0, "madd", "ST" },
98  { kSpecial2Mask | 0xffff, (28 << kOpcodeShift) | 1, "maddu", "ST" },
99  { kSpecial2Mask | 0xffff, (28 << kOpcodeShift) | 2, "mul", "DST" },
100  { kSpecial2Mask | 0xffff, (28 << kOpcodeShift) | 4, "msub", "ST" },
101  { kSpecial2Mask | 0xffff, (28 << kOpcodeShift) | 5, "msubu", "ST" },
102  { kSpecial2Mask | 0x3f, (28 << kOpcodeShift) | 0x3f, "sdbbp", "" },  // TODO: code
103
104  // J-type instructions.
105  { kJTypeMask, 2 << kOpcodeShift, "j", "L" },
106  { kJTypeMask, 3 << kOpcodeShift, "jal", "L" },
107
108  // I-type instructions.
109  { kITypeMask, 4 << kOpcodeShift, "beq", "STB" },
110  { kITypeMask, 5 << kOpcodeShift, "bne", "STB" },
111  { kITypeMask | (0x1f << 16), 1 << kOpcodeShift | (1 << 16), "bgez", "SB" },
112  { kITypeMask | (0x1f << 16), 1 << kOpcodeShift | (0 << 16), "bltz", "SB" },
113  { kITypeMask | (0x1f << 16), 1 << kOpcodeShift | (2 << 16), "bltzl", "SB" },
114  { kITypeMask | (0x1f << 16), 1 << kOpcodeShift | (16 << 16), "bltzal", "SB" },
115  { kITypeMask | (0x1f << 16), 1 << kOpcodeShift | (18 << 16), "bltzall", "SB" },
116  { kITypeMask | (0x1f << 16), 6 << kOpcodeShift | (0 << 16), "blez", "SB" },
117  { kITypeMask | (0x1f << 16), 7 << kOpcodeShift | (0 << 16), "bgtz", "SB" },
118
119  { 0xffff0000, (4 << kOpcodeShift), "b", "B" },
120  { 0xffff0000, (1 << kOpcodeShift) | (17 << 16), "bal", "B" },
121
122  { kITypeMask, 8 << kOpcodeShift, "addi", "TSi", },
123  { kITypeMask, 9 << kOpcodeShift, "addiu", "TSi", },
124  { kITypeMask, 10 << kOpcodeShift, "slti", "TSi", },
125  { kITypeMask, 11 << kOpcodeShift, "sltiu", "TSi", },
126  { kITypeMask, 12 << kOpcodeShift, "andi", "TSi", },
127  { kITypeMask, 13 << kOpcodeShift, "ori", "TSi", },
128  { kITypeMask, 14 << kOpcodeShift, "ori", "TSi", },
129  { kITypeMask, 15 << kOpcodeShift, "lui", "TI", },
130
131  { kITypeMask, 32u << kOpcodeShift, "lb", "TO", },
132  { kITypeMask, 33u << kOpcodeShift, "lh", "TO", },
133  { kITypeMask, 35u << kOpcodeShift, "lw", "TO", },
134  { kITypeMask, 36u << kOpcodeShift, "lbu", "TO", },
135  { kITypeMask, 37u << kOpcodeShift, "lhu", "TO", },
136  { kITypeMask, 40u << kOpcodeShift, "sb", "TO", },
137  { kITypeMask, 41u << kOpcodeShift, "sh", "TO", },
138  { kITypeMask, 43u << kOpcodeShift, "sw", "TO", },
139  { kITypeMask, 49u << kOpcodeShift, "lwc1", "tO", },
140  { kITypeMask, 57u << kOpcodeShift, "swc1", "tO", },
141
142  // Floating point.
143  { kFpMask,                kCop1 | 0, "add", "fdst" },
144  { kFpMask,                kCop1 | 1, "sub", "fdst" },
145  { kFpMask,                kCop1 | 2, "mul", "fdst" },
146  { kFpMask,                kCop1 | 3, "div", "fdst" },
147  { kFpMask | (0x1f << 16), kCop1 | 4, "sqrt", "fdst" },
148  { kFpMask | (0x1f << 16), kCop1 | 5, "abs", "fds" },
149  { kFpMask | (0x1f << 16), kCop1 | 6, "mov", "fds" },
150  { kFpMask | (0x1f << 16), kCop1 | 7, "neg", "fds" },
151  { kFpMask | (0x1f << 16), kCop1 | 8, "round.l", "fds" },
152  { kFpMask | (0x1f << 16), kCop1 | 9, "trunc.l", "fds" },
153  { kFpMask | (0x1f << 16), kCop1 | 10, "ceil.l", "fds" },
154  { kFpMask | (0x1f << 16), kCop1 | 11, "floor.l", "fds" },
155  { kFpMask | (0x1f << 16), kCop1 | 12, "round.w", "fds" },
156  { kFpMask | (0x1f << 16), kCop1 | 13, "trunc.w", "fds" },
157  { kFpMask | (0x1f << 16), kCop1 | 14, "ceil.w", "fds" },
158  { kFpMask | (0x1f << 16), kCop1 | 15, "floor.w", "fds" },
159  { kFpMask | (0x1f << 16), kCop1 | 32, "cvt.s", "fds" },
160  { kFpMask | (0x1f << 16), kCop1 | 33, "cvt.d", "fds" },
161  { kFpMask | (0x1f << 16), kCop1 | 36, "cvt.w", "fds" },
162  { kFpMask | (0x1f << 16), kCop1 | 37, "cvt.l", "fds" },
163  { kFpMask | (0x1f << 16), kCop1 | 38, "cvt.ps", "fds" },
164};
165
166static uint32_t ReadU32(const uint8_t* ptr) {
167  // We only support little-endian MIPS.
168  return ptr[0] | (ptr[1] << 8) | (ptr[2] << 16) | (ptr[3] << 24);
169}
170
171size_t DisassemblerMips::Dump(std::ostream& os, const uint8_t* instr_ptr) {
172  uint32_t instruction = ReadU32(instr_ptr);
173
174  uint32_t rs = (instruction >> 21) & 0x1f;  // I-type, R-type.
175  uint32_t rt = (instruction >> 16) & 0x1f;  // I-type, R-type.
176  uint32_t rd = (instruction >> 11) & 0x1f;  // R-type.
177  uint32_t sa = (instruction >>  6) & 0x1f;  // R-type.
178
179  std::string opcode;
180  std::ostringstream args;
181
182  // TODO: remove this!
183  uint32_t op = (instruction >> 26) & 0x3f;
184  uint32_t function = (instruction & 0x3f);  // R-type.
185  opcode = StringPrintf("op=%d fn=%d", op, function);
186
187  for (size_t i = 0; i < arraysize(gMipsInstructions); ++i) {
188    if (gMipsInstructions[i].Matches(instruction)) {
189      opcode = gMipsInstructions[i].name;
190      for (const char* args_fmt = gMipsInstructions[i].args_fmt; *args_fmt; ++args_fmt) {
191        switch (*args_fmt) {
192          case 'A':  // sa (shift amount).
193            args << sa;
194            break;
195          case 'B':  // Branch offset.
196            {
197              int32_t offset = static_cast<int16_t>(instruction & 0xffff);
198              offset <<= 2;
199              offset += 4;  // Delay slot.
200              args << FormatInstructionPointer(instr_ptr + offset)
201                   << StringPrintf("  ; %+d", offset);
202            }
203            break;
204          case 'D': args << 'r' << rd; break;
205          case 'd': args << 'f' << rd; break;
206          case 'f':  // Floating point "fmt".
207            {
208              size_t fmt = (instruction >> 21) & 0x7;  // TODO: other fmts?
209              switch (fmt) {
210                case 0: opcode += ".s"; break;
211                case 1: opcode += ".d"; break;
212                case 4: opcode += ".w"; break;
213                case 5: opcode += ".l"; break;
214                case 6: opcode += ".ps"; break;
215                default: opcode += ".?"; break;
216              }
217              continue;  // No ", ".
218            }
219            break;
220          case 'I':  // Upper 16-bit immediate.
221            args << reinterpret_cast<void*>((instruction & 0xffff) << 16);
222            break;
223          case 'i':  // Sign-extended lower 16-bit immediate.
224            args << static_cast<int16_t>(instruction & 0xffff);
225            break;
226          case 'L':  // Jump label.
227            {
228              // TODO: is this right?
229              uint32_t instr_index = (instruction & 0x1ffffff);
230              uint32_t target = (instr_index << 2);
231              target |= (reinterpret_cast<uintptr_t>(instr_ptr + 4) & 0xf0000000);
232              args << reinterpret_cast<void*>(target);
233            }
234            break;
235          case 'O':  // +x(rs)
236            {
237              int32_t offset = static_cast<int16_t>(instruction & 0xffff);
238              args << StringPrintf("%+d(r%d)", offset, rs);
239              if (rs == 17) {
240                args << "  ; ";
241                Thread::DumpThreadOffset<4>(args, offset);
242              }
243            }
244            break;
245          case 'S': args << 'r' << rs; break;
246          case 's': args << 'f' << rs; break;
247          case 'T': args << 'r' << rt; break;
248          case 't': args << 'f' << rt; break;
249        }
250        if (*(args_fmt + 1)) {
251          args << ", ";
252        }
253      }
254      break;
255    }
256  }
257
258  os << FormatInstructionPointer(instr_ptr)
259     << StringPrintf(": %08x\t%-7s ", instruction, opcode.c_str())
260     << args.str() << '\n';
261  return 4;
262}
263
264void DisassemblerMips::Dump(std::ostream& os, const uint8_t* begin, const uint8_t* end) {
265  for (const uint8_t* cur = begin; cur < end; cur += 4) {
266    Dump(os, cur);
267  }
268}
269
270}  // namespace mips
271}  // namespace art
272