_setjmp.S revision c124baaf29a948fd8b93e7f1fefc20b659271026 
1/*	$OpenBSD: _setjmp.S,v 1.4 2005/08/07 16:40:15 espie Exp $ */
2
3/*
4 * Copyright (c) 2002 Opsycon AB  (www.opsycon.se / www.opsycon.com)
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 * 3. Neither the name of Opsycon AB nor the names of its contributors
15 *    may be used to endorse or promote products derived from this software
16 *    without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
19 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
20 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
22 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 */
31
32#include <machine/asm.h>
33#include <machine/regnum.h>
34#include <machine/setjmp.h>
35
36/*
37 * _setjmp, _longjmp (not restoring signal state)
38 *
39 * XXX FPSET should probably be taken from SR setting. hmmm...
40 *  GPOFF and FRAMESIZE must be the same for both _setjmp and _longjmp!
41 *
42 */
43
44FRAMESZ= MKFSIZ(0,4)
45GPOFF= FRAMESZ-2*REGSZ
46
47#define FPREG64_S(FPR, OFF, BASE)       \
48        swc1    FPR, OFF(BASE)  ;       \
49        mfhc1   t0, FPR         ;       \
50        sw      t0, OFF+4(BASE) ;
51
52#define FPREG64_L(FPR, OFF, BASE)       \
53        lw      t0, OFF+4(BASE) ;       \
54        lw      t1, OFF(BASE)   ;       \
55        mtc1    t1, FPR         ;       \
56        mthc1   t0, FPR         ;       \
57
58LEAF(_setjmp, FRAMESZ)
59	PTR_SUBU sp, FRAMESZ
60	SETUP_GP64(GPOFF, _setjmp)
61	SAVE_GP(GPOFF)
62	.set	noreorder
63#if defined(__mips64)
64	dli	v0, 0xACEDBADE			# sigcontext magic number
65#else
66	li	v0, 0xACEDBADE			# sigcontext magic number
67#endif
68	REG_S	v0, SC_REGS+ZERO*REGSZ(a0)
69	REG_S	s0, SC_REGS+S0*REGSZ(a0)
70	REG_S	s1, SC_REGS+S1*REGSZ(a0)
71	REG_S	s2, SC_REGS+S2*REGSZ(a0)
72	REG_S	s3, SC_REGS+S3*REGSZ(a0)
73	REG_S	s4, SC_REGS+S4*REGSZ(a0)
74	REG_S	s5, SC_REGS+S5*REGSZ(a0)
75	REG_S	s6, SC_REGS+S6*REGSZ(a0)
76	REG_S	s7, SC_REGS+S7*REGSZ(a0)
77	REG_S	s8, SC_REGS+S8*REGSZ(a0)
78	REG_L	v0, GPOFF(sp)
79	REG_S	v0, SC_REGS+GP*REGSZ(a0)
80	PTR_ADDU v0, sp, FRAMESZ
81	REG_S	v0, SC_REGS+SP*REGSZ(a0)
82	REG_S	ra, SC_PC(a0)
83
84#if !defined(SOFTFLOAT)
85	li	v0, 1				# be nice if we could tell
86	REG_S	v0, SC_FPUSED(a0)		# sc_fpused = 1
87	cfc1	v0, $31
88#if _MIPS_FPSET == 32
89        FPREG64_S($f20, SC_FPREGS+((F20-F0)*REGSZ_FP), a0)
90        FPREG64_S($f21, SC_FPREGS+((F21-F0)*REGSZ_FP), a0)
91        FPREG64_S($f22, SC_FPREGS+((F22-F0)*REGSZ_FP), a0)
92        FPREG64_S($f23, SC_FPREGS+((F23-F0)*REGSZ_FP), a0)
93        FPREG64_S($f24, SC_FPREGS+((F24-F0)*REGSZ_FP), a0)
94        FPREG64_S($f25, SC_FPREGS+((F25-F0)*REGSZ_FP), a0)
95        FPREG64_S($f26, SC_FPREGS+((F26-F0)*REGSZ_FP), a0)
96        FPREG64_S($f27, SC_FPREGS+((F27-F0)*REGSZ_FP), a0)
97        FPREG64_S($f28, SC_FPREGS+((F28-F0)*REGSZ_FP), a0)
98        FPREG64_S($f29, SC_FPREGS+((F29-F0)*REGSZ_FP), a0)
99        FPREG64_S($f30, SC_FPREGS+((F30-F0)*REGSZ_FP), a0)
100        FPREG64_S($f31, SC_FPREGS+((F31-F0)*REGSZ_FP), a0)
101#else
102        swc1    $f20, SC_FPREGS+((F20-F0)*REGSZ_FP)(a0)
103        swc1    $f21, SC_FPREGS+((F21-F0)*REGSZ_FP)(a0)
104        swc1    $f22, SC_FPREGS+((F22-F0)*REGSZ_FP)(a0)
105        swc1    $f23, SC_FPREGS+((F23-F0)*REGSZ_FP)(a0)
106        swc1    $f24, SC_FPREGS+((F24-F0)*REGSZ_FP)(a0)
107        swc1    $f25, SC_FPREGS+((F25-F0)*REGSZ_FP)(a0)
108        swc1    $f26, SC_FPREGS+((F26-F0)*REGSZ_FP)(a0)
109        swc1    $f27, SC_FPREGS+((F27-F0)*REGSZ_FP)(a0)
110        swc1    $f28, SC_FPREGS+((F28-F0)*REGSZ_FP)(a0)
111        swc1    $f29, SC_FPREGS+((F29-F0)*REGSZ_FP)(a0)
112        swc1    $f30, SC_FPREGS+((F30-F0)*REGSZ_FP)(a0)
113        swc1    $f31, SC_FPREGS+((F31-F0)*REGSZ_FP)(a0)
114#endif
115	REG_S	v0, SC_FPREGS+((FSR-F0)*REGSZ)(a0)
116#endif /* !SOFTFLOAT */
117	RESTORE_GP64
118	PTR_ADDU sp, FRAMESZ
119	j	ra
120	 move	v0, zero
121END(_setjmp)
122
123LEAF(_longjmp, FRAMESZ)
124	PTR_SUBU sp, FRAMESZ
125	SETUP_GP64(GPOFF, _longjmp)
126	SAVE_GP(GPOFF)
127	.set    noreorder
128	REG_L	v0, SC_REGS+ZERO*REGSZ(a0)
129	bne	v0, 0xACEDBADE, botch		# jump if error
130	REG_L	ra, SC_PC(a0)
131	REG_L	v0, SC_FPREGS+((FSR-F0)*REGSZ)(a0)
132	REG_L	s0, SC_REGS+S0*REGSZ(a0)
133	REG_L	s1, SC_REGS+S1*REGSZ(a0)
134	REG_L	s2, SC_REGS+S2*REGSZ(a0)
135	REG_L	s3, SC_REGS+S3*REGSZ(a0)
136	REG_L	s4, SC_REGS+S4*REGSZ(a0)
137	REG_L	s5, SC_REGS+S5*REGSZ(a0)
138	REG_L	s6, SC_REGS+S6*REGSZ(a0)
139	REG_L	s7, SC_REGS+S7*REGSZ(a0)
140	REG_L	s8, SC_REGS+S8*REGSZ(a0)
141	REG_L	gp, SC_REGS+GP*REGSZ(a0)
142	REG_L	sp, SC_REGS+SP*REGSZ(a0)
143#if !defined(SOFTFLOAT)
144	ctc1	v0, $31
145#if _MIPS_FPSET == 32
146        FPREG64_L($f20, SC_FPREGS+((F20-F0)*REGSZ_FP), a0)
147        FPREG64_L($f21, SC_FPREGS+((F21-F0)*REGSZ_FP), a0)
148        FPREG64_L($f22, SC_FPREGS+((F22-F0)*REGSZ_FP), a0)
149        FPREG64_L($f23, SC_FPREGS+((F23-F0)*REGSZ_FP), a0)
150        FPREG64_L($f24, SC_FPREGS+((F24-F0)*REGSZ_FP), a0)
151        FPREG64_L($f25, SC_FPREGS+((F25-F0)*REGSZ_FP), a0)
152        FPREG64_L($f26, SC_FPREGS+((F26-F0)*REGSZ_FP), a0)
153        FPREG64_L($f27, SC_FPREGS+((F27-F0)*REGSZ_FP), a0)
154        FPREG64_L($f28, SC_FPREGS+((F28-F0)*REGSZ_FP), a0)
155        FPREG64_L($f29, SC_FPREGS+((F29-F0)*REGSZ_FP), a0)
156        FPREG64_L($f30, SC_FPREGS+((F30-F0)*REGSZ_FP), a0)
157        FPREG64_L($f31, SC_FPREGS+((F31-F0)*REGSZ_FP), a0)
158#else
159        lwc1    $f20, SC_FPREGS+((F20-F0)*REGSZ_FP)(a0)
160        lwc1    $f21, SC_FPREGS+((F21-F0)*REGSZ_FP)(a0)
161        lwc1    $f22, SC_FPREGS+((F22-F0)*REGSZ_FP)(a0)
162        lwc1    $f23, SC_FPREGS+((F23-F0)*REGSZ_FP)(a0)
163        lwc1    $f24, SC_FPREGS+((F24-F0)*REGSZ_FP)(a0)
164        lwc1    $f25, SC_FPREGS+((F25-F0)*REGSZ_FP)(a0)
165        lwc1    $f26, SC_FPREGS+((F26-F0)*REGSZ_FP)(a0)
166        lwc1    $f27, SC_FPREGS+((F27-F0)*REGSZ_FP)(a0)
167        lwc1    $f28, SC_FPREGS+((F28-F0)*REGSZ_FP)(a0)
168        lwc1    $f29, SC_FPREGS+((F29-F0)*REGSZ_FP)(a0)
169        lwc1    $f30, SC_FPREGS+((F30-F0)*REGSZ_FP)(a0)
170        lwc1    $f31, SC_FPREGS+((F31-F0)*REGSZ_FP)(a0)
171#endif
172#endif /* !SOFTFLOAT */
173	bne	a1, zero, 1f
174	 nop
175	li	a1, 1			# never return 0!
1761:
177	j	ra
178	 move	v0, a1
179
180botch:
181	jal	longjmperror
182	nop
183	jal	abort
184	nop
185	RESTORE_GP64
186	PTR_ADDU sp, FRAMESZ
187END(_longjmp)
188
189