tegra_drm.h revision 8cb52b056cfc302e05304d847c4228dff15715cf
1/**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19#ifndef _UAPI_TEGRA_DRM_H_ 20#define _UAPI_TEGRA_DRM_H_ 21struct drm_tegra_gem_create { 22 __u64 size; 23/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 24 __u32 flags; 25 __u32 handle; 26}; 27struct drm_tegra_gem_mmap { 28/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 29 __u32 handle; 30 __u32 offset; 31}; 32struct drm_tegra_syncpt_read { 33/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 34 __u32 id; 35 __u32 value; 36}; 37struct drm_tegra_syncpt_incr { 38/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 39 __u32 id; 40 __u32 pad; 41}; 42struct drm_tegra_syncpt_wait { 43/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 44 __u32 id; 45 __u32 thresh; 46 __u32 timeout; 47 __u32 value; 48/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 49}; 50#define DRM_TEGRA_NO_TIMEOUT (0xffffffff) 51struct drm_tegra_open_channel { 52 __u32 client; 53/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 54 __u32 pad; 55 __u64 context; 56}; 57struct drm_tegra_close_channel { 58/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 59 __u64 context; 60}; 61struct drm_tegra_get_syncpt { 62 __u64 context; 63/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 64 __u32 index; 65 __u32 id; 66}; 67struct drm_tegra_syncpt { 68/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 69 __u32 id; 70 __u32 incrs; 71}; 72struct drm_tegra_cmdbuf { 73/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 74 __u32 handle; 75 __u32 offset; 76 __u32 words; 77 __u32 pad; 78/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 79}; 80struct drm_tegra_reloc { 81 struct { 82 __u32 handle; 83/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 84 __u32 offset; 85 } cmdbuf; 86 struct { 87 __u32 handle; 88/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 89 __u32 offset; 90 } target; 91 __u32 shift; 92 __u32 pad; 93/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 94}; 95struct drm_tegra_waitchk { 96 __u32 handle; 97 __u32 offset; 98/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 99 __u32 syncpt; 100 __u32 thresh; 101}; 102struct drm_tegra_submit { 103/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 104 __u64 context; 105 __u32 num_syncpts; 106 __u32 num_cmdbufs; 107 __u32 num_relocs; 108/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 109 __u32 num_waitchks; 110 __u32 waitchk_mask; 111 __u32 timeout; 112 __u32 pad; 113/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 114 __u64 syncpts; 115 __u64 cmdbufs; 116 __u64 relocs; 117 __u64 waitchks; 118/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 119 __u32 fence; 120 __u32 reserved[5]; 121}; 122#define DRM_TEGRA_GEM_CREATE 0x00 123/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 124#define DRM_TEGRA_GEM_MMAP 0x01 125#define DRM_TEGRA_SYNCPT_READ 0x02 126#define DRM_TEGRA_SYNCPT_INCR 0x03 127#define DRM_TEGRA_SYNCPT_WAIT 0x04 128/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 129#define DRM_TEGRA_OPEN_CHANNEL 0x05 130#define DRM_TEGRA_CLOSE_CHANNEL 0x06 131#define DRM_TEGRA_GET_SYNCPT 0x07 132#define DRM_TEGRA_SUBMIT 0x08 133/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 134#define DRM_IOCTL_TEGRA_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_CREATE, struct drm_tegra_gem_create) 135#define DRM_IOCTL_TEGRA_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_MMAP, struct drm_tegra_gem_mmap) 136#define DRM_IOCTL_TEGRA_SYNCPT_READ DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_READ, struct drm_tegra_syncpt_read) 137#define DRM_IOCTL_TEGRA_SYNCPT_INCR DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_INCR, struct drm_tegra_syncpt_incr) 138/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 139#define DRM_IOCTL_TEGRA_SYNCPT_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_WAIT, struct drm_tegra_syncpt_wait) 140#define DRM_IOCTL_TEGRA_OPEN_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_OPEN_CHANNEL, struct drm_tegra_open_channel) 141#define DRM_IOCTL_TEGRA_CLOSE_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_CLOSE_CHANNEL, struct drm_tegra_open_channel) 142#define DRM_IOCTL_TEGRA_GET_SYNCPT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT, struct drm_tegra_get_syncpt) 143/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 144#define DRM_IOCTL_TEGRA_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SUBMIT, struct drm_tegra_submit) 145#endif 146