fenv.h revision a147a1da5c268e9d556c207be0d3da0a519b2d54 
1/*-
2 * Copyright (c) 2004-2005 David Schultz <das@FreeBSD.ORG>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: src/lib/msun/arm/fenv.h,v 1.5 2005/03/16 19:03:45 das Exp $
27 */
28
29/*
30 * In ARMv8, AArch64 state, floating-point operation is controlled by:
31 *
32 *  * FPCR - 32Bit Floating-Point Control Register:
33 *      * [31:27] - Reserved, Res0;
34 *      * [26]    - AHP, Alternative half-precision control bit;
35 *      * [25]    - DN, Default NaN mode control bit;
36 *      * [24]    - FZ, Flush-to-zero mode control bit;
37 *      * [23:22] - RMode, Rounding Mode control field:
38 *            * 00  - Round to Nearest (RN) mode;
39 *            * 01  - Round towards Plus Infinity (RP) mode;
40 *            * 10  - Round towards Minus Infinity (RM) mode;
41 *            * 11  - Round towards Zero (RZ) mode.
42 *      * [21:20] - Stride, ignored during AArch64 execution;
43 *      * [19]    - Reserved, Res0;
44 *      * [18:16] - Len, ignored during AArch64 execution;
45 *      * [15]    - IDE, Input Denormal exception trap;
46 *      * [14:13] - Reserved, Res0;
47 *      * [12]    - IXE, Inexact exception trap;
48 *      * [11]    - UFE, Underflow exception trap;
49 *      * [10]    - OFE, Overflow exception trap;
50 *      * [9]     - DZE, Division by Zero exception;
51 *      * [8]     - IOE, Invalid Operation exception;
52 *      * [7:0]   - Reserved, Res0.
53 *
54 *  * FPSR - 32Bit Floating-Point Status Register:
55 *      * [31]    - N, Negative condition flag for AArch32 (AArch64 sets PSTATE.N);
56 *      * [30]    - Z, Zero condition flag for AArch32 (AArch64 sets PSTATE.Z);
57 *      * [29]    - C, Carry conditon flag for AArch32 (AArch64 sets PSTATE.C);
58 *      * [28]    - V, Overflow conditon flag for AArch32 (AArch64 sets PSTATE.V);
59 *      * [27]    - QC, Cumulative saturation bit, Advanced SIMD only;
60 *      * [26:8]  - Reserved, Res0;
61 *      * [7]     - IDC, Input Denormal cumulative exception;
62 *      * [6:5]   - Reserved, Res0;
63 *      * [4]     - IXC, Inexact cumulative exception;
64 *      * [3]     - UFC, Underflow cumulative exception;
65 *      * [2]     - OFC, Overflow cumulative exception;
66 *      * [1]     - DZC, Division by Zero cumulative exception;
67 *      * [0]     - IOC, Invalid Operation cumulative exception.
68 */
69
70#ifndef _ARM64_FENV_H_
71#define _ARM64_FENV_H_
72
73#include <sys/types.h>
74
75__BEGIN_DECLS
76
77typedef struct {
78  __uint32_t __control;     /* FPCR, Floating-point Control Register */
79  __uint32_t __status;      /* FPSR, Floating-point Status Register */
80} fenv_t;
81
82typedef __uint32_t fexcept_t;
83
84/* Exception flags. */
85#define FE_INVALID    0x01
86#define FE_DIVBYZERO  0x02
87#define FE_OVERFLOW   0x04
88#define FE_UNDERFLOW  0x08
89#define FE_INEXACT    0x10
90#define FE_DENORMAL   0x80
91#define FE_ALL_EXCEPT (FE_DIVBYZERO | FE_INEXACT | FE_INVALID | \
92                       FE_OVERFLOW | FE_UNDERFLOW | FE_DENORMAL)
93
94/* Rounding modes. */
95#define FE_TONEAREST  0x0
96#define FE_UPWARD     0x1
97#define FE_DOWNWARD   0x2
98#define FE_TOWARDZERO 0x3
99
100__END_DECLS
101
102#endif /* !_ARM64_FENV_H_ */
103