130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#ifndef _I810_DRM_H_ 230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define _I810_DRM_H_ 330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng/* WARNING: These defines must be the same as what the Xserver uses. 530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * if you change them, you must change the defines in the Xserver. 630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng */ 730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#ifndef _I810_DEFINES_ 930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define _I810_DEFINES_ 1030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 1130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define I810_DMA_BUF_ORDER 12 1230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define I810_DMA_BUF_SZ (1<<I810_DMA_BUF_ORDER) 1330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define I810_DMA_BUF_NR 256 1430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define I810_NR_SAREA_CLIPRECTS 8 1530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 1630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng/* Each region is a minimum of 64k, and there are at most 64 of them. 1730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng */ 1830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define I810_NR_TEX_REGIONS 64 1930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define I810_LOG_MIN_TEX_REGION_SIZE 16 2030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#endif 2130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 2230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define I810_UPLOAD_TEX0IMAGE 0x1 /* handled clientside */ 2330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define I810_UPLOAD_TEX1IMAGE 0x2 /* handled clientside */ 2430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define I810_UPLOAD_CTX 0x4 2530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define I810_UPLOAD_BUFFERS 0x8 2630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define I810_UPLOAD_TEX0 0x10 2730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define I810_UPLOAD_TEX1 0x20 2830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define I810_UPLOAD_CLIPRECTS 0x40 2930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 3030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng/* Indices into buf.Setup where various bits of state are mirrored per 3130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * context and per buffer. These can be fired at the card as a unit, 3230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * or in a piecewise fashion as required. 3330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng */ 3430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 3530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng/* Destbuffer state 3630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * - backbuffer linear offset and pitch -- invarient in the current dri 3730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * - zbuffer linear offset and pitch -- also invarient 3830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * - drawing origin in back and depth buffers. 3930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * 4030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * Keep the depth/back buffer state here to accommodate private buffers 4130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * in the future. 4230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng */ 4330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define I810_DESTREG_DI0 0 /* CMD_OP_DESTBUFFER_INFO (2 dwords) */ 4430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define I810_DESTREG_DI1 1 4530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define I810_DESTREG_DV0 2 /* GFX_OP_DESTBUFFER_VARS (2 dwords) */ 4630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define I810_DESTREG_DV1 3 4730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define I810_DESTREG_DR0 4 /* GFX_OP_DRAWRECT_INFO (4 dwords) */ 4830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define I810_DESTREG_DR1 5 4930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define I810_DESTREG_DR2 6 5030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define I810_DESTREG_DR3 7 5130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define I810_DESTREG_DR4 8 5230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define I810_DEST_SETUP_SIZE 10 5330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 5430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng/* Context state 5530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng */ 5630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define I810_CTXREG_CF0 0 /* GFX_OP_COLOR_FACTOR */ 5730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define I810_CTXREG_CF1 1 5830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define I810_CTXREG_ST0 2 /* GFX_OP_STIPPLE */ 5930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define I810_CTXREG_ST1 3 6030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define I810_CTXREG_VF 4 /* GFX_OP_VERTEX_FMT */ 6130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define I810_CTXREG_MT 5 /* GFX_OP_MAP_TEXELS */ 6230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define I810_CTXREG_MC0 6 /* GFX_OP_MAP_COLOR_STAGES - stage 0 */ 6330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define I810_CTXREG_MC1 7 /* GFX_OP_MAP_COLOR_STAGES - stage 1 */ 6430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define I810_CTXREG_MC2 8 /* GFX_OP_MAP_COLOR_STAGES - stage 2 */ 6530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define I810_CTXREG_MA0 9 /* GFX_OP_MAP_ALPHA_STAGES - stage 0 */ 6630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define I810_CTXREG_MA1 10 /* GFX_OP_MAP_ALPHA_STAGES - stage 1 */ 6730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define I810_CTXREG_MA2 11 /* GFX_OP_MAP_ALPHA_STAGES - stage 2 */ 6830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define I810_CTXREG_SDM 12 /* GFX_OP_SRC_DEST_MONO */ 6930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define I810_CTXREG_FOG 13 /* GFX_OP_FOG_COLOR */ 7030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define I810_CTXREG_B1 14 /* GFX_OP_BOOL_1 */ 7130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define I810_CTXREG_B2 15 /* GFX_OP_BOOL_2 */ 7230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define I810_CTXREG_LCS 16 /* GFX_OP_LINEWIDTH_CULL_SHADE_MODE */ 7330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define I810_CTXREG_PV 17 /* GFX_OP_PV_RULE -- Invarient! */ 7430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define I810_CTXREG_ZA 18 /* GFX_OP_ZBIAS_ALPHAFUNC */ 7530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define I810_CTXREG_AA 19 /* GFX_OP_ANTIALIAS */ 7630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define I810_CTX_SETUP_SIZE 20 7730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 7830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng/* Texture state (per tex unit) 7930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng */ 8030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define I810_TEXREG_MI0 0 /* GFX_OP_MAP_INFO (4 dwords) */ 8130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define I810_TEXREG_MI1 1 8230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define I810_TEXREG_MI2 2 8330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define I810_TEXREG_MI3 3 8430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define I810_TEXREG_MF 4 /* GFX_OP_MAP_FILTER */ 8530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define I810_TEXREG_MLC 5 /* GFX_OP_MAP_LOD_CTL */ 8630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define I810_TEXREG_MLL 6 /* GFX_OP_MAP_LOD_LIMITS */ 8730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define I810_TEXREG_MCS 7 /* GFX_OP_MAP_COORD_SETS ??? */ 8830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define I810_TEX_SETUP_SIZE 8 8930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 9030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng/* Flags for clear ioctl 9130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng */ 9230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define I810_FRONT 0x1 9330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define I810_BACK 0x2 9430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define I810_DEPTH 0x4 9530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 9630692c65c4174412c90e79489e98ab85c1a7412fBen Chengtypedef enum _drm_i810_init_func { 9730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng I810_INIT_DMA = 0x01, 9830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng I810_CLEANUP_DMA = 0x02, 9930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng I810_INIT_DMA_1_4 = 0x03 10030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng} drm_i810_init_func_t; 10130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 10230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng/* This is the init structure after v1.2 */ 10330692c65c4174412c90e79489e98ab85c1a7412fBen Chengtypedef struct _drm_i810_init { 10430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng drm_i810_init_func_t func; 10530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int mmio_offset; 10630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int buffers_offset; 10730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng int sarea_priv_offset; 10830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int ring_start; 10930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int ring_end; 11030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int ring_size; 11130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int front_offset; 11230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int back_offset; 11330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int depth_offset; 11430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int overlay_offset; 11530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int overlay_physical; 11630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int w; 11730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int h; 11830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int pitch; 11930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int pitch_bits; 12030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng} drm_i810_init_t; 12130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 12230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng/* This is the init structure prior to v1.2 */ 12330692c65c4174412c90e79489e98ab85c1a7412fBen Chengtypedef struct _drm_i810_pre12_init { 12430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng drm_i810_init_func_t func; 12530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int mmio_offset; 12630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int buffers_offset; 12730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng int sarea_priv_offset; 12830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int ring_start; 12930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int ring_end; 13030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int ring_size; 13130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int front_offset; 13230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int back_offset; 13330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int depth_offset; 13430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int w; 13530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int h; 13630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int pitch; 13730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int pitch_bits; 13830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng} drm_i810_pre12_init_t; 13930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 14030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng/* Warning: If you change the SAREA structure you must change the Xserver 14130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * structure as well */ 14230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 14330692c65c4174412c90e79489e98ab85c1a7412fBen Chengtypedef struct _drm_i810_tex_region { 14430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned char next, prev; /* indices to form a circular LRU */ 14530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned char in_use; /* owned by a client, or free? */ 14630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng int age; /* tracked by clients to update local LRU's */ 14730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng} drm_i810_tex_region_t; 14830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 14930692c65c4174412c90e79489e98ab85c1a7412fBen Chengtypedef struct _drm_i810_sarea { 15030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int ContextState[I810_CTX_SETUP_SIZE]; 15130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int BufferState[I810_DEST_SETUP_SIZE]; 15230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int TexState[2][I810_TEX_SETUP_SIZE]; 15330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int dirty; 15430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 15530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int nbox; 15630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng struct drm_clip_rect boxes[I810_NR_SAREA_CLIPRECTS]; 15730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 15830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng /* Maintain an LRU of contiguous regions of texture space. If 15930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * you think you own a region of texture memory, and it has an 16030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * age different to the one you set, then you are mistaken and 16130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * it has been stolen by another client. If global texAge 16230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * hasn't changed, there is no need to walk the list. 16330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * 16430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * These regions can be used as a proxy for the fine-grained 16530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * texture information of other clients - by maintaining them 16630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * in the same lru which is used to age their own textures, 16730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * clients have an approximate lru for the whole of global 16830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * texture space, and can make informed decisions as to which 16930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * areas to kick out. There is no need to choose whether to 17030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * kick out your own texture or someone else's - simply eject 17130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * them all in LRU order. 17230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng */ 17330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 17430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng drm_i810_tex_region_t texList[I810_NR_TEX_REGIONS + 1]; 17530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng /* Last elt is sentinal */ 17630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng int texAge; /* last time texture was uploaded */ 17730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng int last_enqueue; /* last time a buffer was enqueued */ 17830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng int last_dispatch; /* age of the most recently dispatched buffer */ 17930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng int last_quiescent; /* */ 18030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng int ctxOwner; /* last context to upload state */ 18130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 18230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng int vertex_prim; 18330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 18430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng int pf_enabled; /* is pageflipping allowed? */ 18530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng int pf_active; 18630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng int pf_current_page; /* which buffer is being displayed? */ 18730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng} drm_i810_sarea_t; 18830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 18930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng/* WARNING: If you change any of these defines, make sure to change the 19030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * defines in the Xserver file (xf86drmMga.h) 19130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng */ 19230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 19330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng/* i810 specific ioctls 19430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * The device specific ioctl range is 0x40 to 0x79. 19530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng */ 19630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DRM_I810_INIT 0x00 19730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DRM_I810_VERTEX 0x01 19830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DRM_I810_CLEAR 0x02 19930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DRM_I810_FLUSH 0x03 20030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DRM_I810_GETAGE 0x04 20130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DRM_I810_GETBUF 0x05 20230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DRM_I810_SWAP 0x06 20330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DRM_I810_COPY 0x07 20430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DRM_I810_DOCOPY 0x08 20530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DRM_I810_OV0INFO 0x09 20630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DRM_I810_FSTATUS 0x0a 20730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DRM_I810_OV0FLIP 0x0b 20830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DRM_I810_MC 0x0c 20930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DRM_I810_RSTATUS 0x0d 21030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DRM_I810_FLIP 0x0e 21130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 21230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DRM_IOCTL_I810_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I810_INIT, drm_i810_init_t) 21330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DRM_IOCTL_I810_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_I810_VERTEX, drm_i810_vertex_t) 21430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DRM_IOCTL_I810_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_I810_CLEAR, drm_i810_clear_t) 21530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DRM_IOCTL_I810_FLUSH DRM_IO( DRM_COMMAND_BASE + DRM_I810_FLUSH) 21630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DRM_IOCTL_I810_GETAGE DRM_IO( DRM_COMMAND_BASE + DRM_I810_GETAGE) 21730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DRM_IOCTL_I810_GETBUF DRM_IOWR(DRM_COMMAND_BASE + DRM_I810_GETBUF, drm_i810_dma_t) 21830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DRM_IOCTL_I810_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_I810_SWAP) 21930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DRM_IOCTL_I810_COPY DRM_IOW( DRM_COMMAND_BASE + DRM_I810_COPY, drm_i810_copy_t) 22030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DRM_IOCTL_I810_DOCOPY DRM_IO( DRM_COMMAND_BASE + DRM_I810_DOCOPY) 22130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DRM_IOCTL_I810_OV0INFO DRM_IOR( DRM_COMMAND_BASE + DRM_I810_OV0INFO, drm_i810_overlay_t) 22230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DRM_IOCTL_I810_FSTATUS DRM_IO ( DRM_COMMAND_BASE + DRM_I810_FSTATUS) 22330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DRM_IOCTL_I810_OV0FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I810_OV0FLIP) 22430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DRM_IOCTL_I810_MC DRM_IOW( DRM_COMMAND_BASE + DRM_I810_MC, drm_i810_mc_t) 22530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DRM_IOCTL_I810_RSTATUS DRM_IO ( DRM_COMMAND_BASE + DRM_I810_RSTATUS) 22630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DRM_IOCTL_I810_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I810_FLIP) 22730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 22830692c65c4174412c90e79489e98ab85c1a7412fBen Chengtypedef struct _drm_i810_clear { 22930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng int clear_color; 23030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng int clear_depth; 23130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng int flags; 23230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng} drm_i810_clear_t; 23330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 23430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng/* These may be placeholders if we have more cliprects than 23530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * I810_NR_SAREA_CLIPRECTS. In that case, the client sets discard to 23630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * false, indicating that the buffer will be dispatched again with a 23730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * new set of cliprects. 23830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng */ 23930692c65c4174412c90e79489e98ab85c1a7412fBen Chengtypedef struct _drm_i810_vertex { 24030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng int idx; /* buffer index */ 24130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng int used; /* nr bytes in use */ 24230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng int discard; /* client is finished with the buffer? */ 24330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng} drm_i810_vertex_t; 24430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 24530692c65c4174412c90e79489e98ab85c1a7412fBen Chengtypedef struct _drm_i810_copy_t { 24630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng int idx; /* buffer index */ 24730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng int used; /* nr bytes in use */ 24830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng void *address; /* Address to copy from */ 24930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng} drm_i810_copy_t; 25030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 25130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define PR_TRIANGLES (0x0<<18) 25230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define PR_TRISTRIP_0 (0x1<<18) 25330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define PR_TRISTRIP_1 (0x2<<18) 25430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define PR_TRIFAN (0x3<<18) 25530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define PR_POLYGON (0x4<<18) 25630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define PR_LINES (0x5<<18) 25730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define PR_LINESTRIP (0x6<<18) 25830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define PR_RECTS (0x7<<18) 25930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define PR_MASK (0x7<<18) 26030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 26130692c65c4174412c90e79489e98ab85c1a7412fBen Chengtypedef struct drm_i810_dma { 26230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng void *virtual; 26330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng int request_idx; 26430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng int request_size; 26530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng int granted; 26630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng} drm_i810_dma_t; 26730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 26830692c65c4174412c90e79489e98ab85c1a7412fBen Chengtypedef struct _drm_i810_overlay_t { 26930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int offset; /* Address of the Overlay Regs */ 27030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int physical; 27130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng} drm_i810_overlay_t; 27230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 27330692c65c4174412c90e79489e98ab85c1a7412fBen Chengtypedef struct _drm_i810_mc { 27430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng int idx; /* buffer index */ 27530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng int used; /* nr bytes in use */ 27630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng int num_blocks; /* number of GFXBlocks */ 27730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng int *length; /* List of lengths for GFXBlocks (FUTURE) */ 27830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int last_render; /* Last Render Request */ 27930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng} drm_i810_mc_t; 28030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 28130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#endif /* _I810_DRM_H_ */ 282