Passes.h revision 3fb99a73686c39d9855b3f8881add977af3868cb
1//===-- Passes.h - Target independent code generation passes ----*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines interfaces to access the target independent code generation 11// passes provided by the LLVM backend. 12// 13//===----------------------------------------------------------------------===// 14 15#ifndef LLVM_CODEGEN_PASSES_H 16#define LLVM_CODEGEN_PASSES_H 17 18#include "llvm/Pass.h" 19#include "llvm/Target/TargetMachine.h" 20#include <string> 21 22namespace llvm { 23 24 class FunctionPass; 25 class MachineFunctionPass; 26 class PassInfo; 27 class PassManagerBase; 28 class TargetLowering; 29 class TargetRegisterClass; 30 class raw_ostream; 31} 32 33namespace llvm { 34 35class PassConfigImpl; 36 37/// Target-Independent Code Generator Pass Configuration Options. 38/// 39/// This is an ImmutablePass solely for the purpose of exposing CodeGen options 40/// to the internals of other CodeGen passes. 41class TargetPassConfig : public ImmutablePass { 42public: 43 /// Pseudo Pass IDs. These are defined within TargetPassConfig because they 44 /// are unregistered pass IDs. They are only useful for use with 45 /// TargetPassConfig APIs to identify multiple occurrences of the same pass. 46 /// 47 48 /// EarlyTailDuplicate - A clone of the TailDuplicate pass that runs early 49 /// during codegen, on SSA form. 50 static char EarlyTailDuplicateID; 51 52 /// PostRAMachineLICM - A clone of the LICM pass that runs during late machine 53 /// optimization after regalloc. 54 static char PostRAMachineLICMID; 55 56private: 57 PassManagerBase *PM; 58 59protected: 60 TargetMachine *TM; 61 PassConfigImpl *Impl; // Internal data structures 62 bool Initialized; // Flagged after all passes are configured. 63 64 // Target Pass Options 65 // Targets provide a default setting, user flags override. 66 // 67 bool DisableVerify; 68 69 /// Default setting for -enable-tail-merge on this target. 70 bool EnableTailMerge; 71 72public: 73 TargetPassConfig(TargetMachine *tm, PassManagerBase &pm); 74 // Dummy constructor. 75 TargetPassConfig(); 76 77 virtual ~TargetPassConfig(); 78 79 static char ID; 80 81 /// Get the right type of TargetMachine for this target. 82 template<typename TMC> TMC &getTM() const { 83 return *static_cast<TMC*>(TM); 84 } 85 86 const TargetLowering *getTargetLowering() const { 87 return TM->getTargetLowering(); 88 } 89 90 // 91 void setInitialized() { Initialized = true; } 92 93 CodeGenOpt::Level getOptLevel() const { return TM->getOptLevel(); } 94 95 void setDisableVerify(bool Disable) { setOpt(DisableVerify, Disable); } 96 97 bool getEnableTailMerge() const { return EnableTailMerge; } 98 void setEnableTailMerge(bool Enable) { setOpt(EnableTailMerge, Enable); } 99 100 /// Allow the target to override a specific pass without overriding the pass 101 /// pipeline. When passes are added to the standard pipeline at the 102 /// point where StandardID is expected, add TargetID in its place. 103 void substitutePass(AnalysisID StandardID, AnalysisID TargetID); 104 105 /// Insert InsertedPassID pass after TargetPassID pass. 106 void insertPass(AnalysisID TargetPassID, AnalysisID InsertedPassID); 107 108 /// Allow the target to enable a specific standard pass by default. 109 void enablePass(AnalysisID PassID) { substitutePass(PassID, PassID); } 110 111 /// Allow the target to disable a specific standard pass by default. 112 void disablePass(AnalysisID PassID) { substitutePass(PassID, 0); } 113 114 /// Return the pass substituted for StandardID by the target. 115 /// If no substitution exists, return StandardID. 116 AnalysisID getPassSubstitution(AnalysisID StandardID) const; 117 118 /// Return true if the optimized regalloc pipeline is enabled. 119 bool getOptimizeRegAlloc() const; 120 121 /// Add common target configurable passes that perform LLVM IR to IR 122 /// transforms following machine independent optimization. 123 virtual void addIRPasses(); 124 125 /// Add passes to lower exception handling for the code generator. 126 void addPassesToHandleExceptions(); 127 128 /// Add common passes that perform LLVM IR to IR transforms in preparation for 129 /// instruction selection. 130 virtual void addISelPrepare(); 131 132 /// addInstSelector - This method should install an instruction selector pass, 133 /// which converts from LLVM code to machine instructions. 134 virtual bool addInstSelector() { 135 return true; 136 } 137 138 /// Add the complete, standard set of LLVM CodeGen passes. 139 /// Fully developed targets will not generally override this. 140 virtual void addMachinePasses(); 141 142protected: 143 // Helper to verify the analysis is really immutable. 144 void setOpt(bool &Opt, bool Val); 145 146 /// Methods with trivial inline returns are convenient points in the common 147 /// codegen pass pipeline where targets may insert passes. Methods with 148 /// out-of-line standard implementations are major CodeGen stages called by 149 /// addMachinePasses. Some targets may override major stages when inserting 150 /// passes is insufficient, but maintaining overriden stages is more work. 151 /// 152 153 /// addPreISelPasses - This method should add any "last minute" LLVM->LLVM 154 /// passes (which are run just before instruction selector). 155 virtual bool addPreISel() { 156 return true; 157 } 158 159 /// addMachineSSAOptimization - Add standard passes that optimize machine 160 /// instructions in SSA form. 161 virtual void addMachineSSAOptimization(); 162 163 /// addPreRegAlloc - This method may be implemented by targets that want to 164 /// run passes immediately before register allocation. This should return 165 /// true if -print-machineinstrs should print after these passes. 166 virtual bool addPreRegAlloc() { 167 return false; 168 } 169 170 /// createTargetRegisterAllocator - Create the register allocator pass for 171 /// this target at the current optimization level. 172 virtual FunctionPass *createTargetRegisterAllocator(bool Optimized); 173 174 /// addFastRegAlloc - Add the minimum set of target-independent passes that 175 /// are required for fast register allocation. 176 virtual void addFastRegAlloc(FunctionPass *RegAllocPass); 177 178 /// addOptimizedRegAlloc - Add passes related to register allocation. 179 /// LLVMTargetMachine provides standard regalloc passes for most targets. 180 virtual void addOptimizedRegAlloc(FunctionPass *RegAllocPass); 181 182 /// addPreRewrite - Add passes to the optimized register allocation pipeline 183 /// after register allocation is complete, but before virtual registers are 184 /// rewritten to physical registers. 185 /// 186 /// These passes must preserve VirtRegMap and LiveIntervals, and when running 187 /// after RABasic or RAGreedy, they should take advantage of LiveRegMatrix. 188 /// When these passes run, VirtRegMap contains legal physreg assignments for 189 /// all virtual registers. 190 virtual bool addPreRewrite() { 191 return false; 192 } 193 194 /// addFinalizeRegAlloc - This method may be implemented by targets that want 195 /// to run passes within the regalloc pipeline, immediately after the register 196 /// allocation pass itself. These passes run as soon as virtual regisiters 197 /// have been rewritten to physical registers but before and other postRA 198 /// optimization happens. Targets that have marked instructions for bundling 199 /// must have finalized those bundles by the time these passes have run, 200 /// because subsequent passes are not guaranteed to be bundle-aware. 201 virtual bool addFinalizeRegAlloc() { 202 return false; 203 } 204 205 /// addPostRegAlloc - This method may be implemented by targets that want to 206 /// run passes after register allocation pass pipeline but before 207 /// prolog-epilog insertion. This should return true if -print-machineinstrs 208 /// should print after these passes. 209 virtual bool addPostRegAlloc() { 210 return false; 211 } 212 213 /// Add passes that optimize machine instructions after register allocation. 214 virtual void addMachineLateOptimization(); 215 216 /// addPreSched2 - This method may be implemented by targets that want to 217 /// run passes after prolog-epilog insertion and before the second instruction 218 /// scheduling pass. This should return true if -print-machineinstrs should 219 /// print after these passes. 220 virtual bool addPreSched2() { 221 return false; 222 } 223 224 /// Add standard basic block placement passes. 225 virtual void addBlockPlacement(); 226 227 /// addPreEmitPass - This pass may be implemented by targets that want to run 228 /// passes immediately before machine code is emitted. This should return 229 /// true if -print-machineinstrs should print out the code after the passes. 230 virtual bool addPreEmitPass() { 231 return false; 232 } 233 234 /// Utilities for targets to add passes to the pass manager. 235 /// 236 237 /// Add a CodeGen pass at this point in the pipeline after checking overrides. 238 /// Return the pass that was added, or zero if no pass was added. 239 AnalysisID addPass(AnalysisID PassID); 240 241 /// Add a pass to the PassManager. 242 void addPass(Pass *P); 243 244 /// addMachinePasses helper to create the target-selected or overriden 245 /// regalloc pass. 246 FunctionPass *createRegAllocPass(bool Optimized); 247 248 /// printAndVerify - Add a pass to dump then verify the machine function, if 249 /// those steps are enabled. 250 /// 251 void printAndVerify(const char *Banner); 252}; 253} // namespace llvm 254 255/// List of target independent CodeGen pass IDs. 256namespace llvm { 257 /// createUnreachableBlockEliminationPass - The LLVM code generator does not 258 /// work well with unreachable basic blocks (what live ranges make sense for a 259 /// block that cannot be reached?). As such, a code generator should either 260 /// not instruction select unreachable blocks, or run this pass as its 261 /// last LLVM modifying pass to clean up blocks that are not reachable from 262 /// the entry block. 263 FunctionPass *createUnreachableBlockEliminationPass(); 264 265 /// MachineFunctionPrinter pass - This pass prints out the machine function to 266 /// the given stream as a debugging tool. 267 MachineFunctionPass * 268 createMachineFunctionPrinterPass(raw_ostream &OS, 269 const std::string &Banner =""); 270 271 /// MachineLoopInfo - This pass is a loop analysis pass. 272 extern char &MachineLoopInfoID; 273 274 /// MachineLoopRanges - This pass is an on-demand loop coverage analysis. 275 extern char &MachineLoopRangesID; 276 277 /// MachineDominators - This pass is a machine dominators analysis pass. 278 extern char &MachineDominatorsID; 279 280 /// EdgeBundles analysis - Bundle machine CFG edges. 281 extern char &EdgeBundlesID; 282 283 /// LiveVariables pass - This pass computes the set of blocks in which each 284 /// variable is life and sets machine operand kill flags. 285 extern char &LiveVariablesID; 286 287 /// PHIElimination - This pass eliminates machine instruction PHI nodes 288 /// by inserting copy instructions. This destroys SSA information, but is the 289 /// desired input for some register allocators. This pass is "required" by 290 /// these register allocator like this: AU.addRequiredID(PHIEliminationID); 291 extern char &PHIEliminationID; 292 293 /// StrongPHIElimination - This pass eliminates machine instruction PHI 294 /// nodes by inserting copy instructions. This destroys SSA information, but 295 /// is the desired input for some register allocators. This pass is 296 /// "required" by these register allocator like this: 297 /// AU.addRequiredID(PHIEliminationID); 298 /// This pass is still in development 299 extern char &StrongPHIEliminationID; 300 301 /// LiveStacks pass. An analysis keeping track of the liveness of stack slots. 302 extern char &LiveStacksID; 303 304 /// TwoAddressInstruction - This pass reduces two-address instructions to 305 /// use two operands. This destroys SSA information but it is desired by 306 /// register allocators. 307 extern char &TwoAddressInstructionPassID; 308 309 /// ProcessImpicitDefs pass - This pass removes IMPLICIT_DEFs. 310 extern char &ProcessImplicitDefsID; 311 312 /// RegisterCoalescer - This pass merges live ranges to eliminate copies. 313 extern char &RegisterCoalescerID; 314 315 /// MachineScheduler - This pass schedules machine instructions. 316 extern char &MachineSchedulerID; 317 318 /// SpillPlacement analysis. Suggest optimal placement of spill code between 319 /// basic blocks. 320 extern char &SpillPlacementID; 321 322 /// VirtRegRewriter pass. Rewrite virtual registers to physical registers as 323 /// assigned in VirtRegMap. 324 extern char &VirtRegRewriterID; 325 326 /// UnreachableMachineBlockElimination - This pass removes unreachable 327 /// machine basic blocks. 328 extern char &UnreachableMachineBlockElimID; 329 330 /// DeadMachineInstructionElim - This pass removes dead machine instructions. 331 extern char &DeadMachineInstructionElimID; 332 333 /// FastRegisterAllocation Pass - This pass register allocates as fast as 334 /// possible. It is best suited for debug code where live ranges are short. 335 /// 336 FunctionPass *createFastRegisterAllocator(); 337 338 /// BasicRegisterAllocation Pass - This pass implements a degenerate global 339 /// register allocator using the basic regalloc framework. 340 /// 341 FunctionPass *createBasicRegisterAllocator(); 342 343 /// Greedy register allocation pass - This pass implements a global register 344 /// allocator for optimized builds. 345 /// 346 FunctionPass *createGreedyRegisterAllocator(); 347 348 /// PBQPRegisterAllocation Pass - This pass implements the Partitioned Boolean 349 /// Quadratic Prograaming (PBQP) based register allocator. 350 /// 351 FunctionPass *createDefaultPBQPRegisterAllocator(); 352 353 /// PrologEpilogCodeInserter - This pass inserts prolog and epilog code, 354 /// and eliminates abstract frame references. 355 extern char &PrologEpilogCodeInserterID; 356 357 /// ExpandPostRAPseudos - This pass expands pseudo instructions after 358 /// register allocation. 359 extern char &ExpandPostRAPseudosID; 360 361 /// createPostRAScheduler - This pass performs post register allocation 362 /// scheduling. 363 extern char &PostRASchedulerID; 364 365 /// BranchFolding - This pass performs machine code CFG based 366 /// optimizations to delete branches to branches, eliminate branches to 367 /// successor blocks (creating fall throughs), and eliminating branches over 368 /// branches. 369 extern char &BranchFolderPassID; 370 371 /// MachineFunctionPrinterPass - This pass prints out MachineInstr's. 372 extern char &MachineFunctionPrinterPassID; 373 374 /// TailDuplicate - Duplicate blocks with unconditional branches 375 /// into tails of their predecessors. 376 extern char &TailDuplicateID; 377 378 /// IfConverter - This pass performs machine code if conversion. 379 extern char &IfConverterID; 380 381 /// MachineBlockPlacement - This pass places basic blocks based on branch 382 /// probabilities. 383 extern char &MachineBlockPlacementID; 384 385 /// MachineBlockPlacementStats - This pass collects statistics about the 386 /// basic block placement using branch probabilities and block frequency 387 /// information. 388 extern char &MachineBlockPlacementStatsID; 389 390 /// Code Placement - This pass optimize code placement and aligns loop 391 /// headers to target specific alignment boundary. 392 extern char &CodePlacementOptID; 393 394 /// GCLowering Pass - Performs target-independent LLVM IR transformations for 395 /// highly portable strategies. 396 /// 397 FunctionPass *createGCLoweringPass(); 398 399 /// GCMachineCodeAnalysis - Target-independent pass to mark safe points 400 /// in machine code. Must be added very late during code generation, just 401 /// prior to output, and importantly after all CFG transformations (such as 402 /// branch folding). 403 extern char &GCMachineCodeAnalysisID; 404 405 /// Deleter Pass - Releases GC metadata. 406 /// 407 FunctionPass *createGCInfoDeleter(); 408 409 /// Creates a pass to print GC metadata. 410 /// 411 FunctionPass *createGCInfoPrinter(raw_ostream &OS); 412 413 /// MachineCSE - This pass performs global CSE on machine instructions. 414 extern char &MachineCSEID; 415 416 /// MachineLICM - This pass performs LICM on machine instructions. 417 extern char &MachineLICMID; 418 419 /// MachineSinking - This pass performs sinking on machine instructions. 420 extern char &MachineSinkingID; 421 422 /// MachineCopyPropagation - This pass performs copy propagation on 423 /// machine instructions. 424 extern char &MachineCopyPropagationID; 425 426 /// PeepholeOptimizer - This pass performs peephole optimizations - 427 /// like extension and comparison eliminations. 428 extern char &PeepholeOptimizerID; 429 430 /// OptimizePHIs - This pass optimizes machine instruction PHIs 431 /// to take advantage of opportunities created during DAG legalization. 432 extern char &OptimizePHIsID; 433 434 /// StackSlotColoring - This pass performs stack slot coloring. 435 extern char &StackSlotColoringID; 436 437 /// createStackProtectorPass - This pass adds stack protectors to functions. 438 /// 439 FunctionPass *createStackProtectorPass(const TargetLowering *tli); 440 441 /// createMachineVerifierPass - This pass verifies cenerated machine code 442 /// instructions for correctness. 443 /// 444 FunctionPass *createMachineVerifierPass(const char *Banner = 0); 445 446 /// createDwarfEHPass - This pass mulches exception handling code into a form 447 /// adapted to code generation. Required if using dwarf exception handling. 448 FunctionPass *createDwarfEHPass(const TargetMachine *tm); 449 450 /// createSjLjEHPreparePass - This pass adapts exception handling code to use 451 /// the GCC-style builtin setjmp/longjmp (sjlj) to handling EH control flow. 452 /// 453 FunctionPass *createSjLjEHPreparePass(const TargetLowering *tli); 454 455 /// LocalStackSlotAllocation - This pass assigns local frame indices to stack 456 /// slots relative to one another and allocates base registers to access them 457 /// when it is estimated by the target to be out of range of normal frame 458 /// pointer or stack pointer index addressing. 459 extern char &LocalStackSlotAllocationID; 460 461 /// ExpandISelPseudos - This pass expands pseudo-instructions. 462 extern char &ExpandISelPseudosID; 463 464 /// createExecutionDependencyFixPass - This pass fixes execution time 465 /// problems with dependent instructions, such as switching execution 466 /// domains to match. 467 /// 468 /// The pass will examine instructions using and defining registers in RC. 469 /// 470 FunctionPass *createExecutionDependencyFixPass(const TargetRegisterClass *RC); 471 472 /// UnpackMachineBundles - This pass unpack machine instruction bundles. 473 extern char &UnpackMachineBundlesID; 474 475 /// FinalizeMachineBundles - This pass finalize machine instruction 476 /// bundles (created earlier, e.g. during pre-RA scheduling). 477 extern char &FinalizeMachineBundlesID; 478 479} // End llvm namespace 480 481#endif 482