LiveIntervalAnalysis.cpp revision 20aa474f8fbebde588edc101b90e834df28ce4ce
1//===-- LiveIntervalAnalysis.cpp - Live Interval Analysis -----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the LiveInterval analysis pass which is used 11// by the Linear Scan Register allocator. This pass linearizes the 12// basic blocks of the function in DFS order and uses the 13// LiveVariables pass to conservatively compute live intervals for 14// each virtual and physical register. 15// 16//===----------------------------------------------------------------------===// 17 18#define DEBUG_TYPE "liveintervals" 19#include "LiveIntervalAnalysis.h" 20#include "llvm/Value.h" 21#include "llvm/Analysis/LoopInfo.h" 22#include "llvm/CodeGen/LiveVariables.h" 23#include "llvm/CodeGen/MachineFrameInfo.h" 24#include "llvm/CodeGen/MachineInstr.h" 25#include "llvm/CodeGen/Passes.h" 26#include "llvm/CodeGen/SSARegMap.h" 27#include "llvm/Target/MRegisterInfo.h" 28#include "llvm/Target/TargetInstrInfo.h" 29#include "llvm/Target/TargetMachine.h" 30#include "llvm/Support/CommandLine.h" 31#include "llvm/Support/Debug.h" 32#include "llvm/ADT/Statistic.h" 33#include "llvm/ADT/STLExtras.h" 34#include "VirtRegMap.h" 35#include <cmath> 36#include <algorithm> 37 38using namespace llvm; 39 40namespace { 41 RegisterAnalysis<LiveIntervals> X("liveintervals", "Live Interval Analysis"); 42 43 Statistic<> numIntervals 44 ("liveintervals", "Number of original intervals"); 45 46 Statistic<> numIntervalsAfter 47 ("liveintervals", "Number of intervals after coalescing"); 48 49 Statistic<> numJoins 50 ("liveintervals", "Number of interval joins performed"); 51 52 Statistic<> numPeep 53 ("liveintervals", "Number of identity moves eliminated after coalescing"); 54 55 Statistic<> numFolded 56 ("liveintervals", "Number of loads/stores folded into instructions"); 57 58 cl::opt<bool> 59 EnableJoining("join-liveintervals", 60 cl::desc("Join compatible live intervals"), 61 cl::init(true)); 62}; 63 64void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const 65{ 66 AU.addPreserved<LiveVariables>(); 67 AU.addRequired<LiveVariables>(); 68 AU.addPreservedID(PHIEliminationID); 69 AU.addRequiredID(PHIEliminationID); 70 AU.addRequiredID(TwoAddressInstructionPassID); 71 AU.addRequired<LoopInfo>(); 72 MachineFunctionPass::getAnalysisUsage(AU); 73} 74 75void LiveIntervals::releaseMemory() 76{ 77 mi2iMap_.clear(); 78 i2miMap_.clear(); 79 r2iMap_.clear(); 80 r2rMap_.clear(); 81} 82 83 84/// runOnMachineFunction - Register allocate the whole function 85/// 86bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) { 87 mf_ = &fn; 88 tm_ = &fn.getTarget(); 89 mri_ = tm_->getRegisterInfo(); 90 lv_ = &getAnalysis<LiveVariables>(); 91 allocatableRegs_ = mri_->getAllocatableSet(fn); 92 93 // number MachineInstrs 94 unsigned miIndex = 0; 95 for (MachineFunction::iterator mbb = mf_->begin(), mbbEnd = mf_->end(); 96 mbb != mbbEnd; ++mbb) 97 for (MachineBasicBlock::iterator mi = mbb->begin(), miEnd = mbb->end(); 98 mi != miEnd; ++mi) { 99 bool inserted = mi2iMap_.insert(std::make_pair(mi, miIndex)).second; 100 assert(inserted && "multiple MachineInstr -> index mappings"); 101 i2miMap_.push_back(mi); 102 miIndex += InstrSlots::NUM; 103 } 104 105 computeIntervals(); 106 107 numIntervals += getNumIntervals(); 108 109#if 1 110 DEBUG(std::cerr << "********** INTERVALS **********\n"); 111 DEBUG(for (iterator I = begin(), E = end(); I != E; ++I) 112 std::cerr << I->second << "\n"); 113#endif 114 115 // join intervals if requested 116 if (EnableJoining) joinIntervals(); 117 118 numIntervalsAfter += getNumIntervals(); 119 120 // perform a final pass over the instructions and compute spill 121 // weights, coalesce virtual registers and remove identity moves 122 const LoopInfo& loopInfo = getAnalysis<LoopInfo>(); 123 const TargetInstrInfo& tii = *tm_->getInstrInfo(); 124 125 for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end(); 126 mbbi != mbbe; ++mbbi) { 127 MachineBasicBlock* mbb = mbbi; 128 unsigned loopDepth = loopInfo.getLoopDepth(mbb->getBasicBlock()); 129 130 for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end(); 131 mii != mie; ) { 132 // if the move will be an identity move delete it 133 unsigned srcReg, dstReg, RegRep; 134 if (tii.isMoveInstr(*mii, srcReg, dstReg) && 135 (RegRep = rep(srcReg)) == rep(dstReg)) { 136 // remove from def list 137 LiveInterval &interval = getOrCreateInterval(RegRep); 138 // remove index -> MachineInstr and 139 // MachineInstr -> index mappings 140 Mi2IndexMap::iterator mi2i = mi2iMap_.find(mii); 141 if (mi2i != mi2iMap_.end()) { 142 i2miMap_[mi2i->second/InstrSlots::NUM] = 0; 143 mi2iMap_.erase(mi2i); 144 } 145 mii = mbbi->erase(mii); 146 ++numPeep; 147 } 148 else { 149 for (unsigned i = 0; i < mii->getNumOperands(); ++i) { 150 const MachineOperand& mop = mii->getOperand(i); 151 if (mop.isRegister() && mop.getReg() && 152 MRegisterInfo::isVirtualRegister(mop.getReg())) { 153 // replace register with representative register 154 unsigned reg = rep(mop.getReg()); 155 mii->SetMachineOperandReg(i, reg); 156 157 LiveInterval &RegInt = getInterval(reg); 158 RegInt.weight += 159 (mop.isUse() + mop.isDef()) * pow(10.0F, loopDepth); 160 } 161 } 162 ++mii; 163 } 164 } 165 } 166 167 DEBUG(std::cerr << "********** INTERVALS **********\n"); 168 DEBUG (for (iterator I = begin(), E = end(); I != E; ++I) 169 std::cerr << I->second << "\n"); 170 DEBUG(std::cerr << "********** MACHINEINSTRS **********\n"); 171 DEBUG( 172 for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end(); 173 mbbi != mbbe; ++mbbi) { 174 std::cerr << ((Value*)mbbi->getBasicBlock())->getName() << ":\n"; 175 for (MachineBasicBlock::iterator mii = mbbi->begin(), 176 mie = mbbi->end(); mii != mie; ++mii) { 177 std::cerr << getInstructionIndex(mii) << '\t'; 178 mii->print(std::cerr, tm_); 179 } 180 }); 181 182 return true; 183} 184 185std::vector<LiveInterval*> LiveIntervals::addIntervalsForSpills( 186 const LiveInterval& li, 187 VirtRegMap& vrm, 188 int slot) 189{ 190 // since this is called after the analysis is done we don't know if 191 // LiveVariables is available 192 lv_ = getAnalysisToUpdate<LiveVariables>(); 193 194 std::vector<LiveInterval*> added; 195 196 assert(li.weight != HUGE_VAL && 197 "attempt to spill already spilled interval!"); 198 199 DEBUG(std::cerr << "\t\t\t\tadding intervals for spills for interval: " 200 << li << '\n'); 201 202 const TargetRegisterClass* rc = mf_->getSSARegMap()->getRegClass(li.reg); 203 204 for (LiveInterval::Ranges::const_iterator 205 i = li.ranges.begin(), e = li.ranges.end(); i != e; ++i) { 206 unsigned index = getBaseIndex(i->start); 207 unsigned end = getBaseIndex(i->end-1) + InstrSlots::NUM; 208 for (; index != end; index += InstrSlots::NUM) { 209 // skip deleted instructions 210 while (index != end && !getInstructionFromIndex(index)) 211 index += InstrSlots::NUM; 212 if (index == end) break; 213 214 MachineBasicBlock::iterator mi = getInstructionFromIndex(index); 215 216 for_operand: 217 for (unsigned i = 0; i != mi->getNumOperands(); ++i) { 218 MachineOperand& mop = mi->getOperand(i); 219 if (mop.isRegister() && mop.getReg() == li.reg) { 220 if (MachineInstr* fmi = mri_->foldMemoryOperand(mi, i, slot)) { 221 if (lv_) 222 lv_->instructionChanged(mi, fmi); 223 vrm.virtFolded(li.reg, mi, fmi); 224 mi2iMap_.erase(mi); 225 i2miMap_[index/InstrSlots::NUM] = fmi; 226 mi2iMap_[fmi] = index; 227 MachineBasicBlock& mbb = *mi->getParent(); 228 mi = mbb.insert(mbb.erase(mi), fmi); 229 ++numFolded; 230 goto for_operand; 231 } 232 else { 233 // This is tricky. We need to add information in 234 // the interval about the spill code so we have to 235 // use our extra load/store slots. 236 // 237 // If we have a use we are going to have a load so 238 // we start the interval from the load slot 239 // onwards. Otherwise we start from the def slot. 240 unsigned start = (mop.isUse() ? 241 getLoadIndex(index) : 242 getDefIndex(index)); 243 // If we have a def we are going to have a store 244 // right after it so we end the interval after the 245 // use of the next instruction. Otherwise we end 246 // after the use of this instruction. 247 unsigned end = 1 + (mop.isDef() ? 248 getStoreIndex(index) : 249 getUseIndex(index)); 250 251 // create a new register for this spill 252 unsigned nReg = mf_->getSSARegMap()->createVirtualRegister(rc); 253 mi->SetMachineOperandReg(i, nReg); 254 vrm.grow(); 255 vrm.assignVirt2StackSlot(nReg, slot); 256 LiveInterval& nI = getOrCreateInterval(nReg); 257 assert(nI.empty()); 258 // the spill weight is now infinity as it 259 // cannot be spilled again 260 nI.weight = HUGE_VAL; 261 LiveRange LR(start, end, nI.getNextValue()); 262 DEBUG(std::cerr << " +" << LR); 263 nI.addRange(LR); 264 added.push_back(&nI); 265 // update live variables if it is available 266 if (lv_) 267 lv_->addVirtualRegisterKilled(nReg, mi); 268 DEBUG(std::cerr << "\t\t\t\tadded new interval: " << nI << '\n'); 269 } 270 } 271 } 272 } 273 } 274 275 return added; 276} 277 278void LiveIntervals::printRegName(unsigned reg) const 279{ 280 if (MRegisterInfo::isPhysicalRegister(reg)) 281 std::cerr << mri_->getName(reg); 282 else 283 std::cerr << "%reg" << reg; 284} 285 286void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock* mbb, 287 MachineBasicBlock::iterator mi, 288 LiveInterval& interval) 289{ 290 DEBUG(std::cerr << "\t\tregister: "; printRegName(interval.reg)); 291 LiveVariables::VarInfo& vi = lv_->getVarInfo(interval.reg); 292 293 // Virtual registers may be defined multiple times (due to phi 294 // elimination and 2-addr elimination). Much of what we do only has to be 295 // done once for the vreg. We use an empty interval to detect the first 296 // time we see a vreg. 297 if (interval.empty()) { 298 // Get the Idx of the defining instructions. 299 unsigned defIndex = getDefIndex(getInstructionIndex(mi)); 300 301 unsigned ValNum = interval.getNextValue(); 302 assert(ValNum == 0 && "First value in interval is not 0?"); 303 ValNum = 0; // Clue in the optimizer. 304 305 // Loop over all of the blocks that the vreg is defined in. There are 306 // two cases we have to handle here. The most common case is a vreg 307 // whose lifetime is contained within a basic block. In this case there 308 // will be a single kill, in MBB, which comes after the definition. 309 if (vi.Kills.size() == 1 && vi.Kills[0]->getParent() == mbb) { 310 // FIXME: what about dead vars? 311 unsigned killIdx; 312 if (vi.Kills[0] != mi) 313 killIdx = getUseIndex(getInstructionIndex(vi.Kills[0]))+1; 314 else 315 killIdx = defIndex+1; 316 317 // If the kill happens after the definition, we have an intra-block 318 // live range. 319 if (killIdx > defIndex) { 320 assert(vi.AliveBlocks.empty() && 321 "Shouldn't be alive across any blocks!"); 322 LiveRange LR(defIndex, killIdx, ValNum); 323 interval.addRange(LR); 324 DEBUG(std::cerr << " +" << LR << "\n"); 325 return; 326 } 327 } 328 329 // The other case we handle is when a virtual register lives to the end 330 // of the defining block, potentially live across some blocks, then is 331 // live into some number of blocks, but gets killed. Start by adding a 332 // range that goes from this definition to the end of the defining block. 333 LiveRange NewLR(defIndex, 334 getInstructionIndex(&mbb->back()) + InstrSlots::NUM, 335 ValNum); 336 DEBUG(std::cerr << " +" << NewLR); 337 interval.addRange(NewLR); 338 339 // Iterate over all of the blocks that the variable is completely 340 // live in, adding [insrtIndex(begin), instrIndex(end)+4) to the 341 // live interval. 342 for (unsigned i = 0, e = vi.AliveBlocks.size(); i != e; ++i) { 343 if (vi.AliveBlocks[i]) { 344 MachineBasicBlock* mbb = mf_->getBlockNumbered(i); 345 if (!mbb->empty()) { 346 LiveRange LR(getInstructionIndex(&mbb->front()), 347 getInstructionIndex(&mbb->back()) + InstrSlots::NUM, 348 ValNum); 349 interval.addRange(LR); 350 DEBUG(std::cerr << " +" << LR); 351 } 352 } 353 } 354 355 // Finally, this virtual register is live from the start of any killing 356 // block to the 'use' slot of the killing instruction. 357 for (unsigned i = 0, e = vi.Kills.size(); i != e; ++i) { 358 MachineInstr *Kill = vi.Kills[i]; 359 LiveRange LR(getInstructionIndex(Kill->getParent()->begin()), 360 getUseIndex(getInstructionIndex(Kill))+1, 361 ValNum); 362 interval.addRange(LR); 363 DEBUG(std::cerr << " +" << LR); 364 } 365 366 } else { 367 // If this is the second time we see a virtual register definition, it 368 // must be due to phi elimination or two addr elimination. If this is 369 // the result of two address elimination, then the vreg is the first 370 // operand, and is a def-and-use. 371 if (mi->getOperand(0).isRegister() && 372 mi->getOperand(0).getReg() == interval.reg && 373 mi->getOperand(0).isDef() && mi->getOperand(0).isUse()) { 374 // If this is a two-address definition, then we have already processed 375 // the live range. The only problem is that we didn't realize there 376 // are actually two values in the live interval. Because of this we 377 // need to take the LiveRegion that defines this register and split it 378 // into two values. 379 unsigned DefIndex = getDefIndex(getInstructionIndex(vi.DefInst)); 380 unsigned RedefIndex = getDefIndex(getInstructionIndex(mi)); 381 382 // Delete the initial value, which should be short and continuous, 383 // becuase the 2-addr copy must be in the same MBB as the redef. 384 interval.removeRange(DefIndex, RedefIndex); 385 386 LiveRange LR(DefIndex, RedefIndex, interval.getNextValue()); 387 DEBUG(std::cerr << " replace range with " << LR); 388 interval.addRange(LR); 389 390 // If this redefinition is dead, we need to add a dummy unit live 391 // range covering the def slot. 392 for (LiveVariables::killed_iterator KI = lv_->dead_begin(mi), 393 E = lv_->dead_end(mi); KI != E; ++KI) 394 if (KI->second == interval.reg) { 395 interval.addRange(LiveRange(RedefIndex, RedefIndex+1, 0)); 396 break; 397 } 398 399 DEBUG(std::cerr << "RESULT: " << interval); 400 401 } else { 402 // Otherwise, this must be because of phi elimination. If this is the 403 // first redefinition of the vreg that we have seen, go back and change 404 // the live range in the PHI block to be a different value number. 405 if (interval.containsOneValue()) { 406 assert(vi.Kills.size() == 1 && 407 "PHI elimination vreg should have one kill, the PHI itself!"); 408 409 // Remove the old range that we now know has an incorrect number. 410 MachineInstr *Killer = vi.Kills[0]; 411 unsigned Start = getInstructionIndex(Killer->getParent()->begin()); 412 unsigned End = getUseIndex(getInstructionIndex(Killer))+1; 413 DEBUG(std::cerr << "Removing [" << Start << "," << End << "] from: " 414 << interval << "\n"); 415 interval.removeRange(Start, End); 416 DEBUG(std::cerr << "RESULT: " << interval); 417 418 // Replace the interval with one of a NEW value number. 419 LiveRange LR(Start, End, interval.getNextValue()); 420 DEBUG(std::cerr << " replace range with " << LR); 421 interval.addRange(LR); 422 DEBUG(std::cerr << "RESULT: " << interval); 423 } 424 425 // In the case of PHI elimination, each variable definition is only 426 // live until the end of the block. We've already taken care of the 427 // rest of the live range. 428 unsigned defIndex = getDefIndex(getInstructionIndex(mi)); 429 LiveRange LR(defIndex, 430 getInstructionIndex(&mbb->back()) + InstrSlots::NUM, 431 interval.getNextValue()); 432 interval.addRange(LR); 433 DEBUG(std::cerr << " +" << LR); 434 } 435 } 436 437 DEBUG(std::cerr << '\n'); 438} 439 440void LiveIntervals::handlePhysicalRegisterDef(MachineBasicBlock *MBB, 441 MachineBasicBlock::iterator mi, 442 LiveInterval& interval) 443{ 444 // A physical register cannot be live across basic block, so its 445 // lifetime must end somewhere in its defining basic block. 446 DEBUG(std::cerr << "\t\tregister: "; printRegName(interval.reg)); 447 typedef LiveVariables::killed_iterator KillIter; 448 449 unsigned baseIndex = getInstructionIndex(mi); 450 unsigned start = getDefIndex(baseIndex); 451 unsigned end = start; 452 453 // If it is not used after definition, it is considered dead at 454 // the instruction defining it. Hence its interval is: 455 // [defSlot(def), defSlot(def)+1) 456 for (KillIter ki = lv_->dead_begin(mi), ke = lv_->dead_end(mi); 457 ki != ke; ++ki) { 458 if (interval.reg == ki->second) { 459 DEBUG(std::cerr << " dead"); 460 end = getDefIndex(start) + 1; 461 goto exit; 462 } 463 } 464 465 // If it is not dead on definition, it must be killed by a 466 // subsequent instruction. Hence its interval is: 467 // [defSlot(def), useSlot(kill)+1) 468 while (true) { 469 ++mi; 470 assert(mi != MBB->end() && "physreg was not killed in defining block!"); 471 baseIndex += InstrSlots::NUM; 472 for (KillIter ki = lv_->killed_begin(mi), ke = lv_->killed_end(mi); 473 ki != ke; ++ki) { 474 if (interval.reg == ki->second) { 475 DEBUG(std::cerr << " killed"); 476 end = getUseIndex(baseIndex) + 1; 477 goto exit; 478 } 479 } 480 } 481 482exit: 483 assert(start < end && "did not find end of interval?"); 484 LiveRange LR(start, end, interval.getNextValue()); 485 interval.addRange(LR); 486 DEBUG(std::cerr << " +" << LR << '\n'); 487} 488 489void LiveIntervals::handleRegisterDef(MachineBasicBlock *MBB, 490 MachineBasicBlock::iterator MI, 491 unsigned reg) { 492 if (MRegisterInfo::isVirtualRegister(reg)) 493 handleVirtualRegisterDef(MBB, MI, getOrCreateInterval(reg)); 494 else if (allocatableRegs_[reg]) { 495 handlePhysicalRegisterDef(MBB, MI, getOrCreateInterval(reg)); 496 for (const unsigned* AS = mri_->getAliasSet(reg); *AS; ++AS) 497 handlePhysicalRegisterDef(MBB, MI, getOrCreateInterval(*AS)); 498 } 499} 500 501/// computeIntervals - computes the live intervals for virtual 502/// registers. for some ordering of the machine instructions [1,N] a 503/// live interval is an interval [i, j) where 1 <= i <= j < N for 504/// which a variable is live 505void LiveIntervals::computeIntervals() 506{ 507 DEBUG(std::cerr << "********** COMPUTING LIVE INTERVALS **********\n"); 508 DEBUG(std::cerr << "********** Function: " 509 << ((Value*)mf_->getFunction())->getName() << '\n'); 510 511 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end(); 512 I != E; ++I) { 513 MachineBasicBlock* mbb = I; 514 DEBUG(std::cerr << ((Value*)mbb->getBasicBlock())->getName() << ":\n"); 515 516 for (MachineBasicBlock::iterator mi = mbb->begin(), miEnd = mbb->end(); 517 mi != miEnd; ++mi) { 518 const TargetInstrDescriptor& tid = 519 tm_->getInstrInfo()->get(mi->getOpcode()); 520 DEBUG(std::cerr << getInstructionIndex(mi) << "\t"; 521 mi->print(std::cerr, tm_)); 522 523 // handle implicit defs 524 for (const unsigned* id = tid.ImplicitDefs; *id; ++id) 525 handleRegisterDef(mbb, mi, *id); 526 527 // handle explicit defs 528 for (int i = mi->getNumOperands() - 1; i >= 0; --i) { 529 MachineOperand& mop = mi->getOperand(i); 530 // handle register defs - build intervals 531 if (mop.isRegister() && mop.getReg() && mop.isDef()) 532 handleRegisterDef(mbb, mi, mop.getReg()); 533 } 534 } 535 } 536} 537 538void LiveIntervals::joinIntervalsInMachineBB(MachineBasicBlock *MBB) { 539 DEBUG(std::cerr << ((Value*)MBB->getBasicBlock())->getName() << ":\n"); 540 const TargetInstrInfo &TII = *tm_->getInstrInfo(); 541 542 for (MachineBasicBlock::iterator mi = MBB->begin(), mie = MBB->end(); 543 mi != mie; ++mi) { 544 DEBUG(std::cerr << getInstructionIndex(mi) << '\t' << *mi); 545 546 // we only join virtual registers with allocatable 547 // physical registers since we do not have liveness information 548 // on not allocatable physical registers 549 unsigned regA, regB; 550 if (TII.isMoveInstr(*mi, regA, regB) && 551 (MRegisterInfo::isVirtualRegister(regA) || allocatableRegs_[regA]) && 552 (MRegisterInfo::isVirtualRegister(regB) || allocatableRegs_[regB])) { 553 554 // Get representative registers. 555 regA = rep(regA); 556 regB = rep(regB); 557 558 // If they are already joined we continue. 559 if (regA == regB) 560 continue; 561 562 // If they are both physical registers, we cannot join them. 563 if (MRegisterInfo::isPhysicalRegister(regA) && 564 MRegisterInfo::isPhysicalRegister(regB)) 565 continue; 566 567 // If they are not of the same register class, we cannot join them. 568 if (differingRegisterClasses(regA, regB)) 569 continue; 570 571 LiveInterval &IntA = getInterval(regA); 572 LiveInterval &IntB = getInterval(regB); 573 assert(IntA.reg == regA && IntB.reg == regB && 574 "Register mapping is horribly broken!"); 575 576 DEBUG(std::cerr << "\t\tInspecting " << IntA << " and " << IntB << ": "); 577 578 // If two intervals contain a single value and are joined by a copy, it 579 // does not matter if the intervals overlap, they can always be joined. 580 bool TriviallyJoinable = 581 IntA.containsOneValue() && IntB.containsOneValue(); 582 583 unsigned MIDefIdx = getDefIndex(getInstructionIndex(mi)); 584 if ((TriviallyJoinable || IntB.joinable(IntA, MIDefIdx)) && 585 !overlapsAliases(&IntA, &IntB)) { 586 IntB.join(IntA, MIDefIdx); 587 588 if (!MRegisterInfo::isPhysicalRegister(regA)) { 589 r2iMap_.erase(regA); 590 r2rMap_[regA] = regB; 591 } else { 592 // Otherwise merge the data structures the other way so we don't lose 593 // the physreg information. 594 r2rMap_[regB] = regA; 595 IntB.reg = regA; 596 IntA.swap(IntB); 597 r2iMap_.erase(regB); 598 } 599 DEBUG(std::cerr << "Joined. Result = " << IntB << "\n"); 600 ++numJoins; 601 } else { 602 DEBUG(std::cerr << "Interference!\n"); 603 } 604 } 605 } 606} 607 608namespace { 609 // DepthMBBCompare - Comparison predicate that sort first based on the loop 610 // depth of the basic block (the unsigned), and then on the MBB number. 611 struct DepthMBBCompare { 612 typedef std::pair<unsigned, MachineBasicBlock*> DepthMBBPair; 613 bool operator()(const DepthMBBPair &LHS, const DepthMBBPair &RHS) const { 614 if (LHS.first > RHS.first) return true; // Deeper loops first 615 return LHS.first == RHS.first && 616 LHS.second->getNumber() < RHS.second->getNumber(); 617 } 618 }; 619} 620 621void LiveIntervals::joinIntervals() { 622 DEBUG(std::cerr << "********** JOINING INTERVALS ***********\n"); 623 624 const LoopInfo &LI = getAnalysis<LoopInfo>(); 625 if (LI.begin() == LI.end()) { 626 // If there are no loops in the function, join intervals in function order. 627 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end(); 628 I != E; ++I) 629 joinIntervalsInMachineBB(I); 630 } else { 631 // Otherwise, join intervals in inner loops before other intervals. 632 // Unfortunately we can't just iterate over loop hierarchy here because 633 // there may be more MBB's than BB's. Collect MBB's for sorting. 634 std::vector<std::pair<unsigned, MachineBasicBlock*> > MBBs; 635 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end(); 636 I != E; ++I) 637 MBBs.push_back(std::make_pair(LI.getLoopDepth(I->getBasicBlock()), I)); 638 639 // Sort by loop depth. 640 std::sort(MBBs.begin(), MBBs.end(), DepthMBBCompare()); 641 642 // Finally, join intervals in loop nest order. 643 for (unsigned i = 0, e = MBBs.size(); i != e; ++i) 644 joinIntervalsInMachineBB(MBBs[i].second); 645 } 646 647 DEBUG(std::cerr << "*** Register mapping ***\n"); 648 DEBUG(for (std::map<unsigned, unsigned>::iterator I = r2rMap_.begin(), 649 E = r2rMap_.end(); I != E; ++I) 650 std::cerr << " reg " << I->first << " -> reg " << I->second << "\n";); 651} 652 653/// Return true if the two specified registers belong to different register 654/// classes. The registers may be either phys or virt regs. 655bool LiveIntervals::differingRegisterClasses(unsigned RegA, 656 unsigned RegB) const { 657 const TargetRegisterClass *RegClass; 658 659 // Get the register classes for the first reg. 660 if (MRegisterInfo::isVirtualRegister(RegA)) 661 RegClass = mf_->getSSARegMap()->getRegClass(RegA); 662 else 663 RegClass = mri_->getRegClass(RegA); 664 665 // Compare against the regclass for the second reg. 666 if (MRegisterInfo::isVirtualRegister(RegB)) 667 return RegClass != mf_->getSSARegMap()->getRegClass(RegB); 668 else 669 return !RegClass->contains(RegB); 670} 671 672bool LiveIntervals::overlapsAliases(const LiveInterval *LHS, 673 const LiveInterval *RHS) const { 674 if (!MRegisterInfo::isPhysicalRegister(LHS->reg)) { 675 if (!MRegisterInfo::isPhysicalRegister(RHS->reg)) 676 return false; // vreg-vreg merge has no aliases! 677 std::swap(LHS, RHS); 678 } 679 680 assert(MRegisterInfo::isPhysicalRegister(LHS->reg) && 681 MRegisterInfo::isVirtualRegister(RHS->reg) && 682 "first interval must describe a physical register"); 683 684 for (const unsigned *AS = mri_->getAliasSet(LHS->reg); *AS; ++AS) 685 if (RHS->overlaps(getInterval(*AS))) 686 return true; 687 688 return false; 689} 690 691LiveInterval LiveIntervals::createInterval(unsigned reg) { 692 float Weight = MRegisterInfo::isPhysicalRegister(reg) ? HUGE_VAL :0.0F; 693 return LiveInterval(reg, Weight); 694} 695