LiveIntervalAnalysis.cpp revision 438f7bc67cf235ccee7e6f7ac7f4ae2186eb8020
1//===-- LiveIntervalAnalysis.cpp - Live Interval Analysis -----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the LiveInterval analysis pass which is used 11// by the Linear Scan Register allocator. This pass linearizes the 12// basic blocks of the function in DFS order and uses the 13// LiveVariables pass to conservatively compute live intervals for 14// each virtual and physical register. 15// 16//===----------------------------------------------------------------------===// 17 18#define DEBUG_TYPE "liveintervals" 19#include "llvm/CodeGen/LiveIntervalAnalysis.h" 20#include "VirtRegMap.h" 21#include "llvm/Value.h" 22#include "llvm/Analysis/LoopInfo.h" 23#include "llvm/CodeGen/LiveVariables.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/MachineInstr.h" 26#include "llvm/CodeGen/Passes.h" 27#include "llvm/CodeGen/SSARegMap.h" 28#include "llvm/Target/MRegisterInfo.h" 29#include "llvm/Target/TargetInstrInfo.h" 30#include "llvm/Target/TargetMachine.h" 31#include "llvm/Support/CommandLine.h" 32#include "llvm/Support/Debug.h" 33#include "llvm/ADT/Statistic.h" 34#include "llvm/ADT/STLExtras.h" 35#include <algorithm> 36#include <iostream> 37using namespace llvm; 38 39namespace { 40 RegisterPass<LiveIntervals> X("liveintervals", "Live Interval Analysis"); 41 42 static Statistic<> numIntervals 43 ("liveintervals", "Number of original intervals"); 44 45 static Statistic<> numIntervalsAfter 46 ("liveintervals", "Number of intervals after coalescing"); 47 48 static Statistic<> numJoins 49 ("liveintervals", "Number of interval joins performed"); 50 51 static Statistic<> numPeep 52 ("liveintervals", "Number of identity moves eliminated after coalescing"); 53 54 static Statistic<> numFolded 55 ("liveintervals", "Number of loads/stores folded into instructions"); 56 57 static cl::opt<bool> 58 EnableJoining("join-liveintervals", 59 cl::desc("Coallesce copies (default=true)"), 60 cl::init(true)); 61} 62 63void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const { 64 AU.addRequired<LiveVariables>(); 65 AU.addPreservedID(PHIEliminationID); 66 AU.addRequiredID(PHIEliminationID); 67 AU.addRequiredID(TwoAddressInstructionPassID); 68 AU.addRequired<LoopInfo>(); 69 MachineFunctionPass::getAnalysisUsage(AU); 70} 71 72void LiveIntervals::releaseMemory() { 73 mi2iMap_.clear(); 74 i2miMap_.clear(); 75 r2iMap_.clear(); 76 r2rMap_.clear(); 77} 78 79 80static bool isZeroLengthInterval(LiveInterval *li) { 81 for (LiveInterval::Ranges::const_iterator 82 i = li->ranges.begin(), e = li->ranges.end(); i != e; ++i) 83 if (i->end - i->start > LiveIntervals::InstrSlots::NUM) 84 return false; 85 return true; 86} 87 88 89/// runOnMachineFunction - Register allocate the whole function 90/// 91bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) { 92 mf_ = &fn; 93 tm_ = &fn.getTarget(); 94 mri_ = tm_->getRegisterInfo(); 95 tii_ = tm_->getInstrInfo(); 96 lv_ = &getAnalysis<LiveVariables>(); 97 allocatableRegs_ = mri_->getAllocatableSet(fn); 98 r2rMap_.grow(mf_->getSSARegMap()->getLastVirtReg()); 99 100 // If this function has any live ins, insert a dummy instruction at the 101 // beginning of the function that we will pretend "defines" the values. This 102 // is to make the interval analysis simpler by providing a number. 103 if (fn.livein_begin() != fn.livein_end()) { 104 unsigned FirstLiveIn = fn.livein_begin()->first; 105 106 // Find a reg class that contains this live in. 107 const TargetRegisterClass *RC = 0; 108 for (MRegisterInfo::regclass_iterator RCI = mri_->regclass_begin(), 109 E = mri_->regclass_end(); RCI != E; ++RCI) 110 if ((*RCI)->contains(FirstLiveIn)) { 111 RC = *RCI; 112 break; 113 } 114 115 MachineInstr *OldFirstMI = fn.begin()->begin(); 116 mri_->copyRegToReg(*fn.begin(), fn.begin()->begin(), 117 FirstLiveIn, FirstLiveIn, RC); 118 assert(OldFirstMI != fn.begin()->begin() && 119 "copyRetToReg didn't insert anything!"); 120 } 121 122 // Number MachineInstrs and MachineBasicBlocks. 123 // Initialize MBB indexes to a sentinal. 124 MBB2IdxMap.resize(mf_->getNumBlockIDs(), ~0U); 125 126 unsigned MIIndex = 0; 127 for (MachineFunction::iterator MBB = mf_->begin(), E = mf_->end(); 128 MBB != E; ++MBB) { 129 // Set the MBB2IdxMap entry for this MBB. 130 MBB2IdxMap[MBB->getNumber()] = MIIndex; 131 132 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); 133 I != E; ++I) { 134 bool inserted = mi2iMap_.insert(std::make_pair(I, MIIndex)).second; 135 assert(inserted && "multiple MachineInstr -> index mappings"); 136 i2miMap_.push_back(I); 137 MIIndex += InstrSlots::NUM; 138 } 139 } 140 141 // Note intervals due to live-in values. 142 if (fn.livein_begin() != fn.livein_end()) { 143 MachineBasicBlock *Entry = fn.begin(); 144 for (MachineFunction::livein_iterator I = fn.livein_begin(), 145 E = fn.livein_end(); I != E; ++I) { 146 handlePhysicalRegisterDef(Entry, Entry->begin(), 0, 147 getOrCreateInterval(I->first), 0); 148 for (const unsigned* AS = mri_->getAliasSet(I->first); *AS; ++AS) 149 handlePhysicalRegisterDef(Entry, Entry->begin(), 0, 150 getOrCreateInterval(*AS), 0); 151 } 152 } 153 154 computeIntervals(); 155 156 numIntervals += getNumIntervals(); 157 158 DEBUG(std::cerr << "********** INTERVALS **********\n"; 159 for (iterator I = begin(), E = end(); I != E; ++I) { 160 I->second.print(std::cerr, mri_); 161 std::cerr << "\n"; 162 }); 163 164 // Join (coallesce) intervals if requested. 165 if (EnableJoining) joinIntervals(); 166 167 numIntervalsAfter += getNumIntervals(); 168 169 170 // perform a final pass over the instructions and compute spill 171 // weights, coalesce virtual registers and remove identity moves. 172 const LoopInfo &loopInfo = getAnalysis<LoopInfo>(); 173 174 for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end(); 175 mbbi != mbbe; ++mbbi) { 176 MachineBasicBlock* mbb = mbbi; 177 unsigned loopDepth = loopInfo.getLoopDepth(mbb->getBasicBlock()); 178 179 for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end(); 180 mii != mie; ) { 181 // if the move will be an identity move delete it 182 unsigned srcReg, dstReg, RegRep; 183 if (tii_->isMoveInstr(*mii, srcReg, dstReg) && 184 (RegRep = rep(srcReg)) == rep(dstReg)) { 185 // remove from def list 186 getOrCreateInterval(RegRep); 187 RemoveMachineInstrFromMaps(mii); 188 mii = mbbi->erase(mii); 189 ++numPeep; 190 } 191 else { 192 for (unsigned i = 0, e = mii->getNumOperands(); i != e; ++i) { 193 const MachineOperand &mop = mii->getOperand(i); 194 if (mop.isRegister() && mop.getReg() && 195 MRegisterInfo::isVirtualRegister(mop.getReg())) { 196 // replace register with representative register 197 unsigned reg = rep(mop.getReg()); 198 mii->getOperand(i).setReg(reg); 199 200 LiveInterval &RegInt = getInterval(reg); 201 RegInt.weight += 202 (mop.isUse() + mop.isDef()) * pow(10.0F, (int)loopDepth); 203 } 204 } 205 ++mii; 206 } 207 } 208 } 209 210 211 for (iterator I = begin(), E = end(); I != E; ++I) { 212 LiveInterval &LI = I->second; 213 if (MRegisterInfo::isVirtualRegister(LI.reg)) { 214 // If the live interval length is essentially zero, i.e. in every live 215 // range the use follows def immediately, it doesn't make sense to spill 216 // it and hope it will be easier to allocate for this li. 217 if (isZeroLengthInterval(&LI)) 218 LI.weight = HUGE_VALF; 219 220 // Divide the weight of the interval by its size. This encourages 221 // spilling of intervals that are large and have few uses, and 222 // discourages spilling of small intervals with many uses. 223 unsigned Size = 0; 224 for (LiveInterval::iterator II = LI.begin(), E = LI.end(); II != E;++II) 225 Size += II->end - II->start; 226 227 LI.weight /= Size; 228 } 229 } 230 231 DEBUG(dump()); 232 return true; 233} 234 235/// print - Implement the dump method. 236void LiveIntervals::print(std::ostream &O, const Module* ) const { 237 O << "********** INTERVALS **********\n"; 238 for (const_iterator I = begin(), E = end(); I != E; ++I) { 239 I->second.print(std::cerr, mri_); 240 std::cerr << "\n"; 241 } 242 243 O << "********** MACHINEINSTRS **********\n"; 244 for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end(); 245 mbbi != mbbe; ++mbbi) { 246 O << ((Value*)mbbi->getBasicBlock())->getName() << ":\n"; 247 for (MachineBasicBlock::iterator mii = mbbi->begin(), 248 mie = mbbi->end(); mii != mie; ++mii) { 249 O << getInstructionIndex(mii) << '\t' << *mii; 250 } 251 } 252} 253 254std::vector<LiveInterval*> LiveIntervals:: 255addIntervalsForSpills(const LiveInterval &li, VirtRegMap &vrm, int slot) { 256 // since this is called after the analysis is done we don't know if 257 // LiveVariables is available 258 lv_ = getAnalysisToUpdate<LiveVariables>(); 259 260 std::vector<LiveInterval*> added; 261 262 assert(li.weight != HUGE_VALF && 263 "attempt to spill already spilled interval!"); 264 265 DEBUG(std::cerr << "\t\t\t\tadding intervals for spills for interval: "; 266 li.print(std::cerr, mri_); std::cerr << '\n'); 267 268 const TargetRegisterClass* rc = mf_->getSSARegMap()->getRegClass(li.reg); 269 270 for (LiveInterval::Ranges::const_iterator 271 i = li.ranges.begin(), e = li.ranges.end(); i != e; ++i) { 272 unsigned index = getBaseIndex(i->start); 273 unsigned end = getBaseIndex(i->end-1) + InstrSlots::NUM; 274 for (; index != end; index += InstrSlots::NUM) { 275 // skip deleted instructions 276 while (index != end && !getInstructionFromIndex(index)) 277 index += InstrSlots::NUM; 278 if (index == end) break; 279 280 MachineInstr *MI = getInstructionFromIndex(index); 281 282 RestartInstruction: 283 for (unsigned i = 0; i != MI->getNumOperands(); ++i) { 284 MachineOperand& mop = MI->getOperand(i); 285 if (mop.isRegister() && mop.getReg() == li.reg) { 286 if (MachineInstr *fmi = mri_->foldMemoryOperand(MI, i, slot)) { 287 // Attempt to fold the memory reference into the instruction. If we 288 // can do this, we don't need to insert spill code. 289 if (lv_) 290 lv_->instructionChanged(MI, fmi); 291 MachineBasicBlock &MBB = *MI->getParent(); 292 vrm.virtFolded(li.reg, MI, i, fmi); 293 mi2iMap_.erase(MI); 294 i2miMap_[index/InstrSlots::NUM] = fmi; 295 mi2iMap_[fmi] = index; 296 MI = MBB.insert(MBB.erase(MI), fmi); 297 ++numFolded; 298 // Folding the load/store can completely change the instruction in 299 // unpredictable ways, rescan it from the beginning. 300 goto RestartInstruction; 301 } else { 302 // Create a new virtual register for the spill interval. 303 unsigned NewVReg = mf_->getSSARegMap()->createVirtualRegister(rc); 304 305 // Scan all of the operands of this instruction rewriting operands 306 // to use NewVReg instead of li.reg as appropriate. We do this for 307 // two reasons: 308 // 309 // 1. If the instr reads the same spilled vreg multiple times, we 310 // want to reuse the NewVReg. 311 // 2. If the instr is a two-addr instruction, we are required to 312 // keep the src/dst regs pinned. 313 // 314 // Keep track of whether we replace a use and/or def so that we can 315 // create the spill interval with the appropriate range. 316 mop.setReg(NewVReg); 317 318 bool HasUse = mop.isUse(); 319 bool HasDef = mop.isDef(); 320 for (unsigned j = i+1, e = MI->getNumOperands(); j != e; ++j) { 321 if (MI->getOperand(j).isReg() && 322 MI->getOperand(j).getReg() == li.reg) { 323 MI->getOperand(j).setReg(NewVReg); 324 HasUse |= MI->getOperand(j).isUse(); 325 HasDef |= MI->getOperand(j).isDef(); 326 } 327 } 328 329 // create a new register for this spill 330 vrm.grow(); 331 vrm.assignVirt2StackSlot(NewVReg, slot); 332 LiveInterval &nI = getOrCreateInterval(NewVReg); 333 assert(nI.empty()); 334 335 // the spill weight is now infinity as it 336 // cannot be spilled again 337 nI.weight = HUGE_VALF; 338 339 if (HasUse) { 340 LiveRange LR(getLoadIndex(index), getUseIndex(index), 341 nI.getNextValue(~0U, 0)); 342 DEBUG(std::cerr << " +" << LR); 343 nI.addRange(LR); 344 } 345 if (HasDef) { 346 LiveRange LR(getDefIndex(index), getStoreIndex(index), 347 nI.getNextValue(~0U, 0)); 348 DEBUG(std::cerr << " +" << LR); 349 nI.addRange(LR); 350 } 351 352 added.push_back(&nI); 353 354 // update live variables if it is available 355 if (lv_) 356 lv_->addVirtualRegisterKilled(NewVReg, MI); 357 358 DEBUG(std::cerr << "\t\t\t\tadded new interval: "; 359 nI.print(std::cerr, mri_); std::cerr << '\n'); 360 } 361 } 362 } 363 } 364 } 365 366 return added; 367} 368 369void LiveIntervals::printRegName(unsigned reg) const { 370 if (MRegisterInfo::isPhysicalRegister(reg)) 371 std::cerr << mri_->getName(reg); 372 else 373 std::cerr << "%reg" << reg; 374} 375 376/// isReDefinedByTwoAddr - Returns true if the Reg re-definition is due to 377/// two addr elimination. 378static bool isReDefinedByTwoAddr(MachineInstr *MI, unsigned Reg, 379 const TargetInstrInfo *TII) { 380 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 381 MachineOperand &MO1 = MI->getOperand(i); 382 if (MO1.isRegister() && MO1.isDef() && MO1.getReg() == Reg) { 383 for (unsigned j = i+1; j < e; ++j) { 384 MachineOperand &MO2 = MI->getOperand(j); 385 if (MO2.isRegister() && MO2.isUse() && MO2.getReg() == Reg && 386 TII->getOperandConstraint(MI->getOpcode(), j, 387 TargetInstrInfo::TIED_TO) == (int)i) 388 return true; 389 } 390 } 391 } 392 return false; 393} 394 395void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb, 396 MachineBasicBlock::iterator mi, 397 unsigned MIIdx, 398 LiveInterval &interval) { 399 DEBUG(std::cerr << "\t\tregister: "; printRegName(interval.reg)); 400 LiveVariables::VarInfo& vi = lv_->getVarInfo(interval.reg); 401 402 // Virtual registers may be defined multiple times (due to phi 403 // elimination and 2-addr elimination). Much of what we do only has to be 404 // done once for the vreg. We use an empty interval to detect the first 405 // time we see a vreg. 406 if (interval.empty()) { 407 // Get the Idx of the defining instructions. 408 unsigned defIndex = getDefIndex(MIIdx); 409 410 unsigned ValNum; 411 unsigned SrcReg, DstReg; 412 if (!tii_->isMoveInstr(*mi, SrcReg, DstReg)) 413 ValNum = interval.getNextValue(~0U, 0); 414 else 415 ValNum = interval.getNextValue(defIndex, SrcReg); 416 417 assert(ValNum == 0 && "First value in interval is not 0?"); 418 ValNum = 0; // Clue in the optimizer. 419 420 // Loop over all of the blocks that the vreg is defined in. There are 421 // two cases we have to handle here. The most common case is a vreg 422 // whose lifetime is contained within a basic block. In this case there 423 // will be a single kill, in MBB, which comes after the definition. 424 if (vi.Kills.size() == 1 && vi.Kills[0]->getParent() == mbb) { 425 // FIXME: what about dead vars? 426 unsigned killIdx; 427 if (vi.Kills[0] != mi) 428 killIdx = getUseIndex(getInstructionIndex(vi.Kills[0]))+1; 429 else 430 killIdx = defIndex+1; 431 432 // If the kill happens after the definition, we have an intra-block 433 // live range. 434 if (killIdx > defIndex) { 435 assert(vi.AliveBlocks.empty() && 436 "Shouldn't be alive across any blocks!"); 437 LiveRange LR(defIndex, killIdx, ValNum); 438 interval.addRange(LR); 439 DEBUG(std::cerr << " +" << LR << "\n"); 440 return; 441 } 442 } 443 444 // The other case we handle is when a virtual register lives to the end 445 // of the defining block, potentially live across some blocks, then is 446 // live into some number of blocks, but gets killed. Start by adding a 447 // range that goes from this definition to the end of the defining block. 448 LiveRange NewLR(defIndex, 449 getInstructionIndex(&mbb->back()) + InstrSlots::NUM, 450 ValNum); 451 DEBUG(std::cerr << " +" << NewLR); 452 interval.addRange(NewLR); 453 454 // Iterate over all of the blocks that the variable is completely 455 // live in, adding [insrtIndex(begin), instrIndex(end)+4) to the 456 // live interval. 457 for (unsigned i = 0, e = vi.AliveBlocks.size(); i != e; ++i) { 458 if (vi.AliveBlocks[i]) { 459 MachineBasicBlock *MBB = mf_->getBlockNumbered(i); 460 if (!MBB->empty()) { 461 LiveRange LR(getMBBStartIdx(i), 462 getInstructionIndex(&MBB->back()) + InstrSlots::NUM, 463 ValNum); 464 interval.addRange(LR); 465 DEBUG(std::cerr << " +" << LR); 466 } 467 } 468 } 469 470 // Finally, this virtual register is live from the start of any killing 471 // block to the 'use' slot of the killing instruction. 472 for (unsigned i = 0, e = vi.Kills.size(); i != e; ++i) { 473 MachineInstr *Kill = vi.Kills[i]; 474 LiveRange LR(getMBBStartIdx(Kill->getParent()), 475 getUseIndex(getInstructionIndex(Kill))+1, 476 ValNum); 477 interval.addRange(LR); 478 DEBUG(std::cerr << " +" << LR); 479 } 480 481 } else { 482 // If this is the second time we see a virtual register definition, it 483 // must be due to phi elimination or two addr elimination. If this is 484 // the result of two address elimination, then the vreg is one of the 485 // def-and-use register operand. 486 if (isReDefinedByTwoAddr(mi, interval.reg, tii_)) { 487 // If this is a two-address definition, then we have already processed 488 // the live range. The only problem is that we didn't realize there 489 // are actually two values in the live interval. Because of this we 490 // need to take the LiveRegion that defines this register and split it 491 // into two values. 492 unsigned DefIndex = getDefIndex(getInstructionIndex(vi.DefInst)); 493 unsigned RedefIndex = getDefIndex(MIIdx); 494 495 // Delete the initial value, which should be short and continuous, 496 // because the 2-addr copy must be in the same MBB as the redef. 497 interval.removeRange(DefIndex, RedefIndex); 498 499 // Two-address vregs should always only be redefined once. This means 500 // that at this point, there should be exactly one value number in it. 501 assert(interval.containsOneValue() && "Unexpected 2-addr liveint!"); 502 503 // The new value number (#1) is defined by the instruction we claimed 504 // defined value #0. 505 unsigned ValNo = interval.getNextValue(0, 0); 506 interval.setValueNumberInfo(1, interval.getValNumInfo(0)); 507 508 // Value#0 is now defined by the 2-addr instruction. 509 interval.setValueNumberInfo(0, std::make_pair(~0U, 0U)); 510 511 // Add the new live interval which replaces the range for the input copy. 512 LiveRange LR(DefIndex, RedefIndex, ValNo); 513 DEBUG(std::cerr << " replace range with " << LR); 514 interval.addRange(LR); 515 516 // If this redefinition is dead, we need to add a dummy unit live 517 // range covering the def slot. 518 if (lv_->RegisterDefIsDead(mi, interval.reg)) 519 interval.addRange(LiveRange(RedefIndex, RedefIndex+1, 0)); 520 521 DEBUG(std::cerr << "RESULT: "; interval.print(std::cerr, mri_)); 522 523 } else { 524 // Otherwise, this must be because of phi elimination. If this is the 525 // first redefinition of the vreg that we have seen, go back and change 526 // the live range in the PHI block to be a different value number. 527 if (interval.containsOneValue()) { 528 assert(vi.Kills.size() == 1 && 529 "PHI elimination vreg should have one kill, the PHI itself!"); 530 531 // Remove the old range that we now know has an incorrect number. 532 MachineInstr *Killer = vi.Kills[0]; 533 unsigned Start = getMBBStartIdx(Killer->getParent()); 534 unsigned End = getUseIndex(getInstructionIndex(Killer))+1; 535 DEBUG(std::cerr << "Removing [" << Start << "," << End << "] from: "; 536 interval.print(std::cerr, mri_); std::cerr << "\n"); 537 interval.removeRange(Start, End); 538 DEBUG(std::cerr << "RESULT: "; interval.print(std::cerr, mri_)); 539 540 // Replace the interval with one of a NEW value number. Note that this 541 // value number isn't actually defined by an instruction, weird huh? :) 542 LiveRange LR(Start, End, interval.getNextValue(~0U, 0)); 543 DEBUG(std::cerr << " replace range with " << LR); 544 interval.addRange(LR); 545 DEBUG(std::cerr << "RESULT: "; interval.print(std::cerr, mri_)); 546 } 547 548 // In the case of PHI elimination, each variable definition is only 549 // live until the end of the block. We've already taken care of the 550 // rest of the live range. 551 unsigned defIndex = getDefIndex(MIIdx); 552 553 unsigned ValNum; 554 unsigned SrcReg, DstReg; 555 if (!tii_->isMoveInstr(*mi, SrcReg, DstReg)) 556 ValNum = interval.getNextValue(~0U, 0); 557 else 558 ValNum = interval.getNextValue(defIndex, SrcReg); 559 560 LiveRange LR(defIndex, 561 getInstructionIndex(&mbb->back()) + InstrSlots::NUM, ValNum); 562 interval.addRange(LR); 563 DEBUG(std::cerr << " +" << LR); 564 } 565 } 566 567 DEBUG(std::cerr << '\n'); 568} 569 570void LiveIntervals::handlePhysicalRegisterDef(MachineBasicBlock *MBB, 571 MachineBasicBlock::iterator mi, 572 unsigned MIIdx, 573 LiveInterval &interval, 574 unsigned SrcReg) { 575 // A physical register cannot be live across basic block, so its 576 // lifetime must end somewhere in its defining basic block. 577 DEBUG(std::cerr << "\t\tregister: "; printRegName(interval.reg)); 578 typedef LiveVariables::killed_iterator KillIter; 579 580 unsigned baseIndex = MIIdx; 581 unsigned start = getDefIndex(baseIndex); 582 unsigned end = start; 583 584 // If it is not used after definition, it is considered dead at 585 // the instruction defining it. Hence its interval is: 586 // [defSlot(def), defSlot(def)+1) 587 if (lv_->RegisterDefIsDead(mi, interval.reg)) { 588 DEBUG(std::cerr << " dead"); 589 end = getDefIndex(start) + 1; 590 goto exit; 591 } 592 593 // If it is not dead on definition, it must be killed by a 594 // subsequent instruction. Hence its interval is: 595 // [defSlot(def), useSlot(kill)+1) 596 while (++mi != MBB->end()) { 597 baseIndex += InstrSlots::NUM; 598 if (lv_->KillsRegister(mi, interval.reg)) { 599 DEBUG(std::cerr << " killed"); 600 end = getUseIndex(baseIndex) + 1; 601 goto exit; 602 } 603 } 604 605 // The only case we should have a dead physreg here without a killing or 606 // instruction where we know it's dead is if it is live-in to the function 607 // and never used. 608 assert(!SrcReg && "physreg was not killed in defining block!"); 609 end = getDefIndex(start) + 1; // It's dead. 610 611exit: 612 assert(start < end && "did not find end of interval?"); 613 614 LiveRange LR(start, end, interval.getNextValue(SrcReg != 0 ? start : ~0U, 615 SrcReg)); 616 interval.addRange(LR); 617 DEBUG(std::cerr << " +" << LR << '\n'); 618} 619 620void LiveIntervals::handleRegisterDef(MachineBasicBlock *MBB, 621 MachineBasicBlock::iterator MI, 622 unsigned MIIdx, 623 unsigned reg) { 624 if (MRegisterInfo::isVirtualRegister(reg)) 625 handleVirtualRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(reg)); 626 else if (allocatableRegs_[reg]) { 627 unsigned SrcReg, DstReg; 628 if (!tii_->isMoveInstr(*MI, SrcReg, DstReg)) 629 SrcReg = 0; 630 handlePhysicalRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(reg), SrcReg); 631 for (const unsigned* AS = mri_->getAliasSet(reg); *AS; ++AS) 632 handlePhysicalRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(*AS), 0); 633 } 634} 635 636/// computeIntervals - computes the live intervals for virtual 637/// registers. for some ordering of the machine instructions [1,N] a 638/// live interval is an interval [i, j) where 1 <= i <= j < N for 639/// which a variable is live 640void LiveIntervals::computeIntervals() { 641 DEBUG(std::cerr << "********** COMPUTING LIVE INTERVALS **********\n"); 642 DEBUG(std::cerr << "********** Function: " 643 << ((Value*)mf_->getFunction())->getName() << '\n'); 644 bool IgnoreFirstInstr = mf_->livein_begin() != mf_->livein_end(); 645 646 // Track the index of the current machine instr. 647 unsigned MIIndex = 0; 648 for (MachineFunction::iterator MBBI = mf_->begin(), E = mf_->end(); 649 MBBI != E; ++MBBI) { 650 MachineBasicBlock *MBB = MBBI; 651 DEBUG(std::cerr << ((Value*)MBB->getBasicBlock())->getName() << ":\n"); 652 653 MachineBasicBlock::iterator MI = MBB->begin(), miEnd = MBB->end(); 654 if (IgnoreFirstInstr) { 655 ++MI; 656 IgnoreFirstInstr = false; 657 MIIndex += InstrSlots::NUM; 658 } 659 660 for (; MI != miEnd; ++MI) { 661 DEBUG(std::cerr << MIIndex << "\t" << *MI); 662 663 // Handle defs. 664 for (int i = MI->getNumOperands() - 1; i >= 0; --i) { 665 MachineOperand &MO = MI->getOperand(i); 666 // handle register defs - build intervals 667 if (MO.isRegister() && MO.getReg() && MO.isDef()) 668 handleRegisterDef(MBB, MI, MIIndex, MO.getReg()); 669 } 670 671 MIIndex += InstrSlots::NUM; 672 } 673 } 674} 675 676/// AdjustCopiesBackFrom - We found a non-trivially-coallescable copy with IntA 677/// being the source and IntB being the dest, thus this defines a value number 678/// in IntB. If the source value number (in IntA) is defined by a copy from B, 679/// see if we can merge these two pieces of B into a single value number, 680/// eliminating a copy. For example: 681/// 682/// A3 = B0 683/// ... 684/// B1 = A3 <- this copy 685/// 686/// In this case, B0 can be extended to where the B1 copy lives, allowing the B1 687/// value number to be replaced with B0 (which simplifies the B liveinterval). 688/// 689/// This returns true if an interval was modified. 690/// 691bool LiveIntervals::AdjustCopiesBackFrom(LiveInterval &IntA, LiveInterval &IntB, 692 MachineInstr *CopyMI) { 693 unsigned CopyIdx = getDefIndex(getInstructionIndex(CopyMI)); 694 695 // BValNo is a value number in B that is defined by a copy from A. 'B3' in 696 // the example above. 697 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx); 698 unsigned BValNo = BLR->ValId; 699 700 // Get the location that B is defined at. Two options: either this value has 701 // an unknown definition point or it is defined at CopyIdx. If unknown, we 702 // can't process it. 703 unsigned BValNoDefIdx = IntB.getInstForValNum(BValNo); 704 if (BValNoDefIdx == ~0U) return false; 705 assert(BValNoDefIdx == CopyIdx && 706 "Copy doesn't define the value?"); 707 708 // AValNo is the value number in A that defines the copy, A0 in the example. 709 LiveInterval::iterator AValLR = IntA.FindLiveRangeContaining(CopyIdx-1); 710 unsigned AValNo = AValLR->ValId; 711 712 // If AValNo is defined as a copy from IntB, we can potentially process this. 713 714 // Get the instruction that defines this value number. 715 unsigned SrcReg = IntA.getSrcRegForValNum(AValNo); 716 if (!SrcReg) return false; // Not defined by a copy. 717 718 // If the value number is not defined by a copy instruction, ignore it. 719 720 // If the source register comes from an interval other than IntB, we can't 721 // handle this. 722 if (rep(SrcReg) != IntB.reg) return false; 723 724 // Get the LiveRange in IntB that this value number starts with. 725 unsigned AValNoInstIdx = IntA.getInstForValNum(AValNo); 726 LiveInterval::iterator ValLR = IntB.FindLiveRangeContaining(AValNoInstIdx-1); 727 728 // Make sure that the end of the live range is inside the same block as 729 // CopyMI. 730 MachineInstr *ValLREndInst = getInstructionFromIndex(ValLR->end-1); 731 if (!ValLREndInst || 732 ValLREndInst->getParent() != CopyMI->getParent()) return false; 733 734 // Okay, we now know that ValLR ends in the same block that the CopyMI 735 // live-range starts. If there are no intervening live ranges between them in 736 // IntB, we can merge them. 737 if (ValLR+1 != BLR) return false; 738 739 DEBUG(std::cerr << "\nExtending: "; IntB.print(std::cerr, mri_)); 740 741 // We are about to delete CopyMI, so need to remove it as the 'instruction 742 // that defines this value #'. 743 IntB.setValueNumberInfo(BValNo, std::make_pair(~0U, 0)); 744 745 // Okay, we can merge them. We need to insert a new liverange: 746 // [ValLR.end, BLR.begin) of either value number, then we merge the 747 // two value numbers. 748 unsigned FillerStart = ValLR->end, FillerEnd = BLR->start; 749 IntB.addRange(LiveRange(FillerStart, FillerEnd, BValNo)); 750 751 // If the IntB live range is assigned to a physical register, and if that 752 // physreg has aliases, 753 if (MRegisterInfo::isPhysicalRegister(IntB.reg)) { 754 for (const unsigned *AS = mri_->getAliasSet(IntB.reg); *AS; ++AS) { 755 LiveInterval &AliasLI = getInterval(*AS); 756 AliasLI.addRange(LiveRange(FillerStart, FillerEnd, 757 AliasLI.getNextValue(~0U, 0))); 758 } 759 } 760 761 // Okay, merge "B1" into the same value number as "B0". 762 if (BValNo != ValLR->ValId) 763 IntB.MergeValueNumberInto(BValNo, ValLR->ValId); 764 DEBUG(std::cerr << " result = "; IntB.print(std::cerr, mri_); 765 std::cerr << "\n"); 766 767 // Finally, delete the copy instruction. 768 RemoveMachineInstrFromMaps(CopyMI); 769 CopyMI->eraseFromParent(); 770 ++numPeep; 771 return true; 772} 773 774 775/// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg, 776/// which are the src/dst of the copy instruction CopyMI. This returns true 777/// if the copy was successfully coallesced away, or if it is never possible 778/// to coallesce these this copy, due to register constraints. It returns 779/// false if it is not currently possible to coallesce this interval, but 780/// it may be possible if other things get coallesced. 781bool LiveIntervals::JoinCopy(MachineInstr *CopyMI, 782 unsigned SrcReg, unsigned DstReg) { 783 784 785 DEBUG(std::cerr << getInstructionIndex(CopyMI) << '\t' << *CopyMI); 786 787 // Get representative registers. 788 SrcReg = rep(SrcReg); 789 DstReg = rep(DstReg); 790 791 // If they are already joined we continue. 792 if (SrcReg == DstReg) { 793 DEBUG(std::cerr << "\tCopy already coallesced.\n"); 794 return true; // Not coallescable. 795 } 796 797 // If they are both physical registers, we cannot join them. 798 if (MRegisterInfo::isPhysicalRegister(SrcReg) && 799 MRegisterInfo::isPhysicalRegister(DstReg)) { 800 DEBUG(std::cerr << "\tCan not coallesce physregs.\n"); 801 return true; // Not coallescable. 802 } 803 804 // We only join virtual registers with allocatable physical registers. 805 if (MRegisterInfo::isPhysicalRegister(SrcReg) && !allocatableRegs_[SrcReg]){ 806 DEBUG(std::cerr << "\tSrc reg is unallocatable physreg.\n"); 807 return true; // Not coallescable. 808 } 809 if (MRegisterInfo::isPhysicalRegister(DstReg) && !allocatableRegs_[DstReg]){ 810 DEBUG(std::cerr << "\tDst reg is unallocatable physreg.\n"); 811 return true; // Not coallescable. 812 } 813 814 // If they are not of the same register class, we cannot join them. 815 if (differingRegisterClasses(SrcReg, DstReg)) { 816 DEBUG(std::cerr << "\tSrc/Dest are different register classes.\n"); 817 return true; // Not coallescable. 818 } 819 820 LiveInterval &SrcInt = getInterval(SrcReg); 821 LiveInterval &DestInt = getInterval(DstReg); 822 assert(SrcInt.reg == SrcReg && DestInt.reg == DstReg && 823 "Register mapping is horribly broken!"); 824 825 DEBUG(std::cerr << "\t\tInspecting "; SrcInt.print(std::cerr, mri_); 826 std::cerr << " and "; DestInt.print(std::cerr, mri_); 827 std::cerr << ": "); 828 829 // Okay, attempt to join these two intervals. On failure, this returns false. 830 // Otherwise, if one of the intervals being joined is a physreg, this method 831 // always canonicalizes DestInt to be it. The output "SrcInt" will not have 832 // been modified, so we can use this information below to update aliases. 833 if (!JoinIntervals(DestInt, SrcInt)) { 834 // Coallescing failed. 835 836 // If we can eliminate the copy without merging the live ranges, do so now. 837 if (AdjustCopiesBackFrom(SrcInt, DestInt, CopyMI)) 838 return true; 839 840 // Otherwise, we are unable to join the intervals. 841 DEBUG(std::cerr << "Interference!\n"); 842 return false; 843 } 844 845 bool Swapped = SrcReg == DestInt.reg; 846 if (Swapped) 847 std::swap(SrcReg, DstReg); 848 assert(MRegisterInfo::isVirtualRegister(SrcReg) && 849 "LiveInterval::join didn't work right!"); 850 851 // If we're about to merge live ranges into a physical register live range, 852 // we have to update any aliased register's live ranges to indicate that they 853 // have clobbered values for this range. 854 if (MRegisterInfo::isPhysicalRegister(DstReg)) { 855 for (const unsigned *AS = mri_->getAliasSet(DstReg); *AS; ++AS) 856 getInterval(*AS).MergeInClobberRanges(SrcInt); 857 } 858 859 DEBUG(std::cerr << "\n\t\tJoined. Result = "; DestInt.print(std::cerr, mri_); 860 std::cerr << "\n"); 861 862 // If the intervals were swapped by Join, swap them back so that the register 863 // mapping (in the r2i map) is correct. 864 if (Swapped) SrcInt.swap(DestInt); 865 r2iMap_.erase(SrcReg); 866 r2rMap_[SrcReg] = DstReg; 867 868 // Finally, delete the copy instruction. 869 RemoveMachineInstrFromMaps(CopyMI); 870 CopyMI->eraseFromParent(); 871 ++numPeep; 872 ++numJoins; 873 return true; 874} 875 876/// ComputeUltimateVN - Assuming we are going to join two live intervals, 877/// compute what the resultant value numbers for each value in the input two 878/// ranges will be. This is complicated by copies between the two which can 879/// and will commonly cause multiple value numbers to be merged into one. 880/// 881/// VN is the value number that we're trying to resolve. InstDefiningValue 882/// keeps track of the new InstDefiningValue assignment for the result 883/// LiveInterval. ThisFromOther/OtherFromThis are sets that keep track of 884/// whether a value in this or other is a copy from the opposite set. 885/// ThisValNoAssignments/OtherValNoAssignments keep track of value #'s that have 886/// already been assigned. 887/// 888/// ThisFromOther[x] - If x is defined as a copy from the other interval, this 889/// contains the value number the copy is from. 890/// 891static unsigned ComputeUltimateVN(unsigned VN, 892 SmallVector<std::pair<unsigned, 893 unsigned>, 16> &ValueNumberInfo, 894 SmallVector<int, 16> &ThisFromOther, 895 SmallVector<int, 16> &OtherFromThis, 896 SmallVector<int, 16> &ThisValNoAssignments, 897 SmallVector<int, 16> &OtherValNoAssignments, 898 LiveInterval &ThisLI, LiveInterval &OtherLI) { 899 // If the VN has already been computed, just return it. 900 if (ThisValNoAssignments[VN] >= 0) 901 return ThisValNoAssignments[VN]; 902// assert(ThisValNoAssignments[VN] != -2 && "Cyclic case?"); 903 904 // If this val is not a copy from the other val, then it must be a new value 905 // number in the destination. 906 int OtherValNo = ThisFromOther[VN]; 907 if (OtherValNo == -1) { 908 ValueNumberInfo.push_back(ThisLI.getValNumInfo(VN)); 909 return ThisValNoAssignments[VN] = ValueNumberInfo.size()-1; 910 } 911 912 // Otherwise, this *is* a copy from the RHS. If the other side has already 913 // been computed, return it. 914 if (OtherValNoAssignments[OtherValNo] >= 0) 915 return ThisValNoAssignments[VN] = OtherValNoAssignments[OtherValNo]; 916 917 // Mark this value number as currently being computed, then ask what the 918 // ultimate value # of the other value is. 919 ThisValNoAssignments[VN] = -2; 920 unsigned UltimateVN = 921 ComputeUltimateVN(OtherValNo, ValueNumberInfo, 922 OtherFromThis, ThisFromOther, 923 OtherValNoAssignments, ThisValNoAssignments, 924 OtherLI, ThisLI); 925 return ThisValNoAssignments[VN] = UltimateVN; 926} 927 928static bool InVector(unsigned Val, const SmallVector<unsigned, 8> &V) { 929 return std::find(V.begin(), V.end(), Val) != V.end(); 930} 931 932/// SimpleJoin - Attempt to joint the specified interval into this one. The 933/// caller of this method must guarantee that the RHS only contains a single 934/// value number and that the RHS is not defined by a copy from this 935/// interval. This returns false if the intervals are not joinable, or it 936/// joins them and returns true. 937bool LiveIntervals::SimpleJoin(LiveInterval &LHS, LiveInterval &RHS) { 938 assert(RHS.containsOneValue()); 939 940 // Some number (potentially more than one) value numbers in the current 941 // interval may be defined as copies from the RHS. Scan the overlapping 942 // portions of the LHS and RHS, keeping track of this and looking for 943 // overlapping live ranges that are NOT defined as copies. If these exist, we 944 // cannot coallesce. 945 946 LiveInterval::iterator LHSIt = LHS.begin(), LHSEnd = LHS.end(); 947 LiveInterval::iterator RHSIt = RHS.begin(), RHSEnd = RHS.end(); 948 949 if (LHSIt->start < RHSIt->start) { 950 LHSIt = std::upper_bound(LHSIt, LHSEnd, RHSIt->start); 951 if (LHSIt != LHS.begin()) --LHSIt; 952 } else if (RHSIt->start < LHSIt->start) { 953 RHSIt = std::upper_bound(RHSIt, RHSEnd, LHSIt->start); 954 if (RHSIt != RHS.begin()) --RHSIt; 955 } 956 957 SmallVector<unsigned, 8> EliminatedLHSVals; 958 959 while (1) { 960 // Determine if these live intervals overlap. 961 bool Overlaps = false; 962 if (LHSIt->start <= RHSIt->start) 963 Overlaps = LHSIt->end > RHSIt->start; 964 else 965 Overlaps = RHSIt->end > LHSIt->start; 966 967 // If the live intervals overlap, there are two interesting cases: if the 968 // LHS interval is defined by a copy from the RHS, it's ok and we record 969 // that the LHS value # is the same as the RHS. If it's not, then we cannot 970 // coallesce these live ranges and we bail out. 971 if (Overlaps) { 972 // If we haven't already recorded that this value # is safe, check it. 973 if (!InVector(LHSIt->ValId, EliminatedLHSVals)) { 974 // Copy from the RHS? 975 unsigned SrcReg = LHS.getSrcRegForValNum(LHSIt->ValId); 976 if (rep(SrcReg) != RHS.reg) 977 return false; // Nope, bail out. 978 979 EliminatedLHSVals.push_back(LHSIt->ValId); 980 } 981 982 // We know this entire LHS live range is okay, so skip it now. 983 if (++LHSIt == LHSEnd) break; 984 continue; 985 } 986 987 if (LHSIt->end < RHSIt->end) { 988 if (++LHSIt == LHSEnd) break; 989 } else { 990 // One interesting case to check here. It's possible that we have 991 // something like "X3 = Y" which defines a new value number in the LHS, 992 // and is the last use of this liverange of the RHS. In this case, we 993 // want to notice this copy (so that it gets coallesced away) even though 994 // the live ranges don't actually overlap. 995 if (LHSIt->start == RHSIt->end) { 996 if (InVector(LHSIt->ValId, EliminatedLHSVals)) { 997 // We already know that this value number is going to be merged in 998 // if coallescing succeeds. Just skip the liverange. 999 if (++LHSIt == LHSEnd) break; 1000 } else { 1001 // Otherwise, if this is a copy from the RHS, mark it as being merged 1002 // in. 1003 if (rep(LHS.getSrcRegForValNum(LHSIt->ValId)) == RHS.reg) { 1004 EliminatedLHSVals.push_back(LHSIt->ValId); 1005 1006 // We know this entire LHS live range is okay, so skip it now. 1007 if (++LHSIt == LHSEnd) break; 1008 } 1009 } 1010 } 1011 1012 if (++RHSIt == RHSEnd) break; 1013 } 1014 } 1015 1016 // If we got here, we know that the coallescing will be successful and that 1017 // the value numbers in EliminatedLHSVals will all be merged together. Since 1018 // the most common case is that EliminatedLHSVals has a single number, we 1019 // optimize for it: if there is more than one value, we merge them all into 1020 // the lowest numbered one, then handle the interval as if we were merging 1021 // with one value number. 1022 unsigned LHSValNo; 1023 if (EliminatedLHSVals.size() > 1) { 1024 // Loop through all the equal value numbers merging them into the smallest 1025 // one. 1026 unsigned Smallest = EliminatedLHSVals[0]; 1027 for (unsigned i = 1, e = EliminatedLHSVals.size(); i != e; ++i) { 1028 if (EliminatedLHSVals[i] < Smallest) { 1029 // Merge the current notion of the smallest into the smaller one. 1030 LHS.MergeValueNumberInto(Smallest, EliminatedLHSVals[i]); 1031 Smallest = EliminatedLHSVals[i]; 1032 } else { 1033 // Merge into the smallest. 1034 LHS.MergeValueNumberInto(EliminatedLHSVals[i], Smallest); 1035 } 1036 } 1037 LHSValNo = Smallest; 1038 } else { 1039 assert(!EliminatedLHSVals.empty() && "No copies from the RHS?"); 1040 LHSValNo = EliminatedLHSVals[0]; 1041 } 1042 1043 // Okay, now that there is a single LHS value number that we're merging the 1044 // RHS into, update the value number info for the LHS to indicate that the 1045 // value number is defined where the RHS value number was. 1046 LHS.setValueNumberInfo(LHSValNo, RHS.getValNumInfo(0)); 1047 1048 // Okay, the final step is to loop over the RHS live intervals, adding them to 1049 // the LHS. 1050 LHS.MergeRangesInAsValue(RHS, LHSValNo); 1051 LHS.weight += RHS.weight; 1052 1053 return true; 1054} 1055 1056/// JoinIntervals - Attempt to join these two intervals. On failure, this 1057/// returns false. Otherwise, if one of the intervals being joined is a 1058/// physreg, this method always canonicalizes LHS to be it. The output 1059/// "RHS" will not have been modified, so we can use this information 1060/// below to update aliases. 1061bool LiveIntervals::JoinIntervals(LiveInterval &LHS, LiveInterval &RHS) { 1062 // Compute the final value assignment, assuming that the live ranges can be 1063 // coallesced. 1064 SmallVector<int, 16> LHSValNoAssignments; 1065 SmallVector<int, 16> RHSValNoAssignments; 1066 SmallVector<std::pair<unsigned,unsigned>, 16> ValueNumberInfo; 1067 1068 // Compute ultimate value numbers for the LHS and RHS values. 1069 if (RHS.containsOneValue()) { 1070 // Copies from a liveinterval with a single value are simple to handle and 1071 // very common, handle the special case here. This is important, because 1072 // often RHS is small and LHS is large (e.g. a physreg). 1073 1074 // Find out if the RHS is defined as a copy from some value in the LHS. 1075 int RHSValID = -1; 1076 std::pair<unsigned,unsigned> RHSValNoInfo; 1077 unsigned RHSSrcReg = RHS.getSrcRegForValNum(0); 1078 if ((RHSSrcReg == 0 || rep(RHSSrcReg) != LHS.reg)) { 1079 // If RHS is not defined as a copy from the LHS, we can use simpler and 1080 // faster checks to see if the live ranges are coallescable. This joiner 1081 // can't swap the LHS/RHS intervals though. 1082 if (!MRegisterInfo::isPhysicalRegister(RHS.reg)) { 1083 return SimpleJoin(LHS, RHS); 1084 } else { 1085 RHSValNoInfo = RHS.getValNumInfo(0); 1086 } 1087 } else { 1088 // It was defined as a copy from the LHS, find out what value # it is. 1089 unsigned ValInst = RHS.getInstForValNum(0); 1090 RHSValID = LHS.getLiveRangeContaining(ValInst-1)->ValId; 1091 RHSValNoInfo = LHS.getValNumInfo(RHSValID); 1092 } 1093 1094 LHSValNoAssignments.resize(LHS.getNumValNums(), -1); 1095 RHSValNoAssignments.resize(RHS.getNumValNums(), -1); 1096 ValueNumberInfo.resize(LHS.getNumValNums()); 1097 1098 // Okay, *all* of the values in LHS that are defined as a copy from RHS 1099 // should now get updated. 1100 for (unsigned VN = 0, e = LHS.getNumValNums(); VN != e; ++VN) { 1101 if (unsigned LHSSrcReg = LHS.getSrcRegForValNum(VN)) { 1102 if (rep(LHSSrcReg) != RHS.reg) { 1103 // If this is not a copy from the RHS, its value number will be 1104 // unmodified by the coallescing. 1105 ValueNumberInfo[VN] = LHS.getValNumInfo(VN); 1106 LHSValNoAssignments[VN] = VN; 1107 } else if (RHSValID == -1) { 1108 // Otherwise, it is a copy from the RHS, and we don't already have a 1109 // value# for it. Keep the current value number, but remember it. 1110 LHSValNoAssignments[VN] = RHSValID = VN; 1111 ValueNumberInfo[VN] = RHSValNoInfo; 1112 } else { 1113 // Otherwise, use the specified value #. 1114 LHSValNoAssignments[VN] = RHSValID; 1115 if (VN != (unsigned)RHSValID) 1116 ValueNumberInfo[VN].first = ~1U; 1117 else 1118 ValueNumberInfo[VN] = RHSValNoInfo; 1119 } 1120 } else { 1121 ValueNumberInfo[VN] = LHS.getValNumInfo(VN); 1122 LHSValNoAssignments[VN] = VN; 1123 } 1124 } 1125 1126 assert(RHSValID != -1 && "Didn't find value #?"); 1127 RHSValNoAssignments[0] = RHSValID; 1128 1129 } else { 1130 // Loop over the value numbers of the LHS, seeing if any are defined from 1131 // the RHS. 1132 SmallVector<int, 16> LHSValsDefinedFromRHS; 1133 LHSValsDefinedFromRHS.resize(LHS.getNumValNums(), -1); 1134 for (unsigned VN = 0, e = LHS.getNumValNums(); VN != e; ++VN) { 1135 unsigned ValSrcReg = LHS.getSrcRegForValNum(VN); 1136 if (ValSrcReg == 0) // Src not defined by a copy? 1137 continue; 1138 1139 // DstReg is known to be a register in the LHS interval. If the src is 1140 // from the RHS interval, we can use its value #. 1141 if (rep(ValSrcReg) != RHS.reg) 1142 continue; 1143 1144 // Figure out the value # from the RHS. 1145 unsigned ValInst = LHS.getInstForValNum(VN); 1146 LHSValsDefinedFromRHS[VN] = RHS.getLiveRangeContaining(ValInst-1)->ValId; 1147 } 1148 1149 // Loop over the value numbers of the RHS, seeing if any are defined from 1150 // the LHS. 1151 SmallVector<int, 16> RHSValsDefinedFromLHS; 1152 RHSValsDefinedFromLHS.resize(RHS.getNumValNums(), -1); 1153 for (unsigned VN = 0, e = RHS.getNumValNums(); VN != e; ++VN) { 1154 unsigned ValSrcReg = RHS.getSrcRegForValNum(VN); 1155 if (ValSrcReg == 0) // Src not defined by a copy? 1156 continue; 1157 1158 // DstReg is known to be a register in the RHS interval. If the src is 1159 // from the LHS interval, we can use its value #. 1160 if (rep(ValSrcReg) != LHS.reg) 1161 continue; 1162 1163 // Figure out the value # from the LHS. 1164 unsigned ValInst = RHS.getInstForValNum(VN); 1165 RHSValsDefinedFromLHS[VN] = LHS.getLiveRangeContaining(ValInst-1)->ValId; 1166 } 1167 1168 LHSValNoAssignments.resize(LHS.getNumValNums(), -1); 1169 RHSValNoAssignments.resize(RHS.getNumValNums(), -1); 1170 ValueNumberInfo.reserve(LHS.getNumValNums() + RHS.getNumValNums()); 1171 1172 for (unsigned VN = 0, e = LHS.getNumValNums(); VN != e; ++VN) { 1173 if (LHSValNoAssignments[VN] >= 0 || LHS.getInstForValNum(VN) == ~2U) 1174 continue; 1175 ComputeUltimateVN(VN, ValueNumberInfo, 1176 LHSValsDefinedFromRHS, RHSValsDefinedFromLHS, 1177 LHSValNoAssignments, RHSValNoAssignments, LHS, RHS); 1178 } 1179 for (unsigned VN = 0, e = RHS.getNumValNums(); VN != e; ++VN) { 1180 if (RHSValNoAssignments[VN] >= 0 || RHS.getInstForValNum(VN) == ~2U) 1181 continue; 1182 // If this value number isn't a copy from the LHS, it's a new number. 1183 if (RHSValsDefinedFromLHS[VN] == -1) { 1184 ValueNumberInfo.push_back(RHS.getValNumInfo(VN)); 1185 RHSValNoAssignments[VN] = ValueNumberInfo.size()-1; 1186 continue; 1187 } 1188 1189 ComputeUltimateVN(VN, ValueNumberInfo, 1190 RHSValsDefinedFromLHS, LHSValsDefinedFromRHS, 1191 RHSValNoAssignments, LHSValNoAssignments, RHS, LHS); 1192 } 1193 } 1194 1195 // Armed with the mappings of LHS/RHS values to ultimate values, walk the 1196 // interval lists to see if these intervals are coallescable. 1197 LiveInterval::const_iterator I = LHS.begin(); 1198 LiveInterval::const_iterator IE = LHS.end(); 1199 LiveInterval::const_iterator J = RHS.begin(); 1200 LiveInterval::const_iterator JE = RHS.end(); 1201 1202 // Skip ahead until the first place of potential sharing. 1203 if (I->start < J->start) { 1204 I = std::upper_bound(I, IE, J->start); 1205 if (I != LHS.begin()) --I; 1206 } else if (J->start < I->start) { 1207 J = std::upper_bound(J, JE, I->start); 1208 if (J != RHS.begin()) --J; 1209 } 1210 1211 while (1) { 1212 // Determine if these two live ranges overlap. 1213 bool Overlaps; 1214 if (I->start < J->start) { 1215 Overlaps = I->end > J->start; 1216 } else { 1217 Overlaps = J->end > I->start; 1218 } 1219 1220 // If so, check value # info to determine if they are really different. 1221 if (Overlaps) { 1222 // If the live range overlap will map to the same value number in the 1223 // result liverange, we can still coallesce them. If not, we can't. 1224 if (LHSValNoAssignments[I->ValId] != RHSValNoAssignments[J->ValId]) 1225 return false; 1226 } 1227 1228 if (I->end < J->end) { 1229 ++I; 1230 if (I == IE) break; 1231 } else { 1232 ++J; 1233 if (J == JE) break; 1234 } 1235 } 1236 1237 // If we get here, we know that we can coallesce the live ranges. Ask the 1238 // intervals to coallesce themselves now. 1239 LHS.join(RHS, &LHSValNoAssignments[0], &RHSValNoAssignments[0], 1240 ValueNumberInfo); 1241 return true; 1242} 1243 1244 1245namespace { 1246 // DepthMBBCompare - Comparison predicate that sort first based on the loop 1247 // depth of the basic block (the unsigned), and then on the MBB number. 1248 struct DepthMBBCompare { 1249 typedef std::pair<unsigned, MachineBasicBlock*> DepthMBBPair; 1250 bool operator()(const DepthMBBPair &LHS, const DepthMBBPair &RHS) const { 1251 if (LHS.first > RHS.first) return true; // Deeper loops first 1252 return LHS.first == RHS.first && 1253 LHS.second->getNumber() < RHS.second->getNumber(); 1254 } 1255 }; 1256} 1257 1258 1259void LiveIntervals::CopyCoallesceInMBB(MachineBasicBlock *MBB, 1260 std::vector<CopyRec> &TryAgain) { 1261 DEBUG(std::cerr << ((Value*)MBB->getBasicBlock())->getName() << ":\n"); 1262 1263 for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end(); 1264 MII != E;) { 1265 MachineInstr *Inst = MII++; 1266 1267 // If this isn't a copy, we can't join intervals. 1268 unsigned SrcReg, DstReg; 1269 if (!tii_->isMoveInstr(*Inst, SrcReg, DstReg)) continue; 1270 1271 if (!JoinCopy(Inst, SrcReg, DstReg)) 1272 TryAgain.push_back(getCopyRec(Inst, SrcReg, DstReg)); 1273 } 1274} 1275 1276 1277void LiveIntervals::joinIntervals() { 1278 DEBUG(std::cerr << "********** JOINING INTERVALS ***********\n"); 1279 1280 std::vector<CopyRec> TryAgainList; 1281 1282 const LoopInfo &LI = getAnalysis<LoopInfo>(); 1283 if (LI.begin() == LI.end()) { 1284 // If there are no loops in the function, join intervals in function order. 1285 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end(); 1286 I != E; ++I) 1287 CopyCoallesceInMBB(I, TryAgainList); 1288 } else { 1289 // Otherwise, join intervals in inner loops before other intervals. 1290 // Unfortunately we can't just iterate over loop hierarchy here because 1291 // there may be more MBB's than BB's. Collect MBB's for sorting. 1292 std::vector<std::pair<unsigned, MachineBasicBlock*> > MBBs; 1293 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end(); 1294 I != E; ++I) 1295 MBBs.push_back(std::make_pair(LI.getLoopDepth(I->getBasicBlock()), I)); 1296 1297 // Sort by loop depth. 1298 std::sort(MBBs.begin(), MBBs.end(), DepthMBBCompare()); 1299 1300 // Finally, join intervals in loop nest order. 1301 for (unsigned i = 0, e = MBBs.size(); i != e; ++i) 1302 CopyCoallesceInMBB(MBBs[i].second, TryAgainList); 1303 } 1304 1305 // Joining intervals can allow other intervals to be joined. Iteratively join 1306 // until we make no progress. 1307 bool ProgressMade = true; 1308 while (ProgressMade) { 1309 ProgressMade = false; 1310 1311 for (unsigned i = 0, e = TryAgainList.size(); i != e; ++i) { 1312 CopyRec &TheCopy = TryAgainList[i]; 1313 if (TheCopy.MI && 1314 JoinCopy(TheCopy.MI, TheCopy.SrcReg, TheCopy.DstReg)) { 1315 TheCopy.MI = 0; // Mark this one as done. 1316 ProgressMade = true; 1317 } 1318 } 1319 } 1320 1321 DEBUG(std::cerr << "*** Register mapping ***\n"); 1322 DEBUG(for (int i = 0, e = r2rMap_.size(); i != e; ++i) 1323 if (r2rMap_[i]) { 1324 std::cerr << " reg " << i << " -> "; 1325 printRegName(r2rMap_[i]); 1326 std::cerr << "\n"; 1327 }); 1328} 1329 1330/// Return true if the two specified registers belong to different register 1331/// classes. The registers may be either phys or virt regs. 1332bool LiveIntervals::differingRegisterClasses(unsigned RegA, 1333 unsigned RegB) const { 1334 1335 // Get the register classes for the first reg. 1336 if (MRegisterInfo::isPhysicalRegister(RegA)) { 1337 assert(MRegisterInfo::isVirtualRegister(RegB) && 1338 "Shouldn't consider two physregs!"); 1339 return !mf_->getSSARegMap()->getRegClass(RegB)->contains(RegA); 1340 } 1341 1342 // Compare against the regclass for the second reg. 1343 const TargetRegisterClass *RegClass = mf_->getSSARegMap()->getRegClass(RegA); 1344 if (MRegisterInfo::isVirtualRegister(RegB)) 1345 return RegClass != mf_->getSSARegMap()->getRegClass(RegB); 1346 else 1347 return !RegClass->contains(RegB); 1348} 1349 1350LiveInterval LiveIntervals::createInterval(unsigned reg) { 1351 float Weight = MRegisterInfo::isPhysicalRegister(reg) ? 1352 HUGE_VALF : 0.0F; 1353 return LiveInterval(reg, Weight); 1354} 1355