LiveIntervalAnalysis.cpp revision 5d0d1e350a30772fd70798b5733bb060febd7b0d
1//===-- LiveIntervalAnalysis.cpp - Live Interval Analysis -----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the LiveInterval analysis pass which is used 11// by the Linear Scan Register allocator. This pass linearizes the 12// basic blocks of the function in DFS order and uses the 13// LiveVariables pass to conservatively compute live intervals for 14// each virtual and physical register. 15// 16//===----------------------------------------------------------------------===// 17 18#define DEBUG_TYPE "liveintervals" 19#include "LiveIntervalAnalysis.h" 20#include "VirtRegMap.h" 21#include "llvm/Value.h" 22#include "llvm/Analysis/LoopInfo.h" 23#include "llvm/CodeGen/LiveVariables.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/MachineInstr.h" 26#include "llvm/CodeGen/Passes.h" 27#include "llvm/CodeGen/SSARegMap.h" 28#include "llvm/Target/MRegisterInfo.h" 29#include "llvm/Target/TargetInstrInfo.h" 30#include "llvm/Target/TargetMachine.h" 31#include "llvm/Support/CommandLine.h" 32#include "llvm/Support/Debug.h" 33#include "llvm/ADT/Statistic.h" 34#include "llvm/ADT/STLExtras.h" 35#include <algorithm> 36#include <cmath> 37using namespace llvm; 38 39namespace { 40 RegisterAnalysis<LiveIntervals> X("liveintervals", "Live Interval Analysis"); 41 42 Statistic<> numIntervals 43 ("liveintervals", "Number of original intervals"); 44 45 Statistic<> numIntervalsAfter 46 ("liveintervals", "Number of intervals after coalescing"); 47 48 Statistic<> numJoins 49 ("liveintervals", "Number of interval joins performed"); 50 51 Statistic<> numPeep 52 ("liveintervals", "Number of identity moves eliminated after coalescing"); 53 54 Statistic<> numFolded 55 ("liveintervals", "Number of loads/stores folded into instructions"); 56 57 cl::opt<bool> 58 EnableJoining("join-liveintervals", 59 cl::desc("Join compatible live intervals"), 60 cl::init(true)); 61}; 62 63void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const 64{ 65 AU.addPreserved<LiveVariables>(); 66 AU.addRequired<LiveVariables>(); 67 AU.addPreservedID(PHIEliminationID); 68 AU.addRequiredID(PHIEliminationID); 69 AU.addRequiredID(TwoAddressInstructionPassID); 70 AU.addRequired<LoopInfo>(); 71 MachineFunctionPass::getAnalysisUsage(AU); 72} 73 74void LiveIntervals::releaseMemory() 75{ 76 mi2iMap_.clear(); 77 i2miMap_.clear(); 78 r2iMap_.clear(); 79 r2rMap_.clear(); 80} 81 82 83/// runOnMachineFunction - Register allocate the whole function 84/// 85bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) { 86 mf_ = &fn; 87 tm_ = &fn.getTarget(); 88 mri_ = tm_->getRegisterInfo(); 89 lv_ = &getAnalysis<LiveVariables>(); 90 allocatableRegs_ = mri_->getAllocatableSet(fn); 91 92 // number MachineInstrs 93 unsigned miIndex = 0; 94 for (MachineFunction::iterator mbb = mf_->begin(), mbbEnd = mf_->end(); 95 mbb != mbbEnd; ++mbb) 96 for (MachineBasicBlock::iterator mi = mbb->begin(), miEnd = mbb->end(); 97 mi != miEnd; ++mi) { 98 bool inserted = mi2iMap_.insert(std::make_pair(mi, miIndex)).second; 99 assert(inserted && "multiple MachineInstr -> index mappings"); 100 i2miMap_.push_back(mi); 101 miIndex += InstrSlots::NUM; 102 } 103 104 computeIntervals(); 105 106 numIntervals += getNumIntervals(); 107 108#if 1 109 DEBUG(std::cerr << "********** INTERVALS **********\n"); 110 DEBUG(for (iterator I = begin(), E = end(); I != E; ++I) 111 std::cerr << I->second << "\n"); 112#endif 113 114 // join intervals if requested 115 if (EnableJoining) joinIntervals(); 116 117 numIntervalsAfter += getNumIntervals(); 118 119 // perform a final pass over the instructions and compute spill 120 // weights, coalesce virtual registers and remove identity moves 121 const LoopInfo& loopInfo = getAnalysis<LoopInfo>(); 122 const TargetInstrInfo& tii = *tm_->getInstrInfo(); 123 124 for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end(); 125 mbbi != mbbe; ++mbbi) { 126 MachineBasicBlock* mbb = mbbi; 127 unsigned loopDepth = loopInfo.getLoopDepth(mbb->getBasicBlock()); 128 129 for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end(); 130 mii != mie; ) { 131 // if the move will be an identity move delete it 132 unsigned srcReg, dstReg, RegRep; 133 if (tii.isMoveInstr(*mii, srcReg, dstReg) && 134 (RegRep = rep(srcReg)) == rep(dstReg)) { 135 // remove from def list 136 LiveInterval &interval = getOrCreateInterval(RegRep); 137 // remove index -> MachineInstr and 138 // MachineInstr -> index mappings 139 Mi2IndexMap::iterator mi2i = mi2iMap_.find(mii); 140 if (mi2i != mi2iMap_.end()) { 141 i2miMap_[mi2i->second/InstrSlots::NUM] = 0; 142 mi2iMap_.erase(mi2i); 143 } 144 mii = mbbi->erase(mii); 145 ++numPeep; 146 } 147 else { 148 for (unsigned i = 0; i < mii->getNumOperands(); ++i) { 149 const MachineOperand& mop = mii->getOperand(i); 150 if (mop.isRegister() && mop.getReg() && 151 MRegisterInfo::isVirtualRegister(mop.getReg())) { 152 // replace register with representative register 153 unsigned reg = rep(mop.getReg()); 154 mii->SetMachineOperandReg(i, reg); 155 156 LiveInterval &RegInt = getInterval(reg); 157 RegInt.weight += 158 (mop.isUse() + mop.isDef()) * pow(10.0F, loopDepth); 159 } 160 } 161 ++mii; 162 } 163 } 164 } 165 166 DEBUG(std::cerr << "********** INTERVALS **********\n"); 167 DEBUG (for (iterator I = begin(), E = end(); I != E; ++I) 168 std::cerr << I->second << "\n"); 169 DEBUG(std::cerr << "********** MACHINEINSTRS **********\n"); 170 DEBUG( 171 for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end(); 172 mbbi != mbbe; ++mbbi) { 173 std::cerr << ((Value*)mbbi->getBasicBlock())->getName() << ":\n"; 174 for (MachineBasicBlock::iterator mii = mbbi->begin(), 175 mie = mbbi->end(); mii != mie; ++mii) { 176 std::cerr << getInstructionIndex(mii) << '\t'; 177 mii->print(std::cerr, tm_); 178 } 179 }); 180 181 return true; 182} 183 184std::vector<LiveInterval*> LiveIntervals::addIntervalsForSpills( 185 const LiveInterval& li, 186 VirtRegMap& vrm, 187 int slot) 188{ 189 // since this is called after the analysis is done we don't know if 190 // LiveVariables is available 191 lv_ = getAnalysisToUpdate<LiveVariables>(); 192 193 std::vector<LiveInterval*> added; 194 195 assert(li.weight != HUGE_VAL && 196 "attempt to spill already spilled interval!"); 197 198 DEBUG(std::cerr << "\t\t\t\tadding intervals for spills for interval: " 199 << li << '\n'); 200 201 const TargetRegisterClass* rc = mf_->getSSARegMap()->getRegClass(li.reg); 202 203 for (LiveInterval::Ranges::const_iterator 204 i = li.ranges.begin(), e = li.ranges.end(); i != e; ++i) { 205 unsigned index = getBaseIndex(i->start); 206 unsigned end = getBaseIndex(i->end-1) + InstrSlots::NUM; 207 for (; index != end; index += InstrSlots::NUM) { 208 // skip deleted instructions 209 while (index != end && !getInstructionFromIndex(index)) 210 index += InstrSlots::NUM; 211 if (index == end) break; 212 213 MachineBasicBlock::iterator mi = getInstructionFromIndex(index); 214 215 for_operand: 216 for (unsigned i = 0; i != mi->getNumOperands(); ++i) { 217 MachineOperand& mop = mi->getOperand(i); 218 if (mop.isRegister() && mop.getReg() == li.reg) { 219 if (MachineInstr* fmi = mri_->foldMemoryOperand(mi, i, slot)) { 220 if (lv_) 221 lv_->instructionChanged(mi, fmi); 222 vrm.virtFolded(li.reg, mi, fmi); 223 mi2iMap_.erase(mi); 224 i2miMap_[index/InstrSlots::NUM] = fmi; 225 mi2iMap_[fmi] = index; 226 MachineBasicBlock& mbb = *mi->getParent(); 227 mi = mbb.insert(mbb.erase(mi), fmi); 228 ++numFolded; 229 goto for_operand; 230 } 231 else { 232 // This is tricky. We need to add information in 233 // the interval about the spill code so we have to 234 // use our extra load/store slots. 235 // 236 // If we have a use we are going to have a load so 237 // we start the interval from the load slot 238 // onwards. Otherwise we start from the def slot. 239 unsigned start = (mop.isUse() ? 240 getLoadIndex(index) : 241 getDefIndex(index)); 242 // If we have a def we are going to have a store 243 // right after it so we end the interval after the 244 // use of the next instruction. Otherwise we end 245 // after the use of this instruction. 246 unsigned end = 1 + (mop.isDef() ? 247 getStoreIndex(index) : 248 getUseIndex(index)); 249 250 // create a new register for this spill 251 unsigned nReg = mf_->getSSARegMap()->createVirtualRegister(rc); 252 mi->SetMachineOperandReg(i, nReg); 253 vrm.grow(); 254 vrm.assignVirt2StackSlot(nReg, slot); 255 LiveInterval& nI = getOrCreateInterval(nReg); 256 assert(nI.empty()); 257 // the spill weight is now infinity as it 258 // cannot be spilled again 259 nI.weight = HUGE_VAL; 260 LiveRange LR(start, end, nI.getNextValue()); 261 DEBUG(std::cerr << " +" << LR); 262 nI.addRange(LR); 263 added.push_back(&nI); 264 // update live variables if it is available 265 if (lv_) 266 lv_->addVirtualRegisterKilled(nReg, mi); 267 DEBUG(std::cerr << "\t\t\t\tadded new interval: " << nI << '\n'); 268 } 269 } 270 } 271 } 272 } 273 274 return added; 275} 276 277void LiveIntervals::printRegName(unsigned reg) const 278{ 279 if (MRegisterInfo::isPhysicalRegister(reg)) 280 std::cerr << mri_->getName(reg); 281 else 282 std::cerr << "%reg" << reg; 283} 284 285void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock* mbb, 286 MachineBasicBlock::iterator mi, 287 LiveInterval& interval) 288{ 289 DEBUG(std::cerr << "\t\tregister: "; printRegName(interval.reg)); 290 LiveVariables::VarInfo& vi = lv_->getVarInfo(interval.reg); 291 292 // Virtual registers may be defined multiple times (due to phi 293 // elimination and 2-addr elimination). Much of what we do only has to be 294 // done once for the vreg. We use an empty interval to detect the first 295 // time we see a vreg. 296 if (interval.empty()) { 297 // Get the Idx of the defining instructions. 298 unsigned defIndex = getDefIndex(getInstructionIndex(mi)); 299 300 unsigned ValNum = interval.getNextValue(); 301 assert(ValNum == 0 && "First value in interval is not 0?"); 302 ValNum = 0; // Clue in the optimizer. 303 304 // Loop over all of the blocks that the vreg is defined in. There are 305 // two cases we have to handle here. The most common case is a vreg 306 // whose lifetime is contained within a basic block. In this case there 307 // will be a single kill, in MBB, which comes after the definition. 308 if (vi.Kills.size() == 1 && vi.Kills[0]->getParent() == mbb) { 309 // FIXME: what about dead vars? 310 unsigned killIdx; 311 if (vi.Kills[0] != mi) 312 killIdx = getUseIndex(getInstructionIndex(vi.Kills[0]))+1; 313 else 314 killIdx = defIndex+1; 315 316 // If the kill happens after the definition, we have an intra-block 317 // live range. 318 if (killIdx > defIndex) { 319 assert(vi.AliveBlocks.empty() && 320 "Shouldn't be alive across any blocks!"); 321 LiveRange LR(defIndex, killIdx, ValNum); 322 interval.addRange(LR); 323 DEBUG(std::cerr << " +" << LR << "\n"); 324 return; 325 } 326 } 327 328 // The other case we handle is when a virtual register lives to the end 329 // of the defining block, potentially live across some blocks, then is 330 // live into some number of blocks, but gets killed. Start by adding a 331 // range that goes from this definition to the end of the defining block. 332 LiveRange NewLR(defIndex, 333 getInstructionIndex(&mbb->back()) + InstrSlots::NUM, 334 ValNum); 335 DEBUG(std::cerr << " +" << NewLR); 336 interval.addRange(NewLR); 337 338 // Iterate over all of the blocks that the variable is completely 339 // live in, adding [insrtIndex(begin), instrIndex(end)+4) to the 340 // live interval. 341 for (unsigned i = 0, e = vi.AliveBlocks.size(); i != e; ++i) { 342 if (vi.AliveBlocks[i]) { 343 MachineBasicBlock* mbb = mf_->getBlockNumbered(i); 344 if (!mbb->empty()) { 345 LiveRange LR(getInstructionIndex(&mbb->front()), 346 getInstructionIndex(&mbb->back()) + InstrSlots::NUM, 347 ValNum); 348 interval.addRange(LR); 349 DEBUG(std::cerr << " +" << LR); 350 } 351 } 352 } 353 354 // Finally, this virtual register is live from the start of any killing 355 // block to the 'use' slot of the killing instruction. 356 for (unsigned i = 0, e = vi.Kills.size(); i != e; ++i) { 357 MachineInstr *Kill = vi.Kills[i]; 358 LiveRange LR(getInstructionIndex(Kill->getParent()->begin()), 359 getUseIndex(getInstructionIndex(Kill))+1, 360 ValNum); 361 interval.addRange(LR); 362 DEBUG(std::cerr << " +" << LR); 363 } 364 365 } else { 366 // If this is the second time we see a virtual register definition, it 367 // must be due to phi elimination or two addr elimination. If this is 368 // the result of two address elimination, then the vreg is the first 369 // operand, and is a def-and-use. 370 if (mi->getOperand(0).isRegister() && 371 mi->getOperand(0).getReg() == interval.reg && 372 mi->getOperand(0).isDef() && mi->getOperand(0).isUse()) { 373 // If this is a two-address definition, then we have already processed 374 // the live range. The only problem is that we didn't realize there 375 // are actually two values in the live interval. Because of this we 376 // need to take the LiveRegion that defines this register and split it 377 // into two values. 378 unsigned DefIndex = getDefIndex(getInstructionIndex(vi.DefInst)); 379 unsigned RedefIndex = getDefIndex(getInstructionIndex(mi)); 380 381 // Delete the initial value, which should be short and continuous, 382 // becuase the 2-addr copy must be in the same MBB as the redef. 383 interval.removeRange(DefIndex, RedefIndex); 384 385 LiveRange LR(DefIndex, RedefIndex, interval.getNextValue()); 386 DEBUG(std::cerr << " replace range with " << LR); 387 interval.addRange(LR); 388 389 // If this redefinition is dead, we need to add a dummy unit live 390 // range covering the def slot. 391 for (LiveVariables::killed_iterator KI = lv_->dead_begin(mi), 392 E = lv_->dead_end(mi); KI != E; ++KI) 393 if (KI->second == interval.reg) { 394 interval.addRange(LiveRange(RedefIndex, RedefIndex+1, 0)); 395 break; 396 } 397 398 DEBUG(std::cerr << "RESULT: " << interval); 399 400 } else { 401 // Otherwise, this must be because of phi elimination. If this is the 402 // first redefinition of the vreg that we have seen, go back and change 403 // the live range in the PHI block to be a different value number. 404 if (interval.containsOneValue()) { 405 assert(vi.Kills.size() == 1 && 406 "PHI elimination vreg should have one kill, the PHI itself!"); 407 408 // Remove the old range that we now know has an incorrect number. 409 MachineInstr *Killer = vi.Kills[0]; 410 unsigned Start = getInstructionIndex(Killer->getParent()->begin()); 411 unsigned End = getUseIndex(getInstructionIndex(Killer))+1; 412 DEBUG(std::cerr << "Removing [" << Start << "," << End << "] from: " 413 << interval << "\n"); 414 interval.removeRange(Start, End); 415 DEBUG(std::cerr << "RESULT: " << interval); 416 417 // Replace the interval with one of a NEW value number. 418 LiveRange LR(Start, End, interval.getNextValue()); 419 DEBUG(std::cerr << " replace range with " << LR); 420 interval.addRange(LR); 421 DEBUG(std::cerr << "RESULT: " << interval); 422 } 423 424 // In the case of PHI elimination, each variable definition is only 425 // live until the end of the block. We've already taken care of the 426 // rest of the live range. 427 unsigned defIndex = getDefIndex(getInstructionIndex(mi)); 428 LiveRange LR(defIndex, 429 getInstructionIndex(&mbb->back()) + InstrSlots::NUM, 430 interval.getNextValue()); 431 interval.addRange(LR); 432 DEBUG(std::cerr << " +" << LR); 433 } 434 } 435 436 DEBUG(std::cerr << '\n'); 437} 438 439void LiveIntervals::handlePhysicalRegisterDef(MachineBasicBlock *MBB, 440 MachineBasicBlock::iterator mi, 441 LiveInterval& interval) 442{ 443 // A physical register cannot be live across basic block, so its 444 // lifetime must end somewhere in its defining basic block. 445 DEBUG(std::cerr << "\t\tregister: "; printRegName(interval.reg)); 446 typedef LiveVariables::killed_iterator KillIter; 447 448 unsigned baseIndex = getInstructionIndex(mi); 449 unsigned start = getDefIndex(baseIndex); 450 unsigned end = start; 451 452 // If it is not used after definition, it is considered dead at 453 // the instruction defining it. Hence its interval is: 454 // [defSlot(def), defSlot(def)+1) 455 for (KillIter ki = lv_->dead_begin(mi), ke = lv_->dead_end(mi); 456 ki != ke; ++ki) { 457 if (interval.reg == ki->second) { 458 DEBUG(std::cerr << " dead"); 459 end = getDefIndex(start) + 1; 460 goto exit; 461 } 462 } 463 464 // If it is not dead on definition, it must be killed by a 465 // subsequent instruction. Hence its interval is: 466 // [defSlot(def), useSlot(kill)+1) 467 while (true) { 468 ++mi; 469 assert(mi != MBB->end() && "physreg was not killed in defining block!"); 470 baseIndex += InstrSlots::NUM; 471 for (KillIter ki = lv_->killed_begin(mi), ke = lv_->killed_end(mi); 472 ki != ke; ++ki) { 473 if (interval.reg == ki->second) { 474 DEBUG(std::cerr << " killed"); 475 end = getUseIndex(baseIndex) + 1; 476 goto exit; 477 } 478 } 479 } 480 481exit: 482 assert(start < end && "did not find end of interval?"); 483 LiveRange LR(start, end, interval.getNextValue()); 484 interval.addRange(LR); 485 DEBUG(std::cerr << " +" << LR << '\n'); 486} 487 488void LiveIntervals::handleRegisterDef(MachineBasicBlock *MBB, 489 MachineBasicBlock::iterator MI, 490 unsigned reg) { 491 if (MRegisterInfo::isVirtualRegister(reg)) 492 handleVirtualRegisterDef(MBB, MI, getOrCreateInterval(reg)); 493 else if (allocatableRegs_[reg]) { 494 handlePhysicalRegisterDef(MBB, MI, getOrCreateInterval(reg)); 495 for (const unsigned* AS = mri_->getAliasSet(reg); *AS; ++AS) 496 handlePhysicalRegisterDef(MBB, MI, getOrCreateInterval(*AS)); 497 } 498} 499 500/// computeIntervals - computes the live intervals for virtual 501/// registers. for some ordering of the machine instructions [1,N] a 502/// live interval is an interval [i, j) where 1 <= i <= j < N for 503/// which a variable is live 504void LiveIntervals::computeIntervals() 505{ 506 DEBUG(std::cerr << "********** COMPUTING LIVE INTERVALS **********\n"); 507 DEBUG(std::cerr << "********** Function: " 508 << ((Value*)mf_->getFunction())->getName() << '\n'); 509 510 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end(); 511 I != E; ++I) { 512 MachineBasicBlock* mbb = I; 513 DEBUG(std::cerr << ((Value*)mbb->getBasicBlock())->getName() << ":\n"); 514 515 for (MachineBasicBlock::iterator mi = mbb->begin(), miEnd = mbb->end(); 516 mi != miEnd; ++mi) { 517 const TargetInstrDescriptor& tid = 518 tm_->getInstrInfo()->get(mi->getOpcode()); 519 DEBUG(std::cerr << getInstructionIndex(mi) << "\t"; 520 mi->print(std::cerr, tm_)); 521 522 // handle implicit defs 523 for (const unsigned* id = tid.ImplicitDefs; *id; ++id) 524 handleRegisterDef(mbb, mi, *id); 525 526 // handle explicit defs 527 for (int i = mi->getNumOperands() - 1; i >= 0; --i) { 528 MachineOperand& mop = mi->getOperand(i); 529 // handle register defs - build intervals 530 if (mop.isRegister() && mop.getReg() && mop.isDef()) 531 handleRegisterDef(mbb, mi, mop.getReg()); 532 } 533 } 534 } 535} 536 537void LiveIntervals::joinIntervalsInMachineBB(MachineBasicBlock *MBB) { 538 DEBUG(std::cerr << ((Value*)MBB->getBasicBlock())->getName() << ":\n"); 539 const TargetInstrInfo &TII = *tm_->getInstrInfo(); 540 541 for (MachineBasicBlock::iterator mi = MBB->begin(), mie = MBB->end(); 542 mi != mie; ++mi) { 543 DEBUG(std::cerr << getInstructionIndex(mi) << '\t' << *mi); 544 545 // we only join virtual registers with allocatable 546 // physical registers since we do not have liveness information 547 // on not allocatable physical registers 548 unsigned regA, regB; 549 if (TII.isMoveInstr(*mi, regA, regB) && 550 (MRegisterInfo::isVirtualRegister(regA) || allocatableRegs_[regA]) && 551 (MRegisterInfo::isVirtualRegister(regB) || allocatableRegs_[regB])) { 552 553 // Get representative registers. 554 regA = rep(regA); 555 regB = rep(regB); 556 557 // If they are already joined we continue. 558 if (regA == regB) 559 continue; 560 561 // If they are both physical registers, we cannot join them. 562 if (MRegisterInfo::isPhysicalRegister(regA) && 563 MRegisterInfo::isPhysicalRegister(regB)) 564 continue; 565 566 // If they are not of the same register class, we cannot join them. 567 if (differingRegisterClasses(regA, regB)) 568 continue; 569 570 LiveInterval &IntA = getInterval(regA); 571 LiveInterval &IntB = getInterval(regB); 572 assert(IntA.reg == regA && IntB.reg == regB && 573 "Register mapping is horribly broken!"); 574 575 DEBUG(std::cerr << "\t\tInspecting " << IntA << " and " << IntB << ": "); 576 577 // If two intervals contain a single value and are joined by a copy, it 578 // does not matter if the intervals overlap, they can always be joined. 579 bool TriviallyJoinable = 580 IntA.containsOneValue() && IntB.containsOneValue(); 581 582 unsigned MIDefIdx = getDefIndex(getInstructionIndex(mi)); 583 if ((TriviallyJoinable || IntB.joinable(IntA, MIDefIdx)) && 584 !overlapsAliases(&IntA, &IntB)) { 585 IntB.join(IntA, MIDefIdx); 586 587 if (!MRegisterInfo::isPhysicalRegister(regA)) { 588 r2iMap_.erase(regA); 589 r2rMap_[regA] = regB; 590 } else { 591 // Otherwise merge the data structures the other way so we don't lose 592 // the physreg information. 593 r2rMap_[regB] = regA; 594 IntB.reg = regA; 595 IntA.swap(IntB); 596 r2iMap_.erase(regB); 597 } 598 DEBUG(std::cerr << "Joined. Result = " << IntB << "\n"); 599 ++numJoins; 600 } else { 601 DEBUG(std::cerr << "Interference!\n"); 602 } 603 } 604 } 605} 606 607namespace { 608 // DepthMBBCompare - Comparison predicate that sort first based on the loop 609 // depth of the basic block (the unsigned), and then on the MBB number. 610 struct DepthMBBCompare { 611 typedef std::pair<unsigned, MachineBasicBlock*> DepthMBBPair; 612 bool operator()(const DepthMBBPair &LHS, const DepthMBBPair &RHS) const { 613 if (LHS.first > RHS.first) return true; // Deeper loops first 614 return LHS.first == RHS.first && 615 LHS.second->getNumber() < RHS.second->getNumber(); 616 } 617 }; 618} 619 620void LiveIntervals::joinIntervals() { 621 DEBUG(std::cerr << "********** JOINING INTERVALS ***********\n"); 622 // reserve space for the reg2reg map 623 r2rMap_.grow(mf_->getSSARegMap()->getLastVirtReg()); 624 625 const LoopInfo &LI = getAnalysis<LoopInfo>(); 626 if (LI.begin() == LI.end()) { 627 // If there are no loops in the function, join intervals in function order. 628 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end(); 629 I != E; ++I) 630 joinIntervalsInMachineBB(I); 631 } else { 632 // Otherwise, join intervals in inner loops before other intervals. 633 // Unfortunately we can't just iterate over loop hierarchy here because 634 // there may be more MBB's than BB's. Collect MBB's for sorting. 635 std::vector<std::pair<unsigned, MachineBasicBlock*> > MBBs; 636 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end(); 637 I != E; ++I) 638 MBBs.push_back(std::make_pair(LI.getLoopDepth(I->getBasicBlock()), I)); 639 640 // Sort by loop depth. 641 std::sort(MBBs.begin(), MBBs.end(), DepthMBBCompare()); 642 643 // Finally, join intervals in loop nest order. 644 for (unsigned i = 0, e = MBBs.size(); i != e; ++i) 645 joinIntervalsInMachineBB(MBBs[i].second); 646 } 647 648 DEBUG(std::cerr << "*** Register mapping ***\n"); 649 DEBUG(for (int i = 0, e = r2rMap_.size(); i != e; ++i) 650 if (r2rMap_[i]) 651 std::cerr << " reg " << i << " -> reg " << r2rMap_[i] << "\n"); 652} 653 654/// Return true if the two specified registers belong to different register 655/// classes. The registers may be either phys or virt regs. 656bool LiveIntervals::differingRegisterClasses(unsigned RegA, 657 unsigned RegB) const { 658 const TargetRegisterClass *RegClass; 659 660 // Get the register classes for the first reg. 661 if (MRegisterInfo::isVirtualRegister(RegA)) 662 RegClass = mf_->getSSARegMap()->getRegClass(RegA); 663 else 664 RegClass = mri_->getRegClass(RegA); 665 666 // Compare against the regclass for the second reg. 667 if (MRegisterInfo::isVirtualRegister(RegB)) 668 return RegClass != mf_->getSSARegMap()->getRegClass(RegB); 669 else 670 return !RegClass->contains(RegB); 671} 672 673bool LiveIntervals::overlapsAliases(const LiveInterval *LHS, 674 const LiveInterval *RHS) const { 675 if (!MRegisterInfo::isPhysicalRegister(LHS->reg)) { 676 if (!MRegisterInfo::isPhysicalRegister(RHS->reg)) 677 return false; // vreg-vreg merge has no aliases! 678 std::swap(LHS, RHS); 679 } 680 681 assert(MRegisterInfo::isPhysicalRegister(LHS->reg) && 682 MRegisterInfo::isVirtualRegister(RHS->reg) && 683 "first interval must describe a physical register"); 684 685 for (const unsigned *AS = mri_->getAliasSet(LHS->reg); *AS; ++AS) 686 if (RHS->overlaps(getInterval(*AS))) 687 return true; 688 689 return false; 690} 691 692LiveInterval LiveIntervals::createInterval(unsigned reg) { 693 float Weight = MRegisterInfo::isPhysicalRegister(reg) ? HUGE_VAL :0.0F; 694 return LiveInterval(reg, Weight); 695} 696