LiveIntervalAnalysis.cpp revision 84423c8778ed22877c123fe41f5e137cb5a30e90
1//===-- LiveIntervalAnalysis.cpp - Live Interval Analysis -----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the LiveInterval analysis pass which is used 11// by the Linear Scan Register allocator. This pass linearizes the 12// basic blocks of the function in DFS order and uses the 13// LiveVariables pass to conservatively compute live intervals for 14// each virtual and physical register. 15// 16//===----------------------------------------------------------------------===// 17 18#define DEBUG_TYPE "regalloc" 19#include "llvm/CodeGen/LiveIntervalAnalysis.h" 20#include "llvm/Value.h" 21#include "llvm/Analysis/AliasAnalysis.h" 22#include "llvm/CodeGen/LiveVariables.h" 23#include "llvm/CodeGen/MachineInstr.h" 24#include "llvm/CodeGen/MachineRegisterInfo.h" 25#include "llvm/CodeGen/Passes.h" 26#include "llvm/Target/TargetRegisterInfo.h" 27#include "llvm/Target/TargetInstrInfo.h" 28#include "llvm/Target/TargetMachine.h" 29#include "llvm/Support/CommandLine.h" 30#include "llvm/Support/Debug.h" 31#include "llvm/Support/ErrorHandling.h" 32#include "llvm/Support/raw_ostream.h" 33#include "llvm/ADT/DenseSet.h" 34#include "llvm/ADT/Statistic.h" 35#include "llvm/ADT/STLExtras.h" 36#include <algorithm> 37#include <limits> 38#include <cmath> 39using namespace llvm; 40 41// Hidden options for help debugging. 42static cl::opt<bool> DisableReMat("disable-rematerialization", 43 cl::init(false), cl::Hidden); 44 45STATISTIC(numIntervals , "Number of original intervals"); 46 47char LiveIntervals::ID = 0; 48INITIALIZE_PASS_BEGIN(LiveIntervals, "liveintervals", 49 "Live Interval Analysis", false, false) 50INITIALIZE_AG_DEPENDENCY(AliasAnalysis) 51INITIALIZE_PASS_DEPENDENCY(LiveVariables) 52INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree) 53INITIALIZE_PASS_DEPENDENCY(SlotIndexes) 54INITIALIZE_PASS_END(LiveIntervals, "liveintervals", 55 "Live Interval Analysis", false, false) 56 57void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const { 58 AU.setPreservesCFG(); 59 AU.addRequired<AliasAnalysis>(); 60 AU.addPreserved<AliasAnalysis>(); 61 AU.addRequired<LiveVariables>(); 62 AU.addPreserved<LiveVariables>(); 63 AU.addPreservedID(MachineLoopInfoID); 64 AU.addPreservedID(MachineDominatorsID); 65 AU.addPreserved<SlotIndexes>(); 66 AU.addRequiredTransitive<SlotIndexes>(); 67 MachineFunctionPass::getAnalysisUsage(AU); 68} 69 70void LiveIntervals::releaseMemory() { 71 // Free the live intervals themselves. 72 for (DenseMap<unsigned, LiveInterval*>::iterator I = R2IMap.begin(), 73 E = R2IMap.end(); I != E; ++I) 74 delete I->second; 75 76 R2IMap.clear(); 77 RegMaskSlots.clear(); 78 RegMaskBits.clear(); 79 RegMaskBlocks.clear(); 80 81 // Release VNInfo memory regions, VNInfo objects don't need to be dtor'd. 82 VNInfoAllocator.Reset(); 83} 84 85/// runOnMachineFunction - Register allocate the whole function 86/// 87bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) { 88 MF = &fn; 89 MRI = &MF->getRegInfo(); 90 TM = &fn.getTarget(); 91 TRI = TM->getRegisterInfo(); 92 TII = TM->getInstrInfo(); 93 AA = &getAnalysis<AliasAnalysis>(); 94 LV = &getAnalysis<LiveVariables>(); 95 Indexes = &getAnalysis<SlotIndexes>(); 96 AllocatableRegs = TRI->getAllocatableSet(fn); 97 ReservedRegs = TRI->getReservedRegs(fn); 98 99 computeIntervals(); 100 101 numIntervals += getNumIntervals(); 102 103 DEBUG(dump()); 104 return true; 105} 106 107/// print - Implement the dump method. 108void LiveIntervals::print(raw_ostream &OS, const Module* ) const { 109 OS << "********** INTERVALS **********\n"; 110 111 // Dump the physregs. 112 for (unsigned Reg = 1, RegE = TRI->getNumRegs(); Reg != RegE; ++Reg) 113 if (const LiveInterval *LI = R2IMap.lookup(Reg)) { 114 LI->print(OS, TRI); 115 OS << '\n'; 116 } 117 118 // Dump the virtregs. 119 for (unsigned Reg = 0, RegE = MRI->getNumVirtRegs(); Reg != RegE; ++Reg) 120 if (const LiveInterval *LI = 121 R2IMap.lookup(TargetRegisterInfo::index2VirtReg(Reg))) { 122 LI->print(OS, TRI); 123 OS << '\n'; 124 } 125 126 printInstrs(OS); 127} 128 129void LiveIntervals::printInstrs(raw_ostream &OS) const { 130 OS << "********** MACHINEINSTRS **********\n"; 131 MF->print(OS, Indexes); 132} 133 134void LiveIntervals::dumpInstrs() const { 135 printInstrs(dbgs()); 136} 137 138static 139bool MultipleDefsBySameMI(const MachineInstr &MI, unsigned MOIdx) { 140 unsigned Reg = MI.getOperand(MOIdx).getReg(); 141 for (unsigned i = MOIdx+1, e = MI.getNumOperands(); i < e; ++i) { 142 const MachineOperand &MO = MI.getOperand(i); 143 if (!MO.isReg()) 144 continue; 145 if (MO.getReg() == Reg && MO.isDef()) { 146 assert(MI.getOperand(MOIdx).getSubReg() != MO.getSubReg() && 147 MI.getOperand(MOIdx).getSubReg() && 148 (MO.getSubReg() || MO.isImplicit())); 149 return true; 150 } 151 } 152 return false; 153} 154 155/// isPartialRedef - Return true if the specified def at the specific index is 156/// partially re-defining the specified live interval. A common case of this is 157/// a definition of the sub-register. 158bool LiveIntervals::isPartialRedef(SlotIndex MIIdx, MachineOperand &MO, 159 LiveInterval &interval) { 160 if (!MO.getSubReg() || MO.isEarlyClobber()) 161 return false; 162 163 SlotIndex RedefIndex = MIIdx.getRegSlot(); 164 const LiveRange *OldLR = 165 interval.getLiveRangeContaining(RedefIndex.getRegSlot(true)); 166 MachineInstr *DefMI = getInstructionFromIndex(OldLR->valno->def); 167 if (DefMI != 0) { 168 return DefMI->findRegisterDefOperandIdx(interval.reg) != -1; 169 } 170 return false; 171} 172 173void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb, 174 MachineBasicBlock::iterator mi, 175 SlotIndex MIIdx, 176 MachineOperand& MO, 177 unsigned MOIdx, 178 LiveInterval &interval) { 179 DEBUG(dbgs() << "\t\tregister: " << PrintReg(interval.reg, TRI)); 180 181 // Virtual registers may be defined multiple times (due to phi 182 // elimination and 2-addr elimination). Much of what we do only has to be 183 // done once for the vreg. We use an empty interval to detect the first 184 // time we see a vreg. 185 LiveVariables::VarInfo& vi = LV->getVarInfo(interval.reg); 186 if (interval.empty()) { 187 // Get the Idx of the defining instructions. 188 SlotIndex defIndex = MIIdx.getRegSlot(MO.isEarlyClobber()); 189 190 // Make sure the first definition is not a partial redefinition. 191 assert(!MO.readsReg() && "First def cannot also read virtual register " 192 "missing <undef> flag?"); 193 194 VNInfo *ValNo = interval.getNextValue(defIndex, VNInfoAllocator); 195 assert(ValNo->id == 0 && "First value in interval is not 0?"); 196 197 // Loop over all of the blocks that the vreg is defined in. There are 198 // two cases we have to handle here. The most common case is a vreg 199 // whose lifetime is contained within a basic block. In this case there 200 // will be a single kill, in MBB, which comes after the definition. 201 if (vi.Kills.size() == 1 && vi.Kills[0]->getParent() == mbb) { 202 // FIXME: what about dead vars? 203 SlotIndex killIdx; 204 if (vi.Kills[0] != mi) 205 killIdx = getInstructionIndex(vi.Kills[0]).getRegSlot(); 206 else 207 killIdx = defIndex.getDeadSlot(); 208 209 // If the kill happens after the definition, we have an intra-block 210 // live range. 211 if (killIdx > defIndex) { 212 assert(vi.AliveBlocks.empty() && 213 "Shouldn't be alive across any blocks!"); 214 LiveRange LR(defIndex, killIdx, ValNo); 215 interval.addRange(LR); 216 DEBUG(dbgs() << " +" << LR << "\n"); 217 return; 218 } 219 } 220 221 // The other case we handle is when a virtual register lives to the end 222 // of the defining block, potentially live across some blocks, then is 223 // live into some number of blocks, but gets killed. Start by adding a 224 // range that goes from this definition to the end of the defining block. 225 LiveRange NewLR(defIndex, getMBBEndIdx(mbb), ValNo); 226 DEBUG(dbgs() << " +" << NewLR); 227 interval.addRange(NewLR); 228 229 bool PHIJoin = LV->isPHIJoin(interval.reg); 230 231 if (PHIJoin) { 232 // A phi join register is killed at the end of the MBB and revived as a new 233 // valno in the killing blocks. 234 assert(vi.AliveBlocks.empty() && "Phi join can't pass through blocks"); 235 DEBUG(dbgs() << " phi-join"); 236 ValNo->setHasPHIKill(true); 237 } else { 238 // Iterate over all of the blocks that the variable is completely 239 // live in, adding [insrtIndex(begin), instrIndex(end)+4) to the 240 // live interval. 241 for (SparseBitVector<>::iterator I = vi.AliveBlocks.begin(), 242 E = vi.AliveBlocks.end(); I != E; ++I) { 243 MachineBasicBlock *aliveBlock = MF->getBlockNumbered(*I); 244 LiveRange LR(getMBBStartIdx(aliveBlock), getMBBEndIdx(aliveBlock), ValNo); 245 interval.addRange(LR); 246 DEBUG(dbgs() << " +" << LR); 247 } 248 } 249 250 // Finally, this virtual register is live from the start of any killing 251 // block to the 'use' slot of the killing instruction. 252 for (unsigned i = 0, e = vi.Kills.size(); i != e; ++i) { 253 MachineInstr *Kill = vi.Kills[i]; 254 SlotIndex Start = getMBBStartIdx(Kill->getParent()); 255 SlotIndex killIdx = getInstructionIndex(Kill).getRegSlot(); 256 257 // Create interval with one of a NEW value number. Note that this value 258 // number isn't actually defined by an instruction, weird huh? :) 259 if (PHIJoin) { 260 assert(getInstructionFromIndex(Start) == 0 && 261 "PHI def index points at actual instruction."); 262 ValNo = interval.getNextValue(Start, VNInfoAllocator); 263 ValNo->setIsPHIDef(true); 264 } 265 LiveRange LR(Start, killIdx, ValNo); 266 interval.addRange(LR); 267 DEBUG(dbgs() << " +" << LR); 268 } 269 270 } else { 271 if (MultipleDefsBySameMI(*mi, MOIdx)) 272 // Multiple defs of the same virtual register by the same instruction. 273 // e.g. %reg1031:5<def>, %reg1031:6<def> = VLD1q16 %reg1024<kill>, ... 274 // This is likely due to elimination of REG_SEQUENCE instructions. Return 275 // here since there is nothing to do. 276 return; 277 278 // If this is the second time we see a virtual register definition, it 279 // must be due to phi elimination or two addr elimination. If this is 280 // the result of two address elimination, then the vreg is one of the 281 // def-and-use register operand. 282 283 // It may also be partial redef like this: 284 // 80 %reg1041:6<def> = VSHRNv4i16 %reg1034<kill>, 12, pred:14, pred:%reg0 285 // 120 %reg1041:5<def> = VSHRNv4i16 %reg1039<kill>, 12, pred:14, pred:%reg0 286 bool PartReDef = isPartialRedef(MIIdx, MO, interval); 287 if (PartReDef || mi->isRegTiedToUseOperand(MOIdx)) { 288 // If this is a two-address definition, then we have already processed 289 // the live range. The only problem is that we didn't realize there 290 // are actually two values in the live interval. Because of this we 291 // need to take the LiveRegion that defines this register and split it 292 // into two values. 293 SlotIndex RedefIndex = MIIdx.getRegSlot(MO.isEarlyClobber()); 294 295 const LiveRange *OldLR = 296 interval.getLiveRangeContaining(RedefIndex.getRegSlot(true)); 297 VNInfo *OldValNo = OldLR->valno; 298 SlotIndex DefIndex = OldValNo->def.getRegSlot(); 299 300 // Delete the previous value, which should be short and continuous, 301 // because the 2-addr copy must be in the same MBB as the redef. 302 interval.removeRange(DefIndex, RedefIndex); 303 304 // The new value number (#1) is defined by the instruction we claimed 305 // defined value #0. 306 VNInfo *ValNo = interval.createValueCopy(OldValNo, VNInfoAllocator); 307 308 // Value#0 is now defined by the 2-addr instruction. 309 OldValNo->def = RedefIndex; 310 311 // Add the new live interval which replaces the range for the input copy. 312 LiveRange LR(DefIndex, RedefIndex, ValNo); 313 DEBUG(dbgs() << " replace range with " << LR); 314 interval.addRange(LR); 315 316 // If this redefinition is dead, we need to add a dummy unit live 317 // range covering the def slot. 318 if (MO.isDead()) 319 interval.addRange(LiveRange(RedefIndex, RedefIndex.getDeadSlot(), 320 OldValNo)); 321 322 DEBUG({ 323 dbgs() << " RESULT: "; 324 interval.print(dbgs(), TRI); 325 }); 326 } else if (LV->isPHIJoin(interval.reg)) { 327 // In the case of PHI elimination, each variable definition is only 328 // live until the end of the block. We've already taken care of the 329 // rest of the live range. 330 331 SlotIndex defIndex = MIIdx.getRegSlot(); 332 if (MO.isEarlyClobber()) 333 defIndex = MIIdx.getRegSlot(true); 334 335 VNInfo *ValNo = interval.getNextValue(defIndex, VNInfoAllocator); 336 337 SlotIndex killIndex = getMBBEndIdx(mbb); 338 LiveRange LR(defIndex, killIndex, ValNo); 339 interval.addRange(LR); 340 ValNo->setHasPHIKill(true); 341 DEBUG(dbgs() << " phi-join +" << LR); 342 } else { 343 llvm_unreachable("Multiply defined register"); 344 } 345 } 346 347 DEBUG(dbgs() << '\n'); 348} 349 350static bool isRegLiveIntoSuccessor(const MachineBasicBlock *MBB, unsigned Reg) { 351 for (MachineBasicBlock::const_succ_iterator SI = MBB->succ_begin(), 352 SE = MBB->succ_end(); 353 SI != SE; ++SI) { 354 const MachineBasicBlock* succ = *SI; 355 if (succ->isLiveIn(Reg)) 356 return true; 357 } 358 return false; 359} 360 361void LiveIntervals::handlePhysicalRegisterDef(MachineBasicBlock *MBB, 362 MachineBasicBlock::iterator mi, 363 SlotIndex MIIdx, 364 MachineOperand& MO, 365 LiveInterval &interval) { 366 DEBUG(dbgs() << "\t\tregister: " << PrintReg(interval.reg, TRI)); 367 368 SlotIndex baseIndex = MIIdx; 369 SlotIndex start = baseIndex.getRegSlot(MO.isEarlyClobber()); 370 SlotIndex end = start; 371 372 // If it is not used after definition, it is considered dead at 373 // the instruction defining it. Hence its interval is: 374 // [defSlot(def), defSlot(def)+1) 375 // For earlyclobbers, the defSlot was pushed back one; the extra 376 // advance below compensates. 377 if (MO.isDead()) { 378 DEBUG(dbgs() << " dead"); 379 end = start.getDeadSlot(); 380 goto exit; 381 } 382 383 // If it is not dead on definition, it must be killed by a 384 // subsequent instruction. Hence its interval is: 385 // [defSlot(def), useSlot(kill)+1) 386 baseIndex = baseIndex.getNextIndex(); 387 while (++mi != MBB->end()) { 388 389 if (mi->isDebugValue()) 390 continue; 391 if (getInstructionFromIndex(baseIndex) == 0) 392 baseIndex = Indexes->getNextNonNullIndex(baseIndex); 393 394 if (mi->killsRegister(interval.reg, TRI)) { 395 DEBUG(dbgs() << " killed"); 396 end = baseIndex.getRegSlot(); 397 goto exit; 398 } else { 399 int DefIdx = mi->findRegisterDefOperandIdx(interval.reg,false,false,TRI); 400 if (DefIdx != -1) { 401 if (mi->isRegTiedToUseOperand(DefIdx)) { 402 // Two-address instruction. 403 end = baseIndex.getRegSlot(mi->getOperand(DefIdx).isEarlyClobber()); 404 } else { 405 // Another instruction redefines the register before it is ever read. 406 // Then the register is essentially dead at the instruction that 407 // defines it. Hence its interval is: 408 // [defSlot(def), defSlot(def)+1) 409 DEBUG(dbgs() << " dead"); 410 end = start.getDeadSlot(); 411 } 412 goto exit; 413 } 414 } 415 416 baseIndex = baseIndex.getNextIndex(); 417 } 418 419 // If we get here the register *should* be live out. 420 assert(!isAllocatable(interval.reg) && "Physregs shouldn't be live out!"); 421 422 // FIXME: We need saner rules for reserved regs. 423 if (isReserved(interval.reg)) { 424 end = start.getDeadSlot(); 425 } else { 426 // Unreserved, unallocable registers like EFLAGS can be live across basic 427 // block boundaries. 428 assert(isRegLiveIntoSuccessor(MBB, interval.reg) && 429 "Unreserved reg not live-out?"); 430 end = getMBBEndIdx(MBB); 431 } 432exit: 433 assert(start < end && "did not find end of interval?"); 434 435 // Already exists? Extend old live interval. 436 VNInfo *ValNo = interval.getVNInfoAt(start); 437 bool Extend = ValNo != 0; 438 if (!Extend) 439 ValNo = interval.getNextValue(start, VNInfoAllocator); 440 LiveRange LR(start, end, ValNo); 441 interval.addRange(LR); 442 DEBUG(dbgs() << " +" << LR << '\n'); 443} 444 445void LiveIntervals::handleRegisterDef(MachineBasicBlock *MBB, 446 MachineBasicBlock::iterator MI, 447 SlotIndex MIIdx, 448 MachineOperand& MO, 449 unsigned MOIdx) { 450 if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) 451 handleVirtualRegisterDef(MBB, MI, MIIdx, MO, MOIdx, 452 getOrCreateInterval(MO.getReg())); 453 else 454 handlePhysicalRegisterDef(MBB, MI, MIIdx, MO, 455 getOrCreateInterval(MO.getReg())); 456} 457 458void LiveIntervals::handleLiveInRegister(MachineBasicBlock *MBB, 459 SlotIndex MIIdx, 460 LiveInterval &interval) { 461 assert(TargetRegisterInfo::isPhysicalRegister(interval.reg) && 462 "Only physical registers can be live in."); 463 assert((!isAllocatable(interval.reg) || MBB->getParent()->begin() || 464 MBB->isLandingPad()) && 465 "Allocatable live-ins only valid for entry blocks and landing pads."); 466 467 DEBUG(dbgs() << "\t\tlivein register: " << PrintReg(interval.reg, TRI)); 468 469 // Look for kills, if it reaches a def before it's killed, then it shouldn't 470 // be considered a livein. 471 MachineBasicBlock::iterator mi = MBB->begin(); 472 MachineBasicBlock::iterator E = MBB->end(); 473 // Skip over DBG_VALUE at the start of the MBB. 474 if (mi != E && mi->isDebugValue()) { 475 while (++mi != E && mi->isDebugValue()) 476 ; 477 if (mi == E) 478 // MBB is empty except for DBG_VALUE's. 479 return; 480 } 481 482 SlotIndex baseIndex = MIIdx; 483 SlotIndex start = baseIndex; 484 if (getInstructionFromIndex(baseIndex) == 0) 485 baseIndex = Indexes->getNextNonNullIndex(baseIndex); 486 487 SlotIndex end = baseIndex; 488 bool SeenDefUse = false; 489 490 while (mi != E) { 491 if (mi->killsRegister(interval.reg, TRI)) { 492 DEBUG(dbgs() << " killed"); 493 end = baseIndex.getRegSlot(); 494 SeenDefUse = true; 495 break; 496 } else if (mi->modifiesRegister(interval.reg, TRI)) { 497 // Another instruction redefines the register before it is ever read. 498 // Then the register is essentially dead at the instruction that defines 499 // it. Hence its interval is: 500 // [defSlot(def), defSlot(def)+1) 501 DEBUG(dbgs() << " dead"); 502 end = start.getDeadSlot(); 503 SeenDefUse = true; 504 break; 505 } 506 507 while (++mi != E && mi->isDebugValue()) 508 // Skip over DBG_VALUE. 509 ; 510 if (mi != E) 511 baseIndex = Indexes->getNextNonNullIndex(baseIndex); 512 } 513 514 // Live-in register might not be used at all. 515 if (!SeenDefUse) { 516 if (isAllocatable(interval.reg) || 517 !isRegLiveIntoSuccessor(MBB, interval.reg)) { 518 // Allocatable registers are never live through. 519 // Non-allocatable registers that aren't live into any successors also 520 // aren't live through. 521 DEBUG(dbgs() << " dead"); 522 return; 523 } else { 524 // If we get here the register is non-allocatable and live into some 525 // successor. We'll conservatively assume it's live-through. 526 DEBUG(dbgs() << " live through"); 527 end = getMBBEndIdx(MBB); 528 } 529 } 530 531 SlotIndex defIdx = getMBBStartIdx(MBB); 532 assert(getInstructionFromIndex(defIdx) == 0 && 533 "PHI def index points at actual instruction."); 534 VNInfo *vni = interval.getNextValue(defIdx, VNInfoAllocator); 535 vni->setIsPHIDef(true); 536 LiveRange LR(start, end, vni); 537 538 interval.addRange(LR); 539 DEBUG(dbgs() << " +" << LR << '\n'); 540} 541 542/// computeIntervals - computes the live intervals for virtual 543/// registers. for some ordering of the machine instructions [1,N] a 544/// live interval is an interval [i, j) where 1 <= i <= j < N for 545/// which a variable is live 546void LiveIntervals::computeIntervals() { 547 DEBUG(dbgs() << "********** COMPUTING LIVE INTERVALS **********\n" 548 << "********** Function: " 549 << ((Value*)MF->getFunction())->getName() << '\n'); 550 551 RegMaskBlocks.resize(MF->getNumBlockIDs()); 552 553 SmallVector<unsigned, 8> UndefUses; 554 for (MachineFunction::iterator MBBI = MF->begin(), E = MF->end(); 555 MBBI != E; ++MBBI) { 556 MachineBasicBlock *MBB = MBBI; 557 RegMaskBlocks[MBB->getNumber()].first = RegMaskSlots.size(); 558 559 if (MBB->empty()) 560 continue; 561 562 // Track the index of the current machine instr. 563 SlotIndex MIIndex = getMBBStartIdx(MBB); 564 DEBUG(dbgs() << "BB#" << MBB->getNumber() 565 << ":\t\t# derived from " << MBB->getName() << "\n"); 566 567 // Create intervals for live-ins to this BB first. 568 for (MachineBasicBlock::livein_iterator LI = MBB->livein_begin(), 569 LE = MBB->livein_end(); LI != LE; ++LI) { 570 handleLiveInRegister(MBB, MIIndex, getOrCreateInterval(*LI)); 571 } 572 573 // Skip over empty initial indices. 574 if (getInstructionFromIndex(MIIndex) == 0) 575 MIIndex = Indexes->getNextNonNullIndex(MIIndex); 576 577 for (MachineBasicBlock::iterator MI = MBB->begin(), miEnd = MBB->end(); 578 MI != miEnd; ++MI) { 579 DEBUG(dbgs() << MIIndex << "\t" << *MI); 580 if (MI->isDebugValue()) 581 continue; 582 assert(Indexes->getInstructionFromIndex(MIIndex) == MI && 583 "Lost SlotIndex synchronization"); 584 585 // Handle defs. 586 for (int i = MI->getNumOperands() - 1; i >= 0; --i) { 587 MachineOperand &MO = MI->getOperand(i); 588 589 // Collect register masks. 590 if (MO.isRegMask()) { 591 RegMaskSlots.push_back(MIIndex.getRegSlot()); 592 RegMaskBits.push_back(MO.getRegMask()); 593 continue; 594 } 595 596 if (!MO.isReg() || !MO.getReg()) 597 continue; 598 599 // handle register defs - build intervals 600 if (MO.isDef()) 601 handleRegisterDef(MBB, MI, MIIndex, MO, i); 602 else if (MO.isUndef()) 603 UndefUses.push_back(MO.getReg()); 604 } 605 606 // Move to the next instr slot. 607 MIIndex = Indexes->getNextNonNullIndex(MIIndex); 608 } 609 610 // Compute the number of register mask instructions in this block. 611 std::pair<unsigned, unsigned> &RMB = RegMaskBlocks[MBB->getNumber()]; 612 RMB.second = RegMaskSlots.size() - RMB.first;; 613 } 614 615 // Create empty intervals for registers defined by implicit_def's (except 616 // for those implicit_def that define values which are liveout of their 617 // blocks. 618 for (unsigned i = 0, e = UndefUses.size(); i != e; ++i) { 619 unsigned UndefReg = UndefUses[i]; 620 (void)getOrCreateInterval(UndefReg); 621 } 622} 623 624LiveInterval* LiveIntervals::createInterval(unsigned reg) { 625 float Weight = TargetRegisterInfo::isPhysicalRegister(reg) ? HUGE_VALF : 0.0F; 626 return new LiveInterval(reg, Weight); 627} 628 629/// shrinkToUses - After removing some uses of a register, shrink its live 630/// range to just the remaining uses. This method does not compute reaching 631/// defs for new uses, and it doesn't remove dead defs. 632bool LiveIntervals::shrinkToUses(LiveInterval *li, 633 SmallVectorImpl<MachineInstr*> *dead) { 634 DEBUG(dbgs() << "Shrink: " << *li << '\n'); 635 assert(TargetRegisterInfo::isVirtualRegister(li->reg) 636 && "Can only shrink virtual registers"); 637 // Find all the values used, including PHI kills. 638 SmallVector<std::pair<SlotIndex, VNInfo*>, 16> WorkList; 639 640 // Blocks that have already been added to WorkList as live-out. 641 SmallPtrSet<MachineBasicBlock*, 16> LiveOut; 642 643 // Visit all instructions reading li->reg. 644 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(li->reg); 645 MachineInstr *UseMI = I.skipInstruction();) { 646 if (UseMI->isDebugValue() || !UseMI->readsVirtualRegister(li->reg)) 647 continue; 648 SlotIndex Idx = getInstructionIndex(UseMI).getRegSlot(); 649 LiveRangeQuery LRQ(*li, Idx); 650 VNInfo *VNI = LRQ.valueIn(); 651 if (!VNI) { 652 // This shouldn't happen: readsVirtualRegister returns true, but there is 653 // no live value. It is likely caused by a target getting <undef> flags 654 // wrong. 655 DEBUG(dbgs() << Idx << '\t' << *UseMI 656 << "Warning: Instr claims to read non-existent value in " 657 << *li << '\n'); 658 continue; 659 } 660 // Special case: An early-clobber tied operand reads and writes the 661 // register one slot early. 662 if (VNInfo *DefVNI = LRQ.valueDefined()) 663 Idx = DefVNI->def; 664 665 WorkList.push_back(std::make_pair(Idx, VNI)); 666 } 667 668 // Create a new live interval with only minimal live segments per def. 669 LiveInterval NewLI(li->reg, 0); 670 for (LiveInterval::vni_iterator I = li->vni_begin(), E = li->vni_end(); 671 I != E; ++I) { 672 VNInfo *VNI = *I; 673 if (VNI->isUnused()) 674 continue; 675 NewLI.addRange(LiveRange(VNI->def, VNI->def.getDeadSlot(), VNI)); 676 } 677 678 // Keep track of the PHIs that are in use. 679 SmallPtrSet<VNInfo*, 8> UsedPHIs; 680 681 // Extend intervals to reach all uses in WorkList. 682 while (!WorkList.empty()) { 683 SlotIndex Idx = WorkList.back().first; 684 VNInfo *VNI = WorkList.back().second; 685 WorkList.pop_back(); 686 const MachineBasicBlock *MBB = getMBBFromIndex(Idx.getPrevSlot()); 687 SlotIndex BlockStart = getMBBStartIdx(MBB); 688 689 // Extend the live range for VNI to be live at Idx. 690 if (VNInfo *ExtVNI = NewLI.extendInBlock(BlockStart, Idx)) { 691 (void)ExtVNI; 692 assert(ExtVNI == VNI && "Unexpected existing value number"); 693 // Is this a PHIDef we haven't seen before? 694 if (!VNI->isPHIDef() || VNI->def != BlockStart || !UsedPHIs.insert(VNI)) 695 continue; 696 // The PHI is live, make sure the predecessors are live-out. 697 for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(), 698 PE = MBB->pred_end(); PI != PE; ++PI) { 699 if (!LiveOut.insert(*PI)) 700 continue; 701 SlotIndex Stop = getMBBEndIdx(*PI); 702 // A predecessor is not required to have a live-out value for a PHI. 703 if (VNInfo *PVNI = li->getVNInfoBefore(Stop)) 704 WorkList.push_back(std::make_pair(Stop, PVNI)); 705 } 706 continue; 707 } 708 709 // VNI is live-in to MBB. 710 DEBUG(dbgs() << " live-in at " << BlockStart << '\n'); 711 NewLI.addRange(LiveRange(BlockStart, Idx, VNI)); 712 713 // Make sure VNI is live-out from the predecessors. 714 for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(), 715 PE = MBB->pred_end(); PI != PE; ++PI) { 716 if (!LiveOut.insert(*PI)) 717 continue; 718 SlotIndex Stop = getMBBEndIdx(*PI); 719 assert(li->getVNInfoBefore(Stop) == VNI && 720 "Wrong value out of predecessor"); 721 WorkList.push_back(std::make_pair(Stop, VNI)); 722 } 723 } 724 725 // Handle dead values. 726 bool CanSeparate = false; 727 for (LiveInterval::vni_iterator I = li->vni_begin(), E = li->vni_end(); 728 I != E; ++I) { 729 VNInfo *VNI = *I; 730 if (VNI->isUnused()) 731 continue; 732 LiveInterval::iterator LII = NewLI.FindLiveRangeContaining(VNI->def); 733 assert(LII != NewLI.end() && "Missing live range for PHI"); 734 if (LII->end != VNI->def.getDeadSlot()) 735 continue; 736 if (VNI->isPHIDef()) { 737 // This is a dead PHI. Remove it. 738 VNI->setIsUnused(true); 739 NewLI.removeRange(*LII); 740 DEBUG(dbgs() << "Dead PHI at " << VNI->def << " may separate interval\n"); 741 CanSeparate = true; 742 } else { 743 // This is a dead def. Make sure the instruction knows. 744 MachineInstr *MI = getInstructionFromIndex(VNI->def); 745 assert(MI && "No instruction defining live value"); 746 MI->addRegisterDead(li->reg, TRI); 747 if (dead && MI->allDefsAreDead()) { 748 DEBUG(dbgs() << "All defs dead: " << VNI->def << '\t' << *MI); 749 dead->push_back(MI); 750 } 751 } 752 } 753 754 // Move the trimmed ranges back. 755 li->ranges.swap(NewLI.ranges); 756 DEBUG(dbgs() << "Shrunk: " << *li << '\n'); 757 return CanSeparate; 758} 759 760 761//===----------------------------------------------------------------------===// 762// Register allocator hooks. 763// 764 765void LiveIntervals::addKillFlags() { 766 for (iterator I = begin(), E = end(); I != E; ++I) { 767 unsigned Reg = I->first; 768 if (TargetRegisterInfo::isPhysicalRegister(Reg)) 769 continue; 770 if (MRI->reg_nodbg_empty(Reg)) 771 continue; 772 LiveInterval *LI = I->second; 773 774 // Every instruction that kills Reg corresponds to a live range end point. 775 for (LiveInterval::iterator RI = LI->begin(), RE = LI->end(); RI != RE; 776 ++RI) { 777 // A block index indicates an MBB edge. 778 if (RI->end.isBlock()) 779 continue; 780 MachineInstr *MI = getInstructionFromIndex(RI->end); 781 if (!MI) 782 continue; 783 MI->addRegisterKilled(Reg, NULL); 784 } 785 } 786} 787 788/// getReMatImplicitUse - If the remat definition MI has one (for now, we only 789/// allow one) virtual register operand, then its uses are implicitly using 790/// the register. Returns the virtual register. 791unsigned LiveIntervals::getReMatImplicitUse(const LiveInterval &li, 792 MachineInstr *MI) const { 793 unsigned RegOp = 0; 794 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 795 MachineOperand &MO = MI->getOperand(i); 796 if (!MO.isReg() || !MO.isUse()) 797 continue; 798 unsigned Reg = MO.getReg(); 799 if (Reg == 0 || Reg == li.reg) 800 continue; 801 802 if (TargetRegisterInfo::isPhysicalRegister(Reg) && !isAllocatable(Reg)) 803 continue; 804 RegOp = MO.getReg(); 805 break; // Found vreg operand - leave the loop. 806 } 807 return RegOp; 808} 809 810/// isValNoAvailableAt - Return true if the val# of the specified interval 811/// which reaches the given instruction also reaches the specified use index. 812bool LiveIntervals::isValNoAvailableAt(const LiveInterval &li, MachineInstr *MI, 813 SlotIndex UseIdx) const { 814 VNInfo *UValNo = li.getVNInfoAt(UseIdx); 815 return UValNo && UValNo == li.getVNInfoAt(getInstructionIndex(MI)); 816} 817 818/// isReMaterializable - Returns true if the definition MI of the specified 819/// val# of the specified interval is re-materializable. 820bool 821LiveIntervals::isReMaterializable(const LiveInterval &li, 822 const VNInfo *ValNo, MachineInstr *MI, 823 const SmallVectorImpl<LiveInterval*> *SpillIs, 824 bool &isLoad) { 825 if (DisableReMat) 826 return false; 827 828 if (!TII->isTriviallyReMaterializable(MI, AA)) 829 return false; 830 831 // Target-specific code can mark an instruction as being rematerializable 832 // if it has one virtual reg use, though it had better be something like 833 // a PIC base register which is likely to be live everywhere. 834 unsigned ImpUse = getReMatImplicitUse(li, MI); 835 if (ImpUse) { 836 const LiveInterval &ImpLi = getInterval(ImpUse); 837 for (MachineRegisterInfo::use_nodbg_iterator 838 ri = MRI->use_nodbg_begin(li.reg), re = MRI->use_nodbg_end(); 839 ri != re; ++ri) { 840 MachineInstr *UseMI = &*ri; 841 SlotIndex UseIdx = getInstructionIndex(UseMI); 842 if (li.getVNInfoAt(UseIdx) != ValNo) 843 continue; 844 if (!isValNoAvailableAt(ImpLi, MI, UseIdx)) 845 return false; 846 } 847 848 // If a register operand of the re-materialized instruction is going to 849 // be spilled next, then it's not legal to re-materialize this instruction. 850 if (SpillIs) 851 for (unsigned i = 0, e = SpillIs->size(); i != e; ++i) 852 if (ImpUse == (*SpillIs)[i]->reg) 853 return false; 854 } 855 return true; 856} 857 858/// isReMaterializable - Returns true if every definition of MI of every 859/// val# of the specified interval is re-materializable. 860bool 861LiveIntervals::isReMaterializable(const LiveInterval &li, 862 const SmallVectorImpl<LiveInterval*> *SpillIs, 863 bool &isLoad) { 864 isLoad = false; 865 for (LiveInterval::const_vni_iterator i = li.vni_begin(), e = li.vni_end(); 866 i != e; ++i) { 867 const VNInfo *VNI = *i; 868 if (VNI->isUnused()) 869 continue; // Dead val#. 870 // Is the def for the val# rematerializable? 871 MachineInstr *ReMatDefMI = getInstructionFromIndex(VNI->def); 872 if (!ReMatDefMI) 873 return false; 874 bool DefIsLoad = false; 875 if (!ReMatDefMI || 876 !isReMaterializable(li, VNI, ReMatDefMI, SpillIs, DefIsLoad)) 877 return false; 878 isLoad |= DefIsLoad; 879 } 880 return true; 881} 882 883MachineBasicBlock* 884LiveIntervals::intervalIsInOneMBB(const LiveInterval &LI) const { 885 // A local live range must be fully contained inside the block, meaning it is 886 // defined and killed at instructions, not at block boundaries. It is not 887 // live in or or out of any block. 888 // 889 // It is technically possible to have a PHI-defined live range identical to a 890 // single block, but we are going to return false in that case. 891 892 SlotIndex Start = LI.beginIndex(); 893 if (Start.isBlock()) 894 return NULL; 895 896 SlotIndex Stop = LI.endIndex(); 897 if (Stop.isBlock()) 898 return NULL; 899 900 // getMBBFromIndex doesn't need to search the MBB table when both indexes 901 // belong to proper instructions. 902 MachineBasicBlock *MBB1 = Indexes->getMBBFromIndex(Start); 903 MachineBasicBlock *MBB2 = Indexes->getMBBFromIndex(Stop); 904 return MBB1 == MBB2 ? MBB1 : NULL; 905} 906 907float 908LiveIntervals::getSpillWeight(bool isDef, bool isUse, unsigned loopDepth) { 909 // Limit the loop depth ridiculousness. 910 if (loopDepth > 200) 911 loopDepth = 200; 912 913 // The loop depth is used to roughly estimate the number of times the 914 // instruction is executed. Something like 10^d is simple, but will quickly 915 // overflow a float. This expression behaves like 10^d for small d, but is 916 // more tempered for large d. At d=200 we get 6.7e33 which leaves a bit of 917 // headroom before overflow. 918 // By the way, powf() might be unavailable here. For consistency, 919 // We may take pow(double,double). 920 float lc = std::pow(1 + (100.0 / (loopDepth + 10)), (double)loopDepth); 921 922 return (isDef + isUse) * lc; 923} 924 925LiveRange LiveIntervals::addLiveRangeToEndOfBlock(unsigned reg, 926 MachineInstr* startInst) { 927 LiveInterval& Interval = getOrCreateInterval(reg); 928 VNInfo* VN = Interval.getNextValue( 929 SlotIndex(getInstructionIndex(startInst).getRegSlot()), 930 getVNInfoAllocator()); 931 VN->setHasPHIKill(true); 932 LiveRange LR( 933 SlotIndex(getInstructionIndex(startInst).getRegSlot()), 934 getMBBEndIdx(startInst->getParent()), VN); 935 Interval.addRange(LR); 936 937 return LR; 938} 939 940 941//===----------------------------------------------------------------------===// 942// Register mask functions 943//===----------------------------------------------------------------------===// 944 945bool LiveIntervals::checkRegMaskInterference(LiveInterval &LI, 946 BitVector &UsableRegs) { 947 if (LI.empty()) 948 return false; 949 LiveInterval::iterator LiveI = LI.begin(), LiveE = LI.end(); 950 951 // Use a smaller arrays for local live ranges. 952 ArrayRef<SlotIndex> Slots; 953 ArrayRef<const uint32_t*> Bits; 954 if (MachineBasicBlock *MBB = intervalIsInOneMBB(LI)) { 955 Slots = getRegMaskSlotsInBlock(MBB->getNumber()); 956 Bits = getRegMaskBitsInBlock(MBB->getNumber()); 957 } else { 958 Slots = getRegMaskSlots(); 959 Bits = getRegMaskBits(); 960 } 961 962 // We are going to enumerate all the register mask slots contained in LI. 963 // Start with a binary search of RegMaskSlots to find a starting point. 964 ArrayRef<SlotIndex>::iterator SlotI = 965 std::lower_bound(Slots.begin(), Slots.end(), LiveI->start); 966 ArrayRef<SlotIndex>::iterator SlotE = Slots.end(); 967 968 // No slots in range, LI begins after the last call. 969 if (SlotI == SlotE) 970 return false; 971 972 bool Found = false; 973 for (;;) { 974 assert(*SlotI >= LiveI->start); 975 // Loop over all slots overlapping this segment. 976 while (*SlotI < LiveI->end) { 977 // *SlotI overlaps LI. Collect mask bits. 978 if (!Found) { 979 // This is the first overlap. Initialize UsableRegs to all ones. 980 UsableRegs.clear(); 981 UsableRegs.resize(TRI->getNumRegs(), true); 982 Found = true; 983 } 984 // Remove usable registers clobbered by this mask. 985 UsableRegs.clearBitsNotInMask(Bits[SlotI-Slots.begin()]); 986 if (++SlotI == SlotE) 987 return Found; 988 } 989 // *SlotI is beyond the current LI segment. 990 LiveI = LI.advanceTo(LiveI, *SlotI); 991 if (LiveI == LiveE) 992 return Found; 993 // Advance SlotI until it overlaps. 994 while (*SlotI < LiveI->start) 995 if (++SlotI == SlotE) 996 return Found; 997 } 998} 999 1000//===----------------------------------------------------------------------===// 1001// IntervalUpdate class. 1002//===----------------------------------------------------------------------===// 1003 1004// HMEditor is a toolkit used by handleMove to trim or extend live intervals. 1005class LiveIntervals::HMEditor { 1006private: 1007 LiveIntervals& LIS; 1008 const MachineRegisterInfo& MRI; 1009 const TargetRegisterInfo& TRI; 1010 SlotIndex NewIdx; 1011 1012 typedef std::pair<LiveInterval*, LiveRange*> IntRangePair; 1013 typedef DenseSet<IntRangePair> RangeSet; 1014 1015 struct RegRanges { 1016 LiveRange* Use; 1017 LiveRange* EC; 1018 LiveRange* Dead; 1019 LiveRange* Def; 1020 RegRanges() : Use(0), EC(0), Dead(0), Def(0) {} 1021 }; 1022 typedef DenseMap<unsigned, RegRanges> BundleRanges; 1023 1024public: 1025 HMEditor(LiveIntervals& LIS, const MachineRegisterInfo& MRI, 1026 const TargetRegisterInfo& TRI, SlotIndex NewIdx) 1027 : LIS(LIS), MRI(MRI), TRI(TRI), NewIdx(NewIdx) {} 1028 1029 // Update intervals for all operands of MI from OldIdx to NewIdx. 1030 // This assumes that MI used to be at OldIdx, and now resides at 1031 // NewIdx. 1032 void moveAllRangesFrom(MachineInstr* MI, SlotIndex OldIdx) { 1033 assert(NewIdx != OldIdx && "No-op move? That's a bit strange."); 1034 1035 // Collect the operands. 1036 RangeSet Entering, Internal, Exiting; 1037 bool hasRegMaskOp = false; 1038 collectRanges(MI, Entering, Internal, Exiting, hasRegMaskOp, OldIdx); 1039 1040 // To keep the LiveRanges valid within an interval, move the ranges closest 1041 // to the destination first. This prevents ranges from overlapping, to that 1042 // APIs like removeRange still work. 1043 if (NewIdx < OldIdx) { 1044 moveAllEnteringFrom(OldIdx, Entering); 1045 moveAllInternalFrom(OldIdx, Internal); 1046 moveAllExitingFrom(OldIdx, Exiting); 1047 } 1048 else { 1049 moveAllExitingFrom(OldIdx, Exiting); 1050 moveAllInternalFrom(OldIdx, Internal); 1051 moveAllEnteringFrom(OldIdx, Entering); 1052 } 1053 1054 if (hasRegMaskOp) 1055 updateRegMaskSlots(OldIdx); 1056 1057#ifndef NDEBUG 1058 LIValidator validator; 1059 validator = std::for_each(Entering.begin(), Entering.end(), validator); 1060 validator = std::for_each(Internal.begin(), Internal.end(), validator); 1061 validator = std::for_each(Exiting.begin(), Exiting.end(), validator); 1062 assert(validator.rangesOk() && "moveAllOperandsFrom broke liveness."); 1063#endif 1064 1065 } 1066 1067 // Update intervals for all operands of MI to refer to BundleStart's 1068 // SlotIndex. 1069 void moveAllRangesInto(MachineInstr* MI, MachineInstr* BundleStart) { 1070 if (MI == BundleStart) 1071 return; // Bundling instr with itself - nothing to do. 1072 1073 SlotIndex OldIdx = LIS.getSlotIndexes()->getInstructionIndex(MI); 1074 assert(LIS.getSlotIndexes()->getInstructionFromIndex(OldIdx) == MI && 1075 "SlotIndex <-> Instruction mapping broken for MI"); 1076 1077 // Collect all ranges already in the bundle. 1078 MachineBasicBlock::instr_iterator BII(BundleStart); 1079 RangeSet Entering, Internal, Exiting; 1080 bool hasRegMaskOp = false; 1081 collectRanges(BII, Entering, Internal, Exiting, hasRegMaskOp, NewIdx); 1082 assert(!hasRegMaskOp && "Can't have RegMask operand in bundle."); 1083 for (++BII; &*BII == MI || BII->isInsideBundle(); ++BII) { 1084 if (&*BII == MI) 1085 continue; 1086 collectRanges(BII, Entering, Internal, Exiting, hasRegMaskOp, NewIdx); 1087 assert(!hasRegMaskOp && "Can't have RegMask operand in bundle."); 1088 } 1089 1090 BundleRanges BR = createBundleRanges(Entering, Internal, Exiting); 1091 1092 Entering.clear(); 1093 Internal.clear(); 1094 Exiting.clear(); 1095 collectRanges(MI, Entering, Internal, Exiting, hasRegMaskOp, OldIdx); 1096 assert(!hasRegMaskOp && "Can't have RegMask operand in bundle."); 1097 1098 DEBUG(dbgs() << "Entering: " << Entering.size() << "\n"); 1099 DEBUG(dbgs() << "Internal: " << Internal.size() << "\n"); 1100 DEBUG(dbgs() << "Exiting: " << Exiting.size() << "\n"); 1101 1102 moveAllEnteringFromInto(OldIdx, Entering, BR); 1103 moveAllInternalFromInto(OldIdx, Internal, BR); 1104 moveAllExitingFromInto(OldIdx, Exiting, BR); 1105 1106 1107#ifndef NDEBUG 1108 LIValidator validator; 1109 validator = std::for_each(Entering.begin(), Entering.end(), validator); 1110 validator = std::for_each(Internal.begin(), Internal.end(), validator); 1111 validator = std::for_each(Exiting.begin(), Exiting.end(), validator); 1112 assert(validator.rangesOk() && "moveAllOperandsInto broke liveness."); 1113#endif 1114 } 1115 1116private: 1117 1118#ifndef NDEBUG 1119 class LIValidator { 1120 private: 1121 DenseSet<const LiveInterval*> Checked, Bogus; 1122 public: 1123 void operator()(const IntRangePair& P) { 1124 const LiveInterval* LI = P.first; 1125 if (Checked.count(LI)) 1126 return; 1127 Checked.insert(LI); 1128 if (LI->empty()) 1129 return; 1130 SlotIndex LastEnd = LI->begin()->start; 1131 for (LiveInterval::const_iterator LRI = LI->begin(), LRE = LI->end(); 1132 LRI != LRE; ++LRI) { 1133 const LiveRange& LR = *LRI; 1134 if (LastEnd > LR.start || LR.start >= LR.end) 1135 Bogus.insert(LI); 1136 LastEnd = LR.end; 1137 } 1138 } 1139 1140 bool rangesOk() const { 1141 return Bogus.empty(); 1142 } 1143 }; 1144#endif 1145 1146 // Collect IntRangePairs for all operands of MI that may need fixing. 1147 // Treat's MI's index as OldIdx (regardless of what it is in SlotIndexes' 1148 // maps). 1149 void collectRanges(MachineInstr* MI, RangeSet& Entering, RangeSet& Internal, 1150 RangeSet& Exiting, bool& hasRegMaskOp, SlotIndex OldIdx) { 1151 hasRegMaskOp = false; 1152 for (MachineInstr::mop_iterator MOI = MI->operands_begin(), 1153 MOE = MI->operands_end(); 1154 MOI != MOE; ++MOI) { 1155 const MachineOperand& MO = *MOI; 1156 1157 if (MO.isRegMask()) { 1158 hasRegMaskOp = true; 1159 continue; 1160 } 1161 1162 if (!MO.isReg() || MO.getReg() == 0) 1163 continue; 1164 1165 unsigned Reg = MO.getReg(); 1166 1167 // TODO: Currently we're skipping uses that are reserved or have no 1168 // interval, but we're not updating their kills. This should be 1169 // fixed. 1170 if (!LIS.hasInterval(Reg) || 1171 (TargetRegisterInfo::isPhysicalRegister(Reg) && LIS.isReserved(Reg))) 1172 continue; 1173 1174 LiveInterval* LI = &LIS.getInterval(Reg); 1175 1176 if (MO.readsReg()) { 1177 LiveRange* LR = LI->getLiveRangeContaining(OldIdx); 1178 if (LR != 0) 1179 Entering.insert(std::make_pair(LI, LR)); 1180 } 1181 if (MO.isDef()) { 1182 if (MO.isEarlyClobber()) { 1183 LiveRange* LR = LI->getLiveRangeContaining(OldIdx.getRegSlot(true)); 1184 assert(LR != 0 && "No EC range?"); 1185 if (LR->end > OldIdx.getDeadSlot()) 1186 Exiting.insert(std::make_pair(LI, LR)); 1187 else 1188 Internal.insert(std::make_pair(LI, LR)); 1189 } else if (MO.isDead()) { 1190 LiveRange* LR = LI->getLiveRangeContaining(OldIdx.getRegSlot()); 1191 assert(LR != 0 && "No dead-def range?"); 1192 Internal.insert(std::make_pair(LI, LR)); 1193 } else { 1194 LiveRange* LR = LI->getLiveRangeContaining(OldIdx.getDeadSlot()); 1195 assert(LR && LR->end > OldIdx.getDeadSlot() && 1196 "Non-dead-def should have live range exiting."); 1197 Exiting.insert(std::make_pair(LI, LR)); 1198 } 1199 } 1200 } 1201 } 1202 1203 // Collect IntRangePairs for all operands of MI that may need fixing. 1204 void collectRangesInBundle(MachineInstr* MI, RangeSet& Entering, 1205 RangeSet& Exiting, SlotIndex MIStartIdx, 1206 SlotIndex MIEndIdx) { 1207 for (MachineInstr::mop_iterator MOI = MI->operands_begin(), 1208 MOE = MI->operands_end(); 1209 MOI != MOE; ++MOI) { 1210 const MachineOperand& MO = *MOI; 1211 assert(!MO.isRegMask() && "Can't have RegMasks in bundles."); 1212 if (!MO.isReg() || MO.getReg() == 0) 1213 continue; 1214 1215 unsigned Reg = MO.getReg(); 1216 1217 // TODO: Currently we're skipping uses that are reserved or have no 1218 // interval, but we're not updating their kills. This should be 1219 // fixed. 1220 if (!LIS.hasInterval(Reg) || 1221 (TargetRegisterInfo::isPhysicalRegister(Reg) && LIS.isReserved(Reg))) 1222 continue; 1223 1224 LiveInterval* LI = &LIS.getInterval(Reg); 1225 1226 if (MO.readsReg()) { 1227 LiveRange* LR = LI->getLiveRangeContaining(MIStartIdx); 1228 if (LR != 0) 1229 Entering.insert(std::make_pair(LI, LR)); 1230 } 1231 if (MO.isDef()) { 1232 assert(!MO.isEarlyClobber() && "Early clobbers not allowed in bundles."); 1233 assert(!MO.isDead() && "Dead-defs not allowed in bundles."); 1234 LiveRange* LR = LI->getLiveRangeContaining(MIEndIdx.getDeadSlot()); 1235 assert(LR != 0 && "Internal ranges not allowed in bundles."); 1236 Exiting.insert(std::make_pair(LI, LR)); 1237 } 1238 } 1239 } 1240 1241 BundleRanges createBundleRanges(RangeSet& Entering, RangeSet& Internal, RangeSet& Exiting) { 1242 BundleRanges BR; 1243 1244 for (RangeSet::iterator EI = Entering.begin(), EE = Entering.end(); 1245 EI != EE; ++EI) { 1246 LiveInterval* LI = EI->first; 1247 LiveRange* LR = EI->second; 1248 BR[LI->reg].Use = LR; 1249 } 1250 1251 for (RangeSet::iterator II = Internal.begin(), IE = Internal.end(); 1252 II != IE; ++II) { 1253 LiveInterval* LI = II->first; 1254 LiveRange* LR = II->second; 1255 if (LR->end.isDead()) { 1256 BR[LI->reg].Dead = LR; 1257 } else { 1258 BR[LI->reg].EC = LR; 1259 } 1260 } 1261 1262 for (RangeSet::iterator EI = Exiting.begin(), EE = Exiting.end(); 1263 EI != EE; ++EI) { 1264 LiveInterval* LI = EI->first; 1265 LiveRange* LR = EI->second; 1266 BR[LI->reg].Def = LR; 1267 } 1268 1269 return BR; 1270 } 1271 1272 void moveKillFlags(unsigned reg, SlotIndex OldIdx, SlotIndex newKillIdx) { 1273 MachineInstr* OldKillMI = LIS.getInstructionFromIndex(OldIdx); 1274 if (!OldKillMI->killsRegister(reg)) 1275 return; // Bail out if we don't have kill flags on the old register. 1276 MachineInstr* NewKillMI = LIS.getInstructionFromIndex(newKillIdx); 1277 assert(OldKillMI->killsRegister(reg) && "Old 'kill' instr isn't a kill."); 1278 assert(!NewKillMI->killsRegister(reg) && "New kill instr is already a kill."); 1279 OldKillMI->clearRegisterKills(reg, &TRI); 1280 NewKillMI->addRegisterKilled(reg, &TRI); 1281 } 1282 1283 void updateRegMaskSlots(SlotIndex OldIdx) { 1284 SmallVectorImpl<SlotIndex>::iterator RI = 1285 std::lower_bound(LIS.RegMaskSlots.begin(), LIS.RegMaskSlots.end(), 1286 OldIdx); 1287 assert(*RI == OldIdx && "No RegMask at OldIdx."); 1288 *RI = NewIdx; 1289 assert(*prior(RI) < *RI && *RI < *next(RI) && 1290 "RegSlots out of order. Did you move one call across another?"); 1291 } 1292 1293 // Return the last use of reg between NewIdx and OldIdx. 1294 SlotIndex findLastUseBefore(unsigned Reg, SlotIndex OldIdx) { 1295 SlotIndex LastUse = NewIdx; 1296 for (MachineRegisterInfo::use_nodbg_iterator 1297 UI = MRI.use_nodbg_begin(Reg), 1298 UE = MRI.use_nodbg_end(); 1299 UI != UE; UI.skipInstruction()) { 1300 const MachineInstr* MI = &*UI; 1301 SlotIndex InstSlot = LIS.getSlotIndexes()->getInstructionIndex(MI); 1302 if (InstSlot > LastUse && InstSlot < OldIdx) 1303 LastUse = InstSlot; 1304 } 1305 return LastUse; 1306 } 1307 1308 void moveEnteringUpFrom(SlotIndex OldIdx, IntRangePair& P) { 1309 LiveInterval* LI = P.first; 1310 LiveRange* LR = P.second; 1311 bool LiveThrough = LR->end > OldIdx.getRegSlot(); 1312 if (LiveThrough) 1313 return; 1314 SlotIndex LastUse = findLastUseBefore(LI->reg, OldIdx); 1315 if (LastUse != NewIdx) 1316 moveKillFlags(LI->reg, NewIdx, LastUse); 1317 LR->end = LastUse.getRegSlot(); 1318 } 1319 1320 void moveEnteringDownFrom(SlotIndex OldIdx, IntRangePair& P) { 1321 LiveInterval* LI = P.first; 1322 LiveRange* LR = P.second; 1323 // Extend the LiveRange if NewIdx is past the end. 1324 if (NewIdx > LR->end) { 1325 // Move kill flags if OldIdx was not originally the end 1326 // (otherwise LR->end points to an invalid slot). 1327 if (LR->end.getRegSlot() != OldIdx.getRegSlot()) { 1328 assert(LR->end > OldIdx && "LiveRange does not cover original slot"); 1329 moveKillFlags(LI->reg, LR->end, NewIdx); 1330 } 1331 LR->end = NewIdx.getRegSlot(); 1332 } 1333 } 1334 1335 void moveAllEnteringFrom(SlotIndex OldIdx, RangeSet& Entering) { 1336 bool GoingUp = NewIdx < OldIdx; 1337 1338 if (GoingUp) { 1339 for (RangeSet::iterator EI = Entering.begin(), EE = Entering.end(); 1340 EI != EE; ++EI) 1341 moveEnteringUpFrom(OldIdx, *EI); 1342 } else { 1343 for (RangeSet::iterator EI = Entering.begin(), EE = Entering.end(); 1344 EI != EE; ++EI) 1345 moveEnteringDownFrom(OldIdx, *EI); 1346 } 1347 } 1348 1349 void moveInternalFrom(SlotIndex OldIdx, IntRangePair& P) { 1350 LiveInterval* LI = P.first; 1351 LiveRange* LR = P.second; 1352 assert(OldIdx < LR->start && LR->start < OldIdx.getDeadSlot() && 1353 LR->end <= OldIdx.getDeadSlot() && 1354 "Range should be internal to OldIdx."); 1355 LiveRange Tmp(*LR); 1356 Tmp.start = NewIdx.getRegSlot(LR->start.isEarlyClobber()); 1357 Tmp.valno->def = Tmp.start; 1358 Tmp.end = LR->end.isDead() ? NewIdx.getDeadSlot() : NewIdx.getRegSlot(); 1359 LI->removeRange(*LR); 1360 LI->addRange(Tmp); 1361 } 1362 1363 void moveAllInternalFrom(SlotIndex OldIdx, RangeSet& Internal) { 1364 for (RangeSet::iterator II = Internal.begin(), IE = Internal.end(); 1365 II != IE; ++II) 1366 moveInternalFrom(OldIdx, *II); 1367 } 1368 1369 void moveExitingFrom(SlotIndex OldIdx, IntRangePair& P) { 1370 LiveRange* LR = P.second; 1371 assert(OldIdx < LR->start && LR->start < OldIdx.getDeadSlot() && 1372 "Range should start in OldIdx."); 1373 assert(LR->end > OldIdx.getDeadSlot() && "Range should exit OldIdx."); 1374 SlotIndex NewStart = NewIdx.getRegSlot(LR->start.isEarlyClobber()); 1375 LR->start = NewStart; 1376 LR->valno->def = NewStart; 1377 } 1378 1379 void moveAllExitingFrom(SlotIndex OldIdx, RangeSet& Exiting) { 1380 for (RangeSet::iterator EI = Exiting.begin(), EE = Exiting.end(); 1381 EI != EE; ++EI) 1382 moveExitingFrom(OldIdx, *EI); 1383 } 1384 1385 void moveEnteringUpFromInto(SlotIndex OldIdx, IntRangePair& P, 1386 BundleRanges& BR) { 1387 LiveInterval* LI = P.first; 1388 LiveRange* LR = P.second; 1389 bool LiveThrough = LR->end > OldIdx.getRegSlot(); 1390 if (LiveThrough) { 1391 assert((LR->start < NewIdx || BR[LI->reg].Def == LR) && 1392 "Def in bundle should be def range."); 1393 assert((BR[LI->reg].Use == 0 || BR[LI->reg].Use == LR) && 1394 "If bundle has use for this reg it should be LR."); 1395 BR[LI->reg].Use = LR; 1396 return; 1397 } 1398 1399 SlotIndex LastUse = findLastUseBefore(LI->reg, OldIdx); 1400 moveKillFlags(LI->reg, OldIdx, LastUse); 1401 1402 if (LR->start < NewIdx) { 1403 // Becoming a new entering range. 1404 assert(BR[LI->reg].Dead == 0 && BR[LI->reg].Def == 0 && 1405 "Bundle shouldn't be re-defining reg mid-range."); 1406 assert((BR[LI->reg].Use == 0 || BR[LI->reg].Use == LR) && 1407 "Bundle shouldn't have different use range for same reg."); 1408 LR->end = LastUse.getRegSlot(); 1409 BR[LI->reg].Use = LR; 1410 } else { 1411 // Becoming a new Dead-def. 1412 assert(LR->start == NewIdx.getRegSlot(LR->start.isEarlyClobber()) && 1413 "Live range starting at unexpected slot."); 1414 assert(BR[LI->reg].Def == LR && "Reg should have def range."); 1415 assert(BR[LI->reg].Dead == 0 && 1416 "Can't have def and dead def of same reg in a bundle."); 1417 LR->end = LastUse.getDeadSlot(); 1418 BR[LI->reg].Dead = BR[LI->reg].Def; 1419 BR[LI->reg].Def = 0; 1420 } 1421 } 1422 1423 void moveEnteringDownFromInto(SlotIndex OldIdx, IntRangePair& P, 1424 BundleRanges& BR) { 1425 LiveInterval* LI = P.first; 1426 LiveRange* LR = P.second; 1427 if (NewIdx > LR->end) { 1428 // Range extended to bundle. Add to bundle uses. 1429 // Note: Currently adds kill flags to bundle start. 1430 assert(BR[LI->reg].Use == 0 && 1431 "Bundle already has use range for reg."); 1432 moveKillFlags(LI->reg, LR->end, NewIdx); 1433 LR->end = NewIdx.getRegSlot(); 1434 BR[LI->reg].Use = LR; 1435 } else { 1436 assert(BR[LI->reg].Use != 0 && 1437 "Bundle should already have a use range for reg."); 1438 } 1439 } 1440 1441 void moveAllEnteringFromInto(SlotIndex OldIdx, RangeSet& Entering, 1442 BundleRanges& BR) { 1443 bool GoingUp = NewIdx < OldIdx; 1444 1445 if (GoingUp) { 1446 for (RangeSet::iterator EI = Entering.begin(), EE = Entering.end(); 1447 EI != EE; ++EI) 1448 moveEnteringUpFromInto(OldIdx, *EI, BR); 1449 } else { 1450 for (RangeSet::iterator EI = Entering.begin(), EE = Entering.end(); 1451 EI != EE; ++EI) 1452 moveEnteringDownFromInto(OldIdx, *EI, BR); 1453 } 1454 } 1455 1456 void moveInternalFromInto(SlotIndex OldIdx, IntRangePair& P, 1457 BundleRanges& BR) { 1458 // TODO: Sane rules for moving ranges into bundles. 1459 } 1460 1461 void moveAllInternalFromInto(SlotIndex OldIdx, RangeSet& Internal, 1462 BundleRanges& BR) { 1463 for (RangeSet::iterator II = Internal.begin(), IE = Internal.end(); 1464 II != IE; ++II) 1465 moveInternalFromInto(OldIdx, *II, BR); 1466 } 1467 1468 void moveExitingFromInto(SlotIndex OldIdx, IntRangePair& P, 1469 BundleRanges& BR) { 1470 LiveInterval* LI = P.first; 1471 LiveRange* LR = P.second; 1472 1473 assert(LR->start.isRegister() && 1474 "Don't know how to merge exiting ECs into bundles yet."); 1475 1476 if (LR->end > NewIdx.getDeadSlot()) { 1477 // This range is becoming an exiting range on the bundle. 1478 // If there was an old dead-def of this reg, delete it. 1479 if (BR[LI->reg].Dead != 0) { 1480 LI->removeRange(*BR[LI->reg].Dead); 1481 BR[LI->reg].Dead = 0; 1482 } 1483 assert(BR[LI->reg].Def == 0 && 1484 "Can't have two defs for the same variable exiting a bundle."); 1485 LR->start = NewIdx.getRegSlot(); 1486 LR->valno->def = LR->start; 1487 BR[LI->reg].Def = LR; 1488 } else { 1489 // This range is becoming internal to the bundle. 1490 assert(LR->end == NewIdx.getRegSlot() && 1491 "Can't bundle def whose kill is before the bundle"); 1492 if (BR[LI->reg].Dead || BR[LI->reg].Def) { 1493 // Already have a def for this. Just delete range. 1494 LI->removeRange(*LR); 1495 } else { 1496 // Make range dead, record. 1497 LR->end = NewIdx.getDeadSlot(); 1498 BR[LI->reg].Dead = LR; 1499 assert(BR[LI->reg].Use == LR && 1500 "Range becoming dead should currently be use."); 1501 } 1502 // In both cases the range is no longer a use on the bundle. 1503 BR[LI->reg].Use = 0; 1504 } 1505 } 1506 1507 void moveAllExitingFromInto(SlotIndex OldIdx, RangeSet& Exiting, 1508 BundleRanges& BR) { 1509 for (RangeSet::iterator EI = Exiting.begin(), EE = Exiting.end(); 1510 EI != EE; ++EI) 1511 moveExitingFromInto(OldIdx, *EI, BR); 1512 } 1513 1514}; 1515 1516void LiveIntervals::handleMove(MachineInstr* MI) { 1517 SlotIndex OldIndex = Indexes->getInstructionIndex(MI); 1518 Indexes->removeMachineInstrFromMaps(MI); 1519 SlotIndex NewIndex = MI->isInsideBundle() ? 1520 Indexes->getInstructionIndex(MI) : 1521 Indexes->insertMachineInstrInMaps(MI); 1522 assert(getMBBStartIdx(MI->getParent()) <= OldIndex && 1523 OldIndex < getMBBEndIdx(MI->getParent()) && 1524 "Cannot handle moves across basic block boundaries."); 1525 assert(!MI->isBundled() && "Can't handle bundled instructions yet."); 1526 1527 HMEditor HME(*this, *MRI, *TRI, NewIndex); 1528 HME.moveAllRangesFrom(MI, OldIndex); 1529} 1530 1531void LiveIntervals::handleMoveIntoBundle(MachineInstr* MI, MachineInstr* BundleStart) { 1532 SlotIndex NewIndex = Indexes->getInstructionIndex(BundleStart); 1533 HMEditor HME(*this, *MRI, *TRI, NewIndex); 1534 HME.moveAllRangesInto(MI, BundleStart); 1535} 1536