LiveIntervalAnalysis.cpp revision ef0543689ff90337af358add9dad74a1e23e9d74
1//===-- LiveIntervalAnalysis.cpp - Live Interval Analysis -----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the LiveInterval analysis pass which is used 11// by the Linear Scan Register allocator. This pass linearizes the 12// basic blocks of the function in DFS order and uses the 13// LiveVariables pass to conservatively compute live intervals for 14// each virtual and physical register. 15// 16//===----------------------------------------------------------------------===// 17 18#define DEBUG_TYPE "liveintervals" 19#include "LiveIntervalAnalysis.h" 20#include "VirtRegMap.h" 21#include "llvm/Value.h" 22#include "llvm/Analysis/LoopInfo.h" 23#include "llvm/CodeGen/LiveVariables.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/MachineInstr.h" 26#include "llvm/CodeGen/Passes.h" 27#include "llvm/CodeGen/SSARegMap.h" 28#include "llvm/Target/MRegisterInfo.h" 29#include "llvm/Target/TargetInstrInfo.h" 30#include "llvm/Target/TargetMachine.h" 31#include "llvm/Support/CommandLine.h" 32#include "llvm/Support/Debug.h" 33#include "llvm/ADT/Statistic.h" 34#include "llvm/ADT/STLExtras.h" 35#include <algorithm> 36#include <cmath> 37using namespace llvm; 38 39namespace { 40 RegisterAnalysis<LiveIntervals> X("liveintervals", "Live Interval Analysis"); 41 42 Statistic<> numIntervals 43 ("liveintervals", "Number of original intervals"); 44 45 Statistic<> numIntervalsAfter 46 ("liveintervals", "Number of intervals after coalescing"); 47 48 Statistic<> numJoins 49 ("liveintervals", "Number of interval joins performed"); 50 51 Statistic<> numPeep 52 ("liveintervals", "Number of identity moves eliminated after coalescing"); 53 54 Statistic<> numFolded 55 ("liveintervals", "Number of loads/stores folded into instructions"); 56 57 cl::opt<bool> 58 EnableJoining("join-liveintervals", 59 cl::desc("Join compatible live intervals"), 60 cl::init(true)); 61}; 62 63void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const 64{ 65 AU.addPreserved<LiveVariables>(); 66 AU.addRequired<LiveVariables>(); 67 AU.addPreservedID(PHIEliminationID); 68 AU.addRequiredID(PHIEliminationID); 69 AU.addRequiredID(TwoAddressInstructionPassID); 70 AU.addRequired<LoopInfo>(); 71 MachineFunctionPass::getAnalysisUsage(AU); 72} 73 74void LiveIntervals::releaseMemory() 75{ 76 mi2iMap_.clear(); 77 i2miMap_.clear(); 78 r2iMap_.clear(); 79 r2rMap_.clear(); 80} 81 82 83/// runOnMachineFunction - Register allocate the whole function 84/// 85bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) { 86 mf_ = &fn; 87 tm_ = &fn.getTarget(); 88 mri_ = tm_->getRegisterInfo(); 89 lv_ = &getAnalysis<LiveVariables>(); 90 allocatableRegs_ = mri_->getAllocatableSet(fn); 91 r2rMap_.grow(mf_->getSSARegMap()->getLastVirtReg()); 92 93 // number MachineInstrs 94 unsigned miIndex = 0; 95 for (MachineFunction::iterator mbb = mf_->begin(), mbbEnd = mf_->end(); 96 mbb != mbbEnd; ++mbb) 97 for (MachineBasicBlock::iterator mi = mbb->begin(), miEnd = mbb->end(); 98 mi != miEnd; ++mi) { 99 bool inserted = mi2iMap_.insert(std::make_pair(mi, miIndex)).second; 100 assert(inserted && "multiple MachineInstr -> index mappings"); 101 i2miMap_.push_back(mi); 102 miIndex += InstrSlots::NUM; 103 } 104 105 computeIntervals(); 106 107 numIntervals += getNumIntervals(); 108 109#if 1 110 DEBUG(std::cerr << "********** INTERVALS **********\n"); 111 DEBUG(for (iterator I = begin(), E = end(); I != E; ++I) 112 std::cerr << I->second << "\n"); 113#endif 114 115 // join intervals if requested 116 if (EnableJoining) joinIntervals(); 117 118 numIntervalsAfter += getNumIntervals(); 119 120 // perform a final pass over the instructions and compute spill 121 // weights, coalesce virtual registers and remove identity moves 122 const LoopInfo& loopInfo = getAnalysis<LoopInfo>(); 123 const TargetInstrInfo& tii = *tm_->getInstrInfo(); 124 125 for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end(); 126 mbbi != mbbe; ++mbbi) { 127 MachineBasicBlock* mbb = mbbi; 128 unsigned loopDepth = loopInfo.getLoopDepth(mbb->getBasicBlock()); 129 130 for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end(); 131 mii != mie; ) { 132 // if the move will be an identity move delete it 133 unsigned srcReg, dstReg, RegRep; 134 if (tii.isMoveInstr(*mii, srcReg, dstReg) && 135 (RegRep = rep(srcReg)) == rep(dstReg)) { 136 // remove from def list 137 LiveInterval &interval = getOrCreateInterval(RegRep); 138 // remove index -> MachineInstr and 139 // MachineInstr -> index mappings 140 Mi2IndexMap::iterator mi2i = mi2iMap_.find(mii); 141 if (mi2i != mi2iMap_.end()) { 142 i2miMap_[mi2i->second/InstrSlots::NUM] = 0; 143 mi2iMap_.erase(mi2i); 144 } 145 mii = mbbi->erase(mii); 146 ++numPeep; 147 } 148 else { 149 for (unsigned i = 0; i < mii->getNumOperands(); ++i) { 150 const MachineOperand& mop = mii->getOperand(i); 151 if (mop.isRegister() && mop.getReg() && 152 MRegisterInfo::isVirtualRegister(mop.getReg())) { 153 // replace register with representative register 154 unsigned reg = rep(mop.getReg()); 155 mii->SetMachineOperandReg(i, reg); 156 157 LiveInterval &RegInt = getInterval(reg); 158 RegInt.weight += 159 (mop.isUse() + mop.isDef()) * pow(10.0F, loopDepth); 160 } 161 } 162 ++mii; 163 } 164 } 165 } 166 167 DEBUG(dump()); 168 return true; 169} 170 171/// print - Implement the dump method. 172void LiveIntervals::print(std::ostream &O) const { 173 O << "********** INTERVALS **********\n"; 174 for (const_iterator I = begin(), E = end(); I != E; ++I) 175 O << " " << I->second << "\n"; 176 177 O << "********** MACHINEINSTRS **********\n"; 178 for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end(); 179 mbbi != mbbe; ++mbbi) { 180 O << ((Value*)mbbi->getBasicBlock())->getName() << ":\n"; 181 for (MachineBasicBlock::iterator mii = mbbi->begin(), 182 mie = mbbi->end(); mii != mie; ++mii) { 183 O << getInstructionIndex(mii) << '\t' << *mii; 184 } 185 } 186} 187 188std::vector<LiveInterval*> LiveIntervals:: 189addIntervalsForSpills(const LiveInterval &li, VirtRegMap &vrm, int slot) { 190 // since this is called after the analysis is done we don't know if 191 // LiveVariables is available 192 lv_ = getAnalysisToUpdate<LiveVariables>(); 193 194 std::vector<LiveInterval*> added; 195 196 assert(li.weight != HUGE_VAL && 197 "attempt to spill already spilled interval!"); 198 199 DEBUG(std::cerr << "\t\t\t\tadding intervals for spills for interval: " 200 << li << '\n'); 201 202 const TargetRegisterClass* rc = mf_->getSSARegMap()->getRegClass(li.reg); 203 204 for (LiveInterval::Ranges::const_iterator 205 i = li.ranges.begin(), e = li.ranges.end(); i != e; ++i) { 206 unsigned index = getBaseIndex(i->start); 207 unsigned end = getBaseIndex(i->end-1) + InstrSlots::NUM; 208 for (; index != end; index += InstrSlots::NUM) { 209 // skip deleted instructions 210 while (index != end && !getInstructionFromIndex(index)) 211 index += InstrSlots::NUM; 212 if (index == end) break; 213 214 MachineBasicBlock::iterator mi = getInstructionFromIndex(index); 215 216 for_operand: 217 for (unsigned i = 0; i != mi->getNumOperands(); ++i) { 218 MachineOperand& mop = mi->getOperand(i); 219 if (mop.isRegister() && mop.getReg() == li.reg) { 220 // First thing, attempt to fold the memory reference into the 221 // instruction. If we can do this, we don't need to insert spill 222 // code. 223 if (MachineInstr* fmi = mri_->foldMemoryOperand(mi, i, slot)) { 224 if (lv_) 225 lv_->instructionChanged(mi, fmi); 226 vrm.virtFolded(li.reg, mi, fmi); 227 mi2iMap_.erase(mi); 228 i2miMap_[index/InstrSlots::NUM] = fmi; 229 mi2iMap_[fmi] = index; 230 MachineBasicBlock &MBB = *mi->getParent(); 231 mi = MBB.insert(MBB.erase(mi), fmi); 232 ++numFolded; 233 234 // Folding the load/store can completely change the instruction in 235 // unpredictable ways, rescan it from the beginning. 236 goto for_operand; 237 } else { 238 // This is tricky. We need to add information in the interval about 239 // the spill code so we have to use our extra load/store slots. 240 // 241 // If we have a use we are going to have a load so we start the 242 // interval from the load slot onwards. Otherwise we start from the 243 // def slot. 244 unsigned start = (mop.isUse() ? 245 getLoadIndex(index) : 246 getDefIndex(index)); 247 // If we have a def we are going to have a store right after it so 248 // we end the interval after the use of the next 249 // instruction. Otherwise we end after the use of this instruction. 250 unsigned end = 1 + (mop.isDef() ? 251 getStoreIndex(index) : 252 getUseIndex(index)); 253 254 // create a new register for this spill 255 unsigned nReg = mf_->getSSARegMap()->createVirtualRegister(rc); 256 mi->SetMachineOperandReg(i, nReg); 257 vrm.grow(); 258 vrm.assignVirt2StackSlot(nReg, slot); 259 LiveInterval& nI = getOrCreateInterval(nReg); 260 assert(nI.empty()); 261 262 // the spill weight is now infinity as it 263 // cannot be spilled again 264 nI.weight = HUGE_VAL; 265 LiveRange LR(start, end, nI.getNextValue()); 266 DEBUG(std::cerr << " +" << LR); 267 nI.addRange(LR); 268 added.push_back(&nI); 269 270 // update live variables if it is available 271 if (lv_) 272 lv_->addVirtualRegisterKilled(nReg, mi); 273 DEBUG(std::cerr << "\t\t\t\tadded new interval: " << nI << '\n'); 274 } 275 } 276 } 277 } 278 } 279 280 return added; 281} 282 283void LiveIntervals::printRegName(unsigned reg) const 284{ 285 if (MRegisterInfo::isPhysicalRegister(reg)) 286 std::cerr << mri_->getName(reg); 287 else 288 std::cerr << "%reg" << reg; 289} 290 291void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock* mbb, 292 MachineBasicBlock::iterator mi, 293 LiveInterval& interval) 294{ 295 DEBUG(std::cerr << "\t\tregister: "; printRegName(interval.reg)); 296 LiveVariables::VarInfo& vi = lv_->getVarInfo(interval.reg); 297 298 // Virtual registers may be defined multiple times (due to phi 299 // elimination and 2-addr elimination). Much of what we do only has to be 300 // done once for the vreg. We use an empty interval to detect the first 301 // time we see a vreg. 302 if (interval.empty()) { 303 // Get the Idx of the defining instructions. 304 unsigned defIndex = getDefIndex(getInstructionIndex(mi)); 305 306 unsigned ValNum = interval.getNextValue(); 307 assert(ValNum == 0 && "First value in interval is not 0?"); 308 ValNum = 0; // Clue in the optimizer. 309 310 // Loop over all of the blocks that the vreg is defined in. There are 311 // two cases we have to handle here. The most common case is a vreg 312 // whose lifetime is contained within a basic block. In this case there 313 // will be a single kill, in MBB, which comes after the definition. 314 if (vi.Kills.size() == 1 && vi.Kills[0]->getParent() == mbb) { 315 // FIXME: what about dead vars? 316 unsigned killIdx; 317 if (vi.Kills[0] != mi) 318 killIdx = getUseIndex(getInstructionIndex(vi.Kills[0]))+1; 319 else 320 killIdx = defIndex+1; 321 322 // If the kill happens after the definition, we have an intra-block 323 // live range. 324 if (killIdx > defIndex) { 325 assert(vi.AliveBlocks.empty() && 326 "Shouldn't be alive across any blocks!"); 327 LiveRange LR(defIndex, killIdx, ValNum); 328 interval.addRange(LR); 329 DEBUG(std::cerr << " +" << LR << "\n"); 330 return; 331 } 332 } 333 334 // The other case we handle is when a virtual register lives to the end 335 // of the defining block, potentially live across some blocks, then is 336 // live into some number of blocks, but gets killed. Start by adding a 337 // range that goes from this definition to the end of the defining block. 338 LiveRange NewLR(defIndex, 339 getInstructionIndex(&mbb->back()) + InstrSlots::NUM, 340 ValNum); 341 DEBUG(std::cerr << " +" << NewLR); 342 interval.addRange(NewLR); 343 344 // Iterate over all of the blocks that the variable is completely 345 // live in, adding [insrtIndex(begin), instrIndex(end)+4) to the 346 // live interval. 347 for (unsigned i = 0, e = vi.AliveBlocks.size(); i != e; ++i) { 348 if (vi.AliveBlocks[i]) { 349 MachineBasicBlock* mbb = mf_->getBlockNumbered(i); 350 if (!mbb->empty()) { 351 LiveRange LR(getInstructionIndex(&mbb->front()), 352 getInstructionIndex(&mbb->back()) + InstrSlots::NUM, 353 ValNum); 354 interval.addRange(LR); 355 DEBUG(std::cerr << " +" << LR); 356 } 357 } 358 } 359 360 // Finally, this virtual register is live from the start of any killing 361 // block to the 'use' slot of the killing instruction. 362 for (unsigned i = 0, e = vi.Kills.size(); i != e; ++i) { 363 MachineInstr *Kill = vi.Kills[i]; 364 LiveRange LR(getInstructionIndex(Kill->getParent()->begin()), 365 getUseIndex(getInstructionIndex(Kill))+1, 366 ValNum); 367 interval.addRange(LR); 368 DEBUG(std::cerr << " +" << LR); 369 } 370 371 } else { 372 // If this is the second time we see a virtual register definition, it 373 // must be due to phi elimination or two addr elimination. If this is 374 // the result of two address elimination, then the vreg is the first 375 // operand, and is a def-and-use. 376 if (mi->getOperand(0).isRegister() && 377 mi->getOperand(0).getReg() == interval.reg && 378 mi->getOperand(0).isDef() && mi->getOperand(0).isUse()) { 379 // If this is a two-address definition, then we have already processed 380 // the live range. The only problem is that we didn't realize there 381 // are actually two values in the live interval. Because of this we 382 // need to take the LiveRegion that defines this register and split it 383 // into two values. 384 unsigned DefIndex = getDefIndex(getInstructionIndex(vi.DefInst)); 385 unsigned RedefIndex = getDefIndex(getInstructionIndex(mi)); 386 387 // Delete the initial value, which should be short and continuous, 388 // becuase the 2-addr copy must be in the same MBB as the redef. 389 interval.removeRange(DefIndex, RedefIndex); 390 391 LiveRange LR(DefIndex, RedefIndex, interval.getNextValue()); 392 DEBUG(std::cerr << " replace range with " << LR); 393 interval.addRange(LR); 394 395 // If this redefinition is dead, we need to add a dummy unit live 396 // range covering the def slot. 397 for (LiveVariables::killed_iterator KI = lv_->dead_begin(mi), 398 E = lv_->dead_end(mi); KI != E; ++KI) 399 if (KI->second == interval.reg) { 400 interval.addRange(LiveRange(RedefIndex, RedefIndex+1, 0)); 401 break; 402 } 403 404 DEBUG(std::cerr << "RESULT: " << interval); 405 406 } else { 407 // Otherwise, this must be because of phi elimination. If this is the 408 // first redefinition of the vreg that we have seen, go back and change 409 // the live range in the PHI block to be a different value number. 410 if (interval.containsOneValue()) { 411 assert(vi.Kills.size() == 1 && 412 "PHI elimination vreg should have one kill, the PHI itself!"); 413 414 // Remove the old range that we now know has an incorrect number. 415 MachineInstr *Killer = vi.Kills[0]; 416 unsigned Start = getInstructionIndex(Killer->getParent()->begin()); 417 unsigned End = getUseIndex(getInstructionIndex(Killer))+1; 418 DEBUG(std::cerr << "Removing [" << Start << "," << End << "] from: " 419 << interval << "\n"); 420 interval.removeRange(Start, End); 421 DEBUG(std::cerr << "RESULT: " << interval); 422 423 // Replace the interval with one of a NEW value number. 424 LiveRange LR(Start, End, interval.getNextValue()); 425 DEBUG(std::cerr << " replace range with " << LR); 426 interval.addRange(LR); 427 DEBUG(std::cerr << "RESULT: " << interval); 428 } 429 430 // In the case of PHI elimination, each variable definition is only 431 // live until the end of the block. We've already taken care of the 432 // rest of the live range. 433 unsigned defIndex = getDefIndex(getInstructionIndex(mi)); 434 LiveRange LR(defIndex, 435 getInstructionIndex(&mbb->back()) + InstrSlots::NUM, 436 interval.getNextValue()); 437 interval.addRange(LR); 438 DEBUG(std::cerr << " +" << LR); 439 } 440 } 441 442 DEBUG(std::cerr << '\n'); 443} 444 445void LiveIntervals::handlePhysicalRegisterDef(MachineBasicBlock *MBB, 446 MachineBasicBlock::iterator mi, 447 LiveInterval& interval) 448{ 449 // A physical register cannot be live across basic block, so its 450 // lifetime must end somewhere in its defining basic block. 451 DEBUG(std::cerr << "\t\tregister: "; printRegName(interval.reg)); 452 typedef LiveVariables::killed_iterator KillIter; 453 454 unsigned baseIndex = getInstructionIndex(mi); 455 unsigned start = getDefIndex(baseIndex); 456 unsigned end = start; 457 458 // If it is not used after definition, it is considered dead at 459 // the instruction defining it. Hence its interval is: 460 // [defSlot(def), defSlot(def)+1) 461 for (KillIter ki = lv_->dead_begin(mi), ke = lv_->dead_end(mi); 462 ki != ke; ++ki) { 463 if (interval.reg == ki->second) { 464 DEBUG(std::cerr << " dead"); 465 end = getDefIndex(start) + 1; 466 goto exit; 467 } 468 } 469 470 // If it is not dead on definition, it must be killed by a 471 // subsequent instruction. Hence its interval is: 472 // [defSlot(def), useSlot(kill)+1) 473 while (true) { 474 ++mi; 475 assert(mi != MBB->end() && "physreg was not killed in defining block!"); 476 baseIndex += InstrSlots::NUM; 477 for (KillIter ki = lv_->killed_begin(mi), ke = lv_->killed_end(mi); 478 ki != ke; ++ki) { 479 if (interval.reg == ki->second) { 480 DEBUG(std::cerr << " killed"); 481 end = getUseIndex(baseIndex) + 1; 482 goto exit; 483 } 484 } 485 } 486 487exit: 488 assert(start < end && "did not find end of interval?"); 489 LiveRange LR(start, end, interval.getNextValue()); 490 interval.addRange(LR); 491 DEBUG(std::cerr << " +" << LR << '\n'); 492} 493 494void LiveIntervals::handleRegisterDef(MachineBasicBlock *MBB, 495 MachineBasicBlock::iterator MI, 496 unsigned reg) { 497 if (MRegisterInfo::isVirtualRegister(reg)) 498 handleVirtualRegisterDef(MBB, MI, getOrCreateInterval(reg)); 499 else if (allocatableRegs_[reg]) { 500 handlePhysicalRegisterDef(MBB, MI, getOrCreateInterval(reg)); 501 for (const unsigned* AS = mri_->getAliasSet(reg); *AS; ++AS) 502 handlePhysicalRegisterDef(MBB, MI, getOrCreateInterval(*AS)); 503 } 504} 505 506/// computeIntervals - computes the live intervals for virtual 507/// registers. for some ordering of the machine instructions [1,N] a 508/// live interval is an interval [i, j) where 1 <= i <= j < N for 509/// which a variable is live 510void LiveIntervals::computeIntervals() 511{ 512 DEBUG(std::cerr << "********** COMPUTING LIVE INTERVALS **********\n"); 513 DEBUG(std::cerr << "********** Function: " 514 << ((Value*)mf_->getFunction())->getName() << '\n'); 515 516 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end(); 517 I != E; ++I) { 518 MachineBasicBlock* mbb = I; 519 DEBUG(std::cerr << ((Value*)mbb->getBasicBlock())->getName() << ":\n"); 520 521 for (MachineBasicBlock::iterator mi = mbb->begin(), miEnd = mbb->end(); 522 mi != miEnd; ++mi) { 523 const TargetInstrDescriptor& tid = 524 tm_->getInstrInfo()->get(mi->getOpcode()); 525 DEBUG(std::cerr << getInstructionIndex(mi) << "\t" << *mi); 526 527 // handle implicit defs 528 for (const unsigned* id = tid.ImplicitDefs; *id; ++id) 529 handleRegisterDef(mbb, mi, *id); 530 531 // handle explicit defs 532 for (int i = mi->getNumOperands() - 1; i >= 0; --i) { 533 MachineOperand& mop = mi->getOperand(i); 534 // handle register defs - build intervals 535 if (mop.isRegister() && mop.getReg() && mop.isDef()) 536 handleRegisterDef(mbb, mi, mop.getReg()); 537 } 538 } 539 } 540} 541 542void LiveIntervals::joinIntervalsInMachineBB(MachineBasicBlock *MBB) { 543 DEBUG(std::cerr << ((Value*)MBB->getBasicBlock())->getName() << ":\n"); 544 const TargetInstrInfo &TII = *tm_->getInstrInfo(); 545 546 for (MachineBasicBlock::iterator mi = MBB->begin(), mie = MBB->end(); 547 mi != mie; ++mi) { 548 DEBUG(std::cerr << getInstructionIndex(mi) << '\t' << *mi); 549 550 // we only join virtual registers with allocatable 551 // physical registers since we do not have liveness information 552 // on not allocatable physical registers 553 unsigned regA, regB; 554 if (TII.isMoveInstr(*mi, regA, regB) && 555 (MRegisterInfo::isVirtualRegister(regA) || allocatableRegs_[regA]) && 556 (MRegisterInfo::isVirtualRegister(regB) || allocatableRegs_[regB])) { 557 558 // Get representative registers. 559 regA = rep(regA); 560 regB = rep(regB); 561 562 // If they are already joined we continue. 563 if (regA == regB) 564 continue; 565 566 // If they are both physical registers, we cannot join them. 567 if (MRegisterInfo::isPhysicalRegister(regA) && 568 MRegisterInfo::isPhysicalRegister(regB)) 569 continue; 570 571 // If they are not of the same register class, we cannot join them. 572 if (differingRegisterClasses(regA, regB)) 573 continue; 574 575 LiveInterval &IntA = getInterval(regA); 576 LiveInterval &IntB = getInterval(regB); 577 assert(IntA.reg == regA && IntB.reg == regB && 578 "Register mapping is horribly broken!"); 579 580 DEBUG(std::cerr << "\t\tInspecting " << IntA << " and " << IntB << ": "); 581 582 // If two intervals contain a single value and are joined by a copy, it 583 // does not matter if the intervals overlap, they can always be joined. 584 bool TriviallyJoinable = 585 IntA.containsOneValue() && IntB.containsOneValue(); 586 587 unsigned MIDefIdx = getDefIndex(getInstructionIndex(mi)); 588 if ((TriviallyJoinable || IntB.joinable(IntA, MIDefIdx)) && 589 !overlapsAliases(&IntA, &IntB)) { 590 IntB.join(IntA, MIDefIdx); 591 592 if (!MRegisterInfo::isPhysicalRegister(regA)) { 593 r2iMap_.erase(regA); 594 r2rMap_[regA] = regB; 595 } else { 596 // Otherwise merge the data structures the other way so we don't lose 597 // the physreg information. 598 r2rMap_[regB] = regA; 599 IntB.reg = regA; 600 IntA.swap(IntB); 601 r2iMap_.erase(regB); 602 } 603 DEBUG(std::cerr << "Joined. Result = " << IntB << "\n"); 604 ++numJoins; 605 } else { 606 DEBUG(std::cerr << "Interference!\n"); 607 } 608 } 609 } 610} 611 612namespace { 613 // DepthMBBCompare - Comparison predicate that sort first based on the loop 614 // depth of the basic block (the unsigned), and then on the MBB number. 615 struct DepthMBBCompare { 616 typedef std::pair<unsigned, MachineBasicBlock*> DepthMBBPair; 617 bool operator()(const DepthMBBPair &LHS, const DepthMBBPair &RHS) const { 618 if (LHS.first > RHS.first) return true; // Deeper loops first 619 return LHS.first == RHS.first && 620 LHS.second->getNumber() < RHS.second->getNumber(); 621 } 622 }; 623} 624 625void LiveIntervals::joinIntervals() { 626 DEBUG(std::cerr << "********** JOINING INTERVALS ***********\n"); 627 628 const LoopInfo &LI = getAnalysis<LoopInfo>(); 629 if (LI.begin() == LI.end()) { 630 // If there are no loops in the function, join intervals in function order. 631 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end(); 632 I != E; ++I) 633 joinIntervalsInMachineBB(I); 634 } else { 635 // Otherwise, join intervals in inner loops before other intervals. 636 // Unfortunately we can't just iterate over loop hierarchy here because 637 // there may be more MBB's than BB's. Collect MBB's for sorting. 638 std::vector<std::pair<unsigned, MachineBasicBlock*> > MBBs; 639 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end(); 640 I != E; ++I) 641 MBBs.push_back(std::make_pair(LI.getLoopDepth(I->getBasicBlock()), I)); 642 643 // Sort by loop depth. 644 std::sort(MBBs.begin(), MBBs.end(), DepthMBBCompare()); 645 646 // Finally, join intervals in loop nest order. 647 for (unsigned i = 0, e = MBBs.size(); i != e; ++i) 648 joinIntervalsInMachineBB(MBBs[i].second); 649 } 650 651 DEBUG(std::cerr << "*** Register mapping ***\n"); 652 DEBUG(for (int i = 0, e = r2rMap_.size(); i != e; ++i) 653 if (r2rMap_[i]) 654 std::cerr << " reg " << i << " -> reg " << r2rMap_[i] << "\n"); 655} 656 657/// Return true if the two specified registers belong to different register 658/// classes. The registers may be either phys or virt regs. 659bool LiveIntervals::differingRegisterClasses(unsigned RegA, 660 unsigned RegB) const { 661 const TargetRegisterClass *RegClass; 662 663 // Get the register classes for the first reg. 664 if (MRegisterInfo::isVirtualRegister(RegA)) 665 RegClass = mf_->getSSARegMap()->getRegClass(RegA); 666 else 667 RegClass = mri_->getRegClass(RegA); 668 669 // Compare against the regclass for the second reg. 670 if (MRegisterInfo::isVirtualRegister(RegB)) 671 return RegClass != mf_->getSSARegMap()->getRegClass(RegB); 672 else 673 return !RegClass->contains(RegB); 674} 675 676bool LiveIntervals::overlapsAliases(const LiveInterval *LHS, 677 const LiveInterval *RHS) const { 678 if (!MRegisterInfo::isPhysicalRegister(LHS->reg)) { 679 if (!MRegisterInfo::isPhysicalRegister(RHS->reg)) 680 return false; // vreg-vreg merge has no aliases! 681 std::swap(LHS, RHS); 682 } 683 684 assert(MRegisterInfo::isPhysicalRegister(LHS->reg) && 685 MRegisterInfo::isVirtualRegister(RHS->reg) && 686 "first interval must describe a physical register"); 687 688 for (const unsigned *AS = mri_->getAliasSet(LHS->reg); *AS; ++AS) 689 if (RHS->overlaps(getInterval(*AS))) 690 return true; 691 692 return false; 693} 694 695LiveInterval LiveIntervals::createInterval(unsigned reg) { 696 float Weight = MRegisterInfo::isPhysicalRegister(reg) ? HUGE_VAL :0.0F; 697 return LiveInterval(reg, Weight); 698} 699