DAGCombiner.cpp revision 68c1868c4bdc04cd319ea92662aa5aaccf6ac378
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "dagcombine" 16#include "llvm/CodeGen/SelectionDAG.h" 17#include "llvm/DerivedTypes.h" 18#include "llvm/CodeGen/MachineFunction.h" 19#include "llvm/CodeGen/MachineFrameInfo.h" 20#include "llvm/CodeGen/PseudoSourceValue.h" 21#include "llvm/Analysis/AliasAnalysis.h" 22#include "llvm/Target/TargetData.h" 23#include "llvm/Target/TargetFrameInfo.h" 24#include "llvm/Target/TargetLowering.h" 25#include "llvm/Target/TargetMachine.h" 26#include "llvm/Target/TargetOptions.h" 27#include "llvm/ADT/SmallPtrSet.h" 28#include "llvm/ADT/Statistic.h" 29#include "llvm/Support/Compiler.h" 30#include "llvm/Support/CommandLine.h" 31#include "llvm/Support/Debug.h" 32#include "llvm/Support/MathExtras.h" 33#include <algorithm> 34#include <set> 35using namespace llvm; 36 37STATISTIC(NodesCombined , "Number of dag nodes combined"); 38STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 39STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 40 41namespace { 42 static cl::opt<bool> 43 CombinerAA("combiner-alias-analysis", cl::Hidden, 44 cl::desc("Turn on alias analysis during testing")); 45 46 static cl::opt<bool> 47 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 48 cl::desc("Include global information in alias analysis")); 49 50//------------------------------ DAGCombiner ---------------------------------// 51 52 class VISIBILITY_HIDDEN DAGCombiner { 53 SelectionDAG &DAG; 54 const TargetLowering &TLI; 55 CombineLevel Level; 56 bool LegalOperations; 57 bool LegalTypes; 58 bool Fast; 59 60 // Worklist of all of the nodes that need to be simplified. 61 std::vector<SDNode*> WorkList; 62 63 // AA - Used for DAG load/store alias analysis. 64 AliasAnalysis &AA; 65 66 /// AddUsersToWorkList - When an instruction is simplified, add all users of 67 /// the instruction to the work lists because they might get more simplified 68 /// now. 69 /// 70 void AddUsersToWorkList(SDNode *N) { 71 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 72 UI != UE; ++UI) 73 AddToWorkList(*UI); 74 } 75 76 /// visit - call the node-specific routine that knows how to fold each 77 /// particular type of node. 78 SDValue visit(SDNode *N); 79 80 public: 81 /// AddToWorkList - Add to the work list making sure it's instance is at the 82 /// the back (next to be processed.) 83 void AddToWorkList(SDNode *N) { 84 removeFromWorkList(N); 85 WorkList.push_back(N); 86 } 87 88 /// removeFromWorkList - remove all instances of N from the worklist. 89 /// 90 void removeFromWorkList(SDNode *N) { 91 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 92 WorkList.end()); 93 } 94 95 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 96 bool AddTo = true); 97 98 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) { 99 return CombineTo(N, &Res, 1, AddTo); 100 } 101 102 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, 103 bool AddTo = true) { 104 SDValue To[] = { Res0, Res1 }; 105 return CombineTo(N, To, 2, AddTo); 106 } 107 108 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO); 109 110 private: 111 112 /// SimplifyDemandedBits - Check the specified integer node value to see if 113 /// it can be simplified or if things it uses can be simplified by bit 114 /// propagation. If so, return true. 115 bool SimplifyDemandedBits(SDValue Op) { 116 APInt Demanded = APInt::getAllOnesValue(Op.getValueSizeInBits()); 117 return SimplifyDemandedBits(Op, Demanded); 118 } 119 120 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded); 121 122 bool CombineToPreIndexedLoadStore(SDNode *N); 123 bool CombineToPostIndexedLoadStore(SDNode *N); 124 125 126 /// combine - call the node-specific routine that knows how to fold each 127 /// particular type of node. If that doesn't do anything, try the 128 /// target-specific DAG combines. 129 SDValue combine(SDNode *N); 130 131 // Visitation implementation - Implement dag node combining for different 132 // node types. The semantics are as follows: 133 // Return Value: 134 // SDValue.getNode() == 0 - No change was made 135 // SDValue.getNode() == N - N was replaced, is dead and has been handled. 136 // otherwise - N should be replaced by the returned Operand. 137 // 138 SDValue visitTokenFactor(SDNode *N); 139 SDValue visitMERGE_VALUES(SDNode *N); 140 SDValue visitADD(SDNode *N); 141 SDValue visitSUB(SDNode *N); 142 SDValue visitADDC(SDNode *N); 143 SDValue visitADDE(SDNode *N); 144 SDValue visitMUL(SDNode *N); 145 SDValue visitSDIV(SDNode *N); 146 SDValue visitUDIV(SDNode *N); 147 SDValue visitSREM(SDNode *N); 148 SDValue visitUREM(SDNode *N); 149 SDValue visitMULHU(SDNode *N); 150 SDValue visitMULHS(SDNode *N); 151 SDValue visitSMUL_LOHI(SDNode *N); 152 SDValue visitUMUL_LOHI(SDNode *N); 153 SDValue visitSDIVREM(SDNode *N); 154 SDValue visitUDIVREM(SDNode *N); 155 SDValue visitAND(SDNode *N); 156 SDValue visitOR(SDNode *N); 157 SDValue visitXOR(SDNode *N); 158 SDValue SimplifyVBinOp(SDNode *N); 159 SDValue visitSHL(SDNode *N); 160 SDValue visitSRA(SDNode *N); 161 SDValue visitSRL(SDNode *N); 162 SDValue visitCTLZ(SDNode *N); 163 SDValue visitCTTZ(SDNode *N); 164 SDValue visitCTPOP(SDNode *N); 165 SDValue visitSELECT(SDNode *N); 166 SDValue visitSELECT_CC(SDNode *N); 167 SDValue visitSETCC(SDNode *N); 168 SDValue visitSIGN_EXTEND(SDNode *N); 169 SDValue visitZERO_EXTEND(SDNode *N); 170 SDValue visitANY_EXTEND(SDNode *N); 171 SDValue visitSIGN_EXTEND_INREG(SDNode *N); 172 SDValue visitTRUNCATE(SDNode *N); 173 SDValue visitBIT_CONVERT(SDNode *N); 174 SDValue visitBUILD_PAIR(SDNode *N); 175 SDValue visitFADD(SDNode *N); 176 SDValue visitFSUB(SDNode *N); 177 SDValue visitFMUL(SDNode *N); 178 SDValue visitFDIV(SDNode *N); 179 SDValue visitFREM(SDNode *N); 180 SDValue visitFCOPYSIGN(SDNode *N); 181 SDValue visitSINT_TO_FP(SDNode *N); 182 SDValue visitUINT_TO_FP(SDNode *N); 183 SDValue visitFP_TO_SINT(SDNode *N); 184 SDValue visitFP_TO_UINT(SDNode *N); 185 SDValue visitFP_ROUND(SDNode *N); 186 SDValue visitFP_ROUND_INREG(SDNode *N); 187 SDValue visitFP_EXTEND(SDNode *N); 188 SDValue visitFNEG(SDNode *N); 189 SDValue visitFABS(SDNode *N); 190 SDValue visitBRCOND(SDNode *N); 191 SDValue visitBR_CC(SDNode *N); 192 SDValue visitLOAD(SDNode *N); 193 SDValue visitSTORE(SDNode *N); 194 SDValue visitINSERT_VECTOR_ELT(SDNode *N); 195 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N); 196 SDValue visitBUILD_VECTOR(SDNode *N); 197 SDValue visitCONCAT_VECTORS(SDNode *N); 198 SDValue visitVECTOR_SHUFFLE(SDNode *N); 199 200 SDValue XformToShuffleWithZero(SDNode *N); 201 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS); 202 203 SDValue visitShiftByConstant(SDNode *N, unsigned Amt); 204 205 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS); 206 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N); 207 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2); 208 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2, 209 SDValue N3, ISD::CondCode CC, 210 bool NotExtCompare = false); 211 SDValue SimplifySetCC(MVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, 212 DebugLoc DL, bool foldBooleans = true); 213 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 214 unsigned HiOp); 215 SDValue CombineConsecutiveLoads(SDNode *N, MVT VT); 216 SDValue ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT); 217 SDValue BuildSDIV(SDNode *N); 218 SDValue BuildUDIV(SDNode *N); 219 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL); 220 SDValue ReduceLoadWidth(SDNode *N); 221 222 SDValue GetDemandedBits(SDValue V, const APInt &Mask); 223 224 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 225 /// looking for aliasing nodes and adding them to the Aliases vector. 226 void GatherAllAliases(SDNode *N, SDValue OriginalChain, 227 SmallVector<SDValue, 8> &Aliases); 228 229 /// isAlias - Return true if there is any possibility that the two addresses 230 /// overlap. 231 bool isAlias(SDValue Ptr1, int64_t Size1, 232 const Value *SrcValue1, int SrcValueOffset1, 233 SDValue Ptr2, int64_t Size2, 234 const Value *SrcValue2, int SrcValueOffset2) const; 235 236 /// FindAliasInfo - Extracts the relevant alias information from the memory 237 /// node. Returns true if the operand was a load. 238 bool FindAliasInfo(SDNode *N, 239 SDValue &Ptr, int64_t &Size, 240 const Value *&SrcValue, int &SrcValueOffset) const; 241 242 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 243 /// looking for a better chain (aliasing node.) 244 SDValue FindBetterChain(SDNode *N, SDValue Chain); 245 246 /// getShiftAmountTy - Returns a type large enough to hold any valid 247 /// shift amount - before type legalization these can be huge. 248 MVT getShiftAmountTy() { 249 return LegalTypes ? TLI.getShiftAmountTy() : TLI.getPointerTy(); 250 } 251 252public: 253 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, bool fast) 254 : DAG(D), 255 TLI(D.getTargetLoweringInfo()), 256 Level(Unrestricted), 257 LegalOperations(false), 258 LegalTypes(false), 259 Fast(fast), 260 AA(A) {} 261 262 /// Run - runs the dag combiner on all nodes in the work list 263 void Run(CombineLevel AtLevel); 264 }; 265} 266 267 268namespace { 269/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 270/// nodes from the worklist. 271class VISIBILITY_HIDDEN WorkListRemover : 272 public SelectionDAG::DAGUpdateListener { 273 DAGCombiner &DC; 274public: 275 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {} 276 277 virtual void NodeDeleted(SDNode *N, SDNode *E) { 278 DC.removeFromWorkList(N); 279 } 280 281 virtual void NodeUpdated(SDNode *N) { 282 // Ignore updates. 283 } 284}; 285} 286 287//===----------------------------------------------------------------------===// 288// TargetLowering::DAGCombinerInfo implementation 289//===----------------------------------------------------------------------===// 290 291void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 292 ((DAGCombiner*)DC)->AddToWorkList(N); 293} 294 295SDValue TargetLowering::DAGCombinerInfo:: 296CombineTo(SDNode *N, const std::vector<SDValue> &To) { 297 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size()); 298} 299 300SDValue TargetLowering::DAGCombinerInfo:: 301CombineTo(SDNode *N, SDValue Res) { 302 return ((DAGCombiner*)DC)->CombineTo(N, Res); 303} 304 305 306SDValue TargetLowering::DAGCombinerInfo:: 307CombineTo(SDNode *N, SDValue Res0, SDValue Res1) { 308 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1); 309} 310 311void TargetLowering::DAGCombinerInfo:: 312CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 313 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO); 314} 315 316//===----------------------------------------------------------------------===// 317// Helper Functions 318//===----------------------------------------------------------------------===// 319 320/// isNegatibleForFree - Return 1 if we can compute the negated form of the 321/// specified expression for the same cost as the expression itself, or 2 if we 322/// can compute the negated form more cheaply than the expression itself. 323static char isNegatibleForFree(SDValue Op, bool LegalOperations, 324 unsigned Depth = 0) { 325 // No compile time optimizations on this type. 326 if (Op.getValueType() == MVT::ppcf128) 327 return 0; 328 329 // fneg is removable even if it has multiple uses. 330 if (Op.getOpcode() == ISD::FNEG) return 2; 331 332 // Don't allow anything with multiple uses. 333 if (!Op.hasOneUse()) return 0; 334 335 // Don't recurse exponentially. 336 if (Depth > 6) return 0; 337 338 switch (Op.getOpcode()) { 339 default: return false; 340 case ISD::ConstantFP: 341 // Don't invert constant FP values after legalize. The negated constant 342 // isn't necessarily legal. 343 return LegalOperations ? 0 : 1; 344 case ISD::FADD: 345 // FIXME: determine better conditions for this xform. 346 if (!UnsafeFPMath) return 0; 347 348 // fold (fsub (fadd A, B)) -> (fsub (fneg A), B) 349 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 350 return V; 351 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 352 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 353 case ISD::FSUB: 354 // We can't turn -(A-B) into B-A when we honor signed zeros. 355 if (!UnsafeFPMath) return 0; 356 357 // fold (fneg (fsub A, B)) -> (fsub B, A) 358 return 1; 359 360 case ISD::FMUL: 361 case ISD::FDIV: 362 if (HonorSignDependentRoundingFPMath()) return 0; 363 364 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y)) 365 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 366 return V; 367 368 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 369 370 case ISD::FP_EXTEND: 371 case ISD::FP_ROUND: 372 case ISD::FSIN: 373 return isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1); 374 } 375} 376 377/// GetNegatedExpression - If isNegatibleForFree returns true, this function 378/// returns the newly negated expression. 379static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG, 380 bool LegalOperations, unsigned Depth = 0) { 381 // fneg is removable even if it has multiple uses. 382 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 383 384 // Don't allow anything with multiple uses. 385 assert(Op.hasOneUse() && "Unknown reuse!"); 386 387 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 388 switch (Op.getOpcode()) { 389 default: assert(0 && "Unknown code"); 390 case ISD::ConstantFP: { 391 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 392 V.changeSign(); 393 return DAG.getConstantFP(V, Op.getValueType()); 394 } 395 case ISD::FADD: 396 // FIXME: determine better conditions for this xform. 397 assert(UnsafeFPMath); 398 399 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B) 400 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 401 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 402 GetNegatedExpression(Op.getOperand(0), DAG, 403 LegalOperations, Depth+1), 404 Op.getOperand(1)); 405 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 406 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 407 GetNegatedExpression(Op.getOperand(1), DAG, 408 LegalOperations, Depth+1), 409 Op.getOperand(0)); 410 case ISD::FSUB: 411 // We can't turn -(A-B) into B-A when we honor signed zeros. 412 assert(UnsafeFPMath); 413 414 // fold (fneg (fsub 0, B)) -> B 415 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 416 if (N0CFP->getValueAPF().isZero()) 417 return Op.getOperand(1); 418 419 // fold (fneg (fsub A, B)) -> (fsub B, A) 420 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 421 Op.getOperand(1), Op.getOperand(0)); 422 423 case ISD::FMUL: 424 case ISD::FDIV: 425 assert(!HonorSignDependentRoundingFPMath()); 426 427 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) 428 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 429 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 430 GetNegatedExpression(Op.getOperand(0), DAG, 431 LegalOperations, Depth+1), 432 Op.getOperand(1)); 433 434 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y)) 435 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 436 Op.getOperand(0), 437 GetNegatedExpression(Op.getOperand(1), DAG, 438 LegalOperations, Depth+1)); 439 440 case ISD::FP_EXTEND: 441 case ISD::FSIN: 442 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 443 GetNegatedExpression(Op.getOperand(0), DAG, 444 LegalOperations, Depth+1)); 445 case ISD::FP_ROUND: 446 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(), 447 GetNegatedExpression(Op.getOperand(0), DAG, 448 LegalOperations, Depth+1), 449 Op.getOperand(1)); 450 } 451} 452 453 454// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 455// that selects between the values 1 and 0, making it equivalent to a setcc. 456// Also, set the incoming LHS, RHS, and CC references to the appropriate 457// nodes based on the type of node we are checking. This simplifies life a 458// bit for the callers. 459static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS, 460 SDValue &CC) { 461 if (N.getOpcode() == ISD::SETCC) { 462 LHS = N.getOperand(0); 463 RHS = N.getOperand(1); 464 CC = N.getOperand(2); 465 return true; 466 } 467 if (N.getOpcode() == ISD::SELECT_CC && 468 N.getOperand(2).getOpcode() == ISD::Constant && 469 N.getOperand(3).getOpcode() == ISD::Constant && 470 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 && 471 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 472 LHS = N.getOperand(0); 473 RHS = N.getOperand(1); 474 CC = N.getOperand(4); 475 return true; 476 } 477 return false; 478} 479 480// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 481// one use. If this is true, it allows the users to invert the operation for 482// free when it is profitable to do so. 483static bool isOneUseSetCC(SDValue N) { 484 SDValue N0, N1, N2; 485 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse()) 486 return true; 487 return false; 488} 489 490SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL, 491 SDValue N0, SDValue N1) { 492 MVT VT = N0.getValueType(); 493 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 494 if (isa<ConstantSDNode>(N1)) { 495 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 496 SDValue OpNode = 497 DAG.FoldConstantArithmetic(Opc, VT, 498 cast<ConstantSDNode>(N0.getOperand(1)), 499 cast<ConstantSDNode>(N1)); 500 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode); 501 } else if (N0.hasOneUse()) { 502 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 503 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 504 N0.getOperand(0), N1); 505 AddToWorkList(OpNode.getNode()); 506 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1)); 507 } 508 } 509 510 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 511 if (isa<ConstantSDNode>(N0)) { 512 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 513 SDValue OpNode = 514 DAG.FoldConstantArithmetic(Opc, VT, 515 cast<ConstantSDNode>(N1.getOperand(1)), 516 cast<ConstantSDNode>(N0)); 517 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode); 518 } else if (N1.hasOneUse()) { 519 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 520 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 521 N1.getOperand(0), N0); 522 AddToWorkList(OpNode.getNode()); 523 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1)); 524 } 525 } 526 527 return SDValue(); 528} 529 530SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 531 bool AddTo) { 532 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 533 ++NodesCombined; 534 DOUT << "\nReplacing.1 "; DEBUG(N->dump(&DAG)); 535 DOUT << "\nWith: "; DEBUG(To[0].getNode()->dump(&DAG)); 536 DOUT << " and " << NumTo-1 << " other values\n"; 537 DEBUG(for (unsigned i = 0, e = NumTo; i != e; ++i) 538 assert(N->getValueType(i) == To[i].getValueType() && 539 "Cannot combine value to value of different type!")); 540 WorkListRemover DeadNodes(*this); 541 DAG.ReplaceAllUsesWith(N, To, &DeadNodes); 542 543 if (AddTo) { 544 // Push the new nodes and any users onto the worklist 545 for (unsigned i = 0, e = NumTo; i != e; ++i) { 546 if (To[i].getNode()) { 547 AddToWorkList(To[i].getNode()); 548 AddUsersToWorkList(To[i].getNode()); 549 } 550 } 551 } 552 553 // Finally, if the node is now dead, remove it from the graph. The node 554 // may not be dead if the replacement process recursively simplified to 555 // something else needing this node. 556 if (N->use_empty()) { 557 // Nodes can be reintroduced into the worklist. Make sure we do not 558 // process a node that has been replaced. 559 removeFromWorkList(N); 560 561 // Finally, since the node is now dead, remove it from the graph. 562 DAG.DeleteNode(N); 563 } 564 return SDValue(N, 0); 565} 566 567void 568DAGCombiner::CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt & 569 TLO) { 570 // Replace all uses. If any nodes become isomorphic to other nodes and 571 // are deleted, make sure to remove them from our worklist. 572 WorkListRemover DeadNodes(*this); 573 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 574 575 // Push the new node and any (possibly new) users onto the worklist. 576 AddToWorkList(TLO.New.getNode()); 577 AddUsersToWorkList(TLO.New.getNode()); 578 579 // Finally, if the node is now dead, remove it from the graph. The node 580 // may not be dead if the replacement process recursively simplified to 581 // something else needing this node. 582 if (TLO.Old.getNode()->use_empty()) { 583 removeFromWorkList(TLO.Old.getNode()); 584 585 // If the operands of this node are only used by the node, they will now 586 // be dead. Make sure to visit them first to delete dead nodes early. 587 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i) 588 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse()) 589 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode()); 590 591 DAG.DeleteNode(TLO.Old.getNode()); 592 } 593} 594 595/// SimplifyDemandedBits - Check the specified integer node value to see if 596/// it can be simplified or if things it uses can be simplified by bit 597/// propagation. If so, return true. 598bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) { 599 TargetLowering::TargetLoweringOpt TLO(DAG); 600 APInt KnownZero, KnownOne; 601 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 602 return false; 603 604 // Revisit the node. 605 AddToWorkList(Op.getNode()); 606 607 // Replace the old value with the new one. 608 ++NodesCombined; 609 DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.getNode()->dump(&DAG)); 610 DOUT << "\nWith: "; DEBUG(TLO.New.getNode()->dump(&DAG)); 611 DOUT << '\n'; 612 613 CommitTargetLoweringOpt(TLO); 614 return true; 615} 616 617//===----------------------------------------------------------------------===// 618// Main DAG Combiner implementation 619//===----------------------------------------------------------------------===// 620 621void DAGCombiner::Run(CombineLevel AtLevel) { 622 // set the instance variables, so that the various visit routines may use it. 623 Level = AtLevel; 624 LegalOperations = Level >= NoIllegalOperations; 625 LegalTypes = Level >= NoIllegalTypes; 626 627 // Add all the dag nodes to the worklist. 628 WorkList.reserve(DAG.allnodes_size()); 629 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 630 E = DAG.allnodes_end(); I != E; ++I) 631 WorkList.push_back(I); 632 633 // Create a dummy node (which is not added to allnodes), that adds a reference 634 // to the root node, preventing it from being deleted, and tracking any 635 // changes of the root. 636 HandleSDNode Dummy(DAG.getRoot()); 637 638 // The root of the dag may dangle to deleted nodes until the dag combiner is 639 // done. Set it to null to avoid confusion. 640 DAG.setRoot(SDValue()); 641 642 // while the worklist isn't empty, inspect the node on the end of it and 643 // try and combine it. 644 while (!WorkList.empty()) { 645 SDNode *N = WorkList.back(); 646 WorkList.pop_back(); 647 648 // If N has no uses, it is dead. Make sure to revisit all N's operands once 649 // N is deleted from the DAG, since they too may now be dead or may have a 650 // reduced number of uses, allowing other xforms. 651 if (N->use_empty() && N != &Dummy) { 652 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 653 AddToWorkList(N->getOperand(i).getNode()); 654 655 DAG.DeleteNode(N); 656 continue; 657 } 658 659 SDValue RV = combine(N); 660 661 if (RV.getNode() == 0) 662 continue; 663 664 ++NodesCombined; 665 666 // If we get back the same node we passed in, rather than a new node or 667 // zero, we know that the node must have defined multiple values and 668 // CombineTo was used. Since CombineTo takes care of the worklist 669 // mechanics for us, we have no work to do in this case. 670 if (RV.getNode() == N) 671 continue; 672 673 assert(N->getOpcode() != ISD::DELETED_NODE && 674 RV.getNode()->getOpcode() != ISD::DELETED_NODE && 675 "Node was deleted but visit returned new node!"); 676 677 DOUT << "\nReplacing.3 "; DEBUG(N->dump(&DAG)); 678 DOUT << "\nWith: "; DEBUG(RV.getNode()->dump(&DAG)); 679 DOUT << '\n'; 680 WorkListRemover DeadNodes(*this); 681 if (N->getNumValues() == RV.getNode()->getNumValues()) 682 DAG.ReplaceAllUsesWith(N, RV.getNode(), &DeadNodes); 683 else { 684 assert(N->getValueType(0) == RV.getValueType() && 685 N->getNumValues() == 1 && "Type mismatch"); 686 SDValue OpV = RV; 687 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes); 688 } 689 690 // Push the new node and any users onto the worklist 691 AddToWorkList(RV.getNode()); 692 AddUsersToWorkList(RV.getNode()); 693 694 // Add any uses of the old node to the worklist in case this node is the 695 // last one that uses them. They may become dead after this node is 696 // deleted. 697 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 698 AddToWorkList(N->getOperand(i).getNode()); 699 700 // Finally, if the node is now dead, remove it from the graph. The node 701 // may not be dead if the replacement process recursively simplified to 702 // something else needing this node. 703 if (N->use_empty()) { 704 // Nodes can be reintroduced into the worklist. Make sure we do not 705 // process a node that has been replaced. 706 removeFromWorkList(N); 707 708 // Finally, since the node is now dead, remove it from the graph. 709 DAG.DeleteNode(N); 710 } 711 } 712 713 // If the root changed (e.g. it was a dead load, update the root). 714 DAG.setRoot(Dummy.getValue()); 715} 716 717SDValue DAGCombiner::visit(SDNode *N) { 718 switch(N->getOpcode()) { 719 default: break; 720 case ISD::TokenFactor: return visitTokenFactor(N); 721 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); 722 case ISD::ADD: return visitADD(N); 723 case ISD::SUB: return visitSUB(N); 724 case ISD::ADDC: return visitADDC(N); 725 case ISD::ADDE: return visitADDE(N); 726 case ISD::MUL: return visitMUL(N); 727 case ISD::SDIV: return visitSDIV(N); 728 case ISD::UDIV: return visitUDIV(N); 729 case ISD::SREM: return visitSREM(N); 730 case ISD::UREM: return visitUREM(N); 731 case ISD::MULHU: return visitMULHU(N); 732 case ISD::MULHS: return visitMULHS(N); 733 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 734 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 735 case ISD::SDIVREM: return visitSDIVREM(N); 736 case ISD::UDIVREM: return visitUDIVREM(N); 737 case ISD::AND: return visitAND(N); 738 case ISD::OR: return visitOR(N); 739 case ISD::XOR: return visitXOR(N); 740 case ISD::SHL: return visitSHL(N); 741 case ISD::SRA: return visitSRA(N); 742 case ISD::SRL: return visitSRL(N); 743 case ISD::CTLZ: return visitCTLZ(N); 744 case ISD::CTTZ: return visitCTTZ(N); 745 case ISD::CTPOP: return visitCTPOP(N); 746 case ISD::SELECT: return visitSELECT(N); 747 case ISD::SELECT_CC: return visitSELECT_CC(N); 748 case ISD::SETCC: return visitSETCC(N); 749 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 750 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 751 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 752 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 753 case ISD::TRUNCATE: return visitTRUNCATE(N); 754 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); 755 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); 756 case ISD::FADD: return visitFADD(N); 757 case ISD::FSUB: return visitFSUB(N); 758 case ISD::FMUL: return visitFMUL(N); 759 case ISD::FDIV: return visitFDIV(N); 760 case ISD::FREM: return visitFREM(N); 761 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 762 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 763 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 764 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 765 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 766 case ISD::FP_ROUND: return visitFP_ROUND(N); 767 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 768 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 769 case ISD::FNEG: return visitFNEG(N); 770 case ISD::FABS: return visitFABS(N); 771 case ISD::BRCOND: return visitBRCOND(N); 772 case ISD::BR_CC: return visitBR_CC(N); 773 case ISD::LOAD: return visitLOAD(N); 774 case ISD::STORE: return visitSTORE(N); 775 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 776 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 777 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 778 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 779 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 780 } 781 return SDValue(); 782} 783 784SDValue DAGCombiner::combine(SDNode *N) { 785 SDValue RV = visit(N); 786 787 // If nothing happened, try a target-specific DAG combine. 788 if (RV.getNode() == 0) { 789 assert(N->getOpcode() != ISD::DELETED_NODE && 790 "Node was deleted but visit returned NULL!"); 791 792 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 793 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 794 795 // Expose the DAG combiner to the target combiner impls. 796 TargetLowering::DAGCombinerInfo 797 DagCombineInfo(DAG, Level == Unrestricted, false, this); 798 799 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 800 } 801 } 802 803 // If N is a commutative binary node, try commuting it to enable more 804 // sdisel CSE. 805 if (RV.getNode() == 0 && 806 SelectionDAG::isCommutativeBinOp(N->getOpcode()) && 807 N->getNumValues() == 1) { 808 SDValue N0 = N->getOperand(0); 809 SDValue N1 = N->getOperand(1); 810 811 // Constant operands are canonicalized to RHS. 812 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) { 813 SDValue Ops[] = { N1, N0 }; 814 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), 815 Ops, 2); 816 if (CSENode) 817 return SDValue(CSENode, 0); 818 } 819 } 820 821 return RV; 822} 823 824/// getInputChainForNode - Given a node, return its input chain if it has one, 825/// otherwise return a null sd operand. 826static SDValue getInputChainForNode(SDNode *N) { 827 if (unsigned NumOps = N->getNumOperands()) { 828 if (N->getOperand(0).getValueType() == MVT::Other) 829 return N->getOperand(0); 830 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 831 return N->getOperand(NumOps-1); 832 for (unsigned i = 1; i < NumOps-1; ++i) 833 if (N->getOperand(i).getValueType() == MVT::Other) 834 return N->getOperand(i); 835 } 836 return SDValue(); 837} 838 839SDValue DAGCombiner::visitTokenFactor(SDNode *N) { 840 // If N has two operands, where one has an input chain equal to the other, 841 // the 'other' chain is redundant. 842 if (N->getNumOperands() == 2) { 843 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1)) 844 return N->getOperand(0); 845 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0)) 846 return N->getOperand(1); 847 } 848 849 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 850 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor. 851 SmallPtrSet<SDNode*, 16> SeenOps; 852 bool Changed = false; // If we should replace this token factor. 853 854 // Start out with this token factor. 855 TFs.push_back(N); 856 857 // Iterate through token factors. The TFs grows when new token factors are 858 // encountered. 859 for (unsigned i = 0; i < TFs.size(); ++i) { 860 SDNode *TF = TFs[i]; 861 862 // Check each of the operands. 863 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 864 SDValue Op = TF->getOperand(i); 865 866 switch (Op.getOpcode()) { 867 case ISD::EntryToken: 868 // Entry tokens don't need to be added to the list. They are 869 // rededundant. 870 Changed = true; 871 break; 872 873 case ISD::TokenFactor: 874 if ((CombinerAA || Op.hasOneUse()) && 875 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) { 876 // Queue up for processing. 877 TFs.push_back(Op.getNode()); 878 // Clean up in case the token factor is removed. 879 AddToWorkList(Op.getNode()); 880 Changed = true; 881 break; 882 } 883 // Fall thru 884 885 default: 886 // Only add if it isn't already in the list. 887 if (SeenOps.insert(Op.getNode())) 888 Ops.push_back(Op); 889 else 890 Changed = true; 891 break; 892 } 893 } 894 } 895 896 SDValue Result; 897 898 // If we've change things around then replace token factor. 899 if (Changed) { 900 if (Ops.empty()) { 901 // The entry token is the only possible outcome. 902 Result = DAG.getEntryNode(); 903 } else { 904 // New and improved token factor. 905 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 906 MVT::Other, &Ops[0], Ops.size()); 907 } 908 909 // Don't add users to work list. 910 return CombineTo(N, Result, false); 911 } 912 913 return Result; 914} 915 916/// MERGE_VALUES can always be eliminated. 917SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) { 918 WorkListRemover DeadNodes(*this); 919 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 920 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i), 921 &DeadNodes); 922 removeFromWorkList(N); 923 DAG.DeleteNode(N); 924 return SDValue(N, 0); // Return N so it doesn't get rechecked! 925} 926 927static 928SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1, 929 SelectionDAG &DAG) { 930 MVT VT = N0.getValueType(); 931 SDValue N00 = N0.getOperand(0); 932 SDValue N01 = N0.getOperand(1); 933 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 934 935 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() && 936 isa<ConstantSDNode>(N00.getOperand(1))) { 937 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 938 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, 939 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT, 940 N00.getOperand(0), N01), 941 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT, 942 N00.getOperand(1), N01)); 943 return DAG.getNode(ISD::ADD, DL, VT, N0, N1); 944 } 945 946 return SDValue(); 947} 948 949SDValue DAGCombiner::visitADD(SDNode *N) { 950 SDValue N0 = N->getOperand(0); 951 SDValue N1 = N->getOperand(1); 952 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 953 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 954 MVT VT = N0.getValueType(); 955 956 // fold vector ops 957 if (VT.isVector()) { 958 SDValue FoldedVOp = SimplifyVBinOp(N); 959 if (FoldedVOp.getNode()) return FoldedVOp; 960 } 961 962 // fold (add x, undef) -> undef 963 if (N0.getOpcode() == ISD::UNDEF) 964 return N0; 965 if (N1.getOpcode() == ISD::UNDEF) 966 return N1; 967 // fold (add c1, c2) -> c1+c2 968 if (N0C && N1C) 969 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C); 970 // canonicalize constant to RHS 971 if (N0C && !N1C) 972 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0); 973 // fold (add x, 0) -> x 974 if (N1C && N1C->isNullValue()) 975 return N0; 976 // fold (add Sym, c) -> Sym+c 977 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 978 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C && 979 GA->getOpcode() == ISD::GlobalAddress) 980 return DAG.getGlobalAddress(GA->getGlobal(), VT, 981 GA->getOffset() + 982 (uint64_t)N1C->getSExtValue()); 983 // fold ((c1-A)+c2) -> (c1+c2)-A 984 if (N1C && N0.getOpcode() == ISD::SUB) 985 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 986 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 987 DAG.getConstant(N1C->getAPIntValue()+ 988 N0C->getAPIntValue(), VT), 989 N0.getOperand(1)); 990 // reassociate add 991 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1); 992 if (RADD.getNode() != 0) 993 return RADD; 994 // fold ((0-A) + B) -> B-A 995 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 996 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 997 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1)); 998 // fold (A + (0-B)) -> A-B 999 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 1000 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 1001 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1)); 1002 // fold (A+(B-A)) -> B 1003 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 1004 return N1.getOperand(0); 1005 // fold ((B-A)+A) -> B 1006 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1)) 1007 return N0.getOperand(0); 1008 // fold (A+(B-(A+C))) to (B-C) 1009 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1010 N0 == N1.getOperand(1).getOperand(0)) 1011 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1012 N1.getOperand(1).getOperand(1)); 1013 // fold (A+(B-(C+A))) to (B-C) 1014 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1015 N0 == N1.getOperand(1).getOperand(1)) 1016 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1017 N1.getOperand(1).getOperand(0)); 1018 // fold (A+((B-A)+or-C)) to (B+or-C) 1019 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) && 1020 N1.getOperand(0).getOpcode() == ISD::SUB && 1021 N0 == N1.getOperand(0).getOperand(1)) 1022 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT, 1023 N1.getOperand(0).getOperand(0), N1.getOperand(1)); 1024 1025 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant 1026 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) { 1027 SDValue N00 = N0.getOperand(0); 1028 SDValue N01 = N0.getOperand(1); 1029 SDValue N10 = N1.getOperand(0); 1030 SDValue N11 = N1.getOperand(1); 1031 1032 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10)) 1033 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1034 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10), 1035 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11)); 1036 } 1037 1038 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0))) 1039 return SDValue(N, 0); 1040 1041 // fold (a+b) -> (a|b) iff a and b share no bits. 1042 if (VT.isInteger() && !VT.isVector()) { 1043 APInt LHSZero, LHSOne; 1044 APInt RHSZero, RHSOne; 1045 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 1046 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1047 1048 if (LHSZero.getBoolValue()) { 1049 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1050 1051 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1052 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1053 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1054 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1055 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1); 1056 } 1057 } 1058 1059 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1060 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) { 1061 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG); 1062 if (Result.getNode()) return Result; 1063 } 1064 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) { 1065 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG); 1066 if (Result.getNode()) return Result; 1067 } 1068 1069 return SDValue(); 1070} 1071 1072SDValue DAGCombiner::visitADDC(SDNode *N) { 1073 SDValue N0 = N->getOperand(0); 1074 SDValue N1 = N->getOperand(1); 1075 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1076 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1077 MVT VT = N0.getValueType(); 1078 1079 // If the flag result is dead, turn this into an ADD. 1080 if (N->hasNUsesOfValue(0, 1)) 1081 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0), 1082 DAG.getNode(ISD::CARRY_FALSE, 1083 N->getDebugLoc(), MVT::Flag)); 1084 1085 // canonicalize constant to RHS. 1086 if (N0C && !N1C) 1087 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1088 1089 // fold (addc x, 0) -> x + no carry out 1090 if (N1C && N1C->isNullValue()) 1091 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, 1092 N->getDebugLoc(), MVT::Flag)); 1093 1094 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 1095 APInt LHSZero, LHSOne; 1096 APInt RHSZero, RHSOne; 1097 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 1098 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1099 1100 if (LHSZero.getBoolValue()) { 1101 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1102 1103 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1104 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1105 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1106 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1107 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1), 1108 DAG.getNode(ISD::CARRY_FALSE, 1109 N->getDebugLoc(), MVT::Flag)); 1110 } 1111 1112 return SDValue(); 1113} 1114 1115SDValue DAGCombiner::visitADDE(SDNode *N) { 1116 SDValue N0 = N->getOperand(0); 1117 SDValue N1 = N->getOperand(1); 1118 SDValue CarryIn = N->getOperand(2); 1119 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1120 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1121 1122 // canonicalize constant to RHS 1123 if (N0C && !N1C) 1124 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(), 1125 N1, N0, CarryIn); 1126 1127 // fold (adde x, y, false) -> (addc x, y) 1128 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1129 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1130 1131 return SDValue(); 1132} 1133 1134SDValue DAGCombiner::visitSUB(SDNode *N) { 1135 SDValue N0 = N->getOperand(0); 1136 SDValue N1 = N->getOperand(1); 1137 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1138 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1139 MVT VT = N0.getValueType(); 1140 1141 // fold vector ops 1142 if (VT.isVector()) { 1143 SDValue FoldedVOp = SimplifyVBinOp(N); 1144 if (FoldedVOp.getNode()) return FoldedVOp; 1145 } 1146 1147 // fold (sub x, x) -> 0 1148 if (N0 == N1) 1149 return DAG.getConstant(0, N->getValueType(0)); 1150 // fold (sub c1, c2) -> c1-c2 1151 if (N0C && N1C) 1152 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C); 1153 // fold (sub x, c) -> (add x, -c) 1154 if (N1C) 1155 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, 1156 DAG.getConstant(-N1C->getAPIntValue(), VT)); 1157 // fold (A+B)-A -> B 1158 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1159 return N0.getOperand(1); 1160 // fold (A+B)-B -> A 1161 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1162 return N0.getOperand(0); 1163 // fold ((A+(B+or-C))-B) -> A+or-C 1164 if (N0.getOpcode() == ISD::ADD && 1165 (N0.getOperand(1).getOpcode() == ISD::SUB || 1166 N0.getOperand(1).getOpcode() == ISD::ADD) && 1167 N0.getOperand(1).getOperand(0) == N1) 1168 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT, 1169 N0.getOperand(0), N0.getOperand(1).getOperand(1)); 1170 // fold ((A+(C+B))-B) -> A+C 1171 if (N0.getOpcode() == ISD::ADD && 1172 N0.getOperand(1).getOpcode() == ISD::ADD && 1173 N0.getOperand(1).getOperand(1) == N1) 1174 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1175 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1176 // fold ((A-(B-C))-C) -> A-B 1177 if (N0.getOpcode() == ISD::SUB && 1178 N0.getOperand(1).getOpcode() == ISD::SUB && 1179 N0.getOperand(1).getOperand(1) == N1) 1180 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1181 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1182 1183 // If either operand of a sub is undef, the result is undef 1184 if (N0.getOpcode() == ISD::UNDEF) 1185 return N0; 1186 if (N1.getOpcode() == ISD::UNDEF) 1187 return N1; 1188 1189 // If the relocation model supports it, consider symbol offsets. 1190 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1191 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) { 1192 // fold (sub Sym, c) -> Sym-c 1193 if (N1C && GA->getOpcode() == ISD::GlobalAddress) 1194 return DAG.getGlobalAddress(GA->getGlobal(), VT, 1195 GA->getOffset() - 1196 (uint64_t)N1C->getSExtValue()); 1197 // fold (sub Sym+c1, Sym+c2) -> c1-c2 1198 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1)) 1199 if (GA->getGlobal() == GB->getGlobal()) 1200 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(), 1201 VT); 1202 } 1203 1204 return SDValue(); 1205} 1206 1207SDValue DAGCombiner::visitMUL(SDNode *N) { 1208 SDValue N0 = N->getOperand(0); 1209 SDValue N1 = N->getOperand(1); 1210 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1211 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1212 MVT VT = N0.getValueType(); 1213 1214 // fold vector ops 1215 if (VT.isVector()) { 1216 SDValue FoldedVOp = SimplifyVBinOp(N); 1217 if (FoldedVOp.getNode()) return FoldedVOp; 1218 } 1219 1220 // fold (mul x, undef) -> 0 1221 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1222 return DAG.getConstant(0, VT); 1223 // fold (mul c1, c2) -> c1*c2 1224 if (N0C && N1C) 1225 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C); 1226 // canonicalize constant to RHS 1227 if (N0C && !N1C) 1228 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0); 1229 // fold (mul x, 0) -> 0 1230 if (N1C && N1C->isNullValue()) 1231 return N1; 1232 // fold (mul x, -1) -> 0-x 1233 if (N1C && N1C->isAllOnesValue()) 1234 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1235 DAG.getConstant(0, VT), N0); 1236 // fold (mul x, (1 << c)) -> x << c 1237 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1238 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1239 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1240 getShiftAmountTy())); 1241 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1242 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) { 1243 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2(); 1244 // FIXME: If the input is something that is easily negated (e.g. a 1245 // single-use add), we should put the negate there. 1246 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1247 DAG.getConstant(0, VT), 1248 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1249 DAG.getConstant(Log2Val, getShiftAmountTy()))); 1250 } 1251 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1252 if (N1C && N0.getOpcode() == ISD::SHL && 1253 isa<ConstantSDNode>(N0.getOperand(1))) { 1254 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1255 N1, N0.getOperand(1)); 1256 AddToWorkList(C3.getNode()); 1257 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1258 N0.getOperand(0), C3); 1259 } 1260 1261 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1262 // use. 1263 { 1264 SDValue Sh(0,0), Y(0,0); 1265 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1266 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1267 N0.getNode()->hasOneUse()) { 1268 Sh = N0; Y = N1; 1269 } else if (N1.getOpcode() == ISD::SHL && 1270 isa<ConstantSDNode>(N1.getOperand(1)) && 1271 N1.getNode()->hasOneUse()) { 1272 Sh = N1; Y = N0; 1273 } 1274 1275 if (Sh.getNode()) { 1276 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1277 Sh.getOperand(0), Y); 1278 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1279 Mul, Sh.getOperand(1)); 1280 } 1281 } 1282 1283 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1284 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() && 1285 isa<ConstantSDNode>(N0.getOperand(1))) 1286 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1287 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT, 1288 N0.getOperand(0), N1), 1289 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT, 1290 N0.getOperand(1), N1)); 1291 1292 // reassociate mul 1293 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1); 1294 if (RMUL.getNode() != 0) 1295 return RMUL; 1296 1297 return SDValue(); 1298} 1299 1300SDValue DAGCombiner::visitSDIV(SDNode *N) { 1301 SDValue N0 = N->getOperand(0); 1302 SDValue N1 = N->getOperand(1); 1303 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1304 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1305 MVT VT = N->getValueType(0); 1306 1307 // fold vector ops 1308 if (VT.isVector()) { 1309 SDValue FoldedVOp = SimplifyVBinOp(N); 1310 if (FoldedVOp.getNode()) return FoldedVOp; 1311 } 1312 1313 // fold (sdiv c1, c2) -> c1/c2 1314 if (N0C && N1C && !N1C->isNullValue()) 1315 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C); 1316 // fold (sdiv X, 1) -> X 1317 if (N1C && N1C->getSExtValue() == 1LL) 1318 return N0; 1319 // fold (sdiv X, -1) -> 0-X 1320 if (N1C && N1C->isAllOnesValue()) 1321 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1322 DAG.getConstant(0, VT), N0); 1323 // If we know the sign bits of both operands are zero, strength reduce to a 1324 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1325 if (!VT.isVector()) { 1326 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1327 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(), 1328 N0, N1); 1329 } 1330 // fold (sdiv X, pow2) -> simple ops after legalize 1331 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() && 1332 (isPowerOf2_64(N1C->getSExtValue()) || 1333 isPowerOf2_64(-N1C->getSExtValue()))) { 1334 // If dividing by powers of two is cheap, then don't perform the following 1335 // fold. 1336 if (TLI.isPow2DivCheap()) 1337 return SDValue(); 1338 1339 int64_t pow2 = N1C->getSExtValue(); 1340 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 1341 unsigned lg2 = Log2_64(abs2); 1342 1343 // Splat the sign bit into the register 1344 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 1345 DAG.getConstant(VT.getSizeInBits()-1, 1346 getShiftAmountTy())); 1347 AddToWorkList(SGN.getNode()); 1348 1349 // Add (N0 < 0) ? abs2 - 1 : 0; 1350 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN, 1351 DAG.getConstant(VT.getSizeInBits() - lg2, 1352 getShiftAmountTy())); 1353 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL); 1354 AddToWorkList(SRL.getNode()); 1355 AddToWorkList(ADD.getNode()); // Divide by pow2 1356 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD, 1357 DAG.getConstant(lg2, getShiftAmountTy())); 1358 1359 // If we're dividing by a positive value, we're done. Otherwise, we must 1360 // negate the result. 1361 if (pow2 > 0) 1362 return SRA; 1363 1364 AddToWorkList(SRA.getNode()); 1365 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1366 DAG.getConstant(0, VT), SRA); 1367 } 1368 1369 // if integer divide is expensive and we satisfy the requirements, emit an 1370 // alternate sequence. 1371 if (N1C && (N1C->getSExtValue() < -1 || N1C->getSExtValue() > 1) && 1372 !TLI.isIntDivCheap()) { 1373 SDValue Op = BuildSDIV(N); 1374 if (Op.getNode()) return Op; 1375 } 1376 1377 // undef / X -> 0 1378 if (N0.getOpcode() == ISD::UNDEF) 1379 return DAG.getConstant(0, VT); 1380 // X / undef -> undef 1381 if (N1.getOpcode() == ISD::UNDEF) 1382 return N1; 1383 1384 return SDValue(); 1385} 1386 1387SDValue DAGCombiner::visitUDIV(SDNode *N) { 1388 SDValue N0 = N->getOperand(0); 1389 SDValue N1 = N->getOperand(1); 1390 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1391 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1392 MVT VT = N->getValueType(0); 1393 1394 // fold vector ops 1395 if (VT.isVector()) { 1396 SDValue FoldedVOp = SimplifyVBinOp(N); 1397 if (FoldedVOp.getNode()) return FoldedVOp; 1398 } 1399 1400 // fold (udiv c1, c2) -> c1/c2 1401 if (N0C && N1C && !N1C->isNullValue()) 1402 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C); 1403 // fold (udiv x, (1 << c)) -> x >>u c 1404 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1405 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 1406 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1407 getShiftAmountTy())); 1408 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1409 if (N1.getOpcode() == ISD::SHL) { 1410 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1411 if (SHC->getAPIntValue().isPowerOf2()) { 1412 MVT ADDVT = N1.getOperand(1).getValueType(); 1413 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT, 1414 N1.getOperand(1), 1415 DAG.getConstant(SHC->getAPIntValue() 1416 .logBase2(), 1417 ADDVT)); 1418 AddToWorkList(Add.getNode()); 1419 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add); 1420 } 1421 } 1422 } 1423 // fold (udiv x, c) -> alternate 1424 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1425 SDValue Op = BuildUDIV(N); 1426 if (Op.getNode()) return Op; 1427 } 1428 1429 // undef / X -> 0 1430 if (N0.getOpcode() == ISD::UNDEF) 1431 return DAG.getConstant(0, VT); 1432 // X / undef -> undef 1433 if (N1.getOpcode() == ISD::UNDEF) 1434 return N1; 1435 1436 return SDValue(); 1437} 1438 1439SDValue DAGCombiner::visitSREM(SDNode *N) { 1440 SDValue N0 = N->getOperand(0); 1441 SDValue N1 = N->getOperand(1); 1442 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1443 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1444 MVT VT = N->getValueType(0); 1445 1446 // fold (srem c1, c2) -> c1%c2 1447 if (N0C && N1C && !N1C->isNullValue()) 1448 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C); 1449 // If we know the sign bits of both operands are zero, strength reduce to a 1450 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1451 if (!VT.isVector()) { 1452 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1453 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1); 1454 } 1455 1456 // If X/C can be simplified by the division-by-constant logic, lower 1457 // X%C to the equivalent of X-X/C*C. 1458 if (N1C && !N1C->isNullValue()) { 1459 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1); 1460 AddToWorkList(Div.getNode()); 1461 SDValue OptimizedDiv = combine(Div.getNode()); 1462 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1463 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1464 OptimizedDiv, N1); 1465 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1466 AddToWorkList(Mul.getNode()); 1467 return Sub; 1468 } 1469 } 1470 1471 // undef % X -> 0 1472 if (N0.getOpcode() == ISD::UNDEF) 1473 return DAG.getConstant(0, VT); 1474 // X % undef -> undef 1475 if (N1.getOpcode() == ISD::UNDEF) 1476 return N1; 1477 1478 return SDValue(); 1479} 1480 1481SDValue DAGCombiner::visitUREM(SDNode *N) { 1482 SDValue N0 = N->getOperand(0); 1483 SDValue N1 = N->getOperand(1); 1484 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1485 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1486 MVT VT = N->getValueType(0); 1487 1488 // fold (urem c1, c2) -> c1%c2 1489 if (N0C && N1C && !N1C->isNullValue()) 1490 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C); 1491 // fold (urem x, pow2) -> (and x, pow2-1) 1492 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2()) 1493 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, 1494 DAG.getConstant(N1C->getAPIntValue()-1,VT)); 1495 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1496 if (N1.getOpcode() == ISD::SHL) { 1497 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1498 if (SHC->getAPIntValue().isPowerOf2()) { 1499 SDValue Add = 1500 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, 1501 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), 1502 VT)); 1503 AddToWorkList(Add.getNode()); 1504 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add); 1505 } 1506 } 1507 } 1508 1509 // If X/C can be simplified by the division-by-constant logic, lower 1510 // X%C to the equivalent of X-X/C*C. 1511 if (N1C && !N1C->isNullValue()) { 1512 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1); 1513 AddToWorkList(Div.getNode()); 1514 SDValue OptimizedDiv = combine(Div.getNode()); 1515 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1516 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1517 OptimizedDiv, N1); 1518 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1519 AddToWorkList(Mul.getNode()); 1520 return Sub; 1521 } 1522 } 1523 1524 // undef % X -> 0 1525 if (N0.getOpcode() == ISD::UNDEF) 1526 return DAG.getConstant(0, VT); 1527 // X % undef -> undef 1528 if (N1.getOpcode() == ISD::UNDEF) 1529 return N1; 1530 1531 return SDValue(); 1532} 1533 1534SDValue DAGCombiner::visitMULHS(SDNode *N) { 1535 SDValue N0 = N->getOperand(0); 1536 SDValue N1 = N->getOperand(1); 1537 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1538 MVT VT = N->getValueType(0); 1539 1540 // fold (mulhs x, 0) -> 0 1541 if (N1C && N1C->isNullValue()) 1542 return N1; 1543 // fold (mulhs x, 1) -> (sra x, size(x)-1) 1544 if (N1C && N1C->getAPIntValue() == 1) 1545 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0, 1546 DAG.getConstant(N0.getValueType().getSizeInBits() - 1, 1547 getShiftAmountTy())); 1548 // fold (mulhs x, undef) -> 0 1549 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1550 return DAG.getConstant(0, VT); 1551 1552 return SDValue(); 1553} 1554 1555SDValue DAGCombiner::visitMULHU(SDNode *N) { 1556 SDValue N0 = N->getOperand(0); 1557 SDValue N1 = N->getOperand(1); 1558 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1559 MVT VT = N->getValueType(0); 1560 1561 // fold (mulhu x, 0) -> 0 1562 if (N1C && N1C->isNullValue()) 1563 return N1; 1564 // fold (mulhu x, 1) -> 0 1565 if (N1C && N1C->getAPIntValue() == 1) 1566 return DAG.getConstant(0, N0.getValueType()); 1567 // fold (mulhu x, undef) -> 0 1568 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1569 return DAG.getConstant(0, VT); 1570 1571 return SDValue(); 1572} 1573 1574/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 1575/// compute two values. LoOp and HiOp give the opcodes for the two computations 1576/// that are being performed. Return true if a simplification was made. 1577/// 1578SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 1579 unsigned HiOp) { 1580 // If the high half is not needed, just compute the low half. 1581 bool HiExists = N->hasAnyUseOfValue(1); 1582 if (!HiExists && 1583 (!LegalOperations || 1584 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 1585 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 1586 N->op_begin(), N->getNumOperands()); 1587 return CombineTo(N, Res, Res); 1588 } 1589 1590 // If the low half is not needed, just compute the high half. 1591 bool LoExists = N->hasAnyUseOfValue(0); 1592 if (!LoExists && 1593 (!LegalOperations || 1594 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 1595 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 1596 N->op_begin(), N->getNumOperands()); 1597 return CombineTo(N, Res, Res); 1598 } 1599 1600 // If both halves are used, return as it is. 1601 if (LoExists && HiExists) 1602 return SDValue(); 1603 1604 // If the two computed results can be simplified separately, separate them. 1605 if (LoExists) { 1606 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 1607 N->op_begin(), N->getNumOperands()); 1608 AddToWorkList(Lo.getNode()); 1609 SDValue LoOpt = combine(Lo.getNode()); 1610 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() && 1611 (!LegalOperations || 1612 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()))) 1613 return CombineTo(N, LoOpt, LoOpt); 1614 } 1615 1616 if (HiExists) { 1617 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 1618 N->op_begin(), N->getNumOperands()); 1619 AddToWorkList(Hi.getNode()); 1620 SDValue HiOpt = combine(Hi.getNode()); 1621 if (HiOpt.getNode() && HiOpt != Hi && 1622 (!LegalOperations || 1623 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType()))) 1624 return CombineTo(N, HiOpt, HiOpt); 1625 } 1626 1627 return SDValue(); 1628} 1629 1630SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) { 1631 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); 1632 if (Res.getNode()) return Res; 1633 1634 return SDValue(); 1635} 1636 1637SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) { 1638 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); 1639 if (Res.getNode()) return Res; 1640 1641 return SDValue(); 1642} 1643 1644SDValue DAGCombiner::visitSDIVREM(SDNode *N) { 1645 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); 1646 if (Res.getNode()) return Res; 1647 1648 return SDValue(); 1649} 1650 1651SDValue DAGCombiner::visitUDIVREM(SDNode *N) { 1652 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); 1653 if (Res.getNode()) return Res; 1654 1655 return SDValue(); 1656} 1657 1658/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 1659/// two operands of the same opcode, try to simplify it. 1660SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 1661 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 1662 MVT VT = N0.getValueType(); 1663 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 1664 1665 // For each of OP in AND/OR/XOR: 1666 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 1667 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 1668 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 1669 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) 1670 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND|| 1671 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) && 1672 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 1673 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 1674 N0.getOperand(0).getValueType(), 1675 N0.getOperand(0), N1.getOperand(0)); 1676 AddToWorkList(ORNode.getNode()); 1677 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode); 1678 } 1679 1680 // For each of OP in SHL/SRL/SRA/AND... 1681 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 1682 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 1683 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 1684 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 1685 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 1686 N0.getOperand(1) == N1.getOperand(1)) { 1687 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 1688 N0.getOperand(0).getValueType(), 1689 N0.getOperand(0), N1.getOperand(0)); 1690 AddToWorkList(ORNode.getNode()); 1691 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 1692 ORNode, N0.getOperand(1)); 1693 } 1694 1695 return SDValue(); 1696} 1697 1698SDValue DAGCombiner::visitAND(SDNode *N) { 1699 SDValue N0 = N->getOperand(0); 1700 SDValue N1 = N->getOperand(1); 1701 SDValue LL, LR, RL, RR, CC0, CC1; 1702 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1703 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1704 MVT VT = N1.getValueType(); 1705 unsigned BitWidth = VT.getSizeInBits(); 1706 1707 // fold vector ops 1708 if (VT.isVector()) { 1709 SDValue FoldedVOp = SimplifyVBinOp(N); 1710 if (FoldedVOp.getNode()) return FoldedVOp; 1711 } 1712 1713 // fold (and x, undef) -> 0 1714 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1715 return DAG.getConstant(0, VT); 1716 // fold (and c1, c2) -> c1&c2 1717 if (N0C && N1C) 1718 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C); 1719 // canonicalize constant to RHS 1720 if (N0C && !N1C) 1721 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0); 1722 // fold (and x, -1) -> x 1723 if (N1C && N1C->isAllOnesValue()) 1724 return N0; 1725 // if (and x, c) is known to be zero, return 0 1726 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 1727 APInt::getAllOnesValue(BitWidth))) 1728 return DAG.getConstant(0, VT); 1729 // reassociate and 1730 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1); 1731 if (RAND.getNode() != 0) 1732 return RAND; 1733 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF 1734 if (N1C && N0.getOpcode() == ISD::OR) 1735 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 1736 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue()) 1737 return N1; 1738 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 1739 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 1740 SDValue N0Op0 = N0.getOperand(0); 1741 APInt Mask = ~N1C->getAPIntValue(); 1742 Mask.trunc(N0Op0.getValueSizeInBits()); 1743 if (DAG.MaskedValueIsZero(N0Op0, Mask)) { 1744 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), 1745 N0.getValueType(), N0Op0); 1746 1747 // Replace uses of the AND with uses of the Zero extend node. 1748 CombineTo(N, Zext); 1749 1750 // We actually want to replace all uses of the any_extend with the 1751 // zero_extend, to avoid duplicating things. This will later cause this 1752 // AND to be folded. 1753 CombineTo(N0.getNode(), Zext); 1754 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1755 } 1756 } 1757 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 1758 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1759 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1760 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1761 1762 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1763 LL.getValueType().isInteger()) { 1764 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0) 1765 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) { 1766 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 1767 LR.getValueType(), LL, RL); 1768 AddToWorkList(ORNode.getNode()); 1769 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 1770 } 1771 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1) 1772 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 1773 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(), 1774 LR.getValueType(), LL, RL); 1775 AddToWorkList(ANDNode.getNode()); 1776 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 1777 } 1778 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1) 1779 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 1780 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 1781 LR.getValueType(), LL, RL); 1782 AddToWorkList(ORNode.getNode()); 1783 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 1784 } 1785 } 1786 // canonicalize equivalent to ll == rl 1787 if (LL == RR && LR == RL) { 1788 Op1 = ISD::getSetCCSwappedOperands(Op1); 1789 std::swap(RL, RR); 1790 } 1791 if (LL == RL && LR == RR) { 1792 bool isInteger = LL.getValueType().isInteger(); 1793 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 1794 if (Result != ISD::SETCC_INVALID && 1795 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 1796 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 1797 LL, LR, Result); 1798 } 1799 } 1800 1801 // Simplify: (and (op x...), (op y...)) -> (op (and x, y)) 1802 if (N0.getOpcode() == N1.getOpcode()) { 1803 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1804 if (Tmp.getNode()) return Tmp; 1805 } 1806 1807 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 1808 // fold (and (sra)) -> (and (srl)) when possible. 1809 if (!VT.isVector() && 1810 SimplifyDemandedBits(SDValue(N, 0))) 1811 return SDValue(N, 0); 1812 // fold (zext_inreg (extload x)) -> (zextload x) 1813 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) { 1814 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1815 MVT EVT = LN0->getMemoryVT(); 1816 // If we zero all the possible extended bits, then we can turn this into 1817 // a zextload if we are running before legalize or the operation is legal. 1818 unsigned BitWidth = N1.getValueSizeInBits(); 1819 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1820 BitWidth - EVT.getSizeInBits())) && 1821 ((!LegalOperations && !LN0->isVolatile()) || 1822 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) { 1823 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 1824 LN0->getChain(), LN0->getBasePtr(), 1825 LN0->getSrcValue(), 1826 LN0->getSrcValueOffset(), EVT, 1827 LN0->isVolatile(), LN0->getAlignment()); 1828 AddToWorkList(N); 1829 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 1830 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1831 } 1832 } 1833 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 1834 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 1835 N0.hasOneUse()) { 1836 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1837 MVT EVT = LN0->getMemoryVT(); 1838 // If we zero all the possible extended bits, then we can turn this into 1839 // a zextload if we are running before legalize or the operation is legal. 1840 unsigned BitWidth = N1.getValueSizeInBits(); 1841 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1842 BitWidth - EVT.getSizeInBits())) && 1843 ((!LegalOperations && !LN0->isVolatile()) || 1844 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) { 1845 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 1846 LN0->getChain(), 1847 LN0->getBasePtr(), LN0->getSrcValue(), 1848 LN0->getSrcValueOffset(), EVT, 1849 LN0->isVolatile(), LN0->getAlignment()); 1850 AddToWorkList(N); 1851 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 1852 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1853 } 1854 } 1855 1856 // fold (and (load x), 255) -> (zextload x, i8) 1857 // fold (and (extload x, i16), 255) -> (zextload x, i8) 1858 if (N1C && N0.getOpcode() == ISD::LOAD) { 1859 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1860 if (LN0->getExtensionType() != ISD::SEXTLOAD && 1861 LN0->isUnindexed() && N0.hasOneUse() && 1862 // Do not change the width of a volatile load. 1863 !LN0->isVolatile()) { 1864 MVT EVT = MVT::Other; 1865 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits(); 1866 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())) 1867 EVT = MVT::getIntegerVT(ActiveBits); 1868 1869 MVT LoadedVT = LN0->getMemoryVT(); 1870 1871 // Do not generate loads of non-round integer types since these can 1872 // be expensive (and would be wrong if the type is not byte sized). 1873 if (EVT != MVT::Other && LoadedVT.bitsGT(EVT) && EVT.isRound() && 1874 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) { 1875 MVT PtrType = N0.getOperand(1).getValueType(); 1876 1877 // For big endian targets, we need to add an offset to the pointer to 1878 // load the correct bytes. For little endian systems, we merely need to 1879 // read fewer bytes from the same pointer. 1880 unsigned LVTStoreBytes = LoadedVT.getStoreSizeInBits()/8; 1881 unsigned EVTStoreBytes = EVT.getStoreSizeInBits()/8; 1882 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 1883 unsigned Alignment = LN0->getAlignment(); 1884 SDValue NewPtr = LN0->getBasePtr(); 1885 1886 if (TLI.isBigEndian()) { 1887 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType, 1888 NewPtr, DAG.getConstant(PtrOff, PtrType)); 1889 Alignment = MinAlign(Alignment, PtrOff); 1890 } 1891 1892 AddToWorkList(NewPtr.getNode()); 1893 SDValue Load = 1894 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), VT, LN0->getChain(), 1895 NewPtr, LN0->getSrcValue(), LN0->getSrcValueOffset(), 1896 EVT, LN0->isVolatile(), Alignment); 1897 AddToWorkList(N); 1898 CombineTo(N0.getNode(), Load, Load.getValue(1)); 1899 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1900 } 1901 } 1902 } 1903 1904 return SDValue(); 1905} 1906 1907SDValue DAGCombiner::visitOR(SDNode *N) { 1908 SDValue N0 = N->getOperand(0); 1909 SDValue N1 = N->getOperand(1); 1910 SDValue LL, LR, RL, RR, CC0, CC1; 1911 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1912 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1913 MVT VT = N1.getValueType(); 1914 1915 // fold vector ops 1916 if (VT.isVector()) { 1917 SDValue FoldedVOp = SimplifyVBinOp(N); 1918 if (FoldedVOp.getNode()) return FoldedVOp; 1919 } 1920 1921 // fold (or x, undef) -> -1 1922 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1923 return DAG.getConstant(~0ULL, VT); 1924 // fold (or c1, c2) -> c1|c2 1925 if (N0C && N1C) 1926 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C); 1927 // canonicalize constant to RHS 1928 if (N0C && !N1C) 1929 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0); 1930 // fold (or x, 0) -> x 1931 if (N1C && N1C->isNullValue()) 1932 return N0; 1933 // fold (or x, -1) -> -1 1934 if (N1C && N1C->isAllOnesValue()) 1935 return N1; 1936 // fold (or x, c) -> c iff (x & ~c) == 0 1937 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) 1938 return N1; 1939 // reassociate or 1940 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1); 1941 if (ROR.getNode() != 0) 1942 return ROR; 1943 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 1944 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() && 1945 isa<ConstantSDNode>(N0.getOperand(1))) { 1946 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 1947 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 1948 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 1949 N0.getOperand(0), N1), 1950 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1)); 1951 } 1952 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 1953 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1954 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1955 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1956 1957 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1958 LL.getValueType().isInteger()) { 1959 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0) 1960 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0) 1961 if (cast<ConstantSDNode>(LR)->isNullValue() && 1962 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 1963 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(), 1964 LR.getValueType(), LL, RL); 1965 AddToWorkList(ORNode.getNode()); 1966 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 1967 } 1968 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1) 1969 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1) 1970 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 1971 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 1972 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(), 1973 LR.getValueType(), LL, RL); 1974 AddToWorkList(ANDNode.getNode()); 1975 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 1976 } 1977 } 1978 // canonicalize equivalent to ll == rl 1979 if (LL == RR && LR == RL) { 1980 Op1 = ISD::getSetCCSwappedOperands(Op1); 1981 std::swap(RL, RR); 1982 } 1983 if (LL == RL && LR == RR) { 1984 bool isInteger = LL.getValueType().isInteger(); 1985 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 1986 if (Result != ISD::SETCC_INVALID && 1987 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 1988 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 1989 LL, LR, Result); 1990 } 1991 } 1992 1993 // Simplify: (or (op x...), (op y...)) -> (op (or x, y)) 1994 if (N0.getOpcode() == N1.getOpcode()) { 1995 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1996 if (Tmp.getNode()) return Tmp; 1997 } 1998 1999 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible. 2000 if (N0.getOpcode() == ISD::AND && 2001 N1.getOpcode() == ISD::AND && 2002 N0.getOperand(1).getOpcode() == ISD::Constant && 2003 N1.getOperand(1).getOpcode() == ISD::Constant && 2004 // Don't increase # computations. 2005 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) { 2006 // We can only do this xform if we know that bits from X that are set in C2 2007 // but not in C1 are already zero. Likewise for Y. 2008 const APInt &LHSMask = 2009 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 2010 const APInt &RHSMask = 2011 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue(); 2012 2013 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 2014 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 2015 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 2016 N0.getOperand(0), N1.getOperand(0)); 2017 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X, 2018 DAG.getConstant(LHSMask | RHSMask, VT)); 2019 } 2020 } 2021 2022 // See if this is some rotate idiom. 2023 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc())) 2024 return SDValue(Rot, 0); 2025 2026 return SDValue(); 2027} 2028 2029/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 2030static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) { 2031 if (Op.getOpcode() == ISD::AND) { 2032 if (isa<ConstantSDNode>(Op.getOperand(1))) { 2033 Mask = Op.getOperand(1); 2034 Op = Op.getOperand(0); 2035 } else { 2036 return false; 2037 } 2038 } 2039 2040 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 2041 Shift = Op; 2042 return true; 2043 } 2044 2045 return false; 2046} 2047 2048// MatchRotate - Handle an 'or' of two operands. If this is one of the many 2049// idioms for rotate, and if the target supports rotation instructions, generate 2050// a rot[lr]. 2051SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) { 2052 // Must be a legal type. Expanded 'n promoted things won't work with rotates. 2053 MVT VT = LHS.getValueType(); 2054 if (!TLI.isTypeLegal(VT)) return 0; 2055 2056 // The target must have at least one rotate flavor. 2057 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT); 2058 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT); 2059 if (!HasROTL && !HasROTR) return 0; 2060 2061 // Match "(X shl/srl V1) & V2" where V2 may not be present. 2062 SDValue LHSShift; // The shift. 2063 SDValue LHSMask; // AND value if any. 2064 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 2065 return 0; // Not part of a rotate. 2066 2067 SDValue RHSShift; // The shift. 2068 SDValue RHSMask; // AND value if any. 2069 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 2070 return 0; // Not part of a rotate. 2071 2072 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 2073 return 0; // Not shifting the same value. 2074 2075 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 2076 return 0; // Shifts must disagree. 2077 2078 // Canonicalize shl to left side in a shl/srl pair. 2079 if (RHSShift.getOpcode() == ISD::SHL) { 2080 std::swap(LHS, RHS); 2081 std::swap(LHSShift, RHSShift); 2082 std::swap(LHSMask , RHSMask ); 2083 } 2084 2085 unsigned OpSizeInBits = VT.getSizeInBits(); 2086 SDValue LHSShiftArg = LHSShift.getOperand(0); 2087 SDValue LHSShiftAmt = LHSShift.getOperand(1); 2088 SDValue RHSShiftAmt = RHSShift.getOperand(1); 2089 2090 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 2091 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 2092 if (LHSShiftAmt.getOpcode() == ISD::Constant && 2093 RHSShiftAmt.getOpcode() == ISD::Constant) { 2094 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue(); 2095 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue(); 2096 if ((LShVal + RShVal) != OpSizeInBits) 2097 return 0; 2098 2099 SDValue Rot; 2100 if (HasROTL) 2101 Rot = DAG.getNode(ISD::ROTL, DL, VT, LHSShiftArg, LHSShiftAmt); 2102 else 2103 Rot = DAG.getNode(ISD::ROTR, DL, VT, LHSShiftArg, RHSShiftAmt); 2104 2105 // If there is an AND of either shifted operand, apply it to the result. 2106 if (LHSMask.getNode() || RHSMask.getNode()) { 2107 APInt Mask = APInt::getAllOnesValue(OpSizeInBits); 2108 2109 if (LHSMask.getNode()) { 2110 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal); 2111 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits; 2112 } 2113 if (RHSMask.getNode()) { 2114 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal); 2115 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits; 2116 } 2117 2118 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT)); 2119 } 2120 2121 return Rot.getNode(); 2122 } 2123 2124 // If there is a mask here, and we have a variable shift, we can't be sure 2125 // that we're masking out the right stuff. 2126 if (LHSMask.getNode() || RHSMask.getNode()) 2127 return 0; 2128 2129 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 2130 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 2131 if (RHSShiftAmt.getOpcode() == ISD::SUB && 2132 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 2133 if (ConstantSDNode *SUBC = 2134 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 2135 if (SUBC->getAPIntValue() == OpSizeInBits) { 2136 if (HasROTL) 2137 return DAG.getNode(ISD::ROTL, DL, VT, 2138 LHSShiftArg, LHSShiftAmt).getNode(); 2139 else 2140 return DAG.getNode(ISD::ROTR, DL, VT, 2141 LHSShiftArg, RHSShiftAmt).getNode(); 2142 } 2143 } 2144 } 2145 2146 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 2147 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 2148 if (LHSShiftAmt.getOpcode() == ISD::SUB && 2149 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 2150 if (ConstantSDNode *SUBC = 2151 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 2152 if (SUBC->getAPIntValue() == OpSizeInBits) { 2153 if (HasROTR) 2154 return DAG.getNode(ISD::ROTR, DL, VT, 2155 LHSShiftArg, RHSShiftAmt).getNode(); 2156 else 2157 return DAG.getNode(ISD::ROTL, DL, VT, 2158 LHSShiftArg, LHSShiftAmt).getNode(); 2159 } 2160 } 2161 } 2162 2163 // Look for sign/zext/any-extended or truncate cases: 2164 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2165 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2166 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2167 || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) && 2168 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2169 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2170 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2171 || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) { 2172 SDValue LExtOp0 = LHSShiftAmt.getOperand(0); 2173 SDValue RExtOp0 = RHSShiftAmt.getOperand(0); 2174 if (RExtOp0.getOpcode() == ISD::SUB && 2175 RExtOp0.getOperand(1) == LExtOp0) { 2176 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2177 // (rotl x, y) 2178 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2179 // (rotr x, (sub 32, y)) 2180 if (ConstantSDNode *SUBC = 2181 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 2182 if (SUBC->getAPIntValue() == OpSizeInBits) { 2183 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, 2184 LHSShiftArg, 2185 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode(); 2186 } 2187 } 2188 } else if (LExtOp0.getOpcode() == ISD::SUB && 2189 RExtOp0 == LExtOp0.getOperand(1)) { 2190 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2191 // (rotr x, y) 2192 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2193 // (rotl x, (sub 32, y)) 2194 if (ConstantSDNode *SUBC = 2195 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 2196 if (SUBC->getAPIntValue() == OpSizeInBits) { 2197 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, 2198 LHSShiftArg, 2199 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode(); 2200 } 2201 } 2202 } 2203 } 2204 2205 return 0; 2206} 2207 2208SDValue DAGCombiner::visitXOR(SDNode *N) { 2209 SDValue N0 = N->getOperand(0); 2210 SDValue N1 = N->getOperand(1); 2211 SDValue LHS, RHS, CC; 2212 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2213 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2214 MVT VT = N0.getValueType(); 2215 2216 // fold vector ops 2217 if (VT.isVector()) { 2218 SDValue FoldedVOp = SimplifyVBinOp(N); 2219 if (FoldedVOp.getNode()) return FoldedVOp; 2220 } 2221 2222 // fold (xor undef, undef) -> 0. This is a common idiom (misuse). 2223 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 2224 return DAG.getConstant(0, VT); 2225 // fold (xor x, undef) -> undef 2226 if (N0.getOpcode() == ISD::UNDEF) 2227 return N0; 2228 if (N1.getOpcode() == ISD::UNDEF) 2229 return N1; 2230 // fold (xor c1, c2) -> c1^c2 2231 if (N0C && N1C) 2232 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C); 2233 // canonicalize constant to RHS 2234 if (N0C && !N1C) 2235 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 2236 // fold (xor x, 0) -> x 2237 if (N1C && N1C->isNullValue()) 2238 return N0; 2239 // reassociate xor 2240 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1); 2241 if (RXOR.getNode() != 0) 2242 return RXOR; 2243 2244 // fold !(x cc y) -> (x !cc y) 2245 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 2246 bool isInt = LHS.getValueType().isInteger(); 2247 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 2248 isInt); 2249 2250 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) { 2251 switch (N0.getOpcode()) { 2252 default: 2253 assert(0 && "Unhandled SetCC Equivalent!"); 2254 abort(); 2255 case ISD::SETCC: 2256 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC); 2257 case ISD::SELECT_CC: 2258 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2), 2259 N0.getOperand(3), NotCC); 2260 } 2261 } 2262 } 2263 2264 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 2265 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 2266 N0.getNode()->hasOneUse() && 2267 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 2268 SDValue V = N0.getOperand(0); 2269 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V, 2270 DAG.getConstant(1, V.getValueType())); 2271 AddToWorkList(V.getNode()); 2272 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V); 2273 } 2274 2275 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc 2276 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 && 2277 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2278 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2279 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 2280 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2281 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 2282 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 2283 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2284 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 2285 } 2286 } 2287 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants 2288 if (N1C && N1C->isAllOnesValue() && 2289 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2290 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2291 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 2292 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2293 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 2294 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 2295 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2296 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 2297 } 2298 } 2299 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2)) 2300 if (N1C && N0.getOpcode() == ISD::XOR) { 2301 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 2302 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2303 if (N00C) 2304 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1), 2305 DAG.getConstant(N1C->getAPIntValue() ^ 2306 N00C->getAPIntValue(), VT)); 2307 if (N01C) 2308 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0), 2309 DAG.getConstant(N1C->getAPIntValue() ^ 2310 N01C->getAPIntValue(), VT)); 2311 } 2312 // fold (xor x, x) -> 0 2313 if (N0 == N1) { 2314 if (!VT.isVector()) { 2315 return DAG.getConstant(0, VT); 2316 } else if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)){ 2317 // Produce a vector of zeros. 2318 SDValue El = DAG.getConstant(0, VT.getVectorElementType()); 2319 std::vector<SDValue> Ops(VT.getVectorNumElements(), El); 2320 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 2321 &Ops[0], Ops.size()); 2322 } 2323 } 2324 2325 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 2326 if (N0.getOpcode() == N1.getOpcode()) { 2327 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2328 if (Tmp.getNode()) return Tmp; 2329 } 2330 2331 // Simplify the expression using non-local knowledge. 2332 if (!VT.isVector() && 2333 SimplifyDemandedBits(SDValue(N, 0))) 2334 return SDValue(N, 0); 2335 2336 return SDValue(); 2337} 2338 2339/// visitShiftByConstant - Handle transforms common to the three shifts, when 2340/// the shift amount is a constant. 2341SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 2342 SDNode *LHS = N->getOperand(0).getNode(); 2343 if (!LHS->hasOneUse()) return SDValue(); 2344 2345 // We want to pull some binops through shifts, so that we have (and (shift)) 2346 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 2347 // thing happens with address calculations, so it's important to canonicalize 2348 // it. 2349 bool HighBitSet = false; // Can we transform this if the high bit is set? 2350 2351 switch (LHS->getOpcode()) { 2352 default: return SDValue(); 2353 case ISD::OR: 2354 case ISD::XOR: 2355 HighBitSet = false; // We can only transform sra if the high bit is clear. 2356 break; 2357 case ISD::AND: 2358 HighBitSet = true; // We can only transform sra if the high bit is set. 2359 break; 2360 case ISD::ADD: 2361 if (N->getOpcode() != ISD::SHL) 2362 return SDValue(); // only shl(add) not sr[al](add). 2363 HighBitSet = false; // We can only transform sra if the high bit is clear. 2364 break; 2365 } 2366 2367 // We require the RHS of the binop to be a constant as well. 2368 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 2369 if (!BinOpCst) return SDValue(); 2370 2371 // FIXME: disable this unless the input to the binop is a shift by a constant. 2372 // If it is not a shift, it pessimizes some common cases like: 2373 // 2374 // void foo(int *X, int i) { X[i & 1235] = 1; } 2375 // int bar(int *X, int i) { return X[i & 255]; } 2376 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode(); 2377 if ((BinOpLHSVal->getOpcode() != ISD::SHL && 2378 BinOpLHSVal->getOpcode() != ISD::SRA && 2379 BinOpLHSVal->getOpcode() != ISD::SRL) || 2380 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 2381 return SDValue(); 2382 2383 MVT VT = N->getValueType(0); 2384 2385 // If this is a signed shift right, and the high bit is modified by the 2386 // logical operation, do not perform the transformation. The highBitSet 2387 // boolean indicates the value of the high bit of the constant which would 2388 // cause it to be modified for this operation. 2389 if (N->getOpcode() == ISD::SRA) { 2390 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative(); 2391 if (BinOpRHSSignSet != HighBitSet) 2392 return SDValue(); 2393 } 2394 2395 // Fold the constants, shifting the binop RHS by the shift amount. 2396 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(), 2397 N->getValueType(0), 2398 LHS->getOperand(1), N->getOperand(1)); 2399 2400 // Create the new shift. 2401 SDValue NewShift = DAG.getNode(N->getOpcode(), LHS->getOperand(0).getDebugLoc(), 2402 VT, LHS->getOperand(0), N->getOperand(1)); 2403 2404 // Create the new binop. 2405 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS); 2406} 2407 2408SDValue DAGCombiner::visitSHL(SDNode *N) { 2409 SDValue N0 = N->getOperand(0); 2410 SDValue N1 = N->getOperand(1); 2411 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2412 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2413 MVT VT = N0.getValueType(); 2414 unsigned OpSizeInBits = VT.getSizeInBits(); 2415 2416 // fold (shl c1, c2) -> c1<<c2 2417 if (N0C && N1C) 2418 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C); 2419 // fold (shl 0, x) -> 0 2420 if (N0C && N0C->isNullValue()) 2421 return N0; 2422 // fold (shl x, c >= size(x)) -> undef 2423 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2424 return DAG.getUNDEF(VT); 2425 // fold (shl x, 0) -> x 2426 if (N1C && N1C->isNullValue()) 2427 return N0; 2428 // if (shl x, c) is known to be zero, return 0 2429 if (DAG.MaskedValueIsZero(SDValue(N, 0), 2430 APInt::getAllOnesValue(VT.getSizeInBits()))) 2431 return DAG.getConstant(0, VT); 2432 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))). 2433 if (N1.getOpcode() == ISD::TRUNCATE && 2434 N1.getOperand(0).getOpcode() == ISD::AND && 2435 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2436 SDValue N101 = N1.getOperand(0).getOperand(1); 2437 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2438 MVT TruncVT = N1.getValueType(); 2439 SDValue N100 = N1.getOperand(0).getOperand(0); 2440 APInt TruncC = N101C->getAPIntValue(); 2441 TruncC.trunc(TruncVT.getSizeInBits()); 2442 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 2443 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT, 2444 DAG.getNode(ISD::TRUNCATE, 2445 N->getDebugLoc(), 2446 TruncVT, N100), 2447 DAG.getConstant(TruncC, TruncVT))); 2448 } 2449 } 2450 2451 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2452 return SDValue(N, 0); 2453 2454 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2)) 2455 if (N1C && N0.getOpcode() == ISD::SHL && 2456 N0.getOperand(1).getOpcode() == ISD::Constant) { 2457 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2458 uint64_t c2 = N1C->getZExtValue(); 2459 if (c1 + c2 > OpSizeInBits) 2460 return DAG.getConstant(0, VT); 2461 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0), 2462 DAG.getConstant(c1 + c2, N1.getValueType())); 2463 } 2464 // fold (shl (srl x, c1), c2) -> (shl (and x, (shl -1, c1)), (sub c2, c1)) or 2465 // (srl (and x, (shl -1, c1)), (sub c1, c2)) 2466 if (N1C && N0.getOpcode() == ISD::SRL && 2467 N0.getOperand(1).getOpcode() == ISD::Constant) { 2468 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2469 uint64_t c2 = N1C->getZExtValue(); 2470 SDValue Mask = DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, N0.getOperand(0), 2471 DAG.getConstant(~0ULL << c1, VT)); 2472 if (c2 > c1) 2473 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, Mask, 2474 DAG.getConstant(c2-c1, N1.getValueType())); 2475 else 2476 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Mask, 2477 DAG.getConstant(c1-c2, N1.getValueType())); 2478 } 2479 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1)) 2480 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) 2481 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 2482 DAG.getConstant(~0ULL << N1C->getZExtValue(), VT)); 2483 2484 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2485} 2486 2487SDValue DAGCombiner::visitSRA(SDNode *N) { 2488 SDValue N0 = N->getOperand(0); 2489 SDValue N1 = N->getOperand(1); 2490 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2491 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2492 MVT VT = N0.getValueType(); 2493 2494 // fold (sra c1, c2) -> (sra c1, c2) 2495 if (N0C && N1C) 2496 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C); 2497 // fold (sra 0, x) -> 0 2498 if (N0C && N0C->isNullValue()) 2499 return N0; 2500 // fold (sra -1, x) -> -1 2501 if (N0C && N0C->isAllOnesValue()) 2502 return N0; 2503 // fold (sra x, (setge c, size(x))) -> undef 2504 if (N1C && N1C->getZExtValue() >= VT.getSizeInBits()) 2505 return DAG.getUNDEF(VT); 2506 // fold (sra x, 0) -> x 2507 if (N1C && N1C->isNullValue()) 2508 return N0; 2509 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 2510 // sext_inreg. 2511 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 2512 unsigned LowBits = VT.getSizeInBits() - (unsigned)N1C->getZExtValue(); 2513 MVT EVT = MVT::getIntegerVT(LowBits); 2514 if ((!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT))) 2515 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 2516 N0.getOperand(0), DAG.getValueType(EVT)); 2517 } 2518 2519 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2)) 2520 if (N1C && N0.getOpcode() == ISD::SRA) { 2521 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2522 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue(); 2523 if (Sum >= VT.getSizeInBits()) Sum = VT.getSizeInBits()-1; 2524 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0), 2525 DAG.getConstant(Sum, N1C->getValueType(0))); 2526 } 2527 } 2528 2529 // fold (sra (shl X, m), (sub result_size, n)) 2530 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for 2531 // result_size - n != m. 2532 // If truncate is free for the target sext(shl) is likely to result in better 2533 // code. 2534 if (N0.getOpcode() == ISD::SHL) { 2535 // Get the two constanst of the shifts, CN0 = m, CN = n. 2536 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2537 if (N01C && N1C) { 2538 // Determine what the truncate's result bitsize and type would be. 2539 unsigned VTValSize = VT.getSizeInBits(); 2540 MVT TruncVT = 2541 MVT::getIntegerVT(VTValSize - N1C->getZExtValue()); 2542 // Determine the residual right-shift amount. 2543 unsigned ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue(); 2544 2545 // If the shift is not a no-op (in which case this should be just a sign 2546 // extend already), the truncated to type is legal, sign_extend is legal 2547 // on that type, and the the truncate to that type is both legal and free, 2548 // perform the transform. 2549 if (ShiftAmt && 2550 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) && 2551 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) && 2552 TLI.isTruncateFree(VT, TruncVT)) { 2553 2554 SDValue Amt = DAG.getConstant(ShiftAmt, getShiftAmountTy()); 2555 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, 2556 N0.getOperand(0), Amt); 2557 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT, 2558 Shift); 2559 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), 2560 N->getValueType(0), Trunc); 2561 } 2562 } 2563 } 2564 2565 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))). 2566 if (N1.getOpcode() == ISD::TRUNCATE && 2567 N1.getOperand(0).getOpcode() == ISD::AND && 2568 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2569 SDValue N101 = N1.getOperand(0).getOperand(1); 2570 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2571 MVT TruncVT = N1.getValueType(); 2572 SDValue N100 = N1.getOperand(0).getOperand(0); 2573 APInt TruncC = N101C->getAPIntValue(); 2574 TruncC.trunc(TruncVT.getSizeInBits()); 2575 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 2576 DAG.getNode(ISD::AND, N->getDebugLoc(), 2577 TruncVT, 2578 DAG.getNode(ISD::TRUNCATE, 2579 N->getDebugLoc(), 2580 TruncVT, N100), 2581 DAG.getConstant(TruncC, TruncVT))); 2582 } 2583 } 2584 2585 // Simplify, based on bits shifted out of the LHS. 2586 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2587 return SDValue(N, 0); 2588 2589 2590 // If the sign bit is known to be zero, switch this to a SRL. 2591 if (DAG.SignBitIsZero(N0)) 2592 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1); 2593 2594 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2595} 2596 2597SDValue DAGCombiner::visitSRL(SDNode *N) { 2598 SDValue N0 = N->getOperand(0); 2599 SDValue N1 = N->getOperand(1); 2600 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2601 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2602 MVT VT = N0.getValueType(); 2603 unsigned OpSizeInBits = VT.getSizeInBits(); 2604 2605 // fold (srl c1, c2) -> c1 >>u c2 2606 if (N0C && N1C) 2607 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C); 2608 // fold (srl 0, x) -> 0 2609 if (N0C && N0C->isNullValue()) 2610 return N0; 2611 // fold (srl x, c >= size(x)) -> undef 2612 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2613 return DAG.getUNDEF(VT); 2614 // fold (srl x, 0) -> x 2615 if (N1C && N1C->isNullValue()) 2616 return N0; 2617 // if (srl x, c) is known to be zero, return 0 2618 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 2619 APInt::getAllOnesValue(OpSizeInBits))) 2620 return DAG.getConstant(0, VT); 2621 2622 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2)) 2623 if (N1C && N0.getOpcode() == ISD::SRL && 2624 N0.getOperand(1).getOpcode() == ISD::Constant) { 2625 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2626 uint64_t c2 = N1C->getZExtValue(); 2627 if (c1 + c2 > OpSizeInBits) 2628 return DAG.getConstant(0, VT); 2629 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), 2630 DAG.getConstant(c1 + c2, N1.getValueType())); 2631 } 2632 2633 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 2634 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2635 // Shifting in all undef bits? 2636 MVT SmallVT = N0.getOperand(0).getValueType(); 2637 if (N1C->getZExtValue() >= SmallVT.getSizeInBits()) 2638 return DAG.getUNDEF(VT); 2639 2640 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT, 2641 N0.getOperand(0), N1); 2642 AddToWorkList(SmallShift.getNode()); 2643 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift); 2644 } 2645 2646 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 2647 // bit, which is unmodified by sra. 2648 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) { 2649 if (N0.getOpcode() == ISD::SRA) 2650 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1); 2651 } 2652 2653 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 2654 if (N1C && N0.getOpcode() == ISD::CTLZ && 2655 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) { 2656 APInt KnownZero, KnownOne; 2657 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 2658 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 2659 2660 // If any of the input bits are KnownOne, then the input couldn't be all 2661 // zeros, thus the result of the srl will always be zero. 2662 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT); 2663 2664 // If all of the bits input the to ctlz node are known to be zero, then 2665 // the result of the ctlz is "32" and the result of the shift is one. 2666 APInt UnknownBits = ~KnownZero & Mask; 2667 if (UnknownBits == 0) return DAG.getConstant(1, VT); 2668 2669 // Otherwise, check to see if there is exactly one bit input to the ctlz. 2670 if ((UnknownBits & (UnknownBits - 1)) == 0) { 2671 // Okay, we know that only that the single bit specified by UnknownBits 2672 // could be set on input to the CTLZ node. If this bit is set, the SRL 2673 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 2674 // to an SRL/XOR pair, which is likely to simplify more. 2675 unsigned ShAmt = UnknownBits.countTrailingZeros(); 2676 SDValue Op = N0.getOperand(0); 2677 2678 if (ShAmt) { 2679 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op, 2680 DAG.getConstant(ShAmt, getShiftAmountTy())); 2681 AddToWorkList(Op.getNode()); 2682 } 2683 2684 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 2685 Op, DAG.getConstant(1, VT)); 2686 } 2687 } 2688 2689 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))). 2690 if (N1.getOpcode() == ISD::TRUNCATE && 2691 N1.getOperand(0).getOpcode() == ISD::AND && 2692 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2693 SDValue N101 = N1.getOperand(0).getOperand(1); 2694 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2695 MVT TruncVT = N1.getValueType(); 2696 SDValue N100 = N1.getOperand(0).getOperand(0); 2697 APInt TruncC = N101C->getAPIntValue(); 2698 TruncC.trunc(TruncVT.getSizeInBits()); 2699 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 2700 DAG.getNode(ISD::AND, N->getDebugLoc(), 2701 TruncVT, 2702 DAG.getNode(ISD::TRUNCATE, 2703 N->getDebugLoc(), 2704 TruncVT, N100), 2705 DAG.getConstant(TruncC, TruncVT))); 2706 } 2707 } 2708 2709 // fold operands of srl based on knowledge that the low bits are not 2710 // demanded. 2711 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2712 return SDValue(N, 0); 2713 2714 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2715} 2716 2717SDValue DAGCombiner::visitCTLZ(SDNode *N) { 2718 SDValue N0 = N->getOperand(0); 2719 MVT VT = N->getValueType(0); 2720 2721 // fold (ctlz c1) -> c2 2722 if (isa<ConstantSDNode>(N0)) 2723 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0); 2724 return SDValue(); 2725} 2726 2727SDValue DAGCombiner::visitCTTZ(SDNode *N) { 2728 SDValue N0 = N->getOperand(0); 2729 MVT VT = N->getValueType(0); 2730 2731 // fold (cttz c1) -> c2 2732 if (isa<ConstantSDNode>(N0)) 2733 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0); 2734 return SDValue(); 2735} 2736 2737SDValue DAGCombiner::visitCTPOP(SDNode *N) { 2738 SDValue N0 = N->getOperand(0); 2739 MVT VT = N->getValueType(0); 2740 2741 // fold (ctpop c1) -> c2 2742 if (isa<ConstantSDNode>(N0)) 2743 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0); 2744 return SDValue(); 2745} 2746 2747SDValue DAGCombiner::visitSELECT(SDNode *N) { 2748 SDValue N0 = N->getOperand(0); 2749 SDValue N1 = N->getOperand(1); 2750 SDValue N2 = N->getOperand(2); 2751 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2752 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2753 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 2754 MVT VT = N->getValueType(0); 2755 MVT VT0 = N0.getValueType(); 2756 2757 // fold (select C, X, X) -> X 2758 if (N1 == N2) 2759 return N1; 2760 // fold (select true, X, Y) -> X 2761 if (N0C && !N0C->isNullValue()) 2762 return N1; 2763 // fold (select false, X, Y) -> Y 2764 if (N0C && N0C->isNullValue()) 2765 return N2; 2766 // fold (select C, 1, X) -> (or C, X) 2767 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1) 2768 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 2769 // fold (select C, 0, 1) -> (xor C, 1) 2770 if (VT.isInteger() && 2771 (VT0 == MVT::i1 || 2772 (VT0.isInteger() && 2773 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent)) && 2774 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) { 2775 SDValue XORNode; 2776 if (VT == VT0) 2777 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0, 2778 N0, DAG.getConstant(1, VT0)); 2779 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0, 2780 N0, DAG.getConstant(1, VT0)); 2781 AddToWorkList(XORNode.getNode()); 2782 if (VT.bitsGT(VT0)) 2783 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode); 2784 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode); 2785 } 2786 // fold (select C, 0, X) -> (and (not C), X) 2787 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 2788 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 2789 AddToWorkList(NOTNode.getNode()); 2790 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2); 2791 } 2792 // fold (select C, X, 1) -> (or (not C), X) 2793 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) { 2794 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 2795 AddToWorkList(NOTNode.getNode()); 2796 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1); 2797 } 2798 // fold (select C, X, 0) -> (and C, X) 2799 if (VT == MVT::i1 && N2C && N2C->isNullValue()) 2800 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 2801 // fold (select X, X, Y) -> (or X, Y) 2802 // fold (select X, 1, Y) -> (or X, Y) 2803 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1))) 2804 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 2805 // fold (select X, Y, X) -> (and X, Y) 2806 // fold (select X, Y, 0) -> (and X, Y) 2807 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0))) 2808 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 2809 2810 // If we can fold this based on the true/false value, do so. 2811 if (SimplifySelectOps(N, N1, N2)) 2812 return SDValue(N, 0); // Don't revisit N. 2813 2814 // fold selects based on a setcc into other things, such as min/max/abs 2815 if (N0.getOpcode() == ISD::SETCC) { 2816 // FIXME: 2817 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 2818 // having to say they don't support SELECT_CC on every type the DAG knows 2819 // about, since there is no way to mark an opcode illegal at all value types 2820 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other)) 2821 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, 2822 N0.getOperand(0), N0.getOperand(1), 2823 N1, N2, N0.getOperand(2)); 2824 return SimplifySelect(N->getDebugLoc(), N0, N1, N2); 2825 } 2826 2827 return SDValue(); 2828} 2829 2830SDValue DAGCombiner::visitSELECT_CC(SDNode *N) { 2831 SDValue N0 = N->getOperand(0); 2832 SDValue N1 = N->getOperand(1); 2833 SDValue N2 = N->getOperand(2); 2834 SDValue N3 = N->getOperand(3); 2835 SDValue N4 = N->getOperand(4); 2836 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 2837 2838 // fold select_cc lhs, rhs, x, x, cc -> x 2839 if (N2 == N3) 2840 return N2; 2841 2842 // Determine if the condition we're dealing with is constant 2843 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 2844 N0, N1, CC, N->getDebugLoc(), false); 2845 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 2846 2847 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) { 2848 if (!SCCC->isNullValue()) 2849 return N2; // cond always true -> true val 2850 else 2851 return N3; // cond always false -> false val 2852 } 2853 2854 // Fold to a simpler select_cc 2855 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC) 2856 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(), 2857 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 2858 SCC.getOperand(2)); 2859 2860 // If we can fold this based on the true/false value, do so. 2861 if (SimplifySelectOps(N, N2, N3)) 2862 return SDValue(N, 0); // Don't revisit N. 2863 2864 // fold select_cc into other things, such as min/max/abs 2865 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC); 2866} 2867 2868SDValue DAGCombiner::visitSETCC(SDNode *N) { 2869 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 2870 cast<CondCodeSDNode>(N->getOperand(2))->get(), 2871 N->getDebugLoc()); 2872} 2873 2874// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 2875// "fold ({s|z}ext (load x)) -> ({s|z}ext (truncate ({s|z}extload x)))" 2876// transformation. Returns true if extension are possible and the above 2877// mentioned transformation is profitable. 2878static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0, 2879 unsigned ExtOpc, 2880 SmallVector<SDNode*, 4> &ExtendNodes, 2881 const TargetLowering &TLI) { 2882 bool HasCopyToRegUses = false; 2883 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 2884 for (SDNode::use_iterator UI = N0.getNode()->use_begin(), 2885 UE = N0.getNode()->use_end(); 2886 UI != UE; ++UI) { 2887 SDNode *User = *UI; 2888 if (User == N) 2889 continue; 2890 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 2891 if (User->getOpcode() == ISD::SETCC) { 2892 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 2893 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 2894 // Sign bits will be lost after a zext. 2895 return false; 2896 bool Add = false; 2897 for (unsigned i = 0; i != 2; ++i) { 2898 SDValue UseOp = User->getOperand(i); 2899 if (UseOp == N0) 2900 continue; 2901 if (!isa<ConstantSDNode>(UseOp)) 2902 return false; 2903 Add = true; 2904 } 2905 if (Add) 2906 ExtendNodes.push_back(User); 2907 } else { 2908 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 2909 SDValue UseOp = User->getOperand(i); 2910 if (UseOp == N0) { 2911 // If truncate from extended type to original load type is free 2912 // on this target, then it's ok to extend a CopyToReg. 2913 if (isTruncFree && User->getOpcode() == ISD::CopyToReg) 2914 HasCopyToRegUses = true; 2915 else 2916 return false; 2917 } 2918 } 2919 } 2920 } 2921 2922 if (HasCopyToRegUses) { 2923 bool BothLiveOut = false; 2924 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 2925 UI != UE; ++UI) { 2926 SDNode *User = *UI; 2927 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 2928 SDValue UseOp = User->getOperand(i); 2929 if (UseOp.getNode() == N && UseOp.getResNo() == 0) { 2930 BothLiveOut = true; 2931 break; 2932 } 2933 } 2934 } 2935 if (BothLiveOut) 2936 // Both unextended and extended values are live out. There had better be 2937 // good a reason for the transformation. 2938 return ExtendNodes.size(); 2939 } 2940 return true; 2941} 2942 2943SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 2944 SDValue N0 = N->getOperand(0); 2945 MVT VT = N->getValueType(0); 2946 2947 // fold (sext c1) -> c1 2948 if (isa<ConstantSDNode>(N0)) 2949 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0); 2950 2951 // fold (sext (sext x)) -> (sext x) 2952 // fold (sext (aext x)) -> (sext x) 2953 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2954 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, 2955 N0.getOperand(0)); 2956 2957 if (N0.getOpcode() == ISD::TRUNCATE) { 2958 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 2959 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 2960 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 2961 if (NarrowLoad.getNode()) { 2962 if (NarrowLoad.getNode() != N0.getNode()) 2963 CombineTo(N0.getNode(), NarrowLoad); 2964 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, NarrowLoad); 2965 } 2966 2967 // See if the value being truncated is already sign extended. If so, just 2968 // eliminate the trunc/sext pair. 2969 SDValue Op = N0.getOperand(0); 2970 unsigned OpBits = Op.getValueType().getSizeInBits(); 2971 unsigned MidBits = N0.getValueType().getSizeInBits(); 2972 unsigned DestBits = VT.getSizeInBits(); 2973 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 2974 2975 if (OpBits == DestBits) { 2976 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 2977 // bits, it is already ready. 2978 if (NumSignBits > DestBits-MidBits) 2979 return Op; 2980 } else if (OpBits < DestBits) { 2981 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 2982 // bits, just sext from i32. 2983 if (NumSignBits > OpBits-MidBits) 2984 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op); 2985 } else { 2986 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 2987 // bits, just truncate to i32. 2988 if (NumSignBits > OpBits-MidBits) 2989 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 2990 } 2991 2992 // fold (sext (truncate x)) -> (sextinreg x). 2993 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 2994 N0.getValueType())) { 2995 if (Op.getValueType().bitsLT(VT)) 2996 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op); 2997 else if (Op.getValueType().bitsGT(VT)) 2998 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op); 2999 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op, 3000 DAG.getValueType(N0.getValueType())); 3001 } 3002 } 3003 3004 // fold (sext (load x)) -> (sext (truncate (sextload x))) 3005 if (ISD::isNON_EXTLoad(N0.getNode()) && 3006 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3007 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) { 3008 bool DoXform = true; 3009 SmallVector<SDNode*, 4> SetCCs; 3010 if (!N0.hasOneUse()) 3011 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 3012 if (DoXform) { 3013 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3014 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), 3015 VT, LN0->getChain(), 3016 LN0->getBasePtr(), LN0->getSrcValue(), 3017 LN0->getSrcValueOffset(), 3018 N0.getValueType(), 3019 LN0->isVolatile(), LN0->getAlignment()); 3020 CombineTo(N, ExtLoad); 3021 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3022 N0.getValueType(), ExtLoad); 3023 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3024 3025 // Extend SetCC uses if necessary. 3026 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3027 SDNode *SetCC = SetCCs[i]; 3028 SmallVector<SDValue, 4> Ops; 3029 3030 for (unsigned j = 0; j != 2; ++j) { 3031 SDValue SOp = SetCC->getOperand(j); 3032 if (SOp == Trunc) 3033 Ops.push_back(ExtLoad); 3034 else 3035 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), 3036 VT, SOp)); 3037 } 3038 3039 Ops.push_back(SetCC->getOperand(2)); 3040 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3041 SetCC->getValueType(0), 3042 &Ops[0], Ops.size())); 3043 } 3044 3045 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3046 } 3047 } 3048 3049 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 3050 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 3051 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3052 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3053 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3054 MVT EVT = LN0->getMemoryVT(); 3055 if ((!LegalOperations && !LN0->isVolatile()) || 3056 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT)) { 3057 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3058 LN0->getChain(), 3059 LN0->getBasePtr(), LN0->getSrcValue(), 3060 LN0->getSrcValueOffset(), EVT, 3061 LN0->isVolatile(), LN0->getAlignment()); 3062 CombineTo(N, ExtLoad); 3063 CombineTo(N0.getNode(), 3064 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3065 N0.getValueType(), ExtLoad), 3066 ExtLoad.getValue(1)); 3067 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3068 } 3069 } 3070 3071 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc) 3072 if (N0.getOpcode() == ISD::SETCC) { 3073 SDValue SCC = 3074 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3075 DAG.getConstant(~0ULL, VT), DAG.getConstant(0, VT), 3076 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3077 if (SCC.getNode()) return SCC; 3078 } 3079 3080 // fold (sext x) -> (zext x) if the sign bit is known zero. 3081 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) && 3082 DAG.SignBitIsZero(N0)) 3083 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 3084 3085 return SDValue(); 3086} 3087 3088SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { 3089 SDValue N0 = N->getOperand(0); 3090 MVT VT = N->getValueType(0); 3091 3092 // fold (zext c1) -> c1 3093 if (isa<ConstantSDNode>(N0)) 3094 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 3095 // fold (zext (zext x)) -> (zext x) 3096 // fold (zext (aext x)) -> (zext x) 3097 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 3098 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, 3099 N0.getOperand(0)); 3100 3101 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 3102 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 3103 if (N0.getOpcode() == ISD::TRUNCATE) { 3104 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3105 if (NarrowLoad.getNode()) { 3106 if (NarrowLoad.getNode() != N0.getNode()) 3107 CombineTo(N0.getNode(), NarrowLoad); 3108 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, NarrowLoad); 3109 } 3110 } 3111 3112 // fold (zext (truncate x)) -> (and x, mask) 3113 if (N0.getOpcode() == ISD::TRUNCATE && 3114 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) { 3115 SDValue Op = N0.getOperand(0); 3116 if (Op.getValueType().bitsLT(VT)) { 3117 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op); 3118 } else if (Op.getValueType().bitsGT(VT)) { 3119 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 3120 } 3121 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(), N0.getValueType()); 3122 } 3123 3124 // fold (zext (and (trunc x), cst)) -> (and x, cst). 3125 if (N0.getOpcode() == ISD::AND && 3126 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3127 N0.getOperand(1).getOpcode() == ISD::Constant) { 3128 SDValue X = N0.getOperand(0).getOperand(0); 3129 if (X.getValueType().bitsLT(VT)) { 3130 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X); 3131 } else if (X.getValueType().bitsGT(VT)) { 3132 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 3133 } 3134 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3135 Mask.zext(VT.getSizeInBits()); 3136 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3137 X, DAG.getConstant(Mask, VT)); 3138 } 3139 3140 // fold (zext (load x)) -> (zext (truncate (zextload x))) 3141 if (ISD::isNON_EXTLoad(N0.getNode()) && 3142 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3143 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 3144 bool DoXform = true; 3145 SmallVector<SDNode*, 4> SetCCs; 3146 if (!N0.hasOneUse()) 3147 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 3148 if (DoXform) { 3149 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3150 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 3151 LN0->getChain(), 3152 LN0->getBasePtr(), LN0->getSrcValue(), 3153 LN0->getSrcValueOffset(), 3154 N0.getValueType(), 3155 LN0->isVolatile(), LN0->getAlignment()); 3156 CombineTo(N, ExtLoad); 3157 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3158 N0.getValueType(), ExtLoad); 3159 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3160 3161 // Extend SetCC uses if necessary. 3162 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3163 SDNode *SetCC = SetCCs[i]; 3164 SmallVector<SDValue, 4> Ops; 3165 3166 for (unsigned j = 0; j != 2; ++j) { 3167 SDValue SOp = SetCC->getOperand(j); 3168 if (SOp == Trunc) 3169 Ops.push_back(ExtLoad); 3170 else 3171 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND, 3172 N->getDebugLoc(), VT, SOp)); 3173 } 3174 3175 Ops.push_back(SetCC->getOperand(2)); 3176 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3177 SetCC->getValueType(0), 3178 &Ops[0], Ops.size())); 3179 } 3180 3181 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3182 } 3183 } 3184 3185 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 3186 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 3187 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3188 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3189 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3190 MVT EVT = LN0->getMemoryVT(); 3191 if ((!LegalOperations && !LN0->isVolatile()) || 3192 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT)) { 3193 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 3194 LN0->getChain(), 3195 LN0->getBasePtr(), LN0->getSrcValue(), 3196 LN0->getSrcValueOffset(), EVT, 3197 LN0->isVolatile(), LN0->getAlignment()); 3198 CombineTo(N, ExtLoad); 3199 CombineTo(N0.getNode(), 3200 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(), 3201 ExtLoad), 3202 ExtLoad.getValue(1)); 3203 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3204 } 3205 } 3206 3207 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3208 if (N0.getOpcode() == ISD::SETCC) { 3209 SDValue SCC = 3210 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3211 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3212 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3213 if (SCC.getNode()) return SCC; 3214 } 3215 3216 return SDValue(); 3217} 3218 3219SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) { 3220 SDValue N0 = N->getOperand(0); 3221 MVT VT = N->getValueType(0); 3222 3223 // fold (aext c1) -> c1 3224 if (isa<ConstantSDNode>(N0)) 3225 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0); 3226 // fold (aext (aext x)) -> (aext x) 3227 // fold (aext (zext x)) -> (zext x) 3228 // fold (aext (sext x)) -> (sext x) 3229 if (N0.getOpcode() == ISD::ANY_EXTEND || 3230 N0.getOpcode() == ISD::ZERO_EXTEND || 3231 N0.getOpcode() == ISD::SIGN_EXTEND) 3232 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0)); 3233 3234 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 3235 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 3236 if (N0.getOpcode() == ISD::TRUNCATE) { 3237 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3238 if (NarrowLoad.getNode()) { 3239 if (NarrowLoad.getNode() != N0.getNode()) 3240 CombineTo(N0.getNode(), NarrowLoad); 3241 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, NarrowLoad); 3242 } 3243 } 3244 3245 // fold (aext (truncate x)) 3246 if (N0.getOpcode() == ISD::TRUNCATE) { 3247 SDValue TruncOp = N0.getOperand(0); 3248 if (TruncOp.getValueType() == VT) 3249 return TruncOp; // x iff x size == zext size. 3250 if (TruncOp.getValueType().bitsGT(VT)) 3251 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp); 3252 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp); 3253 } 3254 3255 // fold (aext (and (trunc x), cst)) -> (and x, cst). 3256 if (N0.getOpcode() == ISD::AND && 3257 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3258 N0.getOperand(1).getOpcode() == ISD::Constant) { 3259 SDValue X = N0.getOperand(0).getOperand(0); 3260 if (X.getValueType().bitsLT(VT)) { 3261 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X); 3262 } else if (X.getValueType().bitsGT(VT)) { 3263 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X); 3264 } 3265 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3266 Mask.zext(VT.getSizeInBits()); 3267 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3268 X, DAG.getConstant(Mask, VT)); 3269 } 3270 3271 // fold (aext (load x)) -> (aext (truncate (extload x))) 3272 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 3273 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3274 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 3275 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3276 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 3277 LN0->getChain(), 3278 LN0->getBasePtr(), LN0->getSrcValue(), 3279 LN0->getSrcValueOffset(), 3280 N0.getValueType(), 3281 LN0->isVolatile(), LN0->getAlignment()); 3282 CombineTo(N, ExtLoad); 3283 // Redirect any chain users to the new load. 3284 DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1), 3285 SDValue(ExtLoad.getNode(), 1)); 3286 // If any node needs the original loaded value, recompute it. 3287 if (!LN0->use_empty()) 3288 CombineTo(LN0, DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3289 N0.getValueType(), ExtLoad), 3290 ExtLoad.getValue(1)); 3291 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3292 } 3293 3294 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 3295 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 3296 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 3297 if (N0.getOpcode() == ISD::LOAD && 3298 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 3299 N0.hasOneUse()) { 3300 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3301 MVT EVT = LN0->getMemoryVT(); 3302 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(), 3303 VT, LN0->getChain(), LN0->getBasePtr(), 3304 LN0->getSrcValue(), 3305 LN0->getSrcValueOffset(), EVT, 3306 LN0->isVolatile(), LN0->getAlignment()); 3307 CombineTo(N, ExtLoad); 3308 CombineTo(N0.getNode(), 3309 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3310 N0.getValueType(), ExtLoad), 3311 ExtLoad.getValue(1)); 3312 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3313 } 3314 3315 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3316 if (N0.getOpcode() == ISD::SETCC) { 3317 SDValue SCC = 3318 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3319 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3320 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3321 if (SCC.getNode()) 3322 return SCC; 3323 } 3324 3325 return SDValue(); 3326} 3327 3328/// GetDemandedBits - See if the specified operand can be simplified with the 3329/// knowledge that only the bits specified by Mask are used. If so, return the 3330/// simpler operand, otherwise return a null SDValue. 3331SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) { 3332 switch (V.getOpcode()) { 3333 default: break; 3334 case ISD::OR: 3335 case ISD::XOR: 3336 // If the LHS or RHS don't contribute bits to the or, drop them. 3337 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 3338 return V.getOperand(1); 3339 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 3340 return V.getOperand(0); 3341 break; 3342 case ISD::SRL: 3343 // Only look at single-use SRLs. 3344 if (!V.getNode()->hasOneUse()) 3345 break; 3346 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 3347 // See if we can recursively simplify the LHS. 3348 unsigned Amt = RHSC->getZExtValue(); 3349 3350 // Watch out for shift count overflow though. 3351 if (Amt >= Mask.getBitWidth()) break; 3352 APInt NewMask = Mask << Amt; 3353 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask); 3354 if (SimplifyLHS.getNode()) 3355 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(), 3356 SimplifyLHS, V.getOperand(1)); 3357 } 3358 } 3359 return SDValue(); 3360} 3361 3362/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 3363/// bits and then truncated to a narrower type and where N is a multiple 3364/// of number of bits of the narrower type, transform it to a narrower load 3365/// from address + N / num of bits of new type. If the result is to be 3366/// extended, also fold the extension to form a extending load. 3367SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { 3368 unsigned Opc = N->getOpcode(); 3369 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 3370 SDValue N0 = N->getOperand(0); 3371 MVT VT = N->getValueType(0); 3372 MVT EVT = VT; 3373 3374 // This transformation isn't valid for vector loads. 3375 if (VT.isVector()) 3376 return SDValue(); 3377 3378 // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then 3379 // extended to VT. 3380 if (Opc == ISD::SIGN_EXTEND_INREG) { 3381 ExtType = ISD::SEXTLOAD; 3382 EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 3383 if (LegalOperations && !TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT)) 3384 return SDValue(); 3385 } 3386 3387 unsigned EVTBits = EVT.getSizeInBits(); 3388 unsigned ShAmt = 0; 3389 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { 3390 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3391 ShAmt = N01->getZExtValue(); 3392 // Is the shift amount a multiple of size of VT? 3393 if ((ShAmt & (EVTBits-1)) == 0) { 3394 N0 = N0.getOperand(0); 3395 if (N0.getValueType().getSizeInBits() <= EVTBits) 3396 return SDValue(); 3397 } 3398 } 3399 } 3400 3401 // Do not generate loads of non-round integer types since these can 3402 // be expensive (and would be wrong if the type is not byte sized). 3403 if (isa<LoadSDNode>(N0) && N0.hasOneUse() && EVT.isRound() && 3404 cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() > EVTBits && 3405 // Do not change the width of a volatile load. 3406 !cast<LoadSDNode>(N0)->isVolatile()) { 3407 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3408 MVT PtrType = N0.getOperand(1).getValueType(); 3409 3410 // For big endian targets, we need to adjust the offset to the pointer to 3411 // load the correct bytes. 3412 if (TLI.isBigEndian()) { 3413 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits(); 3414 unsigned EVTStoreBits = EVT.getStoreSizeInBits(); 3415 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 3416 } 3417 3418 uint64_t PtrOff = ShAmt / 8; 3419 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 3420 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), 3421 PtrType, LN0->getBasePtr(), 3422 DAG.getConstant(PtrOff, PtrType)); 3423 AddToWorkList(NewPtr.getNode()); 3424 3425 SDValue Load = (ExtType == ISD::NON_EXTLOAD) 3426 ? DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr, 3427 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff, 3428 LN0->isVolatile(), NewAlign) 3429 : DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(), NewPtr, 3430 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff, 3431 EVT, LN0->isVolatile(), NewAlign); 3432 3433 // Replace the old load's chain with the new load's chain. 3434 WorkListRemover DeadNodes(*this); 3435 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), 3436 &DeadNodes); 3437 3438 // Return the new loaded value. 3439 return Load; 3440 } 3441 3442 return SDValue(); 3443} 3444 3445SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 3446 SDValue N0 = N->getOperand(0); 3447 SDValue N1 = N->getOperand(1); 3448 MVT VT = N->getValueType(0); 3449 MVT EVT = cast<VTSDNode>(N1)->getVT(); 3450 unsigned VTBits = VT.getSizeInBits(); 3451 unsigned EVTBits = EVT.getSizeInBits(); 3452 3453 // fold (sext_in_reg c1) -> c1 3454 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 3455 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1); 3456 3457 // If the input is already sign extended, just drop the extension. 3458 if (DAG.ComputeNumSignBits(N0) >= VT.getSizeInBits()-EVTBits+1) 3459 return N0; 3460 3461 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 3462 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 3463 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) { 3464 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 3465 N0.getOperand(0), N1); 3466 } 3467 3468 // fold (sext_in_reg (sext x)) -> (sext x) 3469 // fold (sext_in_reg (aext x)) -> (sext x) 3470 // if x is small enough. 3471 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) { 3472 SDValue N00 = N0.getOperand(0); 3473 if (N00.getValueType().getSizeInBits() < EVTBits) 3474 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1); 3475 } 3476 3477 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 3478 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits))) 3479 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT); 3480 3481 // fold operands of sext_in_reg based on knowledge that the top bits are not 3482 // demanded. 3483 if (SimplifyDemandedBits(SDValue(N, 0))) 3484 return SDValue(N, 0); 3485 3486 // fold (sext_in_reg (load x)) -> (smaller sextload x) 3487 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 3488 SDValue NarrowLoad = ReduceLoadWidth(N); 3489 if (NarrowLoad.getNode()) 3490 return NarrowLoad; 3491 3492 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24) 3493 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible. 3494 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 3495 if (N0.getOpcode() == ISD::SRL) { 3496 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 3497 if (ShAmt->getZExtValue()+EVTBits <= VT.getSizeInBits()) { 3498 // We can turn this into an SRA iff the input to the SRL is already sign 3499 // extended enough. 3500 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 3501 if (VT.getSizeInBits()-(ShAmt->getZExtValue()+EVTBits) < InSignBits) 3502 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, 3503 N0.getOperand(0), N0.getOperand(1)); 3504 } 3505 } 3506 3507 // fold (sext_inreg (extload x)) -> (sextload x) 3508 if (ISD::isEXTLoad(N0.getNode()) && 3509 ISD::isUNINDEXEDLoad(N0.getNode()) && 3510 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3511 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3512 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 3513 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3514 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3515 LN0->getChain(), 3516 LN0->getBasePtr(), LN0->getSrcValue(), 3517 LN0->getSrcValueOffset(), EVT, 3518 LN0->isVolatile(), LN0->getAlignment()); 3519 CombineTo(N, ExtLoad); 3520 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 3521 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3522 } 3523 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 3524 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 3525 N0.hasOneUse() && 3526 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3527 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3528 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 3529 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3530 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3531 LN0->getChain(), 3532 LN0->getBasePtr(), LN0->getSrcValue(), 3533 LN0->getSrcValueOffset(), EVT, 3534 LN0->isVolatile(), LN0->getAlignment()); 3535 CombineTo(N, ExtLoad); 3536 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 3537 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3538 } 3539 return SDValue(); 3540} 3541 3542SDValue DAGCombiner::visitTRUNCATE(SDNode *N) { 3543 SDValue N0 = N->getOperand(0); 3544 MVT VT = N->getValueType(0); 3545 3546 // noop truncate 3547 if (N0.getValueType() == N->getValueType(0)) 3548 return N0; 3549 // fold (truncate c1) -> c1 3550 if (isa<ConstantSDNode>(N0)) 3551 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0); 3552 // fold (truncate (truncate x)) -> (truncate x) 3553 if (N0.getOpcode() == ISD::TRUNCATE) 3554 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 3555 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 3556 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND|| 3557 N0.getOpcode() == ISD::ANY_EXTEND) { 3558 if (N0.getOperand(0).getValueType().bitsLT(VT)) 3559 // if the source is smaller than the dest, we still need an extend 3560 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 3561 N0.getOperand(0)); 3562 else if (N0.getOperand(0).getValueType().bitsGT(VT)) 3563 // if the source is larger than the dest, than we just need the truncate 3564 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 3565 else 3566 // if the source and dest are the same type, we can drop both the extend 3567 // and the truncate 3568 return N0.getOperand(0); 3569 } 3570 3571 // See if we can simplify the input to this truncate through knowledge that 3572 // only the low bits are being used. For example "trunc (or (shl x, 8), y)" 3573 // -> trunc y 3574 SDValue Shorter = 3575 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(), 3576 VT.getSizeInBits())); 3577 if (Shorter.getNode()) 3578 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter); 3579 3580 // fold (truncate (load x)) -> (smaller load x) 3581 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 3582 return ReduceLoadWidth(N); 3583} 3584 3585static SDNode *getBuildPairElt(SDNode *N, unsigned i) { 3586 SDValue Elt = N->getOperand(i); 3587 if (Elt.getOpcode() != ISD::MERGE_VALUES) 3588 return Elt.getNode(); 3589 return Elt.getOperand(Elt.getResNo()).getNode(); 3590} 3591 3592/// CombineConsecutiveLoads - build_pair (load, load) -> load 3593/// if load locations are consecutive. 3594SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, MVT VT) { 3595 assert(N->getOpcode() == ISD::BUILD_PAIR); 3596 3597 SDNode *LD1 = getBuildPairElt(N, 0); 3598 if (!ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse()) 3599 return SDValue(); 3600 MVT LD1VT = LD1->getValueType(0); 3601 SDNode *LD2 = getBuildPairElt(N, 1); 3602 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 3603 3604 if (ISD::isNON_EXTLoad(LD2) && 3605 LD2->hasOneUse() && 3606 // If both are volatile this would reduce the number of volatile loads. 3607 // If one is volatile it might be ok, but play conservative and bail out. 3608 !cast<LoadSDNode>(LD1)->isVolatile() && 3609 !cast<LoadSDNode>(LD2)->isVolatile() && 3610 TLI.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1, MFI)) { 3611 LoadSDNode *LD = cast<LoadSDNode>(LD1); 3612 unsigned Align = LD->getAlignment(); 3613 unsigned NewAlign = TLI.getTargetData()-> 3614 getABITypeAlignment(VT.getTypeForMVT()); 3615 3616 if (NewAlign <= Align && 3617 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) 3618 return DAG.getLoad(VT, N->getDebugLoc(), LD->getChain(), LD->getBasePtr(), 3619 LD->getSrcValue(), LD->getSrcValueOffset(), 3620 false, Align); 3621 } 3622 3623 return SDValue(); 3624} 3625 3626SDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) { 3627 SDValue N0 = N->getOperand(0); 3628 MVT VT = N->getValueType(0); 3629 3630 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 3631 // Only do this before legalize, since afterward the target may be depending 3632 // on the bitconvert. 3633 // First check to see if this is all constant. 3634 if (!LegalTypes && 3635 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() && 3636 VT.isVector()) { 3637 bool isSimple = true; 3638 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 3639 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 3640 N0.getOperand(i).getOpcode() != ISD::Constant && 3641 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 3642 isSimple = false; 3643 break; 3644 } 3645 3646 MVT DestEltVT = N->getValueType(0).getVectorElementType(); 3647 assert(!DestEltVT.isVector() && 3648 "Element type of vector ValueType must not be vector!"); 3649 if (isSimple) 3650 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.getNode(), DestEltVT); 3651 } 3652 3653 // If the input is a constant, let getNode fold it. 3654 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 3655 SDValue Res = DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, N0); 3656 if (Res.getNode() != N) return Res; 3657 } 3658 3659 // (conv (conv x, t1), t2) -> (conv x, t2) 3660 if (N0.getOpcode() == ISD::BIT_CONVERT) 3661 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, 3662 N0.getOperand(0)); 3663 3664 // fold (conv (load x)) -> (load (conv*)x) 3665 // If the resultant load doesn't need a higher alignment than the original! 3666 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 3667 // Do not change the width of a volatile load. 3668 !cast<LoadSDNode>(N0)->isVolatile() && 3669 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) { 3670 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3671 unsigned Align = TLI.getTargetData()-> 3672 getABITypeAlignment(VT.getTypeForMVT()); 3673 unsigned OrigAlign = LN0->getAlignment(); 3674 3675 if (Align <= OrigAlign) { 3676 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(), 3677 LN0->getBasePtr(), 3678 LN0->getSrcValue(), LN0->getSrcValueOffset(), 3679 LN0->isVolatile(), OrigAlign); 3680 AddToWorkList(N); 3681 CombineTo(N0.getNode(), 3682 DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), 3683 N0.getValueType(), Load), 3684 Load.getValue(1)); 3685 return Load; 3686 } 3687 } 3688 3689 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit) 3690 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit)) 3691 // This often reduces constant pool loads. 3692 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) && 3693 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) { 3694 SDValue NewConv = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), VT, 3695 N0.getOperand(0)); 3696 AddToWorkList(NewConv.getNode()); 3697 3698 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 3699 if (N0.getOpcode() == ISD::FNEG) 3700 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 3701 NewConv, DAG.getConstant(SignBit, VT)); 3702 assert(N0.getOpcode() == ISD::FABS); 3703 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3704 NewConv, DAG.getConstant(~SignBit, VT)); 3705 } 3706 3707 // fold (bitconvert (fcopysign cst, x)) -> 3708 // (or (and (bitconvert x), sign), (and cst, (not sign))) 3709 // Note that we don't handle (copysign x, cst) because this can always be 3710 // folded to an fneg or fabs. 3711 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() && 3712 isa<ConstantFPSDNode>(N0.getOperand(0)) && 3713 VT.isInteger() && !VT.isVector()) { 3714 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits(); 3715 MVT IntXVT = MVT::getIntegerVT(OrigXWidth); 3716 if (TLI.isTypeLegal(IntXVT) || !LegalTypes) { 3717 SDValue X = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), 3718 IntXVT, N0.getOperand(1)); 3719 AddToWorkList(X.getNode()); 3720 3721 // If X has a different width than the result/lhs, sext it or truncate it. 3722 unsigned VTWidth = VT.getSizeInBits(); 3723 if (OrigXWidth < VTWidth) { 3724 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X); 3725 AddToWorkList(X.getNode()); 3726 } else if (OrigXWidth > VTWidth) { 3727 // To get the sign bit in the right place, we have to shift it right 3728 // before truncating. 3729 X = DAG.getNode(ISD::SRL, X.getDebugLoc(), 3730 X.getValueType(), X, 3731 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType())); 3732 AddToWorkList(X.getNode()); 3733 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 3734 AddToWorkList(X.getNode()); 3735 } 3736 3737 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 3738 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT, 3739 X, DAG.getConstant(SignBit, VT)); 3740 AddToWorkList(X.getNode()); 3741 3742 SDValue Cst = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), 3743 VT, N0.getOperand(0)); 3744 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT, 3745 Cst, DAG.getConstant(~SignBit, VT)); 3746 AddToWorkList(Cst.getNode()); 3747 3748 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst); 3749 } 3750 } 3751 3752 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive. 3753 if (N0.getOpcode() == ISD::BUILD_PAIR) { 3754 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT); 3755 if (CombineLD.getNode()) 3756 return CombineLD; 3757 } 3758 3759 return SDValue(); 3760} 3761 3762SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) { 3763 MVT VT = N->getValueType(0); 3764 return CombineConsecutiveLoads(N, VT); 3765} 3766 3767/// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector 3768/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 3769/// destination element value type. 3770SDValue DAGCombiner:: 3771ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT DstEltVT) { 3772 MVT SrcEltVT = BV->getOperand(0).getValueType(); 3773 3774 // If this is already the right type, we're done. 3775 if (SrcEltVT == DstEltVT) return SDValue(BV, 0); 3776 3777 unsigned SrcBitSize = SrcEltVT.getSizeInBits(); 3778 unsigned DstBitSize = DstEltVT.getSizeInBits(); 3779 3780 // If this is a conversion of N elements of one type to N elements of another 3781 // type, convert each element. This handles FP<->INT cases. 3782 if (SrcBitSize == DstBitSize) { 3783 SmallVector<SDValue, 8> Ops; 3784 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3785 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, BV->getDebugLoc(), 3786 DstEltVT, BV->getOperand(i))); 3787 AddToWorkList(Ops.back().getNode()); 3788 } 3789 MVT VT = MVT::getVectorVT(DstEltVT, 3790 BV->getValueType(0).getVectorNumElements()); 3791 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 3792 &Ops[0], Ops.size()); 3793 } 3794 3795 // Otherwise, we're growing or shrinking the elements. To avoid having to 3796 // handle annoying details of growing/shrinking FP values, we convert them to 3797 // int first. 3798 if (SrcEltVT.isFloatingPoint()) { 3799 // Convert the input float vector to a int vector where the elements are the 3800 // same sizes. 3801 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 3802 MVT IntVT = MVT::getIntegerVT(SrcEltVT.getSizeInBits()); 3803 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).getNode(); 3804 SrcEltVT = IntVT; 3805 } 3806 3807 // Now we know the input is an integer vector. If the output is a FP type, 3808 // convert to integer first, then to FP of the right size. 3809 if (DstEltVT.isFloatingPoint()) { 3810 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 3811 MVT TmpVT = MVT::getIntegerVT(DstEltVT.getSizeInBits()); 3812 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).getNode(); 3813 3814 // Next, convert to FP elements of the same size. 3815 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT); 3816 } 3817 3818 // Okay, we know the src/dst types are both integers of differing types. 3819 // Handling growing first. 3820 assert(SrcEltVT.isInteger() && DstEltVT.isInteger()); 3821 if (SrcBitSize < DstBitSize) { 3822 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 3823 3824 SmallVector<SDValue, 8> Ops; 3825 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 3826 i += NumInputsPerOutput) { 3827 bool isLE = TLI.isLittleEndian(); 3828 APInt NewBits = APInt(DstBitSize, 0); 3829 bool EltIsUndef = true; 3830 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 3831 // Shift the previously computed bits over. 3832 NewBits <<= SrcBitSize; 3833 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 3834 if (Op.getOpcode() == ISD::UNDEF) continue; 3835 EltIsUndef = false; 3836 3837 NewBits |= 3838 APInt(cast<ConstantSDNode>(Op)->getAPIntValue()).zext(DstBitSize); 3839 } 3840 3841 if (EltIsUndef) 3842 Ops.push_back(DAG.getUNDEF(DstEltVT)); 3843 else 3844 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 3845 } 3846 3847 MVT VT = MVT::getVectorVT(DstEltVT, Ops.size()); 3848 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 3849 &Ops[0], Ops.size()); 3850 } 3851 3852 // Finally, this must be the case where we are shrinking elements: each input 3853 // turns into multiple outputs. 3854 bool isS2V = ISD::isScalarToVector(BV); 3855 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 3856 MVT VT = MVT::getVectorVT(DstEltVT, NumOutputsPerInput*BV->getNumOperands()); 3857 SmallVector<SDValue, 8> Ops; 3858 3859 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3860 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 3861 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 3862 Ops.push_back(DAG.getUNDEF(DstEltVT)); 3863 continue; 3864 } 3865 3866 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getAPIntValue(); 3867 3868 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 3869 APInt ThisVal = APInt(OpVal).trunc(DstBitSize); 3870 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 3871 if (isS2V && i == 0 && j == 0 && APInt(ThisVal).zext(SrcBitSize) == OpVal) 3872 // Simply turn this into a SCALAR_TO_VECTOR of the new type. 3873 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 3874 Ops[0]); 3875 OpVal = OpVal.lshr(DstBitSize); 3876 } 3877 3878 // For big endian targets, swap the order of the pieces of each element. 3879 if (TLI.isBigEndian()) 3880 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 3881 } 3882 3883 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 3884 &Ops[0], Ops.size()); 3885} 3886 3887SDValue DAGCombiner::visitFADD(SDNode *N) { 3888 SDValue N0 = N->getOperand(0); 3889 SDValue N1 = N->getOperand(1); 3890 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3891 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3892 MVT VT = N->getValueType(0); 3893 3894 // fold vector ops 3895 if (VT.isVector()) { 3896 SDValue FoldedVOp = SimplifyVBinOp(N); 3897 if (FoldedVOp.getNode()) return FoldedVOp; 3898 } 3899 3900 // fold (fadd c1, c2) -> (fadd c1, c2) 3901 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3902 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1); 3903 // canonicalize constant to RHS 3904 if (N0CFP && !N1CFP) 3905 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0); 3906 // fold (fadd A, 0) -> A 3907 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 3908 return N0; 3909 // fold (fadd A, (fneg B)) -> (fsub A, B) 3910 if (isNegatibleForFree(N1, LegalOperations) == 2) 3911 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, 3912 GetNegatedExpression(N1, DAG, LegalOperations)); 3913 // fold (fadd (fneg A), B) -> (fsub B, A) 3914 if (isNegatibleForFree(N0, LegalOperations) == 2) 3915 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1, 3916 GetNegatedExpression(N0, DAG, LegalOperations)); 3917 3918 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 3919 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD && 3920 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 3921 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0), 3922 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 3923 N0.getOperand(1), N1)); 3924 3925 return SDValue(); 3926} 3927 3928SDValue DAGCombiner::visitFSUB(SDNode *N) { 3929 SDValue N0 = N->getOperand(0); 3930 SDValue N1 = N->getOperand(1); 3931 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3932 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3933 MVT VT = N->getValueType(0); 3934 3935 // fold vector ops 3936 if (VT.isVector()) { 3937 SDValue FoldedVOp = SimplifyVBinOp(N); 3938 if (FoldedVOp.getNode()) return FoldedVOp; 3939 } 3940 3941 // fold (fsub c1, c2) -> c1-c2 3942 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3943 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1); 3944 // fold (fsub A, 0) -> A 3945 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 3946 return N0; 3947 // fold (fsub 0, B) -> -B 3948 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) { 3949 if (isNegatibleForFree(N1, LegalOperations)) 3950 return GetNegatedExpression(N1, DAG, LegalOperations); 3951 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 3952 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N1); 3953 } 3954 // fold (fsub A, (fneg B)) -> (fadd A, B) 3955 if (isNegatibleForFree(N1, LegalOperations)) 3956 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, 3957 GetNegatedExpression(N1, DAG, LegalOperations)); 3958 3959 return SDValue(); 3960} 3961 3962SDValue DAGCombiner::visitFMUL(SDNode *N) { 3963 SDValue N0 = N->getOperand(0); 3964 SDValue N1 = N->getOperand(1); 3965 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3966 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3967 MVT VT = N->getValueType(0); 3968 3969 // fold vector ops 3970 if (VT.isVector()) { 3971 SDValue FoldedVOp = SimplifyVBinOp(N); 3972 if (FoldedVOp.getNode()) return FoldedVOp; 3973 } 3974 3975 // fold (fmul c1, c2) -> c1*c2 3976 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3977 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1); 3978 // canonicalize constant to RHS 3979 if (N0CFP && !N1CFP) 3980 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0); 3981 // fold (fmul A, 0) -> 0 3982 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 3983 return N1; 3984 // fold (fmul X, 2.0) -> (fadd X, X) 3985 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 3986 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0); 3987 // fold (fmul X, (fneg 1.0)) -> (fneg X) 3988 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 3989 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 3990 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0); 3991 3992 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y) 3993 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 3994 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 3995 // Both can be negated for free, check to see if at least one is cheaper 3996 // negated. 3997 if (LHSNeg == 2 || RHSNeg == 2) 3998 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 3999 GetNegatedExpression(N0, DAG, LegalOperations), 4000 GetNegatedExpression(N1, DAG, LegalOperations)); 4001 } 4002 } 4003 4004 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 4005 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL && 4006 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 4007 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0), 4008 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 4009 N0.getOperand(1), N1)); 4010 4011 return SDValue(); 4012} 4013 4014SDValue DAGCombiner::visitFDIV(SDNode *N) { 4015 SDValue N0 = N->getOperand(0); 4016 SDValue N1 = N->getOperand(1); 4017 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4018 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4019 MVT VT = N->getValueType(0); 4020 4021 // fold vector ops 4022 if (VT.isVector()) { 4023 SDValue FoldedVOp = SimplifyVBinOp(N); 4024 if (FoldedVOp.getNode()) return FoldedVOp; 4025 } 4026 4027 // fold (fdiv c1, c2) -> c1/c2 4028 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4029 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1); 4030 4031 4032 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y) 4033 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 4034 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 4035 // Both can be negated for free, check to see if at least one is cheaper 4036 // negated. 4037 if (LHSNeg == 2 || RHSNeg == 2) 4038 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, 4039 GetNegatedExpression(N0, DAG, LegalOperations), 4040 GetNegatedExpression(N1, DAG, LegalOperations)); 4041 } 4042 } 4043 4044 return SDValue(); 4045} 4046 4047SDValue DAGCombiner::visitFREM(SDNode *N) { 4048 SDValue N0 = N->getOperand(0); 4049 SDValue N1 = N->getOperand(1); 4050 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4051 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4052 MVT VT = N->getValueType(0); 4053 4054 // fold (frem c1, c2) -> fmod(c1,c2) 4055 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4056 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1); 4057 4058 return SDValue(); 4059} 4060 4061SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) { 4062 SDValue N0 = N->getOperand(0); 4063 SDValue N1 = N->getOperand(1); 4064 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4065 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4066 MVT VT = N->getValueType(0); 4067 4068 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold 4069 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1); 4070 4071 if (N1CFP) { 4072 const APFloat& V = N1CFP->getValueAPF(); 4073 // copysign(x, c1) -> fabs(x) iff ispos(c1) 4074 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 4075 if (!V.isNegative()) { 4076 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT)) 4077 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 4078 } else { 4079 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4080 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, 4081 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0)); 4082 } 4083 } 4084 4085 // copysign(fabs(x), y) -> copysign(x, y) 4086 // copysign(fneg(x), y) -> copysign(x, y) 4087 // copysign(copysign(x,z), y) -> copysign(x, y) 4088 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 4089 N0.getOpcode() == ISD::FCOPYSIGN) 4090 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4091 N0.getOperand(0), N1); 4092 4093 // copysign(x, abs(y)) -> abs(x) 4094 if (N1.getOpcode() == ISD::FABS) 4095 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 4096 4097 // copysign(x, copysign(y,z)) -> copysign(x, z) 4098 if (N1.getOpcode() == ISD::FCOPYSIGN) 4099 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4100 N0, N1.getOperand(1)); 4101 4102 // copysign(x, fp_extend(y)) -> copysign(x, y) 4103 // copysign(x, fp_round(y)) -> copysign(x, y) 4104 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 4105 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4106 N0, N1.getOperand(0)); 4107 4108 return SDValue(); 4109} 4110 4111SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) { 4112 SDValue N0 = N->getOperand(0); 4113 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 4114 MVT VT = N->getValueType(0); 4115 MVT OpVT = N0.getValueType(); 4116 4117 // fold (sint_to_fp c1) -> c1fp 4118 if (N0C && OpVT != MVT::ppcf128) 4119 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 4120 4121 // If the input is a legal type, and SINT_TO_FP is not legal on this target, 4122 // but UINT_TO_FP is legal on this target, try to convert. 4123 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) && 4124 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) { 4125 // If the sign bit is known to be zero, we can change this to UINT_TO_FP. 4126 if (DAG.SignBitIsZero(N0)) 4127 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 4128 } 4129 4130 return SDValue(); 4131} 4132 4133SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) { 4134 SDValue N0 = N->getOperand(0); 4135 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 4136 MVT VT = N->getValueType(0); 4137 MVT OpVT = N0.getValueType(); 4138 4139 // fold (uint_to_fp c1) -> c1fp 4140 if (N0C && OpVT != MVT::ppcf128) 4141 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 4142 4143 // If the input is a legal type, and UINT_TO_FP is not legal on this target, 4144 // but SINT_TO_FP is legal on this target, try to convert. 4145 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) && 4146 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) { 4147 // If the sign bit is known to be zero, we can change this to SINT_TO_FP. 4148 if (DAG.SignBitIsZero(N0)) 4149 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 4150 } 4151 4152 return SDValue(); 4153} 4154 4155SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) { 4156 SDValue N0 = N->getOperand(0); 4157 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4158 MVT VT = N->getValueType(0); 4159 4160 // fold (fp_to_sint c1fp) -> c1 4161 if (N0CFP) 4162 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0); 4163 4164 return SDValue(); 4165} 4166 4167SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) { 4168 SDValue N0 = N->getOperand(0); 4169 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4170 MVT VT = N->getValueType(0); 4171 4172 // fold (fp_to_uint c1fp) -> c1 4173 if (N0CFP && VT != MVT::ppcf128) 4174 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0); 4175 4176 return SDValue(); 4177} 4178 4179SDValue DAGCombiner::visitFP_ROUND(SDNode *N) { 4180 SDValue N0 = N->getOperand(0); 4181 SDValue N1 = N->getOperand(1); 4182 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4183 MVT VT = N->getValueType(0); 4184 4185 // fold (fp_round c1fp) -> c1fp 4186 if (N0CFP && N0.getValueType() != MVT::ppcf128) 4187 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1); 4188 4189 // fold (fp_round (fp_extend x)) -> x 4190 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 4191 return N0.getOperand(0); 4192 4193 // fold (fp_round (fp_round x)) -> (fp_round x) 4194 if (N0.getOpcode() == ISD::FP_ROUND) { 4195 // This is a value preserving truncation if both round's are. 4196 bool IsTrunc = N->getConstantOperandVal(1) == 1 && 4197 N0.getNode()->getConstantOperandVal(1) == 1; 4198 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0), 4199 DAG.getIntPtrConstant(IsTrunc)); 4200 } 4201 4202 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 4203 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) { 4204 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT, 4205 N0.getOperand(0), N1); 4206 AddToWorkList(Tmp.getNode()); 4207 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4208 Tmp, N0.getOperand(1)); 4209 } 4210 4211 return SDValue(); 4212} 4213 4214SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 4215 SDValue N0 = N->getOperand(0); 4216 MVT VT = N->getValueType(0); 4217 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 4218 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4219 4220 // fold (fp_round_inreg c1fp) -> c1fp 4221 if (N0CFP && (TLI.isTypeLegal(EVT) || !LegalTypes)) { 4222 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT); 4223 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round); 4224 } 4225 4226 return SDValue(); 4227} 4228 4229SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) { 4230 SDValue N0 = N->getOperand(0); 4231 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4232 MVT VT = N->getValueType(0); 4233 4234 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. 4235 if (N->hasOneUse() && 4236 N->use_begin()->getOpcode() == ISD::FP_ROUND) 4237 return SDValue(); 4238 4239 // fold (fp_extend c1fp) -> c1fp 4240 if (N0CFP && VT != MVT::ppcf128) 4241 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0); 4242 4243 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the 4244 // value of X. 4245 if (N0.getOpcode() == ISD::FP_ROUND 4246 && N0.getNode()->getConstantOperandVal(1) == 1) { 4247 SDValue In = N0.getOperand(0); 4248 if (In.getValueType() == VT) return In; 4249 if (VT.bitsLT(In.getValueType())) 4250 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, 4251 In, N0.getOperand(1)); 4252 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In); 4253 } 4254 4255 // fold (fpext (load x)) -> (fpext (fptrunc (extload x))) 4256 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 4257 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4258 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 4259 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4260 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 4261 LN0->getChain(), 4262 LN0->getBasePtr(), LN0->getSrcValue(), 4263 LN0->getSrcValueOffset(), 4264 N0.getValueType(), 4265 LN0->isVolatile(), LN0->getAlignment()); 4266 CombineTo(N, ExtLoad); 4267 CombineTo(N0.getNode(), 4268 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), 4269 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)), 4270 ExtLoad.getValue(1)); 4271 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4272 } 4273 4274 return SDValue(); 4275} 4276 4277SDValue DAGCombiner::visitFNEG(SDNode *N) { 4278 SDValue N0 = N->getOperand(0); 4279 4280 if (isNegatibleForFree(N0, LegalOperations)) 4281 return GetNegatedExpression(N0, DAG, LegalOperations); 4282 4283 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading 4284 // constant pool values. 4285 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() && 4286 N0.getOperand(0).getValueType().isInteger() && 4287 !N0.getOperand(0).getValueType().isVector()) { 4288 SDValue Int = N0.getOperand(0); 4289 MVT IntVT = Int.getValueType(); 4290 if (IntVT.isInteger() && !IntVT.isVector()) { 4291 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int, 4292 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 4293 AddToWorkList(Int.getNode()); 4294 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), 4295 N->getValueType(0), Int); 4296 } 4297 } 4298 4299 return SDValue(); 4300} 4301 4302SDValue DAGCombiner::visitFABS(SDNode *N) { 4303 SDValue N0 = N->getOperand(0); 4304 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4305 MVT VT = N->getValueType(0); 4306 4307 // fold (fabs c1) -> fabs(c1) 4308 if (N0CFP && VT != MVT::ppcf128) 4309 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 4310 // fold (fabs (fabs x)) -> (fabs x) 4311 if (N0.getOpcode() == ISD::FABS) 4312 return N->getOperand(0); 4313 // fold (fabs (fneg x)) -> (fabs x) 4314 // fold (fabs (fcopysign x, y)) -> (fabs x) 4315 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 4316 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0)); 4317 4318 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading 4319 // constant pool values. 4320 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() && 4321 N0.getOperand(0).getValueType().isInteger() && 4322 !N0.getOperand(0).getValueType().isVector()) { 4323 SDValue Int = N0.getOperand(0); 4324 MVT IntVT = Int.getValueType(); 4325 if (IntVT.isInteger() && !IntVT.isVector()) { 4326 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int, 4327 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 4328 AddToWorkList(Int.getNode()); 4329 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), 4330 N->getValueType(0), Int); 4331 } 4332 } 4333 4334 return SDValue(); 4335} 4336 4337SDValue DAGCombiner::visitBRCOND(SDNode *N) { 4338 SDValue Chain = N->getOperand(0); 4339 SDValue N1 = N->getOperand(1); 4340 SDValue N2 = N->getOperand(2); 4341 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 4342 4343 // never taken branch, fold to chain 4344 if (N1C && N1C->isNullValue()) 4345 return Chain; 4346 // unconditional branch 4347 if (N1C && N1C->getAPIntValue() == 1) 4348 return DAG.getNode(ISD::BR, N->getDebugLoc(), MVT::Other, Chain, N2); 4349 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 4350 // on the target. 4351 if (N1.getOpcode() == ISD::SETCC && 4352 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) { 4353 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 4354 Chain, N1.getOperand(2), 4355 N1.getOperand(0), N1.getOperand(1), N2); 4356 } 4357 4358 return SDValue(); 4359} 4360 4361// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 4362// 4363SDValue DAGCombiner::visitBR_CC(SDNode *N) { 4364 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 4365 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 4366 4367 // Use SimplifySetCC to simplify SETCC's. 4368 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()), 4369 CondLHS, CondRHS, CC->get(), N->getDebugLoc(), 4370 false); 4371 if (Simp.getNode()) AddToWorkList(Simp.getNode()); 4372 4373 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.getNode()); 4374 4375 // fold br_cc true, dest -> br dest (unconditional branch) 4376 if (SCCC && !SCCC->isNullValue()) 4377 return DAG.getNode(ISD::BR, N->getDebugLoc(), MVT::Other, 4378 N->getOperand(0), N->getOperand(4)); 4379 // fold br_cc false, dest -> unconditional fall through 4380 if (SCCC && SCCC->isNullValue()) 4381 return N->getOperand(0); 4382 4383 // fold to a simpler setcc 4384 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC) 4385 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 4386 N->getOperand(0), Simp.getOperand(2), 4387 Simp.getOperand(0), Simp.getOperand(1), 4388 N->getOperand(4)); 4389 4390 return SDValue(); 4391} 4392 4393/// CombineToPreIndexedLoadStore - Try turning a load / store into a 4394/// pre-indexed load / store when the base pointer is an add or subtract 4395/// and it has other uses besides the load / store. After the 4396/// transformation, the new indexed load / store has effectively folded 4397/// the add / subtract in and all of its other uses are redirected to the 4398/// new load / store. 4399bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 4400 if (!LegalOperations) 4401 return false; 4402 4403 bool isLoad = true; 4404 SDValue Ptr; 4405 MVT VT; 4406 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4407 if (LD->isIndexed()) 4408 return false; 4409 VT = LD->getMemoryVT(); 4410 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 4411 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 4412 return false; 4413 Ptr = LD->getBasePtr(); 4414 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4415 if (ST->isIndexed()) 4416 return false; 4417 VT = ST->getMemoryVT(); 4418 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 4419 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 4420 return false; 4421 Ptr = ST->getBasePtr(); 4422 isLoad = false; 4423 } else { 4424 return false; 4425 } 4426 4427 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 4428 // out. There is no reason to make this a preinc/predec. 4429 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 4430 Ptr.getNode()->hasOneUse()) 4431 return false; 4432 4433 // Ask the target to do addressing mode selection. 4434 SDValue BasePtr; 4435 SDValue Offset; 4436 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4437 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 4438 return false; 4439 // Don't create a indexed load / store with zero offset. 4440 if (isa<ConstantSDNode>(Offset) && 4441 cast<ConstantSDNode>(Offset)->isNullValue()) 4442 return false; 4443 4444 // Try turning it into a pre-indexed load / store except when: 4445 // 1) The new base ptr is a frame index. 4446 // 2) If N is a store and the new base ptr is either the same as or is a 4447 // predecessor of the value being stored. 4448 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 4449 // that would create a cycle. 4450 // 4) All uses are load / store ops that use it as old base ptr. 4451 4452 // Check #1. Preinc'ing a frame index would require copying the stack pointer 4453 // (plus the implicit offset) to a register to preinc anyway. 4454 if (isa<FrameIndexSDNode>(BasePtr)) 4455 return false; 4456 4457 // Check #2. 4458 if (!isLoad) { 4459 SDValue Val = cast<StoreSDNode>(N)->getValue(); 4460 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode())) 4461 return false; 4462 } 4463 4464 // Now check for #3 and #4. 4465 bool RealUse = false; 4466 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 4467 E = Ptr.getNode()->use_end(); I != E; ++I) { 4468 SDNode *Use = *I; 4469 if (Use == N) 4470 continue; 4471 if (Use->isPredecessorOf(N)) 4472 return false; 4473 4474 if (!((Use->getOpcode() == ISD::LOAD && 4475 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) || 4476 (Use->getOpcode() == ISD::STORE && 4477 cast<StoreSDNode>(Use)->getBasePtr() == Ptr))) 4478 RealUse = true; 4479 } 4480 4481 if (!RealUse) 4482 return false; 4483 4484 SDValue Result; 4485 if (isLoad) 4486 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 4487 BasePtr, Offset, AM); 4488 else 4489 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 4490 BasePtr, Offset, AM); 4491 ++PreIndexedNodes; 4492 ++NodesCombined; 4493 DOUT << "\nReplacing.4 "; DEBUG(N->dump(&DAG)); 4494 DOUT << "\nWith: "; DEBUG(Result.getNode()->dump(&DAG)); 4495 DOUT << '\n'; 4496 WorkListRemover DeadNodes(*this); 4497 if (isLoad) { 4498 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 4499 &DeadNodes); 4500 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 4501 &DeadNodes); 4502 } else { 4503 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 4504 &DeadNodes); 4505 } 4506 4507 // Finally, since the node is now dead, remove it from the graph. 4508 DAG.DeleteNode(N); 4509 4510 // Replace the uses of Ptr with uses of the updated base value. 4511 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 4512 &DeadNodes); 4513 removeFromWorkList(Ptr.getNode()); 4514 DAG.DeleteNode(Ptr.getNode()); 4515 4516 return true; 4517} 4518 4519/// CombineToPostIndexedLoadStore - Try to combine a load / store with a 4520/// add / sub of the base pointer node into a post-indexed load / store. 4521/// The transformation folded the add / subtract into the new indexed 4522/// load / store effectively and all of its uses are redirected to the 4523/// new load / store. 4524bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 4525 if (!LegalOperations) 4526 return false; 4527 4528 bool isLoad = true; 4529 SDValue Ptr; 4530 MVT VT; 4531 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4532 if (LD->isIndexed()) 4533 return false; 4534 VT = LD->getMemoryVT(); 4535 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 4536 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 4537 return false; 4538 Ptr = LD->getBasePtr(); 4539 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4540 if (ST->isIndexed()) 4541 return false; 4542 VT = ST->getMemoryVT(); 4543 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 4544 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 4545 return false; 4546 Ptr = ST->getBasePtr(); 4547 isLoad = false; 4548 } else { 4549 return false; 4550 } 4551 4552 if (Ptr.getNode()->hasOneUse()) 4553 return false; 4554 4555 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 4556 E = Ptr.getNode()->use_end(); I != E; ++I) { 4557 SDNode *Op = *I; 4558 if (Op == N || 4559 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 4560 continue; 4561 4562 SDValue BasePtr; 4563 SDValue Offset; 4564 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4565 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 4566 if (Ptr == Offset) 4567 std::swap(BasePtr, Offset); 4568 if (Ptr != BasePtr) 4569 continue; 4570 // Don't create a indexed load / store with zero offset. 4571 if (isa<ConstantSDNode>(Offset) && 4572 cast<ConstantSDNode>(Offset)->isNullValue()) 4573 continue; 4574 4575 // Try turning it into a post-indexed load / store except when 4576 // 1) All uses are load / store ops that use it as base ptr. 4577 // 2) Op must be independent of N, i.e. Op is neither a predecessor 4578 // nor a successor of N. Otherwise, if Op is folded that would 4579 // create a cycle. 4580 4581 // Check for #1. 4582 bool TryNext = false; 4583 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(), 4584 EE = BasePtr.getNode()->use_end(); II != EE; ++II) { 4585 SDNode *Use = *II; 4586 if (Use == Ptr.getNode()) 4587 continue; 4588 4589 // If all the uses are load / store addresses, then don't do the 4590 // transformation. 4591 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 4592 bool RealUse = false; 4593 for (SDNode::use_iterator III = Use->use_begin(), 4594 EEE = Use->use_end(); III != EEE; ++III) { 4595 SDNode *UseUse = *III; 4596 if (!((UseUse->getOpcode() == ISD::LOAD && 4597 cast<LoadSDNode>(UseUse)->getBasePtr().getNode() == Use) || 4598 (UseUse->getOpcode() == ISD::STORE && 4599 cast<StoreSDNode>(UseUse)->getBasePtr().getNode() == Use))) 4600 RealUse = true; 4601 } 4602 4603 if (!RealUse) { 4604 TryNext = true; 4605 break; 4606 } 4607 } 4608 } 4609 4610 if (TryNext) 4611 continue; 4612 4613 // Check for #2 4614 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) { 4615 SDValue Result = isLoad 4616 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 4617 BasePtr, Offset, AM) 4618 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 4619 BasePtr, Offset, AM); 4620 ++PostIndexedNodes; 4621 ++NodesCombined; 4622 DOUT << "\nReplacing.5 "; DEBUG(N->dump(&DAG)); 4623 DOUT << "\nWith: "; DEBUG(Result.getNode()->dump(&DAG)); 4624 DOUT << '\n'; 4625 WorkListRemover DeadNodes(*this); 4626 if (isLoad) { 4627 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 4628 &DeadNodes); 4629 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 4630 &DeadNodes); 4631 } else { 4632 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 4633 &DeadNodes); 4634 } 4635 4636 // Finally, since the node is now dead, remove it from the graph. 4637 DAG.DeleteNode(N); 4638 4639 // Replace the uses of Use with uses of the updated base value. 4640 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0), 4641 Result.getValue(isLoad ? 1 : 0), 4642 &DeadNodes); 4643 removeFromWorkList(Op); 4644 DAG.DeleteNode(Op); 4645 return true; 4646 } 4647 } 4648 } 4649 4650 return false; 4651} 4652 4653/// InferAlignment - If we can infer some alignment information from this 4654/// pointer, return it. 4655static unsigned InferAlignment(SDValue Ptr, SelectionDAG &DAG) { 4656 // If this is a direct reference to a stack slot, use information about the 4657 // stack slot's alignment. 4658 int FrameIdx = 1 << 31; 4659 int64_t FrameOffset = 0; 4660 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Ptr)) { 4661 FrameIdx = FI->getIndex(); 4662 } else if (Ptr.getOpcode() == ISD::ADD && 4663 isa<ConstantSDNode>(Ptr.getOperand(1)) && 4664 isa<FrameIndexSDNode>(Ptr.getOperand(0))) { 4665 FrameIdx = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex(); 4666 FrameOffset = Ptr.getConstantOperandVal(1); 4667 } 4668 4669 if (FrameIdx != (1 << 31)) { 4670 // FIXME: Handle FI+CST. 4671 const MachineFrameInfo &MFI = *DAG.getMachineFunction().getFrameInfo(); 4672 if (MFI.isFixedObjectIndex(FrameIdx)) { 4673 int64_t ObjectOffset = MFI.getObjectOffset(FrameIdx) + FrameOffset; 4674 4675 // The alignment of the frame index can be determined from its offset from 4676 // the incoming frame position. If the frame object is at offset 32 and 4677 // the stack is guaranteed to be 16-byte aligned, then we know that the 4678 // object is 16-byte aligned. 4679 unsigned StackAlign = DAG.getTarget().getFrameInfo()->getStackAlignment(); 4680 unsigned Align = MinAlign(ObjectOffset, StackAlign); 4681 4682 // Finally, the frame object itself may have a known alignment. Factor 4683 // the alignment + offset into a new alignment. For example, if we know 4684 // the FI is 8 byte aligned, but the pointer is 4 off, we really have a 4685 // 4-byte alignment of the resultant pointer. Likewise align 4 + 4-byte 4686 // offset = 4-byte alignment, align 4 + 1-byte offset = align 1, etc. 4687 unsigned FIInfoAlign = MinAlign(MFI.getObjectAlignment(FrameIdx), 4688 FrameOffset); 4689 return std::max(Align, FIInfoAlign); 4690 } 4691 } 4692 4693 return 0; 4694} 4695 4696SDValue DAGCombiner::visitLOAD(SDNode *N) { 4697 LoadSDNode *LD = cast<LoadSDNode>(N); 4698 SDValue Chain = LD->getChain(); 4699 SDValue Ptr = LD->getBasePtr(); 4700 4701 // Try to infer better alignment information than the load already has. 4702 if (!Fast && LD->isUnindexed()) { 4703 if (unsigned Align = InferAlignment(Ptr, DAG)) { 4704 if (Align > LD->getAlignment()) 4705 return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(), 4706 LD->getValueType(0), 4707 Chain, Ptr, LD->getSrcValue(), 4708 LD->getSrcValueOffset(), LD->getMemoryVT(), 4709 LD->isVolatile(), Align); 4710 } 4711 } 4712 4713 // If load is not volatile and there are no uses of the loaded value (and 4714 // the updated indexed value in case of indexed loads), change uses of the 4715 // chain value into uses of the chain input (i.e. delete the dead load). 4716 if (!LD->isVolatile()) { 4717 if (N->getValueType(1) == MVT::Other) { 4718 // Unindexed loads. 4719 if (N->hasNUsesOfValue(0, 0)) { 4720 // It's not safe to use the two value CombineTo variant here. e.g. 4721 // v1, chain2 = load chain1, loc 4722 // v2, chain3 = load chain2, loc 4723 // v3 = add v2, c 4724 // Now we replace use of chain2 with chain1. This makes the second load 4725 // isomorphic to the one we are deleting, and thus makes this load live. 4726 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG)); 4727 DOUT << "\nWith chain: "; DEBUG(Chain.getNode()->dump(&DAG)); 4728 DOUT << "\n"; 4729 WorkListRemover DeadNodes(*this); 4730 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes); 4731 4732 if (N->use_empty()) { 4733 removeFromWorkList(N); 4734 DAG.DeleteNode(N); 4735 } 4736 4737 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4738 } 4739 } else { 4740 // Indexed loads. 4741 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 4742 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) { 4743 SDValue Undef = DAG.getUNDEF(N->getValueType(0)); 4744 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG)); 4745 DOUT << "\nWith: "; DEBUG(Undef.getNode()->dump(&DAG)); 4746 DOUT << " and 2 other values\n"; 4747 WorkListRemover DeadNodes(*this); 4748 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes); 4749 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), 4750 DAG.getUNDEF(N->getValueType(1)), 4751 &DeadNodes); 4752 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes); 4753 removeFromWorkList(N); 4754 DAG.DeleteNode(N); 4755 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4756 } 4757 } 4758 } 4759 4760 // If this load is directly stored, replace the load value with the stored 4761 // value. 4762 // TODO: Handle store large -> read small portion. 4763 // TODO: Handle TRUNCSTORE/LOADEXT 4764 if (LD->getExtensionType() == ISD::NON_EXTLOAD && 4765 !LD->isVolatile()) { 4766 if (ISD::isNON_TRUNCStore(Chain.getNode())) { 4767 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 4768 if (PrevST->getBasePtr() == Ptr && 4769 PrevST->getValue().getValueType() == N->getValueType(0)) 4770 return CombineTo(N, Chain.getOperand(1), Chain); 4771 } 4772 } 4773 4774 if (CombinerAA) { 4775 // Walk up chain skipping non-aliasing memory nodes. 4776 SDValue BetterChain = FindBetterChain(N, Chain); 4777 4778 // If there is a better chain. 4779 if (Chain != BetterChain) { 4780 SDValue ReplLoad; 4781 4782 // Replace the chain to void dependency. 4783 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 4784 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(), 4785 BetterChain, Ptr, 4786 LD->getSrcValue(), LD->getSrcValueOffset(), 4787 LD->isVolatile(), LD->getAlignment()); 4788 } else { 4789 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(), 4790 LD->getValueType(0), 4791 BetterChain, Ptr, LD->getSrcValue(), 4792 LD->getSrcValueOffset(), 4793 LD->getMemoryVT(), 4794 LD->isVolatile(), 4795 LD->getAlignment()); 4796 } 4797 4798 // Create token factor to keep old chain connected. 4799 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 4800 MVT::Other, Chain, ReplLoad.getValue(1)); 4801 4802 // Replace uses with load result and token factor. Don't add users 4803 // to work list. 4804 return CombineTo(N, ReplLoad.getValue(0), Token, false); 4805 } 4806 } 4807 4808 // Try transforming N to an indexed load. 4809 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 4810 return SDValue(N, 0); 4811 4812 return SDValue(); 4813} 4814 4815SDValue DAGCombiner::visitSTORE(SDNode *N) { 4816 StoreSDNode *ST = cast<StoreSDNode>(N); 4817 SDValue Chain = ST->getChain(); 4818 SDValue Value = ST->getValue(); 4819 SDValue Ptr = ST->getBasePtr(); 4820 4821 // Try to infer better alignment information than the store already has. 4822 if (!Fast && ST->isUnindexed()) { 4823 if (unsigned Align = InferAlignment(Ptr, DAG)) { 4824 if (Align > ST->getAlignment()) 4825 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value, 4826 Ptr, ST->getSrcValue(), 4827 ST->getSrcValueOffset(), ST->getMemoryVT(), 4828 ST->isVolatile(), Align); 4829 } 4830 } 4831 4832 // If this is a store of a bit convert, store the input value if the 4833 // resultant store does not need a higher alignment than the original. 4834 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() && 4835 ST->isUnindexed()) { 4836 unsigned OrigAlign = ST->getAlignment(); 4837 MVT SVT = Value.getOperand(0).getValueType(); 4838 unsigned Align = TLI.getTargetData()-> 4839 getABITypeAlignment(SVT.getTypeForMVT()); 4840 if (Align <= OrigAlign && 4841 ((!LegalOperations && !ST->isVolatile()) || 4842 TLI.isOperationLegalOrCustom(ISD::STORE, SVT))) 4843 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0), 4844 Ptr, ST->getSrcValue(), 4845 ST->getSrcValueOffset(), ST->isVolatile(), OrigAlign); 4846 } 4847 4848 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 4849 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 4850 // NOTE: If the original store is volatile, this transform must not increase 4851 // the number of stores. For example, on x86-32 an f64 can be stored in one 4852 // processor operation but an i64 (which is not legal) requires two. So the 4853 // transform should not be done in this case. 4854 if (Value.getOpcode() != ISD::TargetConstantFP) { 4855 SDValue Tmp; 4856 switch (CFP->getValueType(0).getSimpleVT()) { 4857 default: assert(0 && "Unknown FP type"); 4858 case MVT::f80: // We don't do this for these yet. 4859 case MVT::f128: 4860 case MVT::ppcf128: 4861 break; 4862 case MVT::f32: 4863 if (((TLI.isTypeLegal(MVT::i32) || !LegalTypes) && !LegalOperations && 4864 !ST->isVolatile()) || 4865 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 4866 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 4867 bitcastToAPInt().getZExtValue(), MVT::i32); 4868 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 4869 Ptr, ST->getSrcValue(), 4870 ST->getSrcValueOffset(), ST->isVolatile(), 4871 ST->getAlignment()); 4872 } 4873 break; 4874 case MVT::f64: 4875 if (((TLI.isTypeLegal(MVT::i64) || !LegalTypes) && !LegalOperations && 4876 !ST->isVolatile()) || 4877 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) { 4878 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 4879 getZExtValue(), MVT::i64); 4880 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 4881 Ptr, ST->getSrcValue(), 4882 ST->getSrcValueOffset(), ST->isVolatile(), 4883 ST->getAlignment()); 4884 } else if (!ST->isVolatile() && 4885 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 4886 // Many FP stores are not made apparent until after legalize, e.g. for 4887 // argument passing. Since this is so common, custom legalize the 4888 // 64-bit integer store into two 32-bit stores. 4889 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue(); 4890 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 4891 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32); 4892 if (TLI.isBigEndian()) std::swap(Lo, Hi); 4893 4894 int SVOffset = ST->getSrcValueOffset(); 4895 unsigned Alignment = ST->getAlignment(); 4896 bool isVolatile = ST->isVolatile(); 4897 4898 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo, 4899 Ptr, ST->getSrcValue(), 4900 ST->getSrcValueOffset(), 4901 isVolatile, ST->getAlignment()); 4902 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr, 4903 DAG.getConstant(4, Ptr.getValueType())); 4904 SVOffset += 4; 4905 Alignment = MinAlign(Alignment, 4U); 4906 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi, 4907 Ptr, ST->getSrcValue(), 4908 SVOffset, isVolatile, Alignment); 4909 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 4910 St0, St1); 4911 } 4912 4913 break; 4914 } 4915 } 4916 } 4917 4918 if (CombinerAA) { 4919 // Walk up chain skipping non-aliasing memory nodes. 4920 SDValue BetterChain = FindBetterChain(N, Chain); 4921 4922 // If there is a better chain. 4923 if (Chain != BetterChain) { 4924 // Replace the chain to avoid dependency. 4925 SDValue ReplStore; 4926 if (ST->isTruncatingStore()) { 4927 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr, 4928 ST->getSrcValue(),ST->getSrcValueOffset(), 4929 ST->getMemoryVT(), 4930 ST->isVolatile(), ST->getAlignment()); 4931 } else { 4932 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr, 4933 ST->getSrcValue(), ST->getSrcValueOffset(), 4934 ST->isVolatile(), ST->getAlignment()); 4935 } 4936 4937 // Create token to keep both nodes around. 4938 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 4939 MVT::Other, Chain, ReplStore); 4940 4941 // Don't add users to work list. 4942 return CombineTo(N, Token, false); 4943 } 4944 } 4945 4946 // Try transforming N to an indexed store. 4947 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 4948 return SDValue(N, 0); 4949 4950 // FIXME: is there such a thing as a truncating indexed store? 4951 if (ST->isTruncatingStore() && ST->isUnindexed() && 4952 Value.getValueType().isInteger()) { 4953 // See if we can simplify the input to this truncstore with knowledge that 4954 // only the low bits are being used. For example: 4955 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 4956 SDValue Shorter = 4957 GetDemandedBits(Value, 4958 APInt::getLowBitsSet(Value.getValueSizeInBits(), 4959 ST->getMemoryVT().getSizeInBits())); 4960 AddToWorkList(Value.getNode()); 4961 if (Shorter.getNode()) 4962 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter, 4963 Ptr, ST->getSrcValue(), 4964 ST->getSrcValueOffset(), ST->getMemoryVT(), 4965 ST->isVolatile(), ST->getAlignment()); 4966 4967 // Otherwise, see if we can simplify the operation with 4968 // SimplifyDemandedBits, which only works if the value has a single use. 4969 if (SimplifyDemandedBits(Value, 4970 APInt::getLowBitsSet( 4971 Value.getValueSizeInBits(), 4972 ST->getMemoryVT().getSizeInBits()))) 4973 return SDValue(N, 0); 4974 } 4975 4976 // If this is a load followed by a store to the same location, then the store 4977 // is dead/noop. 4978 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) { 4979 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() && 4980 ST->isUnindexed() && !ST->isVolatile() && 4981 // There can't be any side effects between the load and store, such as 4982 // a call or store. 4983 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) { 4984 // The store is dead, remove it. 4985 return Chain; 4986 } 4987 } 4988 4989 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a 4990 // truncating store. We can do this even if this is already a truncstore. 4991 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) 4992 && Value.getNode()->hasOneUse() && ST->isUnindexed() && 4993 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(), 4994 ST->getMemoryVT())) { 4995 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0), 4996 Ptr, ST->getSrcValue(), 4997 ST->getSrcValueOffset(), ST->getMemoryVT(), 4998 ST->isVolatile(), ST->getAlignment()); 4999 } 5000 5001 return SDValue(); 5002} 5003 5004SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 5005 SDValue InVec = N->getOperand(0); 5006 SDValue InVal = N->getOperand(1); 5007 SDValue EltNo = N->getOperand(2); 5008 5009 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 5010 // vector with the inserted element. 5011 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 5012 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5013 SmallVector<SDValue, 8> Ops(InVec.getNode()->op_begin(), 5014 InVec.getNode()->op_end()); 5015 if (Elt < Ops.size()) 5016 Ops[Elt] = InVal; 5017 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 5018 InVec.getValueType(), &Ops[0], Ops.size()); 5019 } 5020 5021 return SDValue(); 5022} 5023 5024SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 5025 // (vextract (scalar_to_vector val, 0) -> val 5026 SDValue InVec = N->getOperand(0); 5027 5028 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) 5029 return InVec.getOperand(0); 5030 5031 // Perform only after legalization to ensure build_vector / vector_shuffle 5032 // optimizations have already been done. 5033 if (!LegalOperations) return SDValue(); 5034 5035 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size) 5036 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size) 5037 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr) 5038 SDValue EltNo = N->getOperand(1); 5039 5040 if (isa<ConstantSDNode>(EltNo)) { 5041 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5042 bool NewLoad = false; 5043 bool BCNumEltsChanged = false; 5044 MVT VT = InVec.getValueType(); 5045 MVT EVT = VT.getVectorElementType(); 5046 MVT LVT = EVT; 5047 5048 if (InVec.getOpcode() == ISD::BIT_CONVERT) { 5049 MVT BCVT = InVec.getOperand(0).getValueType(); 5050 if (!BCVT.isVector() || EVT.bitsGT(BCVT.getVectorElementType())) 5051 return SDValue(); 5052 if (VT.getVectorNumElements() != BCVT.getVectorNumElements()) 5053 BCNumEltsChanged = true; 5054 InVec = InVec.getOperand(0); 5055 EVT = BCVT.getVectorElementType(); 5056 NewLoad = true; 5057 } 5058 5059 LoadSDNode *LN0 = NULL; 5060 if (ISD::isNormalLoad(InVec.getNode())) { 5061 LN0 = cast<LoadSDNode>(InVec); 5062 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 5063 InVec.getOperand(0).getValueType() == EVT && 5064 ISD::isNormalLoad(InVec.getOperand(0).getNode())) { 5065 LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 5066 } else if (InVec.getOpcode() == ISD::VECTOR_SHUFFLE) { 5067 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1) 5068 // => 5069 // (load $addr+1*size) 5070 5071 // If the bit convert changed the number of elements, it is unsafe 5072 // to examine the mask. 5073 if (BCNumEltsChanged) 5074 return SDValue(); 5075 unsigned Idx = cast<ConstantSDNode>(InVec.getOperand(2). 5076 getOperand(Elt))->getZExtValue(); 5077 unsigned NumElems = InVec.getOperand(2).getNumOperands(); 5078 InVec = (Idx < NumElems) ? InVec.getOperand(0) : InVec.getOperand(1); 5079 if (InVec.getOpcode() == ISD::BIT_CONVERT) 5080 InVec = InVec.getOperand(0); 5081 if (ISD::isNormalLoad(InVec.getNode())) { 5082 LN0 = cast<LoadSDNode>(InVec); 5083 Elt = (Idx < NumElems) ? Idx : Idx - NumElems; 5084 } 5085 } 5086 5087 if (!LN0 || !LN0->hasOneUse() || LN0->isVolatile()) 5088 return SDValue(); 5089 5090 unsigned Align = LN0->getAlignment(); 5091 if (NewLoad) { 5092 // Check the resultant load doesn't need a higher alignment than the 5093 // original load. 5094 unsigned NewAlign = 5095 TLI.getTargetData()->getABITypeAlignment(LVT.getTypeForMVT()); 5096 5097 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT)) 5098 return SDValue(); 5099 5100 Align = NewAlign; 5101 } 5102 5103 SDValue NewPtr = LN0->getBasePtr(); 5104 if (Elt) { 5105 unsigned PtrOff = LVT.getSizeInBits() * Elt / 8; 5106 MVT PtrType = NewPtr.getValueType(); 5107 if (TLI.isBigEndian()) 5108 PtrOff = VT.getSizeInBits() / 8 - PtrOff; 5109 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr, 5110 DAG.getConstant(PtrOff, PtrType)); 5111 } 5112 5113 return DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr, 5114 LN0->getSrcValue(), LN0->getSrcValueOffset(), 5115 LN0->isVolatile(), Align); 5116 } 5117 5118 return SDValue(); 5119} 5120 5121SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 5122 unsigned NumInScalars = N->getNumOperands(); 5123 MVT VT = N->getValueType(0); 5124 unsigned NumElts = VT.getVectorNumElements(); 5125 MVT EltType = VT.getVectorElementType(); 5126 5127 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 5128 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 5129 // at most two distinct vectors, turn this into a shuffle node. 5130 SDValue VecIn1, VecIn2; 5131 for (unsigned i = 0; i != NumInScalars; ++i) { 5132 // Ignore undef inputs. 5133 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 5134 5135 // If this input is something other than a EXTRACT_VECTOR_ELT with a 5136 // constant index, bail out. 5137 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 5138 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 5139 VecIn1 = VecIn2 = SDValue(0, 0); 5140 break; 5141 } 5142 5143 // If the input vector type disagrees with the result of the build_vector, 5144 // we can't make a shuffle. 5145 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0); 5146 if (ExtractedFromVec.getValueType() != VT) { 5147 VecIn1 = VecIn2 = SDValue(0, 0); 5148 break; 5149 } 5150 5151 // Otherwise, remember this. We allow up to two distinct input vectors. 5152 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 5153 continue; 5154 5155 if (VecIn1.getNode() == 0) { 5156 VecIn1 = ExtractedFromVec; 5157 } else if (VecIn2.getNode() == 0) { 5158 VecIn2 = ExtractedFromVec; 5159 } else { 5160 // Too many inputs. 5161 VecIn1 = VecIn2 = SDValue(0, 0); 5162 break; 5163 } 5164 } 5165 5166 // If everything is good, we can make a shuffle operation. 5167 if (VecIn1.getNode()) { 5168 SmallVector<SDValue, 8> BuildVecIndices; 5169 for (unsigned i = 0; i != NumInScalars; ++i) { 5170 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 5171 BuildVecIndices.push_back(DAG.getUNDEF(TLI.getPointerTy())); 5172 continue; 5173 } 5174 5175 SDValue Extract = N->getOperand(i); 5176 5177 // If extracting from the first vector, just use the index directly. 5178 if (Extract.getOperand(0) == VecIn1) { 5179 BuildVecIndices.push_back(Extract.getOperand(1)); 5180 continue; 5181 } 5182 5183 // Otherwise, use InIdx + VecSize 5184 unsigned Idx = 5185 cast<ConstantSDNode>(Extract.getOperand(1))->getZExtValue(); 5186 BuildVecIndices.push_back(DAG.getIntPtrConstant(Idx+NumInScalars)); 5187 } 5188 5189 // Add count and size info. 5190 MVT IndexVT = MVT::getIntegerVT(EltType.getSizeInBits()); 5191 MVT BuildVecVT = MVT::getVectorVT(IndexVT, NumElts); 5192 if (!TLI.isTypeLegal(BuildVecVT) && LegalTypes) 5193 return SDValue(); 5194 5195 // Return the new VECTOR_SHUFFLE node. 5196 SDValue Ops[5]; 5197 Ops[0] = VecIn1; 5198 if (VecIn2.getNode()) { 5199 Ops[1] = VecIn2; 5200 } else { 5201 // Use an undef build_vector as input for the second operand. 5202 std::vector<SDValue> UnOps(NumInScalars, 5203 DAG.getUNDEF(EltType)); 5204 Ops[1] = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 5205 &UnOps[0], UnOps.size()); 5206 AddToWorkList(Ops[1].getNode()); 5207 } 5208 5209 Ops[2] = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), BuildVecVT, 5210 &BuildVecIndices[0], BuildVecIndices.size()); 5211 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getDebugLoc(), VT, Ops, 3); 5212 } 5213 5214 return SDValue(); 5215} 5216 5217SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 5218 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 5219 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 5220 // inputs come from at most two distinct vectors, turn this into a shuffle 5221 // node. 5222 5223 // If we only have one input vector, we don't need to do any concatenation. 5224 if (N->getNumOperands() == 1) 5225 return N->getOperand(0); 5226 5227 return SDValue(); 5228} 5229 5230SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 5231 SDValue ShufMask = N->getOperand(2); 5232 unsigned NumElts = ShufMask.getNumOperands(); 5233 5234 SDValue N0 = N->getOperand(0); 5235 SDValue N1 = N->getOperand(1); 5236 5237 assert(N0.getValueType().getVectorNumElements() == NumElts && 5238 "Vector shuffle must be normalized in DAG"); 5239 5240 // If the shuffle mask is an identity operation on the LHS, return the LHS. 5241 bool isIdentity = true; 5242 for (unsigned i = 0; i != NumElts; ++i) { 5243 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 5244 cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() != i) { 5245 isIdentity = false; 5246 break; 5247 } 5248 } 5249 if (isIdentity) return N->getOperand(0); 5250 5251 // If the shuffle mask is an identity operation on the RHS, return the RHS. 5252 isIdentity = true; 5253 for (unsigned i = 0; i != NumElts; ++i) { 5254 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 5255 cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() != 5256 i+NumElts) { 5257 isIdentity = false; 5258 break; 5259 } 5260 } 5261 if (isIdentity) return N->getOperand(1); 5262 5263 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not 5264 // needed at all. 5265 bool isUnary = true; 5266 bool isSplat = true; 5267 int VecNum = -1; 5268 unsigned BaseIdx = 0; 5269 for (unsigned i = 0; i != NumElts; ++i) 5270 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) { 5271 unsigned Idx=cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue(); 5272 int V = (Idx < NumElts) ? 0 : 1; 5273 if (VecNum == -1) { 5274 VecNum = V; 5275 BaseIdx = Idx; 5276 } else { 5277 if (BaseIdx != Idx) 5278 isSplat = false; 5279 if (VecNum != V) { 5280 isUnary = false; 5281 break; 5282 } 5283 } 5284 } 5285 5286 // Normalize unary shuffle so the RHS is undef. 5287 if (isUnary && VecNum == 1) 5288 std::swap(N0, N1); 5289 5290 // If it is a splat, check if the argument vector is a build_vector with 5291 // all scalar elements the same. 5292 if (isSplat) { 5293 SDNode *V = N0.getNode(); 5294 5295 // If this is a bit convert that changes the element type of the vector but 5296 // not the number of vector elements, look through it. Be careful not to 5297 // look though conversions that change things like v4f32 to v2f64. 5298 if (V->getOpcode() == ISD::BIT_CONVERT) { 5299 SDValue ConvInput = V->getOperand(0); 5300 if (ConvInput.getValueType().isVector() && 5301 ConvInput.getValueType().getVectorNumElements() == NumElts) 5302 V = ConvInput.getNode(); 5303 } 5304 5305 if (V->getOpcode() == ISD::BUILD_VECTOR) { 5306 unsigned NumElems = V->getNumOperands(); 5307 if (NumElems > BaseIdx) { 5308 SDValue Base; 5309 bool AllSame = true; 5310 for (unsigned i = 0; i != NumElems; ++i) { 5311 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 5312 Base = V->getOperand(i); 5313 break; 5314 } 5315 } 5316 // Splat of <u, u, u, u>, return <u, u, u, u> 5317 if (!Base.getNode()) 5318 return N0; 5319 for (unsigned i = 0; i != NumElems; ++i) { 5320 if (V->getOperand(i) != Base) { 5321 AllSame = false; 5322 break; 5323 } 5324 } 5325 // Splat of <x, x, x, x>, return <x, x, x, x> 5326 if (AllSame) 5327 return N0; 5328 } 5329 } 5330 } 5331 5332 // If it is a unary or the LHS and the RHS are the same node, turn the RHS 5333 // into an undef. 5334 if (isUnary || N0 == N1) { 5335 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the 5336 // first operand. 5337 SmallVector<SDValue, 8> MappedOps; 5338 5339 for (unsigned i = 0; i != NumElts; ++i) { 5340 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF || 5341 cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() < 5342 NumElts) { 5343 MappedOps.push_back(ShufMask.getOperand(i)); 5344 } else { 5345 unsigned NewIdx = 5346 cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() - 5347 NumElts; 5348 MappedOps.push_back(DAG.getConstant(NewIdx, 5349 ShufMask.getOperand(i).getValueType())); 5350 } 5351 } 5352 5353 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 5354 ShufMask.getValueType(), 5355 &MappedOps[0], MappedOps.size()); 5356 AddToWorkList(ShufMask.getNode()); 5357 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getDebugLoc(), 5358 N->getValueType(0), N0, 5359 DAG.getUNDEF(N->getValueType(0)), 5360 ShufMask); 5361 } 5362 5363 return SDValue(); 5364} 5365 5366/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 5367/// an AND to a vector_shuffle with the destination vector and a zero vector. 5368/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 5369/// vector_shuffle V, Zero, <0, 4, 2, 4> 5370SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) { 5371 SDValue LHS = N->getOperand(0); 5372 SDValue RHS = N->getOperand(1); 5373 if (N->getOpcode() == ISD::AND) { 5374 if (RHS.getOpcode() == ISD::BIT_CONVERT) 5375 RHS = RHS.getOperand(0); 5376 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 5377 std::vector<SDValue> IdxOps; 5378 unsigned NumOps = RHS.getNumOperands(); 5379 unsigned NumElts = NumOps; 5380 for (unsigned i = 0; i != NumElts; ++i) { 5381 SDValue Elt = RHS.getOperand(i); 5382 if (!isa<ConstantSDNode>(Elt)) 5383 return SDValue(); 5384 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 5385 IdxOps.push_back(DAG.getIntPtrConstant(i)); 5386 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 5387 IdxOps.push_back(DAG.getIntPtrConstant(NumElts)); 5388 else 5389 return SDValue(); 5390 } 5391 5392 // Let's see if the target supports this vector_shuffle. 5393 if (!TLI.isVectorClearMaskLegal(IdxOps, TLI.getPointerTy(), DAG)) 5394 return SDValue(); 5395 5396 // Return the new VECTOR_SHUFFLE node. 5397 MVT EVT = RHS.getValueType().getVectorElementType(); 5398 MVT VT = MVT::getVectorVT(EVT, NumElts); 5399 MVT MaskVT = MVT::getVectorVT(TLI.getPointerTy(), NumElts); 5400 std::vector<SDValue> Ops; 5401 LHS = DAG.getNode(ISD::BIT_CONVERT, LHS.getDebugLoc(), VT, LHS); 5402 Ops.push_back(LHS); 5403 AddToWorkList(LHS.getNode()); 5404 std::vector<SDValue> ZeroOps(NumElts, DAG.getConstant(0, EVT)); 5405 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 5406 VT, &ZeroOps[0], ZeroOps.size())); 5407 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 5408 MaskVT, &IdxOps[0], IdxOps.size())); 5409 SDValue Result = DAG.getNode(ISD::VECTOR_SHUFFLE, N->getDebugLoc(), 5410 VT, &Ops[0], Ops.size()); 5411 5412 if (VT != N->getValueType(0)) 5413 Result = DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), 5414 N->getValueType(0), Result); 5415 5416 return Result; 5417 } 5418 } 5419 5420 return SDValue(); 5421} 5422 5423/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 5424SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) { 5425 // After legalize, the target may be depending on adds and other 5426 // binary ops to provide legal ways to construct constants or other 5427 // things. Simplifying them may result in a loss of legality. 5428 if (LegalOperations) return SDValue(); 5429 5430 MVT VT = N->getValueType(0); 5431 assert(VT.isVector() && "SimplifyVBinOp only works on vectors!"); 5432 5433 MVT EltType = VT.getVectorElementType(); 5434 SDValue LHS = N->getOperand(0); 5435 SDValue RHS = N->getOperand(1); 5436 SDValue Shuffle = XformToShuffleWithZero(N); 5437 if (Shuffle.getNode()) return Shuffle; 5438 5439 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 5440 // this operation. 5441 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 5442 RHS.getOpcode() == ISD::BUILD_VECTOR) { 5443 SmallVector<SDValue, 8> Ops; 5444 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 5445 SDValue LHSOp = LHS.getOperand(i); 5446 SDValue RHSOp = RHS.getOperand(i); 5447 // If these two elements can't be folded, bail out. 5448 if ((LHSOp.getOpcode() != ISD::UNDEF && 5449 LHSOp.getOpcode() != ISD::Constant && 5450 LHSOp.getOpcode() != ISD::ConstantFP) || 5451 (RHSOp.getOpcode() != ISD::UNDEF && 5452 RHSOp.getOpcode() != ISD::Constant && 5453 RHSOp.getOpcode() != ISD::ConstantFP)) 5454 break; 5455 5456 // Can't fold divide by zero. 5457 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 5458 N->getOpcode() == ISD::FDIV) { 5459 if ((RHSOp.getOpcode() == ISD::Constant && 5460 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) || 5461 (RHSOp.getOpcode() == ISD::ConstantFP && 5462 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero())) 5463 break; 5464 } 5465 5466 Ops.push_back(DAG.getNode(N->getOpcode(), LHS.getDebugLoc(), 5467 EltType, LHSOp, RHSOp)); 5468 AddToWorkList(Ops.back().getNode()); 5469 assert((Ops.back().getOpcode() == ISD::UNDEF || 5470 Ops.back().getOpcode() == ISD::Constant || 5471 Ops.back().getOpcode() == ISD::ConstantFP) && 5472 "Scalar binop didn't fold!"); 5473 } 5474 5475 if (Ops.size() == LHS.getNumOperands()) { 5476 MVT VT = LHS.getValueType(); 5477 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 5478 &Ops[0], Ops.size()); 5479 } 5480 } 5481 5482 return SDValue(); 5483} 5484 5485SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0, 5486 SDValue N1, SDValue N2){ 5487 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 5488 5489 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2, 5490 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 5491 5492 // If we got a simplified select_cc node back from SimplifySelectCC, then 5493 // break it down into a new SETCC node, and a new SELECT node, and then return 5494 // the SELECT node, since we were called with a SELECT node. 5495 if (SCC.getNode()) { 5496 // Check to see if we got a select_cc back (to turn into setcc/select). 5497 // Otherwise, just return whatever node we got back, like fabs. 5498 if (SCC.getOpcode() == ISD::SELECT_CC) { 5499 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(), 5500 N0.getValueType(), 5501 SCC.getOperand(0), SCC.getOperand(1), 5502 SCC.getOperand(4)); 5503 AddToWorkList(SETCC.getNode()); 5504 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(), 5505 SCC.getOperand(2), SCC.getOperand(3), SETCC); 5506 } 5507 5508 return SCC; 5509 } 5510 return SDValue(); 5511} 5512 5513/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 5514/// are the two values being selected between, see if we can simplify the 5515/// select. Callers of this should assume that TheSelect is deleted if this 5516/// returns true. As such, they should return the appropriate thing (e.g. the 5517/// node) back to the top-level of the DAG combiner loop to avoid it being 5518/// looked at. 5519bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS, 5520 SDValue RHS) { 5521 5522 // If this is a select from two identical things, try to pull the operation 5523 // through the select. 5524 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 5525 // If this is a load and the token chain is identical, replace the select 5526 // of two loads with a load through a select of the address to load from. 5527 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 5528 // constants have been dropped into the constant pool. 5529 if (LHS.getOpcode() == ISD::LOAD && 5530 // Do not let this transformation reduce the number of volatile loads. 5531 !cast<LoadSDNode>(LHS)->isVolatile() && 5532 !cast<LoadSDNode>(RHS)->isVolatile() && 5533 // Token chains must be identical. 5534 LHS.getOperand(0) == RHS.getOperand(0)) { 5535 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 5536 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 5537 5538 // If this is an EXTLOAD, the VT's must match. 5539 if (LLD->getMemoryVT() == RLD->getMemoryVT()) { 5540 // FIXME: this conflates two src values, discarding one. This is not 5541 // the right thing to do, but nothing uses srcvalues now. When they do, 5542 // turn SrcValue into a list of locations. 5543 SDValue Addr; 5544 if (TheSelect->getOpcode() == ISD::SELECT) { 5545 // Check that the condition doesn't reach either load. If so, folding 5546 // this will induce a cycle into the DAG. 5547 if (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5548 !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode())) { 5549 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(), 5550 LLD->getBasePtr().getValueType(), 5551 TheSelect->getOperand(0), LLD->getBasePtr(), 5552 RLD->getBasePtr()); 5553 } 5554 } else { 5555 // Check that the condition doesn't reach either load. If so, folding 5556 // this will induce a cycle into the DAG. 5557 if (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5558 !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5559 !LLD->isPredecessorOf(TheSelect->getOperand(1).getNode()) && 5560 !RLD->isPredecessorOf(TheSelect->getOperand(1).getNode())) { 5561 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(), 5562 LLD->getBasePtr().getValueType(), 5563 TheSelect->getOperand(0), 5564 TheSelect->getOperand(1), 5565 LLD->getBasePtr(), RLD->getBasePtr(), 5566 TheSelect->getOperand(4)); 5567 } 5568 } 5569 5570 if (Addr.getNode()) { 5571 SDValue Load; 5572 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) { 5573 Load = DAG.getLoad(TheSelect->getValueType(0), 5574 TheSelect->getDebugLoc(), 5575 LLD->getChain(), 5576 Addr,LLD->getSrcValue(), 5577 LLD->getSrcValueOffset(), 5578 LLD->isVolatile(), 5579 LLD->getAlignment()); 5580 } else { 5581 Load = DAG.getExtLoad(LLD->getExtensionType(), 5582 TheSelect->getDebugLoc(), 5583 TheSelect->getValueType(0), 5584 LLD->getChain(), Addr, LLD->getSrcValue(), 5585 LLD->getSrcValueOffset(), 5586 LLD->getMemoryVT(), 5587 LLD->isVolatile(), 5588 LLD->getAlignment()); 5589 } 5590 5591 // Users of the select now use the result of the load. 5592 CombineTo(TheSelect, Load); 5593 5594 // Users of the old loads now use the new load's chain. We know the 5595 // old-load value is dead now. 5596 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1)); 5597 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1)); 5598 return true; 5599 } 5600 } 5601 } 5602 } 5603 5604 return false; 5605} 5606 5607/// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3 5608/// where 'cond' is the comparison specified by CC. 5609SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, 5610 SDValue N2, SDValue N3, 5611 ISD::CondCode CC, bool NotExtCompare) { 5612 // (x ? y : y) -> y. 5613 if (N2 == N3) return N2; 5614 5615 MVT VT = N2.getValueType(); 5616 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 5617 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 5618 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode()); 5619 5620 // Determine if the condition we're dealing with is constant 5621 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 5622 N0, N1, CC, DL, false); 5623 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 5624 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode()); 5625 5626 // fold select_cc true, x, y -> x 5627 if (SCCC && !SCCC->isNullValue()) 5628 return N2; 5629 // fold select_cc false, x, y -> y 5630 if (SCCC && SCCC->isNullValue()) 5631 return N3; 5632 5633 // Check to see if we can simplify the select into an fabs node 5634 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 5635 // Allow either -0.0 or 0.0 5636 if (CFP->getValueAPF().isZero()) { 5637 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 5638 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 5639 N0 == N2 && N3.getOpcode() == ISD::FNEG && 5640 N2 == N3.getOperand(0)) 5641 return DAG.getNode(ISD::FABS, DL, VT, N0); 5642 5643 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 5644 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 5645 N0 == N3 && N2.getOpcode() == ISD::FNEG && 5646 N2.getOperand(0) == N3) 5647 return DAG.getNode(ISD::FABS, DL, VT, N3); 5648 } 5649 } 5650 5651 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)" 5652 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0 5653 // in it. This is a win when the constant is not otherwise available because 5654 // it replaces two constant pool loads with one. We only do this if the FP 5655 // type is known to be legal, because if it isn't, then we are before legalize 5656 // types an we want the other legalization to happen first (e.g. to avoid 5657 // messing with soft float). 5658 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2)) 5659 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) { 5660 if (TLI.isTypeLegal(N2.getValueType()) && 5661 // If both constants have multiple uses, then we won't need to do an 5662 // extra load, they are likely around in registers for other users. 5663 (TV->hasOneUse() || FV->hasOneUse())) { 5664 Constant *Elts[] = { 5665 const_cast<ConstantFP*>(FV->getConstantFPValue()), 5666 const_cast<ConstantFP*>(TV->getConstantFPValue()) 5667 }; 5668 const Type *FPTy = Elts[0]->getType(); 5669 const TargetData &TD = *TLI.getTargetData(); 5670 5671 // Create a ConstantArray of the two constants. 5672 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts, 2); 5673 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(), 5674 TD.getPrefTypeAlignment(FPTy)); 5675 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 5676 5677 // Get the offsets to the 0 and 1 element of the array so that we can 5678 // select between them. 5679 SDValue Zero = DAG.getIntPtrConstant(0); 5680 unsigned EltSize = (unsigned)TD.getTypePaddedSize(Elts[0]->getType()); 5681 SDValue One = DAG.getIntPtrConstant(EltSize); 5682 5683 SDValue Cond = DAG.getSetCC(DL, 5684 TLI.getSetCCResultType(N0.getValueType()), 5685 N0, N1, CC); 5686 SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(), 5687 Cond, One, Zero); 5688 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx, 5689 CstOffset); 5690 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx, 5691 PseudoSourceValue::getConstantPool(), 0, false, 5692 Alignment); 5693 5694 } 5695 } 5696 5697 // Check to see if we can perform the "gzip trick", transforming 5698 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A) 5699 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 5700 N0.getValueType().isInteger() && 5701 N2.getValueType().isInteger() && 5702 (N1C->isNullValue() || // (a < 0) ? b : 0 5703 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 5704 MVT XType = N0.getValueType(); 5705 MVT AType = N2.getValueType(); 5706 if (XType.bitsGE(AType)) { 5707 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 5708 // single-bit constant. 5709 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) { 5710 unsigned ShCtV = N2C->getAPIntValue().logBase2(); 5711 ShCtV = XType.getSizeInBits()-ShCtV-1; 5712 SDValue ShCt = DAG.getConstant(ShCtV, getShiftAmountTy()); 5713 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), 5714 XType, N0, ShCt); 5715 AddToWorkList(Shift.getNode()); 5716 5717 if (XType.bitsGT(AType)) { 5718 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 5719 AddToWorkList(Shift.getNode()); 5720 } 5721 5722 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 5723 } 5724 5725 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), 5726 XType, N0, 5727 DAG.getConstant(XType.getSizeInBits()-1, 5728 getShiftAmountTy())); 5729 AddToWorkList(Shift.getNode()); 5730 5731 if (XType.bitsGT(AType)) { 5732 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 5733 AddToWorkList(Shift.getNode()); 5734 } 5735 5736 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 5737 } 5738 } 5739 5740 // fold select C, 16, 0 -> shl C, 4 5741 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() && 5742 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent) { 5743 5744 // If the caller doesn't want us to simplify this into a zext of a compare, 5745 // don't do it. 5746 if (NotExtCompare && N2C->getAPIntValue() == 1) 5747 return SDValue(); 5748 5749 // Get a SetCC of the condition 5750 // FIXME: Should probably make sure that setcc is legal if we ever have a 5751 // target where it isn't. 5752 SDValue Temp, SCC; 5753 // cast from setcc result type to select result type 5754 if (LegalTypes) { 5755 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()), 5756 N0, N1, CC); 5757 if (N2.getValueType().bitsLT(SCC.getValueType())) 5758 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), N2.getValueType()); 5759 else 5760 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 5761 N2.getValueType(), SCC); 5762 } else { 5763 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC); 5764 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 5765 N2.getValueType(), SCC); 5766 } 5767 5768 AddToWorkList(SCC.getNode()); 5769 AddToWorkList(Temp.getNode()); 5770 5771 if (N2C->getAPIntValue() == 1) 5772 return Temp; 5773 5774 // shl setcc result by log2 n2c 5775 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp, 5776 DAG.getConstant(N2C->getAPIntValue().logBase2(), 5777 getShiftAmountTy())); 5778 } 5779 5780 // Check to see if this is the equivalent of setcc 5781 // FIXME: Turn all of these into setcc if setcc if setcc is legal 5782 // otherwise, go ahead with the folds. 5783 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) { 5784 MVT XType = N0.getValueType(); 5785 if (!LegalOperations || 5786 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) { 5787 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC); 5788 if (Res.getValueType() != VT) 5789 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res); 5790 return Res; 5791 } 5792 5793 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X)))) 5794 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 5795 (!LegalOperations || 5796 TLI.isOperationLegal(ISD::CTLZ, XType))) { 5797 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0); 5798 return DAG.getNode(ISD::SRL, DL, XType, Ctlz, 5799 DAG.getConstant(Log2_32(XType.getSizeInBits()), 5800 getShiftAmountTy())); 5801 } 5802 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1)) 5803 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 5804 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(), 5805 XType, DAG.getConstant(0, XType), N0); 5806 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType); 5807 return DAG.getNode(ISD::SRL, DL, XType, 5808 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0), 5809 DAG.getConstant(XType.getSizeInBits()-1, 5810 getShiftAmountTy())); 5811 } 5812 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1)) 5813 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 5814 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0, 5815 DAG.getConstant(XType.getSizeInBits()-1, 5816 getShiftAmountTy())); 5817 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType)); 5818 } 5819 } 5820 5821 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 5822 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 5823 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 5824 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) && 5825 N2.getOperand(0) == N1 && N0.getValueType().isInteger()) { 5826 MVT XType = N0.getValueType(); 5827 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, N0, 5828 DAG.getConstant(XType.getSizeInBits()-1, 5829 getShiftAmountTy())); 5830 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), XType, 5831 N0, Shift); 5832 AddToWorkList(Shift.getNode()); 5833 AddToWorkList(Add.getNode()); 5834 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); 5835 } 5836 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X -> 5837 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 5838 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT && 5839 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) { 5840 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) { 5841 MVT XType = N0.getValueType(); 5842 if (SubC->isNullValue() && XType.isInteger()) { 5843 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, 5844 N0, 5845 DAG.getConstant(XType.getSizeInBits()-1, 5846 getShiftAmountTy())); 5847 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), 5848 XType, N0, Shift); 5849 AddToWorkList(Shift.getNode()); 5850 AddToWorkList(Add.getNode()); 5851 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); 5852 } 5853 } 5854 } 5855 5856 return SDValue(); 5857} 5858 5859/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 5860SDValue DAGCombiner::SimplifySetCC(MVT VT, SDValue N0, 5861 SDValue N1, ISD::CondCode Cond, 5862 DebugLoc DL, bool foldBooleans) { 5863 TargetLowering::DAGCombinerInfo 5864 DagCombineInfo(DAG, Level == Unrestricted, false, this); 5865 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL); 5866} 5867 5868/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 5869/// return a DAG expression to select that will generate the same value by 5870/// multiplying by a magic number. See: 5871/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 5872SDValue DAGCombiner::BuildSDIV(SDNode *N) { 5873 std::vector<SDNode*> Built; 5874 SDValue S = TLI.BuildSDIV(N, DAG, &Built); 5875 5876 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 5877 ii != ee; ++ii) 5878 AddToWorkList(*ii); 5879 return S; 5880} 5881 5882/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 5883/// return a DAG expression to select that will generate the same value by 5884/// multiplying by a magic number. See: 5885/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 5886SDValue DAGCombiner::BuildUDIV(SDNode *N) { 5887 std::vector<SDNode*> Built; 5888 SDValue S = TLI.BuildUDIV(N, DAG, &Built); 5889 5890 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 5891 ii != ee; ++ii) 5892 AddToWorkList(*ii); 5893 return S; 5894} 5895 5896/// FindBaseOffset - Return true if base is known not to alias with anything 5897/// but itself. Provides base object and offset as results. 5898static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset) { 5899 // Assume it is a primitive operation. 5900 Base = Ptr; Offset = 0; 5901 5902 // If it's an adding a simple constant then integrate the offset. 5903 if (Base.getOpcode() == ISD::ADD) { 5904 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 5905 Base = Base.getOperand(0); 5906 Offset += C->getZExtValue(); 5907 } 5908 } 5909 5910 // If it's any of the following then it can't alias with anything but itself. 5911 return isa<FrameIndexSDNode>(Base) || 5912 isa<ConstantPoolSDNode>(Base) || 5913 isa<GlobalAddressSDNode>(Base); 5914} 5915 5916/// isAlias - Return true if there is any possibility that the two addresses 5917/// overlap. 5918bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1, 5919 const Value *SrcValue1, int SrcValueOffset1, 5920 SDValue Ptr2, int64_t Size2, 5921 const Value *SrcValue2, int SrcValueOffset2) const { 5922 // If they are the same then they must be aliases. 5923 if (Ptr1 == Ptr2) return true; 5924 5925 // Gather base node and offset information. 5926 SDValue Base1, Base2; 5927 int64_t Offset1, Offset2; 5928 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1); 5929 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2); 5930 5931 // If they have a same base address then... 5932 if (Base1 == Base2) 5933 // Check to see if the addresses overlap. 5934 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 5935 5936 // If we know both bases then they can't alias. 5937 if (KnownBase1 && KnownBase2) return false; 5938 5939 if (CombinerGlobalAA) { 5940 // Use alias analysis information. 5941 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 5942 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 5943 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 5944 AliasAnalysis::AliasResult AAResult = 5945 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2); 5946 if (AAResult == AliasAnalysis::NoAlias) 5947 return false; 5948 } 5949 5950 // Otherwise we have to assume they alias. 5951 return true; 5952} 5953 5954/// FindAliasInfo - Extracts the relevant alias information from the memory 5955/// node. Returns true if the operand was a load. 5956bool DAGCombiner::FindAliasInfo(SDNode *N, 5957 SDValue &Ptr, int64_t &Size, 5958 const Value *&SrcValue, int &SrcValueOffset) const { 5959 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 5960 Ptr = LD->getBasePtr(); 5961 Size = LD->getMemoryVT().getSizeInBits() >> 3; 5962 SrcValue = LD->getSrcValue(); 5963 SrcValueOffset = LD->getSrcValueOffset(); 5964 return true; 5965 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 5966 Ptr = ST->getBasePtr(); 5967 Size = ST->getMemoryVT().getSizeInBits() >> 3; 5968 SrcValue = ST->getSrcValue(); 5969 SrcValueOffset = ST->getSrcValueOffset(); 5970 } else { 5971 assert(0 && "FindAliasInfo expected a memory operand"); 5972 } 5973 5974 return false; 5975} 5976 5977/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 5978/// looking for aliasing nodes and adding them to the Aliases vector. 5979void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain, 5980 SmallVector<SDValue, 8> &Aliases) { 5981 SmallVector<SDValue, 8> Chains; // List of chains to visit. 5982 std::set<SDNode *> Visited; // Visited node set. 5983 5984 // Get alias information for node. 5985 SDValue Ptr; 5986 int64_t Size; 5987 const Value *SrcValue; 5988 int SrcValueOffset; 5989 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset); 5990 5991 // Starting off. 5992 Chains.push_back(OriginalChain); 5993 5994 // Look at each chain and determine if it is an alias. If so, add it to the 5995 // aliases list. If not, then continue up the chain looking for the next 5996 // candidate. 5997 while (!Chains.empty()) { 5998 SDValue Chain = Chains.back(); 5999 Chains.pop_back(); 6000 6001 // Don't bother if we've been before. 6002 if (Visited.find(Chain.getNode()) != Visited.end()) continue; 6003 Visited.insert(Chain.getNode()); 6004 6005 switch (Chain.getOpcode()) { 6006 case ISD::EntryToken: 6007 // Entry token is ideal chain operand, but handled in FindBetterChain. 6008 break; 6009 6010 case ISD::LOAD: 6011 case ISD::STORE: { 6012 // Get alias information for Chain. 6013 SDValue OpPtr; 6014 int64_t OpSize; 6015 const Value *OpSrcValue; 6016 int OpSrcValueOffset; 6017 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize, 6018 OpSrcValue, OpSrcValueOffset); 6019 6020 // If chain is alias then stop here. 6021 if (!(IsLoad && IsOpLoad) && 6022 isAlias(Ptr, Size, SrcValue, SrcValueOffset, 6023 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) { 6024 Aliases.push_back(Chain); 6025 } else { 6026 // Look further up the chain. 6027 Chains.push_back(Chain.getOperand(0)); 6028 // Clean up old chain. 6029 AddToWorkList(Chain.getNode()); 6030 } 6031 break; 6032 } 6033 6034 case ISD::TokenFactor: 6035 // We have to check each of the operands of the token factor, so we queue 6036 // then up. Adding the operands to the queue (stack) in reverse order 6037 // maintains the original order and increases the likelihood that getNode 6038 // will find a matching token factor (CSE.) 6039 for (unsigned n = Chain.getNumOperands(); n;) 6040 Chains.push_back(Chain.getOperand(--n)); 6041 // Eliminate the token factor if we can. 6042 AddToWorkList(Chain.getNode()); 6043 break; 6044 6045 default: 6046 // For all other instructions we will just have to take what we can get. 6047 Aliases.push_back(Chain); 6048 break; 6049 } 6050 } 6051} 6052 6053/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 6054/// for a better chain (aliasing node.) 6055SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) { 6056 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor. 6057 6058 // Accumulate all the aliases to this node. 6059 GatherAllAliases(N, OldChain, Aliases); 6060 6061 if (Aliases.size() == 0) { 6062 // If no operands then chain to entry token. 6063 return DAG.getEntryNode(); 6064 } else if (Aliases.size() == 1) { 6065 // If a single operand then chain to it. We don't need to revisit it. 6066 return Aliases[0]; 6067 } 6068 6069 // Construct a custom tailored token factor. 6070 SDValue NewChain = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 6071 &Aliases[0], Aliases.size()); 6072 6073 // Make sure the old chain gets cleaned up. 6074 if (NewChain != OldChain) AddToWorkList(OldChain.getNode()); 6075 6076 return NewChain; 6077} 6078 6079// SelectionDAG::Combine - This is the entry point for the file. 6080// 6081void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA, bool Fast) { 6082 /// run - This is the main entry point to this class. 6083 /// 6084 DAGCombiner(*this, AA, Fast).Run(Level); 6085} 6086