FastISel.cpp revision 474d3b3f40e117a66946e9fb9d2016b4c05caef0
1///===-- FastISel.cpp - Implementation of the FastISel class --------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the implementation of the FastISel class. 11// 12// "Fast" instruction selection is designed to emit very poor code quickly. 13// Also, it is not designed to be able to do much lowering, so most illegal 14// types (e.g. i64 on 32-bit targets) and operations are not supported. It is 15// also not intended to be able to do much optimization, except in a few cases 16// where doing optimizations reduces overall compile time. For example, folding 17// constants into immediate fields is often done, because it's cheap and it 18// reduces the number of instructions later phases have to examine. 19// 20// "Fast" instruction selection is able to fail gracefully and transfer 21// control to the SelectionDAG selector for operations that it doesn't 22// support. In many cases, this allows us to avoid duplicating a lot of 23// the complicated lowering logic that SelectionDAG currently has. 24// 25// The intended use for "fast" instruction selection is "-O0" mode 26// compilation, where the quality of the generated code is irrelevant when 27// weighed against the speed at which the code can be generated. Also, 28// at -O0, the LLVM optimizers are not running, and this makes the 29// compile time of codegen a much higher portion of the overall compile 30// time. Despite its limitations, "fast" instruction selection is able to 31// handle enough code on its own to provide noticeable overall speedups 32// in -O0 compiles. 33// 34// Basic operations are supported in a target-independent way, by reading 35// the same instruction descriptions that the SelectionDAG selector reads, 36// and identifying simple arithmetic operations that can be directly selected 37// from simple operators. More complicated operations currently require 38// target-specific code. 39// 40//===----------------------------------------------------------------------===// 41 42#include "llvm/Function.h" 43#include "llvm/GlobalVariable.h" 44#include "llvm/Instructions.h" 45#include "llvm/IntrinsicInst.h" 46#include "llvm/CodeGen/FastISel.h" 47#include "llvm/CodeGen/MachineInstrBuilder.h" 48#include "llvm/CodeGen/MachineModuleInfo.h" 49#include "llvm/CodeGen/MachineRegisterInfo.h" 50#include "llvm/CodeGen/DwarfWriter.h" 51#include "llvm/Analysis/DebugInfo.h" 52#include "llvm/Target/TargetData.h" 53#include "llvm/Target/TargetInstrInfo.h" 54#include "llvm/Target/TargetLowering.h" 55#include "llvm/Target/TargetMachine.h" 56#include "SelectionDAGBuild.h" 57using namespace llvm; 58 59unsigned FastISel::getRegForValue(Value *V) { 60 MVT::SimpleValueType VT = TLI.getValueType(V->getType()).getSimpleVT(); 61 62 // Ignore illegal types. We must do this before looking up the value 63 // in ValueMap because Arguments are given virtual registers regardless 64 // of whether FastISel can handle them. 65 if (!TLI.isTypeLegal(VT)) { 66 // Promote MVT::i1 to a legal type though, because it's common and easy. 67 if (VT == MVT::i1) 68 VT = TLI.getTypeToTransformTo(VT).getSimpleVT(); 69 else 70 return 0; 71 } 72 73 // Look up the value to see if we already have a register for it. We 74 // cache values defined by Instructions across blocks, and other values 75 // only locally. This is because Instructions already have the SSA 76 // def-dominatess-use requirement enforced. 77 if (ValueMap.count(V)) 78 return ValueMap[V]; 79 unsigned Reg = LocalValueMap[V]; 80 if (Reg != 0) 81 return Reg; 82 83 if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) { 84 if (CI->getValue().getActiveBits() <= 64) 85 Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue()); 86 } else if (isa<AllocaInst>(V)) { 87 Reg = TargetMaterializeAlloca(cast<AllocaInst>(V)); 88 } else if (isa<ConstantPointerNull>(V)) { 89 // Translate this as an integer zero so that it can be 90 // local-CSE'd with actual integer zeros. 91 Reg = getRegForValue(Constant::getNullValue(TD.getIntPtrType())); 92 } else if (ConstantFP *CF = dyn_cast<ConstantFP>(V)) { 93 Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF); 94 95 if (!Reg) { 96 const APFloat &Flt = CF->getValueAPF(); 97 MVT IntVT = TLI.getPointerTy(); 98 99 uint64_t x[2]; 100 uint32_t IntBitWidth = IntVT.getSizeInBits(); 101 bool isExact; 102 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true, 103 APFloat::rmTowardZero, &isExact); 104 if (isExact) { 105 APInt IntVal(IntBitWidth, 2, x); 106 107 unsigned IntegerReg = getRegForValue(ConstantInt::get(IntVal)); 108 if (IntegerReg != 0) 109 Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg); 110 } 111 } 112 } else if (ConstantExpr *CE = dyn_cast<ConstantExpr>(V)) { 113 if (!SelectOperator(CE, CE->getOpcode())) return 0; 114 Reg = LocalValueMap[CE]; 115 } else if (isa<UndefValue>(V)) { 116 Reg = createResultReg(TLI.getRegClassFor(VT)); 117 BuildMI(MBB, DL, TII.get(TargetInstrInfo::IMPLICIT_DEF), Reg); 118 } 119 120 // If target-independent code couldn't handle the value, give target-specific 121 // code a try. 122 if (!Reg && isa<Constant>(V)) 123 Reg = TargetMaterializeConstant(cast<Constant>(V)); 124 125 // Don't cache constant materializations in the general ValueMap. 126 // To do so would require tracking what uses they dominate. 127 if (Reg != 0) 128 LocalValueMap[V] = Reg; 129 return Reg; 130} 131 132unsigned FastISel::lookUpRegForValue(Value *V) { 133 // Look up the value to see if we already have a register for it. We 134 // cache values defined by Instructions across blocks, and other values 135 // only locally. This is because Instructions already have the SSA 136 // def-dominatess-use requirement enforced. 137 if (ValueMap.count(V)) 138 return ValueMap[V]; 139 return LocalValueMap[V]; 140} 141 142/// UpdateValueMap - Update the value map to include the new mapping for this 143/// instruction, or insert an extra copy to get the result in a previous 144/// determined register. 145/// NOTE: This is only necessary because we might select a block that uses 146/// a value before we select the block that defines the value. It might be 147/// possible to fix this by selecting blocks in reverse postorder. 148void FastISel::UpdateValueMap(Value* I, unsigned Reg) { 149 if (!isa<Instruction>(I)) { 150 LocalValueMap[I] = Reg; 151 return; 152 } 153 if (!ValueMap.count(I)) 154 ValueMap[I] = Reg; 155 else 156 TII.copyRegToReg(*MBB, MBB->end(), ValueMap[I], 157 Reg, MRI.getRegClass(Reg), MRI.getRegClass(Reg)); 158} 159 160unsigned FastISel::getRegForGEPIndex(Value *Idx) { 161 unsigned IdxN = getRegForValue(Idx); 162 if (IdxN == 0) 163 // Unhandled operand. Halt "fast" selection and bail. 164 return 0; 165 166 // If the index is smaller or larger than intptr_t, truncate or extend it. 167 MVT PtrVT = TLI.getPointerTy(); 168 MVT IdxVT = MVT::getMVT(Idx->getType(), /*HandleUnknown=*/false); 169 if (IdxVT.bitsLT(PtrVT)) 170 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT.getSimpleVT(), 171 ISD::SIGN_EXTEND, IdxN); 172 else if (IdxVT.bitsGT(PtrVT)) 173 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT.getSimpleVT(), 174 ISD::TRUNCATE, IdxN); 175 return IdxN; 176} 177 178/// SelectBinaryOp - Select and emit code for a binary operator instruction, 179/// which has an opcode which directly corresponds to the given ISD opcode. 180/// 181bool FastISel::SelectBinaryOp(User *I, ISD::NodeType ISDOpcode) { 182 MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/true); 183 if (VT == MVT::Other || !VT.isSimple()) 184 // Unhandled type. Halt "fast" selection and bail. 185 return false; 186 187 // We only handle legal types. For example, on x86-32 the instruction 188 // selector contains all of the 64-bit instructions from x86-64, 189 // under the assumption that i64 won't be used if the target doesn't 190 // support it. 191 if (!TLI.isTypeLegal(VT)) { 192 // MVT::i1 is special. Allow AND, OR, or XOR because they 193 // don't require additional zeroing, which makes them easy. 194 if (VT == MVT::i1 && 195 (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR || 196 ISDOpcode == ISD::XOR)) 197 VT = TLI.getTypeToTransformTo(VT); 198 else 199 return false; 200 } 201 202 unsigned Op0 = getRegForValue(I->getOperand(0)); 203 if (Op0 == 0) 204 // Unhandled operand. Halt "fast" selection and bail. 205 return false; 206 207 // Check if the second operand is a constant and handle it appropriately. 208 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) { 209 unsigned ResultReg = FastEmit_ri(VT.getSimpleVT(), VT.getSimpleVT(), 210 ISDOpcode, Op0, CI->getZExtValue()); 211 if (ResultReg != 0) { 212 // We successfully emitted code for the given LLVM Instruction. 213 UpdateValueMap(I, ResultReg); 214 return true; 215 } 216 } 217 218 // Check if the second operand is a constant float. 219 if (ConstantFP *CF = dyn_cast<ConstantFP>(I->getOperand(1))) { 220 unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(), 221 ISDOpcode, Op0, CF); 222 if (ResultReg != 0) { 223 // We successfully emitted code for the given LLVM Instruction. 224 UpdateValueMap(I, ResultReg); 225 return true; 226 } 227 } 228 229 unsigned Op1 = getRegForValue(I->getOperand(1)); 230 if (Op1 == 0) 231 // Unhandled operand. Halt "fast" selection and bail. 232 return false; 233 234 // Now we have both operands in registers. Emit the instruction. 235 unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(), 236 ISDOpcode, Op0, Op1); 237 if (ResultReg == 0) 238 // Target-specific code wasn't able to find a machine opcode for 239 // the given ISD opcode and type. Halt "fast" selection and bail. 240 return false; 241 242 // We successfully emitted code for the given LLVM Instruction. 243 UpdateValueMap(I, ResultReg); 244 return true; 245} 246 247bool FastISel::SelectGetElementPtr(User *I) { 248 unsigned N = getRegForValue(I->getOperand(0)); 249 if (N == 0) 250 // Unhandled operand. Halt "fast" selection and bail. 251 return false; 252 253 const Type *Ty = I->getOperand(0)->getType(); 254 MVT::SimpleValueType VT = TLI.getPointerTy().getSimpleVT(); 255 for (GetElementPtrInst::op_iterator OI = I->op_begin()+1, E = I->op_end(); 256 OI != E; ++OI) { 257 Value *Idx = *OI; 258 if (const StructType *StTy = dyn_cast<StructType>(Ty)) { 259 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 260 if (Field) { 261 // N = N + Offset 262 uint64_t Offs = TD.getStructLayout(StTy)->getElementOffset(Field); 263 // FIXME: This can be optimized by combining the add with a 264 // subsequent one. 265 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT); 266 if (N == 0) 267 // Unhandled operand. Halt "fast" selection and bail. 268 return false; 269 } 270 Ty = StTy->getElementType(Field); 271 } else { 272 Ty = cast<SequentialType>(Ty)->getElementType(); 273 274 // If this is a constant subscript, handle it quickly. 275 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 276 if (CI->getZExtValue() == 0) continue; 277 uint64_t Offs = 278 TD.getTypePaddedSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 279 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT); 280 if (N == 0) 281 // Unhandled operand. Halt "fast" selection and bail. 282 return false; 283 continue; 284 } 285 286 // N = N + Idx * ElementSize; 287 uint64_t ElementSize = TD.getTypePaddedSize(Ty); 288 unsigned IdxN = getRegForGEPIndex(Idx); 289 if (IdxN == 0) 290 // Unhandled operand. Halt "fast" selection and bail. 291 return false; 292 293 if (ElementSize != 1) { 294 IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, ElementSize, VT); 295 if (IdxN == 0) 296 // Unhandled operand. Halt "fast" selection and bail. 297 return false; 298 } 299 N = FastEmit_rr(VT, VT, ISD::ADD, N, IdxN); 300 if (N == 0) 301 // Unhandled operand. Halt "fast" selection and bail. 302 return false; 303 } 304 } 305 306 // We successfully emitted code for the given LLVM Instruction. 307 UpdateValueMap(I, N); 308 return true; 309} 310 311bool FastISel::SelectCall(User *I) { 312 Function *F = cast<CallInst>(I)->getCalledFunction(); 313 if (!F) return false; 314 315 unsigned IID = F->getIntrinsicID(); 316 switch (IID) { 317 default: break; 318 case Intrinsic::dbg_stoppoint: { 319 DbgStopPointInst *SPI = cast<DbgStopPointInst>(I); 320 if (DW && DW->ValidDebugInfo(SPI->getContext())) { 321 DICompileUnit CU(cast<GlobalVariable>(SPI->getContext())); 322 std::string Dir, FN; 323 unsigned SrcFile = DW->getOrCreateSourceID(CU.getDirectory(Dir), 324 CU.getFilename(FN)); 325 unsigned Line = SPI->getLine(); 326 unsigned Col = SPI->getColumn(); 327 unsigned ID = DW->RecordSourceLine(Line, Col, SrcFile); 328 unsigned Idx = MF.getOrCreateDebugLocID(SrcFile, Line, Col); 329 setCurDebugLoc(DebugLoc::get(Idx)); 330 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL); 331 BuildMI(MBB, DL, II).addImm(ID); 332 } 333 return true; 334 } 335 case Intrinsic::dbg_region_start: { 336 DbgRegionStartInst *RSI = cast<DbgRegionStartInst>(I); 337 if (DW && DW->ValidDebugInfo(RSI->getContext())) { 338 unsigned ID = 339 DW->RecordRegionStart(cast<GlobalVariable>(RSI->getContext())); 340 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL); 341 BuildMI(MBB, DL, II).addImm(ID); 342 } 343 return true; 344 } 345 case Intrinsic::dbg_region_end: { 346 DbgRegionEndInst *REI = cast<DbgRegionEndInst>(I); 347 if (DW && DW->ValidDebugInfo(REI->getContext())) { 348 unsigned ID = 349 DW->RecordRegionEnd(cast<GlobalVariable>(REI->getContext())); 350 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL); 351 BuildMI(MBB, DL, II).addImm(ID); 352 } 353 return true; 354 } 355 case Intrinsic::dbg_func_start: { 356 if (!DW) return true; 357 DbgFuncStartInst *FSI = cast<DbgFuncStartInst>(I); 358 Value *SP = FSI->getSubprogram(); 359 360 if (DW->ValidDebugInfo(SP)) { 361 // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is what 362 // (most?) gdb expects. 363 DISubprogram Subprogram(cast<GlobalVariable>(SP)); 364 DICompileUnit CompileUnit = Subprogram.getCompileUnit(); 365 std::string Dir, FN; 366 unsigned SrcFile = DW->getOrCreateSourceID(CompileUnit.getDirectory(Dir), 367 CompileUnit.getFilename(FN)); 368 369 // Record the source line but does not create a label for the normal 370 // function start. It will be emitted at asm emission time. However, 371 // create a label if this is a beginning of inlined function. 372 unsigned Line = Subprogram.getLineNumber(); 373 unsigned LabelID = DW->RecordSourceLine(Line, 0, SrcFile); 374 setCurDebugLoc(DebugLoc::get(MF.getOrCreateDebugLocID(SrcFile, Line, 0))); 375 376 if (DW->getRecordSourceLineCount() != 1) { 377 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL); 378 BuildMI(MBB, DL, II).addImm(LabelID); 379 } 380 } 381 382 return true; 383 } 384 case Intrinsic::dbg_declare: { 385 DbgDeclareInst *DI = cast<DbgDeclareInst>(I); 386 Value *Variable = DI->getVariable(); 387 if (DW && DW->ValidDebugInfo(Variable)) { 388 // Determine the address of the declared object. 389 Value *Address = DI->getAddress(); 390 if (BitCastInst *BCI = dyn_cast<BitCastInst>(Address)) 391 Address = BCI->getOperand(0); 392 AllocaInst *AI = dyn_cast<AllocaInst>(Address); 393 // Don't handle byval struct arguments or VLAs, for example. 394 if (!AI) break; 395 DenseMap<const AllocaInst*, int>::iterator SI = 396 StaticAllocaMap.find(AI); 397 if (SI == StaticAllocaMap.end()) break; // VLAs. 398 int FI = SI->second; 399 400 // Determine the debug globalvariable. 401 GlobalValue *GV = cast<GlobalVariable>(Variable); 402 403 // Build the DECLARE instruction. 404 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DECLARE); 405 BuildMI(MBB, DL, II).addFrameIndex(FI).addGlobalAddress(GV); 406 } 407 return true; 408 } 409 case Intrinsic::eh_exception: { 410 MVT VT = TLI.getValueType(I->getType()); 411 switch (TLI.getOperationAction(ISD::EXCEPTIONADDR, VT)) { 412 default: break; 413 case TargetLowering::Expand: { 414 if (!MBB->isLandingPad()) { 415 // FIXME: Mark exception register as live in. Hack for PR1508. 416 unsigned Reg = TLI.getExceptionAddressRegister(); 417 if (Reg) MBB->addLiveIn(Reg); 418 } 419 unsigned Reg = TLI.getExceptionAddressRegister(); 420 const TargetRegisterClass *RC = TLI.getRegClassFor(VT); 421 unsigned ResultReg = createResultReg(RC); 422 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 423 Reg, RC, RC); 424 assert(InsertedCopy && "Can't copy address registers!"); 425 InsertedCopy = InsertedCopy; 426 UpdateValueMap(I, ResultReg); 427 return true; 428 } 429 } 430 break; 431 } 432 case Intrinsic::eh_selector_i32: 433 case Intrinsic::eh_selector_i64: { 434 MVT VT = TLI.getValueType(I->getType()); 435 switch (TLI.getOperationAction(ISD::EHSELECTION, VT)) { 436 default: break; 437 case TargetLowering::Expand: { 438 MVT VT = (IID == Intrinsic::eh_selector_i32 ? 439 MVT::i32 : MVT::i64); 440 441 if (MMI) { 442 if (MBB->isLandingPad()) 443 AddCatchInfo(*cast<CallInst>(I), MMI, MBB); 444 else { 445#ifndef NDEBUG 446 CatchInfoLost.insert(cast<CallInst>(I)); 447#endif 448 // FIXME: Mark exception selector register as live in. Hack for PR1508. 449 unsigned Reg = TLI.getExceptionSelectorRegister(); 450 if (Reg) MBB->addLiveIn(Reg); 451 } 452 453 unsigned Reg = TLI.getExceptionSelectorRegister(); 454 const TargetRegisterClass *RC = TLI.getRegClassFor(VT); 455 unsigned ResultReg = createResultReg(RC); 456 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 457 Reg, RC, RC); 458 assert(InsertedCopy && "Can't copy address registers!"); 459 InsertedCopy = InsertedCopy; 460 UpdateValueMap(I, ResultReg); 461 } else { 462 unsigned ResultReg = 463 getRegForValue(Constant::getNullValue(I->getType())); 464 UpdateValueMap(I, ResultReg); 465 } 466 return true; 467 } 468 } 469 break; 470 } 471 } 472 return false; 473} 474 475bool FastISel::SelectCast(User *I, ISD::NodeType Opcode) { 476 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 477 MVT DstVT = TLI.getValueType(I->getType()); 478 479 if (SrcVT == MVT::Other || !SrcVT.isSimple() || 480 DstVT == MVT::Other || !DstVT.isSimple()) 481 // Unhandled type. Halt "fast" selection and bail. 482 return false; 483 484 // Check if the destination type is legal. Or as a special case, 485 // it may be i1 if we're doing a truncate because that's 486 // easy and somewhat common. 487 if (!TLI.isTypeLegal(DstVT)) 488 if (DstVT != MVT::i1 || Opcode != ISD::TRUNCATE) 489 // Unhandled type. Halt "fast" selection and bail. 490 return false; 491 492 // Check if the source operand is legal. Or as a special case, 493 // it may be i1 if we're doing zero-extension because that's 494 // easy and somewhat common. 495 if (!TLI.isTypeLegal(SrcVT)) 496 if (SrcVT != MVT::i1 || Opcode != ISD::ZERO_EXTEND) 497 // Unhandled type. Halt "fast" selection and bail. 498 return false; 499 500 unsigned InputReg = getRegForValue(I->getOperand(0)); 501 if (!InputReg) 502 // Unhandled operand. Halt "fast" selection and bail. 503 return false; 504 505 // If the operand is i1, arrange for the high bits in the register to be zero. 506 if (SrcVT == MVT::i1) { 507 SrcVT = TLI.getTypeToTransformTo(SrcVT); 508 InputReg = FastEmitZExtFromI1(SrcVT.getSimpleVT(), InputReg); 509 if (!InputReg) 510 return false; 511 } 512 // If the result is i1, truncate to the target's type for i1 first. 513 if (DstVT == MVT::i1) 514 DstVT = TLI.getTypeToTransformTo(DstVT); 515 516 unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(), 517 DstVT.getSimpleVT(), 518 Opcode, 519 InputReg); 520 if (!ResultReg) 521 return false; 522 523 UpdateValueMap(I, ResultReg); 524 return true; 525} 526 527bool FastISel::SelectBitCast(User *I) { 528 // If the bitcast doesn't change the type, just use the operand value. 529 if (I->getType() == I->getOperand(0)->getType()) { 530 unsigned Reg = getRegForValue(I->getOperand(0)); 531 if (Reg == 0) 532 return false; 533 UpdateValueMap(I, Reg); 534 return true; 535 } 536 537 // Bitcasts of other values become reg-reg copies or BIT_CONVERT operators. 538 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 539 MVT DstVT = TLI.getValueType(I->getType()); 540 541 if (SrcVT == MVT::Other || !SrcVT.isSimple() || 542 DstVT == MVT::Other || !DstVT.isSimple() || 543 !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT)) 544 // Unhandled type. Halt "fast" selection and bail. 545 return false; 546 547 unsigned Op0 = getRegForValue(I->getOperand(0)); 548 if (Op0 == 0) 549 // Unhandled operand. Halt "fast" selection and bail. 550 return false; 551 552 // First, try to perform the bitcast by inserting a reg-reg copy. 553 unsigned ResultReg = 0; 554 if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) { 555 TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT); 556 TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT); 557 ResultReg = createResultReg(DstClass); 558 559 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 560 Op0, DstClass, SrcClass); 561 if (!InsertedCopy) 562 ResultReg = 0; 563 } 564 565 // If the reg-reg copy failed, select a BIT_CONVERT opcode. 566 if (!ResultReg) 567 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), 568 ISD::BIT_CONVERT, Op0); 569 570 if (!ResultReg) 571 return false; 572 573 UpdateValueMap(I, ResultReg); 574 return true; 575} 576 577bool 578FastISel::SelectInstruction(Instruction *I) { 579 return SelectOperator(I, I->getOpcode()); 580} 581 582/// FastEmitBranch - Emit an unconditional branch to the given block, 583/// unless it is the immediate (fall-through) successor, and update 584/// the CFG. 585void 586FastISel::FastEmitBranch(MachineBasicBlock *MSucc) { 587 MachineFunction::iterator NextMBB = 588 next(MachineFunction::iterator(MBB)); 589 590 if (MBB->isLayoutSuccessor(MSucc)) { 591 // The unconditional fall-through case, which needs no instructions. 592 } else { 593 // The unconditional branch case. 594 TII.InsertBranch(*MBB, MSucc, NULL, SmallVector<MachineOperand, 0>()); 595 } 596 MBB->addSuccessor(MSucc); 597} 598 599bool 600FastISel::SelectOperator(User *I, unsigned Opcode) { 601 switch (Opcode) { 602 case Instruction::Add: { 603 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FADD : ISD::ADD; 604 return SelectBinaryOp(I, Opc); 605 } 606 case Instruction::Sub: { 607 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FSUB : ISD::SUB; 608 return SelectBinaryOp(I, Opc); 609 } 610 case Instruction::Mul: { 611 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FMUL : ISD::MUL; 612 return SelectBinaryOp(I, Opc); 613 } 614 case Instruction::SDiv: 615 return SelectBinaryOp(I, ISD::SDIV); 616 case Instruction::UDiv: 617 return SelectBinaryOp(I, ISD::UDIV); 618 case Instruction::FDiv: 619 return SelectBinaryOp(I, ISD::FDIV); 620 case Instruction::SRem: 621 return SelectBinaryOp(I, ISD::SREM); 622 case Instruction::URem: 623 return SelectBinaryOp(I, ISD::UREM); 624 case Instruction::FRem: 625 return SelectBinaryOp(I, ISD::FREM); 626 case Instruction::Shl: 627 return SelectBinaryOp(I, ISD::SHL); 628 case Instruction::LShr: 629 return SelectBinaryOp(I, ISD::SRL); 630 case Instruction::AShr: 631 return SelectBinaryOp(I, ISD::SRA); 632 case Instruction::And: 633 return SelectBinaryOp(I, ISD::AND); 634 case Instruction::Or: 635 return SelectBinaryOp(I, ISD::OR); 636 case Instruction::Xor: 637 return SelectBinaryOp(I, ISD::XOR); 638 639 case Instruction::GetElementPtr: 640 return SelectGetElementPtr(I); 641 642 case Instruction::Br: { 643 BranchInst *BI = cast<BranchInst>(I); 644 645 if (BI->isUnconditional()) { 646 BasicBlock *LLVMSucc = BI->getSuccessor(0); 647 MachineBasicBlock *MSucc = MBBMap[LLVMSucc]; 648 FastEmitBranch(MSucc); 649 return true; 650 } 651 652 // Conditional branches are not handed yet. 653 // Halt "fast" selection and bail. 654 return false; 655 } 656 657 case Instruction::Unreachable: 658 // Nothing to emit. 659 return true; 660 661 case Instruction::PHI: 662 // PHI nodes are already emitted. 663 return true; 664 665 case Instruction::Alloca: 666 // FunctionLowering has the static-sized case covered. 667 if (StaticAllocaMap.count(cast<AllocaInst>(I))) 668 return true; 669 670 // Dynamic-sized alloca is not handled yet. 671 return false; 672 673 case Instruction::Call: 674 return SelectCall(I); 675 676 case Instruction::BitCast: 677 return SelectBitCast(I); 678 679 case Instruction::FPToSI: 680 return SelectCast(I, ISD::FP_TO_SINT); 681 case Instruction::ZExt: 682 return SelectCast(I, ISD::ZERO_EXTEND); 683 case Instruction::SExt: 684 return SelectCast(I, ISD::SIGN_EXTEND); 685 case Instruction::Trunc: 686 return SelectCast(I, ISD::TRUNCATE); 687 case Instruction::SIToFP: 688 return SelectCast(I, ISD::SINT_TO_FP); 689 690 case Instruction::IntToPtr: // Deliberate fall-through. 691 case Instruction::PtrToInt: { 692 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 693 MVT DstVT = TLI.getValueType(I->getType()); 694 if (DstVT.bitsGT(SrcVT)) 695 return SelectCast(I, ISD::ZERO_EXTEND); 696 if (DstVT.bitsLT(SrcVT)) 697 return SelectCast(I, ISD::TRUNCATE); 698 unsigned Reg = getRegForValue(I->getOperand(0)); 699 if (Reg == 0) return false; 700 UpdateValueMap(I, Reg); 701 return true; 702 } 703 704 default: 705 // Unhandled instruction. Halt "fast" selection and bail. 706 return false; 707 } 708} 709 710FastISel::FastISel(MachineFunction &mf, 711 MachineModuleInfo *mmi, 712 DwarfWriter *dw, 713 DenseMap<const Value *, unsigned> &vm, 714 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm, 715 DenseMap<const AllocaInst *, int> &am 716#ifndef NDEBUG 717 , SmallSet<Instruction*, 8> &cil 718#endif 719 ) 720 : MBB(0), 721 ValueMap(vm), 722 MBBMap(bm), 723 StaticAllocaMap(am), 724#ifndef NDEBUG 725 CatchInfoLost(cil), 726#endif 727 MF(mf), 728 MMI(mmi), 729 DW(dw), 730 MRI(MF.getRegInfo()), 731 MFI(*MF.getFrameInfo()), 732 MCP(*MF.getConstantPool()), 733 TM(MF.getTarget()), 734 TD(*TM.getTargetData()), 735 TII(*TM.getInstrInfo()), 736 TLI(*TM.getTargetLowering()) { 737} 738 739FastISel::~FastISel() {} 740 741unsigned FastISel::FastEmit_(MVT::SimpleValueType, MVT::SimpleValueType, 742 ISD::NodeType) { 743 return 0; 744} 745 746unsigned FastISel::FastEmit_r(MVT::SimpleValueType, MVT::SimpleValueType, 747 ISD::NodeType, unsigned /*Op0*/) { 748 return 0; 749} 750 751unsigned FastISel::FastEmit_rr(MVT::SimpleValueType, MVT::SimpleValueType, 752 ISD::NodeType, unsigned /*Op0*/, 753 unsigned /*Op0*/) { 754 return 0; 755} 756 757unsigned FastISel::FastEmit_i(MVT::SimpleValueType, MVT::SimpleValueType, 758 ISD::NodeType, uint64_t /*Imm*/) { 759 return 0; 760} 761 762unsigned FastISel::FastEmit_f(MVT::SimpleValueType, MVT::SimpleValueType, 763 ISD::NodeType, ConstantFP * /*FPImm*/) { 764 return 0; 765} 766 767unsigned FastISel::FastEmit_ri(MVT::SimpleValueType, MVT::SimpleValueType, 768 ISD::NodeType, unsigned /*Op0*/, 769 uint64_t /*Imm*/) { 770 return 0; 771} 772 773unsigned FastISel::FastEmit_rf(MVT::SimpleValueType, MVT::SimpleValueType, 774 ISD::NodeType, unsigned /*Op0*/, 775 ConstantFP * /*FPImm*/) { 776 return 0; 777} 778 779unsigned FastISel::FastEmit_rri(MVT::SimpleValueType, MVT::SimpleValueType, 780 ISD::NodeType, 781 unsigned /*Op0*/, unsigned /*Op1*/, 782 uint64_t /*Imm*/) { 783 return 0; 784} 785 786/// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries 787/// to emit an instruction with an immediate operand using FastEmit_ri. 788/// If that fails, it materializes the immediate into a register and try 789/// FastEmit_rr instead. 790unsigned FastISel::FastEmit_ri_(MVT::SimpleValueType VT, ISD::NodeType Opcode, 791 unsigned Op0, uint64_t Imm, 792 MVT::SimpleValueType ImmType) { 793 // First check if immediate type is legal. If not, we can't use the ri form. 794 unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Imm); 795 if (ResultReg != 0) 796 return ResultReg; 797 unsigned MaterialReg = FastEmit_i(ImmType, ImmType, ISD::Constant, Imm); 798 if (MaterialReg == 0) 799 return 0; 800 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg); 801} 802 803/// FastEmit_rf_ - This method is a wrapper of FastEmit_ri. It first tries 804/// to emit an instruction with a floating-point immediate operand using 805/// FastEmit_rf. If that fails, it materializes the immediate into a register 806/// and try FastEmit_rr instead. 807unsigned FastISel::FastEmit_rf_(MVT::SimpleValueType VT, ISD::NodeType Opcode, 808 unsigned Op0, ConstantFP *FPImm, 809 MVT::SimpleValueType ImmType) { 810 // First check if immediate type is legal. If not, we can't use the rf form. 811 unsigned ResultReg = FastEmit_rf(VT, VT, Opcode, Op0, FPImm); 812 if (ResultReg != 0) 813 return ResultReg; 814 815 // Materialize the constant in a register. 816 unsigned MaterialReg = FastEmit_f(ImmType, ImmType, ISD::ConstantFP, FPImm); 817 if (MaterialReg == 0) { 818 // If the target doesn't have a way to directly enter a floating-point 819 // value into a register, use an alternate approach. 820 // TODO: The current approach only supports floating-point constants 821 // that can be constructed by conversion from integer values. This should 822 // be replaced by code that creates a load from a constant-pool entry, 823 // which will require some target-specific work. 824 const APFloat &Flt = FPImm->getValueAPF(); 825 MVT IntVT = TLI.getPointerTy(); 826 827 uint64_t x[2]; 828 uint32_t IntBitWidth = IntVT.getSizeInBits(); 829 bool isExact; 830 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true, 831 APFloat::rmTowardZero, &isExact); 832 if (!isExact) 833 return 0; 834 APInt IntVal(IntBitWidth, 2, x); 835 836 unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(), 837 ISD::Constant, IntVal.getZExtValue()); 838 if (IntegerReg == 0) 839 return 0; 840 MaterialReg = FastEmit_r(IntVT.getSimpleVT(), VT, 841 ISD::SINT_TO_FP, IntegerReg); 842 if (MaterialReg == 0) 843 return 0; 844 } 845 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg); 846} 847 848unsigned FastISel::createResultReg(const TargetRegisterClass* RC) { 849 return MRI.createVirtualRegister(RC); 850} 851 852unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode, 853 const TargetRegisterClass* RC) { 854 unsigned ResultReg = createResultReg(RC); 855 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 856 857 BuildMI(MBB, DL, II, ResultReg); 858 return ResultReg; 859} 860 861unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode, 862 const TargetRegisterClass *RC, 863 unsigned Op0) { 864 unsigned ResultReg = createResultReg(RC); 865 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 866 867 if (II.getNumDefs() >= 1) 868 BuildMI(MBB, DL, II, ResultReg).addReg(Op0); 869 else { 870 BuildMI(MBB, DL, II).addReg(Op0); 871 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 872 II.ImplicitDefs[0], RC, RC); 873 if (!InsertedCopy) 874 ResultReg = 0; 875 } 876 877 return ResultReg; 878} 879 880unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode, 881 const TargetRegisterClass *RC, 882 unsigned Op0, unsigned Op1) { 883 unsigned ResultReg = createResultReg(RC); 884 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 885 886 if (II.getNumDefs() >= 1) 887 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addReg(Op1); 888 else { 889 BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1); 890 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 891 II.ImplicitDefs[0], RC, RC); 892 if (!InsertedCopy) 893 ResultReg = 0; 894 } 895 return ResultReg; 896} 897 898unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode, 899 const TargetRegisterClass *RC, 900 unsigned Op0, uint64_t Imm) { 901 unsigned ResultReg = createResultReg(RC); 902 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 903 904 if (II.getNumDefs() >= 1) 905 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addImm(Imm); 906 else { 907 BuildMI(MBB, DL, II).addReg(Op0).addImm(Imm); 908 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 909 II.ImplicitDefs[0], RC, RC); 910 if (!InsertedCopy) 911 ResultReg = 0; 912 } 913 return ResultReg; 914} 915 916unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode, 917 const TargetRegisterClass *RC, 918 unsigned Op0, ConstantFP *FPImm) { 919 unsigned ResultReg = createResultReg(RC); 920 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 921 922 if (II.getNumDefs() >= 1) 923 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addFPImm(FPImm); 924 else { 925 BuildMI(MBB, DL, II).addReg(Op0).addFPImm(FPImm); 926 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 927 II.ImplicitDefs[0], RC, RC); 928 if (!InsertedCopy) 929 ResultReg = 0; 930 } 931 return ResultReg; 932} 933 934unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode, 935 const TargetRegisterClass *RC, 936 unsigned Op0, unsigned Op1, uint64_t Imm) { 937 unsigned ResultReg = createResultReg(RC); 938 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 939 940 if (II.getNumDefs() >= 1) 941 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addReg(Op1).addImm(Imm); 942 else { 943 BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1).addImm(Imm); 944 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 945 II.ImplicitDefs[0], RC, RC); 946 if (!InsertedCopy) 947 ResultReg = 0; 948 } 949 return ResultReg; 950} 951 952unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode, 953 const TargetRegisterClass *RC, 954 uint64_t Imm) { 955 unsigned ResultReg = createResultReg(RC); 956 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 957 958 if (II.getNumDefs() >= 1) 959 BuildMI(MBB, DL, II, ResultReg).addImm(Imm); 960 else { 961 BuildMI(MBB, DL, II).addImm(Imm); 962 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 963 II.ImplicitDefs[0], RC, RC); 964 if (!InsertedCopy) 965 ResultReg = 0; 966 } 967 return ResultReg; 968} 969 970unsigned FastISel::FastEmitInst_extractsubreg(MVT::SimpleValueType RetVT, 971 unsigned Op0, uint32_t Idx) { 972 const TargetRegisterClass* RC = MRI.getRegClass(Op0); 973 974 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT)); 975 const TargetInstrDesc &II = TII.get(TargetInstrInfo::EXTRACT_SUBREG); 976 977 if (II.getNumDefs() >= 1) 978 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addImm(Idx); 979 else { 980 BuildMI(MBB, DL, II).addReg(Op0).addImm(Idx); 981 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 982 II.ImplicitDefs[0], RC, RC); 983 if (!InsertedCopy) 984 ResultReg = 0; 985 } 986 return ResultReg; 987} 988 989/// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op 990/// with all but the least significant bit set to zero. 991unsigned FastISel::FastEmitZExtFromI1(MVT::SimpleValueType VT, unsigned Op) { 992 return FastEmit_ri(VT, VT, ISD::AND, Op, 1); 993} 994