FastISel.cpp revision bf0ca2b477e761e2c81f6c36d6c7bec055933b15
1///===-- FastISel.cpp - Implementation of the FastISel class --------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the implementation of the FastISel class. 11// 12// "Fast" instruction selection is designed to emit very poor code quickly. 13// Also, it is not designed to be able to do much lowering, so most illegal 14// types (e.g. i64 on 32-bit targets) and operations are not supported. It is 15// also not intended to be able to do much optimization, except in a few cases 16// where doing optimizations reduces overall compile time. For example, folding 17// constants into immediate fields is often done, because it's cheap and it 18// reduces the number of instructions later phases have to examine. 19// 20// "Fast" instruction selection is able to fail gracefully and transfer 21// control to the SelectionDAG selector for operations that it doesn't 22// support. In many cases, this allows us to avoid duplicating a lot of 23// the complicated lowering logic that SelectionDAG currently has. 24// 25// The intended use for "fast" instruction selection is "-O0" mode 26// compilation, where the quality of the generated code is irrelevant when 27// weighed against the speed at which the code can be generated. Also, 28// at -O0, the LLVM optimizers are not running, and this makes the 29// compile time of codegen a much higher portion of the overall compile 30// time. Despite its limitations, "fast" instruction selection is able to 31// handle enough code on its own to provide noticeable overall speedups 32// in -O0 compiles. 33// 34// Basic operations are supported in a target-independent way, by reading 35// the same instruction descriptions that the SelectionDAG selector reads, 36// and identifying simple arithmetic operations that can be directly selected 37// from simple operators. More complicated operations currently require 38// target-specific code. 39// 40//===----------------------------------------------------------------------===// 41 42#include "llvm/Function.h" 43#include "llvm/GlobalVariable.h" 44#include "llvm/Instructions.h" 45#include "llvm/IntrinsicInst.h" 46#include "llvm/CodeGen/FastISel.h" 47#include "llvm/CodeGen/MachineInstrBuilder.h" 48#include "llvm/CodeGen/MachineModuleInfo.h" 49#include "llvm/CodeGen/MachineRegisterInfo.h" 50#include "llvm/CodeGen/DwarfWriter.h" 51#include "llvm/Analysis/DebugInfo.h" 52#include "llvm/Target/TargetData.h" 53#include "llvm/Target/TargetInstrInfo.h" 54#include "llvm/Target/TargetLowering.h" 55#include "llvm/Target/TargetMachine.h" 56#include "SelectionDAGBuilder.h" 57#include "FunctionLoweringInfo.h" 58using namespace llvm; 59 60unsigned FastISel::getRegForValue(Value *V) { 61 EVT RealVT = TLI.getValueType(V->getType(), /*AllowUnknown=*/true); 62 // Don't handle non-simple values in FastISel. 63 if (!RealVT.isSimple()) 64 return 0; 65 66 // Ignore illegal types. We must do this before looking up the value 67 // in ValueMap because Arguments are given virtual registers regardless 68 // of whether FastISel can handle them. 69 MVT VT = RealVT.getSimpleVT(); 70 if (!TLI.isTypeLegal(VT)) { 71 // Promote MVT::i1 to a legal type though, because it's common and easy. 72 if (VT == MVT::i1) 73 VT = TLI.getTypeToTransformTo(V->getContext(), VT).getSimpleVT(); 74 else 75 return 0; 76 } 77 78 // Look up the value to see if we already have a register for it. We 79 // cache values defined by Instructions across blocks, and other values 80 // only locally. This is because Instructions already have the SSA 81 // def-dominatess-use requirement enforced. 82 if (ValueMap.count(V)) 83 return ValueMap[V]; 84 unsigned Reg = LocalValueMap[V]; 85 if (Reg != 0) 86 return Reg; 87 88 if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) { 89 if (CI->getValue().getActiveBits() <= 64) 90 Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue()); 91 } else if (isa<AllocaInst>(V)) { 92 Reg = TargetMaterializeAlloca(cast<AllocaInst>(V)); 93 } else if (isa<ConstantPointerNull>(V)) { 94 // Translate this as an integer zero so that it can be 95 // local-CSE'd with actual integer zeros. 96 Reg = 97 getRegForValue(Constant::getNullValue(TD.getIntPtrType(V->getContext()))); 98 } else if (ConstantFP *CF = dyn_cast<ConstantFP>(V)) { 99 Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF); 100 101 if (!Reg) { 102 const APFloat &Flt = CF->getValueAPF(); 103 EVT IntVT = TLI.getPointerTy(); 104 105 uint64_t x[2]; 106 uint32_t IntBitWidth = IntVT.getSizeInBits(); 107 bool isExact; 108 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true, 109 APFloat::rmTowardZero, &isExact); 110 if (isExact) { 111 APInt IntVal(IntBitWidth, 2, x); 112 113 unsigned IntegerReg = 114 getRegForValue(ConstantInt::get(V->getContext(), IntVal)); 115 if (IntegerReg != 0) 116 Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg); 117 } 118 } 119 } else if (ConstantExpr *CE = dyn_cast<ConstantExpr>(V)) { 120 if (!SelectOperator(CE, CE->getOpcode())) return 0; 121 Reg = LocalValueMap[CE]; 122 } else if (isa<UndefValue>(V)) { 123 Reg = createResultReg(TLI.getRegClassFor(VT)); 124 BuildMI(MBB, DL, TII.get(TargetInstrInfo::IMPLICIT_DEF), Reg); 125 } 126 127 // If target-independent code couldn't handle the value, give target-specific 128 // code a try. 129 if (!Reg && isa<Constant>(V)) 130 Reg = TargetMaterializeConstant(cast<Constant>(V)); 131 132 // Don't cache constant materializations in the general ValueMap. 133 // To do so would require tracking what uses they dominate. 134 if (Reg != 0) 135 LocalValueMap[V] = Reg; 136 return Reg; 137} 138 139unsigned FastISel::lookUpRegForValue(Value *V) { 140 // Look up the value to see if we already have a register for it. We 141 // cache values defined by Instructions across blocks, and other values 142 // only locally. This is because Instructions already have the SSA 143 // def-dominatess-use requirement enforced. 144 if (ValueMap.count(V)) 145 return ValueMap[V]; 146 return LocalValueMap[V]; 147} 148 149/// UpdateValueMap - Update the value map to include the new mapping for this 150/// instruction, or insert an extra copy to get the result in a previous 151/// determined register. 152/// NOTE: This is only necessary because we might select a block that uses 153/// a value before we select the block that defines the value. It might be 154/// possible to fix this by selecting blocks in reverse postorder. 155unsigned FastISel::UpdateValueMap(Value* I, unsigned Reg) { 156 if (!isa<Instruction>(I)) { 157 LocalValueMap[I] = Reg; 158 return Reg; 159 } 160 161 unsigned &AssignedReg = ValueMap[I]; 162 if (AssignedReg == 0) 163 AssignedReg = Reg; 164 else if (Reg != AssignedReg) { 165 const TargetRegisterClass *RegClass = MRI.getRegClass(Reg); 166 TII.copyRegToReg(*MBB, MBB->end(), AssignedReg, 167 Reg, RegClass, RegClass); 168 } 169 return AssignedReg; 170} 171 172unsigned FastISel::getRegForGEPIndex(Value *Idx) { 173 unsigned IdxN = getRegForValue(Idx); 174 if (IdxN == 0) 175 // Unhandled operand. Halt "fast" selection and bail. 176 return 0; 177 178 // If the index is smaller or larger than intptr_t, truncate or extend it. 179 MVT PtrVT = TLI.getPointerTy(); 180 EVT IdxVT = EVT::getEVT(Idx->getType(), /*HandleUnknown=*/false); 181 if (IdxVT.bitsLT(PtrVT)) 182 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::SIGN_EXTEND, IdxN); 183 else if (IdxVT.bitsGT(PtrVT)) 184 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::TRUNCATE, IdxN); 185 return IdxN; 186} 187 188/// SelectBinaryOp - Select and emit code for a binary operator instruction, 189/// which has an opcode which directly corresponds to the given ISD opcode. 190/// 191bool FastISel::SelectBinaryOp(User *I, ISD::NodeType ISDOpcode) { 192 EVT VT = EVT::getEVT(I->getType(), /*HandleUnknown=*/true); 193 if (VT == MVT::Other || !VT.isSimple()) 194 // Unhandled type. Halt "fast" selection and bail. 195 return false; 196 197 // We only handle legal types. For example, on x86-32 the instruction 198 // selector contains all of the 64-bit instructions from x86-64, 199 // under the assumption that i64 won't be used if the target doesn't 200 // support it. 201 if (!TLI.isTypeLegal(VT)) { 202 // MVT::i1 is special. Allow AND, OR, or XOR because they 203 // don't require additional zeroing, which makes them easy. 204 if (VT == MVT::i1 && 205 (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR || 206 ISDOpcode == ISD::XOR)) 207 VT = TLI.getTypeToTransformTo(I->getContext(), VT); 208 else 209 return false; 210 } 211 212 unsigned Op0 = getRegForValue(I->getOperand(0)); 213 if (Op0 == 0) 214 // Unhandled operand. Halt "fast" selection and bail. 215 return false; 216 217 // Check if the second operand is a constant and handle it appropriately. 218 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) { 219 unsigned ResultReg = FastEmit_ri(VT.getSimpleVT(), VT.getSimpleVT(), 220 ISDOpcode, Op0, CI->getZExtValue()); 221 if (ResultReg != 0) { 222 // We successfully emitted code for the given LLVM Instruction. 223 UpdateValueMap(I, ResultReg); 224 return true; 225 } 226 } 227 228 // Check if the second operand is a constant float. 229 if (ConstantFP *CF = dyn_cast<ConstantFP>(I->getOperand(1))) { 230 unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(), 231 ISDOpcode, Op0, CF); 232 if (ResultReg != 0) { 233 // We successfully emitted code for the given LLVM Instruction. 234 UpdateValueMap(I, ResultReg); 235 return true; 236 } 237 } 238 239 unsigned Op1 = getRegForValue(I->getOperand(1)); 240 if (Op1 == 0) 241 // Unhandled operand. Halt "fast" selection and bail. 242 return false; 243 244 // Now we have both operands in registers. Emit the instruction. 245 unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(), 246 ISDOpcode, Op0, Op1); 247 if (ResultReg == 0) 248 // Target-specific code wasn't able to find a machine opcode for 249 // the given ISD opcode and type. Halt "fast" selection and bail. 250 return false; 251 252 // We successfully emitted code for the given LLVM Instruction. 253 UpdateValueMap(I, ResultReg); 254 return true; 255} 256 257bool FastISel::SelectGetElementPtr(User *I) { 258 unsigned N = getRegForValue(I->getOperand(0)); 259 if (N == 0) 260 // Unhandled operand. Halt "fast" selection and bail. 261 return false; 262 263 const Type *Ty = I->getOperand(0)->getType(); 264 MVT VT = TLI.getPointerTy(); 265 for (GetElementPtrInst::op_iterator OI = I->op_begin()+1, E = I->op_end(); 266 OI != E; ++OI) { 267 Value *Idx = *OI; 268 if (const StructType *StTy = dyn_cast<StructType>(Ty)) { 269 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 270 if (Field) { 271 // N = N + Offset 272 uint64_t Offs = TD.getStructLayout(StTy)->getElementOffset(Field); 273 // FIXME: This can be optimized by combining the add with a 274 // subsequent one. 275 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT); 276 if (N == 0) 277 // Unhandled operand. Halt "fast" selection and bail. 278 return false; 279 } 280 Ty = StTy->getElementType(Field); 281 } else { 282 Ty = cast<SequentialType>(Ty)->getElementType(); 283 284 // If this is a constant subscript, handle it quickly. 285 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 286 if (CI->getZExtValue() == 0) continue; 287 uint64_t Offs = 288 TD.getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 289 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT); 290 if (N == 0) 291 // Unhandled operand. Halt "fast" selection and bail. 292 return false; 293 continue; 294 } 295 296 // N = N + Idx * ElementSize; 297 uint64_t ElementSize = TD.getTypeAllocSize(Ty); 298 unsigned IdxN = getRegForGEPIndex(Idx); 299 if (IdxN == 0) 300 // Unhandled operand. Halt "fast" selection and bail. 301 return false; 302 303 if (ElementSize != 1) { 304 IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, ElementSize, VT); 305 if (IdxN == 0) 306 // Unhandled operand. Halt "fast" selection and bail. 307 return false; 308 } 309 N = FastEmit_rr(VT, VT, ISD::ADD, N, IdxN); 310 if (N == 0) 311 // Unhandled operand. Halt "fast" selection and bail. 312 return false; 313 } 314 } 315 316 // We successfully emitted code for the given LLVM Instruction. 317 UpdateValueMap(I, N); 318 return true; 319} 320 321bool FastISel::SelectCall(User *I) { 322 Function *F = cast<CallInst>(I)->getCalledFunction(); 323 if (!F) return false; 324 325 unsigned IID = F->getIntrinsicID(); 326 switch (IID) { 327 default: break; 328 case Intrinsic::dbg_stoppoint: 329 case Intrinsic::dbg_region_start: 330 case Intrinsic::dbg_region_end: 331 case Intrinsic::dbg_func_start: 332 // FIXME - Remove this instructions once the dust settles. 333 return true; 334 case Intrinsic::dbg_declare: { 335 DbgDeclareInst *DI = cast<DbgDeclareInst>(I); 336 if (!DIDescriptor::ValidDebugInfo(DI->getVariable(), CodeGenOpt::None)||!DW 337 || !DW->ShouldEmitDwarfDebug()) 338 return true; 339 340 Value *Address = DI->getAddress(); 341 if (BitCastInst *BCI = dyn_cast<BitCastInst>(Address)) 342 Address = BCI->getOperand(0); 343 AllocaInst *AI = dyn_cast<AllocaInst>(Address); 344 // Don't handle byval struct arguments or VLAs, for example. 345 if (!AI) break; 346 DenseMap<const AllocaInst*, int>::iterator SI = 347 StaticAllocaMap.find(AI); 348 if (SI == StaticAllocaMap.end()) break; // VLAs. 349 int FI = SI->second; 350 if (MMI) { 351 if (MDNode *Dbg = DI->getMetadata("dbg")) 352 MMI->setVariableDbgInfo(DI->getVariable(), FI, Dbg); 353 } 354 return true; 355 } 356 case Intrinsic::eh_exception: { 357 EVT VT = TLI.getValueType(I->getType()); 358 switch (TLI.getOperationAction(ISD::EXCEPTIONADDR, VT)) { 359 default: break; 360 case TargetLowering::Expand: { 361 assert(MBB->isLandingPad() && "Call to eh.exception not in landing pad!"); 362 unsigned Reg = TLI.getExceptionAddressRegister(); 363 const TargetRegisterClass *RC = TLI.getRegClassFor(VT); 364 unsigned ResultReg = createResultReg(RC); 365 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 366 Reg, RC, RC); 367 assert(InsertedCopy && "Can't copy address registers!"); 368 InsertedCopy = InsertedCopy; 369 UpdateValueMap(I, ResultReg); 370 return true; 371 } 372 } 373 break; 374 } 375 case Intrinsic::eh_selector: { 376 EVT VT = TLI.getValueType(I->getType()); 377 switch (TLI.getOperationAction(ISD::EHSELECTION, VT)) { 378 default: break; 379 case TargetLowering::Expand: { 380 if (MMI) { 381 if (MBB->isLandingPad()) 382 AddCatchInfo(*cast<CallInst>(I), MMI, MBB); 383 else { 384#ifndef NDEBUG 385 CatchInfoLost.insert(cast<CallInst>(I)); 386#endif 387 // FIXME: Mark exception selector register as live in. Hack for PR1508. 388 unsigned Reg = TLI.getExceptionSelectorRegister(); 389 if (Reg) MBB->addLiveIn(Reg); 390 } 391 392 unsigned Reg = TLI.getExceptionSelectorRegister(); 393 EVT SrcVT = TLI.getPointerTy(); 394 const TargetRegisterClass *RC = TLI.getRegClassFor(SrcVT); 395 unsigned ResultReg = createResultReg(RC); 396 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, Reg, 397 RC, RC); 398 assert(InsertedCopy && "Can't copy address registers!"); 399 InsertedCopy = InsertedCopy; 400 401 // Cast the register to the type of the selector. 402 if (SrcVT.bitsGT(MVT::i32)) 403 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), MVT::i32, ISD::TRUNCATE, 404 ResultReg); 405 else if (SrcVT.bitsLT(MVT::i32)) 406 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), MVT::i32, 407 ISD::SIGN_EXTEND, ResultReg); 408 if (ResultReg == 0) 409 // Unhandled operand. Halt "fast" selection and bail. 410 return false; 411 412 UpdateValueMap(I, ResultReg); 413 } else { 414 unsigned ResultReg = 415 getRegForValue(Constant::getNullValue(I->getType())); 416 UpdateValueMap(I, ResultReg); 417 } 418 return true; 419 } 420 } 421 break; 422 } 423 } 424 return false; 425} 426 427bool FastISel::SelectCast(User *I, ISD::NodeType Opcode) { 428 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 429 EVT DstVT = TLI.getValueType(I->getType()); 430 431 if (SrcVT == MVT::Other || !SrcVT.isSimple() || 432 DstVT == MVT::Other || !DstVT.isSimple()) 433 // Unhandled type. Halt "fast" selection and bail. 434 return false; 435 436 // Check if the destination type is legal. Or as a special case, 437 // it may be i1 if we're doing a truncate because that's 438 // easy and somewhat common. 439 if (!TLI.isTypeLegal(DstVT)) 440 if (DstVT != MVT::i1 || Opcode != ISD::TRUNCATE) 441 // Unhandled type. Halt "fast" selection and bail. 442 return false; 443 444 // Check if the source operand is legal. Or as a special case, 445 // it may be i1 if we're doing zero-extension because that's 446 // easy and somewhat common. 447 if (!TLI.isTypeLegal(SrcVT)) 448 if (SrcVT != MVT::i1 || Opcode != ISD::ZERO_EXTEND) 449 // Unhandled type. Halt "fast" selection and bail. 450 return false; 451 452 unsigned InputReg = getRegForValue(I->getOperand(0)); 453 if (!InputReg) 454 // Unhandled operand. Halt "fast" selection and bail. 455 return false; 456 457 // If the operand is i1, arrange for the high bits in the register to be zero. 458 if (SrcVT == MVT::i1) { 459 SrcVT = TLI.getTypeToTransformTo(I->getContext(), SrcVT); 460 InputReg = FastEmitZExtFromI1(SrcVT.getSimpleVT(), InputReg); 461 if (!InputReg) 462 return false; 463 } 464 // If the result is i1, truncate to the target's type for i1 first. 465 if (DstVT == MVT::i1) 466 DstVT = TLI.getTypeToTransformTo(I->getContext(), DstVT); 467 468 unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(), 469 DstVT.getSimpleVT(), 470 Opcode, 471 InputReg); 472 if (!ResultReg) 473 return false; 474 475 UpdateValueMap(I, ResultReg); 476 return true; 477} 478 479bool FastISel::SelectBitCast(User *I) { 480 // If the bitcast doesn't change the type, just use the operand value. 481 if (I->getType() == I->getOperand(0)->getType()) { 482 unsigned Reg = getRegForValue(I->getOperand(0)); 483 if (Reg == 0) 484 return false; 485 UpdateValueMap(I, Reg); 486 return true; 487 } 488 489 // Bitcasts of other values become reg-reg copies or BIT_CONVERT operators. 490 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 491 EVT DstVT = TLI.getValueType(I->getType()); 492 493 if (SrcVT == MVT::Other || !SrcVT.isSimple() || 494 DstVT == MVT::Other || !DstVT.isSimple() || 495 !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT)) 496 // Unhandled type. Halt "fast" selection and bail. 497 return false; 498 499 unsigned Op0 = getRegForValue(I->getOperand(0)); 500 if (Op0 == 0) 501 // Unhandled operand. Halt "fast" selection and bail. 502 return false; 503 504 // First, try to perform the bitcast by inserting a reg-reg copy. 505 unsigned ResultReg = 0; 506 if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) { 507 TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT); 508 TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT); 509 ResultReg = createResultReg(DstClass); 510 511 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 512 Op0, DstClass, SrcClass); 513 if (!InsertedCopy) 514 ResultReg = 0; 515 } 516 517 // If the reg-reg copy failed, select a BIT_CONVERT opcode. 518 if (!ResultReg) 519 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), 520 ISD::BIT_CONVERT, Op0); 521 522 if (!ResultReg) 523 return false; 524 525 UpdateValueMap(I, ResultReg); 526 return true; 527} 528 529bool 530FastISel::SelectInstruction(Instruction *I) { 531 // First, try doing target-independent selection. 532 if (SelectOperator(I, I->getOpcode())) 533 return true; 534 535 // Next, try calling the target to attempt to handle the instruction. 536 if (TargetSelectInstruction(I)) 537 return true; 538 539 return false; 540} 541 542/// FastEmitBranch - Emit an unconditional branch to the given block, 543/// unless it is the immediate (fall-through) successor, and update 544/// the CFG. 545void 546FastISel::FastEmitBranch(MachineBasicBlock *MSucc) { 547 if (MBB->isLayoutSuccessor(MSucc)) { 548 // The unconditional fall-through case, which needs no instructions. 549 } else { 550 // The unconditional branch case. 551 TII.InsertBranch(*MBB, MSucc, NULL, SmallVector<MachineOperand, 0>()); 552 } 553 MBB->addSuccessor(MSucc); 554} 555 556/// SelectFNeg - Emit an FNeg operation. 557/// 558bool 559FastISel::SelectFNeg(User *I) { 560 unsigned OpReg = getRegForValue(BinaryOperator::getFNegArgument(I)); 561 if (OpReg == 0) return false; 562 563 // If the target has ISD::FNEG, use it. 564 EVT VT = TLI.getValueType(I->getType()); 565 unsigned ResultReg = FastEmit_r(VT.getSimpleVT(), VT.getSimpleVT(), 566 ISD::FNEG, OpReg); 567 if (ResultReg != 0) { 568 UpdateValueMap(I, ResultReg); 569 return true; 570 } 571 572 // Bitcast the value to integer, twiddle the sign bit with xor, 573 // and then bitcast it back to floating-point. 574 if (VT.getSizeInBits() > 64) return false; 575 EVT IntVT = EVT::getIntegerVT(I->getContext(), VT.getSizeInBits()); 576 if (!TLI.isTypeLegal(IntVT)) 577 return false; 578 579 unsigned IntReg = FastEmit_r(VT.getSimpleVT(), IntVT.getSimpleVT(), 580 ISD::BIT_CONVERT, OpReg); 581 if (IntReg == 0) 582 return false; 583 584 unsigned IntResultReg = FastEmit_ri_(IntVT.getSimpleVT(), ISD::XOR, IntReg, 585 UINT64_C(1) << (VT.getSizeInBits()-1), 586 IntVT.getSimpleVT()); 587 if (IntResultReg == 0) 588 return false; 589 590 ResultReg = FastEmit_r(IntVT.getSimpleVT(), VT.getSimpleVT(), 591 ISD::BIT_CONVERT, IntResultReg); 592 if (ResultReg == 0) 593 return false; 594 595 UpdateValueMap(I, ResultReg); 596 return true; 597} 598 599bool 600FastISel::SelectOperator(User *I, unsigned Opcode) { 601 switch (Opcode) { 602 case Instruction::Add: 603 return SelectBinaryOp(I, ISD::ADD); 604 case Instruction::FAdd: 605 return SelectBinaryOp(I, ISD::FADD); 606 case Instruction::Sub: 607 return SelectBinaryOp(I, ISD::SUB); 608 case Instruction::FSub: 609 // FNeg is currently represented in LLVM IR as a special case of FSub. 610 if (BinaryOperator::isFNeg(I)) 611 return SelectFNeg(I); 612 return SelectBinaryOp(I, ISD::FSUB); 613 case Instruction::Mul: 614 return SelectBinaryOp(I, ISD::MUL); 615 case Instruction::FMul: 616 return SelectBinaryOp(I, ISD::FMUL); 617 case Instruction::SDiv: 618 return SelectBinaryOp(I, ISD::SDIV); 619 case Instruction::UDiv: 620 return SelectBinaryOp(I, ISD::UDIV); 621 case Instruction::FDiv: 622 return SelectBinaryOp(I, ISD::FDIV); 623 case Instruction::SRem: 624 return SelectBinaryOp(I, ISD::SREM); 625 case Instruction::URem: 626 return SelectBinaryOp(I, ISD::UREM); 627 case Instruction::FRem: 628 return SelectBinaryOp(I, ISD::FREM); 629 case Instruction::Shl: 630 return SelectBinaryOp(I, ISD::SHL); 631 case Instruction::LShr: 632 return SelectBinaryOp(I, ISD::SRL); 633 case Instruction::AShr: 634 return SelectBinaryOp(I, ISD::SRA); 635 case Instruction::And: 636 return SelectBinaryOp(I, ISD::AND); 637 case Instruction::Or: 638 return SelectBinaryOp(I, ISD::OR); 639 case Instruction::Xor: 640 return SelectBinaryOp(I, ISD::XOR); 641 642 case Instruction::GetElementPtr: 643 return SelectGetElementPtr(I); 644 645 case Instruction::Br: { 646 BranchInst *BI = cast<BranchInst>(I); 647 648 if (BI->isUnconditional()) { 649 BasicBlock *LLVMSucc = BI->getSuccessor(0); 650 MachineBasicBlock *MSucc = MBBMap[LLVMSucc]; 651 FastEmitBranch(MSucc); 652 return true; 653 } 654 655 // Conditional branches are not handed yet. 656 // Halt "fast" selection and bail. 657 return false; 658 } 659 660 case Instruction::Unreachable: 661 // Nothing to emit. 662 return true; 663 664 case Instruction::PHI: 665 // PHI nodes are already emitted. 666 return true; 667 668 case Instruction::Alloca: 669 // FunctionLowering has the static-sized case covered. 670 if (StaticAllocaMap.count(cast<AllocaInst>(I))) 671 return true; 672 673 // Dynamic-sized alloca is not handled yet. 674 return false; 675 676 case Instruction::Call: 677 return SelectCall(I); 678 679 case Instruction::BitCast: 680 return SelectBitCast(I); 681 682 case Instruction::FPToSI: 683 return SelectCast(I, ISD::FP_TO_SINT); 684 case Instruction::ZExt: 685 return SelectCast(I, ISD::ZERO_EXTEND); 686 case Instruction::SExt: 687 return SelectCast(I, ISD::SIGN_EXTEND); 688 case Instruction::Trunc: 689 return SelectCast(I, ISD::TRUNCATE); 690 case Instruction::SIToFP: 691 return SelectCast(I, ISD::SINT_TO_FP); 692 693 case Instruction::IntToPtr: // Deliberate fall-through. 694 case Instruction::PtrToInt: { 695 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 696 EVT DstVT = TLI.getValueType(I->getType()); 697 if (DstVT.bitsGT(SrcVT)) 698 return SelectCast(I, ISD::ZERO_EXTEND); 699 if (DstVT.bitsLT(SrcVT)) 700 return SelectCast(I, ISD::TRUNCATE); 701 unsigned Reg = getRegForValue(I->getOperand(0)); 702 if (Reg == 0) return false; 703 UpdateValueMap(I, Reg); 704 return true; 705 } 706 707 default: 708 // Unhandled instruction. Halt "fast" selection and bail. 709 return false; 710 } 711} 712 713FastISel::FastISel(MachineFunction &mf, 714 MachineModuleInfo *mmi, 715 DwarfWriter *dw, 716 DenseMap<const Value *, unsigned> &vm, 717 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm, 718 DenseMap<const AllocaInst *, int> &am 719#ifndef NDEBUG 720 , SmallSet<Instruction*, 8> &cil 721#endif 722 ) 723 : MBB(0), 724 ValueMap(vm), 725 MBBMap(bm), 726 StaticAllocaMap(am), 727#ifndef NDEBUG 728 CatchInfoLost(cil), 729#endif 730 MF(mf), 731 MMI(mmi), 732 DW(dw), 733 MRI(MF.getRegInfo()), 734 MFI(*MF.getFrameInfo()), 735 MCP(*MF.getConstantPool()), 736 TM(MF.getTarget()), 737 TD(*TM.getTargetData()), 738 TII(*TM.getInstrInfo()), 739 TLI(*TM.getTargetLowering()) { 740} 741 742FastISel::~FastISel() {} 743 744unsigned FastISel::FastEmit_(MVT, MVT, 745 ISD::NodeType) { 746 return 0; 747} 748 749unsigned FastISel::FastEmit_r(MVT, MVT, 750 ISD::NodeType, unsigned /*Op0*/) { 751 return 0; 752} 753 754unsigned FastISel::FastEmit_rr(MVT, MVT, 755 ISD::NodeType, unsigned /*Op0*/, 756 unsigned /*Op0*/) { 757 return 0; 758} 759 760unsigned FastISel::FastEmit_i(MVT, MVT, ISD::NodeType, uint64_t /*Imm*/) { 761 return 0; 762} 763 764unsigned FastISel::FastEmit_f(MVT, MVT, 765 ISD::NodeType, ConstantFP * /*FPImm*/) { 766 return 0; 767} 768 769unsigned FastISel::FastEmit_ri(MVT, MVT, 770 ISD::NodeType, unsigned /*Op0*/, 771 uint64_t /*Imm*/) { 772 return 0; 773} 774 775unsigned FastISel::FastEmit_rf(MVT, MVT, 776 ISD::NodeType, unsigned /*Op0*/, 777 ConstantFP * /*FPImm*/) { 778 return 0; 779} 780 781unsigned FastISel::FastEmit_rri(MVT, MVT, 782 ISD::NodeType, 783 unsigned /*Op0*/, unsigned /*Op1*/, 784 uint64_t /*Imm*/) { 785 return 0; 786} 787 788/// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries 789/// to emit an instruction with an immediate operand using FastEmit_ri. 790/// If that fails, it materializes the immediate into a register and try 791/// FastEmit_rr instead. 792unsigned FastISel::FastEmit_ri_(MVT VT, ISD::NodeType Opcode, 793 unsigned Op0, uint64_t Imm, 794 MVT ImmType) { 795 // First check if immediate type is legal. If not, we can't use the ri form. 796 unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Imm); 797 if (ResultReg != 0) 798 return ResultReg; 799 unsigned MaterialReg = FastEmit_i(ImmType, ImmType, ISD::Constant, Imm); 800 if (MaterialReg == 0) 801 return 0; 802 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg); 803} 804 805/// FastEmit_rf_ - This method is a wrapper of FastEmit_ri. It first tries 806/// to emit an instruction with a floating-point immediate operand using 807/// FastEmit_rf. If that fails, it materializes the immediate into a register 808/// and try FastEmit_rr instead. 809unsigned FastISel::FastEmit_rf_(MVT VT, ISD::NodeType Opcode, 810 unsigned Op0, ConstantFP *FPImm, 811 MVT ImmType) { 812 // First check if immediate type is legal. If not, we can't use the rf form. 813 unsigned ResultReg = FastEmit_rf(VT, VT, Opcode, Op0, FPImm); 814 if (ResultReg != 0) 815 return ResultReg; 816 817 // Materialize the constant in a register. 818 unsigned MaterialReg = FastEmit_f(ImmType, ImmType, ISD::ConstantFP, FPImm); 819 if (MaterialReg == 0) { 820 // If the target doesn't have a way to directly enter a floating-point 821 // value into a register, use an alternate approach. 822 // TODO: The current approach only supports floating-point constants 823 // that can be constructed by conversion from integer values. This should 824 // be replaced by code that creates a load from a constant-pool entry, 825 // which will require some target-specific work. 826 const APFloat &Flt = FPImm->getValueAPF(); 827 EVT IntVT = TLI.getPointerTy(); 828 829 uint64_t x[2]; 830 uint32_t IntBitWidth = IntVT.getSizeInBits(); 831 bool isExact; 832 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true, 833 APFloat::rmTowardZero, &isExact); 834 if (!isExact) 835 return 0; 836 APInt IntVal(IntBitWidth, 2, x); 837 838 unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(), 839 ISD::Constant, IntVal.getZExtValue()); 840 if (IntegerReg == 0) 841 return 0; 842 MaterialReg = FastEmit_r(IntVT.getSimpleVT(), VT, 843 ISD::SINT_TO_FP, IntegerReg); 844 if (MaterialReg == 0) 845 return 0; 846 } 847 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg); 848} 849 850unsigned FastISel::createResultReg(const TargetRegisterClass* RC) { 851 return MRI.createVirtualRegister(RC); 852} 853 854unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode, 855 const TargetRegisterClass* RC) { 856 unsigned ResultReg = createResultReg(RC); 857 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 858 859 BuildMI(MBB, DL, II, ResultReg); 860 return ResultReg; 861} 862 863unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode, 864 const TargetRegisterClass *RC, 865 unsigned Op0) { 866 unsigned ResultReg = createResultReg(RC); 867 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 868 869 if (II.getNumDefs() >= 1) 870 BuildMI(MBB, DL, II, ResultReg).addReg(Op0); 871 else { 872 BuildMI(MBB, DL, II).addReg(Op0); 873 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 874 II.ImplicitDefs[0], RC, RC); 875 if (!InsertedCopy) 876 ResultReg = 0; 877 } 878 879 return ResultReg; 880} 881 882unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode, 883 const TargetRegisterClass *RC, 884 unsigned Op0, unsigned Op1) { 885 unsigned ResultReg = createResultReg(RC); 886 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 887 888 if (II.getNumDefs() >= 1) 889 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addReg(Op1); 890 else { 891 BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1); 892 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 893 II.ImplicitDefs[0], RC, RC); 894 if (!InsertedCopy) 895 ResultReg = 0; 896 } 897 return ResultReg; 898} 899 900unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode, 901 const TargetRegisterClass *RC, 902 unsigned Op0, uint64_t Imm) { 903 unsigned ResultReg = createResultReg(RC); 904 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 905 906 if (II.getNumDefs() >= 1) 907 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addImm(Imm); 908 else { 909 BuildMI(MBB, DL, II).addReg(Op0).addImm(Imm); 910 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 911 II.ImplicitDefs[0], RC, RC); 912 if (!InsertedCopy) 913 ResultReg = 0; 914 } 915 return ResultReg; 916} 917 918unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode, 919 const TargetRegisterClass *RC, 920 unsigned Op0, ConstantFP *FPImm) { 921 unsigned ResultReg = createResultReg(RC); 922 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 923 924 if (II.getNumDefs() >= 1) 925 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addFPImm(FPImm); 926 else { 927 BuildMI(MBB, DL, II).addReg(Op0).addFPImm(FPImm); 928 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 929 II.ImplicitDefs[0], RC, RC); 930 if (!InsertedCopy) 931 ResultReg = 0; 932 } 933 return ResultReg; 934} 935 936unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode, 937 const TargetRegisterClass *RC, 938 unsigned Op0, unsigned Op1, uint64_t Imm) { 939 unsigned ResultReg = createResultReg(RC); 940 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 941 942 if (II.getNumDefs() >= 1) 943 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addReg(Op1).addImm(Imm); 944 else { 945 BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1).addImm(Imm); 946 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 947 II.ImplicitDefs[0], RC, RC); 948 if (!InsertedCopy) 949 ResultReg = 0; 950 } 951 return ResultReg; 952} 953 954unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode, 955 const TargetRegisterClass *RC, 956 uint64_t Imm) { 957 unsigned ResultReg = createResultReg(RC); 958 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 959 960 if (II.getNumDefs() >= 1) 961 BuildMI(MBB, DL, II, ResultReg).addImm(Imm); 962 else { 963 BuildMI(MBB, DL, II).addImm(Imm); 964 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 965 II.ImplicitDefs[0], RC, RC); 966 if (!InsertedCopy) 967 ResultReg = 0; 968 } 969 return ResultReg; 970} 971 972unsigned FastISel::FastEmitInst_extractsubreg(MVT RetVT, 973 unsigned Op0, uint32_t Idx) { 974 const TargetRegisterClass* RC = MRI.getRegClass(Op0); 975 976 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT)); 977 const TargetInstrDesc &II = TII.get(TargetInstrInfo::EXTRACT_SUBREG); 978 979 if (II.getNumDefs() >= 1) 980 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addImm(Idx); 981 else { 982 BuildMI(MBB, DL, II).addReg(Op0).addImm(Idx); 983 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 984 II.ImplicitDefs[0], RC, RC); 985 if (!InsertedCopy) 986 ResultReg = 0; 987 } 988 return ResultReg; 989} 990 991/// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op 992/// with all but the least significant bit set to zero. 993unsigned FastISel::FastEmitZExtFromI1(MVT VT, unsigned Op) { 994 return FastEmit_ri(VT, VT, ISD::AND, Op, 1); 995} 996