LegalizeVectorTypes.cpp revision b05e4778f0871cbb02f61e4d55ad7375738a1d01
1//===------- LegalizeVectorTypes.cpp - Legalization of vector types -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file performs vector type splitting and scalarization for LegalizeTypes. 11// Scalarization is the act of changing a computation in an illegal one-element 12// vector type to be a computation in its scalar element type. For example, 13// implementing <1 x f32> arithmetic in a scalar f32 register. This is needed 14// as a base case when scalarizing vector arithmetic like <4 x f32>, which 15// eventually decomposes to scalars if the target doesn't support v4f32 or v2f32 16// types. 17// Splitting is the act of changing a computation in an invalid vector type to 18// be a computation in two vectors of half the size. For example, implementing 19// <128 x f32> operations in terms of two <64 x f32> operations. 20// 21//===----------------------------------------------------------------------===// 22 23#include "LegalizeTypes.h" 24#include "llvm/IR/DataLayout.h" 25#include "llvm/Support/ErrorHandling.h" 26#include "llvm/Support/raw_ostream.h" 27using namespace llvm; 28 29//===----------------------------------------------------------------------===// 30// Result Vector Scalarization: <1 x ty> -> ty. 31//===----------------------------------------------------------------------===// 32 33void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) { 34 DEBUG(dbgs() << "Scalarize node result " << ResNo << ": "; 35 N->dump(&DAG); 36 dbgs() << "\n"); 37 SDValue R = SDValue(); 38 39 switch (N->getOpcode()) { 40 default: 41#ifndef NDEBUG 42 dbgs() << "ScalarizeVectorResult #" << ResNo << ": "; 43 N->dump(&DAG); 44 dbgs() << "\n"; 45#endif 46 report_fatal_error("Do not know how to scalarize the result of this " 47 "operator!\n"); 48 49 case ISD::MERGE_VALUES: R = ScalarizeVecRes_MERGE_VALUES(N, ResNo);break; 50 case ISD::BITCAST: R = ScalarizeVecRes_BITCAST(N); break; 51 case ISD::BUILD_VECTOR: R = ScalarizeVecRes_BUILD_VECTOR(N); break; 52 case ISD::CONVERT_RNDSAT: R = ScalarizeVecRes_CONVERT_RNDSAT(N); break; 53 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break; 54 case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break; 55 case ISD::FP_ROUND_INREG: R = ScalarizeVecRes_InregOp(N); break; 56 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break; 57 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break; 58 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break; 59 case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break; 60 case ISD::SIGN_EXTEND_INREG: R = ScalarizeVecRes_InregOp(N); break; 61 case ISD::VSELECT: R = ScalarizeVecRes_VSELECT(N); break; 62 case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break; 63 case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break; 64 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break; 65 case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break; 66 case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break; 67 case ISD::ANY_EXTEND: 68 case ISD::CTLZ: 69 case ISD::CTPOP: 70 case ISD::CTTZ: 71 case ISD::FABS: 72 case ISD::FCEIL: 73 case ISD::FCOS: 74 case ISD::FEXP: 75 case ISD::FEXP2: 76 case ISD::FFLOOR: 77 case ISD::FLOG: 78 case ISD::FLOG10: 79 case ISD::FLOG2: 80 case ISD::FNEARBYINT: 81 case ISD::FNEG: 82 case ISD::FP_EXTEND: 83 case ISD::FP_TO_SINT: 84 case ISD::FP_TO_UINT: 85 case ISD::FRINT: 86 case ISD::FSIN: 87 case ISD::FSQRT: 88 case ISD::FTRUNC: 89 case ISD::SIGN_EXTEND: 90 case ISD::SINT_TO_FP: 91 case ISD::TRUNCATE: 92 case ISD::UINT_TO_FP: 93 case ISD::ZERO_EXTEND: 94 R = ScalarizeVecRes_UnaryOp(N); 95 break; 96 97 case ISD::ADD: 98 case ISD::AND: 99 case ISD::FADD: 100 case ISD::FDIV: 101 case ISD::FMUL: 102 case ISD::FPOW: 103 case ISD::FREM: 104 case ISD::FSUB: 105 case ISD::MUL: 106 case ISD::OR: 107 case ISD::SDIV: 108 case ISD::SREM: 109 case ISD::SUB: 110 case ISD::UDIV: 111 case ISD::UREM: 112 case ISD::XOR: 113 case ISD::SHL: 114 case ISD::SRA: 115 case ISD::SRL: 116 R = ScalarizeVecRes_BinOp(N); 117 break; 118 case ISD::FMA: 119 R = ScalarizeVecRes_TernaryOp(N); 120 break; 121 } 122 123 // If R is null, the sub-method took care of registering the result. 124 if (R.getNode()) 125 SetScalarizedVector(SDValue(N, ResNo), R); 126} 127 128SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) { 129 SDValue LHS = GetScalarizedVector(N->getOperand(0)); 130 SDValue RHS = GetScalarizedVector(N->getOperand(1)); 131 return DAG.getNode(N->getOpcode(), SDLoc(N), 132 LHS.getValueType(), LHS, RHS); 133} 134 135SDValue DAGTypeLegalizer::ScalarizeVecRes_TernaryOp(SDNode *N) { 136 SDValue Op0 = GetScalarizedVector(N->getOperand(0)); 137 SDValue Op1 = GetScalarizedVector(N->getOperand(1)); 138 SDValue Op2 = GetScalarizedVector(N->getOperand(2)); 139 return DAG.getNode(N->getOpcode(), SDLoc(N), 140 Op0.getValueType(), Op0, Op1, Op2); 141} 142 143SDValue DAGTypeLegalizer::ScalarizeVecRes_MERGE_VALUES(SDNode *N, 144 unsigned ResNo) { 145 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo); 146 return GetScalarizedVector(Op); 147} 148 149SDValue DAGTypeLegalizer::ScalarizeVecRes_BITCAST(SDNode *N) { 150 EVT NewVT = N->getValueType(0).getVectorElementType(); 151 return DAG.getNode(ISD::BITCAST, SDLoc(N), 152 NewVT, N->getOperand(0)); 153} 154 155SDValue DAGTypeLegalizer::ScalarizeVecRes_BUILD_VECTOR(SDNode *N) { 156 EVT EltVT = N->getValueType(0).getVectorElementType(); 157 SDValue InOp = N->getOperand(0); 158 // The BUILD_VECTOR operands may be of wider element types and 159 // we may need to truncate them back to the requested return type. 160 if (EltVT.isInteger()) 161 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, InOp); 162 return InOp; 163} 164 165SDValue DAGTypeLegalizer::ScalarizeVecRes_CONVERT_RNDSAT(SDNode *N) { 166 EVT NewVT = N->getValueType(0).getVectorElementType(); 167 SDValue Op0 = GetScalarizedVector(N->getOperand(0)); 168 return DAG.getConvertRndSat(NewVT, SDLoc(N), 169 Op0, DAG.getValueType(NewVT), 170 DAG.getValueType(Op0.getValueType()), 171 N->getOperand(3), 172 N->getOperand(4), 173 cast<CvtRndSatSDNode>(N)->getCvtCode()); 174} 175 176SDValue DAGTypeLegalizer::ScalarizeVecRes_EXTRACT_SUBVECTOR(SDNode *N) { 177 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N), 178 N->getValueType(0).getVectorElementType(), 179 N->getOperand(0), N->getOperand(1)); 180} 181 182SDValue DAGTypeLegalizer::ScalarizeVecRes_FP_ROUND(SDNode *N) { 183 EVT NewVT = N->getValueType(0).getVectorElementType(); 184 SDValue Op = GetScalarizedVector(N->getOperand(0)); 185 return DAG.getNode(ISD::FP_ROUND, SDLoc(N), 186 NewVT, Op, N->getOperand(1)); 187} 188 189SDValue DAGTypeLegalizer::ScalarizeVecRes_FPOWI(SDNode *N) { 190 SDValue Op = GetScalarizedVector(N->getOperand(0)); 191 return DAG.getNode(ISD::FPOWI, SDLoc(N), 192 Op.getValueType(), Op, N->getOperand(1)); 193} 194 195SDValue DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) { 196 // The value to insert may have a wider type than the vector element type, 197 // so be sure to truncate it to the element type if necessary. 198 SDValue Op = N->getOperand(1); 199 EVT EltVT = N->getValueType(0).getVectorElementType(); 200 if (Op.getValueType() != EltVT) 201 // FIXME: Can this happen for floating point types? 202 Op = DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, Op); 203 return Op; 204} 205 206SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) { 207 assert(N->isUnindexed() && "Indexed vector load?"); 208 209 SDValue Result = DAG.getLoad(ISD::UNINDEXED, 210 N->getExtensionType(), 211 N->getValueType(0).getVectorElementType(), 212 SDLoc(N), 213 N->getChain(), N->getBasePtr(), 214 DAG.getUNDEF(N->getBasePtr().getValueType()), 215 N->getPointerInfo(), 216 N->getMemoryVT().getVectorElementType(), 217 N->isVolatile(), N->isNonTemporal(), 218 N->isInvariant(), N->getOriginalAlignment()); 219 220 // Legalized the chain result - switch anything that used the old chain to 221 // use the new one. 222 ReplaceValueWith(SDValue(N, 1), Result.getValue(1)); 223 return Result; 224} 225 226SDValue DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) { 227 // Get the dest type - it doesn't always match the input type, e.g. int_to_fp. 228 EVT DestVT = N->getValueType(0).getVectorElementType(); 229 SDValue Op = GetScalarizedVector(N->getOperand(0)); 230 return DAG.getNode(N->getOpcode(), SDLoc(N), DestVT, Op); 231} 232 233SDValue DAGTypeLegalizer::ScalarizeVecRes_InregOp(SDNode *N) { 234 EVT EltVT = N->getValueType(0).getVectorElementType(); 235 EVT ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT().getVectorElementType(); 236 SDValue LHS = GetScalarizedVector(N->getOperand(0)); 237 return DAG.getNode(N->getOpcode(), SDLoc(N), EltVT, 238 LHS, DAG.getValueType(ExtVT)); 239} 240 241SDValue DAGTypeLegalizer::ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N) { 242 // If the operand is wider than the vector element type then it is implicitly 243 // truncated. Make that explicit here. 244 EVT EltVT = N->getValueType(0).getVectorElementType(); 245 SDValue InOp = N->getOperand(0); 246 if (InOp.getValueType() != EltVT) 247 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, InOp); 248 return InOp; 249} 250 251SDValue DAGTypeLegalizer::ScalarizeVecRes_VSELECT(SDNode *N) { 252 SDValue Cond = GetScalarizedVector(N->getOperand(0)); 253 SDValue LHS = GetScalarizedVector(N->getOperand(1)); 254 TargetLowering::BooleanContent ScalarBool = TLI.getBooleanContents(false); 255 TargetLowering::BooleanContent VecBool = TLI.getBooleanContents(true); 256 if (ScalarBool != VecBool) { 257 EVT CondVT = Cond.getValueType(); 258 switch (ScalarBool) { 259 case TargetLowering::UndefinedBooleanContent: 260 break; 261 case TargetLowering::ZeroOrOneBooleanContent: 262 assert(VecBool == TargetLowering::UndefinedBooleanContent || 263 VecBool == TargetLowering::ZeroOrNegativeOneBooleanContent); 264 // Vector read from all ones, scalar expects a single 1 so mask. 265 Cond = DAG.getNode(ISD::AND, SDLoc(N), CondVT, 266 Cond, DAG.getConstant(1, CondVT)); 267 break; 268 case TargetLowering::ZeroOrNegativeOneBooleanContent: 269 assert(VecBool == TargetLowering::UndefinedBooleanContent || 270 VecBool == TargetLowering::ZeroOrOneBooleanContent); 271 // Vector reads from a one, scalar from all ones so sign extend. 272 Cond = DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), CondVT, 273 Cond, DAG.getValueType(MVT::i1)); 274 break; 275 } 276 } 277 278 return DAG.getSelect(SDLoc(N), 279 LHS.getValueType(), Cond, LHS, 280 GetScalarizedVector(N->getOperand(2))); 281} 282 283SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT(SDNode *N) { 284 SDValue LHS = GetScalarizedVector(N->getOperand(1)); 285 return DAG.getSelect(SDLoc(N), 286 LHS.getValueType(), N->getOperand(0), LHS, 287 GetScalarizedVector(N->getOperand(2))); 288} 289 290SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT_CC(SDNode *N) { 291 SDValue LHS = GetScalarizedVector(N->getOperand(2)); 292 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), LHS.getValueType(), 293 N->getOperand(0), N->getOperand(1), 294 LHS, GetScalarizedVector(N->getOperand(3)), 295 N->getOperand(4)); 296} 297 298SDValue DAGTypeLegalizer::ScalarizeVecRes_SETCC(SDNode *N) { 299 assert(N->getValueType(0).isVector() == 300 N->getOperand(0).getValueType().isVector() && 301 "Scalar/Vector type mismatch"); 302 303 if (N->getValueType(0).isVector()) return ScalarizeVecRes_VSETCC(N); 304 305 SDValue LHS = GetScalarizedVector(N->getOperand(0)); 306 SDValue RHS = GetScalarizedVector(N->getOperand(1)); 307 SDLoc DL(N); 308 309 // Turn it into a scalar SETCC. 310 return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2)); 311} 312 313SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) { 314 return DAG.getUNDEF(N->getValueType(0).getVectorElementType()); 315} 316 317SDValue DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) { 318 // Figure out if the scalar is the LHS or RHS and return it. 319 SDValue Arg = N->getOperand(2).getOperand(0); 320 if (Arg.getOpcode() == ISD::UNDEF) 321 return DAG.getUNDEF(N->getValueType(0).getVectorElementType()); 322 unsigned Op = !cast<ConstantSDNode>(Arg)->isNullValue(); 323 return GetScalarizedVector(N->getOperand(Op)); 324} 325 326SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) { 327 assert(N->getValueType(0).isVector() && 328 N->getOperand(0).getValueType().isVector() && 329 "Operand types must be vectors"); 330 331 SDValue LHS = GetScalarizedVector(N->getOperand(0)); 332 SDValue RHS = GetScalarizedVector(N->getOperand(1)); 333 EVT NVT = N->getValueType(0).getVectorElementType(); 334 SDLoc DL(N); 335 336 // Turn it into a scalar SETCC. 337 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, 338 N->getOperand(2)); 339 // Vectors may have a different boolean contents to scalars. Promote the 340 // value appropriately. 341 ISD::NodeType ExtendCode = 342 TargetLowering::getExtendForContent(TLI.getBooleanContents(true)); 343 return DAG.getNode(ExtendCode, DL, NVT, Res); 344} 345 346 347//===----------------------------------------------------------------------===// 348// Operand Vector Scalarization <1 x ty> -> ty. 349//===----------------------------------------------------------------------===// 350 351bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) { 352 DEBUG(dbgs() << "Scalarize node operand " << OpNo << ": "; 353 N->dump(&DAG); 354 dbgs() << "\n"); 355 SDValue Res = SDValue(); 356 357 if (Res.getNode() == 0) { 358 switch (N->getOpcode()) { 359 default: 360#ifndef NDEBUG 361 dbgs() << "ScalarizeVectorOperand Op #" << OpNo << ": "; 362 N->dump(&DAG); 363 dbgs() << "\n"; 364#endif 365 llvm_unreachable("Do not know how to scalarize this operator's operand!"); 366 case ISD::BITCAST: 367 Res = ScalarizeVecOp_BITCAST(N); 368 break; 369 case ISD::ANY_EXTEND: 370 case ISD::ZERO_EXTEND: 371 case ISD::SIGN_EXTEND: 372 Res = ScalarizeVecOp_EXTEND(N); 373 break; 374 case ISD::CONCAT_VECTORS: 375 Res = ScalarizeVecOp_CONCAT_VECTORS(N); 376 break; 377 case ISD::EXTRACT_VECTOR_ELT: 378 Res = ScalarizeVecOp_EXTRACT_VECTOR_ELT(N); 379 break; 380 case ISD::STORE: 381 Res = ScalarizeVecOp_STORE(cast<StoreSDNode>(N), OpNo); 382 break; 383 } 384 } 385 386 // If the result is null, the sub-method took care of registering results etc. 387 if (!Res.getNode()) return false; 388 389 // If the result is N, the sub-method updated N in place. Tell the legalizer 390 // core about this. 391 if (Res.getNode() == N) 392 return true; 393 394 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 395 "Invalid operand expansion"); 396 397 ReplaceValueWith(SDValue(N, 0), Res); 398 return false; 399} 400 401/// ScalarizeVecOp_BITCAST - If the value to convert is a vector that needs 402/// to be scalarized, it must be <1 x ty>. Convert the element instead. 403SDValue DAGTypeLegalizer::ScalarizeVecOp_BITCAST(SDNode *N) { 404 SDValue Elt = GetScalarizedVector(N->getOperand(0)); 405 return DAG.getNode(ISD::BITCAST, SDLoc(N), 406 N->getValueType(0), Elt); 407} 408 409/// ScalarizeVecOp_EXTEND - If the value to extend is a vector that needs 410/// to be scalarized, it must be <1 x ty>. Extend the element instead. 411SDValue DAGTypeLegalizer::ScalarizeVecOp_EXTEND(SDNode *N) { 412 assert(N->getValueType(0).getVectorNumElements() == 1 && 413 "Unexected vector type!"); 414 SDValue Elt = GetScalarizedVector(N->getOperand(0)); 415 SmallVector<SDValue, 1> Ops(1); 416 Ops[0] = DAG.getNode(N->getOpcode(), SDLoc(N), 417 N->getValueType(0).getScalarType(), Elt); 418 // Revectorize the result so the types line up with what the uses of this 419 // expression expect. 420 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), N->getValueType(0), 421 &Ops[0], 1); 422} 423 424/// ScalarizeVecOp_CONCAT_VECTORS - The vectors to concatenate have length one - 425/// use a BUILD_VECTOR instead. 426SDValue DAGTypeLegalizer::ScalarizeVecOp_CONCAT_VECTORS(SDNode *N) { 427 SmallVector<SDValue, 8> Ops(N->getNumOperands()); 428 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i) 429 Ops[i] = GetScalarizedVector(N->getOperand(i)); 430 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), N->getValueType(0), 431 &Ops[0], Ops.size()); 432} 433 434/// ScalarizeVecOp_EXTRACT_VECTOR_ELT - If the input is a vector that needs to 435/// be scalarized, it must be <1 x ty>, so just return the element, ignoring the 436/// index. 437SDValue DAGTypeLegalizer::ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N) { 438 SDValue Res = GetScalarizedVector(N->getOperand(0)); 439 if (Res.getValueType() != N->getValueType(0)) 440 Res = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), N->getValueType(0), 441 Res); 442 return Res; 443} 444 445/// ScalarizeVecOp_STORE - If the value to store is a vector that needs to be 446/// scalarized, it must be <1 x ty>. Just store the element. 447SDValue DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){ 448 assert(N->isUnindexed() && "Indexed store of one-element vector?"); 449 assert(OpNo == 1 && "Do not know how to scalarize this operand!"); 450 SDLoc dl(N); 451 452 if (N->isTruncatingStore()) 453 return DAG.getTruncStore(N->getChain(), dl, 454 GetScalarizedVector(N->getOperand(1)), 455 N->getBasePtr(), N->getPointerInfo(), 456 N->getMemoryVT().getVectorElementType(), 457 N->isVolatile(), N->isNonTemporal(), 458 N->getAlignment()); 459 460 return DAG.getStore(N->getChain(), dl, GetScalarizedVector(N->getOperand(1)), 461 N->getBasePtr(), N->getPointerInfo(), 462 N->isVolatile(), N->isNonTemporal(), 463 N->getOriginalAlignment()); 464} 465 466 467//===----------------------------------------------------------------------===// 468// Result Vector Splitting 469//===----------------------------------------------------------------------===// 470 471/// SplitVectorResult - This method is called when the specified result of the 472/// specified node is found to need vector splitting. At this point, the node 473/// may also have invalid operands or may have other results that need 474/// legalization, we just know that (at least) one result needs vector 475/// splitting. 476void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) { 477 DEBUG(dbgs() << "Split node result: "; 478 N->dump(&DAG); 479 dbgs() << "\n"); 480 SDValue Lo, Hi; 481 482 // See if the target wants to custom expand this node. 483 if (CustomLowerNode(N, N->getValueType(ResNo), true)) 484 return; 485 486 switch (N->getOpcode()) { 487 default: 488#ifndef NDEBUG 489 dbgs() << "SplitVectorResult #" << ResNo << ": "; 490 N->dump(&DAG); 491 dbgs() << "\n"; 492#endif 493 report_fatal_error("Do not know how to split the result of this " 494 "operator!\n"); 495 496 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break; 497 case ISD::VSELECT: 498 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break; 499 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break; 500 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break; 501 case ISD::BITCAST: SplitVecRes_BITCAST(N, Lo, Hi); break; 502 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break; 503 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break; 504 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break; 505 case ISD::FP_ROUND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break; 506 case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break; 507 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break; 508 case ISD::SCALAR_TO_VECTOR: SplitVecRes_SCALAR_TO_VECTOR(N, Lo, Hi); break; 509 case ISD::SIGN_EXTEND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break; 510 case ISD::LOAD: 511 SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); 512 break; 513 case ISD::SETCC: 514 SplitVecRes_SETCC(N, Lo, Hi); 515 break; 516 case ISD::VECTOR_SHUFFLE: 517 SplitVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N), Lo, Hi); 518 break; 519 520 case ISD::ANY_EXTEND: 521 case ISD::CONVERT_RNDSAT: 522 case ISD::CTLZ: 523 case ISD::CTTZ: 524 case ISD::CTLZ_ZERO_UNDEF: 525 case ISD::CTTZ_ZERO_UNDEF: 526 case ISD::CTPOP: 527 case ISD::FABS: 528 case ISD::FCEIL: 529 case ISD::FCOS: 530 case ISD::FEXP: 531 case ISD::FEXP2: 532 case ISD::FFLOOR: 533 case ISD::FLOG: 534 case ISD::FLOG10: 535 case ISD::FLOG2: 536 case ISD::FNEARBYINT: 537 case ISD::FNEG: 538 case ISD::FP_EXTEND: 539 case ISD::FP_ROUND: 540 case ISD::FP_TO_SINT: 541 case ISD::FP_TO_UINT: 542 case ISD::FRINT: 543 case ISD::FSIN: 544 case ISD::FSQRT: 545 case ISD::FTRUNC: 546 case ISD::SIGN_EXTEND: 547 case ISD::SINT_TO_FP: 548 case ISD::TRUNCATE: 549 case ISD::UINT_TO_FP: 550 case ISD::ZERO_EXTEND: 551 SplitVecRes_UnaryOp(N, Lo, Hi); 552 break; 553 554 case ISD::ADD: 555 case ISD::SUB: 556 case ISD::MUL: 557 case ISD::FADD: 558 case ISD::FSUB: 559 case ISD::FMUL: 560 case ISD::SDIV: 561 case ISD::UDIV: 562 case ISD::FDIV: 563 case ISD::FPOW: 564 case ISD::AND: 565 case ISD::OR: 566 case ISD::XOR: 567 case ISD::SHL: 568 case ISD::SRA: 569 case ISD::SRL: 570 case ISD::UREM: 571 case ISD::SREM: 572 case ISD::FREM: 573 SplitVecRes_BinOp(N, Lo, Hi); 574 break; 575 case ISD::FMA: 576 SplitVecRes_TernaryOp(N, Lo, Hi); 577 break; 578 } 579 580 // If Lo/Hi is null, the sub-method took care of registering results etc. 581 if (Lo.getNode()) 582 SetSplitVector(SDValue(N, ResNo), Lo, Hi); 583} 584 585void DAGTypeLegalizer::SplitVecRes_BinOp(SDNode *N, SDValue &Lo, 586 SDValue &Hi) { 587 SDValue LHSLo, LHSHi; 588 GetSplitVector(N->getOperand(0), LHSLo, LHSHi); 589 SDValue RHSLo, RHSHi; 590 GetSplitVector(N->getOperand(1), RHSLo, RHSHi); 591 SDLoc dl(N); 592 593 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo, RHSLo); 594 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi, RHSHi); 595} 596 597void DAGTypeLegalizer::SplitVecRes_TernaryOp(SDNode *N, SDValue &Lo, 598 SDValue &Hi) { 599 SDValue Op0Lo, Op0Hi; 600 GetSplitVector(N->getOperand(0), Op0Lo, Op0Hi); 601 SDValue Op1Lo, Op1Hi; 602 GetSplitVector(N->getOperand(1), Op1Lo, Op1Hi); 603 SDValue Op2Lo, Op2Hi; 604 GetSplitVector(N->getOperand(2), Op2Lo, Op2Hi); 605 SDLoc dl(N); 606 607 Lo = DAG.getNode(N->getOpcode(), dl, Op0Lo.getValueType(), 608 Op0Lo, Op1Lo, Op2Lo); 609 Hi = DAG.getNode(N->getOpcode(), dl, Op0Hi.getValueType(), 610 Op0Hi, Op1Hi, Op2Hi); 611} 612 613void DAGTypeLegalizer::SplitVecRes_BITCAST(SDNode *N, SDValue &Lo, 614 SDValue &Hi) { 615 // We know the result is a vector. The input may be either a vector or a 616 // scalar value. 617 EVT LoVT, HiVT; 618 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 619 SDLoc dl(N); 620 621 SDValue InOp = N->getOperand(0); 622 EVT InVT = InOp.getValueType(); 623 624 // Handle some special cases efficiently. 625 switch (getTypeAction(InVT)) { 626 case TargetLowering::TypeLegal: 627 case TargetLowering::TypePromoteInteger: 628 case TargetLowering::TypeSoftenFloat: 629 case TargetLowering::TypeScalarizeVector: 630 case TargetLowering::TypeWidenVector: 631 break; 632 case TargetLowering::TypeExpandInteger: 633 case TargetLowering::TypeExpandFloat: 634 // A scalar to vector conversion, where the scalar needs expansion. 635 // If the vector is being split in two then we can just convert the 636 // expanded pieces. 637 if (LoVT == HiVT) { 638 GetExpandedOp(InOp, Lo, Hi); 639 if (TLI.isBigEndian()) 640 std::swap(Lo, Hi); 641 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo); 642 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi); 643 return; 644 } 645 break; 646 case TargetLowering::TypeSplitVector: 647 // If the input is a vector that needs to be split, convert each split 648 // piece of the input now. 649 GetSplitVector(InOp, Lo, Hi); 650 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo); 651 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi); 652 return; 653 } 654 655 // In the general case, convert the input to an integer and split it by hand. 656 EVT LoIntVT = EVT::getIntegerVT(*DAG.getContext(), LoVT.getSizeInBits()); 657 EVT HiIntVT = EVT::getIntegerVT(*DAG.getContext(), HiVT.getSizeInBits()); 658 if (TLI.isBigEndian()) 659 std::swap(LoIntVT, HiIntVT); 660 661 SplitInteger(BitConvertToInteger(InOp), LoIntVT, HiIntVT, Lo, Hi); 662 663 if (TLI.isBigEndian()) 664 std::swap(Lo, Hi); 665 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo); 666 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi); 667} 668 669void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo, 670 SDValue &Hi) { 671 EVT LoVT, HiVT; 672 SDLoc dl(N); 673 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 674 unsigned LoNumElts = LoVT.getVectorNumElements(); 675 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts); 676 Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, LoVT, &LoOps[0], LoOps.size()); 677 678 SmallVector<SDValue, 8> HiOps(N->op_begin()+LoNumElts, N->op_end()); 679 Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, HiVT, &HiOps[0], HiOps.size()); 680} 681 682void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo, 683 SDValue &Hi) { 684 assert(!(N->getNumOperands() & 1) && "Unsupported CONCAT_VECTORS"); 685 SDLoc dl(N); 686 unsigned NumSubvectors = N->getNumOperands() / 2; 687 if (NumSubvectors == 1) { 688 Lo = N->getOperand(0); 689 Hi = N->getOperand(1); 690 return; 691 } 692 693 EVT LoVT, HiVT; 694 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 695 696 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors); 697 Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, LoVT, &LoOps[0], LoOps.size()); 698 699 SmallVector<SDValue, 8> HiOps(N->op_begin()+NumSubvectors, N->op_end()); 700 Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HiVT, &HiOps[0], HiOps.size()); 701} 702 703void DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo, 704 SDValue &Hi) { 705 SDValue Vec = N->getOperand(0); 706 SDValue Idx = N->getOperand(1); 707 SDLoc dl(N); 708 709 EVT LoVT, HiVT; 710 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 711 712 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx); 713 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 714 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HiVT, Vec, 715 DAG.getIntPtrConstant(IdxVal + LoVT.getVectorNumElements())); 716} 717 718void DAGTypeLegalizer::SplitVecRes_FPOWI(SDNode *N, SDValue &Lo, 719 SDValue &Hi) { 720 SDLoc dl(N); 721 GetSplitVector(N->getOperand(0), Lo, Hi); 722 Lo = DAG.getNode(ISD::FPOWI, dl, Lo.getValueType(), Lo, N->getOperand(1)); 723 Hi = DAG.getNode(ISD::FPOWI, dl, Hi.getValueType(), Hi, N->getOperand(1)); 724} 725 726void DAGTypeLegalizer::SplitVecRes_InregOp(SDNode *N, SDValue &Lo, 727 SDValue &Hi) { 728 SDValue LHSLo, LHSHi; 729 GetSplitVector(N->getOperand(0), LHSLo, LHSHi); 730 SDLoc dl(N); 731 732 EVT LoVT, HiVT; 733 GetSplitDestVTs(cast<VTSDNode>(N->getOperand(1))->getVT(), LoVT, HiVT); 734 735 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo, 736 DAG.getValueType(LoVT)); 737 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi, 738 DAG.getValueType(HiVT)); 739} 740 741void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo, 742 SDValue &Hi) { 743 SDValue Vec = N->getOperand(0); 744 SDValue Elt = N->getOperand(1); 745 SDValue Idx = N->getOperand(2); 746 SDLoc dl(N); 747 GetSplitVector(Vec, Lo, Hi); 748 749 if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) { 750 unsigned IdxVal = CIdx->getZExtValue(); 751 unsigned LoNumElts = Lo.getValueType().getVectorNumElements(); 752 if (IdxVal < LoNumElts) 753 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, 754 Lo.getValueType(), Lo, Elt, Idx); 755 else 756 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, Hi.getValueType(), Hi, Elt, 757 DAG.getIntPtrConstant(IdxVal - LoNumElts)); 758 return; 759 } 760 761 // Spill the vector to the stack. 762 EVT VecVT = Vec.getValueType(); 763 EVT EltVT = VecVT.getVectorElementType(); 764 SDValue StackPtr = DAG.CreateStackTemporary(VecVT); 765 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, 766 MachinePointerInfo(), false, false, 0); 767 768 // Store the new element. This may be larger than the vector element type, 769 // so use a truncating store. 770 SDValue EltPtr = GetVectorElementPointer(StackPtr, EltVT, Idx); 771 Type *VecType = VecVT.getTypeForEVT(*DAG.getContext()); 772 unsigned Alignment = 773 TLI.getDataLayout()->getPrefTypeAlignment(VecType); 774 Store = DAG.getTruncStore(Store, dl, Elt, EltPtr, MachinePointerInfo(), EltVT, 775 false, false, 0); 776 777 // Load the Lo part from the stack slot. 778 Lo = DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, MachinePointerInfo(), 779 false, false, false, 0); 780 781 // Increment the pointer to the other part. 782 unsigned IncrementSize = Lo.getValueType().getSizeInBits() / 8; 783 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, 784 DAG.getIntPtrConstant(IncrementSize)); 785 786 // Load the Hi part from the stack slot. 787 Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, MachinePointerInfo(), 788 false, false, false, MinAlign(Alignment, IncrementSize)); 789} 790 791void DAGTypeLegalizer::SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo, 792 SDValue &Hi) { 793 EVT LoVT, HiVT; 794 SDLoc dl(N); 795 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 796 Lo = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoVT, N->getOperand(0)); 797 Hi = DAG.getUNDEF(HiVT); 798} 799 800void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo, 801 SDValue &Hi) { 802 assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!"); 803 EVT LoVT, HiVT; 804 SDLoc dl(LD); 805 GetSplitDestVTs(LD->getValueType(0), LoVT, HiVT); 806 807 ISD::LoadExtType ExtType = LD->getExtensionType(); 808 SDValue Ch = LD->getChain(); 809 SDValue Ptr = LD->getBasePtr(); 810 SDValue Offset = DAG.getUNDEF(Ptr.getValueType()); 811 EVT MemoryVT = LD->getMemoryVT(); 812 unsigned Alignment = LD->getOriginalAlignment(); 813 bool isVolatile = LD->isVolatile(); 814 bool isNonTemporal = LD->isNonTemporal(); 815 bool isInvariant = LD->isInvariant(); 816 817 EVT LoMemVT, HiMemVT; 818 GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT); 819 820 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, dl, Ch, Ptr, Offset, 821 LD->getPointerInfo(), LoMemVT, isVolatile, isNonTemporal, 822 isInvariant, Alignment); 823 824 unsigned IncrementSize = LoMemVT.getSizeInBits()/8; 825 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 826 DAG.getIntPtrConstant(IncrementSize)); 827 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset, 828 LD->getPointerInfo().getWithOffset(IncrementSize), 829 HiMemVT, isVolatile, isNonTemporal, isInvariant, Alignment); 830 831 // Build a factor node to remember that this load is independent of the 832 // other one. 833 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 834 Hi.getValue(1)); 835 836 // Legalized the chain result - switch anything that used the old chain to 837 // use the new one. 838 ReplaceValueWith(SDValue(LD, 1), Ch); 839} 840 841void DAGTypeLegalizer::SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi) { 842 assert(N->getValueType(0).isVector() && 843 N->getOperand(0).getValueType().isVector() && 844 "Operand types must be vectors"); 845 846 EVT LoVT, HiVT; 847 SDLoc DL(N); 848 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 849 850 // Split the input. 851 EVT InVT = N->getOperand(0).getValueType(); 852 SDValue LL, LH, RL, RH; 853 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(), 854 LoVT.getVectorNumElements()); 855 LL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(0), 856 DAG.getIntPtrConstant(0)); 857 LH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(0), 858 DAG.getIntPtrConstant(InNVT.getVectorNumElements())); 859 860 RL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(1), 861 DAG.getIntPtrConstant(0)); 862 RH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(1), 863 DAG.getIntPtrConstant(InNVT.getVectorNumElements())); 864 865 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, LL, RL, N->getOperand(2)); 866 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2)); 867} 868 869void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo, 870 SDValue &Hi) { 871 // Get the dest types - they may not match the input types, e.g. int_to_fp. 872 EVT LoVT, HiVT; 873 SDLoc dl(N); 874 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 875 876 // If the input also splits, handle it directly for a compile time speedup. 877 // Otherwise split it by hand. 878 EVT InVT = N->getOperand(0).getValueType(); 879 if (getTypeAction(InVT) == TargetLowering::TypeSplitVector) { 880 GetSplitVector(N->getOperand(0), Lo, Hi); 881 } else { 882 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(), 883 LoVT.getVectorNumElements()); 884 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0), 885 DAG.getIntPtrConstant(0)); 886 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0), 887 DAG.getIntPtrConstant(InNVT.getVectorNumElements())); 888 } 889 890 if (N->getOpcode() == ISD::FP_ROUND) { 891 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo, N->getOperand(1)); 892 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi, N->getOperand(1)); 893 } else if (N->getOpcode() == ISD::CONVERT_RNDSAT) { 894 SDValue DTyOpLo = DAG.getValueType(LoVT); 895 SDValue DTyOpHi = DAG.getValueType(HiVT); 896 SDValue STyOpLo = DAG.getValueType(Lo.getValueType()); 897 SDValue STyOpHi = DAG.getValueType(Hi.getValueType()); 898 SDValue RndOp = N->getOperand(3); 899 SDValue SatOp = N->getOperand(4); 900 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode(); 901 Lo = DAG.getConvertRndSat(LoVT, dl, Lo, DTyOpLo, STyOpLo, RndOp, SatOp, 902 CvtCode); 903 Hi = DAG.getConvertRndSat(HiVT, dl, Hi, DTyOpHi, STyOpHi, RndOp, SatOp, 904 CvtCode); 905 } else { 906 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo); 907 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi); 908 } 909} 910 911void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N, 912 SDValue &Lo, SDValue &Hi) { 913 // The low and high parts of the original input give four input vectors. 914 SDValue Inputs[4]; 915 SDLoc dl(N); 916 GetSplitVector(N->getOperand(0), Inputs[0], Inputs[1]); 917 GetSplitVector(N->getOperand(1), Inputs[2], Inputs[3]); 918 EVT NewVT = Inputs[0].getValueType(); 919 unsigned NewElts = NewVT.getVectorNumElements(); 920 921 // If Lo or Hi uses elements from at most two of the four input vectors, then 922 // express it as a vector shuffle of those two inputs. Otherwise extract the 923 // input elements by hand and construct the Lo/Hi output using a BUILD_VECTOR. 924 SmallVector<int, 16> Ops; 925 for (unsigned High = 0; High < 2; ++High) { 926 SDValue &Output = High ? Hi : Lo; 927 928 // Build a shuffle mask for the output, discovering on the fly which 929 // input vectors to use as shuffle operands (recorded in InputUsed). 930 // If building a suitable shuffle vector proves too hard, then bail 931 // out with useBuildVector set. 932 unsigned InputUsed[2] = { -1U, -1U }; // Not yet discovered. 933 unsigned FirstMaskIdx = High * NewElts; 934 bool useBuildVector = false; 935 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) { 936 // The mask element. This indexes into the input. 937 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset); 938 939 // The input vector this mask element indexes into. 940 unsigned Input = (unsigned)Idx / NewElts; 941 942 if (Input >= array_lengthof(Inputs)) { 943 // The mask element does not index into any input vector. 944 Ops.push_back(-1); 945 continue; 946 } 947 948 // Turn the index into an offset from the start of the input vector. 949 Idx -= Input * NewElts; 950 951 // Find or create a shuffle vector operand to hold this input. 952 unsigned OpNo; 953 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) { 954 if (InputUsed[OpNo] == Input) { 955 // This input vector is already an operand. 956 break; 957 } else if (InputUsed[OpNo] == -1U) { 958 // Create a new operand for this input vector. 959 InputUsed[OpNo] = Input; 960 break; 961 } 962 } 963 964 if (OpNo >= array_lengthof(InputUsed)) { 965 // More than two input vectors used! Give up on trying to create a 966 // shuffle vector. Insert all elements into a BUILD_VECTOR instead. 967 useBuildVector = true; 968 break; 969 } 970 971 // Add the mask index for the new shuffle vector. 972 Ops.push_back(Idx + OpNo * NewElts); 973 } 974 975 if (useBuildVector) { 976 EVT EltVT = NewVT.getVectorElementType(); 977 SmallVector<SDValue, 16> SVOps; 978 979 // Extract the input elements by hand. 980 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) { 981 // The mask element. This indexes into the input. 982 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset); 983 984 // The input vector this mask element indexes into. 985 unsigned Input = (unsigned)Idx / NewElts; 986 987 if (Input >= array_lengthof(Inputs)) { 988 // The mask element is "undef" or indexes off the end of the input. 989 SVOps.push_back(DAG.getUNDEF(EltVT)); 990 continue; 991 } 992 993 // Turn the index into an offset from the start of the input vector. 994 Idx -= Input * NewElts; 995 996 // Extract the vector element by hand. 997 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, 998 Inputs[Input], DAG.getIntPtrConstant(Idx))); 999 } 1000 1001 // Construct the Lo/Hi output using a BUILD_VECTOR. 1002 Output = DAG.getNode(ISD::BUILD_VECTOR,dl,NewVT, &SVOps[0], SVOps.size()); 1003 } else if (InputUsed[0] == -1U) { 1004 // No input vectors were used! The result is undefined. 1005 Output = DAG.getUNDEF(NewVT); 1006 } else { 1007 SDValue Op0 = Inputs[InputUsed[0]]; 1008 // If only one input was used, use an undefined vector for the other. 1009 SDValue Op1 = InputUsed[1] == -1U ? 1010 DAG.getUNDEF(NewVT) : Inputs[InputUsed[1]]; 1011 // At least one input vector was used. Create a new shuffle vector. 1012 Output = DAG.getVectorShuffle(NewVT, dl, Op0, Op1, &Ops[0]); 1013 } 1014 1015 Ops.clear(); 1016 } 1017} 1018 1019 1020//===----------------------------------------------------------------------===// 1021// Operand Vector Splitting 1022//===----------------------------------------------------------------------===// 1023 1024/// SplitVectorOperand - This method is called when the specified operand of the 1025/// specified node is found to need vector splitting. At this point, all of the 1026/// result types of the node are known to be legal, but other operands of the 1027/// node may need legalization as well as the specified one. 1028bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) { 1029 DEBUG(dbgs() << "Split node operand: "; 1030 N->dump(&DAG); 1031 dbgs() << "\n"); 1032 SDValue Res = SDValue(); 1033 1034 if (Res.getNode() == 0) { 1035 switch (N->getOpcode()) { 1036 default: 1037#ifndef NDEBUG 1038 dbgs() << "SplitVectorOperand Op #" << OpNo << ": "; 1039 N->dump(&DAG); 1040 dbgs() << "\n"; 1041#endif 1042 report_fatal_error("Do not know how to split this operator's " 1043 "operand!\n"); 1044 1045 case ISD::SETCC: Res = SplitVecOp_VSETCC(N); break; 1046 case ISD::BITCAST: Res = SplitVecOp_BITCAST(N); break; 1047 case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break; 1048 case ISD::EXTRACT_VECTOR_ELT:Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break; 1049 case ISD::CONCAT_VECTORS: Res = SplitVecOp_CONCAT_VECTORS(N); break; 1050 case ISD::TRUNCATE: Res = SplitVecOp_TRUNCATE(N); break; 1051 case ISD::FP_ROUND: Res = SplitVecOp_FP_ROUND(N); break; 1052 case ISD::STORE: 1053 Res = SplitVecOp_STORE(cast<StoreSDNode>(N), OpNo); 1054 break; 1055 case ISD::VSELECT: 1056 Res = SplitVecOp_VSELECT(N, OpNo); 1057 break; 1058 case ISD::CTTZ: 1059 case ISD::CTLZ: 1060 case ISD::CTPOP: 1061 case ISD::FP_EXTEND: 1062 case ISD::FP_TO_SINT: 1063 case ISD::FP_TO_UINT: 1064 case ISD::SINT_TO_FP: 1065 case ISD::UINT_TO_FP: 1066 case ISD::FTRUNC: 1067 case ISD::SIGN_EXTEND: 1068 case ISD::ZERO_EXTEND: 1069 case ISD::ANY_EXTEND: 1070 Res = SplitVecOp_UnaryOp(N); 1071 break; 1072 } 1073 } 1074 1075 // If the result is null, the sub-method took care of registering results etc. 1076 if (!Res.getNode()) return false; 1077 1078 // If the result is N, the sub-method updated N in place. Tell the legalizer 1079 // core about this. 1080 if (Res.getNode() == N) 1081 return true; 1082 1083 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 1084 "Invalid operand expansion"); 1085 1086 ReplaceValueWith(SDValue(N, 0), Res); 1087 return false; 1088} 1089 1090SDValue DAGTypeLegalizer::SplitVecOp_VSELECT(SDNode *N, unsigned OpNo) { 1091 // The only possibility for an illegal operand is the mask, since result type 1092 // legalization would have handled this node already otherwise. 1093 assert(OpNo == 0 && "Illegal operand must be mask"); 1094 1095 SDValue Mask = N->getOperand(0); 1096 SDValue Src0 = N->getOperand(1); 1097 SDValue Src1 = N->getOperand(2); 1098 SDLoc DL(N); 1099 EVT MaskVT = Mask.getValueType(); 1100 assert(MaskVT.isVector() && "VSELECT without a vector mask?"); 1101 1102 SDValue Lo, Hi; 1103 GetSplitVector(N->getOperand(0), Lo, Hi); 1104 assert(Lo.getValueType() == Hi.getValueType() && 1105 "Lo and Hi have differing types"); 1106 1107 unsigned LoNumElts = Lo.getValueType().getVectorNumElements(); 1108 unsigned HiNumElts = Hi.getValueType().getVectorNumElements(); 1109 assert(LoNumElts == HiNumElts && "Asymmetric vector split?"); 1110 1111 LLVMContext &Ctx = *DAG.getContext(); 1112 SDValue Zero = DAG.getIntPtrConstant(0); 1113 SDValue LoElts = DAG.getIntPtrConstant(LoNumElts); 1114 EVT Src0VT = Src0.getValueType(); 1115 EVT Src0EltTy = Src0VT.getVectorElementType(); 1116 EVT MaskEltTy = MaskVT.getVectorElementType(); 1117 1118 EVT LoOpVT = EVT::getVectorVT(Ctx, Src0EltTy, LoNumElts); 1119 EVT LoMaskVT = EVT::getVectorVT(Ctx, MaskEltTy, LoNumElts); 1120 EVT HiOpVT = EVT::getVectorVT(Ctx, Src0EltTy, HiNumElts); 1121 EVT HiMaskVT = EVT::getVectorVT(Ctx, MaskEltTy, HiNumElts); 1122 1123 SDValue LoOp0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, LoOpVT, Src0, Zero); 1124 SDValue LoOp1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, LoOpVT, Src1, Zero); 1125 1126 SDValue HiOp0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HiOpVT, Src0, LoElts); 1127 SDValue HiOp1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HiOpVT, Src1, LoElts); 1128 1129 SDValue LoMask = 1130 DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, LoMaskVT, Mask, Zero); 1131 SDValue HiMask = 1132 DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HiMaskVT, Mask, LoElts); 1133 1134 SDValue LoSelect = 1135 DAG.getNode(ISD::VSELECT, DL, LoOpVT, LoMask, LoOp0, LoOp1); 1136 SDValue HiSelect = 1137 DAG.getNode(ISD::VSELECT, DL, HiOpVT, HiMask, HiOp0, HiOp1); 1138 1139 return DAG.getNode(ISD::CONCAT_VECTORS, DL, Src0VT, LoSelect, HiSelect); 1140} 1141 1142SDValue DAGTypeLegalizer::SplitVecOp_UnaryOp(SDNode *N) { 1143 // The result has a legal vector type, but the input needs splitting. 1144 EVT ResVT = N->getValueType(0); 1145 SDValue Lo, Hi; 1146 SDLoc dl(N); 1147 GetSplitVector(N->getOperand(0), Lo, Hi); 1148 EVT InVT = Lo.getValueType(); 1149 1150 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(), 1151 InVT.getVectorNumElements()); 1152 1153 Lo = DAG.getNode(N->getOpcode(), dl, OutVT, Lo); 1154 Hi = DAG.getNode(N->getOpcode(), dl, OutVT, Hi); 1155 1156 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi); 1157} 1158 1159SDValue DAGTypeLegalizer::SplitVecOp_BITCAST(SDNode *N) { 1160 // For example, i64 = BITCAST v4i16 on alpha. Typically the vector will 1161 // end up being split all the way down to individual components. Convert the 1162 // split pieces into integers and reassemble. 1163 SDValue Lo, Hi; 1164 GetSplitVector(N->getOperand(0), Lo, Hi); 1165 Lo = BitConvertToInteger(Lo); 1166 Hi = BitConvertToInteger(Hi); 1167 1168 if (TLI.isBigEndian()) 1169 std::swap(Lo, Hi); 1170 1171 return DAG.getNode(ISD::BITCAST, SDLoc(N), N->getValueType(0), 1172 JoinIntegers(Lo, Hi)); 1173} 1174 1175SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) { 1176 // We know that the extracted result type is legal. 1177 EVT SubVT = N->getValueType(0); 1178 SDValue Idx = N->getOperand(1); 1179 SDLoc dl(N); 1180 SDValue Lo, Hi; 1181 GetSplitVector(N->getOperand(0), Lo, Hi); 1182 1183 uint64_t LoElts = Lo.getValueType().getVectorNumElements(); 1184 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 1185 1186 if (IdxVal < LoElts) { 1187 assert(IdxVal + SubVT.getVectorNumElements() <= LoElts && 1188 "Extracted subvector crosses vector split!"); 1189 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Lo, Idx); 1190 } else { 1191 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Hi, 1192 DAG.getConstant(IdxVal - LoElts, Idx.getValueType())); 1193 } 1194} 1195 1196SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) { 1197 SDValue Vec = N->getOperand(0); 1198 SDValue Idx = N->getOperand(1); 1199 EVT VecVT = Vec.getValueType(); 1200 1201 if (isa<ConstantSDNode>(Idx)) { 1202 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 1203 assert(IdxVal < VecVT.getVectorNumElements() && "Invalid vector index!"); 1204 1205 SDValue Lo, Hi; 1206 GetSplitVector(Vec, Lo, Hi); 1207 1208 uint64_t LoElts = Lo.getValueType().getVectorNumElements(); 1209 1210 if (IdxVal < LoElts) 1211 return SDValue(DAG.UpdateNodeOperands(N, Lo, Idx), 0); 1212 return SDValue(DAG.UpdateNodeOperands(N, Hi, 1213 DAG.getConstant(IdxVal - LoElts, 1214 Idx.getValueType())), 0); 1215 } 1216 1217 // Store the vector to the stack. 1218 EVT EltVT = VecVT.getVectorElementType(); 1219 SDLoc dl(N); 1220 SDValue StackPtr = DAG.CreateStackTemporary(VecVT); 1221 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, 1222 MachinePointerInfo(), false, false, 0); 1223 1224 // Load back the required element. 1225 StackPtr = GetVectorElementPointer(StackPtr, EltVT, Idx); 1226 return DAG.getExtLoad(ISD::EXTLOAD, dl, N->getValueType(0), Store, StackPtr, 1227 MachinePointerInfo(), EltVT, false, false, 0); 1228} 1229 1230SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) { 1231 assert(N->isUnindexed() && "Indexed store of vector?"); 1232 assert(OpNo == 1 && "Can only split the stored value"); 1233 SDLoc DL(N); 1234 1235 bool isTruncating = N->isTruncatingStore(); 1236 SDValue Ch = N->getChain(); 1237 SDValue Ptr = N->getBasePtr(); 1238 EVT MemoryVT = N->getMemoryVT(); 1239 unsigned Alignment = N->getOriginalAlignment(); 1240 bool isVol = N->isVolatile(); 1241 bool isNT = N->isNonTemporal(); 1242 SDValue Lo, Hi; 1243 GetSplitVector(N->getOperand(1), Lo, Hi); 1244 1245 EVT LoMemVT, HiMemVT; 1246 GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT); 1247 1248 unsigned IncrementSize = LoMemVT.getSizeInBits()/8; 1249 1250 if (isTruncating) 1251 Lo = DAG.getTruncStore(Ch, DL, Lo, Ptr, N->getPointerInfo(), 1252 LoMemVT, isVol, isNT, Alignment); 1253 else 1254 Lo = DAG.getStore(Ch, DL, Lo, Ptr, N->getPointerInfo(), 1255 isVol, isNT, Alignment); 1256 1257 // Increment the pointer to the other half. 1258 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr, 1259 DAG.getIntPtrConstant(IncrementSize)); 1260 1261 if (isTruncating) 1262 Hi = DAG.getTruncStore(Ch, DL, Hi, Ptr, 1263 N->getPointerInfo().getWithOffset(IncrementSize), 1264 HiMemVT, isVol, isNT, Alignment); 1265 else 1266 Hi = DAG.getStore(Ch, DL, Hi, Ptr, 1267 N->getPointerInfo().getWithOffset(IncrementSize), 1268 isVol, isNT, Alignment); 1269 1270 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi); 1271} 1272 1273SDValue DAGTypeLegalizer::SplitVecOp_CONCAT_VECTORS(SDNode *N) { 1274 SDLoc DL(N); 1275 1276 // The input operands all must have the same type, and we know the result 1277 // type is valid. Convert this to a buildvector which extracts all the 1278 // input elements. 1279 // TODO: If the input elements are power-two vectors, we could convert this to 1280 // a new CONCAT_VECTORS node with elements that are half-wide. 1281 SmallVector<SDValue, 32> Elts; 1282 EVT EltVT = N->getValueType(0).getVectorElementType(); 1283 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) { 1284 SDValue Op = N->getOperand(op); 1285 for (unsigned i = 0, e = Op.getValueType().getVectorNumElements(); 1286 i != e; ++i) { 1287 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, 1288 Op, DAG.getIntPtrConstant(i))); 1289 1290 } 1291 } 1292 1293 return DAG.getNode(ISD::BUILD_VECTOR, DL, N->getValueType(0), 1294 &Elts[0], Elts.size()); 1295} 1296 1297SDValue DAGTypeLegalizer::SplitVecOp_TRUNCATE(SDNode *N) { 1298 // The result type is legal, but the input type is illegal. If splitting 1299 // ends up with the result type of each half still being legal, just 1300 // do that. If, however, that would result in an illegal result type, 1301 // we can try to get more clever with power-two vectors. Specifically, 1302 // split the input type, but also widen the result element size, then 1303 // concatenate the halves and truncate again. For example, consider a target 1304 // where v8i8 is legal and v8i32 is not (ARM, which doesn't have 256-bit 1305 // vectors). To perform a "%res = v8i8 trunc v8i32 %in" we do: 1306 // %inlo = v4i32 extract_subvector %in, 0 1307 // %inhi = v4i32 extract_subvector %in, 4 1308 // %lo16 = v4i16 trunc v4i32 %inlo 1309 // %hi16 = v4i16 trunc v4i32 %inhi 1310 // %in16 = v8i16 concat_vectors v4i16 %lo16, v4i16 %hi16 1311 // %res = v8i8 trunc v8i16 %in16 1312 // 1313 // Without this transform, the original truncate would end up being 1314 // scalarized, which is pretty much always a last resort. 1315 SDValue InVec = N->getOperand(0); 1316 EVT InVT = InVec->getValueType(0); 1317 EVT OutVT = N->getValueType(0); 1318 unsigned NumElements = OutVT.getVectorNumElements(); 1319 // Widening should have already made sure this is a power-two vector 1320 // if we're trying to split it at all. assert() that's true, just in case. 1321 assert(!(NumElements & 1) && "Splitting vector, but not in half!"); 1322 1323 unsigned InElementSize = InVT.getVectorElementType().getSizeInBits(); 1324 unsigned OutElementSize = OutVT.getVectorElementType().getSizeInBits(); 1325 1326 // If the input elements are only 1/2 the width of the result elements, 1327 // just use the normal splitting. Our trick only work if there's room 1328 // to split more than once. 1329 if (InElementSize <= OutElementSize * 2) 1330 return SplitVecOp_UnaryOp(N); 1331 SDLoc DL(N); 1332 1333 // Extract the halves of the input via extract_subvector. 1334 EVT SplitVT = EVT::getVectorVT(*DAG.getContext(), 1335 InVT.getVectorElementType(), NumElements/2); 1336 SDValue InLoVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, InVec, 1337 DAG.getIntPtrConstant(0)); 1338 SDValue InHiVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, InVec, 1339 DAG.getIntPtrConstant(NumElements/2)); 1340 // Truncate them to 1/2 the element size. 1341 EVT HalfElementVT = EVT::getIntegerVT(*DAG.getContext(), InElementSize/2); 1342 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), HalfElementVT, 1343 NumElements/2); 1344 SDValue HalfLo = DAG.getNode(ISD::TRUNCATE, DL, HalfVT, InLoVec); 1345 SDValue HalfHi = DAG.getNode(ISD::TRUNCATE, DL, HalfVT, InHiVec); 1346 // Concatenate them to get the full intermediate truncation result. 1347 EVT InterVT = EVT::getVectorVT(*DAG.getContext(), HalfElementVT, NumElements); 1348 SDValue InterVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InterVT, HalfLo, 1349 HalfHi); 1350 // Now finish up by truncating all the way down to the original result 1351 // type. This should normally be something that ends up being legal directly, 1352 // but in theory if a target has very wide vectors and an annoyingly 1353 // restricted set of legal types, this split can chain to build things up. 1354 return DAG.getNode(ISD::TRUNCATE, DL, OutVT, InterVec); 1355} 1356 1357SDValue DAGTypeLegalizer::SplitVecOp_VSETCC(SDNode *N) { 1358 assert(N->getValueType(0).isVector() && 1359 N->getOperand(0).getValueType().isVector() && 1360 "Operand types must be vectors"); 1361 // The result has a legal vector type, but the input needs splitting. 1362 SDValue Lo0, Hi0, Lo1, Hi1, LoRes, HiRes; 1363 SDLoc DL(N); 1364 GetSplitVector(N->getOperand(0), Lo0, Hi0); 1365 GetSplitVector(N->getOperand(1), Lo1, Hi1); 1366 unsigned PartElements = Lo0.getValueType().getVectorNumElements(); 1367 EVT PartResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, PartElements); 1368 EVT WideResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, 2*PartElements); 1369 1370 LoRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Lo0, Lo1, N->getOperand(2)); 1371 HiRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Hi0, Hi1, N->getOperand(2)); 1372 SDValue Con = DAG.getNode(ISD::CONCAT_VECTORS, DL, WideResVT, LoRes, HiRes); 1373 return PromoteTargetBoolean(Con, N->getValueType(0)); 1374} 1375 1376 1377SDValue DAGTypeLegalizer::SplitVecOp_FP_ROUND(SDNode *N) { 1378 // The result has a legal vector type, but the input needs splitting. 1379 EVT ResVT = N->getValueType(0); 1380 SDValue Lo, Hi; 1381 SDLoc DL(N); 1382 GetSplitVector(N->getOperand(0), Lo, Hi); 1383 EVT InVT = Lo.getValueType(); 1384 1385 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(), 1386 InVT.getVectorNumElements()); 1387 1388 Lo = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Lo, N->getOperand(1)); 1389 Hi = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Hi, N->getOperand(1)); 1390 1391 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi); 1392} 1393 1394 1395 1396//===----------------------------------------------------------------------===// 1397// Result Vector Widening 1398//===----------------------------------------------------------------------===// 1399 1400void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) { 1401 DEBUG(dbgs() << "Widen node result " << ResNo << ": "; 1402 N->dump(&DAG); 1403 dbgs() << "\n"); 1404 1405 // See if the target wants to custom widen this node. 1406 if (CustomWidenLowerNode(N, N->getValueType(ResNo))) 1407 return; 1408 1409 SDValue Res = SDValue(); 1410 switch (N->getOpcode()) { 1411 default: 1412#ifndef NDEBUG 1413 dbgs() << "WidenVectorResult #" << ResNo << ": "; 1414 N->dump(&DAG); 1415 dbgs() << "\n"; 1416#endif 1417 llvm_unreachable("Do not know how to widen the result of this operator!"); 1418 1419 case ISD::MERGE_VALUES: Res = WidenVecRes_MERGE_VALUES(N, ResNo); break; 1420 case ISD::BITCAST: Res = WidenVecRes_BITCAST(N); break; 1421 case ISD::BUILD_VECTOR: Res = WidenVecRes_BUILD_VECTOR(N); break; 1422 case ISD::CONCAT_VECTORS: Res = WidenVecRes_CONCAT_VECTORS(N); break; 1423 case ISD::CONVERT_RNDSAT: Res = WidenVecRes_CONVERT_RNDSAT(N); break; 1424 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecRes_EXTRACT_SUBVECTOR(N); break; 1425 case ISD::FP_ROUND_INREG: Res = WidenVecRes_InregOp(N); break; 1426 case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break; 1427 case ISD::LOAD: Res = WidenVecRes_LOAD(N); break; 1428 case ISD::SCALAR_TO_VECTOR: Res = WidenVecRes_SCALAR_TO_VECTOR(N); break; 1429 case ISD::SIGN_EXTEND_INREG: Res = WidenVecRes_InregOp(N); break; 1430 case ISD::VSELECT: 1431 case ISD::SELECT: Res = WidenVecRes_SELECT(N); break; 1432 case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break; 1433 case ISD::SETCC: Res = WidenVecRes_SETCC(N); break; 1434 case ISD::UNDEF: Res = WidenVecRes_UNDEF(N); break; 1435 case ISD::VECTOR_SHUFFLE: 1436 Res = WidenVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N)); 1437 break; 1438 case ISD::ADD: 1439 case ISD::AND: 1440 case ISD::BSWAP: 1441 case ISD::FADD: 1442 case ISD::FCOPYSIGN: 1443 case ISD::FDIV: 1444 case ISD::FMUL: 1445 case ISD::FPOW: 1446 case ISD::FREM: 1447 case ISD::FSUB: 1448 case ISD::MUL: 1449 case ISD::MULHS: 1450 case ISD::MULHU: 1451 case ISD::OR: 1452 case ISD::SDIV: 1453 case ISD::SREM: 1454 case ISD::UDIV: 1455 case ISD::UREM: 1456 case ISD::SUB: 1457 case ISD::XOR: 1458 Res = WidenVecRes_Binary(N); 1459 break; 1460 1461 case ISD::FPOWI: 1462 Res = WidenVecRes_POWI(N); 1463 break; 1464 1465 case ISD::SHL: 1466 case ISD::SRA: 1467 case ISD::SRL: 1468 Res = WidenVecRes_Shift(N); 1469 break; 1470 1471 case ISD::ANY_EXTEND: 1472 case ISD::FP_EXTEND: 1473 case ISD::FP_ROUND: 1474 case ISD::FP_TO_SINT: 1475 case ISD::FP_TO_UINT: 1476 case ISD::SIGN_EXTEND: 1477 case ISD::SINT_TO_FP: 1478 case ISD::TRUNCATE: 1479 case ISD::UINT_TO_FP: 1480 case ISD::ZERO_EXTEND: 1481 Res = WidenVecRes_Convert(N); 1482 break; 1483 1484 case ISD::CTLZ: 1485 case ISD::CTPOP: 1486 case ISD::CTTZ: 1487 case ISD::FABS: 1488 case ISD::FCEIL: 1489 case ISD::FCOS: 1490 case ISD::FEXP: 1491 case ISD::FEXP2: 1492 case ISD::FFLOOR: 1493 case ISD::FLOG: 1494 case ISD::FLOG10: 1495 case ISD::FLOG2: 1496 case ISD::FNEARBYINT: 1497 case ISD::FNEG: 1498 case ISD::FRINT: 1499 case ISD::FSIN: 1500 case ISD::FSQRT: 1501 case ISD::FTRUNC: 1502 Res = WidenVecRes_Unary(N); 1503 break; 1504 case ISD::FMA: 1505 Res = WidenVecRes_Ternary(N); 1506 break; 1507 } 1508 1509 // If Res is null, the sub-method took care of registering the result. 1510 if (Res.getNode()) 1511 SetWidenedVector(SDValue(N, ResNo), Res); 1512} 1513 1514SDValue DAGTypeLegalizer::WidenVecRes_Ternary(SDNode *N) { 1515 // Ternary op widening. 1516 SDLoc dl(N); 1517 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1518 SDValue InOp1 = GetWidenedVector(N->getOperand(0)); 1519 SDValue InOp2 = GetWidenedVector(N->getOperand(1)); 1520 SDValue InOp3 = GetWidenedVector(N->getOperand(2)); 1521 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2, InOp3); 1522} 1523 1524SDValue DAGTypeLegalizer::WidenVecRes_Binary(SDNode *N) { 1525 // Binary op widening. 1526 unsigned Opcode = N->getOpcode(); 1527 SDLoc dl(N); 1528 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1529 EVT WidenEltVT = WidenVT.getVectorElementType(); 1530 EVT VT = WidenVT; 1531 unsigned NumElts = VT.getVectorNumElements(); 1532 while (!TLI.isTypeLegal(VT) && NumElts != 1) { 1533 NumElts = NumElts / 2; 1534 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts); 1535 } 1536 1537 if (NumElts != 1 && !TLI.canOpTrap(N->getOpcode(), VT)) { 1538 // Operation doesn't trap so just widen as normal. 1539 SDValue InOp1 = GetWidenedVector(N->getOperand(0)); 1540 SDValue InOp2 = GetWidenedVector(N->getOperand(1)); 1541 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2); 1542 } 1543 1544 // No legal vector version so unroll the vector operation and then widen. 1545 if (NumElts == 1) 1546 return DAG.UnrollVectorOp(N, WidenVT.getVectorNumElements()); 1547 1548 // Since the operation can trap, apply operation on the original vector. 1549 EVT MaxVT = VT; 1550 SDValue InOp1 = GetWidenedVector(N->getOperand(0)); 1551 SDValue InOp2 = GetWidenedVector(N->getOperand(1)); 1552 unsigned CurNumElts = N->getValueType(0).getVectorNumElements(); 1553 1554 SmallVector<SDValue, 16> ConcatOps(CurNumElts); 1555 unsigned ConcatEnd = 0; // Current ConcatOps index. 1556 int Idx = 0; // Current Idx into input vectors. 1557 1558 // NumElts := greatest legal vector size (at most WidenVT) 1559 // while (orig. vector has unhandled elements) { 1560 // take munches of size NumElts from the beginning and add to ConcatOps 1561 // NumElts := next smaller supported vector size or 1 1562 // } 1563 while (CurNumElts != 0) { 1564 while (CurNumElts >= NumElts) { 1565 SDValue EOp1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp1, 1566 DAG.getIntPtrConstant(Idx)); 1567 SDValue EOp2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp2, 1568 DAG.getIntPtrConstant(Idx)); 1569 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, VT, EOp1, EOp2); 1570 Idx += NumElts; 1571 CurNumElts -= NumElts; 1572 } 1573 do { 1574 NumElts = NumElts / 2; 1575 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts); 1576 } while (!TLI.isTypeLegal(VT) && NumElts != 1); 1577 1578 if (NumElts == 1) { 1579 for (unsigned i = 0; i != CurNumElts; ++i, ++Idx) { 1580 SDValue EOp1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT, 1581 InOp1, DAG.getIntPtrConstant(Idx)); 1582 SDValue EOp2 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT, 1583 InOp2, DAG.getIntPtrConstant(Idx)); 1584 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, WidenEltVT, 1585 EOp1, EOp2); 1586 } 1587 CurNumElts = 0; 1588 } 1589 } 1590 1591 // Check to see if we have a single operation with the widen type. 1592 if (ConcatEnd == 1) { 1593 VT = ConcatOps[0].getValueType(); 1594 if (VT == WidenVT) 1595 return ConcatOps[0]; 1596 } 1597 1598 // while (Some element of ConcatOps is not of type MaxVT) { 1599 // From the end of ConcatOps, collect elements of the same type and put 1600 // them into an op of the next larger supported type 1601 // } 1602 while (ConcatOps[ConcatEnd-1].getValueType() != MaxVT) { 1603 Idx = ConcatEnd - 1; 1604 VT = ConcatOps[Idx--].getValueType(); 1605 while (Idx >= 0 && ConcatOps[Idx].getValueType() == VT) 1606 Idx--; 1607 1608 int NextSize = VT.isVector() ? VT.getVectorNumElements() : 1; 1609 EVT NextVT; 1610 do { 1611 NextSize *= 2; 1612 NextVT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NextSize); 1613 } while (!TLI.isTypeLegal(NextVT)); 1614 1615 if (!VT.isVector()) { 1616 // Scalar type, create an INSERT_VECTOR_ELEMENT of type NextVT 1617 SDValue VecOp = DAG.getUNDEF(NextVT); 1618 unsigned NumToInsert = ConcatEnd - Idx - 1; 1619 for (unsigned i = 0, OpIdx = Idx+1; i < NumToInsert; i++, OpIdx++) { 1620 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NextVT, VecOp, 1621 ConcatOps[OpIdx], DAG.getIntPtrConstant(i)); 1622 } 1623 ConcatOps[Idx+1] = VecOp; 1624 ConcatEnd = Idx + 2; 1625 } else { 1626 // Vector type, create a CONCAT_VECTORS of type NextVT 1627 SDValue undefVec = DAG.getUNDEF(VT); 1628 unsigned OpsToConcat = NextSize/VT.getVectorNumElements(); 1629 SmallVector<SDValue, 16> SubConcatOps(OpsToConcat); 1630 unsigned RealVals = ConcatEnd - Idx - 1; 1631 unsigned SubConcatEnd = 0; 1632 unsigned SubConcatIdx = Idx + 1; 1633 while (SubConcatEnd < RealVals) 1634 SubConcatOps[SubConcatEnd++] = ConcatOps[++Idx]; 1635 while (SubConcatEnd < OpsToConcat) 1636 SubConcatOps[SubConcatEnd++] = undefVec; 1637 ConcatOps[SubConcatIdx] = DAG.getNode(ISD::CONCAT_VECTORS, dl, 1638 NextVT, &SubConcatOps[0], 1639 OpsToConcat); 1640 ConcatEnd = SubConcatIdx + 1; 1641 } 1642 } 1643 1644 // Check to see if we have a single operation with the widen type. 1645 if (ConcatEnd == 1) { 1646 VT = ConcatOps[0].getValueType(); 1647 if (VT == WidenVT) 1648 return ConcatOps[0]; 1649 } 1650 1651 // add undefs of size MaxVT until ConcatOps grows to length of WidenVT 1652 unsigned NumOps = WidenVT.getVectorNumElements()/MaxVT.getVectorNumElements(); 1653 if (NumOps != ConcatEnd ) { 1654 SDValue UndefVal = DAG.getUNDEF(MaxVT); 1655 for (unsigned j = ConcatEnd; j < NumOps; ++j) 1656 ConcatOps[j] = UndefVal; 1657 } 1658 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &ConcatOps[0], NumOps); 1659} 1660 1661SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) { 1662 SDValue InOp = N->getOperand(0); 1663 SDLoc DL(N); 1664 1665 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1666 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 1667 1668 EVT InVT = InOp.getValueType(); 1669 EVT InEltVT = InVT.getVectorElementType(); 1670 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts); 1671 1672 unsigned Opcode = N->getOpcode(); 1673 unsigned InVTNumElts = InVT.getVectorNumElements(); 1674 1675 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) { 1676 InOp = GetWidenedVector(N->getOperand(0)); 1677 InVT = InOp.getValueType(); 1678 InVTNumElts = InVT.getVectorNumElements(); 1679 if (InVTNumElts == WidenNumElts) { 1680 if (N->getNumOperands() == 1) 1681 return DAG.getNode(Opcode, DL, WidenVT, InOp); 1682 return DAG.getNode(Opcode, DL, WidenVT, InOp, N->getOperand(1)); 1683 } 1684 } 1685 1686 if (TLI.isTypeLegal(InWidenVT)) { 1687 // Because the result and the input are different vector types, widening 1688 // the result could create a legal type but widening the input might make 1689 // it an illegal type that might lead to repeatedly splitting the input 1690 // and then widening it. To avoid this, we widen the input only if 1691 // it results in a legal type. 1692 if (WidenNumElts % InVTNumElts == 0) { 1693 // Widen the input and call convert on the widened input vector. 1694 unsigned NumConcat = WidenNumElts/InVTNumElts; 1695 SmallVector<SDValue, 16> Ops(NumConcat); 1696 Ops[0] = InOp; 1697 SDValue UndefVal = DAG.getUNDEF(InVT); 1698 for (unsigned i = 1; i != NumConcat; ++i) 1699 Ops[i] = UndefVal; 1700 SDValue InVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InWidenVT, 1701 &Ops[0], NumConcat); 1702 if (N->getNumOperands() == 1) 1703 return DAG.getNode(Opcode, DL, WidenVT, InVec); 1704 return DAG.getNode(Opcode, DL, WidenVT, InVec, N->getOperand(1)); 1705 } 1706 1707 if (InVTNumElts % WidenNumElts == 0) { 1708 SDValue InVal = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InWidenVT, 1709 InOp, DAG.getIntPtrConstant(0)); 1710 // Extract the input and convert the shorten input vector. 1711 if (N->getNumOperands() == 1) 1712 return DAG.getNode(Opcode, DL, WidenVT, InVal); 1713 return DAG.getNode(Opcode, DL, WidenVT, InVal, N->getOperand(1)); 1714 } 1715 } 1716 1717 // Otherwise unroll into some nasty scalar code and rebuild the vector. 1718 SmallVector<SDValue, 16> Ops(WidenNumElts); 1719 EVT EltVT = WidenVT.getVectorElementType(); 1720 unsigned MinElts = std::min(InVTNumElts, WidenNumElts); 1721 unsigned i; 1722 for (i=0; i < MinElts; ++i) { 1723 SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, InEltVT, InOp, 1724 DAG.getIntPtrConstant(i)); 1725 if (N->getNumOperands() == 1) 1726 Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val); 1727 else 1728 Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val, N->getOperand(1)); 1729 } 1730 1731 SDValue UndefVal = DAG.getUNDEF(EltVT); 1732 for (; i < WidenNumElts; ++i) 1733 Ops[i] = UndefVal; 1734 1735 return DAG.getNode(ISD::BUILD_VECTOR, DL, WidenVT, &Ops[0], WidenNumElts); 1736} 1737 1738SDValue DAGTypeLegalizer::WidenVecRes_POWI(SDNode *N) { 1739 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1740 SDValue InOp = GetWidenedVector(N->getOperand(0)); 1741 SDValue ShOp = N->getOperand(1); 1742 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp, ShOp); 1743} 1744 1745SDValue DAGTypeLegalizer::WidenVecRes_Shift(SDNode *N) { 1746 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1747 SDValue InOp = GetWidenedVector(N->getOperand(0)); 1748 SDValue ShOp = N->getOperand(1); 1749 1750 EVT ShVT = ShOp.getValueType(); 1751 if (getTypeAction(ShVT) == TargetLowering::TypeWidenVector) { 1752 ShOp = GetWidenedVector(ShOp); 1753 ShVT = ShOp.getValueType(); 1754 } 1755 EVT ShWidenVT = EVT::getVectorVT(*DAG.getContext(), 1756 ShVT.getVectorElementType(), 1757 WidenVT.getVectorNumElements()); 1758 if (ShVT != ShWidenVT) 1759 ShOp = ModifyToType(ShOp, ShWidenVT); 1760 1761 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp, ShOp); 1762} 1763 1764SDValue DAGTypeLegalizer::WidenVecRes_Unary(SDNode *N) { 1765 // Unary op widening. 1766 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1767 SDValue InOp = GetWidenedVector(N->getOperand(0)); 1768 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp); 1769} 1770 1771SDValue DAGTypeLegalizer::WidenVecRes_InregOp(SDNode *N) { 1772 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1773 EVT ExtVT = EVT::getVectorVT(*DAG.getContext(), 1774 cast<VTSDNode>(N->getOperand(1))->getVT() 1775 .getVectorElementType(), 1776 WidenVT.getVectorNumElements()); 1777 SDValue WidenLHS = GetWidenedVector(N->getOperand(0)); 1778 return DAG.getNode(N->getOpcode(), SDLoc(N), 1779 WidenVT, WidenLHS, DAG.getValueType(ExtVT)); 1780} 1781 1782SDValue DAGTypeLegalizer::WidenVecRes_MERGE_VALUES(SDNode *N, unsigned ResNo) { 1783 SDValue WidenVec = DisintegrateMERGE_VALUES(N, ResNo); 1784 return GetWidenedVector(WidenVec); 1785} 1786 1787SDValue DAGTypeLegalizer::WidenVecRes_BITCAST(SDNode *N) { 1788 SDValue InOp = N->getOperand(0); 1789 EVT InVT = InOp.getValueType(); 1790 EVT VT = N->getValueType(0); 1791 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); 1792 SDLoc dl(N); 1793 1794 switch (getTypeAction(InVT)) { 1795 case TargetLowering::TypeLegal: 1796 break; 1797 case TargetLowering::TypePromoteInteger: 1798 // If the incoming type is a vector that is being promoted, then 1799 // we know that the elements are arranged differently and that we 1800 // must perform the conversion using a stack slot. 1801 if (InVT.isVector()) 1802 break; 1803 1804 // If the InOp is promoted to the same size, convert it. Otherwise, 1805 // fall out of the switch and widen the promoted input. 1806 InOp = GetPromotedInteger(InOp); 1807 InVT = InOp.getValueType(); 1808 if (WidenVT.bitsEq(InVT)) 1809 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp); 1810 break; 1811 case TargetLowering::TypeSoftenFloat: 1812 case TargetLowering::TypeExpandInteger: 1813 case TargetLowering::TypeExpandFloat: 1814 case TargetLowering::TypeScalarizeVector: 1815 case TargetLowering::TypeSplitVector: 1816 break; 1817 case TargetLowering::TypeWidenVector: 1818 // If the InOp is widened to the same size, convert it. Otherwise, fall 1819 // out of the switch and widen the widened input. 1820 InOp = GetWidenedVector(InOp); 1821 InVT = InOp.getValueType(); 1822 if (WidenVT.bitsEq(InVT)) 1823 // The input widens to the same size. Convert to the widen value. 1824 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp); 1825 break; 1826 } 1827 1828 unsigned WidenSize = WidenVT.getSizeInBits(); 1829 unsigned InSize = InVT.getSizeInBits(); 1830 // x86mmx is not an acceptable vector element type, so don't try. 1831 if (WidenSize % InSize == 0 && InVT != MVT::x86mmx) { 1832 // Determine new input vector type. The new input vector type will use 1833 // the same element type (if its a vector) or use the input type as a 1834 // vector. It is the same size as the type to widen to. 1835 EVT NewInVT; 1836 unsigned NewNumElts = WidenSize / InSize; 1837 if (InVT.isVector()) { 1838 EVT InEltVT = InVT.getVectorElementType(); 1839 NewInVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, 1840 WidenSize / InEltVT.getSizeInBits()); 1841 } else { 1842 NewInVT = EVT::getVectorVT(*DAG.getContext(), InVT, NewNumElts); 1843 } 1844 1845 if (TLI.isTypeLegal(NewInVT)) { 1846 // Because the result and the input are different vector types, widening 1847 // the result could create a legal type but widening the input might make 1848 // it an illegal type that might lead to repeatedly splitting the input 1849 // and then widening it. To avoid this, we widen the input only if 1850 // it results in a legal type. 1851 SmallVector<SDValue, 16> Ops(NewNumElts); 1852 SDValue UndefVal = DAG.getUNDEF(InVT); 1853 Ops[0] = InOp; 1854 for (unsigned i = 1; i < NewNumElts; ++i) 1855 Ops[i] = UndefVal; 1856 1857 SDValue NewVec; 1858 if (InVT.isVector()) 1859 NewVec = DAG.getNode(ISD::CONCAT_VECTORS, dl, 1860 NewInVT, &Ops[0], NewNumElts); 1861 else 1862 NewVec = DAG.getNode(ISD::BUILD_VECTOR, dl, 1863 NewInVT, &Ops[0], NewNumElts); 1864 return DAG.getNode(ISD::BITCAST, dl, WidenVT, NewVec); 1865 } 1866 } 1867 1868 return CreateStackStoreLoad(InOp, WidenVT); 1869} 1870 1871SDValue DAGTypeLegalizer::WidenVecRes_BUILD_VECTOR(SDNode *N) { 1872 SDLoc dl(N); 1873 // Build a vector with undefined for the new nodes. 1874 EVT VT = N->getValueType(0); 1875 EVT EltVT = VT.getVectorElementType(); 1876 unsigned NumElts = VT.getVectorNumElements(); 1877 1878 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); 1879 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 1880 1881 SmallVector<SDValue, 16> NewOps(N->op_begin(), N->op_end()); 1882 assert(WidenNumElts >= NumElts && "Shrinking vector instead of widening!"); 1883 NewOps.append(WidenNumElts - NumElts, DAG.getUNDEF(EltVT)); 1884 1885 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &NewOps[0], NewOps.size()); 1886} 1887 1888SDValue DAGTypeLegalizer::WidenVecRes_CONCAT_VECTORS(SDNode *N) { 1889 EVT InVT = N->getOperand(0).getValueType(); 1890 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1891 SDLoc dl(N); 1892 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 1893 unsigned NumInElts = InVT.getVectorNumElements(); 1894 unsigned NumOperands = N->getNumOperands(); 1895 1896 bool InputWidened = false; // Indicates we need to widen the input. 1897 if (getTypeAction(InVT) != TargetLowering::TypeWidenVector) { 1898 if (WidenVT.getVectorNumElements() % InVT.getVectorNumElements() == 0) { 1899 // Add undef vectors to widen to correct length. 1900 unsigned NumConcat = WidenVT.getVectorNumElements() / 1901 InVT.getVectorNumElements(); 1902 SDValue UndefVal = DAG.getUNDEF(InVT); 1903 SmallVector<SDValue, 16> Ops(NumConcat); 1904 for (unsigned i=0; i < NumOperands; ++i) 1905 Ops[i] = N->getOperand(i); 1906 for (unsigned i = NumOperands; i != NumConcat; ++i) 1907 Ops[i] = UndefVal; 1908 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &Ops[0], NumConcat); 1909 } 1910 } else { 1911 InputWidened = true; 1912 if (WidenVT == TLI.getTypeToTransformTo(*DAG.getContext(), InVT)) { 1913 // The inputs and the result are widen to the same value. 1914 unsigned i; 1915 for (i=1; i < NumOperands; ++i) 1916 if (N->getOperand(i).getOpcode() != ISD::UNDEF) 1917 break; 1918 1919 if (i == NumOperands) 1920 // Everything but the first operand is an UNDEF so just return the 1921 // widened first operand. 1922 return GetWidenedVector(N->getOperand(0)); 1923 1924 if (NumOperands == 2) { 1925 // Replace concat of two operands with a shuffle. 1926 SmallVector<int, 16> MaskOps(WidenNumElts, -1); 1927 for (unsigned i = 0; i < NumInElts; ++i) { 1928 MaskOps[i] = i; 1929 MaskOps[i + NumInElts] = i + WidenNumElts; 1930 } 1931 return DAG.getVectorShuffle(WidenVT, dl, 1932 GetWidenedVector(N->getOperand(0)), 1933 GetWidenedVector(N->getOperand(1)), 1934 &MaskOps[0]); 1935 } 1936 } 1937 } 1938 1939 // Fall back to use extracts and build vector. 1940 EVT EltVT = WidenVT.getVectorElementType(); 1941 SmallVector<SDValue, 16> Ops(WidenNumElts); 1942 unsigned Idx = 0; 1943 for (unsigned i=0; i < NumOperands; ++i) { 1944 SDValue InOp = N->getOperand(i); 1945 if (InputWidened) 1946 InOp = GetWidenedVector(InOp); 1947 for (unsigned j=0; j < NumInElts; ++j) 1948 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp, 1949 DAG.getIntPtrConstant(j)); 1950 } 1951 SDValue UndefVal = DAG.getUNDEF(EltVT); 1952 for (; Idx < WidenNumElts; ++Idx) 1953 Ops[Idx] = UndefVal; 1954 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts); 1955} 1956 1957SDValue DAGTypeLegalizer::WidenVecRes_CONVERT_RNDSAT(SDNode *N) { 1958 SDLoc dl(N); 1959 SDValue InOp = N->getOperand(0); 1960 SDValue RndOp = N->getOperand(3); 1961 SDValue SatOp = N->getOperand(4); 1962 1963 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1964 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 1965 1966 EVT InVT = InOp.getValueType(); 1967 EVT InEltVT = InVT.getVectorElementType(); 1968 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts); 1969 1970 SDValue DTyOp = DAG.getValueType(WidenVT); 1971 SDValue STyOp = DAG.getValueType(InWidenVT); 1972 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode(); 1973 1974 unsigned InVTNumElts = InVT.getVectorNumElements(); 1975 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) { 1976 InOp = GetWidenedVector(InOp); 1977 InVT = InOp.getValueType(); 1978 InVTNumElts = InVT.getVectorNumElements(); 1979 if (InVTNumElts == WidenNumElts) 1980 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp, 1981 SatOp, CvtCode); 1982 } 1983 1984 if (TLI.isTypeLegal(InWidenVT)) { 1985 // Because the result and the input are different vector types, widening 1986 // the result could create a legal type but widening the input might make 1987 // it an illegal type that might lead to repeatedly splitting the input 1988 // and then widening it. To avoid this, we widen the input only if 1989 // it results in a legal type. 1990 if (WidenNumElts % InVTNumElts == 0) { 1991 // Widen the input and call convert on the widened input vector. 1992 unsigned NumConcat = WidenNumElts/InVTNumElts; 1993 SmallVector<SDValue, 16> Ops(NumConcat); 1994 Ops[0] = InOp; 1995 SDValue UndefVal = DAG.getUNDEF(InVT); 1996 for (unsigned i = 1; i != NumConcat; ++i) 1997 Ops[i] = UndefVal; 1998 1999 InOp = DAG.getNode(ISD::CONCAT_VECTORS, dl, InWidenVT, &Ops[0],NumConcat); 2000 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp, 2001 SatOp, CvtCode); 2002 } 2003 2004 if (InVTNumElts % WidenNumElts == 0) { 2005 // Extract the input and convert the shorten input vector. 2006 InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InWidenVT, InOp, 2007 DAG.getIntPtrConstant(0)); 2008 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp, 2009 SatOp, CvtCode); 2010 } 2011 } 2012 2013 // Otherwise unroll into some nasty scalar code and rebuild the vector. 2014 SmallVector<SDValue, 16> Ops(WidenNumElts); 2015 EVT EltVT = WidenVT.getVectorElementType(); 2016 DTyOp = DAG.getValueType(EltVT); 2017 STyOp = DAG.getValueType(InEltVT); 2018 2019 unsigned MinElts = std::min(InVTNumElts, WidenNumElts); 2020 unsigned i; 2021 for (i=0; i < MinElts; ++i) { 2022 SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp, 2023 DAG.getIntPtrConstant(i)); 2024 Ops[i] = DAG.getConvertRndSat(WidenVT, dl, ExtVal, DTyOp, STyOp, RndOp, 2025 SatOp, CvtCode); 2026 } 2027 2028 SDValue UndefVal = DAG.getUNDEF(EltVT); 2029 for (; i < WidenNumElts; ++i) 2030 Ops[i] = UndefVal; 2031 2032 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts); 2033} 2034 2035SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) { 2036 EVT VT = N->getValueType(0); 2037 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); 2038 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 2039 SDValue InOp = N->getOperand(0); 2040 SDValue Idx = N->getOperand(1); 2041 SDLoc dl(N); 2042 2043 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector) 2044 InOp = GetWidenedVector(InOp); 2045 2046 EVT InVT = InOp.getValueType(); 2047 2048 // Check if we can just return the input vector after widening. 2049 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 2050 if (IdxVal == 0 && InVT == WidenVT) 2051 return InOp; 2052 2053 // Check if we can extract from the vector. 2054 unsigned InNumElts = InVT.getVectorNumElements(); 2055 if (IdxVal % WidenNumElts == 0 && IdxVal + WidenNumElts < InNumElts) 2056 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, WidenVT, InOp, Idx); 2057 2058 // We could try widening the input to the right length but for now, extract 2059 // the original elements, fill the rest with undefs and build a vector. 2060 SmallVector<SDValue, 16> Ops(WidenNumElts); 2061 EVT EltVT = VT.getVectorElementType(); 2062 unsigned NumElts = VT.getVectorNumElements(); 2063 unsigned i; 2064 for (i=0; i < NumElts; ++i) 2065 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp, 2066 DAG.getIntPtrConstant(IdxVal+i)); 2067 2068 SDValue UndefVal = DAG.getUNDEF(EltVT); 2069 for (; i < WidenNumElts; ++i) 2070 Ops[i] = UndefVal; 2071 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts); 2072} 2073 2074SDValue DAGTypeLegalizer::WidenVecRes_INSERT_VECTOR_ELT(SDNode *N) { 2075 SDValue InOp = GetWidenedVector(N->getOperand(0)); 2076 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N), 2077 InOp.getValueType(), InOp, 2078 N->getOperand(1), N->getOperand(2)); 2079} 2080 2081SDValue DAGTypeLegalizer::WidenVecRes_LOAD(SDNode *N) { 2082 LoadSDNode *LD = cast<LoadSDNode>(N); 2083 ISD::LoadExtType ExtType = LD->getExtensionType(); 2084 2085 SDValue Result; 2086 SmallVector<SDValue, 16> LdChain; // Chain for the series of load 2087 if (ExtType != ISD::NON_EXTLOAD) 2088 Result = GenWidenVectorExtLoads(LdChain, LD, ExtType); 2089 else 2090 Result = GenWidenVectorLoads(LdChain, LD); 2091 2092 // If we generate a single load, we can use that for the chain. Otherwise, 2093 // build a factor node to remember the multiple loads are independent and 2094 // chain to that. 2095 SDValue NewChain; 2096 if (LdChain.size() == 1) 2097 NewChain = LdChain[0]; 2098 else 2099 NewChain = DAG.getNode(ISD::TokenFactor, SDLoc(LD), MVT::Other, 2100 &LdChain[0], LdChain.size()); 2101 2102 // Modified the chain - switch anything that used the old chain to use 2103 // the new one. 2104 ReplaceValueWith(SDValue(N, 1), NewChain); 2105 2106 return Result; 2107} 2108 2109SDValue DAGTypeLegalizer::WidenVecRes_SCALAR_TO_VECTOR(SDNode *N) { 2110 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 2111 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), 2112 WidenVT, N->getOperand(0)); 2113} 2114 2115SDValue DAGTypeLegalizer::WidenVecRes_SELECT(SDNode *N) { 2116 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 2117 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 2118 2119 SDValue Cond1 = N->getOperand(0); 2120 EVT CondVT = Cond1.getValueType(); 2121 if (CondVT.isVector()) { 2122 EVT CondEltVT = CondVT.getVectorElementType(); 2123 EVT CondWidenVT = EVT::getVectorVT(*DAG.getContext(), 2124 CondEltVT, WidenNumElts); 2125 if (getTypeAction(CondVT) == TargetLowering::TypeWidenVector) 2126 Cond1 = GetWidenedVector(Cond1); 2127 2128 if (Cond1.getValueType() != CondWidenVT) 2129 Cond1 = ModifyToType(Cond1, CondWidenVT); 2130 } 2131 2132 SDValue InOp1 = GetWidenedVector(N->getOperand(1)); 2133 SDValue InOp2 = GetWidenedVector(N->getOperand(2)); 2134 assert(InOp1.getValueType() == WidenVT && InOp2.getValueType() == WidenVT); 2135 return DAG.getNode(N->getOpcode(), SDLoc(N), 2136 WidenVT, Cond1, InOp1, InOp2); 2137} 2138 2139SDValue DAGTypeLegalizer::WidenVecRes_SELECT_CC(SDNode *N) { 2140 SDValue InOp1 = GetWidenedVector(N->getOperand(2)); 2141 SDValue InOp2 = GetWidenedVector(N->getOperand(3)); 2142 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), 2143 InOp1.getValueType(), N->getOperand(0), 2144 N->getOperand(1), InOp1, InOp2, N->getOperand(4)); 2145} 2146 2147SDValue DAGTypeLegalizer::WidenVecRes_SETCC(SDNode *N) { 2148 assert(N->getValueType(0).isVector() == 2149 N->getOperand(0).getValueType().isVector() && 2150 "Scalar/Vector type mismatch"); 2151 if (N->getValueType(0).isVector()) return WidenVecRes_VSETCC(N); 2152 2153 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 2154 SDValue InOp1 = GetWidenedVector(N->getOperand(0)); 2155 SDValue InOp2 = GetWidenedVector(N->getOperand(1)); 2156 return DAG.getNode(ISD::SETCC, SDLoc(N), WidenVT, 2157 InOp1, InOp2, N->getOperand(2)); 2158} 2159 2160SDValue DAGTypeLegalizer::WidenVecRes_UNDEF(SDNode *N) { 2161 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 2162 return DAG.getUNDEF(WidenVT); 2163} 2164 2165SDValue DAGTypeLegalizer::WidenVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N) { 2166 EVT VT = N->getValueType(0); 2167 SDLoc dl(N); 2168 2169 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); 2170 unsigned NumElts = VT.getVectorNumElements(); 2171 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 2172 2173 SDValue InOp1 = GetWidenedVector(N->getOperand(0)); 2174 SDValue InOp2 = GetWidenedVector(N->getOperand(1)); 2175 2176 // Adjust mask based on new input vector length. 2177 SmallVector<int, 16> NewMask; 2178 for (unsigned i = 0; i != NumElts; ++i) { 2179 int Idx = N->getMaskElt(i); 2180 if (Idx < (int)NumElts) 2181 NewMask.push_back(Idx); 2182 else 2183 NewMask.push_back(Idx - NumElts + WidenNumElts); 2184 } 2185 for (unsigned i = NumElts; i != WidenNumElts; ++i) 2186 NewMask.push_back(-1); 2187 return DAG.getVectorShuffle(WidenVT, dl, InOp1, InOp2, &NewMask[0]); 2188} 2189 2190SDValue DAGTypeLegalizer::WidenVecRes_VSETCC(SDNode *N) { 2191 assert(N->getValueType(0).isVector() && 2192 N->getOperand(0).getValueType().isVector() && 2193 "Operands must be vectors"); 2194 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 2195 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 2196 2197 SDValue InOp1 = N->getOperand(0); 2198 EVT InVT = InOp1.getValueType(); 2199 assert(InVT.isVector() && "can not widen non vector type"); 2200 EVT WidenInVT = EVT::getVectorVT(*DAG.getContext(), 2201 InVT.getVectorElementType(), WidenNumElts); 2202 InOp1 = GetWidenedVector(InOp1); 2203 SDValue InOp2 = GetWidenedVector(N->getOperand(1)); 2204 2205 // Assume that the input and output will be widen appropriately. If not, 2206 // we will have to unroll it at some point. 2207 assert(InOp1.getValueType() == WidenInVT && 2208 InOp2.getValueType() == WidenInVT && 2209 "Input not widened to expected type!"); 2210 (void)WidenInVT; 2211 return DAG.getNode(ISD::SETCC, SDLoc(N), 2212 WidenVT, InOp1, InOp2, N->getOperand(2)); 2213} 2214 2215 2216//===----------------------------------------------------------------------===// 2217// Widen Vector Operand 2218//===----------------------------------------------------------------------===// 2219bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned OpNo) { 2220 DEBUG(dbgs() << "Widen node operand " << OpNo << ": "; 2221 N->dump(&DAG); 2222 dbgs() << "\n"); 2223 SDValue Res = SDValue(); 2224 2225 // See if the target wants to custom widen this node. 2226 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false)) 2227 return false; 2228 2229 switch (N->getOpcode()) { 2230 default: 2231#ifndef NDEBUG 2232 dbgs() << "WidenVectorOperand op #" << OpNo << ": "; 2233 N->dump(&DAG); 2234 dbgs() << "\n"; 2235#endif 2236 llvm_unreachable("Do not know how to widen this operator's operand!"); 2237 2238 case ISD::BITCAST: Res = WidenVecOp_BITCAST(N); break; 2239 case ISD::CONCAT_VECTORS: Res = WidenVecOp_CONCAT_VECTORS(N); break; 2240 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecOp_EXTRACT_SUBVECTOR(N); break; 2241 case ISD::EXTRACT_VECTOR_ELT: Res = WidenVecOp_EXTRACT_VECTOR_ELT(N); break; 2242 case ISD::STORE: Res = WidenVecOp_STORE(N); break; 2243 case ISD::SETCC: Res = WidenVecOp_SETCC(N); break; 2244 2245 case ISD::FP_EXTEND: 2246 case ISD::FP_TO_SINT: 2247 case ISD::FP_TO_UINT: 2248 case ISD::SINT_TO_FP: 2249 case ISD::UINT_TO_FP: 2250 case ISD::TRUNCATE: 2251 case ISD::SIGN_EXTEND: 2252 case ISD::ZERO_EXTEND: 2253 case ISD::ANY_EXTEND: 2254 Res = WidenVecOp_Convert(N); 2255 break; 2256 } 2257 2258 // If Res is null, the sub-method took care of registering the result. 2259 if (!Res.getNode()) return false; 2260 2261 // If the result is N, the sub-method updated N in place. Tell the legalizer 2262 // core about this. 2263 if (Res.getNode() == N) 2264 return true; 2265 2266 2267 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 2268 "Invalid operand expansion"); 2269 2270 ReplaceValueWith(SDValue(N, 0), Res); 2271 return false; 2272} 2273 2274SDValue DAGTypeLegalizer::WidenVecOp_Convert(SDNode *N) { 2275 // Since the result is legal and the input is illegal, it is unlikely 2276 // that we can fix the input to a legal type so unroll the convert 2277 // into some scalar code and create a nasty build vector. 2278 EVT VT = N->getValueType(0); 2279 EVT EltVT = VT.getVectorElementType(); 2280 SDLoc dl(N); 2281 unsigned NumElts = VT.getVectorNumElements(); 2282 SDValue InOp = N->getOperand(0); 2283 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector) 2284 InOp = GetWidenedVector(InOp); 2285 EVT InVT = InOp.getValueType(); 2286 EVT InEltVT = InVT.getVectorElementType(); 2287 2288 unsigned Opcode = N->getOpcode(); 2289 SmallVector<SDValue, 16> Ops(NumElts); 2290 for (unsigned i=0; i < NumElts; ++i) 2291 Ops[i] = DAG.getNode(Opcode, dl, EltVT, 2292 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp, 2293 DAG.getIntPtrConstant(i))); 2294 2295 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElts); 2296} 2297 2298SDValue DAGTypeLegalizer::WidenVecOp_BITCAST(SDNode *N) { 2299 EVT VT = N->getValueType(0); 2300 SDValue InOp = GetWidenedVector(N->getOperand(0)); 2301 EVT InWidenVT = InOp.getValueType(); 2302 SDLoc dl(N); 2303 2304 // Check if we can convert between two legal vector types and extract. 2305 unsigned InWidenSize = InWidenVT.getSizeInBits(); 2306 unsigned Size = VT.getSizeInBits(); 2307 // x86mmx is not an acceptable vector element type, so don't try. 2308 if (InWidenSize % Size == 0 && !VT.isVector() && VT != MVT::x86mmx) { 2309 unsigned NewNumElts = InWidenSize / Size; 2310 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), VT, NewNumElts); 2311 if (TLI.isTypeLegal(NewVT)) { 2312 SDValue BitOp = DAG.getNode(ISD::BITCAST, dl, NewVT, InOp); 2313 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, BitOp, 2314 DAG.getIntPtrConstant(0)); 2315 } 2316 } 2317 2318 return CreateStackStoreLoad(InOp, VT); 2319} 2320 2321SDValue DAGTypeLegalizer::WidenVecOp_CONCAT_VECTORS(SDNode *N) { 2322 // If the input vector is not legal, it is likely that we will not find a 2323 // legal vector of the same size. Replace the concatenate vector with a 2324 // nasty build vector. 2325 EVT VT = N->getValueType(0); 2326 EVT EltVT = VT.getVectorElementType(); 2327 SDLoc dl(N); 2328 unsigned NumElts = VT.getVectorNumElements(); 2329 SmallVector<SDValue, 16> Ops(NumElts); 2330 2331 EVT InVT = N->getOperand(0).getValueType(); 2332 unsigned NumInElts = InVT.getVectorNumElements(); 2333 2334 unsigned Idx = 0; 2335 unsigned NumOperands = N->getNumOperands(); 2336 for (unsigned i=0; i < NumOperands; ++i) { 2337 SDValue InOp = N->getOperand(i); 2338 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector) 2339 InOp = GetWidenedVector(InOp); 2340 for (unsigned j=0; j < NumInElts; ++j) 2341 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp, 2342 DAG.getIntPtrConstant(j)); 2343 } 2344 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElts); 2345} 2346 2347SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_SUBVECTOR(SDNode *N) { 2348 SDValue InOp = GetWidenedVector(N->getOperand(0)); 2349 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N), 2350 N->getValueType(0), InOp, N->getOperand(1)); 2351} 2352 2353SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_VECTOR_ELT(SDNode *N) { 2354 SDValue InOp = GetWidenedVector(N->getOperand(0)); 2355 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N), 2356 N->getValueType(0), InOp, N->getOperand(1)); 2357} 2358 2359SDValue DAGTypeLegalizer::WidenVecOp_STORE(SDNode *N) { 2360 // We have to widen the value but we want only to store the original 2361 // vector type. 2362 StoreSDNode *ST = cast<StoreSDNode>(N); 2363 2364 SmallVector<SDValue, 16> StChain; 2365 if (ST->isTruncatingStore()) 2366 GenWidenVectorTruncStores(StChain, ST); 2367 else 2368 GenWidenVectorStores(StChain, ST); 2369 2370 if (StChain.size() == 1) 2371 return StChain[0]; 2372 else 2373 return DAG.getNode(ISD::TokenFactor, SDLoc(ST), 2374 MVT::Other,&StChain[0],StChain.size()); 2375} 2376 2377SDValue DAGTypeLegalizer::WidenVecOp_SETCC(SDNode *N) { 2378 SDValue InOp0 = GetWidenedVector(N->getOperand(0)); 2379 SDValue InOp1 = GetWidenedVector(N->getOperand(1)); 2380 SDLoc dl(N); 2381 2382 // WARNING: In this code we widen the compare instruction with garbage. 2383 // This garbage may contain denormal floats which may be slow. Is this a real 2384 // concern ? Should we zero the unused lanes if this is a float compare ? 2385 2386 // Get a new SETCC node to compare the newly widened operands. 2387 // Only some of the compared elements are legal. 2388 EVT SVT = TLI.getSetCCResultType(*DAG.getContext(), InOp0.getValueType()); 2389 SDValue WideSETCC = DAG.getNode(ISD::SETCC, SDLoc(N), 2390 SVT, InOp0, InOp1, N->getOperand(2)); 2391 2392 // Extract the needed results from the result vector. 2393 EVT ResVT = EVT::getVectorVT(*DAG.getContext(), 2394 SVT.getVectorElementType(), 2395 N->getValueType(0).getVectorNumElements()); 2396 SDValue CC = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, 2397 ResVT, WideSETCC, DAG.getIntPtrConstant(0)); 2398 2399 return PromoteTargetBoolean(CC, N->getValueType(0)); 2400} 2401 2402 2403//===----------------------------------------------------------------------===// 2404// Vector Widening Utilities 2405//===----------------------------------------------------------------------===// 2406 2407// Utility function to find the type to chop up a widen vector for load/store 2408// TLI: Target lowering used to determine legal types. 2409// Width: Width left need to load/store. 2410// WidenVT: The widen vector type to load to/store from 2411// Align: If 0, don't allow use of a wider type 2412// WidenEx: If Align is not 0, the amount additional we can load/store from. 2413 2414static EVT FindMemType(SelectionDAG& DAG, const TargetLowering &TLI, 2415 unsigned Width, EVT WidenVT, 2416 unsigned Align = 0, unsigned WidenEx = 0) { 2417 EVT WidenEltVT = WidenVT.getVectorElementType(); 2418 unsigned WidenWidth = WidenVT.getSizeInBits(); 2419 unsigned WidenEltWidth = WidenEltVT.getSizeInBits(); 2420 unsigned AlignInBits = Align*8; 2421 2422 // If we have one element to load/store, return it. 2423 EVT RetVT = WidenEltVT; 2424 if (Width == WidenEltWidth) 2425 return RetVT; 2426 2427 // See if there is larger legal integer than the element type to load/store 2428 unsigned VT; 2429 for (VT = (unsigned)MVT::LAST_INTEGER_VALUETYPE; 2430 VT >= (unsigned)MVT::FIRST_INTEGER_VALUETYPE; --VT) { 2431 EVT MemVT((MVT::SimpleValueType) VT); 2432 unsigned MemVTWidth = MemVT.getSizeInBits(); 2433 if (MemVT.getSizeInBits() <= WidenEltWidth) 2434 break; 2435 if (TLI.isTypeLegal(MemVT) && (WidenWidth % MemVTWidth) == 0 && 2436 isPowerOf2_32(WidenWidth / MemVTWidth) && 2437 (MemVTWidth <= Width || 2438 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) { 2439 RetVT = MemVT; 2440 break; 2441 } 2442 } 2443 2444 // See if there is a larger vector type to load/store that has the same vector 2445 // element type and is evenly divisible with the WidenVT. 2446 for (VT = (unsigned)MVT::LAST_VECTOR_VALUETYPE; 2447 VT >= (unsigned)MVT::FIRST_VECTOR_VALUETYPE; --VT) { 2448 EVT MemVT = (MVT::SimpleValueType) VT; 2449 unsigned MemVTWidth = MemVT.getSizeInBits(); 2450 if (TLI.isTypeLegal(MemVT) && WidenEltVT == MemVT.getVectorElementType() && 2451 (WidenWidth % MemVTWidth) == 0 && 2452 isPowerOf2_32(WidenWidth / MemVTWidth) && 2453 (MemVTWidth <= Width || 2454 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) { 2455 if (RetVT.getSizeInBits() < MemVTWidth || MemVT == WidenVT) 2456 return MemVT; 2457 } 2458 } 2459 2460 return RetVT; 2461} 2462 2463// Builds a vector type from scalar loads 2464// VecTy: Resulting Vector type 2465// LDOps: Load operators to build a vector type 2466// [Start,End) the list of loads to use. 2467static SDValue BuildVectorFromScalar(SelectionDAG& DAG, EVT VecTy, 2468 SmallVector<SDValue, 16>& LdOps, 2469 unsigned Start, unsigned End) { 2470 SDLoc dl(LdOps[Start]); 2471 EVT LdTy = LdOps[Start].getValueType(); 2472 unsigned Width = VecTy.getSizeInBits(); 2473 unsigned NumElts = Width / LdTy.getSizeInBits(); 2474 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), LdTy, NumElts); 2475 2476 unsigned Idx = 1; 2477 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT,LdOps[Start]); 2478 2479 for (unsigned i = Start + 1; i != End; ++i) { 2480 EVT NewLdTy = LdOps[i].getValueType(); 2481 if (NewLdTy != LdTy) { 2482 NumElts = Width / NewLdTy.getSizeInBits(); 2483 NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewLdTy, NumElts); 2484 VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, VecOp); 2485 // Readjust position and vector position based on new load type 2486 Idx = Idx * LdTy.getSizeInBits() / NewLdTy.getSizeInBits(); 2487 LdTy = NewLdTy; 2488 } 2489 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, VecOp, LdOps[i], 2490 DAG.getIntPtrConstant(Idx++)); 2491 } 2492 return DAG.getNode(ISD::BITCAST, dl, VecTy, VecOp); 2493} 2494 2495SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVector<SDValue, 16> &LdChain, 2496 LoadSDNode *LD) { 2497 // The strategy assumes that we can efficiently load powers of two widths. 2498 // The routines chops the vector into the largest vector loads with the same 2499 // element type or scalar loads and then recombines it to the widen vector 2500 // type. 2501 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0)); 2502 unsigned WidenWidth = WidenVT.getSizeInBits(); 2503 EVT LdVT = LD->getMemoryVT(); 2504 SDLoc dl(LD); 2505 assert(LdVT.isVector() && WidenVT.isVector()); 2506 assert(LdVT.getVectorElementType() == WidenVT.getVectorElementType()); 2507 2508 // Load information 2509 SDValue Chain = LD->getChain(); 2510 SDValue BasePtr = LD->getBasePtr(); 2511 unsigned Align = LD->getAlignment(); 2512 bool isVolatile = LD->isVolatile(); 2513 bool isNonTemporal = LD->isNonTemporal(); 2514 bool isInvariant = LD->isInvariant(); 2515 2516 int LdWidth = LdVT.getSizeInBits(); 2517 int WidthDiff = WidenWidth - LdWidth; // Difference 2518 unsigned LdAlign = (isVolatile) ? 0 : Align; // Allow wider loads 2519 2520 // Find the vector type that can load from. 2521 EVT NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff); 2522 int NewVTWidth = NewVT.getSizeInBits(); 2523 SDValue LdOp = DAG.getLoad(NewVT, dl, Chain, BasePtr, LD->getPointerInfo(), 2524 isVolatile, isNonTemporal, isInvariant, Align); 2525 LdChain.push_back(LdOp.getValue(1)); 2526 2527 // Check if we can load the element with one instruction 2528 if (LdWidth <= NewVTWidth) { 2529 if (!NewVT.isVector()) { 2530 unsigned NumElts = WidenWidth / NewVTWidth; 2531 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts); 2532 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT, LdOp); 2533 return DAG.getNode(ISD::BITCAST, dl, WidenVT, VecOp); 2534 } 2535 if (NewVT == WidenVT) 2536 return LdOp; 2537 2538 assert(WidenWidth % NewVTWidth == 0); 2539 unsigned NumConcat = WidenWidth / NewVTWidth; 2540 SmallVector<SDValue, 16> ConcatOps(NumConcat); 2541 SDValue UndefVal = DAG.getUNDEF(NewVT); 2542 ConcatOps[0] = LdOp; 2543 for (unsigned i = 1; i != NumConcat; ++i) 2544 ConcatOps[i] = UndefVal; 2545 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &ConcatOps[0], 2546 NumConcat); 2547 } 2548 2549 // Load vector by using multiple loads from largest vector to scalar 2550 SmallVector<SDValue, 16> LdOps; 2551 LdOps.push_back(LdOp); 2552 2553 LdWidth -= NewVTWidth; 2554 unsigned Offset = 0; 2555 2556 while (LdWidth > 0) { 2557 unsigned Increment = NewVTWidth / 8; 2558 Offset += Increment; 2559 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, 2560 DAG.getIntPtrConstant(Increment)); 2561 2562 SDValue L; 2563 if (LdWidth < NewVTWidth) { 2564 // Our current type we are using is too large, find a better size 2565 NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff); 2566 NewVTWidth = NewVT.getSizeInBits(); 2567 L = DAG.getLoad(NewVT, dl, Chain, BasePtr, 2568 LD->getPointerInfo().getWithOffset(Offset), isVolatile, 2569 isNonTemporal, isInvariant, MinAlign(Align, Increment)); 2570 LdChain.push_back(L.getValue(1)); 2571 if (L->getValueType(0).isVector()) { 2572 SmallVector<SDValue, 16> Loads; 2573 Loads.push_back(L); 2574 unsigned size = L->getValueSizeInBits(0); 2575 while (size < LdOp->getValueSizeInBits(0)) { 2576 Loads.push_back(DAG.getUNDEF(L->getValueType(0))); 2577 size += L->getValueSizeInBits(0); 2578 } 2579 L = DAG.getNode(ISD::CONCAT_VECTORS, dl, LdOp->getValueType(0), 2580 &Loads[0], Loads.size()); 2581 } 2582 } else { 2583 L = DAG.getLoad(NewVT, dl, Chain, BasePtr, 2584 LD->getPointerInfo().getWithOffset(Offset), isVolatile, 2585 isNonTemporal, isInvariant, MinAlign(Align, Increment)); 2586 LdChain.push_back(L.getValue(1)); 2587 } 2588 2589 LdOps.push_back(L); 2590 2591 2592 LdWidth -= NewVTWidth; 2593 } 2594 2595 // Build the vector from the loads operations 2596 unsigned End = LdOps.size(); 2597 if (!LdOps[0].getValueType().isVector()) 2598 // All the loads are scalar loads. 2599 return BuildVectorFromScalar(DAG, WidenVT, LdOps, 0, End); 2600 2601 // If the load contains vectors, build the vector using concat vector. 2602 // All of the vectors used to loads are power of 2 and the scalars load 2603 // can be combined to make a power of 2 vector. 2604 SmallVector<SDValue, 16> ConcatOps(End); 2605 int i = End - 1; 2606 int Idx = End; 2607 EVT LdTy = LdOps[i].getValueType(); 2608 // First combine the scalar loads to a vector 2609 if (!LdTy.isVector()) { 2610 for (--i; i >= 0; --i) { 2611 LdTy = LdOps[i].getValueType(); 2612 if (LdTy.isVector()) 2613 break; 2614 } 2615 ConcatOps[--Idx] = BuildVectorFromScalar(DAG, LdTy, LdOps, i+1, End); 2616 } 2617 ConcatOps[--Idx] = LdOps[i]; 2618 for (--i; i >= 0; --i) { 2619 EVT NewLdTy = LdOps[i].getValueType(); 2620 if (NewLdTy != LdTy) { 2621 // Create a larger vector 2622 ConcatOps[End-1] = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewLdTy, 2623 &ConcatOps[Idx], End - Idx); 2624 Idx = End - 1; 2625 LdTy = NewLdTy; 2626 } 2627 ConcatOps[--Idx] = LdOps[i]; 2628 } 2629 2630 if (WidenWidth == LdTy.getSizeInBits()*(End - Idx)) 2631 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, 2632 &ConcatOps[Idx], End - Idx); 2633 2634 // We need to fill the rest with undefs to build the vector 2635 unsigned NumOps = WidenWidth / LdTy.getSizeInBits(); 2636 SmallVector<SDValue, 16> WidenOps(NumOps); 2637 SDValue UndefVal = DAG.getUNDEF(LdTy); 2638 { 2639 unsigned i = 0; 2640 for (; i != End-Idx; ++i) 2641 WidenOps[i] = ConcatOps[Idx+i]; 2642 for (; i != NumOps; ++i) 2643 WidenOps[i] = UndefVal; 2644 } 2645 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &WidenOps[0],NumOps); 2646} 2647 2648SDValue 2649DAGTypeLegalizer::GenWidenVectorExtLoads(SmallVector<SDValue, 16>& LdChain, 2650 LoadSDNode * LD, 2651 ISD::LoadExtType ExtType) { 2652 // For extension loads, it may not be more efficient to chop up the vector 2653 // and then extended it. Instead, we unroll the load and build a new vector. 2654 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0)); 2655 EVT LdVT = LD->getMemoryVT(); 2656 SDLoc dl(LD); 2657 assert(LdVT.isVector() && WidenVT.isVector()); 2658 2659 // Load information 2660 SDValue Chain = LD->getChain(); 2661 SDValue BasePtr = LD->getBasePtr(); 2662 unsigned Align = LD->getAlignment(); 2663 bool isVolatile = LD->isVolatile(); 2664 bool isNonTemporal = LD->isNonTemporal(); 2665 2666 EVT EltVT = WidenVT.getVectorElementType(); 2667 EVT LdEltVT = LdVT.getVectorElementType(); 2668 unsigned NumElts = LdVT.getVectorNumElements(); 2669 2670 // Load each element and widen 2671 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 2672 SmallVector<SDValue, 16> Ops(WidenNumElts); 2673 unsigned Increment = LdEltVT.getSizeInBits() / 8; 2674 Ops[0] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, BasePtr, 2675 LD->getPointerInfo(), 2676 LdEltVT, isVolatile, isNonTemporal, Align); 2677 LdChain.push_back(Ops[0].getValue(1)); 2678 unsigned i = 0, Offset = Increment; 2679 for (i=1; i < NumElts; ++i, Offset += Increment) { 2680 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), 2681 BasePtr, DAG.getIntPtrConstant(Offset)); 2682 Ops[i] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, NewBasePtr, 2683 LD->getPointerInfo().getWithOffset(Offset), LdEltVT, 2684 isVolatile, isNonTemporal, Align); 2685 LdChain.push_back(Ops[i].getValue(1)); 2686 } 2687 2688 // Fill the rest with undefs 2689 SDValue UndefVal = DAG.getUNDEF(EltVT); 2690 for (; i != WidenNumElts; ++i) 2691 Ops[i] = UndefVal; 2692 2693 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], Ops.size()); 2694} 2695 2696 2697void DAGTypeLegalizer::GenWidenVectorStores(SmallVector<SDValue, 16>& StChain, 2698 StoreSDNode *ST) { 2699 // The strategy assumes that we can efficiently store powers of two widths. 2700 // The routines chops the vector into the largest vector stores with the same 2701 // element type or scalar stores. 2702 SDValue Chain = ST->getChain(); 2703 SDValue BasePtr = ST->getBasePtr(); 2704 unsigned Align = ST->getAlignment(); 2705 bool isVolatile = ST->isVolatile(); 2706 bool isNonTemporal = ST->isNonTemporal(); 2707 SDValue ValOp = GetWidenedVector(ST->getValue()); 2708 SDLoc dl(ST); 2709 2710 EVT StVT = ST->getMemoryVT(); 2711 unsigned StWidth = StVT.getSizeInBits(); 2712 EVT ValVT = ValOp.getValueType(); 2713 unsigned ValWidth = ValVT.getSizeInBits(); 2714 EVT ValEltVT = ValVT.getVectorElementType(); 2715 unsigned ValEltWidth = ValEltVT.getSizeInBits(); 2716 assert(StVT.getVectorElementType() == ValEltVT); 2717 2718 int Idx = 0; // current index to store 2719 unsigned Offset = 0; // offset from base to store 2720 while (StWidth != 0) { 2721 // Find the largest vector type we can store with 2722 EVT NewVT = FindMemType(DAG, TLI, StWidth, ValVT); 2723 unsigned NewVTWidth = NewVT.getSizeInBits(); 2724 unsigned Increment = NewVTWidth / 8; 2725 if (NewVT.isVector()) { 2726 unsigned NumVTElts = NewVT.getVectorNumElements(); 2727 do { 2728 SDValue EOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT, ValOp, 2729 DAG.getIntPtrConstant(Idx)); 2730 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr, 2731 ST->getPointerInfo().getWithOffset(Offset), 2732 isVolatile, isNonTemporal, 2733 MinAlign(Align, Offset))); 2734 StWidth -= NewVTWidth; 2735 Offset += Increment; 2736 Idx += NumVTElts; 2737 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, 2738 DAG.getIntPtrConstant(Increment)); 2739 } while (StWidth != 0 && StWidth >= NewVTWidth); 2740 } else { 2741 // Cast the vector to the scalar type we can store 2742 unsigned NumElts = ValWidth / NewVTWidth; 2743 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts); 2744 SDValue VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, ValOp); 2745 // Readjust index position based on new vector type 2746 Idx = Idx * ValEltWidth / NewVTWidth; 2747 do { 2748 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, VecOp, 2749 DAG.getIntPtrConstant(Idx++)); 2750 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr, 2751 ST->getPointerInfo().getWithOffset(Offset), 2752 isVolatile, isNonTemporal, 2753 MinAlign(Align, Offset))); 2754 StWidth -= NewVTWidth; 2755 Offset += Increment; 2756 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, 2757 DAG.getIntPtrConstant(Increment)); 2758 } while (StWidth != 0 && StWidth >= NewVTWidth); 2759 // Restore index back to be relative to the original widen element type 2760 Idx = Idx * NewVTWidth / ValEltWidth; 2761 } 2762 } 2763} 2764 2765void 2766DAGTypeLegalizer::GenWidenVectorTruncStores(SmallVector<SDValue, 16>& StChain, 2767 StoreSDNode *ST) { 2768 // For extension loads, it may not be more efficient to truncate the vector 2769 // and then store it. Instead, we extract each element and then store it. 2770 SDValue Chain = ST->getChain(); 2771 SDValue BasePtr = ST->getBasePtr(); 2772 unsigned Align = ST->getAlignment(); 2773 bool isVolatile = ST->isVolatile(); 2774 bool isNonTemporal = ST->isNonTemporal(); 2775 SDValue ValOp = GetWidenedVector(ST->getValue()); 2776 SDLoc dl(ST); 2777 2778 EVT StVT = ST->getMemoryVT(); 2779 EVT ValVT = ValOp.getValueType(); 2780 2781 // It must be true that we the widen vector type is bigger than where 2782 // we need to store. 2783 assert(StVT.isVector() && ValOp.getValueType().isVector()); 2784 assert(StVT.bitsLT(ValOp.getValueType())); 2785 2786 // For truncating stores, we can not play the tricks of chopping legal 2787 // vector types and bit cast it to the right type. Instead, we unroll 2788 // the store. 2789 EVT StEltVT = StVT.getVectorElementType(); 2790 EVT ValEltVT = ValVT.getVectorElementType(); 2791 unsigned Increment = ValEltVT.getSizeInBits() / 8; 2792 unsigned NumElts = StVT.getVectorNumElements(); 2793 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp, 2794 DAG.getIntPtrConstant(0)); 2795 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, BasePtr, 2796 ST->getPointerInfo(), StEltVT, 2797 isVolatile, isNonTemporal, Align)); 2798 unsigned Offset = Increment; 2799 for (unsigned i=1; i < NumElts; ++i, Offset += Increment) { 2800 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), 2801 BasePtr, DAG.getIntPtrConstant(Offset)); 2802 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp, 2803 DAG.getIntPtrConstant(0)); 2804 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, NewBasePtr, 2805 ST->getPointerInfo().getWithOffset(Offset), 2806 StEltVT, isVolatile, isNonTemporal, 2807 MinAlign(Align, Offset))); 2808 } 2809} 2810 2811/// Modifies a vector input (widen or narrows) to a vector of NVT. The 2812/// input vector must have the same element type as NVT. 2813SDValue DAGTypeLegalizer::ModifyToType(SDValue InOp, EVT NVT) { 2814 // Note that InOp might have been widened so it might already have 2815 // the right width or it might need be narrowed. 2816 EVT InVT = InOp.getValueType(); 2817 assert(InVT.getVectorElementType() == NVT.getVectorElementType() && 2818 "input and widen element type must match"); 2819 SDLoc dl(InOp); 2820 2821 // Check if InOp already has the right width. 2822 if (InVT == NVT) 2823 return InOp; 2824 2825 unsigned InNumElts = InVT.getVectorNumElements(); 2826 unsigned WidenNumElts = NVT.getVectorNumElements(); 2827 if (WidenNumElts > InNumElts && WidenNumElts % InNumElts == 0) { 2828 unsigned NumConcat = WidenNumElts / InNumElts; 2829 SmallVector<SDValue, 16> Ops(NumConcat); 2830 SDValue UndefVal = DAG.getUNDEF(InVT); 2831 Ops[0] = InOp; 2832 for (unsigned i = 1; i != NumConcat; ++i) 2833 Ops[i] = UndefVal; 2834 2835 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, &Ops[0], NumConcat); 2836 } 2837 2838 if (WidenNumElts < InNumElts && InNumElts % WidenNumElts) 2839 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT, InOp, 2840 DAG.getIntPtrConstant(0)); 2841 2842 // Fall back to extract and build. 2843 SmallVector<SDValue, 16> Ops(WidenNumElts); 2844 EVT EltVT = NVT.getVectorElementType(); 2845 unsigned MinNumElts = std::min(WidenNumElts, InNumElts); 2846 unsigned Idx; 2847 for (Idx = 0; Idx < MinNumElts; ++Idx) 2848 Ops[Idx] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp, 2849 DAG.getIntPtrConstant(Idx)); 2850 2851 SDValue UndefVal = DAG.getUNDEF(EltVT); 2852 for ( ; Idx < WidenNumElts; ++Idx) 2853 Ops[Idx] = UndefVal; 2854 return DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &Ops[0], WidenNumElts); 2855} 2856