SelectionDAG.cpp revision 03228089d5235f8c90477f88809139464e9c6ea5
1//===-- SelectionDAG.cpp - Implement the SelectionDAG data structures -----===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAG class. 11// 12//===----------------------------------------------------------------------===// 13#include "llvm/CodeGen/SelectionDAG.h" 14#include "llvm/Constants.h" 15#include "llvm/Analysis/ValueTracking.h" 16#include "llvm/GlobalAlias.h" 17#include "llvm/GlobalVariable.h" 18#include "llvm/Intrinsics.h" 19#include "llvm/DerivedTypes.h" 20#include "llvm/Assembly/Writer.h" 21#include "llvm/CallingConv.h" 22#include "llvm/CodeGen/MachineBasicBlock.h" 23#include "llvm/CodeGen/MachineConstantPool.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/MachineModuleInfo.h" 26#include "llvm/CodeGen/PseudoSourceValue.h" 27#include "llvm/Target/TargetRegisterInfo.h" 28#include "llvm/Target/TargetData.h" 29#include "llvm/Target/TargetLowering.h" 30#include "llvm/Target/TargetInstrInfo.h" 31#include "llvm/Target/TargetMachine.h" 32#include "llvm/Support/CommandLine.h" 33#include "llvm/Support/MathExtras.h" 34#include "llvm/Support/raw_ostream.h" 35#include "llvm/ADT/SetVector.h" 36#include "llvm/ADT/SmallPtrSet.h" 37#include "llvm/ADT/SmallSet.h" 38#include "llvm/ADT/SmallVector.h" 39#include "llvm/ADT/StringExtras.h" 40#include <algorithm> 41#include <cmath> 42using namespace llvm; 43 44/// makeVTList - Return an instance of the SDVTList struct initialized with the 45/// specified members. 46static SDVTList makeVTList(const MVT *VTs, unsigned NumVTs) { 47 SDVTList Res = {VTs, NumVTs}; 48 return Res; 49} 50 51static const fltSemantics *MVTToAPFloatSemantics(MVT VT) { 52 switch (VT.getSimpleVT()) { 53 default: assert(0 && "Unknown FP format"); 54 case MVT::f32: return &APFloat::IEEEsingle; 55 case MVT::f64: return &APFloat::IEEEdouble; 56 case MVT::f80: return &APFloat::x87DoubleExtended; 57 case MVT::f128: return &APFloat::IEEEquad; 58 case MVT::ppcf128: return &APFloat::PPCDoubleDouble; 59 } 60} 61 62SelectionDAG::DAGUpdateListener::~DAGUpdateListener() {} 63 64//===----------------------------------------------------------------------===// 65// ConstantFPSDNode Class 66//===----------------------------------------------------------------------===// 67 68/// isExactlyValue - We don't rely on operator== working on double values, as 69/// it returns true for things that are clearly not equal, like -0.0 and 0.0. 70/// As such, this method can be used to do an exact bit-for-bit comparison of 71/// two floating point values. 72bool ConstantFPSDNode::isExactlyValue(const APFloat& V) const { 73 return getValueAPF().bitwiseIsEqual(V); 74} 75 76bool ConstantFPSDNode::isValueValidForType(MVT VT, 77 const APFloat& Val) { 78 assert(VT.isFloatingPoint() && "Can only convert between FP types"); 79 80 // PPC long double cannot be converted to any other type. 81 if (VT == MVT::ppcf128 || 82 &Val.getSemantics() == &APFloat::PPCDoubleDouble) 83 return false; 84 85 // convert modifies in place, so make a copy. 86 APFloat Val2 = APFloat(Val); 87 bool losesInfo; 88 (void) Val2.convert(*MVTToAPFloatSemantics(VT), APFloat::rmNearestTiesToEven, 89 &losesInfo); 90 return !losesInfo; 91} 92 93//===----------------------------------------------------------------------===// 94// ISD Namespace 95//===----------------------------------------------------------------------===// 96 97/// isBuildVectorAllOnes - Return true if the specified node is a 98/// BUILD_VECTOR where all of the elements are ~0 or undef. 99bool ISD::isBuildVectorAllOnes(const SDNode *N) { 100 // Look through a bit convert. 101 if (N->getOpcode() == ISD::BIT_CONVERT) 102 N = N->getOperand(0).getNode(); 103 104 if (N->getOpcode() != ISD::BUILD_VECTOR) return false; 105 106 unsigned i = 0, e = N->getNumOperands(); 107 108 // Skip over all of the undef values. 109 while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF) 110 ++i; 111 112 // Do not accept an all-undef vector. 113 if (i == e) return false; 114 115 // Do not accept build_vectors that aren't all constants or which have non-~0 116 // elements. 117 SDValue NotZero = N->getOperand(i); 118 if (isa<ConstantSDNode>(NotZero)) { 119 if (!cast<ConstantSDNode>(NotZero)->isAllOnesValue()) 120 return false; 121 } else if (isa<ConstantFPSDNode>(NotZero)) { 122 if (!cast<ConstantFPSDNode>(NotZero)->getValueAPF(). 123 bitcastToAPInt().isAllOnesValue()) 124 return false; 125 } else 126 return false; 127 128 // Okay, we have at least one ~0 value, check to see if the rest match or are 129 // undefs. 130 for (++i; i != e; ++i) 131 if (N->getOperand(i) != NotZero && 132 N->getOperand(i).getOpcode() != ISD::UNDEF) 133 return false; 134 return true; 135} 136 137 138/// isBuildVectorAllZeros - Return true if the specified node is a 139/// BUILD_VECTOR where all of the elements are 0 or undef. 140bool ISD::isBuildVectorAllZeros(const SDNode *N) { 141 // Look through a bit convert. 142 if (N->getOpcode() == ISD::BIT_CONVERT) 143 N = N->getOperand(0).getNode(); 144 145 if (N->getOpcode() != ISD::BUILD_VECTOR) return false; 146 147 unsigned i = 0, e = N->getNumOperands(); 148 149 // Skip over all of the undef values. 150 while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF) 151 ++i; 152 153 // Do not accept an all-undef vector. 154 if (i == e) return false; 155 156 // Do not accept build_vectors that aren't all constants or which have non-~0 157 // elements. 158 SDValue Zero = N->getOperand(i); 159 if (isa<ConstantSDNode>(Zero)) { 160 if (!cast<ConstantSDNode>(Zero)->isNullValue()) 161 return false; 162 } else if (isa<ConstantFPSDNode>(Zero)) { 163 if (!cast<ConstantFPSDNode>(Zero)->getValueAPF().isPosZero()) 164 return false; 165 } else 166 return false; 167 168 // Okay, we have at least one ~0 value, check to see if the rest match or are 169 // undefs. 170 for (++i; i != e; ++i) 171 if (N->getOperand(i) != Zero && 172 N->getOperand(i).getOpcode() != ISD::UNDEF) 173 return false; 174 return true; 175} 176 177/// isScalarToVector - Return true if the specified node is a 178/// ISD::SCALAR_TO_VECTOR node or a BUILD_VECTOR node where only the low 179/// element is not an undef. 180bool ISD::isScalarToVector(const SDNode *N) { 181 if (N->getOpcode() == ISD::SCALAR_TO_VECTOR) 182 return true; 183 184 if (N->getOpcode() != ISD::BUILD_VECTOR) 185 return false; 186 if (N->getOperand(0).getOpcode() == ISD::UNDEF) 187 return false; 188 unsigned NumElems = N->getNumOperands(); 189 for (unsigned i = 1; i < NumElems; ++i) { 190 SDValue V = N->getOperand(i); 191 if (V.getOpcode() != ISD::UNDEF) 192 return false; 193 } 194 return true; 195} 196 197 198/// isDebugLabel - Return true if the specified node represents a debug 199/// label (i.e. ISD::DBG_LABEL or TargetInstrInfo::DBG_LABEL node). 200bool ISD::isDebugLabel(const SDNode *N) { 201 SDValue Zero; 202 if (N->getOpcode() == ISD::DBG_LABEL) 203 return true; 204 if (N->isMachineOpcode() && 205 N->getMachineOpcode() == TargetInstrInfo::DBG_LABEL) 206 return true; 207 return false; 208} 209 210/// getSetCCSwappedOperands - Return the operation corresponding to (Y op X) 211/// when given the operation for (X op Y). 212ISD::CondCode ISD::getSetCCSwappedOperands(ISD::CondCode Operation) { 213 // To perform this operation, we just need to swap the L and G bits of the 214 // operation. 215 unsigned OldL = (Operation >> 2) & 1; 216 unsigned OldG = (Operation >> 1) & 1; 217 return ISD::CondCode((Operation & ~6) | // Keep the N, U, E bits 218 (OldL << 1) | // New G bit 219 (OldG << 2)); // New L bit. 220} 221 222/// getSetCCInverse - Return the operation corresponding to !(X op Y), where 223/// 'op' is a valid SetCC operation. 224ISD::CondCode ISD::getSetCCInverse(ISD::CondCode Op, bool isInteger) { 225 unsigned Operation = Op; 226 if (isInteger) 227 Operation ^= 7; // Flip L, G, E bits, but not U. 228 else 229 Operation ^= 15; // Flip all of the condition bits. 230 231 if (Operation > ISD::SETTRUE2) 232 Operation &= ~8; // Don't let N and U bits get set. 233 234 return ISD::CondCode(Operation); 235} 236 237 238/// isSignedOp - For an integer comparison, return 1 if the comparison is a 239/// signed operation and 2 if the result is an unsigned comparison. Return zero 240/// if the operation does not depend on the sign of the input (setne and seteq). 241static int isSignedOp(ISD::CondCode Opcode) { 242 switch (Opcode) { 243 default: assert(0 && "Illegal integer setcc operation!"); 244 case ISD::SETEQ: 245 case ISD::SETNE: return 0; 246 case ISD::SETLT: 247 case ISD::SETLE: 248 case ISD::SETGT: 249 case ISD::SETGE: return 1; 250 case ISD::SETULT: 251 case ISD::SETULE: 252 case ISD::SETUGT: 253 case ISD::SETUGE: return 2; 254 } 255} 256 257/// getSetCCOrOperation - Return the result of a logical OR between different 258/// comparisons of identical values: ((X op1 Y) | (X op2 Y)). This function 259/// returns SETCC_INVALID if it is not possible to represent the resultant 260/// comparison. 261ISD::CondCode ISD::getSetCCOrOperation(ISD::CondCode Op1, ISD::CondCode Op2, 262 bool isInteger) { 263 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 264 // Cannot fold a signed integer setcc with an unsigned integer setcc. 265 return ISD::SETCC_INVALID; 266 267 unsigned Op = Op1 | Op2; // Combine all of the condition bits. 268 269 // If the N and U bits get set then the resultant comparison DOES suddenly 270 // care about orderedness, and is true when ordered. 271 if (Op > ISD::SETTRUE2) 272 Op &= ~16; // Clear the U bit if the N bit is set. 273 274 // Canonicalize illegal integer setcc's. 275 if (isInteger && Op == ISD::SETUNE) // e.g. SETUGT | SETULT 276 Op = ISD::SETNE; 277 278 return ISD::CondCode(Op); 279} 280 281/// getSetCCAndOperation - Return the result of a logical AND between different 282/// comparisons of identical values: ((X op1 Y) & (X op2 Y)). This 283/// function returns zero if it is not possible to represent the resultant 284/// comparison. 285ISD::CondCode ISD::getSetCCAndOperation(ISD::CondCode Op1, ISD::CondCode Op2, 286 bool isInteger) { 287 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 288 // Cannot fold a signed setcc with an unsigned setcc. 289 return ISD::SETCC_INVALID; 290 291 // Combine all of the condition bits. 292 ISD::CondCode Result = ISD::CondCode(Op1 & Op2); 293 294 // Canonicalize illegal integer setcc's. 295 if (isInteger) { 296 switch (Result) { 297 default: break; 298 case ISD::SETUO : Result = ISD::SETFALSE; break; // SETUGT & SETULT 299 case ISD::SETOEQ: // SETEQ & SETU[LG]E 300 case ISD::SETUEQ: Result = ISD::SETEQ ; break; // SETUGE & SETULE 301 case ISD::SETOLT: Result = ISD::SETULT ; break; // SETULT & SETNE 302 case ISD::SETOGT: Result = ISD::SETUGT ; break; // SETUGT & SETNE 303 } 304 } 305 306 return Result; 307} 308 309const TargetMachine &SelectionDAG::getTarget() const { 310 return MF->getTarget(); 311} 312 313//===----------------------------------------------------------------------===// 314// SDNode Profile Support 315//===----------------------------------------------------------------------===// 316 317/// AddNodeIDOpcode - Add the node opcode to the NodeID data. 318/// 319static void AddNodeIDOpcode(FoldingSetNodeID &ID, unsigned OpC) { 320 ID.AddInteger(OpC); 321} 322 323/// AddNodeIDValueTypes - Value type lists are intern'd so we can represent them 324/// solely with their pointer. 325static void AddNodeIDValueTypes(FoldingSetNodeID &ID, SDVTList VTList) { 326 ID.AddPointer(VTList.VTs); 327} 328 329/// AddNodeIDOperands - Various routines for adding operands to the NodeID data. 330/// 331static void AddNodeIDOperands(FoldingSetNodeID &ID, 332 const SDValue *Ops, unsigned NumOps) { 333 for (; NumOps; --NumOps, ++Ops) { 334 ID.AddPointer(Ops->getNode()); 335 ID.AddInteger(Ops->getResNo()); 336 } 337} 338 339/// AddNodeIDOperands - Various routines for adding operands to the NodeID data. 340/// 341static void AddNodeIDOperands(FoldingSetNodeID &ID, 342 const SDUse *Ops, unsigned NumOps) { 343 for (; NumOps; --NumOps, ++Ops) { 344 ID.AddPointer(Ops->getVal()); 345 ID.AddInteger(Ops->getSDValue().getResNo()); 346 } 347} 348 349static void AddNodeIDNode(FoldingSetNodeID &ID, 350 unsigned short OpC, SDVTList VTList, 351 const SDValue *OpList, unsigned N) { 352 AddNodeIDOpcode(ID, OpC); 353 AddNodeIDValueTypes(ID, VTList); 354 AddNodeIDOperands(ID, OpList, N); 355} 356 357/// AddNodeIDCustom - If this is an SDNode with special info, add this info to 358/// the NodeID data. 359static void AddNodeIDCustom(FoldingSetNodeID &ID, const SDNode *N) { 360 switch (N->getOpcode()) { 361 default: break; // Normal nodes don't need extra info. 362 case ISD::ARG_FLAGS: 363 ID.AddInteger(cast<ARG_FLAGSSDNode>(N)->getArgFlags().getRawBits()); 364 break; 365 case ISD::TargetConstant: 366 case ISD::Constant: 367 ID.AddPointer(cast<ConstantSDNode>(N)->getConstantIntValue()); 368 break; 369 case ISD::TargetConstantFP: 370 case ISD::ConstantFP: { 371 ID.AddPointer(cast<ConstantFPSDNode>(N)->getConstantFPValue()); 372 break; 373 } 374 case ISD::TargetGlobalAddress: 375 case ISD::GlobalAddress: 376 case ISD::TargetGlobalTLSAddress: 377 case ISD::GlobalTLSAddress: { 378 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(N); 379 ID.AddPointer(GA->getGlobal()); 380 ID.AddInteger(GA->getOffset()); 381 break; 382 } 383 case ISD::BasicBlock: 384 ID.AddPointer(cast<BasicBlockSDNode>(N)->getBasicBlock()); 385 break; 386 case ISD::Register: 387 ID.AddInteger(cast<RegisterSDNode>(N)->getReg()); 388 break; 389 case ISD::DBG_STOPPOINT: { 390 const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(N); 391 ID.AddInteger(DSP->getLine()); 392 ID.AddInteger(DSP->getColumn()); 393 ID.AddPointer(DSP->getCompileUnit()); 394 break; 395 } 396 case ISD::SRCVALUE: 397 ID.AddPointer(cast<SrcValueSDNode>(N)->getValue()); 398 break; 399 case ISD::MEMOPERAND: { 400 const MachineMemOperand &MO = cast<MemOperandSDNode>(N)->MO; 401 MO.Profile(ID); 402 break; 403 } 404 case ISD::FrameIndex: 405 case ISD::TargetFrameIndex: 406 ID.AddInteger(cast<FrameIndexSDNode>(N)->getIndex()); 407 break; 408 case ISD::JumpTable: 409 case ISD::TargetJumpTable: 410 ID.AddInteger(cast<JumpTableSDNode>(N)->getIndex()); 411 break; 412 case ISD::ConstantPool: 413 case ISD::TargetConstantPool: { 414 const ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(N); 415 ID.AddInteger(CP->getAlignment()); 416 ID.AddInteger(CP->getOffset()); 417 if (CP->isMachineConstantPoolEntry()) 418 CP->getMachineCPVal()->AddSelectionDAGCSEId(ID); 419 else 420 ID.AddPointer(CP->getConstVal()); 421 break; 422 } 423 case ISD::CALL: { 424 const CallSDNode *Call = cast<CallSDNode>(N); 425 ID.AddInteger(Call->getCallingConv()); 426 ID.AddInteger(Call->isVarArg()); 427 break; 428 } 429 case ISD::LOAD: { 430 const LoadSDNode *LD = cast<LoadSDNode>(N); 431 ID.AddInteger(LD->getAddressingMode()); 432 ID.AddInteger(LD->getExtensionType()); 433 ID.AddInteger(LD->getMemoryVT().getRawBits()); 434 ID.AddInteger(LD->getRawFlags()); 435 break; 436 } 437 case ISD::STORE: { 438 const StoreSDNode *ST = cast<StoreSDNode>(N); 439 ID.AddInteger(ST->getAddressingMode()); 440 ID.AddInteger(ST->isTruncatingStore()); 441 ID.AddInteger(ST->getMemoryVT().getRawBits()); 442 ID.AddInteger(ST->getRawFlags()); 443 break; 444 } 445 case ISD::ATOMIC_CMP_SWAP_8: 446 case ISD::ATOMIC_SWAP_8: 447 case ISD::ATOMIC_LOAD_ADD_8: 448 case ISD::ATOMIC_LOAD_SUB_8: 449 case ISD::ATOMIC_LOAD_AND_8: 450 case ISD::ATOMIC_LOAD_OR_8: 451 case ISD::ATOMIC_LOAD_XOR_8: 452 case ISD::ATOMIC_LOAD_NAND_8: 453 case ISD::ATOMIC_LOAD_MIN_8: 454 case ISD::ATOMIC_LOAD_MAX_8: 455 case ISD::ATOMIC_LOAD_UMIN_8: 456 case ISD::ATOMIC_LOAD_UMAX_8: 457 case ISD::ATOMIC_CMP_SWAP_16: 458 case ISD::ATOMIC_SWAP_16: 459 case ISD::ATOMIC_LOAD_ADD_16: 460 case ISD::ATOMIC_LOAD_SUB_16: 461 case ISD::ATOMIC_LOAD_AND_16: 462 case ISD::ATOMIC_LOAD_OR_16: 463 case ISD::ATOMIC_LOAD_XOR_16: 464 case ISD::ATOMIC_LOAD_NAND_16: 465 case ISD::ATOMIC_LOAD_MIN_16: 466 case ISD::ATOMIC_LOAD_MAX_16: 467 case ISD::ATOMIC_LOAD_UMIN_16: 468 case ISD::ATOMIC_LOAD_UMAX_16: 469 case ISD::ATOMIC_CMP_SWAP_32: 470 case ISD::ATOMIC_SWAP_32: 471 case ISD::ATOMIC_LOAD_ADD_32: 472 case ISD::ATOMIC_LOAD_SUB_32: 473 case ISD::ATOMIC_LOAD_AND_32: 474 case ISD::ATOMIC_LOAD_OR_32: 475 case ISD::ATOMIC_LOAD_XOR_32: 476 case ISD::ATOMIC_LOAD_NAND_32: 477 case ISD::ATOMIC_LOAD_MIN_32: 478 case ISD::ATOMIC_LOAD_MAX_32: 479 case ISD::ATOMIC_LOAD_UMIN_32: 480 case ISD::ATOMIC_LOAD_UMAX_32: 481 case ISD::ATOMIC_CMP_SWAP_64: 482 case ISD::ATOMIC_SWAP_64: 483 case ISD::ATOMIC_LOAD_ADD_64: 484 case ISD::ATOMIC_LOAD_SUB_64: 485 case ISD::ATOMIC_LOAD_AND_64: 486 case ISD::ATOMIC_LOAD_OR_64: 487 case ISD::ATOMIC_LOAD_XOR_64: 488 case ISD::ATOMIC_LOAD_NAND_64: 489 case ISD::ATOMIC_LOAD_MIN_64: 490 case ISD::ATOMIC_LOAD_MAX_64: 491 case ISD::ATOMIC_LOAD_UMIN_64: 492 case ISD::ATOMIC_LOAD_UMAX_64: { 493 const AtomicSDNode *AT = cast<AtomicSDNode>(N); 494 ID.AddInteger(AT->getRawFlags()); 495 break; 496 } 497 } // end switch (N->getOpcode()) 498} 499 500/// AddNodeIDNode - Generic routine for adding a nodes info to the NodeID 501/// data. 502static void AddNodeIDNode(FoldingSetNodeID &ID, const SDNode *N) { 503 AddNodeIDOpcode(ID, N->getOpcode()); 504 // Add the return value info. 505 AddNodeIDValueTypes(ID, N->getVTList()); 506 // Add the operand info. 507 AddNodeIDOperands(ID, N->op_begin(), N->getNumOperands()); 508 509 // Handle SDNode leafs with special info. 510 AddNodeIDCustom(ID, N); 511} 512 513/// encodeMemSDNodeFlags - Generic routine for computing a value for use in 514/// the CSE map that carries both alignment and volatility information. 515/// 516static inline unsigned 517encodeMemSDNodeFlags(bool isVolatile, unsigned Alignment) { 518 return isVolatile | ((Log2_32(Alignment) + 1) << 1); 519} 520 521//===----------------------------------------------------------------------===// 522// SelectionDAG Class 523//===----------------------------------------------------------------------===// 524 525/// doNotCSE - Return true if CSE should not be performed for this node. 526static bool doNotCSE(SDNode *N) { 527 if (N->getValueType(0) == MVT::Flag) 528 return true; // Never CSE anything that produces a flag. 529 530 switch (N->getOpcode()) { 531 default: break; 532 case ISD::HANDLENODE: 533 case ISD::DBG_LABEL: 534 case ISD::DBG_STOPPOINT: 535 case ISD::EH_LABEL: 536 case ISD::DECLARE: 537 return true; // Never CSE these nodes. 538 } 539 540 // Check that remaining values produced are not flags. 541 for (unsigned i = 1, e = N->getNumValues(); i != e; ++i) 542 if (N->getValueType(i) == MVT::Flag) 543 return true; // Never CSE anything that produces a flag. 544 545 return false; 546} 547 548/// RemoveDeadNodes - This method deletes all unreachable nodes in the 549/// SelectionDAG. 550void SelectionDAG::RemoveDeadNodes() { 551 // Create a dummy node (which is not added to allnodes), that adds a reference 552 // to the root node, preventing it from being deleted. 553 HandleSDNode Dummy(getRoot()); 554 555 SmallVector<SDNode*, 128> DeadNodes; 556 557 // Add all obviously-dead nodes to the DeadNodes worklist. 558 for (allnodes_iterator I = allnodes_begin(), E = allnodes_end(); I != E; ++I) 559 if (I->use_empty()) 560 DeadNodes.push_back(I); 561 562 RemoveDeadNodes(DeadNodes); 563 564 // If the root changed (e.g. it was a dead load, update the root). 565 setRoot(Dummy.getValue()); 566} 567 568/// RemoveDeadNodes - This method deletes the unreachable nodes in the 569/// given list, and any nodes that become unreachable as a result. 570void SelectionDAG::RemoveDeadNodes(SmallVectorImpl<SDNode *> &DeadNodes, 571 DAGUpdateListener *UpdateListener) { 572 573 // Process the worklist, deleting the nodes and adding their uses to the 574 // worklist. 575 while (!DeadNodes.empty()) { 576 SDNode *N = DeadNodes.back(); 577 DeadNodes.pop_back(); 578 579 if (UpdateListener) 580 UpdateListener->NodeDeleted(N, 0); 581 582 // Take the node out of the appropriate CSE map. 583 RemoveNodeFromCSEMaps(N); 584 585 // Next, brutally remove the operand list. This is safe to do, as there are 586 // no cycles in the graph. 587 for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ++I) { 588 SDNode *Operand = I->getVal(); 589 Operand->removeUser(std::distance(N->op_begin(), I), N); 590 591 // Now that we removed this operand, see if there are no uses of it left. 592 if (Operand->use_empty()) 593 DeadNodes.push_back(Operand); 594 } 595 596 if (N->OperandsNeedDelete) 597 delete[] N->OperandList; 598 599 N->OperandList = 0; 600 N->NumOperands = 0; 601 602 // Finally, remove N itself. 603 NodeAllocator.Deallocate(AllNodes.remove(N)); 604 } 605} 606 607void SelectionDAG::RemoveDeadNode(SDNode *N, DAGUpdateListener *UpdateListener){ 608 SmallVector<SDNode*, 16> DeadNodes(1, N); 609 RemoveDeadNodes(DeadNodes, UpdateListener); 610} 611 612void SelectionDAG::DeleteNode(SDNode *N) { 613 assert(N->use_empty() && "Cannot delete a node that is not dead!"); 614 615 // First take this out of the appropriate CSE map. 616 RemoveNodeFromCSEMaps(N); 617 618 // Finally, remove uses due to operands of this node, remove from the 619 // AllNodes list, and delete the node. 620 DeleteNodeNotInCSEMaps(N); 621} 622 623void SelectionDAG::DeleteNodeNotInCSEMaps(SDNode *N) { 624 // Drop all of the operands and decrement used node's use counts. 625 for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ++I) 626 I->getVal()->removeUser(std::distance(N->op_begin(), I), N); 627 628 if (N->OperandsNeedDelete) { 629 delete[] N->OperandList; 630 N->OperandList = 0; 631 } 632 633 assert(N != AllNodes.begin()); 634 NodeAllocator.Deallocate(AllNodes.remove(N)); 635} 636 637/// RemoveNodeFromCSEMaps - Take the specified node out of the CSE map that 638/// correspond to it. This is useful when we're about to delete or repurpose 639/// the node. We don't want future request for structurally identical nodes 640/// to return N anymore. 641bool SelectionDAG::RemoveNodeFromCSEMaps(SDNode *N) { 642 bool Erased = false; 643 switch (N->getOpcode()) { 644 case ISD::EntryToken: 645 assert(0 && "EntryToken should not be in CSEMaps!"); 646 return false; 647 case ISD::HANDLENODE: return false; // noop. 648 case ISD::CONDCODE: 649 assert(CondCodeNodes[cast<CondCodeSDNode>(N)->get()] && 650 "Cond code doesn't exist!"); 651 Erased = CondCodeNodes[cast<CondCodeSDNode>(N)->get()] != 0; 652 CondCodeNodes[cast<CondCodeSDNode>(N)->get()] = 0; 653 break; 654 case ISD::ExternalSymbol: 655 Erased = ExternalSymbols.erase(cast<ExternalSymbolSDNode>(N)->getSymbol()); 656 break; 657 case ISD::TargetExternalSymbol: 658 Erased = 659 TargetExternalSymbols.erase(cast<ExternalSymbolSDNode>(N)->getSymbol()); 660 break; 661 case ISD::VALUETYPE: { 662 MVT VT = cast<VTSDNode>(N)->getVT(); 663 if (VT.isExtended()) { 664 Erased = ExtendedValueTypeNodes.erase(VT); 665 } else { 666 Erased = ValueTypeNodes[VT.getSimpleVT()] != 0; 667 ValueTypeNodes[VT.getSimpleVT()] = 0; 668 } 669 break; 670 } 671 default: 672 // Remove it from the CSE Map. 673 Erased = CSEMap.RemoveNode(N); 674 break; 675 } 676#ifndef NDEBUG 677 // Verify that the node was actually in one of the CSE maps, unless it has a 678 // flag result (which cannot be CSE'd) or is one of the special cases that are 679 // not subject to CSE. 680 if (!Erased && N->getValueType(N->getNumValues()-1) != MVT::Flag && 681 !N->isMachineOpcode() && !doNotCSE(N)) { 682 N->dump(this); 683 cerr << "\n"; 684 assert(0 && "Node is not in map!"); 685 } 686#endif 687 return Erased; 688} 689 690/// AddNonLeafNodeToCSEMaps - Add the specified node back to the CSE maps. It 691/// has been taken out and modified in some way. If the specified node already 692/// exists in the CSE maps, do not modify the maps, but return the existing node 693/// instead. If it doesn't exist, add it and return null. 694/// 695SDNode *SelectionDAG::AddNonLeafNodeToCSEMaps(SDNode *N) { 696 assert(N->getNumOperands() && "This is a leaf node!"); 697 698 if (doNotCSE(N)) 699 return 0; 700 701 SDNode *New = CSEMap.GetOrInsertNode(N); 702 if (New != N) return New; // Node already existed. 703 return 0; 704} 705 706/// FindModifiedNodeSlot - Find a slot for the specified node if its operands 707/// were replaced with those specified. If this node is never memoized, 708/// return null, otherwise return a pointer to the slot it would take. If a 709/// node already exists with these operands, the slot will be non-null. 710SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, SDValue Op, 711 void *&InsertPos) { 712 if (doNotCSE(N)) 713 return 0; 714 715 SDValue Ops[] = { Op }; 716 FoldingSetNodeID ID; 717 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, 1); 718 AddNodeIDCustom(ID, N); 719 return CSEMap.FindNodeOrInsertPos(ID, InsertPos); 720} 721 722/// FindModifiedNodeSlot - Find a slot for the specified node if its operands 723/// were replaced with those specified. If this node is never memoized, 724/// return null, otherwise return a pointer to the slot it would take. If a 725/// node already exists with these operands, the slot will be non-null. 726SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, 727 SDValue Op1, SDValue Op2, 728 void *&InsertPos) { 729 if (doNotCSE(N)) 730 return 0; 731 732 SDValue Ops[] = { Op1, Op2 }; 733 FoldingSetNodeID ID; 734 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, 2); 735 AddNodeIDCustom(ID, N); 736 return CSEMap.FindNodeOrInsertPos(ID, InsertPos); 737} 738 739 740/// FindModifiedNodeSlot - Find a slot for the specified node if its operands 741/// were replaced with those specified. If this node is never memoized, 742/// return null, otherwise return a pointer to the slot it would take. If a 743/// node already exists with these operands, the slot will be non-null. 744SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, 745 const SDValue *Ops,unsigned NumOps, 746 void *&InsertPos) { 747 if (doNotCSE(N)) 748 return 0; 749 750 FoldingSetNodeID ID; 751 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, NumOps); 752 AddNodeIDCustom(ID, N); 753 return CSEMap.FindNodeOrInsertPos(ID, InsertPos); 754} 755 756/// VerifyNode - Sanity check the given node. Aborts if it is invalid. 757void SelectionDAG::VerifyNode(SDNode *N) { 758 switch (N->getOpcode()) { 759 default: 760 break; 761 case ISD::BUILD_PAIR: { 762 MVT VT = N->getValueType(0); 763 assert(N->getNumValues() == 1 && "Too many results!"); 764 assert(!VT.isVector() && (VT.isInteger() || VT.isFloatingPoint()) && 765 "Wrong return type!"); 766 assert(N->getNumOperands() == 2 && "Wrong number of operands!"); 767 assert(N->getOperand(0).getValueType() == N->getOperand(1).getValueType() && 768 "Mismatched operand types!"); 769 assert(N->getOperand(0).getValueType().isInteger() == VT.isInteger() && 770 "Wrong operand type!"); 771 assert(VT.getSizeInBits() == 2 * N->getOperand(0).getValueSizeInBits() && 772 "Wrong return type size"); 773 break; 774 } 775 case ISD::BUILD_VECTOR: { 776 assert(N->getNumValues() == 1 && "Too many results!"); 777 assert(N->getValueType(0).isVector() && "Wrong return type!"); 778 assert(N->getNumOperands() == N->getValueType(0).getVectorNumElements() && 779 "Wrong number of operands!"); 780 // FIXME: Change vector_shuffle to a variadic node with mask elements being 781 // operands of the node. Currently the mask is a BUILD_VECTOR passed as an 782 // operand, and it is not always possible to legalize it. Turning off the 783 // following checks at least makes it possible to legalize most of the time. 784// MVT EltVT = N->getValueType(0).getVectorElementType(); 785// for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ++I) 786// assert(I->getSDValue().getValueType() == EltVT && 787// "Wrong operand type!"); 788 break; 789 } 790 } 791} 792 793/// getMVTAlignment - Compute the default alignment value for the 794/// given type. 795/// 796unsigned SelectionDAG::getMVTAlignment(MVT VT) const { 797 const Type *Ty = VT == MVT::iPTR ? 798 PointerType::get(Type::Int8Ty, 0) : 799 VT.getTypeForMVT(); 800 801 return TLI.getTargetData()->getABITypeAlignment(Ty); 802} 803 804SelectionDAG::SelectionDAG(TargetLowering &tli, FunctionLoweringInfo &fli) 805 : TLI(tli), FLI(fli), 806 EntryNode(ISD::EntryToken, getVTList(MVT::Other)), 807 Root(getEntryNode()) { 808 AllNodes.push_back(&EntryNode); 809} 810 811void SelectionDAG::init(MachineFunction &mf, MachineModuleInfo *mmi) { 812 MF = &mf; 813 MMI = mmi; 814} 815 816SelectionDAG::~SelectionDAG() { 817 allnodes_clear(); 818} 819 820void SelectionDAG::allnodes_clear() { 821 assert(&*AllNodes.begin() == &EntryNode); 822 AllNodes.remove(AllNodes.begin()); 823 while (!AllNodes.empty()) { 824 SDNode *N = AllNodes.remove(AllNodes.begin()); 825 N->SetNextInBucket(0); 826 827 if (N->OperandsNeedDelete) { 828 delete [] N->OperandList; 829 N->OperandList = 0; 830 } 831 832 NodeAllocator.Deallocate(N); 833 } 834} 835 836void SelectionDAG::clear() { 837 allnodes_clear(); 838 OperandAllocator.Reset(); 839 CSEMap.clear(); 840 841 ExtendedValueTypeNodes.clear(); 842 ExternalSymbols.clear(); 843 TargetExternalSymbols.clear(); 844 std::fill(CondCodeNodes.begin(), CondCodeNodes.end(), 845 static_cast<CondCodeSDNode*>(0)); 846 std::fill(ValueTypeNodes.begin(), ValueTypeNodes.end(), 847 static_cast<SDNode*>(0)); 848 849 EntryNode.Uses = 0; 850 AllNodes.push_back(&EntryNode); 851 Root = getEntryNode(); 852} 853 854SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, MVT VT) { 855 if (Op.getValueType() == VT) return Op; 856 APInt Imm = APInt::getLowBitsSet(Op.getValueSizeInBits(), 857 VT.getSizeInBits()); 858 return getNode(ISD::AND, Op.getValueType(), Op, 859 getConstant(Imm, Op.getValueType())); 860} 861 862SDValue SelectionDAG::getConstant(uint64_t Val, MVT VT, bool isT) { 863 MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 864 return getConstant(APInt(EltVT.getSizeInBits(), Val), VT, isT); 865} 866 867SDValue SelectionDAG::getConstant(const APInt &Val, MVT VT, bool isT) { 868 return getConstant(*ConstantInt::get(Val), VT, isT); 869} 870 871SDValue SelectionDAG::getConstant(const ConstantInt &Val, MVT VT, bool isT) { 872 assert(VT.isInteger() && "Cannot create FP integer constant!"); 873 874 MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 875 assert(Val.getBitWidth() == EltVT.getSizeInBits() && 876 "APInt size does not match type size!"); 877 878 unsigned Opc = isT ? ISD::TargetConstant : ISD::Constant; 879 FoldingSetNodeID ID; 880 AddNodeIDNode(ID, Opc, getVTList(EltVT), 0, 0); 881 ID.AddPointer(&Val); 882 void *IP = 0; 883 SDNode *N = NULL; 884 if ((N = CSEMap.FindNodeOrInsertPos(ID, IP))) 885 if (!VT.isVector()) 886 return SDValue(N, 0); 887 if (!N) { 888 N = NodeAllocator.Allocate<ConstantSDNode>(); 889 new (N) ConstantSDNode(isT, &Val, EltVT); 890 CSEMap.InsertNode(N, IP); 891 AllNodes.push_back(N); 892 } 893 894 SDValue Result(N, 0); 895 if (VT.isVector()) { 896 SmallVector<SDValue, 8> Ops; 897 Ops.assign(VT.getVectorNumElements(), Result); 898 Result = getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 899 } 900 return Result; 901} 902 903SDValue SelectionDAG::getIntPtrConstant(uint64_t Val, bool isTarget) { 904 return getConstant(Val, TLI.getPointerTy(), isTarget); 905} 906 907 908SDValue SelectionDAG::getConstantFP(const APFloat& V, MVT VT, bool isTarget) { 909 return getConstantFP(*ConstantFP::get(V), VT, isTarget); 910} 911 912SDValue SelectionDAG::getConstantFP(const ConstantFP& V, MVT VT, bool isTarget){ 913 assert(VT.isFloatingPoint() && "Cannot create integer FP constant!"); 914 915 MVT EltVT = 916 VT.isVector() ? VT.getVectorElementType() : VT; 917 918 // Do the map lookup using the actual bit pattern for the floating point 919 // value, so that we don't have problems with 0.0 comparing equal to -0.0, and 920 // we don't have issues with SNANs. 921 unsigned Opc = isTarget ? ISD::TargetConstantFP : ISD::ConstantFP; 922 FoldingSetNodeID ID; 923 AddNodeIDNode(ID, Opc, getVTList(EltVT), 0, 0); 924 ID.AddPointer(&V); 925 void *IP = 0; 926 SDNode *N = NULL; 927 if ((N = CSEMap.FindNodeOrInsertPos(ID, IP))) 928 if (!VT.isVector()) 929 return SDValue(N, 0); 930 if (!N) { 931 N = NodeAllocator.Allocate<ConstantFPSDNode>(); 932 new (N) ConstantFPSDNode(isTarget, &V, EltVT); 933 CSEMap.InsertNode(N, IP); 934 AllNodes.push_back(N); 935 } 936 937 SDValue Result(N, 0); 938 if (VT.isVector()) { 939 SmallVector<SDValue, 8> Ops; 940 Ops.assign(VT.getVectorNumElements(), Result); 941 Result = getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 942 } 943 return Result; 944} 945 946SDValue SelectionDAG::getConstantFP(double Val, MVT VT, bool isTarget) { 947 MVT EltVT = 948 VT.isVector() ? VT.getVectorElementType() : VT; 949 if (EltVT==MVT::f32) 950 return getConstantFP(APFloat((float)Val), VT, isTarget); 951 else 952 return getConstantFP(APFloat(Val), VT, isTarget); 953} 954 955SDValue SelectionDAG::getGlobalAddress(const GlobalValue *GV, 956 MVT VT, int64_t Offset, 957 bool isTargetGA) { 958 unsigned Opc; 959 960 // Truncate (with sign-extension) the offset value to the pointer size. 961 unsigned BitWidth = TLI.getPointerTy().getSizeInBits(); 962 if (BitWidth < 64) 963 Offset = (Offset << (64 - BitWidth) >> (64 - BitWidth)); 964 965 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV); 966 if (!GVar) { 967 // If GV is an alias then use the aliasee for determining thread-localness. 968 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) 969 GVar = dyn_cast_or_null<GlobalVariable>(GA->resolveAliasedGlobal(false)); 970 } 971 972 if (GVar && GVar->isThreadLocal()) 973 Opc = isTargetGA ? ISD::TargetGlobalTLSAddress : ISD::GlobalTLSAddress; 974 else 975 Opc = isTargetGA ? ISD::TargetGlobalAddress : ISD::GlobalAddress; 976 977 FoldingSetNodeID ID; 978 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 979 ID.AddPointer(GV); 980 ID.AddInteger(Offset); 981 void *IP = 0; 982 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 983 return SDValue(E, 0); 984 SDNode *N = NodeAllocator.Allocate<GlobalAddressSDNode>(); 985 new (N) GlobalAddressSDNode(isTargetGA, GV, VT, Offset); 986 CSEMap.InsertNode(N, IP); 987 AllNodes.push_back(N); 988 return SDValue(N, 0); 989} 990 991SDValue SelectionDAG::getFrameIndex(int FI, MVT VT, bool isTarget) { 992 unsigned Opc = isTarget ? ISD::TargetFrameIndex : ISD::FrameIndex; 993 FoldingSetNodeID ID; 994 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 995 ID.AddInteger(FI); 996 void *IP = 0; 997 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 998 return SDValue(E, 0); 999 SDNode *N = NodeAllocator.Allocate<FrameIndexSDNode>(); 1000 new (N) FrameIndexSDNode(FI, VT, isTarget); 1001 CSEMap.InsertNode(N, IP); 1002 AllNodes.push_back(N); 1003 return SDValue(N, 0); 1004} 1005 1006SDValue SelectionDAG::getJumpTable(int JTI, MVT VT, bool isTarget){ 1007 unsigned Opc = isTarget ? ISD::TargetJumpTable : ISD::JumpTable; 1008 FoldingSetNodeID ID; 1009 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 1010 ID.AddInteger(JTI); 1011 void *IP = 0; 1012 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1013 return SDValue(E, 0); 1014 SDNode *N = NodeAllocator.Allocate<JumpTableSDNode>(); 1015 new (N) JumpTableSDNode(JTI, VT, isTarget); 1016 CSEMap.InsertNode(N, IP); 1017 AllNodes.push_back(N); 1018 return SDValue(N, 0); 1019} 1020 1021SDValue SelectionDAG::getConstantPool(Constant *C, MVT VT, 1022 unsigned Alignment, int Offset, 1023 bool isTarget) { 1024 if (Alignment == 0) 1025 Alignment = 1026 TLI.getTargetData()->getPreferredTypeAlignmentShift(C->getType()); 1027 unsigned Opc = isTarget ? ISD::TargetConstantPool : ISD::ConstantPool; 1028 FoldingSetNodeID ID; 1029 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 1030 ID.AddInteger(Alignment); 1031 ID.AddInteger(Offset); 1032 ID.AddPointer(C); 1033 void *IP = 0; 1034 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1035 return SDValue(E, 0); 1036 SDNode *N = NodeAllocator.Allocate<ConstantPoolSDNode>(); 1037 new (N) ConstantPoolSDNode(isTarget, C, VT, Offset, Alignment); 1038 CSEMap.InsertNode(N, IP); 1039 AllNodes.push_back(N); 1040 return SDValue(N, 0); 1041} 1042 1043 1044SDValue SelectionDAG::getConstantPool(MachineConstantPoolValue *C, MVT VT, 1045 unsigned Alignment, int Offset, 1046 bool isTarget) { 1047 if (Alignment == 0) 1048 Alignment = 1049 TLI.getTargetData()->getPreferredTypeAlignmentShift(C->getType()); 1050 unsigned Opc = isTarget ? ISD::TargetConstantPool : ISD::ConstantPool; 1051 FoldingSetNodeID ID; 1052 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 1053 ID.AddInteger(Alignment); 1054 ID.AddInteger(Offset); 1055 C->AddSelectionDAGCSEId(ID); 1056 void *IP = 0; 1057 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1058 return SDValue(E, 0); 1059 SDNode *N = NodeAllocator.Allocate<ConstantPoolSDNode>(); 1060 new (N) ConstantPoolSDNode(isTarget, C, VT, Offset, Alignment); 1061 CSEMap.InsertNode(N, IP); 1062 AllNodes.push_back(N); 1063 return SDValue(N, 0); 1064} 1065 1066 1067SDValue SelectionDAG::getBasicBlock(MachineBasicBlock *MBB) { 1068 FoldingSetNodeID ID; 1069 AddNodeIDNode(ID, ISD::BasicBlock, getVTList(MVT::Other), 0, 0); 1070 ID.AddPointer(MBB); 1071 void *IP = 0; 1072 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1073 return SDValue(E, 0); 1074 SDNode *N = NodeAllocator.Allocate<BasicBlockSDNode>(); 1075 new (N) BasicBlockSDNode(MBB); 1076 CSEMap.InsertNode(N, IP); 1077 AllNodes.push_back(N); 1078 return SDValue(N, 0); 1079} 1080 1081SDValue SelectionDAG::getArgFlags(ISD::ArgFlagsTy Flags) { 1082 FoldingSetNodeID ID; 1083 AddNodeIDNode(ID, ISD::ARG_FLAGS, getVTList(MVT::Other), 0, 0); 1084 ID.AddInteger(Flags.getRawBits()); 1085 void *IP = 0; 1086 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1087 return SDValue(E, 0); 1088 SDNode *N = NodeAllocator.Allocate<ARG_FLAGSSDNode>(); 1089 new (N) ARG_FLAGSSDNode(Flags); 1090 CSEMap.InsertNode(N, IP); 1091 AllNodes.push_back(N); 1092 return SDValue(N, 0); 1093} 1094 1095SDValue SelectionDAG::getValueType(MVT VT) { 1096 if (VT.isSimple() && (unsigned)VT.getSimpleVT() >= ValueTypeNodes.size()) 1097 ValueTypeNodes.resize(VT.getSimpleVT()+1); 1098 1099 SDNode *&N = VT.isExtended() ? 1100 ExtendedValueTypeNodes[VT] : ValueTypeNodes[VT.getSimpleVT()]; 1101 1102 if (N) return SDValue(N, 0); 1103 N = NodeAllocator.Allocate<VTSDNode>(); 1104 new (N) VTSDNode(VT); 1105 AllNodes.push_back(N); 1106 return SDValue(N, 0); 1107} 1108 1109SDValue SelectionDAG::getExternalSymbol(const char *Sym, MVT VT) { 1110 SDNode *&N = ExternalSymbols[Sym]; 1111 if (N) return SDValue(N, 0); 1112 N = NodeAllocator.Allocate<ExternalSymbolSDNode>(); 1113 new (N) ExternalSymbolSDNode(false, Sym, VT); 1114 AllNodes.push_back(N); 1115 return SDValue(N, 0); 1116} 1117 1118SDValue SelectionDAG::getTargetExternalSymbol(const char *Sym, MVT VT) { 1119 SDNode *&N = TargetExternalSymbols[Sym]; 1120 if (N) return SDValue(N, 0); 1121 N = NodeAllocator.Allocate<ExternalSymbolSDNode>(); 1122 new (N) ExternalSymbolSDNode(true, Sym, VT); 1123 AllNodes.push_back(N); 1124 return SDValue(N, 0); 1125} 1126 1127SDValue SelectionDAG::getCondCode(ISD::CondCode Cond) { 1128 if ((unsigned)Cond >= CondCodeNodes.size()) 1129 CondCodeNodes.resize(Cond+1); 1130 1131 if (CondCodeNodes[Cond] == 0) { 1132 CondCodeSDNode *N = NodeAllocator.Allocate<CondCodeSDNode>(); 1133 new (N) CondCodeSDNode(Cond); 1134 CondCodeNodes[Cond] = N; 1135 AllNodes.push_back(N); 1136 } 1137 return SDValue(CondCodeNodes[Cond], 0); 1138} 1139 1140SDValue SelectionDAG::getConvertRndSat(MVT VT, SDValue Val, SDValue DTy, 1141 SDValue STy, SDValue Rnd, SDValue Sat, 1142 ISD::CvtCode Code) { 1143 FoldingSetNodeID ID; 1144 void* IP = 0; 1145 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1146 return SDValue(E, 0); 1147 CvtRndSatSDNode *N = NodeAllocator.Allocate<CvtRndSatSDNode>(); 1148 SDValue Ops[] = { Val, DTy, STy, Rnd, Sat }; 1149 new (N) CvtRndSatSDNode(VT, Ops, 5, Code); 1150 CSEMap.InsertNode(N, IP); 1151 AllNodes.push_back(N); 1152 return SDValue(N, 0); 1153} 1154 1155SDValue SelectionDAG::getRegister(unsigned RegNo, MVT VT) { 1156 FoldingSetNodeID ID; 1157 AddNodeIDNode(ID, ISD::Register, getVTList(VT), 0, 0); 1158 ID.AddInteger(RegNo); 1159 void *IP = 0; 1160 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1161 return SDValue(E, 0); 1162 SDNode *N = NodeAllocator.Allocate<RegisterSDNode>(); 1163 new (N) RegisterSDNode(RegNo, VT); 1164 CSEMap.InsertNode(N, IP); 1165 AllNodes.push_back(N); 1166 return SDValue(N, 0); 1167} 1168 1169SDValue SelectionDAG::getDbgStopPoint(SDValue Root, 1170 unsigned Line, unsigned Col, 1171 const CompileUnitDesc *CU) { 1172 SDNode *N = NodeAllocator.Allocate<DbgStopPointSDNode>(); 1173 new (N) DbgStopPointSDNode(Root, Line, Col, CU); 1174 AllNodes.push_back(N); 1175 return SDValue(N, 0); 1176} 1177 1178SDValue SelectionDAG::getLabel(unsigned Opcode, 1179 SDValue Root, 1180 unsigned LabelID) { 1181 FoldingSetNodeID ID; 1182 SDValue Ops[] = { Root }; 1183 AddNodeIDNode(ID, Opcode, getVTList(MVT::Other), &Ops[0], 1); 1184 ID.AddInteger(LabelID); 1185 void *IP = 0; 1186 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1187 return SDValue(E, 0); 1188 SDNode *N = NodeAllocator.Allocate<LabelSDNode>(); 1189 new (N) LabelSDNode(Opcode, Root, LabelID); 1190 CSEMap.InsertNode(N, IP); 1191 AllNodes.push_back(N); 1192 return SDValue(N, 0); 1193} 1194 1195SDValue SelectionDAG::getSrcValue(const Value *V) { 1196 assert((!V || isa<PointerType>(V->getType())) && 1197 "SrcValue is not a pointer?"); 1198 1199 FoldingSetNodeID ID; 1200 AddNodeIDNode(ID, ISD::SRCVALUE, getVTList(MVT::Other), 0, 0); 1201 ID.AddPointer(V); 1202 1203 void *IP = 0; 1204 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1205 return SDValue(E, 0); 1206 1207 SDNode *N = NodeAllocator.Allocate<SrcValueSDNode>(); 1208 new (N) SrcValueSDNode(V); 1209 CSEMap.InsertNode(N, IP); 1210 AllNodes.push_back(N); 1211 return SDValue(N, 0); 1212} 1213 1214SDValue SelectionDAG::getMemOperand(const MachineMemOperand &MO) { 1215 const Value *v = MO.getValue(); 1216 assert((!v || isa<PointerType>(v->getType())) && 1217 "SrcValue is not a pointer?"); 1218 1219 FoldingSetNodeID ID; 1220 AddNodeIDNode(ID, ISD::MEMOPERAND, getVTList(MVT::Other), 0, 0); 1221 MO.Profile(ID); 1222 1223 void *IP = 0; 1224 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1225 return SDValue(E, 0); 1226 1227 SDNode *N = NodeAllocator.Allocate<MemOperandSDNode>(); 1228 new (N) MemOperandSDNode(MO); 1229 CSEMap.InsertNode(N, IP); 1230 AllNodes.push_back(N); 1231 return SDValue(N, 0); 1232} 1233 1234/// CreateStackTemporary - Create a stack temporary, suitable for holding the 1235/// specified value type. 1236SDValue SelectionDAG::CreateStackTemporary(MVT VT, unsigned minAlign) { 1237 MachineFrameInfo *FrameInfo = getMachineFunction().getFrameInfo(); 1238 unsigned ByteSize = VT.getSizeInBits()/8; 1239 const Type *Ty = VT.getTypeForMVT(); 1240 unsigned StackAlign = 1241 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), minAlign); 1242 1243 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, StackAlign); 1244 return getFrameIndex(FrameIdx, TLI.getPointerTy()); 1245} 1246 1247SDValue SelectionDAG::FoldSetCC(MVT VT, SDValue N1, 1248 SDValue N2, ISD::CondCode Cond) { 1249 // These setcc operations always fold. 1250 switch (Cond) { 1251 default: break; 1252 case ISD::SETFALSE: 1253 case ISD::SETFALSE2: return getConstant(0, VT); 1254 case ISD::SETTRUE: 1255 case ISD::SETTRUE2: return getConstant(1, VT); 1256 1257 case ISD::SETOEQ: 1258 case ISD::SETOGT: 1259 case ISD::SETOGE: 1260 case ISD::SETOLT: 1261 case ISD::SETOLE: 1262 case ISD::SETONE: 1263 case ISD::SETO: 1264 case ISD::SETUO: 1265 case ISD::SETUEQ: 1266 case ISD::SETUNE: 1267 assert(!N1.getValueType().isInteger() && "Illegal setcc for integer!"); 1268 break; 1269 } 1270 1271 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode())) { 1272 const APInt &C2 = N2C->getAPIntValue(); 1273 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) { 1274 const APInt &C1 = N1C->getAPIntValue(); 1275 1276 switch (Cond) { 1277 default: assert(0 && "Unknown integer setcc!"); 1278 case ISD::SETEQ: return getConstant(C1 == C2, VT); 1279 case ISD::SETNE: return getConstant(C1 != C2, VT); 1280 case ISD::SETULT: return getConstant(C1.ult(C2), VT); 1281 case ISD::SETUGT: return getConstant(C1.ugt(C2), VT); 1282 case ISD::SETULE: return getConstant(C1.ule(C2), VT); 1283 case ISD::SETUGE: return getConstant(C1.uge(C2), VT); 1284 case ISD::SETLT: return getConstant(C1.slt(C2), VT); 1285 case ISD::SETGT: return getConstant(C1.sgt(C2), VT); 1286 case ISD::SETLE: return getConstant(C1.sle(C2), VT); 1287 case ISD::SETGE: return getConstant(C1.sge(C2), VT); 1288 } 1289 } 1290 } 1291 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.getNode())) { 1292 if (ConstantFPSDNode *N2C = dyn_cast<ConstantFPSDNode>(N2.getNode())) { 1293 // No compile time operations on this type yet. 1294 if (N1C->getValueType(0) == MVT::ppcf128) 1295 return SDValue(); 1296 1297 APFloat::cmpResult R = N1C->getValueAPF().compare(N2C->getValueAPF()); 1298 switch (Cond) { 1299 default: break; 1300 case ISD::SETEQ: if (R==APFloat::cmpUnordered) 1301 return getNode(ISD::UNDEF, VT); 1302 // fall through 1303 case ISD::SETOEQ: return getConstant(R==APFloat::cmpEqual, VT); 1304 case ISD::SETNE: if (R==APFloat::cmpUnordered) 1305 return getNode(ISD::UNDEF, VT); 1306 // fall through 1307 case ISD::SETONE: return getConstant(R==APFloat::cmpGreaterThan || 1308 R==APFloat::cmpLessThan, VT); 1309 case ISD::SETLT: if (R==APFloat::cmpUnordered) 1310 return getNode(ISD::UNDEF, VT); 1311 // fall through 1312 case ISD::SETOLT: return getConstant(R==APFloat::cmpLessThan, VT); 1313 case ISD::SETGT: if (R==APFloat::cmpUnordered) 1314 return getNode(ISD::UNDEF, VT); 1315 // fall through 1316 case ISD::SETOGT: return getConstant(R==APFloat::cmpGreaterThan, VT); 1317 case ISD::SETLE: if (R==APFloat::cmpUnordered) 1318 return getNode(ISD::UNDEF, VT); 1319 // fall through 1320 case ISD::SETOLE: return getConstant(R==APFloat::cmpLessThan || 1321 R==APFloat::cmpEqual, VT); 1322 case ISD::SETGE: if (R==APFloat::cmpUnordered) 1323 return getNode(ISD::UNDEF, VT); 1324 // fall through 1325 case ISD::SETOGE: return getConstant(R==APFloat::cmpGreaterThan || 1326 R==APFloat::cmpEqual, VT); 1327 case ISD::SETO: return getConstant(R!=APFloat::cmpUnordered, VT); 1328 case ISD::SETUO: return getConstant(R==APFloat::cmpUnordered, VT); 1329 case ISD::SETUEQ: return getConstant(R==APFloat::cmpUnordered || 1330 R==APFloat::cmpEqual, VT); 1331 case ISD::SETUNE: return getConstant(R!=APFloat::cmpEqual, VT); 1332 case ISD::SETULT: return getConstant(R==APFloat::cmpUnordered || 1333 R==APFloat::cmpLessThan, VT); 1334 case ISD::SETUGT: return getConstant(R==APFloat::cmpGreaterThan || 1335 R==APFloat::cmpUnordered, VT); 1336 case ISD::SETULE: return getConstant(R!=APFloat::cmpGreaterThan, VT); 1337 case ISD::SETUGE: return getConstant(R!=APFloat::cmpLessThan, VT); 1338 } 1339 } else { 1340 // Ensure that the constant occurs on the RHS. 1341 return getSetCC(VT, N2, N1, ISD::getSetCCSwappedOperands(Cond)); 1342 } 1343 } 1344 1345 // Could not fold it. 1346 return SDValue(); 1347} 1348 1349/// SignBitIsZero - Return true if the sign bit of Op is known to be zero. We 1350/// use this predicate to simplify operations downstream. 1351bool SelectionDAG::SignBitIsZero(SDValue Op, unsigned Depth) const { 1352 unsigned BitWidth = Op.getValueSizeInBits(); 1353 return MaskedValueIsZero(Op, APInt::getSignBit(BitWidth), Depth); 1354} 1355 1356/// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero. We use 1357/// this predicate to simplify operations downstream. Mask is known to be zero 1358/// for bits that V cannot have. 1359bool SelectionDAG::MaskedValueIsZero(SDValue Op, const APInt &Mask, 1360 unsigned Depth) const { 1361 APInt KnownZero, KnownOne; 1362 ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth); 1363 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1364 return (KnownZero & Mask) == Mask; 1365} 1366 1367/// ComputeMaskedBits - Determine which of the bits specified in Mask are 1368/// known to be either zero or one and return them in the KnownZero/KnownOne 1369/// bitsets. This code only analyzes bits in Mask, in order to short-circuit 1370/// processing. 1371void SelectionDAG::ComputeMaskedBits(SDValue Op, const APInt &Mask, 1372 APInt &KnownZero, APInt &KnownOne, 1373 unsigned Depth) const { 1374 unsigned BitWidth = Mask.getBitWidth(); 1375 assert(BitWidth == Op.getValueType().getSizeInBits() && 1376 "Mask size mismatches value type size!"); 1377 1378 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything. 1379 if (Depth == 6 || Mask == 0) 1380 return; // Limit search depth. 1381 1382 APInt KnownZero2, KnownOne2; 1383 1384 switch (Op.getOpcode()) { 1385 case ISD::Constant: 1386 // We know all of the bits for a constant! 1387 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & Mask; 1388 KnownZero = ~KnownOne & Mask; 1389 return; 1390 case ISD::AND: 1391 // If either the LHS or the RHS are Zero, the result is zero. 1392 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1393 ComputeMaskedBits(Op.getOperand(0), Mask & ~KnownZero, 1394 KnownZero2, KnownOne2, Depth+1); 1395 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1396 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1397 1398 // Output known-1 bits are only known if set in both the LHS & RHS. 1399 KnownOne &= KnownOne2; 1400 // Output known-0 are known to be clear if zero in either the LHS | RHS. 1401 KnownZero |= KnownZero2; 1402 return; 1403 case ISD::OR: 1404 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1405 ComputeMaskedBits(Op.getOperand(0), Mask & ~KnownOne, 1406 KnownZero2, KnownOne2, Depth+1); 1407 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1408 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1409 1410 // Output known-0 bits are only known if clear in both the LHS & RHS. 1411 KnownZero &= KnownZero2; 1412 // Output known-1 are known to be set if set in either the LHS | RHS. 1413 KnownOne |= KnownOne2; 1414 return; 1415 case ISD::XOR: { 1416 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1417 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1); 1418 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1419 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1420 1421 // Output known-0 bits are known if clear or set in both the LHS & RHS. 1422 APInt KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 1423 // Output known-1 are known to be set if set in only one of the LHS, RHS. 1424 KnownOne = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 1425 KnownZero = KnownZeroOut; 1426 return; 1427 } 1428 case ISD::MUL: { 1429 APInt Mask2 = APInt::getAllOnesValue(BitWidth); 1430 ComputeMaskedBits(Op.getOperand(1), Mask2, KnownZero, KnownOne, Depth+1); 1431 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero2, KnownOne2, Depth+1); 1432 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1433 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1434 1435 // If low bits are zero in either operand, output low known-0 bits. 1436 // Also compute a conserative estimate for high known-0 bits. 1437 // More trickiness is possible, but this is sufficient for the 1438 // interesting case of alignment computation. 1439 KnownOne.clear(); 1440 unsigned TrailZ = KnownZero.countTrailingOnes() + 1441 KnownZero2.countTrailingOnes(); 1442 unsigned LeadZ = std::max(KnownZero.countLeadingOnes() + 1443 KnownZero2.countLeadingOnes(), 1444 BitWidth) - BitWidth; 1445 1446 TrailZ = std::min(TrailZ, BitWidth); 1447 LeadZ = std::min(LeadZ, BitWidth); 1448 KnownZero = APInt::getLowBitsSet(BitWidth, TrailZ) | 1449 APInt::getHighBitsSet(BitWidth, LeadZ); 1450 KnownZero &= Mask; 1451 return; 1452 } 1453 case ISD::UDIV: { 1454 // For the purposes of computing leading zeros we can conservatively 1455 // treat a udiv as a logical right shift by the power of 2 known to 1456 // be less than the denominator. 1457 APInt AllOnes = APInt::getAllOnesValue(BitWidth); 1458 ComputeMaskedBits(Op.getOperand(0), 1459 AllOnes, KnownZero2, KnownOne2, Depth+1); 1460 unsigned LeadZ = KnownZero2.countLeadingOnes(); 1461 1462 KnownOne2.clear(); 1463 KnownZero2.clear(); 1464 ComputeMaskedBits(Op.getOperand(1), 1465 AllOnes, KnownZero2, KnownOne2, Depth+1); 1466 unsigned RHSUnknownLeadingOnes = KnownOne2.countLeadingZeros(); 1467 if (RHSUnknownLeadingOnes != BitWidth) 1468 LeadZ = std::min(BitWidth, 1469 LeadZ + BitWidth - RHSUnknownLeadingOnes - 1); 1470 1471 KnownZero = APInt::getHighBitsSet(BitWidth, LeadZ) & Mask; 1472 return; 1473 } 1474 case ISD::SELECT: 1475 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero, KnownOne, Depth+1); 1476 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero2, KnownOne2, Depth+1); 1477 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1478 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1479 1480 // Only known if known in both the LHS and RHS. 1481 KnownOne &= KnownOne2; 1482 KnownZero &= KnownZero2; 1483 return; 1484 case ISD::SELECT_CC: 1485 ComputeMaskedBits(Op.getOperand(3), Mask, KnownZero, KnownOne, Depth+1); 1486 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero2, KnownOne2, Depth+1); 1487 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1488 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1489 1490 // Only known if known in both the LHS and RHS. 1491 KnownOne &= KnownOne2; 1492 KnownZero &= KnownZero2; 1493 return; 1494 case ISD::SADDO: 1495 case ISD::UADDO: 1496 if (Op.getResNo() != 1) 1497 return; 1498 // The boolean result conforms to getBooleanContents. Fall through. 1499 case ISD::SETCC: 1500 // If we know the result of a setcc has the top bits zero, use this info. 1501 if (TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent && 1502 BitWidth > 1) 1503 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1); 1504 return; 1505 case ISD::SHL: 1506 // (shl X, C1) & C2 == 0 iff (X & C2 >>u C1) == 0 1507 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1508 unsigned ShAmt = SA->getZExtValue(); 1509 1510 // If the shift count is an invalid immediate, don't do anything. 1511 if (ShAmt >= BitWidth) 1512 return; 1513 1514 ComputeMaskedBits(Op.getOperand(0), Mask.lshr(ShAmt), 1515 KnownZero, KnownOne, Depth+1); 1516 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1517 KnownZero <<= ShAmt; 1518 KnownOne <<= ShAmt; 1519 // low bits known zero. 1520 KnownZero |= APInt::getLowBitsSet(BitWidth, ShAmt); 1521 } 1522 return; 1523 case ISD::SRL: 1524 // (ushr X, C1) & C2 == 0 iff (-1 >> C1) & C2 == 0 1525 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1526 unsigned ShAmt = SA->getZExtValue(); 1527 1528 // If the shift count is an invalid immediate, don't do anything. 1529 if (ShAmt >= BitWidth) 1530 return; 1531 1532 ComputeMaskedBits(Op.getOperand(0), (Mask << ShAmt), 1533 KnownZero, KnownOne, Depth+1); 1534 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1535 KnownZero = KnownZero.lshr(ShAmt); 1536 KnownOne = KnownOne.lshr(ShAmt); 1537 1538 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt) & Mask; 1539 KnownZero |= HighBits; // High bits known zero. 1540 } 1541 return; 1542 case ISD::SRA: 1543 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1544 unsigned ShAmt = SA->getZExtValue(); 1545 1546 // If the shift count is an invalid immediate, don't do anything. 1547 if (ShAmt >= BitWidth) 1548 return; 1549 1550 APInt InDemandedMask = (Mask << ShAmt); 1551 // If any of the demanded bits are produced by the sign extension, we also 1552 // demand the input sign bit. 1553 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt) & Mask; 1554 if (HighBits.getBoolValue()) 1555 InDemandedMask |= APInt::getSignBit(BitWidth); 1556 1557 ComputeMaskedBits(Op.getOperand(0), InDemandedMask, KnownZero, KnownOne, 1558 Depth+1); 1559 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1560 KnownZero = KnownZero.lshr(ShAmt); 1561 KnownOne = KnownOne.lshr(ShAmt); 1562 1563 // Handle the sign bits. 1564 APInt SignBit = APInt::getSignBit(BitWidth); 1565 SignBit = SignBit.lshr(ShAmt); // Adjust to where it is now in the mask. 1566 1567 if (KnownZero.intersects(SignBit)) { 1568 KnownZero |= HighBits; // New bits are known zero. 1569 } else if (KnownOne.intersects(SignBit)) { 1570 KnownOne |= HighBits; // New bits are known one. 1571 } 1572 } 1573 return; 1574 case ISD::SIGN_EXTEND_INREG: { 1575 MVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1576 unsigned EBits = EVT.getSizeInBits(); 1577 1578 // Sign extension. Compute the demanded bits in the result that are not 1579 // present in the input. 1580 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - EBits) & Mask; 1581 1582 APInt InSignBit = APInt::getSignBit(EBits); 1583 APInt InputDemandedBits = Mask & APInt::getLowBitsSet(BitWidth, EBits); 1584 1585 // If the sign extended bits are demanded, we know that the sign 1586 // bit is demanded. 1587 InSignBit.zext(BitWidth); 1588 if (NewBits.getBoolValue()) 1589 InputDemandedBits |= InSignBit; 1590 1591 ComputeMaskedBits(Op.getOperand(0), InputDemandedBits, 1592 KnownZero, KnownOne, Depth+1); 1593 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1594 1595 // If the sign bit of the input is known set or clear, then we know the 1596 // top bits of the result. 1597 if (KnownZero.intersects(InSignBit)) { // Input sign bit known clear 1598 KnownZero |= NewBits; 1599 KnownOne &= ~NewBits; 1600 } else if (KnownOne.intersects(InSignBit)) { // Input sign bit known set 1601 KnownOne |= NewBits; 1602 KnownZero &= ~NewBits; 1603 } else { // Input sign bit unknown 1604 KnownZero &= ~NewBits; 1605 KnownOne &= ~NewBits; 1606 } 1607 return; 1608 } 1609 case ISD::CTTZ: 1610 case ISD::CTLZ: 1611 case ISD::CTPOP: { 1612 unsigned LowBits = Log2_32(BitWidth)+1; 1613 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - LowBits); 1614 KnownOne.clear(); 1615 return; 1616 } 1617 case ISD::LOAD: { 1618 if (ISD::isZEXTLoad(Op.getNode())) { 1619 LoadSDNode *LD = cast<LoadSDNode>(Op); 1620 MVT VT = LD->getMemoryVT(); 1621 unsigned MemBits = VT.getSizeInBits(); 1622 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits) & Mask; 1623 } 1624 return; 1625 } 1626 case ISD::ZERO_EXTEND: { 1627 MVT InVT = Op.getOperand(0).getValueType(); 1628 unsigned InBits = InVT.getSizeInBits(); 1629 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - InBits) & Mask; 1630 APInt InMask = Mask; 1631 InMask.trunc(InBits); 1632 KnownZero.trunc(InBits); 1633 KnownOne.trunc(InBits); 1634 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1635 KnownZero.zext(BitWidth); 1636 KnownOne.zext(BitWidth); 1637 KnownZero |= NewBits; 1638 return; 1639 } 1640 case ISD::SIGN_EXTEND: { 1641 MVT InVT = Op.getOperand(0).getValueType(); 1642 unsigned InBits = InVT.getSizeInBits(); 1643 APInt InSignBit = APInt::getSignBit(InBits); 1644 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - InBits) & Mask; 1645 APInt InMask = Mask; 1646 InMask.trunc(InBits); 1647 1648 // If any of the sign extended bits are demanded, we know that the sign 1649 // bit is demanded. Temporarily set this bit in the mask for our callee. 1650 if (NewBits.getBoolValue()) 1651 InMask |= InSignBit; 1652 1653 KnownZero.trunc(InBits); 1654 KnownOne.trunc(InBits); 1655 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1656 1657 // Note if the sign bit is known to be zero or one. 1658 bool SignBitKnownZero = KnownZero.isNegative(); 1659 bool SignBitKnownOne = KnownOne.isNegative(); 1660 assert(!(SignBitKnownZero && SignBitKnownOne) && 1661 "Sign bit can't be known to be both zero and one!"); 1662 1663 // If the sign bit wasn't actually demanded by our caller, we don't 1664 // want it set in the KnownZero and KnownOne result values. Reset the 1665 // mask and reapply it to the result values. 1666 InMask = Mask; 1667 InMask.trunc(InBits); 1668 KnownZero &= InMask; 1669 KnownOne &= InMask; 1670 1671 KnownZero.zext(BitWidth); 1672 KnownOne.zext(BitWidth); 1673 1674 // If the sign bit is known zero or one, the top bits match. 1675 if (SignBitKnownZero) 1676 KnownZero |= NewBits; 1677 else if (SignBitKnownOne) 1678 KnownOne |= NewBits; 1679 return; 1680 } 1681 case ISD::ANY_EXTEND: { 1682 MVT InVT = Op.getOperand(0).getValueType(); 1683 unsigned InBits = InVT.getSizeInBits(); 1684 APInt InMask = Mask; 1685 InMask.trunc(InBits); 1686 KnownZero.trunc(InBits); 1687 KnownOne.trunc(InBits); 1688 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1689 KnownZero.zext(BitWidth); 1690 KnownOne.zext(BitWidth); 1691 return; 1692 } 1693 case ISD::TRUNCATE: { 1694 MVT InVT = Op.getOperand(0).getValueType(); 1695 unsigned InBits = InVT.getSizeInBits(); 1696 APInt InMask = Mask; 1697 InMask.zext(InBits); 1698 KnownZero.zext(InBits); 1699 KnownOne.zext(InBits); 1700 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1701 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1702 KnownZero.trunc(BitWidth); 1703 KnownOne.trunc(BitWidth); 1704 break; 1705 } 1706 case ISD::AssertZext: { 1707 MVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1708 APInt InMask = APInt::getLowBitsSet(BitWidth, VT.getSizeInBits()); 1709 ComputeMaskedBits(Op.getOperand(0), Mask & InMask, KnownZero, 1710 KnownOne, Depth+1); 1711 KnownZero |= (~InMask) & Mask; 1712 return; 1713 } 1714 case ISD::FGETSIGN: 1715 // All bits are zero except the low bit. 1716 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - 1); 1717 return; 1718 1719 case ISD::SUB: { 1720 if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) { 1721 // We know that the top bits of C-X are clear if X contains less bits 1722 // than C (i.e. no wrap-around can happen). For example, 20-X is 1723 // positive if we can prove that X is >= 0 and < 16. 1724 if (CLHS->getAPIntValue().isNonNegative()) { 1725 unsigned NLZ = (CLHS->getAPIntValue()+1).countLeadingZeros(); 1726 // NLZ can't be BitWidth with no sign bit 1727 APInt MaskV = APInt::getHighBitsSet(BitWidth, NLZ+1); 1728 ComputeMaskedBits(Op.getOperand(1), MaskV, KnownZero2, KnownOne2, 1729 Depth+1); 1730 1731 // If all of the MaskV bits are known to be zero, then we know the 1732 // output top bits are zero, because we now know that the output is 1733 // from [0-C]. 1734 if ((KnownZero2 & MaskV) == MaskV) { 1735 unsigned NLZ2 = CLHS->getAPIntValue().countLeadingZeros(); 1736 // Top bits known zero. 1737 KnownZero = APInt::getHighBitsSet(BitWidth, NLZ2) & Mask; 1738 } 1739 } 1740 } 1741 } 1742 // fall through 1743 case ISD::ADD: { 1744 // Output known-0 bits are known if clear or set in both the low clear bits 1745 // common to both LHS & RHS. For example, 8+(X<<3) is known to have the 1746 // low 3 bits clear. 1747 APInt Mask2 = APInt::getLowBitsSet(BitWidth, Mask.countTrailingOnes()); 1748 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero2, KnownOne2, Depth+1); 1749 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1750 unsigned KnownZeroOut = KnownZero2.countTrailingOnes(); 1751 1752 ComputeMaskedBits(Op.getOperand(1), Mask2, KnownZero2, KnownOne2, Depth+1); 1753 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1754 KnownZeroOut = std::min(KnownZeroOut, 1755 KnownZero2.countTrailingOnes()); 1756 1757 KnownZero |= APInt::getLowBitsSet(BitWidth, KnownZeroOut); 1758 return; 1759 } 1760 case ISD::SREM: 1761 if (ConstantSDNode *Rem = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1762 const APInt &RA = Rem->getAPIntValue(); 1763 if (RA.isPowerOf2() || (-RA).isPowerOf2()) { 1764 APInt LowBits = RA.isStrictlyPositive() ? (RA - 1) : ~RA; 1765 APInt Mask2 = LowBits | APInt::getSignBit(BitWidth); 1766 ComputeMaskedBits(Op.getOperand(0), Mask2,KnownZero2,KnownOne2,Depth+1); 1767 1768 // If the sign bit of the first operand is zero, the sign bit of 1769 // the result is zero. If the first operand has no one bits below 1770 // the second operand's single 1 bit, its sign will be zero. 1771 if (KnownZero2[BitWidth-1] || ((KnownZero2 & LowBits) == LowBits)) 1772 KnownZero2 |= ~LowBits; 1773 1774 KnownZero |= KnownZero2 & Mask; 1775 1776 assert((KnownZero & KnownOne) == 0&&"Bits known to be one AND zero?"); 1777 } 1778 } 1779 return; 1780 case ISD::UREM: { 1781 if (ConstantSDNode *Rem = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1782 const APInt &RA = Rem->getAPIntValue(); 1783 if (RA.isPowerOf2()) { 1784 APInt LowBits = (RA - 1); 1785 APInt Mask2 = LowBits & Mask; 1786 KnownZero |= ~LowBits & Mask; 1787 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero, KnownOne,Depth+1); 1788 assert((KnownZero & KnownOne) == 0&&"Bits known to be one AND zero?"); 1789 break; 1790 } 1791 } 1792 1793 // Since the result is less than or equal to either operand, any leading 1794 // zero bits in either operand must also exist in the result. 1795 APInt AllOnes = APInt::getAllOnesValue(BitWidth); 1796 ComputeMaskedBits(Op.getOperand(0), AllOnes, KnownZero, KnownOne, 1797 Depth+1); 1798 ComputeMaskedBits(Op.getOperand(1), AllOnes, KnownZero2, KnownOne2, 1799 Depth+1); 1800 1801 uint32_t Leaders = std::max(KnownZero.countLeadingOnes(), 1802 KnownZero2.countLeadingOnes()); 1803 KnownOne.clear(); 1804 KnownZero = APInt::getHighBitsSet(BitWidth, Leaders) & Mask; 1805 return; 1806 } 1807 default: 1808 // Allow the target to implement this method for its nodes. 1809 if (Op.getOpcode() >= ISD::BUILTIN_OP_END) { 1810 case ISD::INTRINSIC_WO_CHAIN: 1811 case ISD::INTRINSIC_W_CHAIN: 1812 case ISD::INTRINSIC_VOID: 1813 TLI.computeMaskedBitsForTargetNode(Op, Mask, KnownZero, KnownOne, *this); 1814 } 1815 return; 1816 } 1817} 1818 1819/// ComputeNumSignBits - Return the number of times the sign bit of the 1820/// register is replicated into the other bits. We know that at least 1 bit 1821/// is always equal to the sign bit (itself), but other cases can give us 1822/// information. For example, immediately after an "SRA X, 2", we know that 1823/// the top 3 bits are all equal to each other, so we return 3. 1824unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, unsigned Depth) const{ 1825 MVT VT = Op.getValueType(); 1826 assert(VT.isInteger() && "Invalid VT!"); 1827 unsigned VTBits = VT.getSizeInBits(); 1828 unsigned Tmp, Tmp2; 1829 unsigned FirstAnswer = 1; 1830 1831 if (Depth == 6) 1832 return 1; // Limit search depth. 1833 1834 switch (Op.getOpcode()) { 1835 default: break; 1836 case ISD::AssertSext: 1837 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); 1838 return VTBits-Tmp+1; 1839 case ISD::AssertZext: 1840 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); 1841 return VTBits-Tmp; 1842 1843 case ISD::Constant: { 1844 const APInt &Val = cast<ConstantSDNode>(Op)->getAPIntValue(); 1845 // If negative, return # leading ones. 1846 if (Val.isNegative()) 1847 return Val.countLeadingOnes(); 1848 1849 // Return # leading zeros. 1850 return Val.countLeadingZeros(); 1851 } 1852 1853 case ISD::SIGN_EXTEND: 1854 Tmp = VTBits-Op.getOperand(0).getValueType().getSizeInBits(); 1855 return ComputeNumSignBits(Op.getOperand(0), Depth+1) + Tmp; 1856 1857 case ISD::SIGN_EXTEND_INREG: 1858 // Max of the input and what this extends. 1859 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); 1860 Tmp = VTBits-Tmp+1; 1861 1862 Tmp2 = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1863 return std::max(Tmp, Tmp2); 1864 1865 case ISD::SRA: 1866 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1867 // SRA X, C -> adds C sign bits. 1868 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1869 Tmp += C->getZExtValue(); 1870 if (Tmp > VTBits) Tmp = VTBits; 1871 } 1872 return Tmp; 1873 case ISD::SHL: 1874 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1875 // shl destroys sign bits. 1876 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1877 if (C->getZExtValue() >= VTBits || // Bad shift. 1878 C->getZExtValue() >= Tmp) break; // Shifted all sign bits out. 1879 return Tmp - C->getZExtValue(); 1880 } 1881 break; 1882 case ISD::AND: 1883 case ISD::OR: 1884 case ISD::XOR: // NOT is handled here. 1885 // Logical binary ops preserve the number of sign bits at the worst. 1886 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1887 if (Tmp != 1) { 1888 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 1889 FirstAnswer = std::min(Tmp, Tmp2); 1890 // We computed what we know about the sign bits as our first 1891 // answer. Now proceed to the generic code that uses 1892 // ComputeMaskedBits, and pick whichever answer is better. 1893 } 1894 break; 1895 1896 case ISD::SELECT: 1897 Tmp = ComputeNumSignBits(Op.getOperand(1), Depth+1); 1898 if (Tmp == 1) return 1; // Early out. 1899 Tmp2 = ComputeNumSignBits(Op.getOperand(2), Depth+1); 1900 return std::min(Tmp, Tmp2); 1901 1902 case ISD::SADDO: 1903 case ISD::UADDO: 1904 if (Op.getResNo() != 1) 1905 break; 1906 // The boolean result conforms to getBooleanContents. Fall through. 1907 case ISD::SETCC: 1908 // If setcc returns 0/-1, all bits are sign bits. 1909 if (TLI.getBooleanContents() == 1910 TargetLowering::ZeroOrNegativeOneBooleanContent) 1911 return VTBits; 1912 break; 1913 case ISD::ROTL: 1914 case ISD::ROTR: 1915 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1916 unsigned RotAmt = C->getZExtValue() & (VTBits-1); 1917 1918 // Handle rotate right by N like a rotate left by 32-N. 1919 if (Op.getOpcode() == ISD::ROTR) 1920 RotAmt = (VTBits-RotAmt) & (VTBits-1); 1921 1922 // If we aren't rotating out all of the known-in sign bits, return the 1923 // number that are left. This handles rotl(sext(x), 1) for example. 1924 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1925 if (Tmp > RotAmt+1) return Tmp-RotAmt; 1926 } 1927 break; 1928 case ISD::ADD: 1929 // Add can have at most one carry bit. Thus we know that the output 1930 // is, at worst, one more bit than the inputs. 1931 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1932 if (Tmp == 1) return 1; // Early out. 1933 1934 // Special case decrementing a value (ADD X, -1): 1935 if (ConstantSDNode *CRHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) 1936 if (CRHS->isAllOnesValue()) { 1937 APInt KnownZero, KnownOne; 1938 APInt Mask = APInt::getAllOnesValue(VTBits); 1939 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1); 1940 1941 // If the input is known to be 0 or 1, the output is 0/-1, which is all 1942 // sign bits set. 1943 if ((KnownZero | APInt(VTBits, 1)) == Mask) 1944 return VTBits; 1945 1946 // If we are subtracting one from a positive number, there is no carry 1947 // out of the result. 1948 if (KnownZero.isNegative()) 1949 return Tmp; 1950 } 1951 1952 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 1953 if (Tmp2 == 1) return 1; 1954 return std::min(Tmp, Tmp2)-1; 1955 break; 1956 1957 case ISD::SUB: 1958 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 1959 if (Tmp2 == 1) return 1; 1960 1961 // Handle NEG. 1962 if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) 1963 if (CLHS->isNullValue()) { 1964 APInt KnownZero, KnownOne; 1965 APInt Mask = APInt::getAllOnesValue(VTBits); 1966 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1967 // If the input is known to be 0 or 1, the output is 0/-1, which is all 1968 // sign bits set. 1969 if ((KnownZero | APInt(VTBits, 1)) == Mask) 1970 return VTBits; 1971 1972 // If the input is known to be positive (the sign bit is known clear), 1973 // the output of the NEG has the same number of sign bits as the input. 1974 if (KnownZero.isNegative()) 1975 return Tmp2; 1976 1977 // Otherwise, we treat this like a SUB. 1978 } 1979 1980 // Sub can have at most one carry bit. Thus we know that the output 1981 // is, at worst, one more bit than the inputs. 1982 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1983 if (Tmp == 1) return 1; // Early out. 1984 return std::min(Tmp, Tmp2)-1; 1985 break; 1986 case ISD::TRUNCATE: 1987 // FIXME: it's tricky to do anything useful for this, but it is an important 1988 // case for targets like X86. 1989 break; 1990 } 1991 1992 // Handle LOADX separately here. EXTLOAD case will fallthrough. 1993 if (Op.getOpcode() == ISD::LOAD) { 1994 LoadSDNode *LD = cast<LoadSDNode>(Op); 1995 unsigned ExtType = LD->getExtensionType(); 1996 switch (ExtType) { 1997 default: break; 1998 case ISD::SEXTLOAD: // '17' bits known 1999 Tmp = LD->getMemoryVT().getSizeInBits(); 2000 return VTBits-Tmp+1; 2001 case ISD::ZEXTLOAD: // '16' bits known 2002 Tmp = LD->getMemoryVT().getSizeInBits(); 2003 return VTBits-Tmp; 2004 } 2005 } 2006 2007 // Allow the target to implement this method for its nodes. 2008 if (Op.getOpcode() >= ISD::BUILTIN_OP_END || 2009 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 2010 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 2011 Op.getOpcode() == ISD::INTRINSIC_VOID) { 2012 unsigned NumBits = TLI.ComputeNumSignBitsForTargetNode(Op, Depth); 2013 if (NumBits > 1) FirstAnswer = std::max(FirstAnswer, NumBits); 2014 } 2015 2016 // Finally, if we can prove that the top bits of the result are 0's or 1's, 2017 // use this information. 2018 APInt KnownZero, KnownOne; 2019 APInt Mask = APInt::getAllOnesValue(VTBits); 2020 ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth); 2021 2022 if (KnownZero.isNegative()) { // sign bit is 0 2023 Mask = KnownZero; 2024 } else if (KnownOne.isNegative()) { // sign bit is 1; 2025 Mask = KnownOne; 2026 } else { 2027 // Nothing known. 2028 return FirstAnswer; 2029 } 2030 2031 // Okay, we know that the sign bit in Mask is set. Use CLZ to determine 2032 // the number of identical bits in the top of the input value. 2033 Mask = ~Mask; 2034 Mask <<= Mask.getBitWidth()-VTBits; 2035 // Return # leading zeros. We use 'min' here in case Val was zero before 2036 // shifting. We don't want to return '64' as for an i32 "0". 2037 return std::max(FirstAnswer, std::min(VTBits, Mask.countLeadingZeros())); 2038} 2039 2040 2041bool SelectionDAG::isVerifiedDebugInfoDesc(SDValue Op) const { 2042 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op); 2043 if (!GA) return false; 2044 if (GA->getOffset() != 0) return false; 2045 GlobalVariable *GV = dyn_cast<GlobalVariable>(GA->getGlobal()); 2046 if (!GV) return false; 2047 MachineModuleInfo *MMI = getMachineModuleInfo(); 2048 return MMI && MMI->hasDebugInfo() && MMI->isVerified(GV); 2049} 2050 2051 2052/// getShuffleScalarElt - Returns the scalar element that will make up the ith 2053/// element of the result of the vector shuffle. 2054SDValue SelectionDAG::getShuffleScalarElt(const SDNode *N, unsigned i) { 2055 MVT VT = N->getValueType(0); 2056 SDValue PermMask = N->getOperand(2); 2057 SDValue Idx = PermMask.getOperand(i); 2058 if (Idx.getOpcode() == ISD::UNDEF) 2059 return getNode(ISD::UNDEF, VT.getVectorElementType()); 2060 unsigned Index = cast<ConstantSDNode>(Idx)->getZExtValue(); 2061 unsigned NumElems = PermMask.getNumOperands(); 2062 SDValue V = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1); 2063 Index %= NumElems; 2064 2065 if (V.getOpcode() == ISD::BIT_CONVERT) { 2066 V = V.getOperand(0); 2067 if (V.getValueType().getVectorNumElements() != NumElems) 2068 return SDValue(); 2069 } 2070 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) 2071 return (Index == 0) ? V.getOperand(0) 2072 : getNode(ISD::UNDEF, VT.getVectorElementType()); 2073 if (V.getOpcode() == ISD::BUILD_VECTOR) 2074 return V.getOperand(Index); 2075 if (V.getOpcode() == ISD::VECTOR_SHUFFLE) 2076 return getShuffleScalarElt(V.getNode(), Index); 2077 return SDValue(); 2078} 2079 2080 2081/// getNode - Gets or creates the specified node. 2082/// 2083SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT) { 2084 FoldingSetNodeID ID; 2085 AddNodeIDNode(ID, Opcode, getVTList(VT), 0, 0); 2086 void *IP = 0; 2087 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2088 return SDValue(E, 0); 2089 SDNode *N = NodeAllocator.Allocate<SDNode>(); 2090 new (N) SDNode(Opcode, SDNode::getSDVTList(VT)); 2091 CSEMap.InsertNode(N, IP); 2092 2093 AllNodes.push_back(N); 2094#ifndef NDEBUG 2095 VerifyNode(N); 2096#endif 2097 return SDValue(N, 0); 2098} 2099 2100SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, SDValue Operand) { 2101 // Constant fold unary operations with an integer constant operand. 2102 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Operand.getNode())) { 2103 const APInt &Val = C->getAPIntValue(); 2104 unsigned BitWidth = VT.getSizeInBits(); 2105 switch (Opcode) { 2106 default: break; 2107 case ISD::SIGN_EXTEND: 2108 return getConstant(APInt(Val).sextOrTrunc(BitWidth), VT); 2109 case ISD::ANY_EXTEND: 2110 case ISD::ZERO_EXTEND: 2111 case ISD::TRUNCATE: 2112 return getConstant(APInt(Val).zextOrTrunc(BitWidth), VT); 2113 case ISD::UINT_TO_FP: 2114 case ISD::SINT_TO_FP: { 2115 const uint64_t zero[] = {0, 0}; 2116 // No compile time operations on this type. 2117 if (VT==MVT::ppcf128) 2118 break; 2119 APFloat apf = APFloat(APInt(BitWidth, 2, zero)); 2120 (void)apf.convertFromAPInt(Val, 2121 Opcode==ISD::SINT_TO_FP, 2122 APFloat::rmNearestTiesToEven); 2123 return getConstantFP(apf, VT); 2124 } 2125 case ISD::BIT_CONVERT: 2126 if (VT == MVT::f32 && C->getValueType(0) == MVT::i32) 2127 return getConstantFP(Val.bitsToFloat(), VT); 2128 else if (VT == MVT::f64 && C->getValueType(0) == MVT::i64) 2129 return getConstantFP(Val.bitsToDouble(), VT); 2130 break; 2131 case ISD::BSWAP: 2132 return getConstant(Val.byteSwap(), VT); 2133 case ISD::CTPOP: 2134 return getConstant(Val.countPopulation(), VT); 2135 case ISD::CTLZ: 2136 return getConstant(Val.countLeadingZeros(), VT); 2137 case ISD::CTTZ: 2138 return getConstant(Val.countTrailingZeros(), VT); 2139 } 2140 } 2141 2142 // Constant fold unary operations with a floating point constant operand. 2143 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Operand.getNode())) { 2144 APFloat V = C->getValueAPF(); // make copy 2145 if (VT != MVT::ppcf128 && Operand.getValueType() != MVT::ppcf128) { 2146 switch (Opcode) { 2147 case ISD::FNEG: 2148 V.changeSign(); 2149 return getConstantFP(V, VT); 2150 case ISD::FABS: 2151 V.clearSign(); 2152 return getConstantFP(V, VT); 2153 case ISD::FP_ROUND: 2154 case ISD::FP_EXTEND: { 2155 bool ignored; 2156 // This can return overflow, underflow, or inexact; we don't care. 2157 // FIXME need to be more flexible about rounding mode. 2158 (void)V.convert(*MVTToAPFloatSemantics(VT), 2159 APFloat::rmNearestTiesToEven, &ignored); 2160 return getConstantFP(V, VT); 2161 } 2162 case ISD::FP_TO_SINT: 2163 case ISD::FP_TO_UINT: { 2164 integerPart x; 2165 bool ignored; 2166 assert(integerPartWidth >= 64); 2167 // FIXME need to be more flexible about rounding mode. 2168 APFloat::opStatus s = V.convertToInteger(&x, 64U, 2169 Opcode==ISD::FP_TO_SINT, 2170 APFloat::rmTowardZero, &ignored); 2171 if (s==APFloat::opInvalidOp) // inexact is OK, in fact usual 2172 break; 2173 return getConstant(x, VT); 2174 } 2175 case ISD::BIT_CONVERT: 2176 if (VT == MVT::i32 && C->getValueType(0) == MVT::f32) 2177 return getConstant((uint32_t)V.bitcastToAPInt().getZExtValue(), VT); 2178 else if (VT == MVT::i64 && C->getValueType(0) == MVT::f64) 2179 return getConstant(V.bitcastToAPInt().getZExtValue(), VT); 2180 break; 2181 } 2182 } 2183 } 2184 2185 unsigned OpOpcode = Operand.getNode()->getOpcode(); 2186 switch (Opcode) { 2187 case ISD::TokenFactor: 2188 case ISD::CONCAT_VECTORS: 2189 return Operand; // Factor or concat of one node? No need. 2190 case ISD::FP_ROUND: assert(0 && "Invalid method to make FP_ROUND node"); 2191 case ISD::FP_EXTEND: 2192 assert(VT.isFloatingPoint() && 2193 Operand.getValueType().isFloatingPoint() && "Invalid FP cast!"); 2194 if (Operand.getValueType() == VT) return Operand; // noop conversion. 2195 if (Operand.getOpcode() == ISD::UNDEF) 2196 return getNode(ISD::UNDEF, VT); 2197 break; 2198 case ISD::SIGN_EXTEND: 2199 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2200 "Invalid SIGN_EXTEND!"); 2201 if (Operand.getValueType() == VT) return Operand; // noop extension 2202 assert(Operand.getValueType().bitsLT(VT) 2203 && "Invalid sext node, dst < src!"); 2204 if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND) 2205 return getNode(OpOpcode, VT, Operand.getNode()->getOperand(0)); 2206 break; 2207 case ISD::ZERO_EXTEND: 2208 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2209 "Invalid ZERO_EXTEND!"); 2210 if (Operand.getValueType() == VT) return Operand; // noop extension 2211 assert(Operand.getValueType().bitsLT(VT) 2212 && "Invalid zext node, dst < src!"); 2213 if (OpOpcode == ISD::ZERO_EXTEND) // (zext (zext x)) -> (zext x) 2214 return getNode(ISD::ZERO_EXTEND, VT, Operand.getNode()->getOperand(0)); 2215 break; 2216 case ISD::ANY_EXTEND: 2217 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2218 "Invalid ANY_EXTEND!"); 2219 if (Operand.getValueType() == VT) return Operand; // noop extension 2220 assert(Operand.getValueType().bitsLT(VT) 2221 && "Invalid anyext node, dst < src!"); 2222 if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND) 2223 // (ext (zext x)) -> (zext x) and (ext (sext x)) -> (sext x) 2224 return getNode(OpOpcode, VT, Operand.getNode()->getOperand(0)); 2225 break; 2226 case ISD::TRUNCATE: 2227 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2228 "Invalid TRUNCATE!"); 2229 if (Operand.getValueType() == VT) return Operand; // noop truncate 2230 assert(Operand.getValueType().bitsGT(VT) 2231 && "Invalid truncate node, src < dst!"); 2232 if (OpOpcode == ISD::TRUNCATE) 2233 return getNode(ISD::TRUNCATE, VT, Operand.getNode()->getOperand(0)); 2234 else if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND || 2235 OpOpcode == ISD::ANY_EXTEND) { 2236 // If the source is smaller than the dest, we still need an extend. 2237 if (Operand.getNode()->getOperand(0).getValueType().bitsLT(VT)) 2238 return getNode(OpOpcode, VT, Operand.getNode()->getOperand(0)); 2239 else if (Operand.getNode()->getOperand(0).getValueType().bitsGT(VT)) 2240 return getNode(ISD::TRUNCATE, VT, Operand.getNode()->getOperand(0)); 2241 else 2242 return Operand.getNode()->getOperand(0); 2243 } 2244 break; 2245 case ISD::BIT_CONVERT: 2246 // Basic sanity checking. 2247 assert(VT.getSizeInBits() == Operand.getValueType().getSizeInBits() 2248 && "Cannot BIT_CONVERT between types of different sizes!"); 2249 if (VT == Operand.getValueType()) return Operand; // noop conversion. 2250 if (OpOpcode == ISD::BIT_CONVERT) // bitconv(bitconv(x)) -> bitconv(x) 2251 return getNode(ISD::BIT_CONVERT, VT, Operand.getOperand(0)); 2252 if (OpOpcode == ISD::UNDEF) 2253 return getNode(ISD::UNDEF, VT); 2254 break; 2255 case ISD::SCALAR_TO_VECTOR: 2256 assert(VT.isVector() && !Operand.getValueType().isVector() && 2257 VT.getVectorElementType() == Operand.getValueType() && 2258 "Illegal SCALAR_TO_VECTOR node!"); 2259 if (OpOpcode == ISD::UNDEF) 2260 return getNode(ISD::UNDEF, VT); 2261 // scalar_to_vector(extract_vector_elt V, 0) -> V, top bits are undefined. 2262 if (OpOpcode == ISD::EXTRACT_VECTOR_ELT && 2263 isa<ConstantSDNode>(Operand.getOperand(1)) && 2264 Operand.getConstantOperandVal(1) == 0 && 2265 Operand.getOperand(0).getValueType() == VT) 2266 return Operand.getOperand(0); 2267 break; 2268 case ISD::FNEG: 2269 if (OpOpcode == ISD::FSUB) // -(X-Y) -> (Y-X) 2270 return getNode(ISD::FSUB, VT, Operand.getNode()->getOperand(1), 2271 Operand.getNode()->getOperand(0)); 2272 if (OpOpcode == ISD::FNEG) // --X -> X 2273 return Operand.getNode()->getOperand(0); 2274 break; 2275 case ISD::FABS: 2276 if (OpOpcode == ISD::FNEG) // abs(-X) -> abs(X) 2277 return getNode(ISD::FABS, VT, Operand.getNode()->getOperand(0)); 2278 break; 2279 } 2280 2281 SDNode *N; 2282 SDVTList VTs = getVTList(VT); 2283 if (VT != MVT::Flag) { // Don't CSE flag producing nodes 2284 FoldingSetNodeID ID; 2285 SDValue Ops[1] = { Operand }; 2286 AddNodeIDNode(ID, Opcode, VTs, Ops, 1); 2287 void *IP = 0; 2288 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2289 return SDValue(E, 0); 2290 N = NodeAllocator.Allocate<UnarySDNode>(); 2291 new (N) UnarySDNode(Opcode, VTs, Operand); 2292 CSEMap.InsertNode(N, IP); 2293 } else { 2294 N = NodeAllocator.Allocate<UnarySDNode>(); 2295 new (N) UnarySDNode(Opcode, VTs, Operand); 2296 } 2297 2298 AllNodes.push_back(N); 2299#ifndef NDEBUG 2300 VerifyNode(N); 2301#endif 2302 return SDValue(N, 0); 2303} 2304 2305SDValue SelectionDAG::FoldConstantArithmetic(unsigned Opcode, 2306 MVT VT, 2307 ConstantSDNode *Cst1, 2308 ConstantSDNode *Cst2) { 2309 const APInt &C1 = Cst1->getAPIntValue(), &C2 = Cst2->getAPIntValue(); 2310 2311 switch (Opcode) { 2312 case ISD::ADD: return getConstant(C1 + C2, VT); 2313 case ISD::SUB: return getConstant(C1 - C2, VT); 2314 case ISD::MUL: return getConstant(C1 * C2, VT); 2315 case ISD::UDIV: 2316 if (C2.getBoolValue()) return getConstant(C1.udiv(C2), VT); 2317 break; 2318 case ISD::UREM: 2319 if (C2.getBoolValue()) return getConstant(C1.urem(C2), VT); 2320 break; 2321 case ISD::SDIV: 2322 if (C2.getBoolValue()) return getConstant(C1.sdiv(C2), VT); 2323 break; 2324 case ISD::SREM: 2325 if (C2.getBoolValue()) return getConstant(C1.srem(C2), VT); 2326 break; 2327 case ISD::AND: return getConstant(C1 & C2, VT); 2328 case ISD::OR: return getConstant(C1 | C2, VT); 2329 case ISD::XOR: return getConstant(C1 ^ C2, VT); 2330 case ISD::SHL: return getConstant(C1 << C2, VT); 2331 case ISD::SRL: return getConstant(C1.lshr(C2), VT); 2332 case ISD::SRA: return getConstant(C1.ashr(C2), VT); 2333 case ISD::ROTL: return getConstant(C1.rotl(C2), VT); 2334 case ISD::ROTR: return getConstant(C1.rotr(C2), VT); 2335 default: break; 2336 } 2337 2338 return SDValue(); 2339} 2340 2341SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, 2342 SDValue N1, SDValue N2) { 2343 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 2344 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 2345 switch (Opcode) { 2346 default: break; 2347 case ISD::TokenFactor: 2348 assert(VT == MVT::Other && N1.getValueType() == MVT::Other && 2349 N2.getValueType() == MVT::Other && "Invalid token factor!"); 2350 // Fold trivial token factors. 2351 if (N1.getOpcode() == ISD::EntryToken) return N2; 2352 if (N2.getOpcode() == ISD::EntryToken) return N1; 2353 if (N1 == N2) return N1; 2354 break; 2355 case ISD::CONCAT_VECTORS: 2356 // A CONCAT_VECTOR with all operands BUILD_VECTOR can be simplified to 2357 // one big BUILD_VECTOR. 2358 if (N1.getOpcode() == ISD::BUILD_VECTOR && 2359 N2.getOpcode() == ISD::BUILD_VECTOR) { 2360 SmallVector<SDValue, 16> Elts(N1.getNode()->op_begin(), N1.getNode()->op_end()); 2361 Elts.insert(Elts.end(), N2.getNode()->op_begin(), N2.getNode()->op_end()); 2362 return getNode(ISD::BUILD_VECTOR, VT, &Elts[0], Elts.size()); 2363 } 2364 break; 2365 case ISD::AND: 2366 assert(VT.isInteger() && N1.getValueType() == N2.getValueType() && 2367 N1.getValueType() == VT && "Binary operator types must match!"); 2368 // (X & 0) -> 0. This commonly occurs when legalizing i64 values, so it's 2369 // worth handling here. 2370 if (N2C && N2C->isNullValue()) 2371 return N2; 2372 if (N2C && N2C->isAllOnesValue()) // X & -1 -> X 2373 return N1; 2374 break; 2375 case ISD::OR: 2376 case ISD::XOR: 2377 case ISD::ADD: 2378 case ISD::SUB: 2379 assert(VT.isInteger() && N1.getValueType() == N2.getValueType() && 2380 N1.getValueType() == VT && "Binary operator types must match!"); 2381 // (X ^|+- 0) -> X. This commonly occurs when legalizing i64 values, so 2382 // it's worth handling here. 2383 if (N2C && N2C->isNullValue()) 2384 return N1; 2385 break; 2386 case ISD::UDIV: 2387 case ISD::UREM: 2388 case ISD::MULHU: 2389 case ISD::MULHS: 2390 assert(VT.isInteger() && "This operator does not apply to FP types!"); 2391 // fall through 2392 case ISD::MUL: 2393 case ISD::SDIV: 2394 case ISD::SREM: 2395 case ISD::FADD: 2396 case ISD::FSUB: 2397 case ISD::FMUL: 2398 case ISD::FDIV: 2399 case ISD::FREM: 2400 assert(N1.getValueType() == N2.getValueType() && 2401 N1.getValueType() == VT && "Binary operator types must match!"); 2402 break; 2403 case ISD::FCOPYSIGN: // N1 and result must match. N1/N2 need not match. 2404 assert(N1.getValueType() == VT && 2405 N1.getValueType().isFloatingPoint() && 2406 N2.getValueType().isFloatingPoint() && 2407 "Invalid FCOPYSIGN!"); 2408 break; 2409 case ISD::SHL: 2410 case ISD::SRA: 2411 case ISD::SRL: 2412 case ISD::ROTL: 2413 case ISD::ROTR: 2414 assert(VT == N1.getValueType() && 2415 "Shift operators return type must be the same as their first arg"); 2416 assert(VT.isInteger() && N2.getValueType().isInteger() && 2417 "Shifts only work on integers"); 2418 assert(N2.getValueType() == TLI.getShiftAmountTy() && 2419 "Wrong type for shift amount"); 2420 2421 // Always fold shifts of i1 values so the code generator doesn't need to 2422 // handle them. Since we know the size of the shift has to be less than the 2423 // size of the value, the shift/rotate count is guaranteed to be zero. 2424 if (VT == MVT::i1) 2425 return N1; 2426 break; 2427 case ISD::FP_ROUND_INREG: { 2428 MVT EVT = cast<VTSDNode>(N2)->getVT(); 2429 assert(VT == N1.getValueType() && "Not an inreg round!"); 2430 assert(VT.isFloatingPoint() && EVT.isFloatingPoint() && 2431 "Cannot FP_ROUND_INREG integer types"); 2432 assert(EVT.bitsLE(VT) && "Not rounding down!"); 2433 if (cast<VTSDNode>(N2)->getVT() == VT) return N1; // Not actually rounding. 2434 break; 2435 } 2436 case ISD::FP_ROUND: 2437 assert(VT.isFloatingPoint() && 2438 N1.getValueType().isFloatingPoint() && 2439 VT.bitsLE(N1.getValueType()) && 2440 isa<ConstantSDNode>(N2) && "Invalid FP_ROUND!"); 2441 if (N1.getValueType() == VT) return N1; // noop conversion. 2442 break; 2443 case ISD::AssertSext: 2444 case ISD::AssertZext: { 2445 MVT EVT = cast<VTSDNode>(N2)->getVT(); 2446 assert(VT == N1.getValueType() && "Not an inreg extend!"); 2447 assert(VT.isInteger() && EVT.isInteger() && 2448 "Cannot *_EXTEND_INREG FP types"); 2449 assert(EVT.bitsLE(VT) && "Not extending!"); 2450 if (VT == EVT) return N1; // noop assertion. 2451 break; 2452 } 2453 case ISD::SIGN_EXTEND_INREG: { 2454 MVT EVT = cast<VTSDNode>(N2)->getVT(); 2455 assert(VT == N1.getValueType() && "Not an inreg extend!"); 2456 assert(VT.isInteger() && EVT.isInteger() && 2457 "Cannot *_EXTEND_INREG FP types"); 2458 assert(EVT.bitsLE(VT) && "Not extending!"); 2459 if (EVT == VT) return N1; // Not actually extending 2460 2461 if (N1C) { 2462 APInt Val = N1C->getAPIntValue(); 2463 unsigned FromBits = cast<VTSDNode>(N2)->getVT().getSizeInBits(); 2464 Val <<= Val.getBitWidth()-FromBits; 2465 Val = Val.ashr(Val.getBitWidth()-FromBits); 2466 return getConstant(Val, VT); 2467 } 2468 break; 2469 } 2470 case ISD::EXTRACT_VECTOR_ELT: 2471 // EXTRACT_VECTOR_ELT of an UNDEF is an UNDEF. 2472 if (N1.getOpcode() == ISD::UNDEF) 2473 return getNode(ISD::UNDEF, VT); 2474 2475 // EXTRACT_VECTOR_ELT of CONCAT_VECTORS is often formed while lowering is 2476 // expanding copies of large vectors from registers. 2477 if (N2C && 2478 N1.getOpcode() == ISD::CONCAT_VECTORS && 2479 N1.getNumOperands() > 0) { 2480 unsigned Factor = 2481 N1.getOperand(0).getValueType().getVectorNumElements(); 2482 return getNode(ISD::EXTRACT_VECTOR_ELT, VT, 2483 N1.getOperand(N2C->getZExtValue() / Factor), 2484 getConstant(N2C->getZExtValue() % Factor, 2485 N2.getValueType())); 2486 } 2487 2488 // EXTRACT_VECTOR_ELT of BUILD_VECTOR is often formed while lowering is 2489 // expanding large vector constants. 2490 if (N2C && N1.getOpcode() == ISD::BUILD_VECTOR) 2491 return N1.getOperand(N2C->getZExtValue()); 2492 2493 // EXTRACT_VECTOR_ELT of INSERT_VECTOR_ELT is often formed when vector 2494 // operations are lowered to scalars. 2495 if (N1.getOpcode() == ISD::INSERT_VECTOR_ELT) { 2496 if (N1.getOperand(2) == N2) 2497 return N1.getOperand(1); 2498 else 2499 return getNode(ISD::EXTRACT_VECTOR_ELT, VT, N1.getOperand(0), N2); 2500 } 2501 break; 2502 case ISD::EXTRACT_ELEMENT: 2503 assert(N2C && (unsigned)N2C->getZExtValue() < 2 && "Bad EXTRACT_ELEMENT!"); 2504 assert(!N1.getValueType().isVector() && !VT.isVector() && 2505 (N1.getValueType().isInteger() == VT.isInteger()) && 2506 "Wrong types for EXTRACT_ELEMENT!"); 2507 2508 // EXTRACT_ELEMENT of BUILD_PAIR is often formed while legalize is expanding 2509 // 64-bit integers into 32-bit parts. Instead of building the extract of 2510 // the BUILD_PAIR, only to have legalize rip it apart, just do it now. 2511 if (N1.getOpcode() == ISD::BUILD_PAIR) 2512 return N1.getOperand(N2C->getZExtValue()); 2513 2514 // EXTRACT_ELEMENT of a constant int is also very common. 2515 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) { 2516 unsigned ElementSize = VT.getSizeInBits(); 2517 unsigned Shift = ElementSize * N2C->getZExtValue(); 2518 APInt ShiftedVal = C->getAPIntValue().lshr(Shift); 2519 return getConstant(ShiftedVal.trunc(ElementSize), VT); 2520 } 2521 break; 2522 case ISD::EXTRACT_SUBVECTOR: 2523 if (N1.getValueType() == VT) // Trivial extraction. 2524 return N1; 2525 break; 2526 } 2527 2528 if (N1C) { 2529 if (N2C) { 2530 SDValue SV = FoldConstantArithmetic(Opcode, VT, N1C, N2C); 2531 if (SV.getNode()) return SV; 2532 } else { // Cannonicalize constant to RHS if commutative 2533 if (isCommutativeBinOp(Opcode)) { 2534 std::swap(N1C, N2C); 2535 std::swap(N1, N2); 2536 } 2537 } 2538 } 2539 2540 // Constant fold FP operations. 2541 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1.getNode()); 2542 ConstantFPSDNode *N2CFP = dyn_cast<ConstantFPSDNode>(N2.getNode()); 2543 if (N1CFP) { 2544 if (!N2CFP && isCommutativeBinOp(Opcode)) { 2545 // Cannonicalize constant to RHS if commutative 2546 std::swap(N1CFP, N2CFP); 2547 std::swap(N1, N2); 2548 } else if (N2CFP && VT != MVT::ppcf128) { 2549 APFloat V1 = N1CFP->getValueAPF(), V2 = N2CFP->getValueAPF(); 2550 APFloat::opStatus s; 2551 switch (Opcode) { 2552 case ISD::FADD: 2553 s = V1.add(V2, APFloat::rmNearestTiesToEven); 2554 if (s != APFloat::opInvalidOp) 2555 return getConstantFP(V1, VT); 2556 break; 2557 case ISD::FSUB: 2558 s = V1.subtract(V2, APFloat::rmNearestTiesToEven); 2559 if (s!=APFloat::opInvalidOp) 2560 return getConstantFP(V1, VT); 2561 break; 2562 case ISD::FMUL: 2563 s = V1.multiply(V2, APFloat::rmNearestTiesToEven); 2564 if (s!=APFloat::opInvalidOp) 2565 return getConstantFP(V1, VT); 2566 break; 2567 case ISD::FDIV: 2568 s = V1.divide(V2, APFloat::rmNearestTiesToEven); 2569 if (s!=APFloat::opInvalidOp && s!=APFloat::opDivByZero) 2570 return getConstantFP(V1, VT); 2571 break; 2572 case ISD::FREM : 2573 s = V1.mod(V2, APFloat::rmNearestTiesToEven); 2574 if (s!=APFloat::opInvalidOp && s!=APFloat::opDivByZero) 2575 return getConstantFP(V1, VT); 2576 break; 2577 case ISD::FCOPYSIGN: 2578 V1.copySign(V2); 2579 return getConstantFP(V1, VT); 2580 default: break; 2581 } 2582 } 2583 } 2584 2585 // Canonicalize an UNDEF to the RHS, even over a constant. 2586 if (N1.getOpcode() == ISD::UNDEF) { 2587 if (isCommutativeBinOp(Opcode)) { 2588 std::swap(N1, N2); 2589 } else { 2590 switch (Opcode) { 2591 case ISD::FP_ROUND_INREG: 2592 case ISD::SIGN_EXTEND_INREG: 2593 case ISD::SUB: 2594 case ISD::FSUB: 2595 case ISD::FDIV: 2596 case ISD::FREM: 2597 case ISD::SRA: 2598 return N1; // fold op(undef, arg2) -> undef 2599 case ISD::UDIV: 2600 case ISD::SDIV: 2601 case ISD::UREM: 2602 case ISD::SREM: 2603 case ISD::SRL: 2604 case ISD::SHL: 2605 if (!VT.isVector()) 2606 return getConstant(0, VT); // fold op(undef, arg2) -> 0 2607 // For vectors, we can't easily build an all zero vector, just return 2608 // the LHS. 2609 return N2; 2610 } 2611 } 2612 } 2613 2614 // Fold a bunch of operators when the RHS is undef. 2615 if (N2.getOpcode() == ISD::UNDEF) { 2616 switch (Opcode) { 2617 case ISD::XOR: 2618 if (N1.getOpcode() == ISD::UNDEF) 2619 // Handle undef ^ undef -> 0 special case. This is a common 2620 // idiom (misuse). 2621 return getConstant(0, VT); 2622 // fallthrough 2623 case ISD::ADD: 2624 case ISD::ADDC: 2625 case ISD::ADDE: 2626 case ISD::SUB: 2627 case ISD::FADD: 2628 case ISD::FSUB: 2629 case ISD::FMUL: 2630 case ISD::FDIV: 2631 case ISD::FREM: 2632 case ISD::UDIV: 2633 case ISD::SDIV: 2634 case ISD::UREM: 2635 case ISD::SREM: 2636 return N2; // fold op(arg1, undef) -> undef 2637 case ISD::MUL: 2638 case ISD::AND: 2639 case ISD::SRL: 2640 case ISD::SHL: 2641 if (!VT.isVector()) 2642 return getConstant(0, VT); // fold op(arg1, undef) -> 0 2643 // For vectors, we can't easily build an all zero vector, just return 2644 // the LHS. 2645 return N1; 2646 case ISD::OR: 2647 if (!VT.isVector()) 2648 return getConstant(VT.getIntegerVTBitMask(), VT); 2649 // For vectors, we can't easily build an all one vector, just return 2650 // the LHS. 2651 return N1; 2652 case ISD::SRA: 2653 return N1; 2654 } 2655 } 2656 2657 // Memoize this node if possible. 2658 SDNode *N; 2659 SDVTList VTs = getVTList(VT); 2660 if (VT != MVT::Flag) { 2661 SDValue Ops[] = { N1, N2 }; 2662 FoldingSetNodeID ID; 2663 AddNodeIDNode(ID, Opcode, VTs, Ops, 2); 2664 void *IP = 0; 2665 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2666 return SDValue(E, 0); 2667 N = NodeAllocator.Allocate<BinarySDNode>(); 2668 new (N) BinarySDNode(Opcode, VTs, N1, N2); 2669 CSEMap.InsertNode(N, IP); 2670 } else { 2671 N = NodeAllocator.Allocate<BinarySDNode>(); 2672 new (N) BinarySDNode(Opcode, VTs, N1, N2); 2673 } 2674 2675 AllNodes.push_back(N); 2676#ifndef NDEBUG 2677 VerifyNode(N); 2678#endif 2679 return SDValue(N, 0); 2680} 2681 2682SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, 2683 SDValue N1, SDValue N2, SDValue N3) { 2684 // Perform various simplifications. 2685 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 2686 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 2687 switch (Opcode) { 2688 case ISD::CONCAT_VECTORS: 2689 // A CONCAT_VECTOR with all operands BUILD_VECTOR can be simplified to 2690 // one big BUILD_VECTOR. 2691 if (N1.getOpcode() == ISD::BUILD_VECTOR && 2692 N2.getOpcode() == ISD::BUILD_VECTOR && 2693 N3.getOpcode() == ISD::BUILD_VECTOR) { 2694 SmallVector<SDValue, 16> Elts(N1.getNode()->op_begin(), N1.getNode()->op_end()); 2695 Elts.insert(Elts.end(), N2.getNode()->op_begin(), N2.getNode()->op_end()); 2696 Elts.insert(Elts.end(), N3.getNode()->op_begin(), N3.getNode()->op_end()); 2697 return getNode(ISD::BUILD_VECTOR, VT, &Elts[0], Elts.size()); 2698 } 2699 break; 2700 case ISD::SETCC: { 2701 // Use FoldSetCC to simplify SETCC's. 2702 SDValue Simp = FoldSetCC(VT, N1, N2, cast<CondCodeSDNode>(N3)->get()); 2703 if (Simp.getNode()) return Simp; 2704 break; 2705 } 2706 case ISD::SELECT: 2707 if (N1C) { 2708 if (N1C->getZExtValue()) 2709 return N2; // select true, X, Y -> X 2710 else 2711 return N3; // select false, X, Y -> Y 2712 } 2713 2714 if (N2 == N3) return N2; // select C, X, X -> X 2715 break; 2716 case ISD::BRCOND: 2717 if (N2C) { 2718 if (N2C->getZExtValue()) // Unconditional branch 2719 return getNode(ISD::BR, MVT::Other, N1, N3); 2720 else 2721 return N1; // Never-taken branch 2722 } 2723 break; 2724 case ISD::VECTOR_SHUFFLE: 2725 assert(N1.getValueType() == N2.getValueType() && 2726 N1.getValueType().isVector() && 2727 VT.isVector() && N3.getValueType().isVector() && 2728 N3.getOpcode() == ISD::BUILD_VECTOR && 2729 VT.getVectorNumElements() == N3.getNumOperands() && 2730 "Illegal VECTOR_SHUFFLE node!"); 2731 break; 2732 case ISD::BIT_CONVERT: 2733 // Fold bit_convert nodes from a type to themselves. 2734 if (N1.getValueType() == VT) 2735 return N1; 2736 break; 2737 } 2738 2739 // Memoize node if it doesn't produce a flag. 2740 SDNode *N; 2741 SDVTList VTs = getVTList(VT); 2742 if (VT != MVT::Flag) { 2743 SDValue Ops[] = { N1, N2, N3 }; 2744 FoldingSetNodeID ID; 2745 AddNodeIDNode(ID, Opcode, VTs, Ops, 3); 2746 void *IP = 0; 2747 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2748 return SDValue(E, 0); 2749 N = NodeAllocator.Allocate<TernarySDNode>(); 2750 new (N) TernarySDNode(Opcode, VTs, N1, N2, N3); 2751 CSEMap.InsertNode(N, IP); 2752 } else { 2753 N = NodeAllocator.Allocate<TernarySDNode>(); 2754 new (N) TernarySDNode(Opcode, VTs, N1, N2, N3); 2755 } 2756 AllNodes.push_back(N); 2757#ifndef NDEBUG 2758 VerifyNode(N); 2759#endif 2760 return SDValue(N, 0); 2761} 2762 2763SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, 2764 SDValue N1, SDValue N2, SDValue N3, 2765 SDValue N4) { 2766 SDValue Ops[] = { N1, N2, N3, N4 }; 2767 return getNode(Opcode, VT, Ops, 4); 2768} 2769 2770SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, 2771 SDValue N1, SDValue N2, SDValue N3, 2772 SDValue N4, SDValue N5) { 2773 SDValue Ops[] = { N1, N2, N3, N4, N5 }; 2774 return getNode(Opcode, VT, Ops, 5); 2775} 2776 2777/// getMemsetValue - Vectorized representation of the memset value 2778/// operand. 2779static SDValue getMemsetValue(SDValue Value, MVT VT, SelectionDAG &DAG) { 2780 unsigned NumBits = VT.isVector() ? 2781 VT.getVectorElementType().getSizeInBits() : VT.getSizeInBits(); 2782 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) { 2783 APInt Val = APInt(NumBits, C->getZExtValue() & 255); 2784 unsigned Shift = 8; 2785 for (unsigned i = NumBits; i > 8; i >>= 1) { 2786 Val = (Val << Shift) | Val; 2787 Shift <<= 1; 2788 } 2789 if (VT.isInteger()) 2790 return DAG.getConstant(Val, VT); 2791 return DAG.getConstantFP(APFloat(Val), VT); 2792 } 2793 2794 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 2795 Value = DAG.getNode(ISD::ZERO_EXTEND, VT, Value); 2796 unsigned Shift = 8; 2797 for (unsigned i = NumBits; i > 8; i >>= 1) { 2798 Value = DAG.getNode(ISD::OR, VT, 2799 DAG.getNode(ISD::SHL, VT, Value, 2800 DAG.getConstant(Shift, 2801 TLI.getShiftAmountTy())), 2802 Value); 2803 Shift <<= 1; 2804 } 2805 2806 return Value; 2807} 2808 2809/// getMemsetStringVal - Similar to getMemsetValue. Except this is only 2810/// used when a memcpy is turned into a memset when the source is a constant 2811/// string ptr. 2812static SDValue getMemsetStringVal(MVT VT, SelectionDAG &DAG, 2813 const TargetLowering &TLI, 2814 std::string &Str, unsigned Offset) { 2815 // Handle vector with all elements zero. 2816 if (Str.empty()) { 2817 if (VT.isInteger()) 2818 return DAG.getConstant(0, VT); 2819 unsigned NumElts = VT.getVectorNumElements(); 2820 MVT EltVT = (VT.getVectorElementType() == MVT::f32) ? MVT::i32 : MVT::i64; 2821 return DAG.getNode(ISD::BIT_CONVERT, VT, 2822 DAG.getConstant(0, MVT::getVectorVT(EltVT, NumElts))); 2823 } 2824 2825 assert(!VT.isVector() && "Can't handle vector type here!"); 2826 unsigned NumBits = VT.getSizeInBits(); 2827 unsigned MSB = NumBits / 8; 2828 uint64_t Val = 0; 2829 if (TLI.isLittleEndian()) 2830 Offset = Offset + MSB - 1; 2831 for (unsigned i = 0; i != MSB; ++i) { 2832 Val = (Val << 8) | (unsigned char)Str[Offset]; 2833 Offset += TLI.isLittleEndian() ? -1 : 1; 2834 } 2835 return DAG.getConstant(Val, VT); 2836} 2837 2838/// getMemBasePlusOffset - Returns base and offset node for the 2839/// 2840static SDValue getMemBasePlusOffset(SDValue Base, unsigned Offset, 2841 SelectionDAG &DAG) { 2842 MVT VT = Base.getValueType(); 2843 return DAG.getNode(ISD::ADD, VT, Base, DAG.getConstant(Offset, VT)); 2844} 2845 2846/// isMemSrcFromString - Returns true if memcpy source is a string constant. 2847/// 2848static bool isMemSrcFromString(SDValue Src, std::string &Str) { 2849 unsigned SrcDelta = 0; 2850 GlobalAddressSDNode *G = NULL; 2851 if (Src.getOpcode() == ISD::GlobalAddress) 2852 G = cast<GlobalAddressSDNode>(Src); 2853 else if (Src.getOpcode() == ISD::ADD && 2854 Src.getOperand(0).getOpcode() == ISD::GlobalAddress && 2855 Src.getOperand(1).getOpcode() == ISD::Constant) { 2856 G = cast<GlobalAddressSDNode>(Src.getOperand(0)); 2857 SrcDelta = cast<ConstantSDNode>(Src.getOperand(1))->getZExtValue(); 2858 } 2859 if (!G) 2860 return false; 2861 2862 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal()); 2863 if (GV && GetConstantStringInfo(GV, Str, SrcDelta, false)) 2864 return true; 2865 2866 return false; 2867} 2868 2869/// MeetsMaxMemopRequirement - Determines if the number of memory ops required 2870/// to replace the memset / memcpy is below the threshold. It also returns the 2871/// types of the sequence of memory ops to perform memset / memcpy. 2872static 2873bool MeetsMaxMemopRequirement(std::vector<MVT> &MemOps, 2874 SDValue Dst, SDValue Src, 2875 unsigned Limit, uint64_t Size, unsigned &Align, 2876 std::string &Str, bool &isSrcStr, 2877 SelectionDAG &DAG, 2878 const TargetLowering &TLI) { 2879 isSrcStr = isMemSrcFromString(Src, Str); 2880 bool isSrcConst = isa<ConstantSDNode>(Src); 2881 bool AllowUnalign = TLI.allowsUnalignedMemoryAccesses(); 2882 MVT VT = TLI.getOptimalMemOpType(Size, Align, isSrcConst, isSrcStr); 2883 if (VT != MVT::iAny) { 2884 unsigned NewAlign = (unsigned) 2885 TLI.getTargetData()->getABITypeAlignment(VT.getTypeForMVT()); 2886 // If source is a string constant, this will require an unaligned load. 2887 if (NewAlign > Align && (isSrcConst || AllowUnalign)) { 2888 if (Dst.getOpcode() != ISD::FrameIndex) { 2889 // Can't change destination alignment. It requires a unaligned store. 2890 if (AllowUnalign) 2891 VT = MVT::iAny; 2892 } else { 2893 int FI = cast<FrameIndexSDNode>(Dst)->getIndex(); 2894 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 2895 if (MFI->isFixedObjectIndex(FI)) { 2896 // Can't change destination alignment. It requires a unaligned store. 2897 if (AllowUnalign) 2898 VT = MVT::iAny; 2899 } else { 2900 // Give the stack frame object a larger alignment if needed. 2901 if (MFI->getObjectAlignment(FI) < NewAlign) 2902 MFI->setObjectAlignment(FI, NewAlign); 2903 Align = NewAlign; 2904 } 2905 } 2906 } 2907 } 2908 2909 if (VT == MVT::iAny) { 2910 if (AllowUnalign) { 2911 VT = MVT::i64; 2912 } else { 2913 switch (Align & 7) { 2914 case 0: VT = MVT::i64; break; 2915 case 4: VT = MVT::i32; break; 2916 case 2: VT = MVT::i16; break; 2917 default: VT = MVT::i8; break; 2918 } 2919 } 2920 2921 MVT LVT = MVT::i64; 2922 while (!TLI.isTypeLegal(LVT)) 2923 LVT = (MVT::SimpleValueType)(LVT.getSimpleVT() - 1); 2924 assert(LVT.isInteger()); 2925 2926 if (VT.bitsGT(LVT)) 2927 VT = LVT; 2928 } 2929 2930 unsigned NumMemOps = 0; 2931 while (Size != 0) { 2932 unsigned VTSize = VT.getSizeInBits() / 8; 2933 while (VTSize > Size) { 2934 // For now, only use non-vector load / store's for the left-over pieces. 2935 if (VT.isVector()) { 2936 VT = MVT::i64; 2937 while (!TLI.isTypeLegal(VT)) 2938 VT = (MVT::SimpleValueType)(VT.getSimpleVT() - 1); 2939 VTSize = VT.getSizeInBits() / 8; 2940 } else { 2941 VT = (MVT::SimpleValueType)(VT.getSimpleVT() - 1); 2942 VTSize >>= 1; 2943 } 2944 } 2945 2946 if (++NumMemOps > Limit) 2947 return false; 2948 MemOps.push_back(VT); 2949 Size -= VTSize; 2950 } 2951 2952 return true; 2953} 2954 2955static SDValue getMemcpyLoadsAndStores(SelectionDAG &DAG, 2956 SDValue Chain, SDValue Dst, 2957 SDValue Src, uint64_t Size, 2958 unsigned Align, bool AlwaysInline, 2959 const Value *DstSV, uint64_t DstSVOff, 2960 const Value *SrcSV, uint64_t SrcSVOff){ 2961 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 2962 2963 // Expand memcpy to a series of load and store ops if the size operand falls 2964 // below a certain threshold. 2965 std::vector<MVT> MemOps; 2966 uint64_t Limit = -1ULL; 2967 if (!AlwaysInline) 2968 Limit = TLI.getMaxStoresPerMemcpy(); 2969 unsigned DstAlign = Align; // Destination alignment can change. 2970 std::string Str; 2971 bool CopyFromStr; 2972 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, Limit, Size, DstAlign, 2973 Str, CopyFromStr, DAG, TLI)) 2974 return SDValue(); 2975 2976 2977 bool isZeroStr = CopyFromStr && Str.empty(); 2978 SmallVector<SDValue, 8> OutChains; 2979 unsigned NumMemOps = MemOps.size(); 2980 uint64_t SrcOff = 0, DstOff = 0; 2981 for (unsigned i = 0; i < NumMemOps; i++) { 2982 MVT VT = MemOps[i]; 2983 unsigned VTSize = VT.getSizeInBits() / 8; 2984 SDValue Value, Store; 2985 2986 if (CopyFromStr && (isZeroStr || !VT.isVector())) { 2987 // It's unlikely a store of a vector immediate can be done in a single 2988 // instruction. It would require a load from a constantpool first. 2989 // We also handle store a vector with all zero's. 2990 // FIXME: Handle other cases where store of vector immediate is done in 2991 // a single instruction. 2992 Value = getMemsetStringVal(VT, DAG, TLI, Str, SrcOff); 2993 Store = DAG.getStore(Chain, Value, 2994 getMemBasePlusOffset(Dst, DstOff, DAG), 2995 DstSV, DstSVOff + DstOff, false, DstAlign); 2996 } else { 2997 Value = DAG.getLoad(VT, Chain, 2998 getMemBasePlusOffset(Src, SrcOff, DAG), 2999 SrcSV, SrcSVOff + SrcOff, false, Align); 3000 Store = DAG.getStore(Chain, Value, 3001 getMemBasePlusOffset(Dst, DstOff, DAG), 3002 DstSV, DstSVOff + DstOff, false, DstAlign); 3003 } 3004 OutChains.push_back(Store); 3005 SrcOff += VTSize; 3006 DstOff += VTSize; 3007 } 3008 3009 return DAG.getNode(ISD::TokenFactor, MVT::Other, 3010 &OutChains[0], OutChains.size()); 3011} 3012 3013static SDValue getMemmoveLoadsAndStores(SelectionDAG &DAG, 3014 SDValue Chain, SDValue Dst, 3015 SDValue Src, uint64_t Size, 3016 unsigned Align, bool AlwaysInline, 3017 const Value *DstSV, uint64_t DstSVOff, 3018 const Value *SrcSV, uint64_t SrcSVOff){ 3019 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 3020 3021 // Expand memmove to a series of load and store ops if the size operand falls 3022 // below a certain threshold. 3023 std::vector<MVT> MemOps; 3024 uint64_t Limit = -1ULL; 3025 if (!AlwaysInline) 3026 Limit = TLI.getMaxStoresPerMemmove(); 3027 unsigned DstAlign = Align; // Destination alignment can change. 3028 std::string Str; 3029 bool CopyFromStr; 3030 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, Limit, Size, DstAlign, 3031 Str, CopyFromStr, DAG, TLI)) 3032 return SDValue(); 3033 3034 uint64_t SrcOff = 0, DstOff = 0; 3035 3036 SmallVector<SDValue, 8> LoadValues; 3037 SmallVector<SDValue, 8> LoadChains; 3038 SmallVector<SDValue, 8> OutChains; 3039 unsigned NumMemOps = MemOps.size(); 3040 for (unsigned i = 0; i < NumMemOps; i++) { 3041 MVT VT = MemOps[i]; 3042 unsigned VTSize = VT.getSizeInBits() / 8; 3043 SDValue Value, Store; 3044 3045 Value = DAG.getLoad(VT, Chain, 3046 getMemBasePlusOffset(Src, SrcOff, DAG), 3047 SrcSV, SrcSVOff + SrcOff, false, Align); 3048 LoadValues.push_back(Value); 3049 LoadChains.push_back(Value.getValue(1)); 3050 SrcOff += VTSize; 3051 } 3052 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 3053 &LoadChains[0], LoadChains.size()); 3054 OutChains.clear(); 3055 for (unsigned i = 0; i < NumMemOps; i++) { 3056 MVT VT = MemOps[i]; 3057 unsigned VTSize = VT.getSizeInBits() / 8; 3058 SDValue Value, Store; 3059 3060 Store = DAG.getStore(Chain, LoadValues[i], 3061 getMemBasePlusOffset(Dst, DstOff, DAG), 3062 DstSV, DstSVOff + DstOff, false, DstAlign); 3063 OutChains.push_back(Store); 3064 DstOff += VTSize; 3065 } 3066 3067 return DAG.getNode(ISD::TokenFactor, MVT::Other, 3068 &OutChains[0], OutChains.size()); 3069} 3070 3071static SDValue getMemsetStores(SelectionDAG &DAG, 3072 SDValue Chain, SDValue Dst, 3073 SDValue Src, uint64_t Size, 3074 unsigned Align, 3075 const Value *DstSV, uint64_t DstSVOff) { 3076 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 3077 3078 // Expand memset to a series of load/store ops if the size operand 3079 // falls below a certain threshold. 3080 std::vector<MVT> MemOps; 3081 std::string Str; 3082 bool CopyFromStr; 3083 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, TLI.getMaxStoresPerMemset(), 3084 Size, Align, Str, CopyFromStr, DAG, TLI)) 3085 return SDValue(); 3086 3087 SmallVector<SDValue, 8> OutChains; 3088 uint64_t DstOff = 0; 3089 3090 unsigned NumMemOps = MemOps.size(); 3091 for (unsigned i = 0; i < NumMemOps; i++) { 3092 MVT VT = MemOps[i]; 3093 unsigned VTSize = VT.getSizeInBits() / 8; 3094 SDValue Value = getMemsetValue(Src, VT, DAG); 3095 SDValue Store = DAG.getStore(Chain, Value, 3096 getMemBasePlusOffset(Dst, DstOff, DAG), 3097 DstSV, DstSVOff + DstOff); 3098 OutChains.push_back(Store); 3099 DstOff += VTSize; 3100 } 3101 3102 return DAG.getNode(ISD::TokenFactor, MVT::Other, 3103 &OutChains[0], OutChains.size()); 3104} 3105 3106SDValue SelectionDAG::getMemcpy(SDValue Chain, SDValue Dst, 3107 SDValue Src, SDValue Size, 3108 unsigned Align, bool AlwaysInline, 3109 const Value *DstSV, uint64_t DstSVOff, 3110 const Value *SrcSV, uint64_t SrcSVOff) { 3111 3112 // Check to see if we should lower the memcpy to loads and stores first. 3113 // For cases within the target-specified limits, this is the best choice. 3114 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 3115 if (ConstantSize) { 3116 // Memcpy with size zero? Just return the original chain. 3117 if (ConstantSize->isNullValue()) 3118 return Chain; 3119 3120 SDValue Result = 3121 getMemcpyLoadsAndStores(*this, Chain, Dst, Src, 3122 ConstantSize->getZExtValue(), 3123 Align, false, DstSV, DstSVOff, SrcSV, SrcSVOff); 3124 if (Result.getNode()) 3125 return Result; 3126 } 3127 3128 // Then check to see if we should lower the memcpy with target-specific 3129 // code. If the target chooses to do this, this is the next best. 3130 SDValue Result = 3131 TLI.EmitTargetCodeForMemcpy(*this, Chain, Dst, Src, Size, Align, 3132 AlwaysInline, 3133 DstSV, DstSVOff, SrcSV, SrcSVOff); 3134 if (Result.getNode()) 3135 return Result; 3136 3137 // If we really need inline code and the target declined to provide it, 3138 // use a (potentially long) sequence of loads and stores. 3139 if (AlwaysInline) { 3140 assert(ConstantSize && "AlwaysInline requires a constant size!"); 3141 return getMemcpyLoadsAndStores(*this, Chain, Dst, Src, 3142 ConstantSize->getZExtValue(), Align, true, 3143 DstSV, DstSVOff, SrcSV, SrcSVOff); 3144 } 3145 3146 // Emit a library call. 3147 TargetLowering::ArgListTy Args; 3148 TargetLowering::ArgListEntry Entry; 3149 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 3150 Entry.Node = Dst; Args.push_back(Entry); 3151 Entry.Node = Src; Args.push_back(Entry); 3152 Entry.Node = Size; Args.push_back(Entry); 3153 std::pair<SDValue,SDValue> CallResult = 3154 TLI.LowerCallTo(Chain, Type::VoidTy, 3155 false, false, false, false, CallingConv::C, false, 3156 getExternalSymbol("memcpy", TLI.getPointerTy()), 3157 Args, *this); 3158 return CallResult.second; 3159} 3160 3161SDValue SelectionDAG::getMemmove(SDValue Chain, SDValue Dst, 3162 SDValue Src, SDValue Size, 3163 unsigned Align, 3164 const Value *DstSV, uint64_t DstSVOff, 3165 const Value *SrcSV, uint64_t SrcSVOff) { 3166 3167 // Check to see if we should lower the memmove to loads and stores first. 3168 // For cases within the target-specified limits, this is the best choice. 3169 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 3170 if (ConstantSize) { 3171 // Memmove with size zero? Just return the original chain. 3172 if (ConstantSize->isNullValue()) 3173 return Chain; 3174 3175 SDValue Result = 3176 getMemmoveLoadsAndStores(*this, Chain, Dst, Src, 3177 ConstantSize->getZExtValue(), 3178 Align, false, DstSV, DstSVOff, SrcSV, SrcSVOff); 3179 if (Result.getNode()) 3180 return Result; 3181 } 3182 3183 // Then check to see if we should lower the memmove with target-specific 3184 // code. If the target chooses to do this, this is the next best. 3185 SDValue Result = 3186 TLI.EmitTargetCodeForMemmove(*this, Chain, Dst, Src, Size, Align, 3187 DstSV, DstSVOff, SrcSV, SrcSVOff); 3188 if (Result.getNode()) 3189 return Result; 3190 3191 // Emit a library call. 3192 TargetLowering::ArgListTy Args; 3193 TargetLowering::ArgListEntry Entry; 3194 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 3195 Entry.Node = Dst; Args.push_back(Entry); 3196 Entry.Node = Src; Args.push_back(Entry); 3197 Entry.Node = Size; Args.push_back(Entry); 3198 std::pair<SDValue,SDValue> CallResult = 3199 TLI.LowerCallTo(Chain, Type::VoidTy, 3200 false, false, false, false, CallingConv::C, false, 3201 getExternalSymbol("memmove", TLI.getPointerTy()), 3202 Args, *this); 3203 return CallResult.second; 3204} 3205 3206SDValue SelectionDAG::getMemset(SDValue Chain, SDValue Dst, 3207 SDValue Src, SDValue Size, 3208 unsigned Align, 3209 const Value *DstSV, uint64_t DstSVOff) { 3210 3211 // Check to see if we should lower the memset to stores first. 3212 // For cases within the target-specified limits, this is the best choice. 3213 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 3214 if (ConstantSize) { 3215 // Memset with size zero? Just return the original chain. 3216 if (ConstantSize->isNullValue()) 3217 return Chain; 3218 3219 SDValue Result = 3220 getMemsetStores(*this, Chain, Dst, Src, ConstantSize->getZExtValue(), 3221 Align, DstSV, DstSVOff); 3222 if (Result.getNode()) 3223 return Result; 3224 } 3225 3226 // Then check to see if we should lower the memset with target-specific 3227 // code. If the target chooses to do this, this is the next best. 3228 SDValue Result = 3229 TLI.EmitTargetCodeForMemset(*this, Chain, Dst, Src, Size, Align, 3230 DstSV, DstSVOff); 3231 if (Result.getNode()) 3232 return Result; 3233 3234 // Emit a library call. 3235 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType(); 3236 TargetLowering::ArgListTy Args; 3237 TargetLowering::ArgListEntry Entry; 3238 Entry.Node = Dst; Entry.Ty = IntPtrTy; 3239 Args.push_back(Entry); 3240 // Extend or truncate the argument to be an i32 value for the call. 3241 if (Src.getValueType().bitsGT(MVT::i32)) 3242 Src = getNode(ISD::TRUNCATE, MVT::i32, Src); 3243 else 3244 Src = getNode(ISD::ZERO_EXTEND, MVT::i32, Src); 3245 Entry.Node = Src; Entry.Ty = Type::Int32Ty; Entry.isSExt = true; 3246 Args.push_back(Entry); 3247 Entry.Node = Size; Entry.Ty = IntPtrTy; Entry.isSExt = false; 3248 Args.push_back(Entry); 3249 std::pair<SDValue,SDValue> CallResult = 3250 TLI.LowerCallTo(Chain, Type::VoidTy, 3251 false, false, false, false, CallingConv::C, false, 3252 getExternalSymbol("memset", TLI.getPointerTy()), 3253 Args, *this); 3254 return CallResult.second; 3255} 3256 3257SDValue SelectionDAG::getAtomic(unsigned Opcode, SDValue Chain, 3258 SDValue Ptr, SDValue Cmp, 3259 SDValue Swp, const Value* PtrVal, 3260 unsigned Alignment) { 3261 assert((Opcode == ISD::ATOMIC_CMP_SWAP_8 || 3262 Opcode == ISD::ATOMIC_CMP_SWAP_16 || 3263 Opcode == ISD::ATOMIC_CMP_SWAP_32 || 3264 Opcode == ISD::ATOMIC_CMP_SWAP_64) && "Invalid Atomic Op"); 3265 assert(Cmp.getValueType() == Swp.getValueType() && "Invalid Atomic Op Types"); 3266 3267 MVT VT = Cmp.getValueType(); 3268 3269 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3270 Alignment = getMVTAlignment(VT); 3271 3272 SDVTList VTs = getVTList(VT, MVT::Other); 3273 FoldingSetNodeID ID; 3274 SDValue Ops[] = {Chain, Ptr, Cmp, Swp}; 3275 AddNodeIDNode(ID, Opcode, VTs, Ops, 4); 3276 void* IP = 0; 3277 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3278 return SDValue(E, 0); 3279 SDNode* N = NodeAllocator.Allocate<AtomicSDNode>(); 3280 new (N) AtomicSDNode(Opcode, VTs, Chain, Ptr, Cmp, Swp, PtrVal, Alignment); 3281 CSEMap.InsertNode(N, IP); 3282 AllNodes.push_back(N); 3283 return SDValue(N, 0); 3284} 3285 3286SDValue SelectionDAG::getAtomic(unsigned Opcode, SDValue Chain, 3287 SDValue Ptr, SDValue Val, 3288 const Value* PtrVal, 3289 unsigned Alignment) { 3290 assert((Opcode == ISD::ATOMIC_LOAD_ADD_8 || 3291 Opcode == ISD::ATOMIC_LOAD_SUB_8 || 3292 Opcode == ISD::ATOMIC_LOAD_AND_8 || 3293 Opcode == ISD::ATOMIC_LOAD_OR_8 || 3294 Opcode == ISD::ATOMIC_LOAD_XOR_8 || 3295 Opcode == ISD::ATOMIC_LOAD_NAND_8 || 3296 Opcode == ISD::ATOMIC_LOAD_MIN_8 || 3297 Opcode == ISD::ATOMIC_LOAD_MAX_8 || 3298 Opcode == ISD::ATOMIC_LOAD_UMIN_8 || 3299 Opcode == ISD::ATOMIC_LOAD_UMAX_8 || 3300 Opcode == ISD::ATOMIC_SWAP_8 || 3301 Opcode == ISD::ATOMIC_LOAD_ADD_16 || 3302 Opcode == ISD::ATOMIC_LOAD_SUB_16 || 3303 Opcode == ISD::ATOMIC_LOAD_AND_16 || 3304 Opcode == ISD::ATOMIC_LOAD_OR_16 || 3305 Opcode == ISD::ATOMIC_LOAD_XOR_16 || 3306 Opcode == ISD::ATOMIC_LOAD_NAND_16 || 3307 Opcode == ISD::ATOMIC_LOAD_MIN_16 || 3308 Opcode == ISD::ATOMIC_LOAD_MAX_16 || 3309 Opcode == ISD::ATOMIC_LOAD_UMIN_16 || 3310 Opcode == ISD::ATOMIC_LOAD_UMAX_16 || 3311 Opcode == ISD::ATOMIC_SWAP_16 || 3312 Opcode == ISD::ATOMIC_LOAD_ADD_32 || 3313 Opcode == ISD::ATOMIC_LOAD_SUB_32 || 3314 Opcode == ISD::ATOMIC_LOAD_AND_32 || 3315 Opcode == ISD::ATOMIC_LOAD_OR_32 || 3316 Opcode == ISD::ATOMIC_LOAD_XOR_32 || 3317 Opcode == ISD::ATOMIC_LOAD_NAND_32 || 3318 Opcode == ISD::ATOMIC_LOAD_MIN_32 || 3319 Opcode == ISD::ATOMIC_LOAD_MAX_32 || 3320 Opcode == ISD::ATOMIC_LOAD_UMIN_32 || 3321 Opcode == ISD::ATOMIC_LOAD_UMAX_32 || 3322 Opcode == ISD::ATOMIC_SWAP_32 || 3323 Opcode == ISD::ATOMIC_LOAD_ADD_64 || 3324 Opcode == ISD::ATOMIC_LOAD_SUB_64 || 3325 Opcode == ISD::ATOMIC_LOAD_AND_64 || 3326 Opcode == ISD::ATOMIC_LOAD_OR_64 || 3327 Opcode == ISD::ATOMIC_LOAD_XOR_64 || 3328 Opcode == ISD::ATOMIC_LOAD_NAND_64 || 3329 Opcode == ISD::ATOMIC_LOAD_MIN_64 || 3330 Opcode == ISD::ATOMIC_LOAD_MAX_64 || 3331 Opcode == ISD::ATOMIC_LOAD_UMIN_64 || 3332 Opcode == ISD::ATOMIC_LOAD_UMAX_64 || 3333 Opcode == ISD::ATOMIC_SWAP_64) && "Invalid Atomic Op"); 3334 3335 MVT VT = Val.getValueType(); 3336 3337 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3338 Alignment = getMVTAlignment(VT); 3339 3340 SDVTList VTs = getVTList(VT, MVT::Other); 3341 FoldingSetNodeID ID; 3342 SDValue Ops[] = {Chain, Ptr, Val}; 3343 AddNodeIDNode(ID, Opcode, VTs, Ops, 3); 3344 void* IP = 0; 3345 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3346 return SDValue(E, 0); 3347 SDNode* N = NodeAllocator.Allocate<AtomicSDNode>(); 3348 new (N) AtomicSDNode(Opcode, VTs, Chain, Ptr, Val, PtrVal, Alignment); 3349 CSEMap.InsertNode(N, IP); 3350 AllNodes.push_back(N); 3351 return SDValue(N, 0); 3352} 3353 3354/// getMergeValues - Create a MERGE_VALUES node from the given operands. 3355/// Allowed to return something different (and simpler) if Simplify is true. 3356SDValue SelectionDAG::getMergeValues(const SDValue *Ops, unsigned NumOps, 3357 bool Simplify) { 3358 if (Simplify && NumOps == 1) 3359 return Ops[0]; 3360 3361 SmallVector<MVT, 4> VTs; 3362 VTs.reserve(NumOps); 3363 for (unsigned i = 0; i < NumOps; ++i) 3364 VTs.push_back(Ops[i].getValueType()); 3365 return getNode(ISD::MERGE_VALUES, getVTList(&VTs[0], NumOps), Ops, NumOps); 3366} 3367 3368SDValue 3369SelectionDAG::getMemIntrinsicNode(unsigned Opcode, 3370 const MVT *VTs, unsigned NumVTs, 3371 const SDValue *Ops, unsigned NumOps, 3372 MVT MemVT, const Value *srcValue, int SVOff, 3373 unsigned Align, bool Vol, 3374 bool ReadMem, bool WriteMem) { 3375 return getMemIntrinsicNode(Opcode, makeVTList(VTs, NumVTs), Ops, NumOps, 3376 MemVT, srcValue, SVOff, Align, Vol, 3377 ReadMem, WriteMem); 3378} 3379 3380SDValue 3381SelectionDAG::getMemIntrinsicNode(unsigned Opcode, SDVTList VTList, 3382 const SDValue *Ops, unsigned NumOps, 3383 MVT MemVT, const Value *srcValue, int SVOff, 3384 unsigned Align, bool Vol, 3385 bool ReadMem, bool WriteMem) { 3386 // Memoize the node unless it returns a flag. 3387 MemIntrinsicSDNode *N; 3388 if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) { 3389 FoldingSetNodeID ID; 3390 AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps); 3391 void *IP = 0; 3392 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3393 return SDValue(E, 0); 3394 3395 N = NodeAllocator.Allocate<MemIntrinsicSDNode>(); 3396 new (N) MemIntrinsicSDNode(Opcode, VTList, Ops, NumOps, MemVT, 3397 srcValue, SVOff, Align, Vol, ReadMem, WriteMem); 3398 CSEMap.InsertNode(N, IP); 3399 } else { 3400 N = NodeAllocator.Allocate<MemIntrinsicSDNode>(); 3401 new (N) MemIntrinsicSDNode(Opcode, VTList, Ops, NumOps, MemVT, 3402 srcValue, SVOff, Align, Vol, ReadMem, WriteMem); 3403 } 3404 AllNodes.push_back(N); 3405 return SDValue(N, 0); 3406} 3407 3408SDValue 3409SelectionDAG::getCall(unsigned CallingConv, bool IsVarArgs, bool IsTailCall, 3410 bool IsInreg, SDVTList VTs, 3411 const SDValue *Operands, unsigned NumOperands) { 3412 // Do not include isTailCall in the folding set profile. 3413 FoldingSetNodeID ID; 3414 AddNodeIDNode(ID, ISD::CALL, VTs, Operands, NumOperands); 3415 ID.AddInteger(CallingConv); 3416 ID.AddInteger(IsVarArgs); 3417 void *IP = 0; 3418 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) { 3419 // Instead of including isTailCall in the folding set, we just 3420 // set the flag of the existing node. 3421 if (!IsTailCall) 3422 cast<CallSDNode>(E)->setNotTailCall(); 3423 return SDValue(E, 0); 3424 } 3425 SDNode *N = NodeAllocator.Allocate<CallSDNode>(); 3426 new (N) CallSDNode(CallingConv, IsVarArgs, IsTailCall, IsInreg, 3427 VTs, Operands, NumOperands); 3428 CSEMap.InsertNode(N, IP); 3429 AllNodes.push_back(N); 3430 return SDValue(N, 0); 3431} 3432 3433SDValue 3434SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, 3435 MVT VT, SDValue Chain, 3436 SDValue Ptr, SDValue Offset, 3437 const Value *SV, int SVOffset, MVT EVT, 3438 bool isVolatile, unsigned Alignment) { 3439 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3440 Alignment = getMVTAlignment(VT); 3441 3442 if (VT == EVT) { 3443 ExtType = ISD::NON_EXTLOAD; 3444 } else if (ExtType == ISD::NON_EXTLOAD) { 3445 assert(VT == EVT && "Non-extending load from different memory type!"); 3446 } else { 3447 // Extending load. 3448 if (VT.isVector()) 3449 assert(EVT.getVectorNumElements() == VT.getVectorNumElements() && 3450 "Invalid vector extload!"); 3451 else 3452 assert(EVT.bitsLT(VT) && 3453 "Should only be an extending load, not truncating!"); 3454 assert((ExtType == ISD::EXTLOAD || VT.isInteger()) && 3455 "Cannot sign/zero extend a FP/Vector load!"); 3456 assert(VT.isInteger() == EVT.isInteger() && 3457 "Cannot convert from FP to Int or Int -> FP!"); 3458 } 3459 3460 bool Indexed = AM != ISD::UNINDEXED; 3461 assert((Indexed || Offset.getOpcode() == ISD::UNDEF) && 3462 "Unindexed load with an offset!"); 3463 3464 SDVTList VTs = Indexed ? 3465 getVTList(VT, Ptr.getValueType(), MVT::Other) : getVTList(VT, MVT::Other); 3466 SDValue Ops[] = { Chain, Ptr, Offset }; 3467 FoldingSetNodeID ID; 3468 AddNodeIDNode(ID, ISD::LOAD, VTs, Ops, 3); 3469 ID.AddInteger(AM); 3470 ID.AddInteger(ExtType); 3471 ID.AddInteger(EVT.getRawBits()); 3472 ID.AddInteger(encodeMemSDNodeFlags(isVolatile, Alignment)); 3473 void *IP = 0; 3474 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3475 return SDValue(E, 0); 3476 SDNode *N = NodeAllocator.Allocate<LoadSDNode>(); 3477 new (N) LoadSDNode(Ops, VTs, AM, ExtType, EVT, SV, SVOffset, 3478 Alignment, isVolatile); 3479 CSEMap.InsertNode(N, IP); 3480 AllNodes.push_back(N); 3481 return SDValue(N, 0); 3482} 3483 3484SDValue SelectionDAG::getLoad(MVT VT, 3485 SDValue Chain, SDValue Ptr, 3486 const Value *SV, int SVOffset, 3487 bool isVolatile, unsigned Alignment) { 3488 SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType()); 3489 return getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD, VT, Chain, Ptr, Undef, 3490 SV, SVOffset, VT, isVolatile, Alignment); 3491} 3492 3493SDValue SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, MVT VT, 3494 SDValue Chain, SDValue Ptr, 3495 const Value *SV, 3496 int SVOffset, MVT EVT, 3497 bool isVolatile, unsigned Alignment) { 3498 SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType()); 3499 return getLoad(ISD::UNINDEXED, ExtType, VT, Chain, Ptr, Undef, 3500 SV, SVOffset, EVT, isVolatile, Alignment); 3501} 3502 3503SDValue 3504SelectionDAG::getIndexedLoad(SDValue OrigLoad, SDValue Base, 3505 SDValue Offset, ISD::MemIndexedMode AM) { 3506 LoadSDNode *LD = cast<LoadSDNode>(OrigLoad); 3507 assert(LD->getOffset().getOpcode() == ISD::UNDEF && 3508 "Load is already a indexed load!"); 3509 return getLoad(AM, LD->getExtensionType(), OrigLoad.getValueType(), 3510 LD->getChain(), Base, Offset, LD->getSrcValue(), 3511 LD->getSrcValueOffset(), LD->getMemoryVT(), 3512 LD->isVolatile(), LD->getAlignment()); 3513} 3514 3515SDValue SelectionDAG::getStore(SDValue Chain, SDValue Val, 3516 SDValue Ptr, const Value *SV, int SVOffset, 3517 bool isVolatile, unsigned Alignment) { 3518 MVT VT = Val.getValueType(); 3519 3520 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3521 Alignment = getMVTAlignment(VT); 3522 3523 SDVTList VTs = getVTList(MVT::Other); 3524 SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType()); 3525 SDValue Ops[] = { Chain, Val, Ptr, Undef }; 3526 FoldingSetNodeID ID; 3527 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); 3528 ID.AddInteger(ISD::UNINDEXED); 3529 ID.AddInteger(false); 3530 ID.AddInteger(VT.getRawBits()); 3531 ID.AddInteger(encodeMemSDNodeFlags(isVolatile, Alignment)); 3532 void *IP = 0; 3533 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3534 return SDValue(E, 0); 3535 SDNode *N = NodeAllocator.Allocate<StoreSDNode>(); 3536 new (N) StoreSDNode(Ops, VTs, ISD::UNINDEXED, false, 3537 VT, SV, SVOffset, Alignment, isVolatile); 3538 CSEMap.InsertNode(N, IP); 3539 AllNodes.push_back(N); 3540 return SDValue(N, 0); 3541} 3542 3543SDValue SelectionDAG::getTruncStore(SDValue Chain, SDValue Val, 3544 SDValue Ptr, const Value *SV, 3545 int SVOffset, MVT SVT, 3546 bool isVolatile, unsigned Alignment) { 3547 MVT VT = Val.getValueType(); 3548 3549 if (VT == SVT) 3550 return getStore(Chain, Val, Ptr, SV, SVOffset, isVolatile, Alignment); 3551 3552 assert(VT.bitsGT(SVT) && "Not a truncation?"); 3553 assert(VT.isInteger() == SVT.isInteger() && 3554 "Can't do FP-INT conversion!"); 3555 3556 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3557 Alignment = getMVTAlignment(VT); 3558 3559 SDVTList VTs = getVTList(MVT::Other); 3560 SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType()); 3561 SDValue Ops[] = { Chain, Val, Ptr, Undef }; 3562 FoldingSetNodeID ID; 3563 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); 3564 ID.AddInteger(ISD::UNINDEXED); 3565 ID.AddInteger(1); 3566 ID.AddInteger(SVT.getRawBits()); 3567 ID.AddInteger(encodeMemSDNodeFlags(isVolatile, Alignment)); 3568 void *IP = 0; 3569 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3570 return SDValue(E, 0); 3571 SDNode *N = NodeAllocator.Allocate<StoreSDNode>(); 3572 new (N) StoreSDNode(Ops, VTs, ISD::UNINDEXED, true, 3573 SVT, SV, SVOffset, Alignment, isVolatile); 3574 CSEMap.InsertNode(N, IP); 3575 AllNodes.push_back(N); 3576 return SDValue(N, 0); 3577} 3578 3579SDValue 3580SelectionDAG::getIndexedStore(SDValue OrigStore, SDValue Base, 3581 SDValue Offset, ISD::MemIndexedMode AM) { 3582 StoreSDNode *ST = cast<StoreSDNode>(OrigStore); 3583 assert(ST->getOffset().getOpcode() == ISD::UNDEF && 3584 "Store is already a indexed store!"); 3585 SDVTList VTs = getVTList(Base.getValueType(), MVT::Other); 3586 SDValue Ops[] = { ST->getChain(), ST->getValue(), Base, Offset }; 3587 FoldingSetNodeID ID; 3588 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); 3589 ID.AddInteger(AM); 3590 ID.AddInteger(ST->isTruncatingStore()); 3591 ID.AddInteger(ST->getMemoryVT().getRawBits()); 3592 ID.AddInteger(ST->getRawFlags()); 3593 void *IP = 0; 3594 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3595 return SDValue(E, 0); 3596 SDNode *N = NodeAllocator.Allocate<StoreSDNode>(); 3597 new (N) StoreSDNode(Ops, VTs, AM, 3598 ST->isTruncatingStore(), ST->getMemoryVT(), 3599 ST->getSrcValue(), ST->getSrcValueOffset(), 3600 ST->getAlignment(), ST->isVolatile()); 3601 CSEMap.InsertNode(N, IP); 3602 AllNodes.push_back(N); 3603 return SDValue(N, 0); 3604} 3605 3606SDValue SelectionDAG::getVAArg(MVT VT, 3607 SDValue Chain, SDValue Ptr, 3608 SDValue SV) { 3609 SDValue Ops[] = { Chain, Ptr, SV }; 3610 return getNode(ISD::VAARG, getVTList(VT, MVT::Other), Ops, 3); 3611} 3612 3613SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, 3614 const SDUse *Ops, unsigned NumOps) { 3615 switch (NumOps) { 3616 case 0: return getNode(Opcode, VT); 3617 case 1: return getNode(Opcode, VT, Ops[0]); 3618 case 2: return getNode(Opcode, VT, Ops[0], Ops[1]); 3619 case 3: return getNode(Opcode, VT, Ops[0], Ops[1], Ops[2]); 3620 default: break; 3621 } 3622 3623 // Copy from an SDUse array into an SDValue array for use with 3624 // the regular getNode logic. 3625 SmallVector<SDValue, 8> NewOps(Ops, Ops + NumOps); 3626 return getNode(Opcode, VT, &NewOps[0], NumOps); 3627} 3628 3629SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, 3630 const SDValue *Ops, unsigned NumOps) { 3631 switch (NumOps) { 3632 case 0: return getNode(Opcode, VT); 3633 case 1: return getNode(Opcode, VT, Ops[0]); 3634 case 2: return getNode(Opcode, VT, Ops[0], Ops[1]); 3635 case 3: return getNode(Opcode, VT, Ops[0], Ops[1], Ops[2]); 3636 default: break; 3637 } 3638 3639 switch (Opcode) { 3640 default: break; 3641 case ISD::SELECT_CC: { 3642 assert(NumOps == 5 && "SELECT_CC takes 5 operands!"); 3643 assert(Ops[0].getValueType() == Ops[1].getValueType() && 3644 "LHS and RHS of condition must have same type!"); 3645 assert(Ops[2].getValueType() == Ops[3].getValueType() && 3646 "True and False arms of SelectCC must have same type!"); 3647 assert(Ops[2].getValueType() == VT && 3648 "select_cc node must be of same type as true and false value!"); 3649 break; 3650 } 3651 case ISD::BR_CC: { 3652 assert(NumOps == 5 && "BR_CC takes 5 operands!"); 3653 assert(Ops[2].getValueType() == Ops[3].getValueType() && 3654 "LHS/RHS of comparison should match types!"); 3655 break; 3656 } 3657 } 3658 3659 // Memoize nodes. 3660 SDNode *N; 3661 SDVTList VTs = getVTList(VT); 3662 if (VT != MVT::Flag) { 3663 FoldingSetNodeID ID; 3664 AddNodeIDNode(ID, Opcode, VTs, Ops, NumOps); 3665 void *IP = 0; 3666 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3667 return SDValue(E, 0); 3668 N = NodeAllocator.Allocate<SDNode>(); 3669 new (N) SDNode(Opcode, VTs, Ops, NumOps); 3670 CSEMap.InsertNode(N, IP); 3671 } else { 3672 N = NodeAllocator.Allocate<SDNode>(); 3673 new (N) SDNode(Opcode, VTs, Ops, NumOps); 3674 } 3675 AllNodes.push_back(N); 3676#ifndef NDEBUG 3677 VerifyNode(N); 3678#endif 3679 return SDValue(N, 0); 3680} 3681 3682SDValue SelectionDAG::getNode(unsigned Opcode, 3683 const std::vector<MVT> &ResultTys, 3684 const SDValue *Ops, unsigned NumOps) { 3685 return getNode(Opcode, getNodeValueTypes(ResultTys), ResultTys.size(), 3686 Ops, NumOps); 3687} 3688 3689SDValue SelectionDAG::getNode(unsigned Opcode, 3690 const MVT *VTs, unsigned NumVTs, 3691 const SDValue *Ops, unsigned NumOps) { 3692 if (NumVTs == 1) 3693 return getNode(Opcode, VTs[0], Ops, NumOps); 3694 return getNode(Opcode, makeVTList(VTs, NumVTs), Ops, NumOps); 3695} 3696 3697SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, 3698 const SDValue *Ops, unsigned NumOps) { 3699 if (VTList.NumVTs == 1) 3700 return getNode(Opcode, VTList.VTs[0], Ops, NumOps); 3701 3702 switch (Opcode) { 3703 // FIXME: figure out how to safely handle things like 3704 // int foo(int x) { return 1 << (x & 255); } 3705 // int bar() { return foo(256); } 3706#if 0 3707 case ISD::SRA_PARTS: 3708 case ISD::SRL_PARTS: 3709 case ISD::SHL_PARTS: 3710 if (N3.getOpcode() == ISD::SIGN_EXTEND_INREG && 3711 cast<VTSDNode>(N3.getOperand(1))->getVT() != MVT::i1) 3712 return getNode(Opcode, VT, N1, N2, N3.getOperand(0)); 3713 else if (N3.getOpcode() == ISD::AND) 3714 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(N3.getOperand(1))) { 3715 // If the and is only masking out bits that cannot effect the shift, 3716 // eliminate the and. 3717 unsigned NumBits = VT.getSizeInBits()*2; 3718 if ((AndRHS->getValue() & (NumBits-1)) == NumBits-1) 3719 return getNode(Opcode, VT, N1, N2, N3.getOperand(0)); 3720 } 3721 break; 3722#endif 3723 } 3724 3725 // Memoize the node unless it returns a flag. 3726 SDNode *N; 3727 if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) { 3728 FoldingSetNodeID ID; 3729 AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps); 3730 void *IP = 0; 3731 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3732 return SDValue(E, 0); 3733 if (NumOps == 1) { 3734 N = NodeAllocator.Allocate<UnarySDNode>(); 3735 new (N) UnarySDNode(Opcode, VTList, Ops[0]); 3736 } else if (NumOps == 2) { 3737 N = NodeAllocator.Allocate<BinarySDNode>(); 3738 new (N) BinarySDNode(Opcode, VTList, Ops[0], Ops[1]); 3739 } else if (NumOps == 3) { 3740 N = NodeAllocator.Allocate<TernarySDNode>(); 3741 new (N) TernarySDNode(Opcode, VTList, Ops[0], Ops[1], Ops[2]); 3742 } else { 3743 N = NodeAllocator.Allocate<SDNode>(); 3744 new (N) SDNode(Opcode, VTList, Ops, NumOps); 3745 } 3746 CSEMap.InsertNode(N, IP); 3747 } else { 3748 if (NumOps == 1) { 3749 N = NodeAllocator.Allocate<UnarySDNode>(); 3750 new (N) UnarySDNode(Opcode, VTList, Ops[0]); 3751 } else if (NumOps == 2) { 3752 N = NodeAllocator.Allocate<BinarySDNode>(); 3753 new (N) BinarySDNode(Opcode, VTList, Ops[0], Ops[1]); 3754 } else if (NumOps == 3) { 3755 N = NodeAllocator.Allocate<TernarySDNode>(); 3756 new (N) TernarySDNode(Opcode, VTList, Ops[0], Ops[1], Ops[2]); 3757 } else { 3758 N = NodeAllocator.Allocate<SDNode>(); 3759 new (N) SDNode(Opcode, VTList, Ops, NumOps); 3760 } 3761 } 3762 AllNodes.push_back(N); 3763#ifndef NDEBUG 3764 VerifyNode(N); 3765#endif 3766 return SDValue(N, 0); 3767} 3768 3769SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList) { 3770 return getNode(Opcode, VTList, 0, 0); 3771} 3772 3773SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, 3774 SDValue N1) { 3775 SDValue Ops[] = { N1 }; 3776 return getNode(Opcode, VTList, Ops, 1); 3777} 3778 3779SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, 3780 SDValue N1, SDValue N2) { 3781 SDValue Ops[] = { N1, N2 }; 3782 return getNode(Opcode, VTList, Ops, 2); 3783} 3784 3785SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, 3786 SDValue N1, SDValue N2, SDValue N3) { 3787 SDValue Ops[] = { N1, N2, N3 }; 3788 return getNode(Opcode, VTList, Ops, 3); 3789} 3790 3791SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, 3792 SDValue N1, SDValue N2, SDValue N3, 3793 SDValue N4) { 3794 SDValue Ops[] = { N1, N2, N3, N4 }; 3795 return getNode(Opcode, VTList, Ops, 4); 3796} 3797 3798SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, 3799 SDValue N1, SDValue N2, SDValue N3, 3800 SDValue N4, SDValue N5) { 3801 SDValue Ops[] = { N1, N2, N3, N4, N5 }; 3802 return getNode(Opcode, VTList, Ops, 5); 3803} 3804 3805SDVTList SelectionDAG::getVTList(MVT VT) { 3806 return makeVTList(SDNode::getValueTypeList(VT), 1); 3807} 3808 3809SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2) { 3810 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 3811 E = VTList.rend(); I != E; ++I) 3812 if (I->NumVTs == 2 && I->VTs[0] == VT1 && I->VTs[1] == VT2) 3813 return *I; 3814 3815 MVT *Array = Allocator.Allocate<MVT>(2); 3816 Array[0] = VT1; 3817 Array[1] = VT2; 3818 SDVTList Result = makeVTList(Array, 2); 3819 VTList.push_back(Result); 3820 return Result; 3821} 3822 3823SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2, MVT VT3) { 3824 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 3825 E = VTList.rend(); I != E; ++I) 3826 if (I->NumVTs == 3 && I->VTs[0] == VT1 && I->VTs[1] == VT2 && 3827 I->VTs[2] == VT3) 3828 return *I; 3829 3830 MVT *Array = Allocator.Allocate<MVT>(3); 3831 Array[0] = VT1; 3832 Array[1] = VT2; 3833 Array[2] = VT3; 3834 SDVTList Result = makeVTList(Array, 3); 3835 VTList.push_back(Result); 3836 return Result; 3837} 3838 3839SDVTList SelectionDAG::getVTList(const MVT *VTs, unsigned NumVTs) { 3840 switch (NumVTs) { 3841 case 0: assert(0 && "Cannot have nodes without results!"); 3842 case 1: return getVTList(VTs[0]); 3843 case 2: return getVTList(VTs[0], VTs[1]); 3844 case 3: return getVTList(VTs[0], VTs[1], VTs[2]); 3845 default: break; 3846 } 3847 3848 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 3849 E = VTList.rend(); I != E; ++I) { 3850 if (I->NumVTs != NumVTs || VTs[0] != I->VTs[0] || VTs[1] != I->VTs[1]) 3851 continue; 3852 3853 bool NoMatch = false; 3854 for (unsigned i = 2; i != NumVTs; ++i) 3855 if (VTs[i] != I->VTs[i]) { 3856 NoMatch = true; 3857 break; 3858 } 3859 if (!NoMatch) 3860 return *I; 3861 } 3862 3863 MVT *Array = Allocator.Allocate<MVT>(NumVTs); 3864 std::copy(VTs, VTs+NumVTs, Array); 3865 SDVTList Result = makeVTList(Array, NumVTs); 3866 VTList.push_back(Result); 3867 return Result; 3868} 3869 3870 3871/// UpdateNodeOperands - *Mutate* the specified node in-place to have the 3872/// specified operands. If the resultant node already exists in the DAG, 3873/// this does not modify the specified node, instead it returns the node that 3874/// already exists. If the resultant node does not exist in the DAG, the 3875/// input node is returned. As a degenerate case, if you specify the same 3876/// input operands as the node already has, the input node is returned. 3877SDValue SelectionDAG::UpdateNodeOperands(SDValue InN, SDValue Op) { 3878 SDNode *N = InN.getNode(); 3879 assert(N->getNumOperands() == 1 && "Update with wrong number of operands"); 3880 3881 // Check to see if there is no change. 3882 if (Op == N->getOperand(0)) return InN; 3883 3884 // See if the modified node already exists. 3885 void *InsertPos = 0; 3886 if (SDNode *Existing = FindModifiedNodeSlot(N, Op, InsertPos)) 3887 return SDValue(Existing, InN.getResNo()); 3888 3889 // Nope it doesn't. Remove the node from its current place in the maps. 3890 if (InsertPos) 3891 if (!RemoveNodeFromCSEMaps(N)) 3892 InsertPos = 0; 3893 3894 // Now we update the operands. 3895 N->OperandList[0].getVal()->removeUser(0, N); 3896 N->OperandList[0] = Op; 3897 N->OperandList[0].setUser(N); 3898 Op.getNode()->addUser(0, N); 3899 3900 // If this gets put into a CSE map, add it. 3901 if (InsertPos) CSEMap.InsertNode(N, InsertPos); 3902 return InN; 3903} 3904 3905SDValue SelectionDAG:: 3906UpdateNodeOperands(SDValue InN, SDValue Op1, SDValue Op2) { 3907 SDNode *N = InN.getNode(); 3908 assert(N->getNumOperands() == 2 && "Update with wrong number of operands"); 3909 3910 // Check to see if there is no change. 3911 if (Op1 == N->getOperand(0) && Op2 == N->getOperand(1)) 3912 return InN; // No operands changed, just return the input node. 3913 3914 // See if the modified node already exists. 3915 void *InsertPos = 0; 3916 if (SDNode *Existing = FindModifiedNodeSlot(N, Op1, Op2, InsertPos)) 3917 return SDValue(Existing, InN.getResNo()); 3918 3919 // Nope it doesn't. Remove the node from its current place in the maps. 3920 if (InsertPos) 3921 if (!RemoveNodeFromCSEMaps(N)) 3922 InsertPos = 0; 3923 3924 // Now we update the operands. 3925 if (N->OperandList[0] != Op1) { 3926 N->OperandList[0].getVal()->removeUser(0, N); 3927 N->OperandList[0] = Op1; 3928 N->OperandList[0].setUser(N); 3929 Op1.getNode()->addUser(0, N); 3930 } 3931 if (N->OperandList[1] != Op2) { 3932 N->OperandList[1].getVal()->removeUser(1, N); 3933 N->OperandList[1] = Op2; 3934 N->OperandList[1].setUser(N); 3935 Op2.getNode()->addUser(1, N); 3936 } 3937 3938 // If this gets put into a CSE map, add it. 3939 if (InsertPos) CSEMap.InsertNode(N, InsertPos); 3940 return InN; 3941} 3942 3943SDValue SelectionDAG:: 3944UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, SDValue Op3) { 3945 SDValue Ops[] = { Op1, Op2, Op3 }; 3946 return UpdateNodeOperands(N, Ops, 3); 3947} 3948 3949SDValue SelectionDAG:: 3950UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, 3951 SDValue Op3, SDValue Op4) { 3952 SDValue Ops[] = { Op1, Op2, Op3, Op4 }; 3953 return UpdateNodeOperands(N, Ops, 4); 3954} 3955 3956SDValue SelectionDAG:: 3957UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, 3958 SDValue Op3, SDValue Op4, SDValue Op5) { 3959 SDValue Ops[] = { Op1, Op2, Op3, Op4, Op5 }; 3960 return UpdateNodeOperands(N, Ops, 5); 3961} 3962 3963SDValue SelectionDAG:: 3964UpdateNodeOperands(SDValue InN, const SDValue *Ops, unsigned NumOps) { 3965 SDNode *N = InN.getNode(); 3966 assert(N->getNumOperands() == NumOps && 3967 "Update with wrong number of operands"); 3968 3969 // Check to see if there is no change. 3970 bool AnyChange = false; 3971 for (unsigned i = 0; i != NumOps; ++i) { 3972 if (Ops[i] != N->getOperand(i)) { 3973 AnyChange = true; 3974 break; 3975 } 3976 } 3977 3978 // No operands changed, just return the input node. 3979 if (!AnyChange) return InN; 3980 3981 // See if the modified node already exists. 3982 void *InsertPos = 0; 3983 if (SDNode *Existing = FindModifiedNodeSlot(N, Ops, NumOps, InsertPos)) 3984 return SDValue(Existing, InN.getResNo()); 3985 3986 // Nope it doesn't. Remove the node from its current place in the maps. 3987 if (InsertPos) 3988 if (!RemoveNodeFromCSEMaps(N)) 3989 InsertPos = 0; 3990 3991 // Now we update the operands. 3992 for (unsigned i = 0; i != NumOps; ++i) { 3993 if (N->OperandList[i] != Ops[i]) { 3994 N->OperandList[i].getVal()->removeUser(i, N); 3995 N->OperandList[i] = Ops[i]; 3996 N->OperandList[i].setUser(N); 3997 Ops[i].getNode()->addUser(i, N); 3998 } 3999 } 4000 4001 // If this gets put into a CSE map, add it. 4002 if (InsertPos) CSEMap.InsertNode(N, InsertPos); 4003 return InN; 4004} 4005 4006/// DropOperands - Release the operands and set this node to have 4007/// zero operands. 4008void SDNode::DropOperands() { 4009 // Unlike the code in MorphNodeTo that does this, we don't need to 4010 // watch for dead nodes here. 4011 for (op_iterator I = op_begin(), E = op_end(); I != E; ++I) 4012 I->getVal()->removeUser(std::distance(op_begin(), I), this); 4013 4014 NumOperands = 0; 4015} 4016 4017/// SelectNodeTo - These are wrappers around MorphNodeTo that accept a 4018/// machine opcode. 4019/// 4020SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4021 MVT VT) { 4022 SDVTList VTs = getVTList(VT); 4023 return SelectNodeTo(N, MachineOpc, VTs, 0, 0); 4024} 4025 4026SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4027 MVT VT, SDValue Op1) { 4028 SDVTList VTs = getVTList(VT); 4029 SDValue Ops[] = { Op1 }; 4030 return SelectNodeTo(N, MachineOpc, VTs, Ops, 1); 4031} 4032 4033SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4034 MVT VT, SDValue Op1, 4035 SDValue Op2) { 4036 SDVTList VTs = getVTList(VT); 4037 SDValue Ops[] = { Op1, Op2 }; 4038 return SelectNodeTo(N, MachineOpc, VTs, Ops, 2); 4039} 4040 4041SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4042 MVT VT, SDValue Op1, 4043 SDValue Op2, SDValue Op3) { 4044 SDVTList VTs = getVTList(VT); 4045 SDValue Ops[] = { Op1, Op2, Op3 }; 4046 return SelectNodeTo(N, MachineOpc, VTs, Ops, 3); 4047} 4048 4049SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4050 MVT VT, const SDValue *Ops, 4051 unsigned NumOps) { 4052 SDVTList VTs = getVTList(VT); 4053 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 4054} 4055 4056SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4057 MVT VT1, MVT VT2, const SDValue *Ops, 4058 unsigned NumOps) { 4059 SDVTList VTs = getVTList(VT1, VT2); 4060 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 4061} 4062 4063SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4064 MVT VT1, MVT VT2) { 4065 SDVTList VTs = getVTList(VT1, VT2); 4066 return SelectNodeTo(N, MachineOpc, VTs, (SDValue *)0, 0); 4067} 4068 4069SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4070 MVT VT1, MVT VT2, MVT VT3, 4071 const SDValue *Ops, unsigned NumOps) { 4072 SDVTList VTs = getVTList(VT1, VT2, VT3); 4073 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 4074} 4075 4076SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4077 MVT VT1, MVT VT2, 4078 SDValue Op1) { 4079 SDVTList VTs = getVTList(VT1, VT2); 4080 SDValue Ops[] = { Op1 }; 4081 return SelectNodeTo(N, MachineOpc, VTs, Ops, 1); 4082} 4083 4084SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4085 MVT VT1, MVT VT2, 4086 SDValue Op1, SDValue Op2) { 4087 SDVTList VTs = getVTList(VT1, VT2); 4088 SDValue Ops[] = { Op1, Op2 }; 4089 return SelectNodeTo(N, MachineOpc, VTs, Ops, 2); 4090} 4091 4092SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4093 MVT VT1, MVT VT2, 4094 SDValue Op1, SDValue Op2, 4095 SDValue Op3) { 4096 SDVTList VTs = getVTList(VT1, VT2); 4097 SDValue Ops[] = { Op1, Op2, Op3 }; 4098 return SelectNodeTo(N, MachineOpc, VTs, Ops, 3); 4099} 4100 4101SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4102 SDVTList VTs, const SDValue *Ops, 4103 unsigned NumOps) { 4104 return MorphNodeTo(N, ~MachineOpc, VTs, Ops, NumOps); 4105} 4106 4107SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4108 MVT VT) { 4109 SDVTList VTs = getVTList(VT); 4110 return MorphNodeTo(N, Opc, VTs, 0, 0); 4111} 4112 4113SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4114 MVT VT, SDValue Op1) { 4115 SDVTList VTs = getVTList(VT); 4116 SDValue Ops[] = { Op1 }; 4117 return MorphNodeTo(N, Opc, VTs, Ops, 1); 4118} 4119 4120SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4121 MVT VT, SDValue Op1, 4122 SDValue Op2) { 4123 SDVTList VTs = getVTList(VT); 4124 SDValue Ops[] = { Op1, Op2 }; 4125 return MorphNodeTo(N, Opc, VTs, Ops, 2); 4126} 4127 4128SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4129 MVT VT, SDValue Op1, 4130 SDValue Op2, SDValue Op3) { 4131 SDVTList VTs = getVTList(VT); 4132 SDValue Ops[] = { Op1, Op2, Op3 }; 4133 return MorphNodeTo(N, Opc, VTs, Ops, 3); 4134} 4135 4136SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4137 MVT VT, const SDValue *Ops, 4138 unsigned NumOps) { 4139 SDVTList VTs = getVTList(VT); 4140 return MorphNodeTo(N, Opc, VTs, Ops, NumOps); 4141} 4142 4143SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4144 MVT VT1, MVT VT2, const SDValue *Ops, 4145 unsigned NumOps) { 4146 SDVTList VTs = getVTList(VT1, VT2); 4147 return MorphNodeTo(N, Opc, VTs, Ops, NumOps); 4148} 4149 4150SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4151 MVT VT1, MVT VT2) { 4152 SDVTList VTs = getVTList(VT1, VT2); 4153 return MorphNodeTo(N, Opc, VTs, (SDValue *)0, 0); 4154} 4155 4156SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4157 MVT VT1, MVT VT2, MVT VT3, 4158 const SDValue *Ops, unsigned NumOps) { 4159 SDVTList VTs = getVTList(VT1, VT2, VT3); 4160 return MorphNodeTo(N, Opc, VTs, Ops, NumOps); 4161} 4162 4163SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4164 MVT VT1, MVT VT2, 4165 SDValue Op1) { 4166 SDVTList VTs = getVTList(VT1, VT2); 4167 SDValue Ops[] = { Op1 }; 4168 return MorphNodeTo(N, Opc, VTs, Ops, 1); 4169} 4170 4171SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4172 MVT VT1, MVT VT2, 4173 SDValue Op1, SDValue Op2) { 4174 SDVTList VTs = getVTList(VT1, VT2); 4175 SDValue Ops[] = { Op1, Op2 }; 4176 return MorphNodeTo(N, Opc, VTs, Ops, 2); 4177} 4178 4179SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4180 MVT VT1, MVT VT2, 4181 SDValue Op1, SDValue Op2, 4182 SDValue Op3) { 4183 SDVTList VTs = getVTList(VT1, VT2); 4184 SDValue Ops[] = { Op1, Op2, Op3 }; 4185 return MorphNodeTo(N, Opc, VTs, Ops, 3); 4186} 4187 4188/// MorphNodeTo - These *mutate* the specified node to have the specified 4189/// return type, opcode, and operands. 4190/// 4191/// Note that MorphNodeTo returns the resultant node. If there is already a 4192/// node of the specified opcode and operands, it returns that node instead of 4193/// the current one. 4194/// 4195/// Using MorphNodeTo is faster than creating a new node and swapping it in 4196/// with ReplaceAllUsesWith both because it often avoids allocating a new 4197/// node, and because it doesn't require CSE recalculation for any of 4198/// the node's users. 4199/// 4200SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4201 SDVTList VTs, const SDValue *Ops, 4202 unsigned NumOps) { 4203 // If an identical node already exists, use it. 4204 void *IP = 0; 4205 if (VTs.VTs[VTs.NumVTs-1] != MVT::Flag) { 4206 FoldingSetNodeID ID; 4207 AddNodeIDNode(ID, Opc, VTs, Ops, NumOps); 4208 if (SDNode *ON = CSEMap.FindNodeOrInsertPos(ID, IP)) 4209 return ON; 4210 } 4211 4212 if (!RemoveNodeFromCSEMaps(N)) 4213 IP = 0; 4214 4215 // Start the morphing. 4216 N->NodeType = Opc; 4217 N->ValueList = VTs.VTs; 4218 N->NumValues = VTs.NumVTs; 4219 4220 // Clear the operands list, updating used nodes to remove this from their 4221 // use list. Keep track of any operands that become dead as a result. 4222 SmallPtrSet<SDNode*, 16> DeadNodeSet; 4223 for (SDNode::op_iterator B = N->op_begin(), I = B, E = N->op_end(); 4224 I != E; ++I) { 4225 SDNode *Used = I->getVal(); 4226 Used->removeUser(std::distance(B, I), N); 4227 if (Used->use_empty()) 4228 DeadNodeSet.insert(Used); 4229 } 4230 4231 // If NumOps is larger than the # of operands we currently have, reallocate 4232 // the operand list. 4233 if (NumOps > N->NumOperands) { 4234 if (N->OperandsNeedDelete) 4235 delete[] N->OperandList; 4236 4237 if (N->isMachineOpcode()) { 4238 // We're creating a final node that will live unmorphed for the 4239 // remainder of the current SelectionDAG iteration, so we can allocate 4240 // the operands directly out of a pool with no recycling metadata. 4241 N->OperandList = OperandAllocator.Allocate<SDUse>(NumOps); 4242 N->OperandsNeedDelete = false; 4243 } else { 4244 N->OperandList = new SDUse[NumOps]; 4245 N->OperandsNeedDelete = true; 4246 } 4247 } 4248 4249 // Assign the new operands. 4250 N->NumOperands = NumOps; 4251 for (unsigned i = 0, e = NumOps; i != e; ++i) { 4252 N->OperandList[i] = Ops[i]; 4253 N->OperandList[i].setUser(N); 4254 SDNode *ToUse = N->OperandList[i].getVal(); 4255 ToUse->addUser(i, N); 4256 } 4257 4258 // Delete any nodes that are still dead after adding the uses for the 4259 // new operands. 4260 SmallVector<SDNode *, 16> DeadNodes; 4261 for (SmallPtrSet<SDNode *, 16>::iterator I = DeadNodeSet.begin(), 4262 E = DeadNodeSet.end(); I != E; ++I) 4263 if ((*I)->use_empty()) 4264 DeadNodes.push_back(*I); 4265 RemoveDeadNodes(DeadNodes); 4266 4267 if (IP) 4268 CSEMap.InsertNode(N, IP); // Memoize the new node. 4269 return N; 4270} 4271 4272 4273/// getTargetNode - These are used for target selectors to create a new node 4274/// with specified return type(s), target opcode, and operands. 4275/// 4276/// Note that getTargetNode returns the resultant node. If there is already a 4277/// node of the specified opcode and operands, it returns that node instead of 4278/// the current one. 4279SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT) { 4280 return getNode(~Opcode, VT).getNode(); 4281} 4282SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT, SDValue Op1) { 4283 return getNode(~Opcode, VT, Op1).getNode(); 4284} 4285SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT, 4286 SDValue Op1, SDValue Op2) { 4287 return getNode(~Opcode, VT, Op1, Op2).getNode(); 4288} 4289SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT, 4290 SDValue Op1, SDValue Op2, 4291 SDValue Op3) { 4292 return getNode(~Opcode, VT, Op1, Op2, Op3).getNode(); 4293} 4294SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT, 4295 const SDValue *Ops, unsigned NumOps) { 4296 return getNode(~Opcode, VT, Ops, NumOps).getNode(); 4297} 4298SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2) { 4299 const MVT *VTs = getNodeValueTypes(VT1, VT2); 4300 SDValue Op; 4301 return getNode(~Opcode, VTs, 2, &Op, 0).getNode(); 4302} 4303SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, 4304 MVT VT2, SDValue Op1) { 4305 const MVT *VTs = getNodeValueTypes(VT1, VT2); 4306 return getNode(~Opcode, VTs, 2, &Op1, 1).getNode(); 4307} 4308SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, 4309 MVT VT2, SDValue Op1, 4310 SDValue Op2) { 4311 const MVT *VTs = getNodeValueTypes(VT1, VT2); 4312 SDValue Ops[] = { Op1, Op2 }; 4313 return getNode(~Opcode, VTs, 2, Ops, 2).getNode(); 4314} 4315SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, 4316 MVT VT2, SDValue Op1, 4317 SDValue Op2, SDValue Op3) { 4318 const MVT *VTs = getNodeValueTypes(VT1, VT2); 4319 SDValue Ops[] = { Op1, Op2, Op3 }; 4320 return getNode(~Opcode, VTs, 2, Ops, 3).getNode(); 4321} 4322SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, 4323 const SDValue *Ops, unsigned NumOps) { 4324 const MVT *VTs = getNodeValueTypes(VT1, VT2); 4325 return getNode(~Opcode, VTs, 2, Ops, NumOps).getNode(); 4326} 4327SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3, 4328 SDValue Op1, SDValue Op2) { 4329 const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3); 4330 SDValue Ops[] = { Op1, Op2 }; 4331 return getNode(~Opcode, VTs, 3, Ops, 2).getNode(); 4332} 4333SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3, 4334 SDValue Op1, SDValue Op2, 4335 SDValue Op3) { 4336 const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3); 4337 SDValue Ops[] = { Op1, Op2, Op3 }; 4338 return getNode(~Opcode, VTs, 3, Ops, 3).getNode(); 4339} 4340SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3, 4341 const SDValue *Ops, unsigned NumOps) { 4342 const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3); 4343 return getNode(~Opcode, VTs, 3, Ops, NumOps).getNode(); 4344} 4345SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, 4346 MVT VT2, MVT VT3, MVT VT4, 4347 const SDValue *Ops, unsigned NumOps) { 4348 std::vector<MVT> VTList; 4349 VTList.push_back(VT1); 4350 VTList.push_back(VT2); 4351 VTList.push_back(VT3); 4352 VTList.push_back(VT4); 4353 const MVT *VTs = getNodeValueTypes(VTList); 4354 return getNode(~Opcode, VTs, 4, Ops, NumOps).getNode(); 4355} 4356SDNode *SelectionDAG::getTargetNode(unsigned Opcode, 4357 const std::vector<MVT> &ResultTys, 4358 const SDValue *Ops, unsigned NumOps) { 4359 const MVT *VTs = getNodeValueTypes(ResultTys); 4360 return getNode(~Opcode, VTs, ResultTys.size(), 4361 Ops, NumOps).getNode(); 4362} 4363 4364/// getNodeIfExists - Get the specified node if it's already available, or 4365/// else return NULL. 4366SDNode *SelectionDAG::getNodeIfExists(unsigned Opcode, SDVTList VTList, 4367 const SDValue *Ops, unsigned NumOps) { 4368 if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) { 4369 FoldingSetNodeID ID; 4370 AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps); 4371 void *IP = 0; 4372 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 4373 return E; 4374 } 4375 return NULL; 4376} 4377 4378 4379/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. 4380/// This can cause recursive merging of nodes in the DAG. 4381/// 4382/// This version assumes From has a single result value. 4383/// 4384void SelectionDAG::ReplaceAllUsesWith(SDValue FromN, SDValue To, 4385 DAGUpdateListener *UpdateListener) { 4386 SDNode *From = FromN.getNode(); 4387 assert(From->getNumValues() == 1 && FromN.getResNo() == 0 && 4388 "Cannot replace with this method!"); 4389 assert(From != To.getNode() && "Cannot replace uses of with self"); 4390 4391 while (!From->use_empty()) { 4392 SDNode::use_iterator UI = From->use_begin(); 4393 SDNode *U = *UI; 4394 4395 // This node is about to morph, remove its old self from the CSE maps. 4396 RemoveNodeFromCSEMaps(U); 4397 int operandNum = 0; 4398 for (SDNode::op_iterator I = U->op_begin(), E = U->op_end(); 4399 I != E; ++I, ++operandNum) 4400 if (I->getVal() == From) { 4401 From->removeUser(operandNum, U); 4402 *I = To; 4403 I->setUser(U); 4404 To.getNode()->addUser(operandNum, U); 4405 } 4406 4407 // Now that we have modified U, add it back to the CSE maps. If it already 4408 // exists there, recursively merge the results together. 4409 if (SDNode *Existing = AddNonLeafNodeToCSEMaps(U)) { 4410 ReplaceAllUsesWith(U, Existing, UpdateListener); 4411 // U is now dead. Inform the listener if it exists and delete it. 4412 if (UpdateListener) 4413 UpdateListener->NodeDeleted(U, Existing); 4414 DeleteNodeNotInCSEMaps(U); 4415 } else { 4416 // If the node doesn't already exist, we updated it. Inform a listener if 4417 // it exists. 4418 if (UpdateListener) 4419 UpdateListener->NodeUpdated(U); 4420 } 4421 } 4422} 4423 4424/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. 4425/// This can cause recursive merging of nodes in the DAG. 4426/// 4427/// This version assumes From/To have matching types and numbers of result 4428/// values. 4429/// 4430void SelectionDAG::ReplaceAllUsesWith(SDNode *From, SDNode *To, 4431 DAGUpdateListener *UpdateListener) { 4432 assert(From->getVTList().VTs == To->getVTList().VTs && 4433 From->getNumValues() == To->getNumValues() && 4434 "Cannot use this version of ReplaceAllUsesWith!"); 4435 4436 // Handle the trivial case. 4437 if (From == To) 4438 return; 4439 4440 while (!From->use_empty()) { 4441 SDNode::use_iterator UI = From->use_begin(); 4442 SDNode *U = *UI; 4443 4444 // This node is about to morph, remove its old self from the CSE maps. 4445 RemoveNodeFromCSEMaps(U); 4446 int operandNum = 0; 4447 for (SDNode::op_iterator I = U->op_begin(), E = U->op_end(); 4448 I != E; ++I, ++operandNum) 4449 if (I->getVal() == From) { 4450 From->removeUser(operandNum, U); 4451 I->getSDValue().setNode(To); 4452 To->addUser(operandNum, U); 4453 } 4454 4455 // Now that we have modified U, add it back to the CSE maps. If it already 4456 // exists there, recursively merge the results together. 4457 if (SDNode *Existing = AddNonLeafNodeToCSEMaps(U)) { 4458 ReplaceAllUsesWith(U, Existing, UpdateListener); 4459 // U is now dead. Inform the listener if it exists and delete it. 4460 if (UpdateListener) 4461 UpdateListener->NodeDeleted(U, Existing); 4462 DeleteNodeNotInCSEMaps(U); 4463 } else { 4464 // If the node doesn't already exist, we updated it. Inform a listener if 4465 // it exists. 4466 if (UpdateListener) 4467 UpdateListener->NodeUpdated(U); 4468 } 4469 } 4470} 4471 4472/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. 4473/// This can cause recursive merging of nodes in the DAG. 4474/// 4475/// This version can replace From with any result values. To must match the 4476/// number and types of values returned by From. 4477void SelectionDAG::ReplaceAllUsesWith(SDNode *From, 4478 const SDValue *To, 4479 DAGUpdateListener *UpdateListener) { 4480 if (From->getNumValues() == 1) // Handle the simple case efficiently. 4481 return ReplaceAllUsesWith(SDValue(From, 0), To[0], UpdateListener); 4482 4483 while (!From->use_empty()) { 4484 SDNode::use_iterator UI = From->use_begin(); 4485 SDNode *U = *UI; 4486 4487 // This node is about to morph, remove its old self from the CSE maps. 4488 RemoveNodeFromCSEMaps(U); 4489 int operandNum = 0; 4490 for (SDNode::op_iterator I = U->op_begin(), E = U->op_end(); 4491 I != E; ++I, ++operandNum) 4492 if (I->getVal() == From) { 4493 const SDValue &ToOp = To[I->getSDValue().getResNo()]; 4494 From->removeUser(operandNum, U); 4495 *I = ToOp; 4496 I->setUser(U); 4497 ToOp.getNode()->addUser(operandNum, U); 4498 } 4499 4500 // Now that we have modified U, add it back to the CSE maps. If it already 4501 // exists there, recursively merge the results together. 4502 if (SDNode *Existing = AddNonLeafNodeToCSEMaps(U)) { 4503 ReplaceAllUsesWith(U, Existing, UpdateListener); 4504 // U is now dead. Inform the listener if it exists and delete it. 4505 if (UpdateListener) 4506 UpdateListener->NodeDeleted(U, Existing); 4507 DeleteNodeNotInCSEMaps(U); 4508 } else { 4509 // If the node doesn't already exist, we updated it. Inform a listener if 4510 // it exists. 4511 if (UpdateListener) 4512 UpdateListener->NodeUpdated(U); 4513 } 4514 } 4515} 4516 4517/// ReplaceAllUsesOfValueWith - Replace any uses of From with To, leaving 4518/// uses of other values produced by From.getVal() alone. The Deleted vector is 4519/// handled the same way as for ReplaceAllUsesWith. 4520void SelectionDAG::ReplaceAllUsesOfValueWith(SDValue From, SDValue To, 4521 DAGUpdateListener *UpdateListener){ 4522 // Handle the really simple, really trivial case efficiently. 4523 if (From == To) return; 4524 4525 // Handle the simple, trivial, case efficiently. 4526 if (From.getNode()->getNumValues() == 1) { 4527 ReplaceAllUsesWith(From, To, UpdateListener); 4528 return; 4529 } 4530 4531 // Get all of the users of From.getNode(). We want these in a nice, 4532 // deterministically ordered and uniqued set, so we use a SmallSetVector. 4533 SmallSetVector<SDNode*, 16> Users(From.getNode()->use_begin(), From.getNode()->use_end()); 4534 4535 while (!Users.empty()) { 4536 // We know that this user uses some value of From. If it is the right 4537 // value, update it. 4538 SDNode *User = Users.back(); 4539 Users.pop_back(); 4540 4541 // Scan for an operand that matches From. 4542 SDNode::op_iterator Op = User->op_begin(), E = User->op_end(); 4543 for (; Op != E; ++Op) 4544 if (*Op == From) break; 4545 4546 // If there are no matches, the user must use some other result of From. 4547 if (Op == E) continue; 4548 4549 // Okay, we know this user needs to be updated. Remove its old self 4550 // from the CSE maps. 4551 RemoveNodeFromCSEMaps(User); 4552 4553 // Update all operands that match "From" in case there are multiple uses. 4554 for (; Op != E; ++Op) { 4555 if (*Op == From) { 4556 From.getNode()->removeUser(Op-User->op_begin(), User); 4557 *Op = To; 4558 Op->setUser(User); 4559 To.getNode()->addUser(Op-User->op_begin(), User); 4560 } 4561 } 4562 4563 // Now that we have modified User, add it back to the CSE maps. If it 4564 // already exists there, recursively merge the results together. 4565 SDNode *Existing = AddNonLeafNodeToCSEMaps(User); 4566 if (!Existing) { 4567 if (UpdateListener) UpdateListener->NodeUpdated(User); 4568 continue; // Continue on to next user. 4569 } 4570 4571 // If there was already an existing matching node, use ReplaceAllUsesWith 4572 // to replace the dead one with the existing one. This can cause 4573 // recursive merging of other unrelated nodes down the line. 4574 ReplaceAllUsesWith(User, Existing, UpdateListener); 4575 4576 // User is now dead. Notify a listener if present. 4577 if (UpdateListener) UpdateListener->NodeDeleted(User, Existing); 4578 DeleteNodeNotInCSEMaps(User); 4579 } 4580} 4581 4582/// ReplaceAllUsesOfValuesWith - Replace any uses of From with To, leaving 4583/// uses of other values produced by From.getVal() alone. The same value may 4584/// appear in both the From and To list. The Deleted vector is 4585/// handled the same way as for ReplaceAllUsesWith. 4586void SelectionDAG::ReplaceAllUsesOfValuesWith(const SDValue *From, 4587 const SDValue *To, 4588 unsigned Num, 4589 DAGUpdateListener *UpdateListener){ 4590 // Handle the simple, trivial case efficiently. 4591 if (Num == 1) 4592 return ReplaceAllUsesOfValueWith(*From, *To, UpdateListener); 4593 4594 SmallVector<std::pair<SDNode *, unsigned>, 16> Users; 4595 for (unsigned i = 0; i != Num; ++i) 4596 for (SDNode::use_iterator UI = From[i].getNode()->use_begin(), 4597 E = From[i].getNode()->use_end(); UI != E; ++UI) 4598 Users.push_back(std::make_pair(*UI, i)); 4599 4600 while (!Users.empty()) { 4601 // We know that this user uses some value of From. If it is the right 4602 // value, update it. 4603 SDNode *User = Users.back().first; 4604 unsigned i = Users.back().second; 4605 Users.pop_back(); 4606 4607 // Scan for an operand that matches From. 4608 SDNode::op_iterator Op = User->op_begin(), E = User->op_end(); 4609 for (; Op != E; ++Op) 4610 if (*Op == From[i]) break; 4611 4612 // If there are no matches, the user must use some other result of From. 4613 if (Op == E) continue; 4614 4615 // Okay, we know this user needs to be updated. Remove its old self 4616 // from the CSE maps. 4617 RemoveNodeFromCSEMaps(User); 4618 4619 // Update all operands that match "From" in case there are multiple uses. 4620 for (; Op != E; ++Op) { 4621 if (*Op == From[i]) { 4622 From[i].getNode()->removeUser(Op-User->op_begin(), User); 4623 *Op = To[i]; 4624 Op->setUser(User); 4625 To[i].getNode()->addUser(Op-User->op_begin(), User); 4626 } 4627 } 4628 4629 // Now that we have modified User, add it back to the CSE maps. If it 4630 // already exists there, recursively merge the results together. 4631 SDNode *Existing = AddNonLeafNodeToCSEMaps(User); 4632 if (!Existing) { 4633 if (UpdateListener) UpdateListener->NodeUpdated(User); 4634 continue; // Continue on to next user. 4635 } 4636 4637 // If there was already an existing matching node, use ReplaceAllUsesWith 4638 // to replace the dead one with the existing one. This can cause 4639 // recursive merging of other unrelated nodes down the line. 4640 ReplaceAllUsesWith(User, Existing, UpdateListener); 4641 4642 // User is now dead. Notify a listener if present. 4643 if (UpdateListener) UpdateListener->NodeDeleted(User, Existing); 4644 DeleteNodeNotInCSEMaps(User); 4645 } 4646} 4647 4648/// AssignTopologicalOrder - Assign a unique node id for each node in the DAG 4649/// based on their topological order. It returns the maximum id and a vector 4650/// of the SDNodes* in assigned order by reference. 4651unsigned SelectionDAG::AssignTopologicalOrder() { 4652 4653 unsigned DAGSize = 0; 4654 4655 // SortedPos tracks the progress of the algorithm. Nodes before it are 4656 // sorted, nodes after it are unsorted. When the algorithm completes 4657 // it is at the end of the list. 4658 allnodes_iterator SortedPos = allnodes_begin(); 4659 4660 // Visit all the nodes. Move nodes with no operands to the front of 4661 // the list immediately. Annotate nodes that do have operands with their 4662 // operand count. Before we do this, the Node Id fields of the nodes 4663 // may contain arbitrary values. After, the Node Id fields for nodes 4664 // before SortedPos will contain the topological sort index, and the 4665 // Node Id fields for nodes At SortedPos and after will contain the 4666 // count of outstanding operands. 4667 for (allnodes_iterator I = allnodes_begin(),E = allnodes_end(); I != E; ) { 4668 SDNode *N = I++; 4669 unsigned Degree = N->getNumOperands(); 4670 if (Degree == 0) { 4671 // A node with no uses, add it to the result array immediately. 4672 N->setNodeId(DAGSize++); 4673 allnodes_iterator Q = N; 4674 if (Q != SortedPos) 4675 SortedPos = AllNodes.insert(SortedPos, AllNodes.remove(Q)); 4676 ++SortedPos; 4677 } else { 4678 // Temporarily use the Node Id as scratch space for the degree count. 4679 N->setNodeId(Degree); 4680 } 4681 } 4682 4683 // Visit all the nodes. As we iterate, moves nodes into sorted order, 4684 // such that by the time the end is reached all nodes will be sorted. 4685 for (allnodes_iterator I = allnodes_begin(),E = allnodes_end(); I != E; ++I) { 4686 SDNode *N = I; 4687 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 4688 UI != UE; ++UI) { 4689 SDNode *P = *UI; 4690 unsigned Degree = P->getNodeId(); 4691 --Degree; 4692 if (Degree == 0) { 4693 // All of P's operands are sorted, so P may sorted now. 4694 P->setNodeId(DAGSize++); 4695 if (P != SortedPos) 4696 SortedPos = AllNodes.insert(SortedPos, AllNodes.remove(P)); 4697 ++SortedPos; 4698 } else { 4699 // Update P's outstanding operand count. 4700 P->setNodeId(Degree); 4701 } 4702 } 4703 } 4704 4705 assert(SortedPos == AllNodes.end() && 4706 "Topological sort incomplete!"); 4707 assert(AllNodes.front().getOpcode() == ISD::EntryToken && 4708 "First node in topological sort is not the entry token!"); 4709 assert(AllNodes.front().getNodeId() == 0 && 4710 "First node in topological sort has non-zero id!"); 4711 assert(AllNodes.front().getNumOperands() == 0 && 4712 "First node in topological sort has operands!"); 4713 assert(AllNodes.back().getNodeId() == (int)DAGSize-1 && 4714 "Last node in topologic sort has unexpected id!"); 4715 assert(AllNodes.back().use_empty() && 4716 "Last node in topologic sort has users!"); 4717 assert(DAGSize == allnodes_size() && "Node count mismatch!"); 4718 return DAGSize; 4719} 4720 4721 4722 4723//===----------------------------------------------------------------------===// 4724// SDNode Class 4725//===----------------------------------------------------------------------===// 4726 4727// Out-of-line virtual method to give class a home. 4728void SDNode::ANCHOR() {} 4729void UnarySDNode::ANCHOR() {} 4730void BinarySDNode::ANCHOR() {} 4731void TernarySDNode::ANCHOR() {} 4732void HandleSDNode::ANCHOR() {} 4733void ConstantSDNode::ANCHOR() {} 4734void ConstantFPSDNode::ANCHOR() {} 4735void GlobalAddressSDNode::ANCHOR() {} 4736void FrameIndexSDNode::ANCHOR() {} 4737void JumpTableSDNode::ANCHOR() {} 4738void ConstantPoolSDNode::ANCHOR() {} 4739void BasicBlockSDNode::ANCHOR() {} 4740void SrcValueSDNode::ANCHOR() {} 4741void MemOperandSDNode::ANCHOR() {} 4742void RegisterSDNode::ANCHOR() {} 4743void DbgStopPointSDNode::ANCHOR() {} 4744void LabelSDNode::ANCHOR() {} 4745void ExternalSymbolSDNode::ANCHOR() {} 4746void CondCodeSDNode::ANCHOR() {} 4747void ARG_FLAGSSDNode::ANCHOR() {} 4748void VTSDNode::ANCHOR() {} 4749void MemSDNode::ANCHOR() {} 4750void LoadSDNode::ANCHOR() {} 4751void StoreSDNode::ANCHOR() {} 4752void AtomicSDNode::ANCHOR() {} 4753void MemIntrinsicSDNode::ANCHOR() {} 4754void CallSDNode::ANCHOR() {} 4755void CvtRndSatSDNode::ANCHOR() {} 4756 4757HandleSDNode::~HandleSDNode() { 4758 DropOperands(); 4759} 4760 4761GlobalAddressSDNode::GlobalAddressSDNode(bool isTarget, const GlobalValue *GA, 4762 MVT VT, int64_t o) 4763 : SDNode(isa<GlobalVariable>(GA) && 4764 cast<GlobalVariable>(GA)->isThreadLocal() ? 4765 // Thread Local 4766 (isTarget ? ISD::TargetGlobalTLSAddress : ISD::GlobalTLSAddress) : 4767 // Non Thread Local 4768 (isTarget ? ISD::TargetGlobalAddress : ISD::GlobalAddress), 4769 getSDVTList(VT)), Offset(o) { 4770 TheGlobal = const_cast<GlobalValue*>(GA); 4771} 4772 4773MemSDNode::MemSDNode(unsigned Opc, SDVTList VTs, MVT memvt, 4774 const Value *srcValue, int SVO, 4775 unsigned alignment, bool vol) 4776 : SDNode(Opc, VTs), MemoryVT(memvt), SrcValue(srcValue), SVOffset(SVO), 4777 Flags(encodeMemSDNodeFlags(vol, alignment)) { 4778 4779 assert(isPowerOf2_32(alignment) && "Alignment is not a power of 2!"); 4780 assert(getAlignment() == alignment && "Alignment representation error!"); 4781 assert(isVolatile() == vol && "Volatile representation error!"); 4782} 4783 4784MemSDNode::MemSDNode(unsigned Opc, SDVTList VTs, const SDValue *Ops, 4785 unsigned NumOps, MVT memvt, const Value *srcValue, 4786 int SVO, unsigned alignment, bool vol) 4787 : SDNode(Opc, VTs, Ops, NumOps), 4788 MemoryVT(memvt), SrcValue(srcValue), SVOffset(SVO), 4789 Flags(vol | ((Log2_32(alignment) + 1) << 1)) { 4790 assert(isPowerOf2_32(alignment) && "Alignment is not a power of 2!"); 4791 assert(getAlignment() == alignment && "Alignment representation error!"); 4792 assert(isVolatile() == vol && "Volatile representation error!"); 4793} 4794 4795/// getMemOperand - Return a MachineMemOperand object describing the memory 4796/// reference performed by this memory reference. 4797MachineMemOperand MemSDNode::getMemOperand() const { 4798 int Flags = 0; 4799 if (isa<LoadSDNode>(this)) 4800 Flags = MachineMemOperand::MOLoad; 4801 else if (isa<StoreSDNode>(this)) 4802 Flags = MachineMemOperand::MOStore; 4803 else if (isa<AtomicSDNode>(this)) { 4804 Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore; 4805 } 4806 else { 4807 const MemIntrinsicSDNode* MemIntrinNode = dyn_cast<MemIntrinsicSDNode>(this); 4808 assert(MemIntrinNode && "Unknown MemSDNode opcode!"); 4809 if (MemIntrinNode->readMem()) Flags |= MachineMemOperand::MOLoad; 4810 if (MemIntrinNode->writeMem()) Flags |= MachineMemOperand::MOStore; 4811 } 4812 4813 int Size = (getMemoryVT().getSizeInBits() + 7) >> 3; 4814 if (isVolatile()) Flags |= MachineMemOperand::MOVolatile; 4815 4816 // Check if the memory reference references a frame index 4817 const FrameIndexSDNode *FI = 4818 dyn_cast<const FrameIndexSDNode>(getBasePtr().getNode()); 4819 if (!getSrcValue() && FI) 4820 return MachineMemOperand(PseudoSourceValue::getFixedStack(FI->getIndex()), 4821 Flags, 0, Size, getAlignment()); 4822 else 4823 return MachineMemOperand(getSrcValue(), Flags, getSrcValueOffset(), 4824 Size, getAlignment()); 4825} 4826 4827/// Profile - Gather unique data for the node. 4828/// 4829void SDNode::Profile(FoldingSetNodeID &ID) const { 4830 AddNodeIDNode(ID, this); 4831} 4832 4833/// getValueTypeList - Return a pointer to the specified value type. 4834/// 4835const MVT *SDNode::getValueTypeList(MVT VT) { 4836 if (VT.isExtended()) { 4837 static std::set<MVT, MVT::compareRawBits> EVTs; 4838 return &(*EVTs.insert(VT).first); 4839 } else { 4840 static MVT VTs[MVT::LAST_VALUETYPE]; 4841 VTs[VT.getSimpleVT()] = VT; 4842 return &VTs[VT.getSimpleVT()]; 4843 } 4844} 4845 4846/// hasNUsesOfValue - Return true if there are exactly NUSES uses of the 4847/// indicated value. This method ignores uses of other values defined by this 4848/// operation. 4849bool SDNode::hasNUsesOfValue(unsigned NUses, unsigned Value) const { 4850 assert(Value < getNumValues() && "Bad value!"); 4851 4852 // TODO: Only iterate over uses of a given value of the node 4853 for (SDNode::use_iterator UI = use_begin(), E = use_end(); UI != E; ++UI) { 4854 if (UI.getUse().getSDValue().getResNo() == Value) { 4855 if (NUses == 0) 4856 return false; 4857 --NUses; 4858 } 4859 } 4860 4861 // Found exactly the right number of uses? 4862 return NUses == 0; 4863} 4864 4865 4866/// hasAnyUseOfValue - Return true if there are any use of the indicated 4867/// value. This method ignores uses of other values defined by this operation. 4868bool SDNode::hasAnyUseOfValue(unsigned Value) const { 4869 assert(Value < getNumValues() && "Bad value!"); 4870 4871 for (SDNode::use_iterator UI = use_begin(), E = use_end(); UI != E; ++UI) 4872 if (UI.getUse().getSDValue().getResNo() == Value) 4873 return true; 4874 4875 return false; 4876} 4877 4878 4879/// isOnlyUserOf - Return true if this node is the only use of N. 4880/// 4881bool SDNode::isOnlyUserOf(SDNode *N) const { 4882 bool Seen = false; 4883 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 4884 SDNode *User = *I; 4885 if (User == this) 4886 Seen = true; 4887 else 4888 return false; 4889 } 4890 4891 return Seen; 4892} 4893 4894/// isOperand - Return true if this node is an operand of N. 4895/// 4896bool SDValue::isOperandOf(SDNode *N) const { 4897 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 4898 if (*this == N->getOperand(i)) 4899 return true; 4900 return false; 4901} 4902 4903bool SDNode::isOperandOf(SDNode *N) const { 4904 for (unsigned i = 0, e = N->NumOperands; i != e; ++i) 4905 if (this == N->OperandList[i].getVal()) 4906 return true; 4907 return false; 4908} 4909 4910/// reachesChainWithoutSideEffects - Return true if this operand (which must 4911/// be a chain) reaches the specified operand without crossing any 4912/// side-effecting instructions. In practice, this looks through token 4913/// factors and non-volatile loads. In order to remain efficient, this only 4914/// looks a couple of nodes in, it does not do an exhaustive search. 4915bool SDValue::reachesChainWithoutSideEffects(SDValue Dest, 4916 unsigned Depth) const { 4917 if (*this == Dest) return true; 4918 4919 // Don't search too deeply, we just want to be able to see through 4920 // TokenFactor's etc. 4921 if (Depth == 0) return false; 4922 4923 // If this is a token factor, all inputs to the TF happen in parallel. If any 4924 // of the operands of the TF reach dest, then we can do the xform. 4925 if (getOpcode() == ISD::TokenFactor) { 4926 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) 4927 if (getOperand(i).reachesChainWithoutSideEffects(Dest, Depth-1)) 4928 return true; 4929 return false; 4930 } 4931 4932 // Loads don't have side effects, look through them. 4933 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(*this)) { 4934 if (!Ld->isVolatile()) 4935 return Ld->getChain().reachesChainWithoutSideEffects(Dest, Depth-1); 4936 } 4937 return false; 4938} 4939 4940 4941static void findPredecessor(SDNode *N, const SDNode *P, bool &found, 4942 SmallPtrSet<SDNode *, 32> &Visited) { 4943 if (found || !Visited.insert(N)) 4944 return; 4945 4946 for (unsigned i = 0, e = N->getNumOperands(); !found && i != e; ++i) { 4947 SDNode *Op = N->getOperand(i).getNode(); 4948 if (Op == P) { 4949 found = true; 4950 return; 4951 } 4952 findPredecessor(Op, P, found, Visited); 4953 } 4954} 4955 4956/// isPredecessorOf - Return true if this node is a predecessor of N. This node 4957/// is either an operand of N or it can be reached by recursively traversing 4958/// up the operands. 4959/// NOTE: this is an expensive method. Use it carefully. 4960bool SDNode::isPredecessorOf(SDNode *N) const { 4961 SmallPtrSet<SDNode *, 32> Visited; 4962 bool found = false; 4963 findPredecessor(N, this, found, Visited); 4964 return found; 4965} 4966 4967uint64_t SDNode::getConstantOperandVal(unsigned Num) const { 4968 assert(Num < NumOperands && "Invalid child # of SDNode!"); 4969 return cast<ConstantSDNode>(OperandList[Num])->getZExtValue(); 4970} 4971 4972std::string SDNode::getOperationName(const SelectionDAG *G) const { 4973 switch (getOpcode()) { 4974 default: 4975 if (getOpcode() < ISD::BUILTIN_OP_END) 4976 return "<<Unknown DAG Node>>"; 4977 if (isMachineOpcode()) { 4978 if (G) 4979 if (const TargetInstrInfo *TII = G->getTarget().getInstrInfo()) 4980 if (getMachineOpcode() < TII->getNumOpcodes()) 4981 return TII->get(getMachineOpcode()).getName(); 4982 return "<<Unknown Machine Node>>"; 4983 } 4984 if (G) { 4985 TargetLowering &TLI = G->getTargetLoweringInfo(); 4986 const char *Name = TLI.getTargetNodeName(getOpcode()); 4987 if (Name) return Name; 4988 return "<<Unknown Target Node>>"; 4989 } 4990 return "<<Unknown Node>>"; 4991 4992#ifndef NDEBUG 4993 case ISD::DELETED_NODE: 4994 return "<<Deleted Node!>>"; 4995#endif 4996 case ISD::PREFETCH: return "Prefetch"; 4997 case ISD::MEMBARRIER: return "MemBarrier"; 4998 case ISD::ATOMIC_CMP_SWAP_8: return "AtomicCmpSwap8"; 4999 case ISD::ATOMIC_SWAP_8: return "AtomicSwap8"; 5000 case ISD::ATOMIC_LOAD_ADD_8: return "AtomicLoadAdd8"; 5001 case ISD::ATOMIC_LOAD_SUB_8: return "AtomicLoadSub8"; 5002 case ISD::ATOMIC_LOAD_AND_8: return "AtomicLoadAnd8"; 5003 case ISD::ATOMIC_LOAD_OR_8: return "AtomicLoadOr8"; 5004 case ISD::ATOMIC_LOAD_XOR_8: return "AtomicLoadXor8"; 5005 case ISD::ATOMIC_LOAD_NAND_8: return "AtomicLoadNand8"; 5006 case ISD::ATOMIC_LOAD_MIN_8: return "AtomicLoadMin8"; 5007 case ISD::ATOMIC_LOAD_MAX_8: return "AtomicLoadMax8"; 5008 case ISD::ATOMIC_LOAD_UMIN_8: return "AtomicLoadUMin8"; 5009 case ISD::ATOMIC_LOAD_UMAX_8: return "AtomicLoadUMax8"; 5010 case ISD::ATOMIC_CMP_SWAP_16: return "AtomicCmpSwap16"; 5011 case ISD::ATOMIC_SWAP_16: return "AtomicSwap16"; 5012 case ISD::ATOMIC_LOAD_ADD_16: return "AtomicLoadAdd16"; 5013 case ISD::ATOMIC_LOAD_SUB_16: return "AtomicLoadSub16"; 5014 case ISD::ATOMIC_LOAD_AND_16: return "AtomicLoadAnd16"; 5015 case ISD::ATOMIC_LOAD_OR_16: return "AtomicLoadOr16"; 5016 case ISD::ATOMIC_LOAD_XOR_16: return "AtomicLoadXor16"; 5017 case ISD::ATOMIC_LOAD_NAND_16: return "AtomicLoadNand16"; 5018 case ISD::ATOMIC_LOAD_MIN_16: return "AtomicLoadMin16"; 5019 case ISD::ATOMIC_LOAD_MAX_16: return "AtomicLoadMax16"; 5020 case ISD::ATOMIC_LOAD_UMIN_16: return "AtomicLoadUMin16"; 5021 case ISD::ATOMIC_LOAD_UMAX_16: return "AtomicLoadUMax16"; 5022 case ISD::ATOMIC_CMP_SWAP_32: return "AtomicCmpSwap32"; 5023 case ISD::ATOMIC_SWAP_32: return "AtomicSwap32"; 5024 case ISD::ATOMIC_LOAD_ADD_32: return "AtomicLoadAdd32"; 5025 case ISD::ATOMIC_LOAD_SUB_32: return "AtomicLoadSub32"; 5026 case ISD::ATOMIC_LOAD_AND_32: return "AtomicLoadAnd32"; 5027 case ISD::ATOMIC_LOAD_OR_32: return "AtomicLoadOr32"; 5028 case ISD::ATOMIC_LOAD_XOR_32: return "AtomicLoadXor32"; 5029 case ISD::ATOMIC_LOAD_NAND_32: return "AtomicLoadNand32"; 5030 case ISD::ATOMIC_LOAD_MIN_32: return "AtomicLoadMin32"; 5031 case ISD::ATOMIC_LOAD_MAX_32: return "AtomicLoadMax32"; 5032 case ISD::ATOMIC_LOAD_UMIN_32: return "AtomicLoadUMin32"; 5033 case ISD::ATOMIC_LOAD_UMAX_32: return "AtomicLoadUMax32"; 5034 case ISD::ATOMIC_CMP_SWAP_64: return "AtomicCmpSwap64"; 5035 case ISD::ATOMIC_SWAP_64: return "AtomicSwap64"; 5036 case ISD::ATOMIC_LOAD_ADD_64: return "AtomicLoadAdd64"; 5037 case ISD::ATOMIC_LOAD_SUB_64: return "AtomicLoadSub64"; 5038 case ISD::ATOMIC_LOAD_AND_64: return "AtomicLoadAnd64"; 5039 case ISD::ATOMIC_LOAD_OR_64: return "AtomicLoadOr64"; 5040 case ISD::ATOMIC_LOAD_XOR_64: return "AtomicLoadXor64"; 5041 case ISD::ATOMIC_LOAD_NAND_64: return "AtomicLoadNand64"; 5042 case ISD::ATOMIC_LOAD_MIN_64: return "AtomicLoadMin64"; 5043 case ISD::ATOMIC_LOAD_MAX_64: return "AtomicLoadMax64"; 5044 case ISD::ATOMIC_LOAD_UMIN_64: return "AtomicLoadUMin64"; 5045 case ISD::ATOMIC_LOAD_UMAX_64: return "AtomicLoadUMax64"; 5046 case ISD::PCMARKER: return "PCMarker"; 5047 case ISD::READCYCLECOUNTER: return "ReadCycleCounter"; 5048 case ISD::SRCVALUE: return "SrcValue"; 5049 case ISD::MEMOPERAND: return "MemOperand"; 5050 case ISD::EntryToken: return "EntryToken"; 5051 case ISD::TokenFactor: return "TokenFactor"; 5052 case ISD::AssertSext: return "AssertSext"; 5053 case ISD::AssertZext: return "AssertZext"; 5054 5055 case ISD::BasicBlock: return "BasicBlock"; 5056 case ISD::ARG_FLAGS: return "ArgFlags"; 5057 case ISD::VALUETYPE: return "ValueType"; 5058 case ISD::Register: return "Register"; 5059 5060 case ISD::Constant: return "Constant"; 5061 case ISD::ConstantFP: return "ConstantFP"; 5062 case ISD::GlobalAddress: return "GlobalAddress"; 5063 case ISD::GlobalTLSAddress: return "GlobalTLSAddress"; 5064 case ISD::FrameIndex: return "FrameIndex"; 5065 case ISD::JumpTable: return "JumpTable"; 5066 case ISD::GLOBAL_OFFSET_TABLE: return "GLOBAL_OFFSET_TABLE"; 5067 case ISD::RETURNADDR: return "RETURNADDR"; 5068 case ISD::FRAMEADDR: return "FRAMEADDR"; 5069 case ISD::FRAME_TO_ARGS_OFFSET: return "FRAME_TO_ARGS_OFFSET"; 5070 case ISD::EXCEPTIONADDR: return "EXCEPTIONADDR"; 5071 case ISD::EHSELECTION: return "EHSELECTION"; 5072 case ISD::EH_RETURN: return "EH_RETURN"; 5073 case ISD::ConstantPool: return "ConstantPool"; 5074 case ISD::ExternalSymbol: return "ExternalSymbol"; 5075 case ISD::INTRINSIC_WO_CHAIN: { 5076 unsigned IID = cast<ConstantSDNode>(getOperand(0))->getZExtValue(); 5077 return Intrinsic::getName((Intrinsic::ID)IID); 5078 } 5079 case ISD::INTRINSIC_VOID: 5080 case ISD::INTRINSIC_W_CHAIN: { 5081 unsigned IID = cast<ConstantSDNode>(getOperand(1))->getZExtValue(); 5082 return Intrinsic::getName((Intrinsic::ID)IID); 5083 } 5084 5085 case ISD::BUILD_VECTOR: return "BUILD_VECTOR"; 5086 case ISD::TargetConstant: return "TargetConstant"; 5087 case ISD::TargetConstantFP:return "TargetConstantFP"; 5088 case ISD::TargetGlobalAddress: return "TargetGlobalAddress"; 5089 case ISD::TargetGlobalTLSAddress: return "TargetGlobalTLSAddress"; 5090 case ISD::TargetFrameIndex: return "TargetFrameIndex"; 5091 case ISD::TargetJumpTable: return "TargetJumpTable"; 5092 case ISD::TargetConstantPool: return "TargetConstantPool"; 5093 case ISD::TargetExternalSymbol: return "TargetExternalSymbol"; 5094 5095 case ISD::CopyToReg: return "CopyToReg"; 5096 case ISD::CopyFromReg: return "CopyFromReg"; 5097 case ISD::UNDEF: return "undef"; 5098 case ISD::MERGE_VALUES: return "merge_values"; 5099 case ISD::INLINEASM: return "inlineasm"; 5100 case ISD::DBG_LABEL: return "dbg_label"; 5101 case ISD::EH_LABEL: return "eh_label"; 5102 case ISD::DECLARE: return "declare"; 5103 case ISD::HANDLENODE: return "handlenode"; 5104 case ISD::FORMAL_ARGUMENTS: return "formal_arguments"; 5105 case ISD::CALL: return "call"; 5106 5107 // Unary operators 5108 case ISD::FABS: return "fabs"; 5109 case ISD::FNEG: return "fneg"; 5110 case ISD::FSQRT: return "fsqrt"; 5111 case ISD::FSIN: return "fsin"; 5112 case ISD::FCOS: return "fcos"; 5113 case ISD::FPOWI: return "fpowi"; 5114 case ISD::FPOW: return "fpow"; 5115 case ISD::FTRUNC: return "ftrunc"; 5116 case ISD::FFLOOR: return "ffloor"; 5117 case ISD::FCEIL: return "fceil"; 5118 case ISD::FRINT: return "frint"; 5119 case ISD::FNEARBYINT: return "fnearbyint"; 5120 5121 // Binary operators 5122 case ISD::ADD: return "add"; 5123 case ISD::SUB: return "sub"; 5124 case ISD::MUL: return "mul"; 5125 case ISD::MULHU: return "mulhu"; 5126 case ISD::MULHS: return "mulhs"; 5127 case ISD::SDIV: return "sdiv"; 5128 case ISD::UDIV: return "udiv"; 5129 case ISD::SREM: return "srem"; 5130 case ISD::UREM: return "urem"; 5131 case ISD::SMUL_LOHI: return "smul_lohi"; 5132 case ISD::UMUL_LOHI: return "umul_lohi"; 5133 case ISD::SDIVREM: return "sdivrem"; 5134 case ISD::UDIVREM: return "udivrem"; 5135 case ISD::AND: return "and"; 5136 case ISD::OR: return "or"; 5137 case ISD::XOR: return "xor"; 5138 case ISD::SHL: return "shl"; 5139 case ISD::SRA: return "sra"; 5140 case ISD::SRL: return "srl"; 5141 case ISD::ROTL: return "rotl"; 5142 case ISD::ROTR: return "rotr"; 5143 case ISD::FADD: return "fadd"; 5144 case ISD::FSUB: return "fsub"; 5145 case ISD::FMUL: return "fmul"; 5146 case ISD::FDIV: return "fdiv"; 5147 case ISD::FREM: return "frem"; 5148 case ISD::FCOPYSIGN: return "fcopysign"; 5149 case ISD::FGETSIGN: return "fgetsign"; 5150 5151 case ISD::SETCC: return "setcc"; 5152 case ISD::VSETCC: return "vsetcc"; 5153 case ISD::SELECT: return "select"; 5154 case ISD::SELECT_CC: return "select_cc"; 5155 case ISD::INSERT_VECTOR_ELT: return "insert_vector_elt"; 5156 case ISD::EXTRACT_VECTOR_ELT: return "extract_vector_elt"; 5157 case ISD::CONCAT_VECTORS: return "concat_vectors"; 5158 case ISD::EXTRACT_SUBVECTOR: return "extract_subvector"; 5159 case ISD::SCALAR_TO_VECTOR: return "scalar_to_vector"; 5160 case ISD::VECTOR_SHUFFLE: return "vector_shuffle"; 5161 case ISD::CARRY_FALSE: return "carry_false"; 5162 case ISD::ADDC: return "addc"; 5163 case ISD::ADDE: return "adde"; 5164 case ISD::SADDO: return "saddo"; 5165 case ISD::UADDO: return "uaddo"; 5166 case ISD::SUBC: return "subc"; 5167 case ISD::SUBE: return "sube"; 5168 case ISD::SHL_PARTS: return "shl_parts"; 5169 case ISD::SRA_PARTS: return "sra_parts"; 5170 case ISD::SRL_PARTS: return "srl_parts"; 5171 5172 case ISD::EXTRACT_SUBREG: return "extract_subreg"; 5173 case ISD::INSERT_SUBREG: return "insert_subreg"; 5174 5175 // Conversion operators. 5176 case ISD::SIGN_EXTEND: return "sign_extend"; 5177 case ISD::ZERO_EXTEND: return "zero_extend"; 5178 case ISD::ANY_EXTEND: return "any_extend"; 5179 case ISD::SIGN_EXTEND_INREG: return "sign_extend_inreg"; 5180 case ISD::TRUNCATE: return "truncate"; 5181 case ISD::FP_ROUND: return "fp_round"; 5182 case ISD::FLT_ROUNDS_: return "flt_rounds"; 5183 case ISD::FP_ROUND_INREG: return "fp_round_inreg"; 5184 case ISD::FP_EXTEND: return "fp_extend"; 5185 5186 case ISD::SINT_TO_FP: return "sint_to_fp"; 5187 case ISD::UINT_TO_FP: return "uint_to_fp"; 5188 case ISD::FP_TO_SINT: return "fp_to_sint"; 5189 case ISD::FP_TO_UINT: return "fp_to_uint"; 5190 case ISD::BIT_CONVERT: return "bit_convert"; 5191 5192 case ISD::CONVERT_RNDSAT: { 5193 switch (cast<CvtRndSatSDNode>(this)->getCvtCode()) { 5194 default: assert(0 && "Unknown cvt code!"); 5195 case ISD::CVT_FF: return "cvt_ff"; 5196 case ISD::CVT_FS: return "cvt_fs"; 5197 case ISD::CVT_FU: return "cvt_fu"; 5198 case ISD::CVT_SF: return "cvt_sf"; 5199 case ISD::CVT_UF: return "cvt_uf"; 5200 case ISD::CVT_SS: return "cvt_ss"; 5201 case ISD::CVT_SU: return "cvt_su"; 5202 case ISD::CVT_US: return "cvt_us"; 5203 case ISD::CVT_UU: return "cvt_uu"; 5204 } 5205 } 5206 5207 // Control flow instructions 5208 case ISD::BR: return "br"; 5209 case ISD::BRIND: return "brind"; 5210 case ISD::BR_JT: return "br_jt"; 5211 case ISD::BRCOND: return "brcond"; 5212 case ISD::BR_CC: return "br_cc"; 5213 case ISD::RET: return "ret"; 5214 case ISD::CALLSEQ_START: return "callseq_start"; 5215 case ISD::CALLSEQ_END: return "callseq_end"; 5216 5217 // Other operators 5218 case ISD::LOAD: return "load"; 5219 case ISD::STORE: return "store"; 5220 case ISD::VAARG: return "vaarg"; 5221 case ISD::VACOPY: return "vacopy"; 5222 case ISD::VAEND: return "vaend"; 5223 case ISD::VASTART: return "vastart"; 5224 case ISD::DYNAMIC_STACKALLOC: return "dynamic_stackalloc"; 5225 case ISD::EXTRACT_ELEMENT: return "extract_element"; 5226 case ISD::BUILD_PAIR: return "build_pair"; 5227 case ISD::STACKSAVE: return "stacksave"; 5228 case ISD::STACKRESTORE: return "stackrestore"; 5229 case ISD::TRAP: return "trap"; 5230 5231 // Bit manipulation 5232 case ISD::BSWAP: return "bswap"; 5233 case ISD::CTPOP: return "ctpop"; 5234 case ISD::CTTZ: return "cttz"; 5235 case ISD::CTLZ: return "ctlz"; 5236 5237 // Debug info 5238 case ISD::DBG_STOPPOINT: return "dbg_stoppoint"; 5239 case ISD::DEBUG_LOC: return "debug_loc"; 5240 5241 // Trampolines 5242 case ISD::TRAMPOLINE: return "trampoline"; 5243 5244 case ISD::CONDCODE: 5245 switch (cast<CondCodeSDNode>(this)->get()) { 5246 default: assert(0 && "Unknown setcc condition!"); 5247 case ISD::SETOEQ: return "setoeq"; 5248 case ISD::SETOGT: return "setogt"; 5249 case ISD::SETOGE: return "setoge"; 5250 case ISD::SETOLT: return "setolt"; 5251 case ISD::SETOLE: return "setole"; 5252 case ISD::SETONE: return "setone"; 5253 5254 case ISD::SETO: return "seto"; 5255 case ISD::SETUO: return "setuo"; 5256 case ISD::SETUEQ: return "setue"; 5257 case ISD::SETUGT: return "setugt"; 5258 case ISD::SETUGE: return "setuge"; 5259 case ISD::SETULT: return "setult"; 5260 case ISD::SETULE: return "setule"; 5261 case ISD::SETUNE: return "setune"; 5262 5263 case ISD::SETEQ: return "seteq"; 5264 case ISD::SETGT: return "setgt"; 5265 case ISD::SETGE: return "setge"; 5266 case ISD::SETLT: return "setlt"; 5267 case ISD::SETLE: return "setle"; 5268 case ISD::SETNE: return "setne"; 5269 } 5270 } 5271} 5272 5273const char *SDNode::getIndexedModeName(ISD::MemIndexedMode AM) { 5274 switch (AM) { 5275 default: 5276 return ""; 5277 case ISD::PRE_INC: 5278 return "<pre-inc>"; 5279 case ISD::PRE_DEC: 5280 return "<pre-dec>"; 5281 case ISD::POST_INC: 5282 return "<post-inc>"; 5283 case ISD::POST_DEC: 5284 return "<post-dec>"; 5285 } 5286} 5287 5288std::string ISD::ArgFlagsTy::getArgFlagsString() { 5289 std::string S = "< "; 5290 5291 if (isZExt()) 5292 S += "zext "; 5293 if (isSExt()) 5294 S += "sext "; 5295 if (isInReg()) 5296 S += "inreg "; 5297 if (isSRet()) 5298 S += "sret "; 5299 if (isByVal()) 5300 S += "byval "; 5301 if (isNest()) 5302 S += "nest "; 5303 if (getByValAlign()) 5304 S += "byval-align:" + utostr(getByValAlign()) + " "; 5305 if (getOrigAlign()) 5306 S += "orig-align:" + utostr(getOrigAlign()) + " "; 5307 if (getByValSize()) 5308 S += "byval-size:" + utostr(getByValSize()) + " "; 5309 return S + ">"; 5310} 5311 5312void SDNode::dump() const { dump(0); } 5313void SDNode::dump(const SelectionDAG *G) const { 5314 print(errs(), G); 5315 errs().flush(); 5316} 5317 5318void SDNode::print(raw_ostream &OS, const SelectionDAG *G) const { 5319 OS << (void*)this << ": "; 5320 5321 for (unsigned i = 0, e = getNumValues(); i != e; ++i) { 5322 if (i) OS << ","; 5323 if (getValueType(i) == MVT::Other) 5324 OS << "ch"; 5325 else 5326 OS << getValueType(i).getMVTString(); 5327 } 5328 OS << " = " << getOperationName(G); 5329 5330 OS << " "; 5331 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 5332 if (i) OS << ", "; 5333 OS << (void*)getOperand(i).getNode(); 5334 if (unsigned RN = getOperand(i).getResNo()) 5335 OS << ":" << RN; 5336 } 5337 5338 if (!isTargetOpcode() && getOpcode() == ISD::VECTOR_SHUFFLE) { 5339 SDNode *Mask = getOperand(2).getNode(); 5340 OS << "<"; 5341 for (unsigned i = 0, e = Mask->getNumOperands(); i != e; ++i) { 5342 if (i) OS << ","; 5343 if (Mask->getOperand(i).getOpcode() == ISD::UNDEF) 5344 OS << "u"; 5345 else 5346 OS << cast<ConstantSDNode>(Mask->getOperand(i))->getZExtValue(); 5347 } 5348 OS << ">"; 5349 } 5350 5351 if (const ConstantSDNode *CSDN = dyn_cast<ConstantSDNode>(this)) { 5352 OS << '<' << CSDN->getAPIntValue() << '>'; 5353 } else if (const ConstantFPSDNode *CSDN = dyn_cast<ConstantFPSDNode>(this)) { 5354 if (&CSDN->getValueAPF().getSemantics()==&APFloat::IEEEsingle) 5355 OS << '<' << CSDN->getValueAPF().convertToFloat() << '>'; 5356 else if (&CSDN->getValueAPF().getSemantics()==&APFloat::IEEEdouble) 5357 OS << '<' << CSDN->getValueAPF().convertToDouble() << '>'; 5358 else { 5359 OS << "<APFloat("; 5360 CSDN->getValueAPF().bitcastToAPInt().dump(); 5361 OS << ")>"; 5362 } 5363 } else if (const GlobalAddressSDNode *GADN = 5364 dyn_cast<GlobalAddressSDNode>(this)) { 5365 int64_t offset = GADN->getOffset(); 5366 OS << '<'; 5367 WriteAsOperand(OS, GADN->getGlobal()); 5368 OS << '>'; 5369 if (offset > 0) 5370 OS << " + " << offset; 5371 else 5372 OS << " " << offset; 5373 } else if (const FrameIndexSDNode *FIDN = dyn_cast<FrameIndexSDNode>(this)) { 5374 OS << "<" << FIDN->getIndex() << ">"; 5375 } else if (const JumpTableSDNode *JTDN = dyn_cast<JumpTableSDNode>(this)) { 5376 OS << "<" << JTDN->getIndex() << ">"; 5377 } else if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(this)){ 5378 int offset = CP->getOffset(); 5379 if (CP->isMachineConstantPoolEntry()) 5380 OS << "<" << *CP->getMachineCPVal() << ">"; 5381 else 5382 OS << "<" << *CP->getConstVal() << ">"; 5383 if (offset > 0) 5384 OS << " + " << offset; 5385 else 5386 OS << " " << offset; 5387 } else if (const BasicBlockSDNode *BBDN = dyn_cast<BasicBlockSDNode>(this)) { 5388 OS << "<"; 5389 const Value *LBB = (const Value*)BBDN->getBasicBlock()->getBasicBlock(); 5390 if (LBB) 5391 OS << LBB->getName() << " "; 5392 OS << (const void*)BBDN->getBasicBlock() << ">"; 5393 } else if (const RegisterSDNode *R = dyn_cast<RegisterSDNode>(this)) { 5394 if (G && R->getReg() && 5395 TargetRegisterInfo::isPhysicalRegister(R->getReg())) { 5396 OS << " " << G->getTarget().getRegisterInfo()->getName(R->getReg()); 5397 } else { 5398 OS << " #" << R->getReg(); 5399 } 5400 } else if (const ExternalSymbolSDNode *ES = 5401 dyn_cast<ExternalSymbolSDNode>(this)) { 5402 OS << "'" << ES->getSymbol() << "'"; 5403 } else if (const SrcValueSDNode *M = dyn_cast<SrcValueSDNode>(this)) { 5404 if (M->getValue()) 5405 OS << "<" << M->getValue() << ">"; 5406 else 5407 OS << "<null>"; 5408 } else if (const MemOperandSDNode *M = dyn_cast<MemOperandSDNode>(this)) { 5409 if (M->MO.getValue()) 5410 OS << "<" << M->MO.getValue() << ":" << M->MO.getOffset() << ">"; 5411 else 5412 OS << "<null:" << M->MO.getOffset() << ">"; 5413 } else if (const ARG_FLAGSSDNode *N = dyn_cast<ARG_FLAGSSDNode>(this)) { 5414 OS << N->getArgFlags().getArgFlagsString(); 5415 } else if (const VTSDNode *N = dyn_cast<VTSDNode>(this)) { 5416 OS << ":" << N->getVT().getMVTString(); 5417 } 5418 else if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(this)) { 5419 const Value *SrcValue = LD->getSrcValue(); 5420 int SrcOffset = LD->getSrcValueOffset(); 5421 OS << " <"; 5422 if (SrcValue) 5423 OS << SrcValue; 5424 else 5425 OS << "null"; 5426 OS << ":" << SrcOffset << ">"; 5427 5428 bool doExt = true; 5429 switch (LD->getExtensionType()) { 5430 default: doExt = false; break; 5431 case ISD::EXTLOAD: OS << " <anyext "; break; 5432 case ISD::SEXTLOAD: OS << " <sext "; break; 5433 case ISD::ZEXTLOAD: OS << " <zext "; break; 5434 } 5435 if (doExt) 5436 OS << LD->getMemoryVT().getMVTString() << ">"; 5437 5438 const char *AM = getIndexedModeName(LD->getAddressingMode()); 5439 if (*AM) 5440 OS << " " << AM; 5441 if (LD->isVolatile()) 5442 OS << " <volatile>"; 5443 OS << " alignment=" << LD->getAlignment(); 5444 } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(this)) { 5445 const Value *SrcValue = ST->getSrcValue(); 5446 int SrcOffset = ST->getSrcValueOffset(); 5447 OS << " <"; 5448 if (SrcValue) 5449 OS << SrcValue; 5450 else 5451 OS << "null"; 5452 OS << ":" << SrcOffset << ">"; 5453 5454 if (ST->isTruncatingStore()) 5455 OS << " <trunc " << ST->getMemoryVT().getMVTString() << ">"; 5456 5457 const char *AM = getIndexedModeName(ST->getAddressingMode()); 5458 if (*AM) 5459 OS << " " << AM; 5460 if (ST->isVolatile()) 5461 OS << " <volatile>"; 5462 OS << " alignment=" << ST->getAlignment(); 5463 } else if (const AtomicSDNode* AT = dyn_cast<AtomicSDNode>(this)) { 5464 const Value *SrcValue = AT->getSrcValue(); 5465 int SrcOffset = AT->getSrcValueOffset(); 5466 OS << " <"; 5467 if (SrcValue) 5468 OS << SrcValue; 5469 else 5470 OS << "null"; 5471 OS << ":" << SrcOffset << ">"; 5472 if (AT->isVolatile()) 5473 OS << " <volatile>"; 5474 OS << " alignment=" << AT->getAlignment(); 5475 } 5476} 5477 5478static void DumpNodes(const SDNode *N, unsigned indent, const SelectionDAG *G) { 5479 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 5480 if (N->getOperand(i).getNode()->hasOneUse()) 5481 DumpNodes(N->getOperand(i).getNode(), indent+2, G); 5482 else 5483 cerr << "\n" << std::string(indent+2, ' ') 5484 << (void*)N->getOperand(i).getNode() << ": <multiple use>"; 5485 5486 5487 cerr << "\n" << std::string(indent, ' '); 5488 N->dump(G); 5489} 5490 5491void SelectionDAG::dump() const { 5492 cerr << "SelectionDAG has " << AllNodes.size() << " nodes:"; 5493 5494 for (allnodes_const_iterator I = allnodes_begin(), E = allnodes_end(); 5495 I != E; ++I) { 5496 const SDNode *N = I; 5497 if (!N->hasOneUse() && N != getRoot().getNode()) 5498 DumpNodes(N, 2, this); 5499 } 5500 5501 if (getRoot().getNode()) DumpNodes(getRoot().getNode(), 2, this); 5502 5503 cerr << "\n\n"; 5504} 5505 5506const Type *ConstantPoolSDNode::getType() const { 5507 if (isMachineConstantPoolEntry()) 5508 return Val.MachineCPVal->getType(); 5509 return Val.ConstVal->getType(); 5510} 5511