SelectionDAG.cpp revision 0561b3ff9fd08f9cda48551f2f91590ca5f60656
1//===-- SelectionDAG.cpp - Implement the SelectionDAG data structures -----===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAG class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/Constants.h" 16#include "llvm/GlobalValue.h" 17#include "llvm/Assembly/Writer.h" 18#include "llvm/CodeGen/MachineBasicBlock.h" 19#include "llvm/Support/MathExtras.h" 20#include "llvm/Target/TargetLowering.h" 21#include <iostream> 22#include <set> 23#include <cmath> 24#include <algorithm> 25using namespace llvm; 26 27static bool isCommutativeBinOp(unsigned Opcode) { 28 switch (Opcode) { 29 case ISD::ADD: 30 case ISD::MUL: 31 case ISD::AND: 32 case ISD::OR: 33 case ISD::XOR: return true; 34 default: return false; // FIXME: Need commutative info for user ops! 35 } 36} 37 38static bool isAssociativeBinOp(unsigned Opcode) { 39 switch (Opcode) { 40 case ISD::ADD: 41 case ISD::MUL: 42 case ISD::AND: 43 case ISD::OR: 44 case ISD::XOR: return true; 45 default: return false; // FIXME: Need associative info for user ops! 46 } 47} 48 49// isInvertibleForFree - Return true if there is no cost to emitting the logical 50// inverse of this node. 51static bool isInvertibleForFree(SDOperand N) { 52 if (isa<ConstantSDNode>(N.Val)) return true; 53 if (isa<SetCCSDNode>(N.Val) && N.Val->hasOneUse()) 54 return true; 55 return false; 56} 57 58 59/// getSetCCSwappedOperands - Return the operation corresponding to (Y op X) 60/// when given the operation for (X op Y). 61ISD::CondCode ISD::getSetCCSwappedOperands(ISD::CondCode Operation) { 62 // To perform this operation, we just need to swap the L and G bits of the 63 // operation. 64 unsigned OldL = (Operation >> 2) & 1; 65 unsigned OldG = (Operation >> 1) & 1; 66 return ISD::CondCode((Operation & ~6) | // Keep the N, U, E bits 67 (OldL << 1) | // New G bit 68 (OldG << 2)); // New L bit. 69} 70 71/// getSetCCInverse - Return the operation corresponding to !(X op Y), where 72/// 'op' is a valid SetCC operation. 73ISD::CondCode ISD::getSetCCInverse(ISD::CondCode Op, bool isInteger) { 74 unsigned Operation = Op; 75 if (isInteger) 76 Operation ^= 7; // Flip L, G, E bits, but not U. 77 else 78 Operation ^= 15; // Flip all of the condition bits. 79 if (Operation > ISD::SETTRUE2) 80 Operation &= ~8; // Don't let N and U bits get set. 81 return ISD::CondCode(Operation); 82} 83 84 85/// isSignedOp - For an integer comparison, return 1 if the comparison is a 86/// signed operation and 2 if the result is an unsigned comparison. Return zero 87/// if the operation does not depend on the sign of the input (setne and seteq). 88static int isSignedOp(ISD::CondCode Opcode) { 89 switch (Opcode) { 90 default: assert(0 && "Illegal integer setcc operation!"); 91 case ISD::SETEQ: 92 case ISD::SETNE: return 0; 93 case ISD::SETLT: 94 case ISD::SETLE: 95 case ISD::SETGT: 96 case ISD::SETGE: return 1; 97 case ISD::SETULT: 98 case ISD::SETULE: 99 case ISD::SETUGT: 100 case ISD::SETUGE: return 2; 101 } 102} 103 104/// getSetCCOrOperation - Return the result of a logical OR between different 105/// comparisons of identical values: ((X op1 Y) | (X op2 Y)). This function 106/// returns SETCC_INVALID if it is not possible to represent the resultant 107/// comparison. 108ISD::CondCode ISD::getSetCCOrOperation(ISD::CondCode Op1, ISD::CondCode Op2, 109 bool isInteger) { 110 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 111 // Cannot fold a signed integer setcc with an unsigned integer setcc. 112 return ISD::SETCC_INVALID; 113 114 unsigned Op = Op1 | Op2; // Combine all of the condition bits. 115 116 // If the N and U bits get set then the resultant comparison DOES suddenly 117 // care about orderedness, and is true when ordered. 118 if (Op > ISD::SETTRUE2) 119 Op &= ~16; // Clear the N bit. 120 return ISD::CondCode(Op); 121} 122 123/// getSetCCAndOperation - Return the result of a logical AND between different 124/// comparisons of identical values: ((X op1 Y) & (X op2 Y)). This 125/// function returns zero if it is not possible to represent the resultant 126/// comparison. 127ISD::CondCode ISD::getSetCCAndOperation(ISD::CondCode Op1, ISD::CondCode Op2, 128 bool isInteger) { 129 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 130 // Cannot fold a signed setcc with an unsigned setcc. 131 return ISD::SETCC_INVALID; 132 133 // Combine all of the condition bits. 134 return ISD::CondCode(Op1 & Op2); 135} 136 137const TargetMachine &SelectionDAG::getTarget() const { 138 return TLI.getTargetMachine(); 139} 140 141 142/// RemoveDeadNodes - This method deletes all unreachable nodes in the 143/// SelectionDAG, including nodes (like loads) that have uses of their token 144/// chain but no other uses and no side effect. If a node is passed in as an 145/// argument, it is used as the seed for node deletion. 146void SelectionDAG::RemoveDeadNodes(SDNode *N) { 147 std::set<SDNode*> AllNodeSet(AllNodes.begin(), AllNodes.end()); 148 149 // Create a dummy node (which is not added to allnodes), that adds a reference 150 // to the root node, preventing it from being deleted. 151 SDNode *DummyNode = new SDNode(ISD::EntryToken, getRoot()); 152 153 DeleteNodeIfDead(N, &AllNodeSet); 154 155 Restart: 156 unsigned NumNodes = AllNodeSet.size(); 157 for (std::set<SDNode*>::iterator I = AllNodeSet.begin(), E = AllNodeSet.end(); 158 I != E; ++I) { 159 // Try to delete this node. 160 DeleteNodeIfDead(*I, &AllNodeSet); 161 162 // If we actually deleted any nodes, do not use invalid iterators in 163 // AllNodeSet. 164 if (AllNodeSet.size() != NumNodes) 165 goto Restart; 166 } 167 168 // Restore AllNodes. 169 if (AllNodes.size() != NumNodes) 170 AllNodes.assign(AllNodeSet.begin(), AllNodeSet.end()); 171 172 // If the root changed (e.g. it was a dead load, update the root). 173 setRoot(DummyNode->getOperand(0)); 174 175 // Now that we are done with the dummy node, delete it. 176 DummyNode->getOperand(0).Val->removeUser(DummyNode); 177 delete DummyNode; 178} 179 180void SelectionDAG::DeleteNodeIfDead(SDNode *N, void *NodeSet) { 181 if (!N->use_empty()) 182 return; 183 184 // Okay, we really are going to delete this node. First take this out of the 185 // appropriate CSE map. 186 switch (N->getOpcode()) { 187 case ISD::Constant: 188 Constants.erase(std::make_pair(cast<ConstantSDNode>(N)->getValue(), 189 N->getValueType(0))); 190 break; 191 case ISD::ConstantFP: { 192 union { 193 double DV; 194 uint64_t IV; 195 }; 196 DV = cast<ConstantFPSDNode>(N)->getValue(); 197 ConstantFPs.erase(std::make_pair(IV, N->getValueType(0))); 198 break; 199 } 200 case ISD::GlobalAddress: 201 GlobalValues.erase(cast<GlobalAddressSDNode>(N)->getGlobal()); 202 break; 203 case ISD::FrameIndex: 204 FrameIndices.erase(cast<FrameIndexSDNode>(N)->getIndex()); 205 break; 206 case ISD::ConstantPool: 207 ConstantPoolIndices.erase(cast<ConstantPoolSDNode>(N)->getIndex()); 208 break; 209 case ISD::BasicBlock: 210 BBNodes.erase(cast<BasicBlockSDNode>(N)->getBasicBlock()); 211 break; 212 case ISD::ExternalSymbol: 213 ExternalSymbols.erase(cast<ExternalSymbolSDNode>(N)->getSymbol()); 214 break; 215 case ISD::VALUETYPE: 216 ValueTypeNodes[cast<VTSDNode>(N)->getVT()] = 0; 217 break; 218 case ISD::LOAD: 219 Loads.erase(std::make_pair(N->getOperand(1), 220 std::make_pair(N->getOperand(0), 221 N->getValueType(0)))); 222 break; 223 case ISD::SETCC: 224 SetCCs.erase(std::make_pair(std::make_pair(N->getOperand(0), 225 N->getOperand(1)), 226 std::make_pair( 227 cast<SetCCSDNode>(N)->getCondition(), 228 N->getValueType(0)))); 229 break; 230 default: 231 if (N->getNumOperands() == 1) 232 UnaryOps.erase(std::make_pair(N->getOpcode(), 233 std::make_pair(N->getOperand(0), 234 N->getValueType(0)))); 235 else if (N->getNumOperands() == 2) 236 BinaryOps.erase(std::make_pair(N->getOpcode(), 237 std::make_pair(N->getOperand(0), 238 N->getOperand(1)))); 239 else if (N->getNumValues() == 1) { 240 std::vector<SDOperand> Ops(N->op_begin(), N->op_end()); 241 OneResultNodes.erase(std::make_pair(N->getOpcode(), 242 std::make_pair(N->getValueType(0), 243 Ops))); 244 } else { 245 // Remove the node from the ArbitraryNodes map. 246 std::vector<MVT::ValueType> RV(N->value_begin(), N->value_end()); 247 std::vector<SDOperand> Ops(N->op_begin(), N->op_end()); 248 ArbitraryNodes.erase(std::make_pair(N->getOpcode(), 249 std::make_pair(RV, Ops))); 250 } 251 break; 252 } 253 254 // Next, brutally remove the operand list. 255 while (!N->Operands.empty()) { 256 SDNode *O = N->Operands.back().Val; 257 N->Operands.pop_back(); 258 O->removeUser(N); 259 260 // Now that we removed this operand, see if there are no uses of it left. 261 DeleteNodeIfDead(O, NodeSet); 262 } 263 264 // Remove the node from the nodes set and delete it. 265 std::set<SDNode*> &AllNodeSet = *(std::set<SDNode*>*)NodeSet; 266 AllNodeSet.erase(N); 267 268 // Now that the node is gone, check to see if any of the operands of this node 269 // are dead now. 270 delete N; 271} 272 273 274SelectionDAG::~SelectionDAG() { 275 for (unsigned i = 0, e = AllNodes.size(); i != e; ++i) 276 delete AllNodes[i]; 277} 278 279SDOperand SelectionDAG::getZeroExtendInReg(SDOperand Op, MVT::ValueType VT) { 280 if (Op.getValueType() == VT) return Op; 281 int64_t Imm = ~0ULL >> (64-MVT::getSizeInBits(VT)); 282 return getNode(ISD::AND, Op.getValueType(), Op, 283 getConstant(Imm, Op.getValueType())); 284} 285 286SDOperand SelectionDAG::getConstant(uint64_t Val, MVT::ValueType VT) { 287 assert(MVT::isInteger(VT) && "Cannot create FP integer constant!"); 288 // Mask out any bits that are not valid for this constant. 289 if (VT != MVT::i64) 290 Val &= ((uint64_t)1 << MVT::getSizeInBits(VT)) - 1; 291 292 SDNode *&N = Constants[std::make_pair(Val, VT)]; 293 if (N) return SDOperand(N, 0); 294 N = new ConstantSDNode(Val, VT); 295 AllNodes.push_back(N); 296 return SDOperand(N, 0); 297} 298 299SDOperand SelectionDAG::getConstantFP(double Val, MVT::ValueType VT) { 300 assert(MVT::isFloatingPoint(VT) && "Cannot create integer FP constant!"); 301 if (VT == MVT::f32) 302 Val = (float)Val; // Mask out extra precision. 303 304 // Do the map lookup using the actual bit pattern for the floating point 305 // value, so that we don't have problems with 0.0 comparing equal to -0.0, and 306 // we don't have issues with SNANs. 307 union { 308 double DV; 309 uint64_t IV; 310 }; 311 312 DV = Val; 313 314 SDNode *&N = ConstantFPs[std::make_pair(IV, VT)]; 315 if (N) return SDOperand(N, 0); 316 N = new ConstantFPSDNode(Val, VT); 317 AllNodes.push_back(N); 318 return SDOperand(N, 0); 319} 320 321 322 323SDOperand SelectionDAG::getGlobalAddress(const GlobalValue *GV, 324 MVT::ValueType VT) { 325 SDNode *&N = GlobalValues[GV]; 326 if (N) return SDOperand(N, 0); 327 N = new GlobalAddressSDNode(GV,VT); 328 AllNodes.push_back(N); 329 return SDOperand(N, 0); 330} 331 332SDOperand SelectionDAG::getFrameIndex(int FI, MVT::ValueType VT) { 333 SDNode *&N = FrameIndices[FI]; 334 if (N) return SDOperand(N, 0); 335 N = new FrameIndexSDNode(FI, VT); 336 AllNodes.push_back(N); 337 return SDOperand(N, 0); 338} 339 340SDOperand SelectionDAG::getConstantPool(unsigned CPIdx, MVT::ValueType VT) { 341 SDNode *N = ConstantPoolIndices[CPIdx]; 342 if (N) return SDOperand(N, 0); 343 N = new ConstantPoolSDNode(CPIdx, VT); 344 AllNodes.push_back(N); 345 return SDOperand(N, 0); 346} 347 348SDOperand SelectionDAG::getBasicBlock(MachineBasicBlock *MBB) { 349 SDNode *&N = BBNodes[MBB]; 350 if (N) return SDOperand(N, 0); 351 N = new BasicBlockSDNode(MBB); 352 AllNodes.push_back(N); 353 return SDOperand(N, 0); 354} 355 356SDOperand SelectionDAG::getValueType(MVT::ValueType VT) { 357 if ((unsigned)VT >= ValueTypeNodes.size()) 358 ValueTypeNodes.resize(VT+1); 359 if (ValueTypeNodes[VT] == 0) { 360 ValueTypeNodes[VT] = new VTSDNode(VT); 361 AllNodes.push_back(ValueTypeNodes[VT]); 362 } 363 364 return SDOperand(ValueTypeNodes[VT], 0); 365} 366 367SDOperand SelectionDAG::getExternalSymbol(const char *Sym, MVT::ValueType VT) { 368 SDNode *&N = ExternalSymbols[Sym]; 369 if (N) return SDOperand(N, 0); 370 N = new ExternalSymbolSDNode(Sym, VT); 371 AllNodes.push_back(N); 372 return SDOperand(N, 0); 373} 374 375SDOperand SelectionDAG::getSetCC(ISD::CondCode Cond, MVT::ValueType VT, 376 SDOperand N1, SDOperand N2) { 377 // These setcc operations always fold. 378 switch (Cond) { 379 default: break; 380 case ISD::SETFALSE: 381 case ISD::SETFALSE2: return getConstant(0, VT); 382 case ISD::SETTRUE: 383 case ISD::SETTRUE2: return getConstant(1, VT); 384 } 385 386 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val)) { 387 uint64_t C2 = N2C->getValue(); 388 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) { 389 uint64_t C1 = N1C->getValue(); 390 391 // Sign extend the operands if required 392 if (ISD::isSignedIntSetCC(Cond)) { 393 C1 = N1C->getSignExtended(); 394 C2 = N2C->getSignExtended(); 395 } 396 397 switch (Cond) { 398 default: assert(0 && "Unknown integer setcc!"); 399 case ISD::SETEQ: return getConstant(C1 == C2, VT); 400 case ISD::SETNE: return getConstant(C1 != C2, VT); 401 case ISD::SETULT: return getConstant(C1 < C2, VT); 402 case ISD::SETUGT: return getConstant(C1 > C2, VT); 403 case ISD::SETULE: return getConstant(C1 <= C2, VT); 404 case ISD::SETUGE: return getConstant(C1 >= C2, VT); 405 case ISD::SETLT: return getConstant((int64_t)C1 < (int64_t)C2, VT); 406 case ISD::SETGT: return getConstant((int64_t)C1 > (int64_t)C2, VT); 407 case ISD::SETLE: return getConstant((int64_t)C1 <= (int64_t)C2, VT); 408 case ISD::SETGE: return getConstant((int64_t)C1 >= (int64_t)C2, VT); 409 } 410 } else { 411 // If the LHS is a ZERO_EXTEND and if this is an ==/!= comparison, perform 412 // the comparison on the input. 413 if (N1.getOpcode() == ISD::ZERO_EXTEND) { 414 unsigned InSize = MVT::getSizeInBits(N1.getOperand(0).getValueType()); 415 416 // If the comparison constant has bits in the upper part, the 417 // zero-extended value could never match. 418 if (C2 & (~0ULL << InSize)) { 419 unsigned VSize = MVT::getSizeInBits(N1.getValueType()); 420 switch (Cond) { 421 case ISD::SETUGT: 422 case ISD::SETUGE: 423 case ISD::SETEQ: return getConstant(0, VT); 424 case ISD::SETULT: 425 case ISD::SETULE: 426 case ISD::SETNE: return getConstant(1, VT); 427 case ISD::SETGT: 428 case ISD::SETGE: 429 // True if the sign bit of C2 is set. 430 return getConstant((C2 & (1ULL << VSize)) != 0, VT); 431 case ISD::SETLT: 432 case ISD::SETLE: 433 // True if the sign bit of C2 isn't set. 434 return getConstant((C2 & (1ULL << VSize)) == 0, VT); 435 default: 436 break; 437 } 438 } 439 440 // Otherwise, we can perform the comparison with the low bits. 441 switch (Cond) { 442 case ISD::SETEQ: 443 case ISD::SETNE: 444 case ISD::SETUGT: 445 case ISD::SETUGE: 446 case ISD::SETULT: 447 case ISD::SETULE: 448 return getSetCC(Cond, VT, N1.getOperand(0), 449 getConstant(C2, N1.getOperand(0).getValueType())); 450 default: 451 break; // todo, be more careful with signed comparisons 452 } 453 } 454 455 456 uint64_t MinVal, MaxVal; 457 unsigned OperandBitSize = MVT::getSizeInBits(N2C->getValueType(0)); 458 if (ISD::isSignedIntSetCC(Cond)) { 459 MinVal = 1ULL << (OperandBitSize-1); 460 if (OperandBitSize != 1) // Avoid X >> 64, which is undefined. 461 MaxVal = ~0ULL >> (65-OperandBitSize); 462 else 463 MaxVal = 0; 464 } else { 465 MinVal = 0; 466 MaxVal = ~0ULL >> (64-OperandBitSize); 467 } 468 469 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 470 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 471 if (C2 == MinVal) return getConstant(1, VT); // X >= MIN --> true 472 --C2; // X >= C1 --> X > (C1-1) 473 Cond = (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT; 474 N2 = getConstant(C2, N2.getValueType()); 475 N2C = cast<ConstantSDNode>(N2.Val); 476 } 477 478 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 479 if (C2 == MaxVal) return getConstant(1, VT); // X <= MAX --> true 480 ++C2; // X <= C1 --> X < (C1+1) 481 Cond = (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT; 482 N2 = getConstant(C2, N2.getValueType()); 483 N2C = cast<ConstantSDNode>(N2.Val); 484 } 485 486 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C2 == MinVal) 487 return getConstant(0, VT); // X < MIN --> false 488 489 // Canonicalize setgt X, Min --> setne X, Min 490 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C2 == MinVal) 491 return getSetCC(ISD::SETNE, VT, N1, N2); 492 493 // If we have setult X, 1, turn it into seteq X, 0 494 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C2 == MinVal+1) 495 return getSetCC(ISD::SETEQ, VT, N1, 496 getConstant(MinVal, N1.getValueType())); 497 // If we have setugt X, Max-1, turn it into seteq X, Max 498 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C2 == MaxVal-1) 499 return getSetCC(ISD::SETEQ, VT, N1, 500 getConstant(MaxVal, N1.getValueType())); 501 502 // If we have "setcc X, C1", check to see if we can shrink the immediate 503 // by changing cc. 504 505 // SETUGT X, SINTMAX -> SETLT X, 0 506 if (Cond == ISD::SETUGT && OperandBitSize != 1 && 507 C2 == (~0ULL >> (65-OperandBitSize))) 508 return getSetCC(ISD::SETLT, VT, N1, getConstant(0, N2.getValueType())); 509 510 // FIXME: Implement the rest of these. 511 512 513 // Fold bit comparisons when we can. 514 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 515 VT == N1.getValueType() && N1.getOpcode() == ISD::AND) 516 if (ConstantSDNode *AndRHS = 517 dyn_cast<ConstantSDNode>(N1.getOperand(1))) { 518 if (Cond == ISD::SETNE && C2 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 519 // Perform the xform if the AND RHS is a single bit. 520 if ((AndRHS->getValue() & (AndRHS->getValue()-1)) == 0) { 521 return getNode(ISD::SRL, VT, N1, 522 getConstant(Log2_64(AndRHS->getValue()), 523 TLI.getShiftAmountTy())); 524 } 525 } else if (Cond == ISD::SETEQ && C2 == AndRHS->getValue()) { 526 // (X & 8) == 8 --> (X & 8) >> 3 527 // Perform the xform if C2 is a single bit. 528 if ((C2 & (C2-1)) == 0) { 529 return getNode(ISD::SRL, VT, N1, 530 getConstant(Log2_64(C2),TLI.getShiftAmountTy())); 531 } 532 } 533 } 534 } 535 } else if (isa<ConstantSDNode>(N1.Val)) { 536 // Ensure that the constant occurs on the RHS. 537 return getSetCC(ISD::getSetCCSwappedOperands(Cond), VT, N2, N1); 538 } 539 540 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.Val)) 541 if (ConstantFPSDNode *N2C = dyn_cast<ConstantFPSDNode>(N2.Val)) { 542 double C1 = N1C->getValue(), C2 = N2C->getValue(); 543 544 switch (Cond) { 545 default: break; // FIXME: Implement the rest of these! 546 case ISD::SETEQ: return getConstant(C1 == C2, VT); 547 case ISD::SETNE: return getConstant(C1 != C2, VT); 548 case ISD::SETLT: return getConstant(C1 < C2, VT); 549 case ISD::SETGT: return getConstant(C1 > C2, VT); 550 case ISD::SETLE: return getConstant(C1 <= C2, VT); 551 case ISD::SETGE: return getConstant(C1 >= C2, VT); 552 } 553 } else { 554 // Ensure that the constant occurs on the RHS. 555 Cond = ISD::getSetCCSwappedOperands(Cond); 556 std::swap(N1, N2); 557 } 558 559 if (N1 == N2) { 560 // We can always fold X == Y for integer setcc's. 561 if (MVT::isInteger(N1.getValueType())) 562 return getConstant(ISD::isTrueWhenEqual(Cond), VT); 563 unsigned UOF = ISD::getUnorderedFlavor(Cond); 564 if (UOF == 2) // FP operators that are undefined on NaNs. 565 return getConstant(ISD::isTrueWhenEqual(Cond), VT); 566 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 567 return getConstant(UOF, VT); 568 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 569 // if it is not already. 570 Cond = UOF == 0 ? ISD::SETUO : ISD::SETO; 571 } 572 573 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 574 MVT::isInteger(N1.getValueType())) { 575 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 576 N1.getOpcode() == ISD::XOR) { 577 // Simplify (X+Y) == (X+Z) --> Y == Z 578 if (N1.getOpcode() == N2.getOpcode()) { 579 if (N1.getOperand(0) == N2.getOperand(0)) 580 return getSetCC(Cond, VT, N1.getOperand(1), N2.getOperand(1)); 581 if (N1.getOperand(1) == N2.getOperand(1)) 582 return getSetCC(Cond, VT, N1.getOperand(0), N2.getOperand(0)); 583 if (isCommutativeBinOp(N1.getOpcode())) { 584 // If X op Y == Y op X, try other combinations. 585 if (N1.getOperand(0) == N2.getOperand(1)) 586 return getSetCC(Cond, VT, N1.getOperand(1), N2.getOperand(0)); 587 if (N1.getOperand(1) == N2.getOperand(0)) 588 return getSetCC(Cond, VT, N1.getOperand(1), N2.getOperand(1)); 589 } 590 } 591 592 // FIXME: move this stuff to the DAG Combiner when it exists! 593 594 // Simplify (X+Z) == X --> Z == 0 595 if (N1.getOperand(0) == N2) 596 return getSetCC(Cond, VT, N1.getOperand(1), 597 getConstant(0, N1.getValueType())); 598 if (N1.getOperand(1) == N2) { 599 if (isCommutativeBinOp(N1.getOpcode())) 600 return getSetCC(Cond, VT, N1.getOperand(0), 601 getConstant(0, N1.getValueType())); 602 else { 603 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 604 // (Z-X) == X --> Z == X<<1 605 return getSetCC(Cond, VT, N1.getOperand(0), 606 getNode(ISD::SHL, N2.getValueType(), 607 N2, getConstant(1, TLI.getShiftAmountTy()))); 608 } 609 } 610 } 611 612 if (N2.getOpcode() == ISD::ADD || N2.getOpcode() == ISD::SUB || 613 N2.getOpcode() == ISD::XOR) { 614 // Simplify X == (X+Z) --> Z == 0 615 if (N2.getOperand(0) == N1) 616 return getSetCC(Cond, VT, N2.getOperand(1), 617 getConstant(0, N2.getValueType())); 618 else if (N2.getOperand(1) == N1) 619 return getSetCC(Cond, VT, N2.getOperand(0), 620 getConstant(0, N2.getValueType())); 621 } 622 } 623 624 // Fold away ALL boolean setcc's. 625 if (N1.getValueType() == MVT::i1) { 626 switch (Cond) { 627 default: assert(0 && "Unknown integer setcc!"); 628 case ISD::SETEQ: // X == Y -> (X^Y)^1 629 N1 = getNode(ISD::XOR, MVT::i1, 630 getNode(ISD::XOR, MVT::i1, N1, N2), 631 getConstant(1, MVT::i1)); 632 break; 633 case ISD::SETNE: // X != Y --> (X^Y) 634 N1 = getNode(ISD::XOR, MVT::i1, N1, N2); 635 break; 636 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y 637 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y 638 N1 = getNode(ISD::AND, MVT::i1, N2, 639 getNode(ISD::XOR, MVT::i1, N1, getConstant(1, MVT::i1))); 640 break; 641 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X 642 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X 643 N1 = getNode(ISD::AND, MVT::i1, N1, 644 getNode(ISD::XOR, MVT::i1, N2, getConstant(1, MVT::i1))); 645 break; 646 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y 647 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y 648 N1 = getNode(ISD::OR, MVT::i1, N2, 649 getNode(ISD::XOR, MVT::i1, N1, getConstant(1, MVT::i1))); 650 break; 651 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X 652 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X 653 N1 = getNode(ISD::OR, MVT::i1, N1, 654 getNode(ISD::XOR, MVT::i1, N2, getConstant(1, MVT::i1))); 655 break; 656 } 657 if (VT != MVT::i1) 658 N1 = getNode(ISD::ZERO_EXTEND, VT, N1); 659 return N1; 660 } 661 662 663 SetCCSDNode *&N = SetCCs[std::make_pair(std::make_pair(N1, N2), 664 std::make_pair(Cond, VT))]; 665 if (N) return SDOperand(N, 0); 666 N = new SetCCSDNode(Cond, N1, N2); 667 N->setValueTypes(VT); 668 AllNodes.push_back(N); 669 return SDOperand(N, 0); 670} 671 672 673 674/// getNode - Gets or creates the specified node. 675/// 676SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT) { 677 SDNode *N = new SDNode(Opcode, VT); 678 AllNodes.push_back(N); 679 return SDOperand(N, 0); 680} 681 682SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, 683 SDOperand Operand) { 684 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Operand.Val)) { 685 uint64_t Val = C->getValue(); 686 switch (Opcode) { 687 default: break; 688 case ISD::SIGN_EXTEND: return getConstant(C->getSignExtended(), VT); 689 case ISD::ZERO_EXTEND: return getConstant(Val, VT); 690 case ISD::TRUNCATE: return getConstant(Val, VT); 691 case ISD::SINT_TO_FP: return getConstantFP(C->getSignExtended(), VT); 692 case ISD::UINT_TO_FP: return getConstantFP(C->getValue(), VT); 693 } 694 } 695 696 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Operand.Val)) 697 switch (Opcode) { 698 case ISD::FNEG: 699 return getConstantFP(-C->getValue(), VT); 700 case ISD::FP_ROUND: 701 case ISD::FP_EXTEND: 702 return getConstantFP(C->getValue(), VT); 703 case ISD::FP_TO_SINT: 704 return getConstant((int64_t)C->getValue(), VT); 705 case ISD::FP_TO_UINT: 706 return getConstant((uint64_t)C->getValue(), VT); 707 } 708 709 unsigned OpOpcode = Operand.Val->getOpcode(); 710 switch (Opcode) { 711 case ISD::TokenFactor: 712 return Operand; // Factor of one node? No factor. 713 case ISD::SIGN_EXTEND: 714 if (Operand.getValueType() == VT) return Operand; // noop extension 715 if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND) 716 return getNode(OpOpcode, VT, Operand.Val->getOperand(0)); 717 break; 718 case ISD::ZERO_EXTEND: 719 if (Operand.getValueType() == VT) return Operand; // noop extension 720 if (OpOpcode == ISD::ZERO_EXTEND) // (zext (zext x)) -> (zext x) 721 return getNode(ISD::ZERO_EXTEND, VT, Operand.Val->getOperand(0)); 722 break; 723 case ISD::TRUNCATE: 724 if (Operand.getValueType() == VT) return Operand; // noop truncate 725 if (OpOpcode == ISD::TRUNCATE) 726 return getNode(ISD::TRUNCATE, VT, Operand.Val->getOperand(0)); 727 else if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND) { 728 // If the source is smaller than the dest, we still need an extend. 729 if (Operand.Val->getOperand(0).getValueType() < VT) 730 return getNode(OpOpcode, VT, Operand.Val->getOperand(0)); 731 else if (Operand.Val->getOperand(0).getValueType() > VT) 732 return getNode(ISD::TRUNCATE, VT, Operand.Val->getOperand(0)); 733 else 734 return Operand.Val->getOperand(0); 735 } 736 break; 737 case ISD::FNEG: 738 if (OpOpcode == ISD::SUB) // -(X-Y) -> (Y-X) 739 return getNode(ISD::SUB, VT, Operand.Val->getOperand(1), 740 Operand.Val->getOperand(0)); 741 if (OpOpcode == ISD::FNEG) // --X -> X 742 return Operand.Val->getOperand(0); 743 break; 744 case ISD::FABS: 745 if (OpOpcode == ISD::FNEG) // abs(-X) -> abs(X) 746 return getNode(ISD::FABS, VT, Operand.Val->getOperand(0)); 747 break; 748 } 749 750 SDNode *&N = UnaryOps[std::make_pair(Opcode, std::make_pair(Operand, VT))]; 751 if (N) return SDOperand(N, 0); 752 N = new SDNode(Opcode, Operand); 753 N->setValueTypes(VT); 754 AllNodes.push_back(N); 755 return SDOperand(N, 0); 756} 757 758/// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero. We use 759/// this predicate to simplify operations downstream. V and Mask are known to 760/// be the same type. 761static bool MaskedValueIsZero(const SDOperand &Op, uint64_t Mask, 762 const TargetLowering &TLI) { 763 unsigned SrcBits; 764 if (Mask == 0) return true; 765 766 // If we know the result of a setcc has the top bits zero, use this info. 767 switch (Op.getOpcode()) { 768 case ISD::UNDEF: 769 return true; 770 case ISD::Constant: 771 return (cast<ConstantSDNode>(Op)->getValue() & Mask) == 0; 772 773 case ISD::SETCC: 774 return ((Mask & 1) == 0) && 775 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult; 776 777 case ISD::ZEXTLOAD: 778 SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(3))->getVT()); 779 return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits. 780 case ISD::ZERO_EXTEND: 781 SrcBits = MVT::getSizeInBits(Op.getOperand(0).getValueType()); 782 return MaskedValueIsZero(Op.getOperand(0),Mask & ((1ULL << SrcBits)-1),TLI); 783 784 case ISD::AND: 785 // (X & C1) & C2 == 0 iff C1 & C2 == 0. 786 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(Op.getOperand(1))) 787 return MaskedValueIsZero(Op.getOperand(0),AndRHS->getValue() & Mask, TLI); 788 789 // FALL THROUGH 790 case ISD::OR: 791 case ISD::XOR: 792 return MaskedValueIsZero(Op.getOperand(0), Mask, TLI) && 793 MaskedValueIsZero(Op.getOperand(1), Mask, TLI); 794 case ISD::SELECT: 795 return MaskedValueIsZero(Op.getOperand(1), Mask, TLI) && 796 MaskedValueIsZero(Op.getOperand(2), Mask, TLI); 797 798 case ISD::SRL: 799 // (ushr X, C1) & C2 == 0 iff X & (C2 << C1) == 0 800 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 801 uint64_t NewVal = Mask << ShAmt->getValue(); 802 SrcBits = MVT::getSizeInBits(Op.getValueType()); 803 if (SrcBits != 64) NewVal &= (1ULL << SrcBits)-1; 804 return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI); 805 } 806 return false; 807 case ISD::SHL: 808 // (ushl X, C1) & C2 == 0 iff X & (C2 >> C1) == 0 809 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 810 uint64_t NewVal = Mask >> ShAmt->getValue(); 811 return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI); 812 } 813 return false; 814 // TODO we could handle some SRA cases here. 815 default: break; 816 } 817 818 return false; 819} 820 821 822 823SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, 824 SDOperand N1, SDOperand N2) { 825#ifndef NDEBUG 826 switch (Opcode) { 827 case ISD::TokenFactor: 828 assert(VT == MVT::Other && N1.getValueType() == MVT::Other && 829 N2.getValueType() == MVT::Other && "Invalid token factor!"); 830 break; 831 case ISD::AND: 832 case ISD::OR: 833 case ISD::XOR: 834 case ISD::UDIV: 835 case ISD::UREM: 836 case ISD::MULHU: 837 case ISD::MULHS: 838 assert(MVT::isInteger(VT) && "This operator does not apply to FP types!"); 839 // fall through 840 case ISD::ADD: 841 case ISD::SUB: 842 case ISD::MUL: 843 case ISD::SDIV: 844 case ISD::SREM: 845 assert(N1.getValueType() == N2.getValueType() && 846 N1.getValueType() == VT && "Binary operator types must match!"); 847 break; 848 849 case ISD::SHL: 850 case ISD::SRA: 851 case ISD::SRL: 852 assert(VT == N1.getValueType() && 853 "Shift operators return type must be the same as their first arg"); 854 assert(MVT::isInteger(VT) && MVT::isInteger(N2.getValueType()) && 855 VT != MVT::i1 && "Shifts only work on integers"); 856 break; 857 case ISD::FP_ROUND_INREG: { 858 MVT::ValueType EVT = cast<VTSDNode>(N2)->getVT(); 859 assert(VT == N1.getValueType() && "Not an inreg round!"); 860 assert(MVT::isFloatingPoint(VT) && MVT::isFloatingPoint(EVT) && 861 "Cannot FP_ROUND_INREG integer types"); 862 assert(EVT <= VT && "Not rounding down!"); 863 break; 864 } 865 case ISD::SIGN_EXTEND_INREG: { 866 MVT::ValueType EVT = cast<VTSDNode>(N2)->getVT(); 867 assert(VT == N1.getValueType() && "Not an inreg extend!"); 868 assert(MVT::isInteger(VT) && MVT::isInteger(EVT) && 869 "Cannot *_EXTEND_INREG FP types"); 870 assert(EVT <= VT && "Not extending!"); 871 } 872 873 default: break; 874 } 875#endif 876 877 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 878 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 879 if (N1C) { 880 if (N2C) { 881 uint64_t C1 = N1C->getValue(), C2 = N2C->getValue(); 882 switch (Opcode) { 883 case ISD::ADD: return getConstant(C1 + C2, VT); 884 case ISD::SUB: return getConstant(C1 - C2, VT); 885 case ISD::MUL: return getConstant(C1 * C2, VT); 886 case ISD::UDIV: 887 if (C2) return getConstant(C1 / C2, VT); 888 break; 889 case ISD::UREM : 890 if (C2) return getConstant(C1 % C2, VT); 891 break; 892 case ISD::SDIV : 893 if (C2) return getConstant(N1C->getSignExtended() / 894 N2C->getSignExtended(), VT); 895 break; 896 case ISD::SREM : 897 if (C2) return getConstant(N1C->getSignExtended() % 898 N2C->getSignExtended(), VT); 899 break; 900 case ISD::AND : return getConstant(C1 & C2, VT); 901 case ISD::OR : return getConstant(C1 | C2, VT); 902 case ISD::XOR : return getConstant(C1 ^ C2, VT); 903 case ISD::SHL : return getConstant(C1 << (int)C2, VT); 904 case ISD::SRL : return getConstant(C1 >> (unsigned)C2, VT); 905 case ISD::SRA : return getConstant(N1C->getSignExtended() >>(int)C2, VT); 906 default: break; 907 } 908 909 } else { // Cannonicalize constant to RHS if commutative 910 if (isCommutativeBinOp(Opcode)) { 911 std::swap(N1C, N2C); 912 std::swap(N1, N2); 913 } 914 } 915 916 switch (Opcode) { 917 default: break; 918 case ISD::SHL: // shl 0, X -> 0 919 if (N1C->isNullValue()) return N1; 920 break; 921 case ISD::SRL: // srl 0, X -> 0 922 if (N1C->isNullValue()) return N1; 923 break; 924 case ISD::SRA: // sra -1, X -> -1 925 if (N1C->isAllOnesValue()) return N1; 926 break; 927 case ISD::SIGN_EXTEND_INREG: // SIGN_EXTEND_INREG N1C, EVT 928 // Extending a constant? Just return the extended constant. 929 SDOperand Tmp = getNode(ISD::TRUNCATE, cast<VTSDNode>(N2)->getVT(), N1); 930 return getNode(ISD::SIGN_EXTEND, VT, Tmp); 931 } 932 } 933 934 if (N2C) { 935 uint64_t C2 = N2C->getValue(); 936 937 switch (Opcode) { 938 case ISD::ADD: 939 if (!C2) return N1; // add X, 0 -> X 940 break; 941 case ISD::SUB: 942 if (!C2) return N1; // sub X, 0 -> X 943 return getNode(ISD::ADD, VT, N1, getConstant(-C2, VT)); 944 case ISD::MUL: 945 if (!C2) return N2; // mul X, 0 -> 0 946 if (N2C->isAllOnesValue()) // mul X, -1 -> 0-X 947 return getNode(ISD::SUB, VT, getConstant(0, VT), N1); 948 949 // FIXME: Move this to the DAG combiner when it exists. 950 if ((C2 & C2-1) == 0) { 951 SDOperand ShAmt = getConstant(Log2_64(C2), TLI.getShiftAmountTy()); 952 return getNode(ISD::SHL, VT, N1, ShAmt); 953 } 954 break; 955 956 case ISD::MULHU: 957 case ISD::MULHS: 958 if (!C2) return N2; // mul X, 0 -> 0 959 960 if (C2 == 1) // 0X*01 -> 0X hi(0X) == 0 961 return getConstant(0, VT); 962 963 // Many others could be handled here, including -1, powers of 2, etc. 964 break; 965 966 case ISD::UDIV: 967 // FIXME: Move this to the DAG combiner when it exists. 968 if ((C2 & C2-1) == 0 && C2) { 969 SDOperand ShAmt = getConstant(Log2_64(C2), TLI.getShiftAmountTy()); 970 return getNode(ISD::SRL, VT, N1, ShAmt); 971 } 972 break; 973 974 case ISD::SHL: 975 case ISD::SRL: 976 case ISD::SRA: 977 // If the shift amount is bigger than the size of the data, then all the 978 // bits are shifted out. Simplify to undef. 979 if (C2 >= MVT::getSizeInBits(N1.getValueType())) { 980 return getNode(ISD::UNDEF, N1.getValueType()); 981 } 982 if (C2 == 0) return N1; 983 984 if (Opcode == ISD::SHL && N1.getNumOperands() == 2) 985 if (ConstantSDNode *OpSA = dyn_cast<ConstantSDNode>(N1.getOperand(1))) { 986 unsigned OpSAC = OpSA->getValue(); 987 if (N1.getOpcode() == ISD::SHL) { 988 if (C2+OpSAC >= MVT::getSizeInBits(N1.getValueType())) 989 return getConstant(0, N1.getValueType()); 990 return getNode(ISD::SHL, N1.getValueType(), N1.getOperand(0), 991 getConstant(C2+OpSAC, N2.getValueType())); 992 } else if (N1.getOpcode() == ISD::SRL) { 993 // (X >> C1) << C2: if C2 > C1, ((X & ~0<<C1) << C2-C1) 994 SDOperand Mask = getNode(ISD::AND, VT, N1.getOperand(0), 995 getConstant(~0ULL << OpSAC, VT)); 996 if (C2 > OpSAC) { 997 return getNode(ISD::SHL, VT, Mask, 998 getConstant(C2-OpSAC, N2.getValueType())); 999 } else { 1000 // (X >> C1) << C2: if C2 <= C1, ((X & ~0<<C1) >> C1-C2) 1001 return getNode(ISD::SRL, VT, Mask, 1002 getConstant(OpSAC-C2, N2.getValueType())); 1003 } 1004 } else if (N1.getOpcode() == ISD::SRA) { 1005 // if C1 == C2, just mask out low bits. 1006 if (C2 == OpSAC) 1007 return getNode(ISD::AND, VT, N1.getOperand(0), 1008 getConstant(~0ULL << C2, VT)); 1009 } 1010 } 1011 break; 1012 1013 case ISD::AND: 1014 if (!C2) return N2; // X and 0 -> 0 1015 if (N2C->isAllOnesValue()) 1016 return N1; // X and -1 -> X 1017 1018 if (MaskedValueIsZero(N1, C2, TLI)) // X and 0 -> 0 1019 return getConstant(0, VT); 1020 1021 { 1022 uint64_t NotC2 = ~C2; 1023 if (VT != MVT::i64) 1024 NotC2 &= (1ULL << MVT::getSizeInBits(VT))-1; 1025 1026 if (MaskedValueIsZero(N1, NotC2, TLI)) 1027 return N1; // if (X & ~C2) -> 0, the and is redundant 1028 } 1029 1030 // FIXME: Should add a corresponding version of this for 1031 // ZERO_EXTEND/SIGN_EXTEND by converting them to an ANY_EXTEND node which 1032 // we don't have yet. 1033 1034 // and (sign_extend_inreg x:16:32), 1 -> and x, 1 1035 if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) { 1036 // If we are masking out the part of our input that was extended, just 1037 // mask the input to the extension directly. 1038 unsigned ExtendBits = 1039 MVT::getSizeInBits(cast<VTSDNode>(N1.getOperand(1))->getVT()); 1040 if ((C2 & (~0ULL << ExtendBits)) == 0) 1041 return getNode(ISD::AND, VT, N1.getOperand(0), N2); 1042 } 1043 break; 1044 case ISD::OR: 1045 if (!C2)return N1; // X or 0 -> X 1046 if (N2C->isAllOnesValue()) 1047 return N2; // X or -1 -> -1 1048 break; 1049 case ISD::XOR: 1050 if (!C2) return N1; // X xor 0 -> X 1051 if (N2C->isAllOnesValue()) { 1052 if (SetCCSDNode *SetCC = dyn_cast<SetCCSDNode>(N1.Val)){ 1053 // !(X op Y) -> (X !op Y) 1054 bool isInteger = MVT::isInteger(SetCC->getOperand(0).getValueType()); 1055 return getSetCC(ISD::getSetCCInverse(SetCC->getCondition(),isInteger), 1056 SetCC->getValueType(0), 1057 SetCC->getOperand(0), SetCC->getOperand(1)); 1058 } else if (N1.getOpcode() == ISD::AND || N1.getOpcode() == ISD::OR) { 1059 SDNode *Op = N1.Val; 1060 // !(X or Y) -> (!X and !Y) iff X or Y are freely invertible 1061 // !(X and Y) -> (!X or !Y) iff X or Y are freely invertible 1062 SDOperand LHS = Op->getOperand(0), RHS = Op->getOperand(1); 1063 if (isInvertibleForFree(RHS) || isInvertibleForFree(LHS)) { 1064 LHS = getNode(ISD::XOR, VT, LHS, N2); // RHS = ~LHS 1065 RHS = getNode(ISD::XOR, VT, RHS, N2); // RHS = ~RHS 1066 if (Op->getOpcode() == ISD::AND) 1067 return getNode(ISD::OR, VT, LHS, RHS); 1068 return getNode(ISD::AND, VT, LHS, RHS); 1069 } 1070 } 1071 // X xor -1 -> not(x) ? 1072 } 1073 break; 1074 } 1075 1076 // Reassociate ((X op C1) op C2) if possible. 1077 if (N1.getOpcode() == Opcode && isAssociativeBinOp(Opcode)) 1078 if (ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N1.Val->getOperand(1))) 1079 return getNode(Opcode, VT, N1.Val->getOperand(0), 1080 getNode(Opcode, VT, N2, N1.Val->getOperand(1))); 1081 } 1082 1083 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1.Val); 1084 ConstantFPSDNode *N2CFP = dyn_cast<ConstantFPSDNode>(N2.Val); 1085 if (N1CFP) { 1086 if (N2CFP) { 1087 double C1 = N1CFP->getValue(), C2 = N2CFP->getValue(); 1088 switch (Opcode) { 1089 case ISD::ADD: return getConstantFP(C1 + C2, VT); 1090 case ISD::SUB: return getConstantFP(C1 - C2, VT); 1091 case ISD::MUL: return getConstantFP(C1 * C2, VT); 1092 case ISD::SDIV: 1093 if (C2) return getConstantFP(C1 / C2, VT); 1094 break; 1095 case ISD::SREM : 1096 if (C2) return getConstantFP(fmod(C1, C2), VT); 1097 break; 1098 default: break; 1099 } 1100 1101 } else { // Cannonicalize constant to RHS if commutative 1102 if (isCommutativeBinOp(Opcode)) { 1103 std::swap(N1CFP, N2CFP); 1104 std::swap(N1, N2); 1105 } 1106 } 1107 1108 if (Opcode == ISD::FP_ROUND_INREG) 1109 return getNode(ISD::FP_EXTEND, VT, 1110 getNode(ISD::FP_ROUND, cast<VTSDNode>(N2)->getVT(), N1)); 1111 } 1112 1113 // Finally, fold operations that do not require constants. 1114 switch (Opcode) { 1115 case ISD::TokenFactor: 1116 if (N1.getOpcode() == ISD::EntryToken) 1117 return N2; 1118 if (N2.getOpcode() == ISD::EntryToken) 1119 return N1; 1120 break; 1121 1122 case ISD::AND: 1123 case ISD::OR: 1124 if (SetCCSDNode *LHS = dyn_cast<SetCCSDNode>(N1.Val)) 1125 if (SetCCSDNode *RHS = dyn_cast<SetCCSDNode>(N2.Val)) { 1126 SDOperand LL = LHS->getOperand(0), RL = RHS->getOperand(0); 1127 SDOperand LR = LHS->getOperand(1), RR = RHS->getOperand(1); 1128 ISD::CondCode Op2 = RHS->getCondition(); 1129 1130 if (LR == RR && isa<ConstantSDNode>(LR) && 1131 Op2 == LHS->getCondition() && MVT::isInteger(LL.getValueType())) { 1132 // (X != 0) | (Y != 0) -> (X|Y != 0) 1133 // (X == 0) & (Y == 0) -> (X|Y == 0) 1134 // (X < 0) | (Y < 0) -> (X|Y < 0) 1135 if (cast<ConstantSDNode>(LR)->getValue() == 0 && 1136 ((Op2 == ISD::SETEQ && Opcode == ISD::AND) || 1137 (Op2 == ISD::SETNE && Opcode == ISD::OR) || 1138 (Op2 == ISD::SETLT && Opcode == ISD::OR))) 1139 return getSetCC(Op2, VT, 1140 getNode(ISD::OR, LR.getValueType(), LL, RL), LR); 1141 1142 if (cast<ConstantSDNode>(LR)->isAllOnesValue()) { 1143 // (X == -1) & (Y == -1) -> (X&Y == -1) 1144 // (X != -1) | (Y != -1) -> (X&Y != -1) 1145 // (X > -1) | (Y > -1) -> (X&Y > -1) 1146 if ((Opcode == ISD::AND && Op2 == ISD::SETEQ) || 1147 (Opcode == ISD::OR && Op2 == ISD::SETNE) || 1148 (Opcode == ISD::OR && Op2 == ISD::SETGT)) 1149 return getSetCC(Op2, VT, 1150 getNode(ISD::AND, LR.getValueType(), LL, RL), LR); 1151 // (X > -1) & (Y > -1) -> (X|Y > -1) 1152 if (Opcode == ISD::AND && Op2 == ISD::SETGT) 1153 return getSetCC(Op2, VT, 1154 getNode(ISD::OR, LR.getValueType(), LL, RL), LR); 1155 } 1156 } 1157 1158 // (X op1 Y) | (Y op2 X) -> (X op1 Y) | (X swapop2 Y) 1159 if (LL == RR && LR == RL) { 1160 Op2 = ISD::getSetCCSwappedOperands(Op2); 1161 goto MatchedBackwards; 1162 } 1163 1164 if (LL == RL && LR == RR) { 1165 MatchedBackwards: 1166 ISD::CondCode Result; 1167 bool isInteger = MVT::isInteger(LL.getValueType()); 1168 if (Opcode == ISD::OR) 1169 Result = ISD::getSetCCOrOperation(LHS->getCondition(), Op2, 1170 isInteger); 1171 else 1172 Result = ISD::getSetCCAndOperation(LHS->getCondition(), Op2, 1173 isInteger); 1174 if (Result != ISD::SETCC_INVALID) 1175 return getSetCC(Result, LHS->getValueType(0), LL, LR); 1176 } 1177 } 1178 1179 // and/or zext(a), zext(b) -> zext(and/or a, b) 1180 if (N1.getOpcode() == ISD::ZERO_EXTEND && 1181 N2.getOpcode() == ISD::ZERO_EXTEND && 1182 N1.getOperand(0).getValueType() == N2.getOperand(0).getValueType()) 1183 return getNode(ISD::ZERO_EXTEND, VT, 1184 getNode(Opcode, N1.getOperand(0).getValueType(), 1185 N1.getOperand(0), N2.getOperand(0))); 1186 break; 1187 case ISD::XOR: 1188 if (N1 == N2) return getConstant(0, VT); // xor X, Y -> 0 1189 break; 1190 case ISD::ADD: 1191 if (N2.getOpcode() == ISD::FNEG) // (A+ (-B) -> A-B 1192 return getNode(ISD::SUB, VT, N1, N2.getOperand(0)); 1193 if (N1.getOpcode() == ISD::FNEG) // ((-A)+B) -> B-A 1194 return getNode(ISD::SUB, VT, N2, N1.getOperand(0)); 1195 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 1196 cast<ConstantSDNode>(N1.getOperand(0))->getValue() == 0) 1197 return getNode(ISD::SUB, VT, N2, N1.getOperand(1)); // (0-A)+B -> B-A 1198 if (N2.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N2.getOperand(0)) && 1199 cast<ConstantSDNode>(N2.getOperand(0))->getValue() == 0) 1200 return getNode(ISD::SUB, VT, N1, N2.getOperand(1)); // A+(0-B) -> A-B 1201 if (N2.getOpcode() == ISD::SUB && N1 == N2.Val->getOperand(1) && 1202 !MVT::isFloatingPoint(N2.getValueType())) 1203 return N2.Val->getOperand(0); // A+(B-A) -> B 1204 break; 1205 case ISD::SUB: 1206 if (N1.getOpcode() == ISD::ADD) { 1207 if (N1.Val->getOperand(0) == N2 && 1208 !MVT::isFloatingPoint(N2.getValueType())) 1209 return N1.Val->getOperand(1); // (A+B)-A == B 1210 if (N1.Val->getOperand(1) == N2 && 1211 !MVT::isFloatingPoint(N2.getValueType())) 1212 return N1.Val->getOperand(0); // (A+B)-B == A 1213 } 1214 if (N2.getOpcode() == ISD::FNEG) // (A- (-B) -> A+B 1215 return getNode(ISD::ADD, VT, N1, N2.getOperand(0)); 1216 break; 1217 case ISD::FP_ROUND_INREG: 1218 if (cast<VTSDNode>(N2)->getVT() == VT) return N1; // Not actually rounding. 1219 break; 1220 case ISD::SIGN_EXTEND_INREG: { 1221 MVT::ValueType EVT = cast<VTSDNode>(N2)->getVT(); 1222 if (EVT == VT) return N1; // Not actually extending 1223 1224 // If we are sign extending an extension, use the original source. 1225 if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) 1226 if (cast<VTSDNode>(N1.getOperand(1))->getVT() <= EVT) 1227 return N1; 1228 1229 // If we are sign extending a sextload, return just the load. 1230 if (N1.getOpcode() == ISD::SEXTLOAD) 1231 if (cast<VTSDNode>(N1.getOperand(3))->getVT() <= EVT) 1232 return N1; 1233 1234 // If we are extending the result of a setcc, and we already know the 1235 // contents of the top bits, eliminate the extension. 1236 if (N1.getOpcode() == ISD::SETCC && 1237 TLI.getSetCCResultContents() == 1238 TargetLowering::ZeroOrNegativeOneSetCCResult) 1239 return N1; 1240 1241 // If we are sign extending the result of an (and X, C) operation, and we 1242 // know the extended bits are zeros already, don't do the extend. 1243 if (N1.getOpcode() == ISD::AND) 1244 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getOperand(1))) { 1245 uint64_t Mask = N1C->getValue(); 1246 unsigned NumBits = MVT::getSizeInBits(EVT); 1247 if ((Mask & (~0ULL << (NumBits-1))) == 0) 1248 return N1; 1249 } 1250 break; 1251 } 1252 1253 // FIXME: figure out how to safely handle things like 1254 // int foo(int x) { return 1 << (x & 255); } 1255 // int bar() { return foo(256); } 1256#if 0 1257 case ISD::SHL: 1258 case ISD::SRL: 1259 case ISD::SRA: 1260 if (N2.getOpcode() == ISD::SIGN_EXTEND_INREG && 1261 cast<VTSDNode>(N2.getOperand(1))->getVT() != MVT::i1) 1262 return getNode(Opcode, VT, N1, N2.getOperand(0)); 1263 else if (N2.getOpcode() == ISD::AND) 1264 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(N2.getOperand(1))) { 1265 // If the and is only masking out bits that cannot effect the shift, 1266 // eliminate the and. 1267 unsigned NumBits = MVT::getSizeInBits(VT); 1268 if ((AndRHS->getValue() & (NumBits-1)) == NumBits-1) 1269 return getNode(Opcode, VT, N1, N2.getOperand(0)); 1270 } 1271 break; 1272#endif 1273 } 1274 1275 // Memoize this node if possible. 1276 SDNode *N; 1277 if (Opcode != ISD::CALLSEQ_START && Opcode != ISD::CALLSEQ_END) { 1278 SDNode *&BON = BinaryOps[std::make_pair(Opcode, std::make_pair(N1, N2))]; 1279 if (BON) return SDOperand(BON, 0); 1280 1281 BON = N = new SDNode(Opcode, N1, N2); 1282 } else { 1283 N = new SDNode(Opcode, N1, N2); 1284 } 1285 1286 N->setValueTypes(VT); 1287 AllNodes.push_back(N); 1288 return SDOperand(N, 0); 1289} 1290 1291// setAdjCallChain - This method changes the token chain of an 1292// CALLSEQ_START/END node to be the specified operand. 1293void SDNode::setAdjCallChain(SDOperand N) { 1294 assert(N.getValueType() == MVT::Other); 1295 assert((getOpcode() == ISD::CALLSEQ_START || 1296 getOpcode() == ISD::CALLSEQ_END) && "Cannot adjust this node!"); 1297 1298 Operands[0].Val->removeUser(this); 1299 Operands[0] = N; 1300 N.Val->Uses.push_back(this); 1301} 1302 1303 1304 1305SDOperand SelectionDAG::getLoad(MVT::ValueType VT, 1306 SDOperand Chain, SDOperand Ptr, 1307 SDOperand SV) { 1308 SDNode *&N = Loads[std::make_pair(Ptr, std::make_pair(Chain, VT))]; 1309 if (N) return SDOperand(N, 0); 1310 N = new SDNode(ISD::LOAD, Chain, Ptr, SV); 1311 1312 // Loads have a token chain. 1313 N->setValueTypes(VT, MVT::Other); 1314 AllNodes.push_back(N); 1315 return SDOperand(N, 0); 1316} 1317 1318 1319SDOperand SelectionDAG::getExtLoad(unsigned Opcode, MVT::ValueType VT, 1320 SDOperand Chain, SDOperand Ptr, SDOperand SV, 1321 MVT::ValueType EVT) { 1322 std::vector<SDOperand> Ops; 1323 Ops.reserve(4); 1324 Ops.push_back(Chain); 1325 Ops.push_back(Ptr); 1326 Ops.push_back(SV); 1327 Ops.push_back(getValueType(EVT)); 1328 std::vector<MVT::ValueType> VTs; 1329 VTs.reserve(2); 1330 VTs.push_back(VT); VTs.push_back(MVT::Other); // Add token chain. 1331 return getNode(Opcode, VTs, Ops); 1332} 1333 1334SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, 1335 SDOperand N1, SDOperand N2, SDOperand N3) { 1336 // Perform various simplifications. 1337 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1338 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 1339 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val); 1340 switch (Opcode) { 1341 case ISD::SELECT: 1342 if (N1C) 1343 if (N1C->getValue()) 1344 return N2; // select true, X, Y -> X 1345 else 1346 return N3; // select false, X, Y -> Y 1347 1348 if (N2 == N3) return N2; // select C, X, X -> X 1349 1350 if (VT == MVT::i1) { // Boolean SELECT 1351 if (N2C) { 1352 if (N2C->getValue()) // select C, 1, X -> C | X 1353 return getNode(ISD::OR, VT, N1, N3); 1354 else // select C, 0, X -> ~C & X 1355 return getNode(ISD::AND, VT, 1356 getNode(ISD::XOR, N1.getValueType(), N1, 1357 getConstant(1, N1.getValueType())), N3); 1358 } else if (N3C) { 1359 if (N3C->getValue()) // select C, X, 1 -> ~C | X 1360 return getNode(ISD::OR, VT, 1361 getNode(ISD::XOR, N1.getValueType(), N1, 1362 getConstant(1, N1.getValueType())), N2); 1363 else // select C, X, 0 -> C & X 1364 return getNode(ISD::AND, VT, N1, N2); 1365 } 1366 1367 if (N1 == N2) // X ? X : Y --> X ? 1 : Y --> X | Y 1368 return getNode(ISD::OR, VT, N1, N3); 1369 if (N1 == N3) // X ? Y : X --> X ? Y : 0 --> X & Y 1370 return getNode(ISD::AND, VT, N1, N2); 1371 } 1372 1373 // If this is a selectcc, check to see if we can simplify the result. 1374 if (SetCCSDNode *SetCC = dyn_cast<SetCCSDNode>(N1)) { 1375 if (ConstantFPSDNode *CFP = 1376 dyn_cast<ConstantFPSDNode>(SetCC->getOperand(1))) 1377 if (CFP->getValue() == 0.0) { // Allow either -0.0 or 0.0 1378 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 1379 if ((SetCC->getCondition() == ISD::SETGE || 1380 SetCC->getCondition() == ISD::SETGT) && 1381 N2 == SetCC->getOperand(0) && N3.getOpcode() == ISD::FNEG && 1382 N3.getOperand(0) == N2) 1383 return getNode(ISD::FABS, VT, N2); 1384 1385 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 1386 if ((SetCC->getCondition() == ISD::SETLT || 1387 SetCC->getCondition() == ISD::SETLE) && 1388 N3 == SetCC->getOperand(0) && N2.getOpcode() == ISD::FNEG && 1389 N2.getOperand(0) == N3) 1390 return getNode(ISD::FABS, VT, N3); 1391 } 1392 // select (setlt X, 0), A, 0 -> and (sra X, size(X)-1), A 1393 if (ConstantSDNode *CN = 1394 dyn_cast<ConstantSDNode>(SetCC->getOperand(1))) 1395 if (CN->getValue() == 0 && N3C && N3C->getValue() == 0) 1396 if (SetCC->getCondition() == ISD::SETLT) { 1397 MVT::ValueType XType = SetCC->getOperand(0).getValueType(); 1398 MVT::ValueType AType = N2.getValueType(); 1399 if (XType >= AType) { 1400 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 1401 // single-bit constant. FIXME: remove once the dag combiner 1402 // exists. 1403 if (ConstantSDNode *AC = dyn_cast<ConstantSDNode>(N2)) 1404 if ((AC->getValue() & (AC->getValue()-1)) == 0) { 1405 unsigned ShCtV = Log2_64(AC->getValue()); 1406 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1; 1407 SDOperand ShCt = getConstant(ShCtV, TLI.getShiftAmountTy()); 1408 SDOperand Shift = getNode(ISD::SRL, XType, 1409 SetCC->getOperand(0), ShCt); 1410 if (XType > AType) 1411 Shift = getNode(ISD::TRUNCATE, AType, Shift); 1412 return getNode(ISD::AND, AType, Shift, N2); 1413 } 1414 1415 1416 SDOperand Shift = getNode(ISD::SRA, XType, SetCC->getOperand(0), 1417 getConstant(MVT::getSizeInBits(XType)-1, 1418 TLI.getShiftAmountTy())); 1419 if (XType > AType) 1420 Shift = getNode(ISD::TRUNCATE, AType, Shift); 1421 return getNode(ISD::AND, AType, Shift, N2); 1422 } 1423 } 1424 } 1425 break; 1426 case ISD::BRCOND: 1427 if (N2C) 1428 if (N2C->getValue()) // Unconditional branch 1429 return getNode(ISD::BR, MVT::Other, N1, N3); 1430 else 1431 return N1; // Never-taken branch 1432 break; 1433 } 1434 1435 std::vector<SDOperand> Ops; 1436 Ops.reserve(3); 1437 Ops.push_back(N1); 1438 Ops.push_back(N2); 1439 Ops.push_back(N3); 1440 1441 // Memoize nodes. 1442 SDNode *&N = OneResultNodes[std::make_pair(Opcode, std::make_pair(VT, Ops))]; 1443 if (N) return SDOperand(N, 0); 1444 1445 N = new SDNode(Opcode, N1, N2, N3); 1446 N->setValueTypes(VT); 1447 AllNodes.push_back(N); 1448 return SDOperand(N, 0); 1449} 1450 1451SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, 1452 SDOperand N1, SDOperand N2, SDOperand N3, 1453 SDOperand N4) { 1454 std::vector<SDOperand> Ops; 1455 Ops.reserve(4); 1456 Ops.push_back(N1); 1457 Ops.push_back(N2); 1458 Ops.push_back(N3); 1459 Ops.push_back(N4); 1460 return getNode(Opcode, VT, Ops); 1461} 1462 1463SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, 1464 SDOperand N1, SDOperand N2, SDOperand N3, 1465 SDOperand N4, SDOperand N5) { 1466 std::vector<SDOperand> Ops; 1467 Ops.reserve(5); 1468 Ops.push_back(N1); 1469 Ops.push_back(N2); 1470 Ops.push_back(N3); 1471 Ops.push_back(N4); 1472 Ops.push_back(N5); 1473 return getNode(Opcode, VT, Ops); 1474} 1475 1476 1477SDOperand SelectionDAG::getSrcValue(const Value *V, int Offset) { 1478 assert((!V || isa<PointerType>(V->getType())) && 1479 "SrcValue is not a pointer?"); 1480 SDNode *&N = ValueNodes[std::make_pair(V, Offset)]; 1481 if (N) return SDOperand(N, 0); 1482 1483 N = new SrcValueSDNode(V, Offset); 1484 AllNodes.push_back(N); 1485 return SDOperand(N, 0); 1486} 1487 1488SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, 1489 std::vector<SDOperand> &Ops) { 1490 switch (Ops.size()) { 1491 case 0: return getNode(Opcode, VT); 1492 case 1: return getNode(Opcode, VT, Ops[0]); 1493 case 2: return getNode(Opcode, VT, Ops[0], Ops[1]); 1494 case 3: return getNode(Opcode, VT, Ops[0], Ops[1], Ops[2]); 1495 default: break; 1496 } 1497 1498 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Ops[1].Val); 1499 switch (Opcode) { 1500 default: break; 1501 case ISD::BRCONDTWOWAY: 1502 if (N1C) 1503 if (N1C->getValue()) // Unconditional branch to true dest. 1504 return getNode(ISD::BR, MVT::Other, Ops[0], Ops[2]); 1505 else // Unconditional branch to false dest. 1506 return getNode(ISD::BR, MVT::Other, Ops[0], Ops[3]); 1507 break; 1508 1509 case ISD::TRUNCSTORE: { 1510 assert(Ops.size() == 5 && "TRUNCSTORE takes 5 operands!"); 1511 MVT::ValueType EVT = cast<VTSDNode>(Ops[4])->getVT(); 1512#if 0 // FIXME: If the target supports EVT natively, convert to a truncate/store 1513 // If this is a truncating store of a constant, convert to the desired type 1514 // and store it instead. 1515 if (isa<Constant>(Ops[0])) { 1516 SDOperand Op = getNode(ISD::TRUNCATE, EVT, N1); 1517 if (isa<Constant>(Op)) 1518 N1 = Op; 1519 } 1520 // Also for ConstantFP? 1521#endif 1522 if (Ops[0].getValueType() == EVT) // Normal store? 1523 return getNode(ISD::STORE, VT, Ops[0], Ops[1], Ops[2], Ops[3]); 1524 assert(Ops[1].getValueType() > EVT && "Not a truncation?"); 1525 assert(MVT::isInteger(Ops[1].getValueType()) == MVT::isInteger(EVT) && 1526 "Can't do FP-INT conversion!"); 1527 break; 1528 } 1529 } 1530 1531 // Memoize nodes. 1532 SDNode *&N = OneResultNodes[std::make_pair(Opcode, std::make_pair(VT, Ops))]; 1533 if (N) return SDOperand(N, 0); 1534 N = new SDNode(Opcode, Ops); 1535 N->setValueTypes(VT); 1536 AllNodes.push_back(N); 1537 return SDOperand(N, 0); 1538} 1539 1540SDOperand SelectionDAG::getNode(unsigned Opcode, 1541 std::vector<MVT::ValueType> &ResultTys, 1542 std::vector<SDOperand> &Ops) { 1543 if (ResultTys.size() == 1) 1544 return getNode(Opcode, ResultTys[0], Ops); 1545 1546 switch (Opcode) { 1547 case ISD::EXTLOAD: 1548 case ISD::SEXTLOAD: 1549 case ISD::ZEXTLOAD: { 1550 MVT::ValueType EVT = cast<VTSDNode>(Ops[3])->getVT(); 1551 assert(Ops.size() == 4 && ResultTys.size() == 2 && "Bad *EXTLOAD!"); 1552 // If they are asking for an extending load from/to the same thing, return a 1553 // normal load. 1554 if (ResultTys[0] == EVT) 1555 return getLoad(ResultTys[0], Ops[0], Ops[1], Ops[2]); 1556 assert(EVT < ResultTys[0] && 1557 "Should only be an extending load, not truncating!"); 1558 assert((Opcode == ISD::EXTLOAD || MVT::isInteger(ResultTys[0])) && 1559 "Cannot sign/zero extend a FP load!"); 1560 assert(MVT::isInteger(ResultTys[0]) == MVT::isInteger(EVT) && 1561 "Cannot convert from FP to Int or Int -> FP!"); 1562 break; 1563 } 1564 1565 // FIXME: figure out how to safely handle things like 1566 // int foo(int x) { return 1 << (x & 255); } 1567 // int bar() { return foo(256); } 1568#if 0 1569 case ISD::SRA_PARTS: 1570 case ISD::SRL_PARTS: 1571 case ISD::SHL_PARTS: 1572 if (N3.getOpcode() == ISD::SIGN_EXTEND_INREG && 1573 cast<VTSDNode>(N3.getOperand(1))->getVT() != MVT::i1) 1574 return getNode(Opcode, VT, N1, N2, N3.getOperand(0)); 1575 else if (N3.getOpcode() == ISD::AND) 1576 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(N3.getOperand(1))) { 1577 // If the and is only masking out bits that cannot effect the shift, 1578 // eliminate the and. 1579 unsigned NumBits = MVT::getSizeInBits(VT)*2; 1580 if ((AndRHS->getValue() & (NumBits-1)) == NumBits-1) 1581 return getNode(Opcode, VT, N1, N2, N3.getOperand(0)); 1582 } 1583 break; 1584#endif 1585 } 1586 1587 // Memoize the node. 1588 SDNode *&N = ArbitraryNodes[std::make_pair(Opcode, std::make_pair(ResultTys, 1589 Ops))]; 1590 if (N) return SDOperand(N, 0); 1591 N = new SDNode(Opcode, Ops); 1592 N->setValueTypes(ResultTys); 1593 AllNodes.push_back(N); 1594 return SDOperand(N, 0); 1595} 1596 1597/// hasNUsesOfValue - Return true if there are exactly NUSES uses of the 1598/// indicated value. This method ignores uses of other values defined by this 1599/// operation. 1600bool SDNode::hasNUsesOfValue(unsigned NUses, unsigned Value) { 1601 assert(Value < getNumValues() && "Bad value!"); 1602 1603 // If there is only one value, this is easy. 1604 if (getNumValues() == 1) 1605 return use_size() == NUses; 1606 if (Uses.size() < NUses) return false; 1607 1608 SDOperand TheValue(this, Value); 1609 1610 std::set<SDNode*> UsersHandled; 1611 1612 for (std::vector<SDNode*>::iterator UI = Uses.begin(), E = Uses.end(); 1613 UI != E; ++UI) { 1614 SDNode *User = *UI; 1615 if (User->getNumOperands() == 1 || 1616 UsersHandled.insert(User).second) // First time we've seen this? 1617 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 1618 if (User->getOperand(i) == TheValue) { 1619 if (NUses == 0) 1620 return false; // too many uses 1621 --NUses; 1622 } 1623 } 1624 1625 // Found exactly the right number of uses? 1626 return NUses == 0; 1627} 1628 1629 1630const char *SDNode::getOperationName() const { 1631 switch (getOpcode()) { 1632 default: return "<<Unknown>>"; 1633 case ISD::PCMARKER: return "PCMarker"; 1634 case ISD::SRCVALUE: return "SrcValue"; 1635 case ISD::EntryToken: return "EntryToken"; 1636 case ISD::TokenFactor: return "TokenFactor"; 1637 case ISD::Constant: return "Constant"; 1638 case ISD::ConstantFP: return "ConstantFP"; 1639 case ISD::GlobalAddress: return "GlobalAddress"; 1640 case ISD::FrameIndex: return "FrameIndex"; 1641 case ISD::BasicBlock: return "BasicBlock"; 1642 case ISD::ExternalSymbol: return "ExternalSymbol"; 1643 case ISD::ConstantPool: return "ConstantPoolIndex"; 1644 case ISD::CopyToReg: return "CopyToReg"; 1645 case ISD::CopyFromReg: return "CopyFromReg"; 1646 case ISD::ImplicitDef: return "ImplicitDef"; 1647 case ISD::UNDEF: return "undef"; 1648 1649 // Unary operators 1650 case ISD::FABS: return "fabs"; 1651 case ISD::FNEG: return "fneg"; 1652 case ISD::FSQRT: return "fsqrt"; 1653 case ISD::FSIN: return "fsin"; 1654 case ISD::FCOS: return "fcos"; 1655 1656 // Binary operators 1657 case ISD::ADD: return "add"; 1658 case ISD::SUB: return "sub"; 1659 case ISD::MUL: return "mul"; 1660 case ISD::MULHU: return "mulhu"; 1661 case ISD::MULHS: return "mulhs"; 1662 case ISD::SDIV: return "sdiv"; 1663 case ISD::UDIV: return "udiv"; 1664 case ISD::SREM: return "srem"; 1665 case ISD::UREM: return "urem"; 1666 case ISD::AND: return "and"; 1667 case ISD::OR: return "or"; 1668 case ISD::XOR: return "xor"; 1669 case ISD::SHL: return "shl"; 1670 case ISD::SRA: return "sra"; 1671 case ISD::SRL: return "srl"; 1672 1673 case ISD::SELECT: return "select"; 1674 case ISD::ADD_PARTS: return "add_parts"; 1675 case ISD::SUB_PARTS: return "sub_parts"; 1676 case ISD::SHL_PARTS: return "shl_parts"; 1677 case ISD::SRA_PARTS: return "sra_parts"; 1678 case ISD::SRL_PARTS: return "srl_parts"; 1679 1680 // Conversion operators. 1681 case ISD::SIGN_EXTEND: return "sign_extend"; 1682 case ISD::ZERO_EXTEND: return "zero_extend"; 1683 case ISD::SIGN_EXTEND_INREG: return "sign_extend_inreg"; 1684 case ISD::TRUNCATE: return "truncate"; 1685 case ISD::FP_ROUND: return "fp_round"; 1686 case ISD::FP_ROUND_INREG: return "fp_round_inreg"; 1687 case ISD::FP_EXTEND: return "fp_extend"; 1688 1689 case ISD::SINT_TO_FP: return "sint_to_fp"; 1690 case ISD::UINT_TO_FP: return "uint_to_fp"; 1691 case ISD::FP_TO_SINT: return "fp_to_sint"; 1692 case ISD::FP_TO_UINT: return "fp_to_uint"; 1693 1694 // Control flow instructions 1695 case ISD::BR: return "br"; 1696 case ISD::BRCOND: return "brcond"; 1697 case ISD::BRCONDTWOWAY: return "brcondtwoway"; 1698 case ISD::RET: return "ret"; 1699 case ISD::CALL: return "call"; 1700 case ISD::TAILCALL:return "tailcall"; 1701 case ISD::CALLSEQ_START: return "callseq_start"; 1702 case ISD::CALLSEQ_END: return "callseq_end"; 1703 1704 // Other operators 1705 case ISD::LOAD: return "load"; 1706 case ISD::STORE: return "store"; 1707 case ISD::EXTLOAD: return "extload"; 1708 case ISD::SEXTLOAD: return "sextload"; 1709 case ISD::ZEXTLOAD: return "zextload"; 1710 case ISD::TRUNCSTORE: return "truncstore"; 1711 1712 case ISD::DYNAMIC_STACKALLOC: return "dynamic_stackalloc"; 1713 case ISD::EXTRACT_ELEMENT: return "extract_element"; 1714 case ISD::BUILD_PAIR: return "build_pair"; 1715 case ISD::MEMSET: return "memset"; 1716 case ISD::MEMCPY: return "memcpy"; 1717 case ISD::MEMMOVE: return "memmove"; 1718 1719 // Bit counting 1720 case ISD::CTPOP: return "ctpop"; 1721 case ISD::CTTZ: return "cttz"; 1722 case ISD::CTLZ: return "ctlz"; 1723 1724 // IO Intrinsics 1725 case ISD::READPORT: return "readport"; 1726 case ISD::WRITEPORT: return "writeport"; 1727 case ISD::READIO: return "readio"; 1728 case ISD::WRITEIO: return "writeio"; 1729 1730 case ISD::SETCC: 1731 const SetCCSDNode *SetCC = cast<SetCCSDNode>(this); 1732 switch (SetCC->getCondition()) { 1733 default: assert(0 && "Unknown setcc condition!"); 1734 case ISD::SETOEQ: return "setcc:setoeq"; 1735 case ISD::SETOGT: return "setcc:setogt"; 1736 case ISD::SETOGE: return "setcc:setoge"; 1737 case ISD::SETOLT: return "setcc:setolt"; 1738 case ISD::SETOLE: return "setcc:setole"; 1739 case ISD::SETONE: return "setcc:setone"; 1740 1741 case ISD::SETO: return "setcc:seto"; 1742 case ISD::SETUO: return "setcc:setuo"; 1743 case ISD::SETUEQ: return "setcc:setue"; 1744 case ISD::SETUGT: return "setcc:setugt"; 1745 case ISD::SETUGE: return "setcc:setuge"; 1746 case ISD::SETULT: return "setcc:setult"; 1747 case ISD::SETULE: return "setcc:setule"; 1748 case ISD::SETUNE: return "setcc:setune"; 1749 1750 case ISD::SETEQ: return "setcc:seteq"; 1751 case ISD::SETGT: return "setcc:setgt"; 1752 case ISD::SETGE: return "setcc:setge"; 1753 case ISD::SETLT: return "setcc:setlt"; 1754 case ISD::SETLE: return "setcc:setle"; 1755 case ISD::SETNE: return "setcc:setne"; 1756 } 1757 } 1758} 1759 1760void SDNode::dump() const { 1761 std::cerr << (void*)this << ": "; 1762 1763 for (unsigned i = 0, e = getNumValues(); i != e; ++i) { 1764 if (i) std::cerr << ","; 1765 if (getValueType(i) == MVT::Other) 1766 std::cerr << "ch"; 1767 else 1768 std::cerr << MVT::getValueTypeString(getValueType(i)); 1769 } 1770 std::cerr << " = " << getOperationName(); 1771 1772 std::cerr << " "; 1773 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1774 if (i) std::cerr << ", "; 1775 std::cerr << (void*)getOperand(i).Val; 1776 if (unsigned RN = getOperand(i).ResNo) 1777 std::cerr << ":" << RN; 1778 } 1779 1780 if (const ConstantSDNode *CSDN = dyn_cast<ConstantSDNode>(this)) { 1781 std::cerr << "<" << CSDN->getValue() << ">"; 1782 } else if (const ConstantFPSDNode *CSDN = dyn_cast<ConstantFPSDNode>(this)) { 1783 std::cerr << "<" << CSDN->getValue() << ">"; 1784 } else if (const GlobalAddressSDNode *GADN = 1785 dyn_cast<GlobalAddressSDNode>(this)) { 1786 std::cerr << "<"; 1787 WriteAsOperand(std::cerr, GADN->getGlobal()) << ">"; 1788 } else if (const FrameIndexSDNode *FIDN = dyn_cast<FrameIndexSDNode>(this)) { 1789 std::cerr << "<" << FIDN->getIndex() << ">"; 1790 } else if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(this)){ 1791 std::cerr << "<" << CP->getIndex() << ">"; 1792 } else if (const BasicBlockSDNode *BBDN = dyn_cast<BasicBlockSDNode>(this)) { 1793 std::cerr << "<"; 1794 const Value *LBB = (const Value*)BBDN->getBasicBlock()->getBasicBlock(); 1795 if (LBB) 1796 std::cerr << LBB->getName() << " "; 1797 std::cerr << (const void*)BBDN->getBasicBlock() << ">"; 1798 } else if (const RegSDNode *C2V = dyn_cast<RegSDNode>(this)) { 1799 std::cerr << "<reg #" << C2V->getReg() << ">"; 1800 } else if (const ExternalSymbolSDNode *ES = 1801 dyn_cast<ExternalSymbolSDNode>(this)) { 1802 std::cerr << "'" << ES->getSymbol() << "'"; 1803 } else if (const SrcValueSDNode *M = dyn_cast<SrcValueSDNode>(this)) { 1804 if (M->getValue()) 1805 std::cerr << "<" << M->getValue() << ":" << M->getOffset() << ">"; 1806 else 1807 std::cerr << "<null:" << M->getOffset() << ">"; 1808 } 1809} 1810 1811static void DumpNodes(SDNode *N, unsigned indent) { 1812 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1813 if (N->getOperand(i).Val->hasOneUse()) 1814 DumpNodes(N->getOperand(i).Val, indent+2); 1815 else 1816 std::cerr << "\n" << std::string(indent+2, ' ') 1817 << (void*)N->getOperand(i).Val << ": <multiple use>"; 1818 1819 1820 std::cerr << "\n" << std::string(indent, ' '); 1821 N->dump(); 1822} 1823 1824void SelectionDAG::dump() const { 1825 std::cerr << "SelectionDAG has " << AllNodes.size() << " nodes:"; 1826 std::vector<SDNode*> Nodes(AllNodes); 1827 std::sort(Nodes.begin(), Nodes.end()); 1828 1829 for (unsigned i = 0, e = Nodes.size(); i != e; ++i) { 1830 if (!Nodes[i]->hasOneUse() && Nodes[i] != getRoot().Val) 1831 DumpNodes(Nodes[i], 2); 1832 } 1833 1834 DumpNodes(getRoot().Val, 2); 1835 1836 std::cerr << "\n\n"; 1837} 1838 1839