SelectionDAG.cpp revision 0dc4045bd27c177416745d2e72277b0a92c3ab83
1//===-- SelectionDAG.cpp - Implement the SelectionDAG data structures -----===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAG class. 11// 12//===----------------------------------------------------------------------===// 13#include "llvm/CodeGen/SelectionDAG.h" 14#include "llvm/Constants.h" 15#include "llvm/Analysis/ValueTracking.h" 16#include "llvm/GlobalAlias.h" 17#include "llvm/GlobalVariable.h" 18#include "llvm/Intrinsics.h" 19#include "llvm/DerivedTypes.h" 20#include "llvm/Assembly/Writer.h" 21#include "llvm/CallingConv.h" 22#include "llvm/CodeGen/MachineBasicBlock.h" 23#include "llvm/CodeGen/MachineConstantPool.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/MachineModuleInfo.h" 26#include "llvm/CodeGen/PseudoSourceValue.h" 27#include "llvm/Target/TargetRegisterInfo.h" 28#include "llvm/Target/TargetData.h" 29#include "llvm/Target/TargetLowering.h" 30#include "llvm/Target/TargetInstrInfo.h" 31#include "llvm/Target/TargetMachine.h" 32#include "llvm/Support/CommandLine.h" 33#include "llvm/Support/MathExtras.h" 34#include "llvm/Support/raw_ostream.h" 35#include "llvm/ADT/SetVector.h" 36#include "llvm/ADT/SmallPtrSet.h" 37#include "llvm/ADT/SmallSet.h" 38#include "llvm/ADT/SmallVector.h" 39#include "llvm/ADT/StringExtras.h" 40#include <algorithm> 41#include <cmath> 42using namespace llvm; 43 44/// makeVTList - Return an instance of the SDVTList struct initialized with the 45/// specified members. 46static SDVTList makeVTList(const MVT *VTs, unsigned NumVTs) { 47 SDVTList Res = {VTs, NumVTs}; 48 return Res; 49} 50 51static const fltSemantics *MVTToAPFloatSemantics(MVT VT) { 52 switch (VT.getSimpleVT()) { 53 default: assert(0 && "Unknown FP format"); 54 case MVT::f32: return &APFloat::IEEEsingle; 55 case MVT::f64: return &APFloat::IEEEdouble; 56 case MVT::f80: return &APFloat::x87DoubleExtended; 57 case MVT::f128: return &APFloat::IEEEquad; 58 case MVT::ppcf128: return &APFloat::PPCDoubleDouble; 59 } 60} 61 62SelectionDAG::DAGUpdateListener::~DAGUpdateListener() {} 63 64//===----------------------------------------------------------------------===// 65// ConstantFPSDNode Class 66//===----------------------------------------------------------------------===// 67 68/// isExactlyValue - We don't rely on operator== working on double values, as 69/// it returns true for things that are clearly not equal, like -0.0 and 0.0. 70/// As such, this method can be used to do an exact bit-for-bit comparison of 71/// two floating point values. 72bool ConstantFPSDNode::isExactlyValue(const APFloat& V) const { 73 return getValueAPF().bitwiseIsEqual(V); 74} 75 76bool ConstantFPSDNode::isValueValidForType(MVT VT, 77 const APFloat& Val) { 78 assert(VT.isFloatingPoint() && "Can only convert between FP types"); 79 80 // PPC long double cannot be converted to any other type. 81 if (VT == MVT::ppcf128 || 82 &Val.getSemantics() == &APFloat::PPCDoubleDouble) 83 return false; 84 85 // convert modifies in place, so make a copy. 86 APFloat Val2 = APFloat(Val); 87 bool losesInfo; 88 (void) Val2.convert(*MVTToAPFloatSemantics(VT), APFloat::rmNearestTiesToEven, 89 &losesInfo); 90 return !losesInfo; 91} 92 93//===----------------------------------------------------------------------===// 94// ISD Namespace 95//===----------------------------------------------------------------------===// 96 97/// isBuildVectorAllOnes - Return true if the specified node is a 98/// BUILD_VECTOR where all of the elements are ~0 or undef. 99bool ISD::isBuildVectorAllOnes(const SDNode *N) { 100 // Look through a bit convert. 101 if (N->getOpcode() == ISD::BIT_CONVERT) 102 N = N->getOperand(0).getNode(); 103 104 if (N->getOpcode() != ISD::BUILD_VECTOR) return false; 105 106 unsigned i = 0, e = N->getNumOperands(); 107 108 // Skip over all of the undef values. 109 while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF) 110 ++i; 111 112 // Do not accept an all-undef vector. 113 if (i == e) return false; 114 115 // Do not accept build_vectors that aren't all constants or which have non-~0 116 // elements. 117 SDValue NotZero = N->getOperand(i); 118 if (isa<ConstantSDNode>(NotZero)) { 119 if (!cast<ConstantSDNode>(NotZero)->isAllOnesValue()) 120 return false; 121 } else if (isa<ConstantFPSDNode>(NotZero)) { 122 if (!cast<ConstantFPSDNode>(NotZero)->getValueAPF(). 123 bitcastToAPInt().isAllOnesValue()) 124 return false; 125 } else 126 return false; 127 128 // Okay, we have at least one ~0 value, check to see if the rest match or are 129 // undefs. 130 for (++i; i != e; ++i) 131 if (N->getOperand(i) != NotZero && 132 N->getOperand(i).getOpcode() != ISD::UNDEF) 133 return false; 134 return true; 135} 136 137 138/// isBuildVectorAllZeros - Return true if the specified node is a 139/// BUILD_VECTOR where all of the elements are 0 or undef. 140bool ISD::isBuildVectorAllZeros(const SDNode *N) { 141 // Look through a bit convert. 142 if (N->getOpcode() == ISD::BIT_CONVERT) 143 N = N->getOperand(0).getNode(); 144 145 if (N->getOpcode() != ISD::BUILD_VECTOR) return false; 146 147 unsigned i = 0, e = N->getNumOperands(); 148 149 // Skip over all of the undef values. 150 while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF) 151 ++i; 152 153 // Do not accept an all-undef vector. 154 if (i == e) return false; 155 156 // Do not accept build_vectors that aren't all constants or which have non-~0 157 // elements. 158 SDValue Zero = N->getOperand(i); 159 if (isa<ConstantSDNode>(Zero)) { 160 if (!cast<ConstantSDNode>(Zero)->isNullValue()) 161 return false; 162 } else if (isa<ConstantFPSDNode>(Zero)) { 163 if (!cast<ConstantFPSDNode>(Zero)->getValueAPF().isPosZero()) 164 return false; 165 } else 166 return false; 167 168 // Okay, we have at least one ~0 value, check to see if the rest match or are 169 // undefs. 170 for (++i; i != e; ++i) 171 if (N->getOperand(i) != Zero && 172 N->getOperand(i).getOpcode() != ISD::UNDEF) 173 return false; 174 return true; 175} 176 177/// isScalarToVector - Return true if the specified node is a 178/// ISD::SCALAR_TO_VECTOR node or a BUILD_VECTOR node where only the low 179/// element is not an undef. 180bool ISD::isScalarToVector(const SDNode *N) { 181 if (N->getOpcode() == ISD::SCALAR_TO_VECTOR) 182 return true; 183 184 if (N->getOpcode() != ISD::BUILD_VECTOR) 185 return false; 186 if (N->getOperand(0).getOpcode() == ISD::UNDEF) 187 return false; 188 unsigned NumElems = N->getNumOperands(); 189 for (unsigned i = 1; i < NumElems; ++i) { 190 SDValue V = N->getOperand(i); 191 if (V.getOpcode() != ISD::UNDEF) 192 return false; 193 } 194 return true; 195} 196 197 198/// isDebugLabel - Return true if the specified node represents a debug 199/// label (i.e. ISD::DBG_LABEL or TargetInstrInfo::DBG_LABEL node). 200bool ISD::isDebugLabel(const SDNode *N) { 201 SDValue Zero; 202 if (N->getOpcode() == ISD::DBG_LABEL) 203 return true; 204 if (N->isMachineOpcode() && 205 N->getMachineOpcode() == TargetInstrInfo::DBG_LABEL) 206 return true; 207 return false; 208} 209 210/// getSetCCSwappedOperands - Return the operation corresponding to (Y op X) 211/// when given the operation for (X op Y). 212ISD::CondCode ISD::getSetCCSwappedOperands(ISD::CondCode Operation) { 213 // To perform this operation, we just need to swap the L and G bits of the 214 // operation. 215 unsigned OldL = (Operation >> 2) & 1; 216 unsigned OldG = (Operation >> 1) & 1; 217 return ISD::CondCode((Operation & ~6) | // Keep the N, U, E bits 218 (OldL << 1) | // New G bit 219 (OldG << 2)); // New L bit. 220} 221 222/// getSetCCInverse - Return the operation corresponding to !(X op Y), where 223/// 'op' is a valid SetCC operation. 224ISD::CondCode ISD::getSetCCInverse(ISD::CondCode Op, bool isInteger) { 225 unsigned Operation = Op; 226 if (isInteger) 227 Operation ^= 7; // Flip L, G, E bits, but not U. 228 else 229 Operation ^= 15; // Flip all of the condition bits. 230 231 if (Operation > ISD::SETTRUE2) 232 Operation &= ~8; // Don't let N and U bits get set. 233 234 return ISD::CondCode(Operation); 235} 236 237 238/// isSignedOp - For an integer comparison, return 1 if the comparison is a 239/// signed operation and 2 if the result is an unsigned comparison. Return zero 240/// if the operation does not depend on the sign of the input (setne and seteq). 241static int isSignedOp(ISD::CondCode Opcode) { 242 switch (Opcode) { 243 default: assert(0 && "Illegal integer setcc operation!"); 244 case ISD::SETEQ: 245 case ISD::SETNE: return 0; 246 case ISD::SETLT: 247 case ISD::SETLE: 248 case ISD::SETGT: 249 case ISD::SETGE: return 1; 250 case ISD::SETULT: 251 case ISD::SETULE: 252 case ISD::SETUGT: 253 case ISD::SETUGE: return 2; 254 } 255} 256 257/// getSetCCOrOperation - Return the result of a logical OR between different 258/// comparisons of identical values: ((X op1 Y) | (X op2 Y)). This function 259/// returns SETCC_INVALID if it is not possible to represent the resultant 260/// comparison. 261ISD::CondCode ISD::getSetCCOrOperation(ISD::CondCode Op1, ISD::CondCode Op2, 262 bool isInteger) { 263 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 264 // Cannot fold a signed integer setcc with an unsigned integer setcc. 265 return ISD::SETCC_INVALID; 266 267 unsigned Op = Op1 | Op2; // Combine all of the condition bits. 268 269 // If the N and U bits get set then the resultant comparison DOES suddenly 270 // care about orderedness, and is true when ordered. 271 if (Op > ISD::SETTRUE2) 272 Op &= ~16; // Clear the U bit if the N bit is set. 273 274 // Canonicalize illegal integer setcc's. 275 if (isInteger && Op == ISD::SETUNE) // e.g. SETUGT | SETULT 276 Op = ISD::SETNE; 277 278 return ISD::CondCode(Op); 279} 280 281/// getSetCCAndOperation - Return the result of a logical AND between different 282/// comparisons of identical values: ((X op1 Y) & (X op2 Y)). This 283/// function returns zero if it is not possible to represent the resultant 284/// comparison. 285ISD::CondCode ISD::getSetCCAndOperation(ISD::CondCode Op1, ISD::CondCode Op2, 286 bool isInteger) { 287 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 288 // Cannot fold a signed setcc with an unsigned setcc. 289 return ISD::SETCC_INVALID; 290 291 // Combine all of the condition bits. 292 ISD::CondCode Result = ISD::CondCode(Op1 & Op2); 293 294 // Canonicalize illegal integer setcc's. 295 if (isInteger) { 296 switch (Result) { 297 default: break; 298 case ISD::SETUO : Result = ISD::SETFALSE; break; // SETUGT & SETULT 299 case ISD::SETOEQ: // SETEQ & SETU[LG]E 300 case ISD::SETUEQ: Result = ISD::SETEQ ; break; // SETUGE & SETULE 301 case ISD::SETOLT: Result = ISD::SETULT ; break; // SETULT & SETNE 302 case ISD::SETOGT: Result = ISD::SETUGT ; break; // SETUGT & SETNE 303 } 304 } 305 306 return Result; 307} 308 309const TargetMachine &SelectionDAG::getTarget() const { 310 return MF->getTarget(); 311} 312 313//===----------------------------------------------------------------------===// 314// SDNode Profile Support 315//===----------------------------------------------------------------------===// 316 317/// AddNodeIDOpcode - Add the node opcode to the NodeID data. 318/// 319static void AddNodeIDOpcode(FoldingSetNodeID &ID, unsigned OpC) { 320 ID.AddInteger(OpC); 321} 322 323/// AddNodeIDValueTypes - Value type lists are intern'd so we can represent them 324/// solely with their pointer. 325static void AddNodeIDValueTypes(FoldingSetNodeID &ID, SDVTList VTList) { 326 ID.AddPointer(VTList.VTs); 327} 328 329/// AddNodeIDOperands - Various routines for adding operands to the NodeID data. 330/// 331static void AddNodeIDOperands(FoldingSetNodeID &ID, 332 const SDValue *Ops, unsigned NumOps) { 333 for (; NumOps; --NumOps, ++Ops) { 334 ID.AddPointer(Ops->getNode()); 335 ID.AddInteger(Ops->getResNo()); 336 } 337} 338 339/// AddNodeIDOperands - Various routines for adding operands to the NodeID data. 340/// 341static void AddNodeIDOperands(FoldingSetNodeID &ID, 342 const SDUse *Ops, unsigned NumOps) { 343 for (; NumOps; --NumOps, ++Ops) { 344 ID.AddPointer(Ops->getVal()); 345 ID.AddInteger(Ops->getSDValue().getResNo()); 346 } 347} 348 349static void AddNodeIDNode(FoldingSetNodeID &ID, 350 unsigned short OpC, SDVTList VTList, 351 const SDValue *OpList, unsigned N) { 352 AddNodeIDOpcode(ID, OpC); 353 AddNodeIDValueTypes(ID, VTList); 354 AddNodeIDOperands(ID, OpList, N); 355} 356 357/// AddNodeIDCustom - If this is an SDNode with special info, add this info to 358/// the NodeID data. 359static void AddNodeIDCustom(FoldingSetNodeID &ID, const SDNode *N) { 360 switch (N->getOpcode()) { 361 default: break; // Normal nodes don't need extra info. 362 case ISD::ARG_FLAGS: 363 ID.AddInteger(cast<ARG_FLAGSSDNode>(N)->getArgFlags().getRawBits()); 364 break; 365 case ISD::TargetConstant: 366 case ISD::Constant: 367 ID.AddPointer(cast<ConstantSDNode>(N)->getConstantIntValue()); 368 break; 369 case ISD::TargetConstantFP: 370 case ISD::ConstantFP: { 371 ID.AddPointer(cast<ConstantFPSDNode>(N)->getConstantFPValue()); 372 break; 373 } 374 case ISD::TargetGlobalAddress: 375 case ISD::GlobalAddress: 376 case ISD::TargetGlobalTLSAddress: 377 case ISD::GlobalTLSAddress: { 378 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(N); 379 ID.AddPointer(GA->getGlobal()); 380 ID.AddInteger(GA->getOffset()); 381 break; 382 } 383 case ISD::BasicBlock: 384 ID.AddPointer(cast<BasicBlockSDNode>(N)->getBasicBlock()); 385 break; 386 case ISD::Register: 387 ID.AddInteger(cast<RegisterSDNode>(N)->getReg()); 388 break; 389 case ISD::DBG_STOPPOINT: { 390 const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(N); 391 ID.AddInteger(DSP->getLine()); 392 ID.AddInteger(DSP->getColumn()); 393 ID.AddPointer(DSP->getCompileUnit()); 394 break; 395 } 396 case ISD::SRCVALUE: 397 ID.AddPointer(cast<SrcValueSDNode>(N)->getValue()); 398 break; 399 case ISD::MEMOPERAND: { 400 const MachineMemOperand &MO = cast<MemOperandSDNode>(N)->MO; 401 MO.Profile(ID); 402 break; 403 } 404 case ISD::FrameIndex: 405 case ISD::TargetFrameIndex: 406 ID.AddInteger(cast<FrameIndexSDNode>(N)->getIndex()); 407 break; 408 case ISD::JumpTable: 409 case ISD::TargetJumpTable: 410 ID.AddInteger(cast<JumpTableSDNode>(N)->getIndex()); 411 break; 412 case ISD::ConstantPool: 413 case ISD::TargetConstantPool: { 414 const ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(N); 415 ID.AddInteger(CP->getAlignment()); 416 ID.AddInteger(CP->getOffset()); 417 if (CP->isMachineConstantPoolEntry()) 418 CP->getMachineCPVal()->AddSelectionDAGCSEId(ID); 419 else 420 ID.AddPointer(CP->getConstVal()); 421 break; 422 } 423 case ISD::CALL: { 424 const CallSDNode *Call = cast<CallSDNode>(N); 425 ID.AddInteger(Call->getCallingConv()); 426 ID.AddInteger(Call->isVarArg()); 427 break; 428 } 429 case ISD::LOAD: { 430 const LoadSDNode *LD = cast<LoadSDNode>(N); 431 ID.AddInteger(LD->getAddressingMode()); 432 ID.AddInteger(LD->getExtensionType()); 433 ID.AddInteger(LD->getMemoryVT().getRawBits()); 434 ID.AddInteger(LD->getRawFlags()); 435 break; 436 } 437 case ISD::STORE: { 438 const StoreSDNode *ST = cast<StoreSDNode>(N); 439 ID.AddInteger(ST->getAddressingMode()); 440 ID.AddInteger(ST->isTruncatingStore()); 441 ID.AddInteger(ST->getMemoryVT().getRawBits()); 442 ID.AddInteger(ST->getRawFlags()); 443 break; 444 } 445 case ISD::ATOMIC_CMP_SWAP_8: 446 case ISD::ATOMIC_SWAP_8: 447 case ISD::ATOMIC_LOAD_ADD_8: 448 case ISD::ATOMIC_LOAD_SUB_8: 449 case ISD::ATOMIC_LOAD_AND_8: 450 case ISD::ATOMIC_LOAD_OR_8: 451 case ISD::ATOMIC_LOAD_XOR_8: 452 case ISD::ATOMIC_LOAD_NAND_8: 453 case ISD::ATOMIC_LOAD_MIN_8: 454 case ISD::ATOMIC_LOAD_MAX_8: 455 case ISD::ATOMIC_LOAD_UMIN_8: 456 case ISD::ATOMIC_LOAD_UMAX_8: 457 case ISD::ATOMIC_CMP_SWAP_16: 458 case ISD::ATOMIC_SWAP_16: 459 case ISD::ATOMIC_LOAD_ADD_16: 460 case ISD::ATOMIC_LOAD_SUB_16: 461 case ISD::ATOMIC_LOAD_AND_16: 462 case ISD::ATOMIC_LOAD_OR_16: 463 case ISD::ATOMIC_LOAD_XOR_16: 464 case ISD::ATOMIC_LOAD_NAND_16: 465 case ISD::ATOMIC_LOAD_MIN_16: 466 case ISD::ATOMIC_LOAD_MAX_16: 467 case ISD::ATOMIC_LOAD_UMIN_16: 468 case ISD::ATOMIC_LOAD_UMAX_16: 469 case ISD::ATOMIC_CMP_SWAP_32: 470 case ISD::ATOMIC_SWAP_32: 471 case ISD::ATOMIC_LOAD_ADD_32: 472 case ISD::ATOMIC_LOAD_SUB_32: 473 case ISD::ATOMIC_LOAD_AND_32: 474 case ISD::ATOMIC_LOAD_OR_32: 475 case ISD::ATOMIC_LOAD_XOR_32: 476 case ISD::ATOMIC_LOAD_NAND_32: 477 case ISD::ATOMIC_LOAD_MIN_32: 478 case ISD::ATOMIC_LOAD_MAX_32: 479 case ISD::ATOMIC_LOAD_UMIN_32: 480 case ISD::ATOMIC_LOAD_UMAX_32: 481 case ISD::ATOMIC_CMP_SWAP_64: 482 case ISD::ATOMIC_SWAP_64: 483 case ISD::ATOMIC_LOAD_ADD_64: 484 case ISD::ATOMIC_LOAD_SUB_64: 485 case ISD::ATOMIC_LOAD_AND_64: 486 case ISD::ATOMIC_LOAD_OR_64: 487 case ISD::ATOMIC_LOAD_XOR_64: 488 case ISD::ATOMIC_LOAD_NAND_64: 489 case ISD::ATOMIC_LOAD_MIN_64: 490 case ISD::ATOMIC_LOAD_MAX_64: 491 case ISD::ATOMIC_LOAD_UMIN_64: 492 case ISD::ATOMIC_LOAD_UMAX_64: { 493 const AtomicSDNode *AT = cast<AtomicSDNode>(N); 494 ID.AddInteger(AT->getRawFlags()); 495 break; 496 } 497 } // end switch (N->getOpcode()) 498} 499 500/// AddNodeIDNode - Generic routine for adding a nodes info to the NodeID 501/// data. 502static void AddNodeIDNode(FoldingSetNodeID &ID, const SDNode *N) { 503 AddNodeIDOpcode(ID, N->getOpcode()); 504 // Add the return value info. 505 AddNodeIDValueTypes(ID, N->getVTList()); 506 // Add the operand info. 507 AddNodeIDOperands(ID, N->op_begin(), N->getNumOperands()); 508 509 // Handle SDNode leafs with special info. 510 AddNodeIDCustom(ID, N); 511} 512 513/// encodeMemSDNodeFlags - Generic routine for computing a value for use in 514/// the CSE map that carries both alignment and volatility information. 515/// 516static inline unsigned 517encodeMemSDNodeFlags(bool isVolatile, unsigned Alignment) { 518 return isVolatile | ((Log2_32(Alignment) + 1) << 1); 519} 520 521//===----------------------------------------------------------------------===// 522// SelectionDAG Class 523//===----------------------------------------------------------------------===// 524 525/// doNotCSE - Return true if CSE should not be performed for this node. 526static bool doNotCSE(SDNode *N) { 527 if (N->getValueType(0) == MVT::Flag) 528 return true; // Never CSE anything that produces a flag. 529 530 switch (N->getOpcode()) { 531 default: break; 532 case ISD::HANDLENODE: 533 case ISD::DBG_LABEL: 534 case ISD::DBG_STOPPOINT: 535 case ISD::EH_LABEL: 536 case ISD::DECLARE: 537 return true; // Never CSE these nodes. 538 } 539 540 // Check that remaining values produced are not flags. 541 for (unsigned i = 1, e = N->getNumValues(); i != e; ++i) 542 if (N->getValueType(i) == MVT::Flag) 543 return true; // Never CSE anything that produces a flag. 544 545 return false; 546} 547 548/// RemoveDeadNodes - This method deletes all unreachable nodes in the 549/// SelectionDAG. 550void SelectionDAG::RemoveDeadNodes() { 551 // Create a dummy node (which is not added to allnodes), that adds a reference 552 // to the root node, preventing it from being deleted. 553 HandleSDNode Dummy(getRoot()); 554 555 SmallVector<SDNode*, 128> DeadNodes; 556 557 // Add all obviously-dead nodes to the DeadNodes worklist. 558 for (allnodes_iterator I = allnodes_begin(), E = allnodes_end(); I != E; ++I) 559 if (I->use_empty()) 560 DeadNodes.push_back(I); 561 562 RemoveDeadNodes(DeadNodes); 563 564 // If the root changed (e.g. it was a dead load, update the root). 565 setRoot(Dummy.getValue()); 566} 567 568/// RemoveDeadNodes - This method deletes the unreachable nodes in the 569/// given list, and any nodes that become unreachable as a result. 570void SelectionDAG::RemoveDeadNodes(SmallVectorImpl<SDNode *> &DeadNodes, 571 DAGUpdateListener *UpdateListener) { 572 573 // Process the worklist, deleting the nodes and adding their uses to the 574 // worklist. 575 while (!DeadNodes.empty()) { 576 SDNode *N = DeadNodes.back(); 577 DeadNodes.pop_back(); 578 579 if (UpdateListener) 580 UpdateListener->NodeDeleted(N, 0); 581 582 // Take the node out of the appropriate CSE map. 583 RemoveNodeFromCSEMaps(N); 584 585 // Next, brutally remove the operand list. This is safe to do, as there are 586 // no cycles in the graph. 587 for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ++I) { 588 SDNode *Operand = I->getVal(); 589 Operand->removeUser(std::distance(N->op_begin(), I), N); 590 591 // Now that we removed this operand, see if there are no uses of it left. 592 if (Operand->use_empty()) 593 DeadNodes.push_back(Operand); 594 } 595 596 if (N->OperandsNeedDelete) 597 delete[] N->OperandList; 598 599 N->OperandList = 0; 600 N->NumOperands = 0; 601 602 // Finally, remove N itself. 603 NodeAllocator.Deallocate(AllNodes.remove(N)); 604 } 605} 606 607void SelectionDAG::RemoveDeadNode(SDNode *N, DAGUpdateListener *UpdateListener){ 608 SmallVector<SDNode*, 16> DeadNodes(1, N); 609 RemoveDeadNodes(DeadNodes, UpdateListener); 610} 611 612void SelectionDAG::DeleteNode(SDNode *N) { 613 assert(N->use_empty() && "Cannot delete a node that is not dead!"); 614 615 // First take this out of the appropriate CSE map. 616 RemoveNodeFromCSEMaps(N); 617 618 // Finally, remove uses due to operands of this node, remove from the 619 // AllNodes list, and delete the node. 620 DeleteNodeNotInCSEMaps(N); 621} 622 623void SelectionDAG::DeleteNodeNotInCSEMaps(SDNode *N) { 624 // Drop all of the operands and decrement used node's use counts. 625 for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ++I) 626 I->getVal()->removeUser(std::distance(N->op_begin(), I), N); 627 628 if (N->OperandsNeedDelete) { 629 delete[] N->OperandList; 630 N->OperandList = 0; 631 } 632 633 assert(N != AllNodes.begin()); 634 NodeAllocator.Deallocate(AllNodes.remove(N)); 635} 636 637/// RemoveNodeFromCSEMaps - Take the specified node out of the CSE map that 638/// correspond to it. This is useful when we're about to delete or repurpose 639/// the node. We don't want future request for structurally identical nodes 640/// to return N anymore. 641bool SelectionDAG::RemoveNodeFromCSEMaps(SDNode *N) { 642 bool Erased = false; 643 switch (N->getOpcode()) { 644 case ISD::EntryToken: 645 assert(0 && "EntryToken should not be in CSEMaps!"); 646 return false; 647 case ISD::HANDLENODE: return false; // noop. 648 case ISD::CONDCODE: 649 assert(CondCodeNodes[cast<CondCodeSDNode>(N)->get()] && 650 "Cond code doesn't exist!"); 651 Erased = CondCodeNodes[cast<CondCodeSDNode>(N)->get()] != 0; 652 CondCodeNodes[cast<CondCodeSDNode>(N)->get()] = 0; 653 break; 654 case ISD::ExternalSymbol: 655 Erased = ExternalSymbols.erase(cast<ExternalSymbolSDNode>(N)->getSymbol()); 656 break; 657 case ISD::TargetExternalSymbol: 658 Erased = 659 TargetExternalSymbols.erase(cast<ExternalSymbolSDNode>(N)->getSymbol()); 660 break; 661 case ISD::VALUETYPE: { 662 MVT VT = cast<VTSDNode>(N)->getVT(); 663 if (VT.isExtended()) { 664 Erased = ExtendedValueTypeNodes.erase(VT); 665 } else { 666 Erased = ValueTypeNodes[VT.getSimpleVT()] != 0; 667 ValueTypeNodes[VT.getSimpleVT()] = 0; 668 } 669 break; 670 } 671 default: 672 // Remove it from the CSE Map. 673 Erased = CSEMap.RemoveNode(N); 674 break; 675 } 676#ifndef NDEBUG 677 // Verify that the node was actually in one of the CSE maps, unless it has a 678 // flag result (which cannot be CSE'd) or is one of the special cases that are 679 // not subject to CSE. 680 if (!Erased && N->getValueType(N->getNumValues()-1) != MVT::Flag && 681 !N->isMachineOpcode() && !doNotCSE(N)) { 682 N->dump(this); 683 cerr << "\n"; 684 assert(0 && "Node is not in map!"); 685 } 686#endif 687 return Erased; 688} 689 690/// AddNonLeafNodeToCSEMaps - Add the specified node back to the CSE maps. It 691/// has been taken out and modified in some way. If the specified node already 692/// exists in the CSE maps, do not modify the maps, but return the existing node 693/// instead. If it doesn't exist, add it and return null. 694/// 695SDNode *SelectionDAG::AddNonLeafNodeToCSEMaps(SDNode *N) { 696 assert(N->getNumOperands() && "This is a leaf node!"); 697 698 if (doNotCSE(N)) 699 return 0; 700 701 SDNode *New = CSEMap.GetOrInsertNode(N); 702 if (New != N) return New; // Node already existed. 703 return 0; 704} 705 706/// FindModifiedNodeSlot - Find a slot for the specified node if its operands 707/// were replaced with those specified. If this node is never memoized, 708/// return null, otherwise return a pointer to the slot it would take. If a 709/// node already exists with these operands, the slot will be non-null. 710SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, SDValue Op, 711 void *&InsertPos) { 712 if (doNotCSE(N)) 713 return 0; 714 715 SDValue Ops[] = { Op }; 716 FoldingSetNodeID ID; 717 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, 1); 718 AddNodeIDCustom(ID, N); 719 return CSEMap.FindNodeOrInsertPos(ID, InsertPos); 720} 721 722/// FindModifiedNodeSlot - Find a slot for the specified node if its operands 723/// were replaced with those specified. If this node is never memoized, 724/// return null, otherwise return a pointer to the slot it would take. If a 725/// node already exists with these operands, the slot will be non-null. 726SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, 727 SDValue Op1, SDValue Op2, 728 void *&InsertPos) { 729 if (doNotCSE(N)) 730 return 0; 731 732 SDValue Ops[] = { Op1, Op2 }; 733 FoldingSetNodeID ID; 734 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, 2); 735 AddNodeIDCustom(ID, N); 736 return CSEMap.FindNodeOrInsertPos(ID, InsertPos); 737} 738 739 740/// FindModifiedNodeSlot - Find a slot for the specified node if its operands 741/// were replaced with those specified. If this node is never memoized, 742/// return null, otherwise return a pointer to the slot it would take. If a 743/// node already exists with these operands, the slot will be non-null. 744SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, 745 const SDValue *Ops,unsigned NumOps, 746 void *&InsertPos) { 747 if (doNotCSE(N)) 748 return 0; 749 750 FoldingSetNodeID ID; 751 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, NumOps); 752 AddNodeIDCustom(ID, N); 753 return CSEMap.FindNodeOrInsertPos(ID, InsertPos); 754} 755 756/// VerifyNode - Sanity check the given node. Aborts if it is invalid. 757void SelectionDAG::VerifyNode(SDNode *N) { 758 switch (N->getOpcode()) { 759 default: 760 break; 761 case ISD::BUILD_VECTOR: { 762 assert(N->getNumValues() == 1 && "Too many results for BUILD_VECTOR!"); 763 assert(N->getValueType(0).isVector() && "Wrong BUILD_VECTOR return type!"); 764 assert(N->getNumOperands() == N->getValueType(0).getVectorNumElements() && 765 "Wrong number of BUILD_VECTOR operands!"); 766 // FIXME: Change vector_shuffle to a variadic node with mask elements being 767 // operands of the node. Currently the mask is a BUILD_VECTOR passed as an 768 // operand, and it is not always possible to legalize it. Turning off the 769 // following checks at least makes it possible to legalize most of the time. 770// MVT EltVT = N->getValueType(0).getVectorElementType(); 771// for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ++I) 772// assert(I->getSDValue().getValueType() == EltVT && 773// "Wrong BUILD_VECTOR operand type!"); 774 break; 775 } 776 } 777} 778 779/// getMVTAlignment - Compute the default alignment value for the 780/// given type. 781/// 782unsigned SelectionDAG::getMVTAlignment(MVT VT) const { 783 const Type *Ty = VT == MVT::iPTR ? 784 PointerType::get(Type::Int8Ty, 0) : 785 VT.getTypeForMVT(); 786 787 return TLI.getTargetData()->getABITypeAlignment(Ty); 788} 789 790SelectionDAG::SelectionDAG(TargetLowering &tli, FunctionLoweringInfo &fli) 791 : TLI(tli), FLI(fli), 792 EntryNode(ISD::EntryToken, getVTList(MVT::Other)), 793 Root(getEntryNode()) { 794 AllNodes.push_back(&EntryNode); 795} 796 797void SelectionDAG::init(MachineFunction &mf, MachineModuleInfo *mmi) { 798 MF = &mf; 799 MMI = mmi; 800} 801 802SelectionDAG::~SelectionDAG() { 803 allnodes_clear(); 804} 805 806void SelectionDAG::allnodes_clear() { 807 assert(&*AllNodes.begin() == &EntryNode); 808 AllNodes.remove(AllNodes.begin()); 809 while (!AllNodes.empty()) { 810 SDNode *N = AllNodes.remove(AllNodes.begin()); 811 N->SetNextInBucket(0); 812 813 if (N->OperandsNeedDelete) { 814 delete [] N->OperandList; 815 N->OperandList = 0; 816 } 817 818 NodeAllocator.Deallocate(N); 819 } 820} 821 822void SelectionDAG::clear() { 823 allnodes_clear(); 824 OperandAllocator.Reset(); 825 CSEMap.clear(); 826 827 ExtendedValueTypeNodes.clear(); 828 ExternalSymbols.clear(); 829 TargetExternalSymbols.clear(); 830 std::fill(CondCodeNodes.begin(), CondCodeNodes.end(), 831 static_cast<CondCodeSDNode*>(0)); 832 std::fill(ValueTypeNodes.begin(), ValueTypeNodes.end(), 833 static_cast<SDNode*>(0)); 834 835 EntryNode.Uses = 0; 836 AllNodes.push_back(&EntryNode); 837 Root = getEntryNode(); 838} 839 840SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, MVT VT) { 841 if (Op.getValueType() == VT) return Op; 842 APInt Imm = APInt::getLowBitsSet(Op.getValueSizeInBits(), 843 VT.getSizeInBits()); 844 return getNode(ISD::AND, Op.getValueType(), Op, 845 getConstant(Imm, Op.getValueType())); 846} 847 848SDValue SelectionDAG::getConstant(uint64_t Val, MVT VT, bool isT) { 849 MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 850 return getConstant(APInt(EltVT.getSizeInBits(), Val), VT, isT); 851} 852 853SDValue SelectionDAG::getConstant(const APInt &Val, MVT VT, bool isT) { 854 return getConstant(*ConstantInt::get(Val), VT, isT); 855} 856 857SDValue SelectionDAG::getConstant(const ConstantInt &Val, MVT VT, bool isT) { 858 assert(VT.isInteger() && "Cannot create FP integer constant!"); 859 860 MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 861 assert(Val.getBitWidth() == EltVT.getSizeInBits() && 862 "APInt size does not match type size!"); 863 864 unsigned Opc = isT ? ISD::TargetConstant : ISD::Constant; 865 FoldingSetNodeID ID; 866 AddNodeIDNode(ID, Opc, getVTList(EltVT), 0, 0); 867 ID.AddPointer(&Val); 868 void *IP = 0; 869 SDNode *N = NULL; 870 if ((N = CSEMap.FindNodeOrInsertPos(ID, IP))) 871 if (!VT.isVector()) 872 return SDValue(N, 0); 873 if (!N) { 874 N = NodeAllocator.Allocate<ConstantSDNode>(); 875 new (N) ConstantSDNode(isT, &Val, EltVT); 876 CSEMap.InsertNode(N, IP); 877 AllNodes.push_back(N); 878 } 879 880 SDValue Result(N, 0); 881 if (VT.isVector()) { 882 SmallVector<SDValue, 8> Ops; 883 Ops.assign(VT.getVectorNumElements(), Result); 884 Result = getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 885 } 886 return Result; 887} 888 889SDValue SelectionDAG::getIntPtrConstant(uint64_t Val, bool isTarget) { 890 return getConstant(Val, TLI.getPointerTy(), isTarget); 891} 892 893 894SDValue SelectionDAG::getConstantFP(const APFloat& V, MVT VT, bool isTarget) { 895 return getConstantFP(*ConstantFP::get(V), VT, isTarget); 896} 897 898SDValue SelectionDAG::getConstantFP(const ConstantFP& V, MVT VT, bool isTarget){ 899 assert(VT.isFloatingPoint() && "Cannot create integer FP constant!"); 900 901 MVT EltVT = 902 VT.isVector() ? VT.getVectorElementType() : VT; 903 904 // Do the map lookup using the actual bit pattern for the floating point 905 // value, so that we don't have problems with 0.0 comparing equal to -0.0, and 906 // we don't have issues with SNANs. 907 unsigned Opc = isTarget ? ISD::TargetConstantFP : ISD::ConstantFP; 908 FoldingSetNodeID ID; 909 AddNodeIDNode(ID, Opc, getVTList(EltVT), 0, 0); 910 ID.AddPointer(&V); 911 void *IP = 0; 912 SDNode *N = NULL; 913 if ((N = CSEMap.FindNodeOrInsertPos(ID, IP))) 914 if (!VT.isVector()) 915 return SDValue(N, 0); 916 if (!N) { 917 N = NodeAllocator.Allocate<ConstantFPSDNode>(); 918 new (N) ConstantFPSDNode(isTarget, &V, EltVT); 919 CSEMap.InsertNode(N, IP); 920 AllNodes.push_back(N); 921 } 922 923 SDValue Result(N, 0); 924 if (VT.isVector()) { 925 SmallVector<SDValue, 8> Ops; 926 Ops.assign(VT.getVectorNumElements(), Result); 927 Result = getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 928 } 929 return Result; 930} 931 932SDValue SelectionDAG::getConstantFP(double Val, MVT VT, bool isTarget) { 933 MVT EltVT = 934 VT.isVector() ? VT.getVectorElementType() : VT; 935 if (EltVT==MVT::f32) 936 return getConstantFP(APFloat((float)Val), VT, isTarget); 937 else 938 return getConstantFP(APFloat(Val), VT, isTarget); 939} 940 941SDValue SelectionDAG::getGlobalAddress(const GlobalValue *GV, 942 MVT VT, int64_t Offset, 943 bool isTargetGA) { 944 unsigned Opc; 945 946 // Truncate (with sign-extension) the offset value to the pointer size. 947 unsigned BitWidth = TLI.getPointerTy().getSizeInBits(); 948 if (BitWidth < 64) 949 Offset = (Offset << (64 - BitWidth) >> (64 - BitWidth)); 950 951 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV); 952 if (!GVar) { 953 // If GV is an alias then use the aliasee for determining thread-localness. 954 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) 955 GVar = dyn_cast_or_null<GlobalVariable>(GA->resolveAliasedGlobal(false)); 956 } 957 958 if (GVar && GVar->isThreadLocal()) 959 Opc = isTargetGA ? ISD::TargetGlobalTLSAddress : ISD::GlobalTLSAddress; 960 else 961 Opc = isTargetGA ? ISD::TargetGlobalAddress : ISD::GlobalAddress; 962 963 FoldingSetNodeID ID; 964 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 965 ID.AddPointer(GV); 966 ID.AddInteger(Offset); 967 void *IP = 0; 968 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 969 return SDValue(E, 0); 970 SDNode *N = NodeAllocator.Allocate<GlobalAddressSDNode>(); 971 new (N) GlobalAddressSDNode(isTargetGA, GV, VT, Offset); 972 CSEMap.InsertNode(N, IP); 973 AllNodes.push_back(N); 974 return SDValue(N, 0); 975} 976 977SDValue SelectionDAG::getFrameIndex(int FI, MVT VT, bool isTarget) { 978 unsigned Opc = isTarget ? ISD::TargetFrameIndex : ISD::FrameIndex; 979 FoldingSetNodeID ID; 980 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 981 ID.AddInteger(FI); 982 void *IP = 0; 983 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 984 return SDValue(E, 0); 985 SDNode *N = NodeAllocator.Allocate<FrameIndexSDNode>(); 986 new (N) FrameIndexSDNode(FI, VT, isTarget); 987 CSEMap.InsertNode(N, IP); 988 AllNodes.push_back(N); 989 return SDValue(N, 0); 990} 991 992SDValue SelectionDAG::getJumpTable(int JTI, MVT VT, bool isTarget){ 993 unsigned Opc = isTarget ? ISD::TargetJumpTable : ISD::JumpTable; 994 FoldingSetNodeID ID; 995 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 996 ID.AddInteger(JTI); 997 void *IP = 0; 998 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 999 return SDValue(E, 0); 1000 SDNode *N = NodeAllocator.Allocate<JumpTableSDNode>(); 1001 new (N) JumpTableSDNode(JTI, VT, isTarget); 1002 CSEMap.InsertNode(N, IP); 1003 AllNodes.push_back(N); 1004 return SDValue(N, 0); 1005} 1006 1007SDValue SelectionDAG::getConstantPool(Constant *C, MVT VT, 1008 unsigned Alignment, int Offset, 1009 bool isTarget) { 1010 if (Alignment == 0) 1011 Alignment = 1012 TLI.getTargetData()->getPreferredTypeAlignmentShift(C->getType()); 1013 unsigned Opc = isTarget ? ISD::TargetConstantPool : ISD::ConstantPool; 1014 FoldingSetNodeID ID; 1015 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 1016 ID.AddInteger(Alignment); 1017 ID.AddInteger(Offset); 1018 ID.AddPointer(C); 1019 void *IP = 0; 1020 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1021 return SDValue(E, 0); 1022 SDNode *N = NodeAllocator.Allocate<ConstantPoolSDNode>(); 1023 new (N) ConstantPoolSDNode(isTarget, C, VT, Offset, Alignment); 1024 CSEMap.InsertNode(N, IP); 1025 AllNodes.push_back(N); 1026 return SDValue(N, 0); 1027} 1028 1029 1030SDValue SelectionDAG::getConstantPool(MachineConstantPoolValue *C, MVT VT, 1031 unsigned Alignment, int Offset, 1032 bool isTarget) { 1033 if (Alignment == 0) 1034 Alignment = 1035 TLI.getTargetData()->getPreferredTypeAlignmentShift(C->getType()); 1036 unsigned Opc = isTarget ? ISD::TargetConstantPool : ISD::ConstantPool; 1037 FoldingSetNodeID ID; 1038 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 1039 ID.AddInteger(Alignment); 1040 ID.AddInteger(Offset); 1041 C->AddSelectionDAGCSEId(ID); 1042 void *IP = 0; 1043 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1044 return SDValue(E, 0); 1045 SDNode *N = NodeAllocator.Allocate<ConstantPoolSDNode>(); 1046 new (N) ConstantPoolSDNode(isTarget, C, VT, Offset, Alignment); 1047 CSEMap.InsertNode(N, IP); 1048 AllNodes.push_back(N); 1049 return SDValue(N, 0); 1050} 1051 1052 1053SDValue SelectionDAG::getBasicBlock(MachineBasicBlock *MBB) { 1054 FoldingSetNodeID ID; 1055 AddNodeIDNode(ID, ISD::BasicBlock, getVTList(MVT::Other), 0, 0); 1056 ID.AddPointer(MBB); 1057 void *IP = 0; 1058 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1059 return SDValue(E, 0); 1060 SDNode *N = NodeAllocator.Allocate<BasicBlockSDNode>(); 1061 new (N) BasicBlockSDNode(MBB); 1062 CSEMap.InsertNode(N, IP); 1063 AllNodes.push_back(N); 1064 return SDValue(N, 0); 1065} 1066 1067SDValue SelectionDAG::getArgFlags(ISD::ArgFlagsTy Flags) { 1068 FoldingSetNodeID ID; 1069 AddNodeIDNode(ID, ISD::ARG_FLAGS, getVTList(MVT::Other), 0, 0); 1070 ID.AddInteger(Flags.getRawBits()); 1071 void *IP = 0; 1072 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1073 return SDValue(E, 0); 1074 SDNode *N = NodeAllocator.Allocate<ARG_FLAGSSDNode>(); 1075 new (N) ARG_FLAGSSDNode(Flags); 1076 CSEMap.InsertNode(N, IP); 1077 AllNodes.push_back(N); 1078 return SDValue(N, 0); 1079} 1080 1081SDValue SelectionDAG::getValueType(MVT VT) { 1082 if (VT.isSimple() && (unsigned)VT.getSimpleVT() >= ValueTypeNodes.size()) 1083 ValueTypeNodes.resize(VT.getSimpleVT()+1); 1084 1085 SDNode *&N = VT.isExtended() ? 1086 ExtendedValueTypeNodes[VT] : ValueTypeNodes[VT.getSimpleVT()]; 1087 1088 if (N) return SDValue(N, 0); 1089 N = NodeAllocator.Allocate<VTSDNode>(); 1090 new (N) VTSDNode(VT); 1091 AllNodes.push_back(N); 1092 return SDValue(N, 0); 1093} 1094 1095SDValue SelectionDAG::getExternalSymbol(const char *Sym, MVT VT) { 1096 SDNode *&N = ExternalSymbols[Sym]; 1097 if (N) return SDValue(N, 0); 1098 N = NodeAllocator.Allocate<ExternalSymbolSDNode>(); 1099 new (N) ExternalSymbolSDNode(false, Sym, VT); 1100 AllNodes.push_back(N); 1101 return SDValue(N, 0); 1102} 1103 1104SDValue SelectionDAG::getTargetExternalSymbol(const char *Sym, MVT VT) { 1105 SDNode *&N = TargetExternalSymbols[Sym]; 1106 if (N) return SDValue(N, 0); 1107 N = NodeAllocator.Allocate<ExternalSymbolSDNode>(); 1108 new (N) ExternalSymbolSDNode(true, Sym, VT); 1109 AllNodes.push_back(N); 1110 return SDValue(N, 0); 1111} 1112 1113SDValue SelectionDAG::getCondCode(ISD::CondCode Cond) { 1114 if ((unsigned)Cond >= CondCodeNodes.size()) 1115 CondCodeNodes.resize(Cond+1); 1116 1117 if (CondCodeNodes[Cond] == 0) { 1118 CondCodeSDNode *N = NodeAllocator.Allocate<CondCodeSDNode>(); 1119 new (N) CondCodeSDNode(Cond); 1120 CondCodeNodes[Cond] = N; 1121 AllNodes.push_back(N); 1122 } 1123 return SDValue(CondCodeNodes[Cond], 0); 1124} 1125 1126SDValue SelectionDAG::getRegister(unsigned RegNo, MVT VT) { 1127 FoldingSetNodeID ID; 1128 AddNodeIDNode(ID, ISD::Register, getVTList(VT), 0, 0); 1129 ID.AddInteger(RegNo); 1130 void *IP = 0; 1131 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1132 return SDValue(E, 0); 1133 SDNode *N = NodeAllocator.Allocate<RegisterSDNode>(); 1134 new (N) RegisterSDNode(RegNo, VT); 1135 CSEMap.InsertNode(N, IP); 1136 AllNodes.push_back(N); 1137 return SDValue(N, 0); 1138} 1139 1140SDValue SelectionDAG::getDbgStopPoint(SDValue Root, 1141 unsigned Line, unsigned Col, 1142 const CompileUnitDesc *CU) { 1143 SDNode *N = NodeAllocator.Allocate<DbgStopPointSDNode>(); 1144 new (N) DbgStopPointSDNode(Root, Line, Col, CU); 1145 AllNodes.push_back(N); 1146 return SDValue(N, 0); 1147} 1148 1149SDValue SelectionDAG::getLabel(unsigned Opcode, 1150 SDValue Root, 1151 unsigned LabelID) { 1152 FoldingSetNodeID ID; 1153 SDValue Ops[] = { Root }; 1154 AddNodeIDNode(ID, Opcode, getVTList(MVT::Other), &Ops[0], 1); 1155 ID.AddInteger(LabelID); 1156 void *IP = 0; 1157 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1158 return SDValue(E, 0); 1159 SDNode *N = NodeAllocator.Allocate<LabelSDNode>(); 1160 new (N) LabelSDNode(Opcode, Root, LabelID); 1161 CSEMap.InsertNode(N, IP); 1162 AllNodes.push_back(N); 1163 return SDValue(N, 0); 1164} 1165 1166SDValue SelectionDAG::getSrcValue(const Value *V) { 1167 assert((!V || isa<PointerType>(V->getType())) && 1168 "SrcValue is not a pointer?"); 1169 1170 FoldingSetNodeID ID; 1171 AddNodeIDNode(ID, ISD::SRCVALUE, getVTList(MVT::Other), 0, 0); 1172 ID.AddPointer(V); 1173 1174 void *IP = 0; 1175 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1176 return SDValue(E, 0); 1177 1178 SDNode *N = NodeAllocator.Allocate<SrcValueSDNode>(); 1179 new (N) SrcValueSDNode(V); 1180 CSEMap.InsertNode(N, IP); 1181 AllNodes.push_back(N); 1182 return SDValue(N, 0); 1183} 1184 1185SDValue SelectionDAG::getMemOperand(const MachineMemOperand &MO) { 1186 const Value *v = MO.getValue(); 1187 assert((!v || isa<PointerType>(v->getType())) && 1188 "SrcValue is not a pointer?"); 1189 1190 FoldingSetNodeID ID; 1191 AddNodeIDNode(ID, ISD::MEMOPERAND, getVTList(MVT::Other), 0, 0); 1192 MO.Profile(ID); 1193 1194 void *IP = 0; 1195 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1196 return SDValue(E, 0); 1197 1198 SDNode *N = NodeAllocator.Allocate<MemOperandSDNode>(); 1199 new (N) MemOperandSDNode(MO); 1200 CSEMap.InsertNode(N, IP); 1201 AllNodes.push_back(N); 1202 return SDValue(N, 0); 1203} 1204 1205/// CreateStackTemporary - Create a stack temporary, suitable for holding the 1206/// specified value type. 1207SDValue SelectionDAG::CreateStackTemporary(MVT VT, unsigned minAlign) { 1208 MachineFrameInfo *FrameInfo = getMachineFunction().getFrameInfo(); 1209 unsigned ByteSize = VT.getSizeInBits()/8; 1210 const Type *Ty = VT.getTypeForMVT(); 1211 unsigned StackAlign = 1212 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), minAlign); 1213 1214 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, StackAlign); 1215 return getFrameIndex(FrameIdx, TLI.getPointerTy()); 1216} 1217 1218SDValue SelectionDAG::FoldSetCC(MVT VT, SDValue N1, 1219 SDValue N2, ISD::CondCode Cond) { 1220 // These setcc operations always fold. 1221 switch (Cond) { 1222 default: break; 1223 case ISD::SETFALSE: 1224 case ISD::SETFALSE2: return getConstant(0, VT); 1225 case ISD::SETTRUE: 1226 case ISD::SETTRUE2: return getConstant(1, VT); 1227 1228 case ISD::SETOEQ: 1229 case ISD::SETOGT: 1230 case ISD::SETOGE: 1231 case ISD::SETOLT: 1232 case ISD::SETOLE: 1233 case ISD::SETONE: 1234 case ISD::SETO: 1235 case ISD::SETUO: 1236 case ISD::SETUEQ: 1237 case ISD::SETUNE: 1238 assert(!N1.getValueType().isInteger() && "Illegal setcc for integer!"); 1239 break; 1240 } 1241 1242 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode())) { 1243 const APInt &C2 = N2C->getAPIntValue(); 1244 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) { 1245 const APInt &C1 = N1C->getAPIntValue(); 1246 1247 switch (Cond) { 1248 default: assert(0 && "Unknown integer setcc!"); 1249 case ISD::SETEQ: return getConstant(C1 == C2, VT); 1250 case ISD::SETNE: return getConstant(C1 != C2, VT); 1251 case ISD::SETULT: return getConstant(C1.ult(C2), VT); 1252 case ISD::SETUGT: return getConstant(C1.ugt(C2), VT); 1253 case ISD::SETULE: return getConstant(C1.ule(C2), VT); 1254 case ISD::SETUGE: return getConstant(C1.uge(C2), VT); 1255 case ISD::SETLT: return getConstant(C1.slt(C2), VT); 1256 case ISD::SETGT: return getConstant(C1.sgt(C2), VT); 1257 case ISD::SETLE: return getConstant(C1.sle(C2), VT); 1258 case ISD::SETGE: return getConstant(C1.sge(C2), VT); 1259 } 1260 } 1261 } 1262 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.getNode())) { 1263 if (ConstantFPSDNode *N2C = dyn_cast<ConstantFPSDNode>(N2.getNode())) { 1264 // No compile time operations on this type yet. 1265 if (N1C->getValueType(0) == MVT::ppcf128) 1266 return SDValue(); 1267 1268 APFloat::cmpResult R = N1C->getValueAPF().compare(N2C->getValueAPF()); 1269 switch (Cond) { 1270 default: break; 1271 case ISD::SETEQ: if (R==APFloat::cmpUnordered) 1272 return getNode(ISD::UNDEF, VT); 1273 // fall through 1274 case ISD::SETOEQ: return getConstant(R==APFloat::cmpEqual, VT); 1275 case ISD::SETNE: if (R==APFloat::cmpUnordered) 1276 return getNode(ISD::UNDEF, VT); 1277 // fall through 1278 case ISD::SETONE: return getConstant(R==APFloat::cmpGreaterThan || 1279 R==APFloat::cmpLessThan, VT); 1280 case ISD::SETLT: if (R==APFloat::cmpUnordered) 1281 return getNode(ISD::UNDEF, VT); 1282 // fall through 1283 case ISD::SETOLT: return getConstant(R==APFloat::cmpLessThan, VT); 1284 case ISD::SETGT: if (R==APFloat::cmpUnordered) 1285 return getNode(ISD::UNDEF, VT); 1286 // fall through 1287 case ISD::SETOGT: return getConstant(R==APFloat::cmpGreaterThan, VT); 1288 case ISD::SETLE: if (R==APFloat::cmpUnordered) 1289 return getNode(ISD::UNDEF, VT); 1290 // fall through 1291 case ISD::SETOLE: return getConstant(R==APFloat::cmpLessThan || 1292 R==APFloat::cmpEqual, VT); 1293 case ISD::SETGE: if (R==APFloat::cmpUnordered) 1294 return getNode(ISD::UNDEF, VT); 1295 // fall through 1296 case ISD::SETOGE: return getConstant(R==APFloat::cmpGreaterThan || 1297 R==APFloat::cmpEqual, VT); 1298 case ISD::SETO: return getConstant(R!=APFloat::cmpUnordered, VT); 1299 case ISD::SETUO: return getConstant(R==APFloat::cmpUnordered, VT); 1300 case ISD::SETUEQ: return getConstant(R==APFloat::cmpUnordered || 1301 R==APFloat::cmpEqual, VT); 1302 case ISD::SETUNE: return getConstant(R!=APFloat::cmpEqual, VT); 1303 case ISD::SETULT: return getConstant(R==APFloat::cmpUnordered || 1304 R==APFloat::cmpLessThan, VT); 1305 case ISD::SETUGT: return getConstant(R==APFloat::cmpGreaterThan || 1306 R==APFloat::cmpUnordered, VT); 1307 case ISD::SETULE: return getConstant(R!=APFloat::cmpGreaterThan, VT); 1308 case ISD::SETUGE: return getConstant(R!=APFloat::cmpLessThan, VT); 1309 } 1310 } else { 1311 // Ensure that the constant occurs on the RHS. 1312 return getSetCC(VT, N2, N1, ISD::getSetCCSwappedOperands(Cond)); 1313 } 1314 } 1315 1316 // Could not fold it. 1317 return SDValue(); 1318} 1319 1320/// SignBitIsZero - Return true if the sign bit of Op is known to be zero. We 1321/// use this predicate to simplify operations downstream. 1322bool SelectionDAG::SignBitIsZero(SDValue Op, unsigned Depth) const { 1323 unsigned BitWidth = Op.getValueSizeInBits(); 1324 return MaskedValueIsZero(Op, APInt::getSignBit(BitWidth), Depth); 1325} 1326 1327/// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero. We use 1328/// this predicate to simplify operations downstream. Mask is known to be zero 1329/// for bits that V cannot have. 1330bool SelectionDAG::MaskedValueIsZero(SDValue Op, const APInt &Mask, 1331 unsigned Depth) const { 1332 APInt KnownZero, KnownOne; 1333 ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth); 1334 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1335 return (KnownZero & Mask) == Mask; 1336} 1337 1338/// ComputeMaskedBits - Determine which of the bits specified in Mask are 1339/// known to be either zero or one and return them in the KnownZero/KnownOne 1340/// bitsets. This code only analyzes bits in Mask, in order to short-circuit 1341/// processing. 1342void SelectionDAG::ComputeMaskedBits(SDValue Op, const APInt &Mask, 1343 APInt &KnownZero, APInt &KnownOne, 1344 unsigned Depth) const { 1345 unsigned BitWidth = Mask.getBitWidth(); 1346 assert(BitWidth == Op.getValueType().getSizeInBits() && 1347 "Mask size mismatches value type size!"); 1348 1349 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything. 1350 if (Depth == 6 || Mask == 0) 1351 return; // Limit search depth. 1352 1353 APInt KnownZero2, KnownOne2; 1354 1355 switch (Op.getOpcode()) { 1356 case ISD::Constant: 1357 // We know all of the bits for a constant! 1358 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & Mask; 1359 KnownZero = ~KnownOne & Mask; 1360 return; 1361 case ISD::AND: 1362 // If either the LHS or the RHS are Zero, the result is zero. 1363 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1364 ComputeMaskedBits(Op.getOperand(0), Mask & ~KnownZero, 1365 KnownZero2, KnownOne2, Depth+1); 1366 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1367 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1368 1369 // Output known-1 bits are only known if set in both the LHS & RHS. 1370 KnownOne &= KnownOne2; 1371 // Output known-0 are known to be clear if zero in either the LHS | RHS. 1372 KnownZero |= KnownZero2; 1373 return; 1374 case ISD::OR: 1375 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1376 ComputeMaskedBits(Op.getOperand(0), Mask & ~KnownOne, 1377 KnownZero2, KnownOne2, Depth+1); 1378 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1379 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1380 1381 // Output known-0 bits are only known if clear in both the LHS & RHS. 1382 KnownZero &= KnownZero2; 1383 // Output known-1 are known to be set if set in either the LHS | RHS. 1384 KnownOne |= KnownOne2; 1385 return; 1386 case ISD::XOR: { 1387 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1388 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1); 1389 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1390 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1391 1392 // Output known-0 bits are known if clear or set in both the LHS & RHS. 1393 APInt KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 1394 // Output known-1 are known to be set if set in only one of the LHS, RHS. 1395 KnownOne = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 1396 KnownZero = KnownZeroOut; 1397 return; 1398 } 1399 case ISD::MUL: { 1400 APInt Mask2 = APInt::getAllOnesValue(BitWidth); 1401 ComputeMaskedBits(Op.getOperand(1), Mask2, KnownZero, KnownOne, Depth+1); 1402 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero2, KnownOne2, Depth+1); 1403 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1404 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1405 1406 // If low bits are zero in either operand, output low known-0 bits. 1407 // Also compute a conserative estimate for high known-0 bits. 1408 // More trickiness is possible, but this is sufficient for the 1409 // interesting case of alignment computation. 1410 KnownOne.clear(); 1411 unsigned TrailZ = KnownZero.countTrailingOnes() + 1412 KnownZero2.countTrailingOnes(); 1413 unsigned LeadZ = std::max(KnownZero.countLeadingOnes() + 1414 KnownZero2.countLeadingOnes(), 1415 BitWidth) - BitWidth; 1416 1417 TrailZ = std::min(TrailZ, BitWidth); 1418 LeadZ = std::min(LeadZ, BitWidth); 1419 KnownZero = APInt::getLowBitsSet(BitWidth, TrailZ) | 1420 APInt::getHighBitsSet(BitWidth, LeadZ); 1421 KnownZero &= Mask; 1422 return; 1423 } 1424 case ISD::UDIV: { 1425 // For the purposes of computing leading zeros we can conservatively 1426 // treat a udiv as a logical right shift by the power of 2 known to 1427 // be less than the denominator. 1428 APInt AllOnes = APInt::getAllOnesValue(BitWidth); 1429 ComputeMaskedBits(Op.getOperand(0), 1430 AllOnes, KnownZero2, KnownOne2, Depth+1); 1431 unsigned LeadZ = KnownZero2.countLeadingOnes(); 1432 1433 KnownOne2.clear(); 1434 KnownZero2.clear(); 1435 ComputeMaskedBits(Op.getOperand(1), 1436 AllOnes, KnownZero2, KnownOne2, Depth+1); 1437 unsigned RHSUnknownLeadingOnes = KnownOne2.countLeadingZeros(); 1438 if (RHSUnknownLeadingOnes != BitWidth) 1439 LeadZ = std::min(BitWidth, 1440 LeadZ + BitWidth - RHSUnknownLeadingOnes - 1); 1441 1442 KnownZero = APInt::getHighBitsSet(BitWidth, LeadZ) & Mask; 1443 return; 1444 } 1445 case ISD::SELECT: 1446 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero, KnownOne, Depth+1); 1447 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero2, KnownOne2, Depth+1); 1448 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1449 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1450 1451 // Only known if known in both the LHS and RHS. 1452 KnownOne &= KnownOne2; 1453 KnownZero &= KnownZero2; 1454 return; 1455 case ISD::SELECT_CC: 1456 ComputeMaskedBits(Op.getOperand(3), Mask, KnownZero, KnownOne, Depth+1); 1457 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero2, KnownOne2, Depth+1); 1458 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1459 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1460 1461 // Only known if known in both the LHS and RHS. 1462 KnownOne &= KnownOne2; 1463 KnownZero &= KnownZero2; 1464 return; 1465 case ISD::SETCC: 1466 // If we know the result of a setcc has the top bits zero, use this info. 1467 if (TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult && 1468 BitWidth > 1) 1469 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1); 1470 return; 1471 case ISD::SHL: 1472 // (shl X, C1) & C2 == 0 iff (X & C2 >>u C1) == 0 1473 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1474 unsigned ShAmt = SA->getZExtValue(); 1475 1476 // If the shift count is an invalid immediate, don't do anything. 1477 if (ShAmt >= BitWidth) 1478 return; 1479 1480 ComputeMaskedBits(Op.getOperand(0), Mask.lshr(ShAmt), 1481 KnownZero, KnownOne, Depth+1); 1482 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1483 KnownZero <<= ShAmt; 1484 KnownOne <<= ShAmt; 1485 // low bits known zero. 1486 KnownZero |= APInt::getLowBitsSet(BitWidth, ShAmt); 1487 } 1488 return; 1489 case ISD::SRL: 1490 // (ushr X, C1) & C2 == 0 iff (-1 >> C1) & C2 == 0 1491 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1492 unsigned ShAmt = SA->getZExtValue(); 1493 1494 // If the shift count is an invalid immediate, don't do anything. 1495 if (ShAmt >= BitWidth) 1496 return; 1497 1498 ComputeMaskedBits(Op.getOperand(0), (Mask << ShAmt), 1499 KnownZero, KnownOne, Depth+1); 1500 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1501 KnownZero = KnownZero.lshr(ShAmt); 1502 KnownOne = KnownOne.lshr(ShAmt); 1503 1504 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt) & Mask; 1505 KnownZero |= HighBits; // High bits known zero. 1506 } 1507 return; 1508 case ISD::SRA: 1509 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1510 unsigned ShAmt = SA->getZExtValue(); 1511 1512 // If the shift count is an invalid immediate, don't do anything. 1513 if (ShAmt >= BitWidth) 1514 return; 1515 1516 APInt InDemandedMask = (Mask << ShAmt); 1517 // If any of the demanded bits are produced by the sign extension, we also 1518 // demand the input sign bit. 1519 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt) & Mask; 1520 if (HighBits.getBoolValue()) 1521 InDemandedMask |= APInt::getSignBit(BitWidth); 1522 1523 ComputeMaskedBits(Op.getOperand(0), InDemandedMask, KnownZero, KnownOne, 1524 Depth+1); 1525 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1526 KnownZero = KnownZero.lshr(ShAmt); 1527 KnownOne = KnownOne.lshr(ShAmt); 1528 1529 // Handle the sign bits. 1530 APInt SignBit = APInt::getSignBit(BitWidth); 1531 SignBit = SignBit.lshr(ShAmt); // Adjust to where it is now in the mask. 1532 1533 if (KnownZero.intersects(SignBit)) { 1534 KnownZero |= HighBits; // New bits are known zero. 1535 } else if (KnownOne.intersects(SignBit)) { 1536 KnownOne |= HighBits; // New bits are known one. 1537 } 1538 } 1539 return; 1540 case ISD::SIGN_EXTEND_INREG: { 1541 MVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1542 unsigned EBits = EVT.getSizeInBits(); 1543 1544 // Sign extension. Compute the demanded bits in the result that are not 1545 // present in the input. 1546 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - EBits) & Mask; 1547 1548 APInt InSignBit = APInt::getSignBit(EBits); 1549 APInt InputDemandedBits = Mask & APInt::getLowBitsSet(BitWidth, EBits); 1550 1551 // If the sign extended bits are demanded, we know that the sign 1552 // bit is demanded. 1553 InSignBit.zext(BitWidth); 1554 if (NewBits.getBoolValue()) 1555 InputDemandedBits |= InSignBit; 1556 1557 ComputeMaskedBits(Op.getOperand(0), InputDemandedBits, 1558 KnownZero, KnownOne, Depth+1); 1559 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1560 1561 // If the sign bit of the input is known set or clear, then we know the 1562 // top bits of the result. 1563 if (KnownZero.intersects(InSignBit)) { // Input sign bit known clear 1564 KnownZero |= NewBits; 1565 KnownOne &= ~NewBits; 1566 } else if (KnownOne.intersects(InSignBit)) { // Input sign bit known set 1567 KnownOne |= NewBits; 1568 KnownZero &= ~NewBits; 1569 } else { // Input sign bit unknown 1570 KnownZero &= ~NewBits; 1571 KnownOne &= ~NewBits; 1572 } 1573 return; 1574 } 1575 case ISD::CTTZ: 1576 case ISD::CTLZ: 1577 case ISD::CTPOP: { 1578 unsigned LowBits = Log2_32(BitWidth)+1; 1579 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - LowBits); 1580 KnownOne.clear(); 1581 return; 1582 } 1583 case ISD::LOAD: { 1584 if (ISD::isZEXTLoad(Op.getNode())) { 1585 LoadSDNode *LD = cast<LoadSDNode>(Op); 1586 MVT VT = LD->getMemoryVT(); 1587 unsigned MemBits = VT.getSizeInBits(); 1588 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits) & Mask; 1589 } 1590 return; 1591 } 1592 case ISD::ZERO_EXTEND: { 1593 MVT InVT = Op.getOperand(0).getValueType(); 1594 unsigned InBits = InVT.getSizeInBits(); 1595 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - InBits) & Mask; 1596 APInt InMask = Mask; 1597 InMask.trunc(InBits); 1598 KnownZero.trunc(InBits); 1599 KnownOne.trunc(InBits); 1600 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1601 KnownZero.zext(BitWidth); 1602 KnownOne.zext(BitWidth); 1603 KnownZero |= NewBits; 1604 return; 1605 } 1606 case ISD::SIGN_EXTEND: { 1607 MVT InVT = Op.getOperand(0).getValueType(); 1608 unsigned InBits = InVT.getSizeInBits(); 1609 APInt InSignBit = APInt::getSignBit(InBits); 1610 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - InBits) & Mask; 1611 APInt InMask = Mask; 1612 InMask.trunc(InBits); 1613 1614 // If any of the sign extended bits are demanded, we know that the sign 1615 // bit is demanded. Temporarily set this bit in the mask for our callee. 1616 if (NewBits.getBoolValue()) 1617 InMask |= InSignBit; 1618 1619 KnownZero.trunc(InBits); 1620 KnownOne.trunc(InBits); 1621 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1622 1623 // Note if the sign bit is known to be zero or one. 1624 bool SignBitKnownZero = KnownZero.isNegative(); 1625 bool SignBitKnownOne = KnownOne.isNegative(); 1626 assert(!(SignBitKnownZero && SignBitKnownOne) && 1627 "Sign bit can't be known to be both zero and one!"); 1628 1629 // If the sign bit wasn't actually demanded by our caller, we don't 1630 // want it set in the KnownZero and KnownOne result values. Reset the 1631 // mask and reapply it to the result values. 1632 InMask = Mask; 1633 InMask.trunc(InBits); 1634 KnownZero &= InMask; 1635 KnownOne &= InMask; 1636 1637 KnownZero.zext(BitWidth); 1638 KnownOne.zext(BitWidth); 1639 1640 // If the sign bit is known zero or one, the top bits match. 1641 if (SignBitKnownZero) 1642 KnownZero |= NewBits; 1643 else if (SignBitKnownOne) 1644 KnownOne |= NewBits; 1645 return; 1646 } 1647 case ISD::ANY_EXTEND: { 1648 MVT InVT = Op.getOperand(0).getValueType(); 1649 unsigned InBits = InVT.getSizeInBits(); 1650 APInt InMask = Mask; 1651 InMask.trunc(InBits); 1652 KnownZero.trunc(InBits); 1653 KnownOne.trunc(InBits); 1654 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1655 KnownZero.zext(BitWidth); 1656 KnownOne.zext(BitWidth); 1657 return; 1658 } 1659 case ISD::TRUNCATE: { 1660 MVT InVT = Op.getOperand(0).getValueType(); 1661 unsigned InBits = InVT.getSizeInBits(); 1662 APInt InMask = Mask; 1663 InMask.zext(InBits); 1664 KnownZero.zext(InBits); 1665 KnownOne.zext(InBits); 1666 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1667 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1668 KnownZero.trunc(BitWidth); 1669 KnownOne.trunc(BitWidth); 1670 break; 1671 } 1672 case ISD::AssertZext: { 1673 MVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1674 APInt InMask = APInt::getLowBitsSet(BitWidth, VT.getSizeInBits()); 1675 ComputeMaskedBits(Op.getOperand(0), Mask & InMask, KnownZero, 1676 KnownOne, Depth+1); 1677 KnownZero |= (~InMask) & Mask; 1678 return; 1679 } 1680 case ISD::FGETSIGN: 1681 // All bits are zero except the low bit. 1682 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - 1); 1683 return; 1684 1685 case ISD::SUB: { 1686 if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) { 1687 // We know that the top bits of C-X are clear if X contains less bits 1688 // than C (i.e. no wrap-around can happen). For example, 20-X is 1689 // positive if we can prove that X is >= 0 and < 16. 1690 if (CLHS->getAPIntValue().isNonNegative()) { 1691 unsigned NLZ = (CLHS->getAPIntValue()+1).countLeadingZeros(); 1692 // NLZ can't be BitWidth with no sign bit 1693 APInt MaskV = APInt::getHighBitsSet(BitWidth, NLZ+1); 1694 ComputeMaskedBits(Op.getOperand(1), MaskV, KnownZero2, KnownOne2, 1695 Depth+1); 1696 1697 // If all of the MaskV bits are known to be zero, then we know the 1698 // output top bits are zero, because we now know that the output is 1699 // from [0-C]. 1700 if ((KnownZero2 & MaskV) == MaskV) { 1701 unsigned NLZ2 = CLHS->getAPIntValue().countLeadingZeros(); 1702 // Top bits known zero. 1703 KnownZero = APInt::getHighBitsSet(BitWidth, NLZ2) & Mask; 1704 } 1705 } 1706 } 1707 } 1708 // fall through 1709 case ISD::ADD: { 1710 // Output known-0 bits are known if clear or set in both the low clear bits 1711 // common to both LHS & RHS. For example, 8+(X<<3) is known to have the 1712 // low 3 bits clear. 1713 APInt Mask2 = APInt::getLowBitsSet(BitWidth, Mask.countTrailingOnes()); 1714 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero2, KnownOne2, Depth+1); 1715 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1716 unsigned KnownZeroOut = KnownZero2.countTrailingOnes(); 1717 1718 ComputeMaskedBits(Op.getOperand(1), Mask2, KnownZero2, KnownOne2, Depth+1); 1719 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1720 KnownZeroOut = std::min(KnownZeroOut, 1721 KnownZero2.countTrailingOnes()); 1722 1723 KnownZero |= APInt::getLowBitsSet(BitWidth, KnownZeroOut); 1724 return; 1725 } 1726 case ISD::SREM: 1727 if (ConstantSDNode *Rem = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1728 const APInt &RA = Rem->getAPIntValue(); 1729 if (RA.isPowerOf2() || (-RA).isPowerOf2()) { 1730 APInt LowBits = RA.isStrictlyPositive() ? (RA - 1) : ~RA; 1731 APInt Mask2 = LowBits | APInt::getSignBit(BitWidth); 1732 ComputeMaskedBits(Op.getOperand(0), Mask2,KnownZero2,KnownOne2,Depth+1); 1733 1734 // If the sign bit of the first operand is zero, the sign bit of 1735 // the result is zero. If the first operand has no one bits below 1736 // the second operand's single 1 bit, its sign will be zero. 1737 if (KnownZero2[BitWidth-1] || ((KnownZero2 & LowBits) == LowBits)) 1738 KnownZero2 |= ~LowBits; 1739 1740 KnownZero |= KnownZero2 & Mask; 1741 1742 assert((KnownZero & KnownOne) == 0&&"Bits known to be one AND zero?"); 1743 } 1744 } 1745 return; 1746 case ISD::UREM: { 1747 if (ConstantSDNode *Rem = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1748 const APInt &RA = Rem->getAPIntValue(); 1749 if (RA.isPowerOf2()) { 1750 APInt LowBits = (RA - 1); 1751 APInt Mask2 = LowBits & Mask; 1752 KnownZero |= ~LowBits & Mask; 1753 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero, KnownOne,Depth+1); 1754 assert((KnownZero & KnownOne) == 0&&"Bits known to be one AND zero?"); 1755 break; 1756 } 1757 } 1758 1759 // Since the result is less than or equal to either operand, any leading 1760 // zero bits in either operand must also exist in the result. 1761 APInt AllOnes = APInt::getAllOnesValue(BitWidth); 1762 ComputeMaskedBits(Op.getOperand(0), AllOnes, KnownZero, KnownOne, 1763 Depth+1); 1764 ComputeMaskedBits(Op.getOperand(1), AllOnes, KnownZero2, KnownOne2, 1765 Depth+1); 1766 1767 uint32_t Leaders = std::max(KnownZero.countLeadingOnes(), 1768 KnownZero2.countLeadingOnes()); 1769 KnownOne.clear(); 1770 KnownZero = APInt::getHighBitsSet(BitWidth, Leaders) & Mask; 1771 return; 1772 } 1773 default: 1774 // Allow the target to implement this method for its nodes. 1775 if (Op.getOpcode() >= ISD::BUILTIN_OP_END) { 1776 case ISD::INTRINSIC_WO_CHAIN: 1777 case ISD::INTRINSIC_W_CHAIN: 1778 case ISD::INTRINSIC_VOID: 1779 TLI.computeMaskedBitsForTargetNode(Op, Mask, KnownZero, KnownOne, *this); 1780 } 1781 return; 1782 } 1783} 1784 1785/// ComputeNumSignBits - Return the number of times the sign bit of the 1786/// register is replicated into the other bits. We know that at least 1 bit 1787/// is always equal to the sign bit (itself), but other cases can give us 1788/// information. For example, immediately after an "SRA X, 2", we know that 1789/// the top 3 bits are all equal to each other, so we return 3. 1790unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, unsigned Depth) const{ 1791 MVT VT = Op.getValueType(); 1792 assert(VT.isInteger() && "Invalid VT!"); 1793 unsigned VTBits = VT.getSizeInBits(); 1794 unsigned Tmp, Tmp2; 1795 unsigned FirstAnswer = 1; 1796 1797 if (Depth == 6) 1798 return 1; // Limit search depth. 1799 1800 switch (Op.getOpcode()) { 1801 default: break; 1802 case ISD::AssertSext: 1803 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); 1804 return VTBits-Tmp+1; 1805 case ISD::AssertZext: 1806 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); 1807 return VTBits-Tmp; 1808 1809 case ISD::Constant: { 1810 const APInt &Val = cast<ConstantSDNode>(Op)->getAPIntValue(); 1811 // If negative, return # leading ones. 1812 if (Val.isNegative()) 1813 return Val.countLeadingOnes(); 1814 1815 // Return # leading zeros. 1816 return Val.countLeadingZeros(); 1817 } 1818 1819 case ISD::SIGN_EXTEND: 1820 Tmp = VTBits-Op.getOperand(0).getValueType().getSizeInBits(); 1821 return ComputeNumSignBits(Op.getOperand(0), Depth+1) + Tmp; 1822 1823 case ISD::SIGN_EXTEND_INREG: 1824 // Max of the input and what this extends. 1825 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); 1826 Tmp = VTBits-Tmp+1; 1827 1828 Tmp2 = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1829 return std::max(Tmp, Tmp2); 1830 1831 case ISD::SRA: 1832 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1833 // SRA X, C -> adds C sign bits. 1834 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1835 Tmp += C->getZExtValue(); 1836 if (Tmp > VTBits) Tmp = VTBits; 1837 } 1838 return Tmp; 1839 case ISD::SHL: 1840 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1841 // shl destroys sign bits. 1842 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1843 if (C->getZExtValue() >= VTBits || // Bad shift. 1844 C->getZExtValue() >= Tmp) break; // Shifted all sign bits out. 1845 return Tmp - C->getZExtValue(); 1846 } 1847 break; 1848 case ISD::AND: 1849 case ISD::OR: 1850 case ISD::XOR: // NOT is handled here. 1851 // Logical binary ops preserve the number of sign bits at the worst. 1852 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1853 if (Tmp != 1) { 1854 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 1855 FirstAnswer = std::min(Tmp, Tmp2); 1856 // We computed what we know about the sign bits as our first 1857 // answer. Now proceed to the generic code that uses 1858 // ComputeMaskedBits, and pick whichever answer is better. 1859 } 1860 break; 1861 1862 case ISD::SELECT: 1863 Tmp = ComputeNumSignBits(Op.getOperand(1), Depth+1); 1864 if (Tmp == 1) return 1; // Early out. 1865 Tmp2 = ComputeNumSignBits(Op.getOperand(2), Depth+1); 1866 return std::min(Tmp, Tmp2); 1867 1868 case ISD::SETCC: 1869 // If setcc returns 0/-1, all bits are sign bits. 1870 if (TLI.getSetCCResultContents() == 1871 TargetLowering::ZeroOrNegativeOneSetCCResult) 1872 return VTBits; 1873 break; 1874 case ISD::ROTL: 1875 case ISD::ROTR: 1876 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1877 unsigned RotAmt = C->getZExtValue() & (VTBits-1); 1878 1879 // Handle rotate right by N like a rotate left by 32-N. 1880 if (Op.getOpcode() == ISD::ROTR) 1881 RotAmt = (VTBits-RotAmt) & (VTBits-1); 1882 1883 // If we aren't rotating out all of the known-in sign bits, return the 1884 // number that are left. This handles rotl(sext(x), 1) for example. 1885 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1886 if (Tmp > RotAmt+1) return Tmp-RotAmt; 1887 } 1888 break; 1889 case ISD::ADD: 1890 // Add can have at most one carry bit. Thus we know that the output 1891 // is, at worst, one more bit than the inputs. 1892 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1893 if (Tmp == 1) return 1; // Early out. 1894 1895 // Special case decrementing a value (ADD X, -1): 1896 if (ConstantSDNode *CRHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) 1897 if (CRHS->isAllOnesValue()) { 1898 APInt KnownZero, KnownOne; 1899 APInt Mask = APInt::getAllOnesValue(VTBits); 1900 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1); 1901 1902 // If the input is known to be 0 or 1, the output is 0/-1, which is all 1903 // sign bits set. 1904 if ((KnownZero | APInt(VTBits, 1)) == Mask) 1905 return VTBits; 1906 1907 // If we are subtracting one from a positive number, there is no carry 1908 // out of the result. 1909 if (KnownZero.isNegative()) 1910 return Tmp; 1911 } 1912 1913 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 1914 if (Tmp2 == 1) return 1; 1915 return std::min(Tmp, Tmp2)-1; 1916 break; 1917 1918 case ISD::SUB: 1919 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 1920 if (Tmp2 == 1) return 1; 1921 1922 // Handle NEG. 1923 if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) 1924 if (CLHS->isNullValue()) { 1925 APInt KnownZero, KnownOne; 1926 APInt Mask = APInt::getAllOnesValue(VTBits); 1927 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1928 // If the input is known to be 0 or 1, the output is 0/-1, which is all 1929 // sign bits set. 1930 if ((KnownZero | APInt(VTBits, 1)) == Mask) 1931 return VTBits; 1932 1933 // If the input is known to be positive (the sign bit is known clear), 1934 // the output of the NEG has the same number of sign bits as the input. 1935 if (KnownZero.isNegative()) 1936 return Tmp2; 1937 1938 // Otherwise, we treat this like a SUB. 1939 } 1940 1941 // Sub can have at most one carry bit. Thus we know that the output 1942 // is, at worst, one more bit than the inputs. 1943 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1944 if (Tmp == 1) return 1; // Early out. 1945 return std::min(Tmp, Tmp2)-1; 1946 break; 1947 case ISD::TRUNCATE: 1948 // FIXME: it's tricky to do anything useful for this, but it is an important 1949 // case for targets like X86. 1950 break; 1951 } 1952 1953 // Handle LOADX separately here. EXTLOAD case will fallthrough. 1954 if (Op.getOpcode() == ISD::LOAD) { 1955 LoadSDNode *LD = cast<LoadSDNode>(Op); 1956 unsigned ExtType = LD->getExtensionType(); 1957 switch (ExtType) { 1958 default: break; 1959 case ISD::SEXTLOAD: // '17' bits known 1960 Tmp = LD->getMemoryVT().getSizeInBits(); 1961 return VTBits-Tmp+1; 1962 case ISD::ZEXTLOAD: // '16' bits known 1963 Tmp = LD->getMemoryVT().getSizeInBits(); 1964 return VTBits-Tmp; 1965 } 1966 } 1967 1968 // Allow the target to implement this method for its nodes. 1969 if (Op.getOpcode() >= ISD::BUILTIN_OP_END || 1970 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1971 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1972 Op.getOpcode() == ISD::INTRINSIC_VOID) { 1973 unsigned NumBits = TLI.ComputeNumSignBitsForTargetNode(Op, Depth); 1974 if (NumBits > 1) FirstAnswer = std::max(FirstAnswer, NumBits); 1975 } 1976 1977 // Finally, if we can prove that the top bits of the result are 0's or 1's, 1978 // use this information. 1979 APInt KnownZero, KnownOne; 1980 APInt Mask = APInt::getAllOnesValue(VTBits); 1981 ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth); 1982 1983 if (KnownZero.isNegative()) { // sign bit is 0 1984 Mask = KnownZero; 1985 } else if (KnownOne.isNegative()) { // sign bit is 1; 1986 Mask = KnownOne; 1987 } else { 1988 // Nothing known. 1989 return FirstAnswer; 1990 } 1991 1992 // Okay, we know that the sign bit in Mask is set. Use CLZ to determine 1993 // the number of identical bits in the top of the input value. 1994 Mask = ~Mask; 1995 Mask <<= Mask.getBitWidth()-VTBits; 1996 // Return # leading zeros. We use 'min' here in case Val was zero before 1997 // shifting. We don't want to return '64' as for an i32 "0". 1998 return std::max(FirstAnswer, std::min(VTBits, Mask.countLeadingZeros())); 1999} 2000 2001 2002bool SelectionDAG::isVerifiedDebugInfoDesc(SDValue Op) const { 2003 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op); 2004 if (!GA) return false; 2005 if (GA->getOffset() != 0) return false; 2006 GlobalVariable *GV = dyn_cast<GlobalVariable>(GA->getGlobal()); 2007 if (!GV) return false; 2008 MachineModuleInfo *MMI = getMachineModuleInfo(); 2009 return MMI && MMI->hasDebugInfo() && MMI->isVerified(GV); 2010} 2011 2012 2013/// getShuffleScalarElt - Returns the scalar element that will make up the ith 2014/// element of the result of the vector shuffle. 2015SDValue SelectionDAG::getShuffleScalarElt(const SDNode *N, unsigned i) { 2016 MVT VT = N->getValueType(0); 2017 SDValue PermMask = N->getOperand(2); 2018 SDValue Idx = PermMask.getOperand(i); 2019 if (Idx.getOpcode() == ISD::UNDEF) 2020 return getNode(ISD::UNDEF, VT.getVectorElementType()); 2021 unsigned Index = cast<ConstantSDNode>(Idx)->getZExtValue(); 2022 unsigned NumElems = PermMask.getNumOperands(); 2023 SDValue V = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1); 2024 Index %= NumElems; 2025 2026 if (V.getOpcode() == ISD::BIT_CONVERT) { 2027 V = V.getOperand(0); 2028 if (V.getValueType().getVectorNumElements() != NumElems) 2029 return SDValue(); 2030 } 2031 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) 2032 return (Index == 0) ? V.getOperand(0) 2033 : getNode(ISD::UNDEF, VT.getVectorElementType()); 2034 if (V.getOpcode() == ISD::BUILD_VECTOR) 2035 return V.getOperand(Index); 2036 if (V.getOpcode() == ISD::VECTOR_SHUFFLE) 2037 return getShuffleScalarElt(V.getNode(), Index); 2038 return SDValue(); 2039} 2040 2041 2042/// getNode - Gets or creates the specified node. 2043/// 2044SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT) { 2045 FoldingSetNodeID ID; 2046 AddNodeIDNode(ID, Opcode, getVTList(VT), 0, 0); 2047 void *IP = 0; 2048 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2049 return SDValue(E, 0); 2050 SDNode *N = NodeAllocator.Allocate<SDNode>(); 2051 new (N) SDNode(Opcode, SDNode::getSDVTList(VT)); 2052 CSEMap.InsertNode(N, IP); 2053 2054 AllNodes.push_back(N); 2055#ifndef NDEBUG 2056 VerifyNode(N); 2057#endif 2058 return SDValue(N, 0); 2059} 2060 2061SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, SDValue Operand) { 2062 // Constant fold unary operations with an integer constant operand. 2063 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Operand.getNode())) { 2064 const APInt &Val = C->getAPIntValue(); 2065 unsigned BitWidth = VT.getSizeInBits(); 2066 switch (Opcode) { 2067 default: break; 2068 case ISD::SIGN_EXTEND: 2069 return getConstant(APInt(Val).sextOrTrunc(BitWidth), VT); 2070 case ISD::ANY_EXTEND: 2071 case ISD::ZERO_EXTEND: 2072 case ISD::TRUNCATE: 2073 return getConstant(APInt(Val).zextOrTrunc(BitWidth), VT); 2074 case ISD::UINT_TO_FP: 2075 case ISD::SINT_TO_FP: { 2076 const uint64_t zero[] = {0, 0}; 2077 // No compile time operations on this type. 2078 if (VT==MVT::ppcf128) 2079 break; 2080 APFloat apf = APFloat(APInt(BitWidth, 2, zero)); 2081 (void)apf.convertFromAPInt(Val, 2082 Opcode==ISD::SINT_TO_FP, 2083 APFloat::rmNearestTiesToEven); 2084 return getConstantFP(apf, VT); 2085 } 2086 case ISD::BIT_CONVERT: 2087 if (VT == MVT::f32 && C->getValueType(0) == MVT::i32) 2088 return getConstantFP(Val.bitsToFloat(), VT); 2089 else if (VT == MVT::f64 && C->getValueType(0) == MVT::i64) 2090 return getConstantFP(Val.bitsToDouble(), VT); 2091 break; 2092 case ISD::BSWAP: 2093 return getConstant(Val.byteSwap(), VT); 2094 case ISD::CTPOP: 2095 return getConstant(Val.countPopulation(), VT); 2096 case ISD::CTLZ: 2097 return getConstant(Val.countLeadingZeros(), VT); 2098 case ISD::CTTZ: 2099 return getConstant(Val.countTrailingZeros(), VT); 2100 } 2101 } 2102 2103 // Constant fold unary operations with a floating point constant operand. 2104 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Operand.getNode())) { 2105 APFloat V = C->getValueAPF(); // make copy 2106 if (VT != MVT::ppcf128 && Operand.getValueType() != MVT::ppcf128) { 2107 switch (Opcode) { 2108 case ISD::FNEG: 2109 V.changeSign(); 2110 return getConstantFP(V, VT); 2111 case ISD::FABS: 2112 V.clearSign(); 2113 return getConstantFP(V, VT); 2114 case ISD::FP_ROUND: 2115 case ISD::FP_EXTEND: { 2116 bool ignored; 2117 // This can return overflow, underflow, or inexact; we don't care. 2118 // FIXME need to be more flexible about rounding mode. 2119 (void)V.convert(*MVTToAPFloatSemantics(VT), 2120 APFloat::rmNearestTiesToEven, &ignored); 2121 return getConstantFP(V, VT); 2122 } 2123 case ISD::FP_TO_SINT: 2124 case ISD::FP_TO_UINT: { 2125 integerPart x; 2126 bool ignored; 2127 assert(integerPartWidth >= 64); 2128 // FIXME need to be more flexible about rounding mode. 2129 APFloat::opStatus s = V.convertToInteger(&x, 64U, 2130 Opcode==ISD::FP_TO_SINT, 2131 APFloat::rmTowardZero, &ignored); 2132 if (s==APFloat::opInvalidOp) // inexact is OK, in fact usual 2133 break; 2134 return getConstant(x, VT); 2135 } 2136 case ISD::BIT_CONVERT: 2137 if (VT == MVT::i32 && C->getValueType(0) == MVT::f32) 2138 return getConstant((uint32_t)V.bitcastToAPInt().getZExtValue(), VT); 2139 else if (VT == MVT::i64 && C->getValueType(0) == MVT::f64) 2140 return getConstant(V.bitcastToAPInt().getZExtValue(), VT); 2141 break; 2142 } 2143 } 2144 } 2145 2146 unsigned OpOpcode = Operand.getNode()->getOpcode(); 2147 switch (Opcode) { 2148 case ISD::TokenFactor: 2149 case ISD::CONCAT_VECTORS: 2150 return Operand; // Factor or concat of one node? No need. 2151 case ISD::FP_ROUND: assert(0 && "Invalid method to make FP_ROUND node"); 2152 case ISD::FP_EXTEND: 2153 assert(VT.isFloatingPoint() && 2154 Operand.getValueType().isFloatingPoint() && "Invalid FP cast!"); 2155 if (Operand.getValueType() == VT) return Operand; // noop conversion. 2156 if (Operand.getOpcode() == ISD::UNDEF) 2157 return getNode(ISD::UNDEF, VT); 2158 break; 2159 case ISD::SIGN_EXTEND: 2160 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2161 "Invalid SIGN_EXTEND!"); 2162 if (Operand.getValueType() == VT) return Operand; // noop extension 2163 assert(Operand.getValueType().bitsLT(VT) 2164 && "Invalid sext node, dst < src!"); 2165 if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND) 2166 return getNode(OpOpcode, VT, Operand.getNode()->getOperand(0)); 2167 break; 2168 case ISD::ZERO_EXTEND: 2169 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2170 "Invalid ZERO_EXTEND!"); 2171 if (Operand.getValueType() == VT) return Operand; // noop extension 2172 assert(Operand.getValueType().bitsLT(VT) 2173 && "Invalid zext node, dst < src!"); 2174 if (OpOpcode == ISD::ZERO_EXTEND) // (zext (zext x)) -> (zext x) 2175 return getNode(ISD::ZERO_EXTEND, VT, Operand.getNode()->getOperand(0)); 2176 break; 2177 case ISD::ANY_EXTEND: 2178 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2179 "Invalid ANY_EXTEND!"); 2180 if (Operand.getValueType() == VT) return Operand; // noop extension 2181 assert(Operand.getValueType().bitsLT(VT) 2182 && "Invalid anyext node, dst < src!"); 2183 if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND) 2184 // (ext (zext x)) -> (zext x) and (ext (sext x)) -> (sext x) 2185 return getNode(OpOpcode, VT, Operand.getNode()->getOperand(0)); 2186 break; 2187 case ISD::TRUNCATE: 2188 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2189 "Invalid TRUNCATE!"); 2190 if (Operand.getValueType() == VT) return Operand; // noop truncate 2191 assert(Operand.getValueType().bitsGT(VT) 2192 && "Invalid truncate node, src < dst!"); 2193 if (OpOpcode == ISD::TRUNCATE) 2194 return getNode(ISD::TRUNCATE, VT, Operand.getNode()->getOperand(0)); 2195 else if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND || 2196 OpOpcode == ISD::ANY_EXTEND) { 2197 // If the source is smaller than the dest, we still need an extend. 2198 if (Operand.getNode()->getOperand(0).getValueType().bitsLT(VT)) 2199 return getNode(OpOpcode, VT, Operand.getNode()->getOperand(0)); 2200 else if (Operand.getNode()->getOperand(0).getValueType().bitsGT(VT)) 2201 return getNode(ISD::TRUNCATE, VT, Operand.getNode()->getOperand(0)); 2202 else 2203 return Operand.getNode()->getOperand(0); 2204 } 2205 break; 2206 case ISD::BIT_CONVERT: 2207 // Basic sanity checking. 2208 assert(VT.getSizeInBits() == Operand.getValueType().getSizeInBits() 2209 && "Cannot BIT_CONVERT between types of different sizes!"); 2210 if (VT == Operand.getValueType()) return Operand; // noop conversion. 2211 if (OpOpcode == ISD::BIT_CONVERT) // bitconv(bitconv(x)) -> bitconv(x) 2212 return getNode(ISD::BIT_CONVERT, VT, Operand.getOperand(0)); 2213 if (OpOpcode == ISD::UNDEF) 2214 return getNode(ISD::UNDEF, VT); 2215 break; 2216 case ISD::SCALAR_TO_VECTOR: 2217 assert(VT.isVector() && !Operand.getValueType().isVector() && 2218 VT.getVectorElementType() == Operand.getValueType() && 2219 "Illegal SCALAR_TO_VECTOR node!"); 2220 if (OpOpcode == ISD::UNDEF) 2221 return getNode(ISD::UNDEF, VT); 2222 // scalar_to_vector(extract_vector_elt V, 0) -> V, top bits are undefined. 2223 if (OpOpcode == ISD::EXTRACT_VECTOR_ELT && 2224 isa<ConstantSDNode>(Operand.getOperand(1)) && 2225 Operand.getConstantOperandVal(1) == 0 && 2226 Operand.getOperand(0).getValueType() == VT) 2227 return Operand.getOperand(0); 2228 break; 2229 case ISD::FNEG: 2230 if (OpOpcode == ISD::FSUB) // -(X-Y) -> (Y-X) 2231 return getNode(ISD::FSUB, VT, Operand.getNode()->getOperand(1), 2232 Operand.getNode()->getOperand(0)); 2233 if (OpOpcode == ISD::FNEG) // --X -> X 2234 return Operand.getNode()->getOperand(0); 2235 break; 2236 case ISD::FABS: 2237 if (OpOpcode == ISD::FNEG) // abs(-X) -> abs(X) 2238 return getNode(ISD::FABS, VT, Operand.getNode()->getOperand(0)); 2239 break; 2240 } 2241 2242 SDNode *N; 2243 SDVTList VTs = getVTList(VT); 2244 if (VT != MVT::Flag) { // Don't CSE flag producing nodes 2245 FoldingSetNodeID ID; 2246 SDValue Ops[1] = { Operand }; 2247 AddNodeIDNode(ID, Opcode, VTs, Ops, 1); 2248 void *IP = 0; 2249 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2250 return SDValue(E, 0); 2251 N = NodeAllocator.Allocate<UnarySDNode>(); 2252 new (N) UnarySDNode(Opcode, VTs, Operand); 2253 CSEMap.InsertNode(N, IP); 2254 } else { 2255 N = NodeAllocator.Allocate<UnarySDNode>(); 2256 new (N) UnarySDNode(Opcode, VTs, Operand); 2257 } 2258 2259 AllNodes.push_back(N); 2260#ifndef NDEBUG 2261 VerifyNode(N); 2262#endif 2263 return SDValue(N, 0); 2264} 2265 2266SDValue SelectionDAG::FoldConstantArithmetic(unsigned Opcode, 2267 MVT VT, 2268 ConstantSDNode *Cst1, 2269 ConstantSDNode *Cst2) { 2270 const APInt &C1 = Cst1->getAPIntValue(), &C2 = Cst2->getAPIntValue(); 2271 2272 switch (Opcode) { 2273 case ISD::ADD: return getConstant(C1 + C2, VT); 2274 case ISD::SUB: return getConstant(C1 - C2, VT); 2275 case ISD::MUL: return getConstant(C1 * C2, VT); 2276 case ISD::UDIV: 2277 if (C2.getBoolValue()) return getConstant(C1.udiv(C2), VT); 2278 break; 2279 case ISD::UREM: 2280 if (C2.getBoolValue()) return getConstant(C1.urem(C2), VT); 2281 break; 2282 case ISD::SDIV: 2283 if (C2.getBoolValue()) return getConstant(C1.sdiv(C2), VT); 2284 break; 2285 case ISD::SREM: 2286 if (C2.getBoolValue()) return getConstant(C1.srem(C2), VT); 2287 break; 2288 case ISD::AND: return getConstant(C1 & C2, VT); 2289 case ISD::OR: return getConstant(C1 | C2, VT); 2290 case ISD::XOR: return getConstant(C1 ^ C2, VT); 2291 case ISD::SHL: return getConstant(C1 << C2, VT); 2292 case ISD::SRL: return getConstant(C1.lshr(C2), VT); 2293 case ISD::SRA: return getConstant(C1.ashr(C2), VT); 2294 case ISD::ROTL: return getConstant(C1.rotl(C2), VT); 2295 case ISD::ROTR: return getConstant(C1.rotr(C2), VT); 2296 default: break; 2297 } 2298 2299 return SDValue(); 2300} 2301 2302SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, 2303 SDValue N1, SDValue N2) { 2304 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 2305 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 2306 switch (Opcode) { 2307 default: break; 2308 case ISD::TokenFactor: 2309 assert(VT == MVT::Other && N1.getValueType() == MVT::Other && 2310 N2.getValueType() == MVT::Other && "Invalid token factor!"); 2311 // Fold trivial token factors. 2312 if (N1.getOpcode() == ISD::EntryToken) return N2; 2313 if (N2.getOpcode() == ISD::EntryToken) return N1; 2314 if (N1 == N2) return N1; 2315 break; 2316 case ISD::CONCAT_VECTORS: 2317 // A CONCAT_VECTOR with all operands BUILD_VECTOR can be simplified to 2318 // one big BUILD_VECTOR. 2319 if (N1.getOpcode() == ISD::BUILD_VECTOR && 2320 N2.getOpcode() == ISD::BUILD_VECTOR) { 2321 SmallVector<SDValue, 16> Elts(N1.getNode()->op_begin(), N1.getNode()->op_end()); 2322 Elts.insert(Elts.end(), N2.getNode()->op_begin(), N2.getNode()->op_end()); 2323 return getNode(ISD::BUILD_VECTOR, VT, &Elts[0], Elts.size()); 2324 } 2325 break; 2326 case ISD::AND: 2327 assert(VT.isInteger() && N1.getValueType() == N2.getValueType() && 2328 N1.getValueType() == VT && "Binary operator types must match!"); 2329 // (X & 0) -> 0. This commonly occurs when legalizing i64 values, so it's 2330 // worth handling here. 2331 if (N2C && N2C->isNullValue()) 2332 return N2; 2333 if (N2C && N2C->isAllOnesValue()) // X & -1 -> X 2334 return N1; 2335 break; 2336 case ISD::OR: 2337 case ISD::XOR: 2338 case ISD::ADD: 2339 case ISD::SUB: 2340 assert(VT.isInteger() && N1.getValueType() == N2.getValueType() && 2341 N1.getValueType() == VT && "Binary operator types must match!"); 2342 // (X ^|+- 0) -> X. This commonly occurs when legalizing i64 values, so 2343 // it's worth handling here. 2344 if (N2C && N2C->isNullValue()) 2345 return N1; 2346 break; 2347 case ISD::UDIV: 2348 case ISD::UREM: 2349 case ISD::MULHU: 2350 case ISD::MULHS: 2351 assert(VT.isInteger() && "This operator does not apply to FP types!"); 2352 // fall through 2353 case ISD::MUL: 2354 case ISD::SDIV: 2355 case ISD::SREM: 2356 case ISD::FADD: 2357 case ISD::FSUB: 2358 case ISD::FMUL: 2359 case ISD::FDIV: 2360 case ISD::FREM: 2361 assert(N1.getValueType() == N2.getValueType() && 2362 N1.getValueType() == VT && "Binary operator types must match!"); 2363 break; 2364 case ISD::FCOPYSIGN: // N1 and result must match. N1/N2 need not match. 2365 assert(N1.getValueType() == VT && 2366 N1.getValueType().isFloatingPoint() && 2367 N2.getValueType().isFloatingPoint() && 2368 "Invalid FCOPYSIGN!"); 2369 break; 2370 case ISD::SHL: 2371 case ISD::SRA: 2372 case ISD::SRL: 2373 case ISD::ROTL: 2374 case ISD::ROTR: 2375 assert(VT == N1.getValueType() && 2376 "Shift operators return type must be the same as their first arg"); 2377 assert(VT.isInteger() && N2.getValueType().isInteger() && 2378 "Shifts only work on integers"); 2379 2380 // Always fold shifts of i1 values so the code generator doesn't need to 2381 // handle them. Since we know the size of the shift has to be less than the 2382 // size of the value, the shift/rotate count is guaranteed to be zero. 2383 if (VT == MVT::i1) 2384 return N1; 2385 break; 2386 case ISD::FP_ROUND_INREG: { 2387 MVT EVT = cast<VTSDNode>(N2)->getVT(); 2388 assert(VT == N1.getValueType() && "Not an inreg round!"); 2389 assert(VT.isFloatingPoint() && EVT.isFloatingPoint() && 2390 "Cannot FP_ROUND_INREG integer types"); 2391 assert(EVT.bitsLE(VT) && "Not rounding down!"); 2392 if (cast<VTSDNode>(N2)->getVT() == VT) return N1; // Not actually rounding. 2393 break; 2394 } 2395 case ISD::FP_ROUND: 2396 assert(VT.isFloatingPoint() && 2397 N1.getValueType().isFloatingPoint() && 2398 VT.bitsLE(N1.getValueType()) && 2399 isa<ConstantSDNode>(N2) && "Invalid FP_ROUND!"); 2400 if (N1.getValueType() == VT) return N1; // noop conversion. 2401 break; 2402 case ISD::AssertSext: 2403 case ISD::AssertZext: { 2404 MVT EVT = cast<VTSDNode>(N2)->getVT(); 2405 assert(VT == N1.getValueType() && "Not an inreg extend!"); 2406 assert(VT.isInteger() && EVT.isInteger() && 2407 "Cannot *_EXTEND_INREG FP types"); 2408 assert(EVT.bitsLE(VT) && "Not extending!"); 2409 if (VT == EVT) return N1; // noop assertion. 2410 break; 2411 } 2412 case ISD::SIGN_EXTEND_INREG: { 2413 MVT EVT = cast<VTSDNode>(N2)->getVT(); 2414 assert(VT == N1.getValueType() && "Not an inreg extend!"); 2415 assert(VT.isInteger() && EVT.isInteger() && 2416 "Cannot *_EXTEND_INREG FP types"); 2417 assert(EVT.bitsLE(VT) && "Not extending!"); 2418 if (EVT == VT) return N1; // Not actually extending 2419 2420 if (N1C) { 2421 APInt Val = N1C->getAPIntValue(); 2422 unsigned FromBits = cast<VTSDNode>(N2)->getVT().getSizeInBits(); 2423 Val <<= Val.getBitWidth()-FromBits; 2424 Val = Val.ashr(Val.getBitWidth()-FromBits); 2425 return getConstant(Val, VT); 2426 } 2427 break; 2428 } 2429 case ISD::EXTRACT_VECTOR_ELT: 2430 // EXTRACT_VECTOR_ELT of an UNDEF is an UNDEF. 2431 if (N1.getOpcode() == ISD::UNDEF) 2432 return getNode(ISD::UNDEF, VT); 2433 2434 // EXTRACT_VECTOR_ELT of CONCAT_VECTORS is often formed while lowering is 2435 // expanding copies of large vectors from registers. 2436 if (N2C && 2437 N1.getOpcode() == ISD::CONCAT_VECTORS && 2438 N1.getNumOperands() > 0) { 2439 unsigned Factor = 2440 N1.getOperand(0).getValueType().getVectorNumElements(); 2441 return getNode(ISD::EXTRACT_VECTOR_ELT, VT, 2442 N1.getOperand(N2C->getZExtValue() / Factor), 2443 getConstant(N2C->getZExtValue() % Factor, 2444 N2.getValueType())); 2445 } 2446 2447 // EXTRACT_VECTOR_ELT of BUILD_VECTOR is often formed while lowering is 2448 // expanding large vector constants. 2449 if (N2C && N1.getOpcode() == ISD::BUILD_VECTOR) 2450 return N1.getOperand(N2C->getZExtValue()); 2451 2452 // EXTRACT_VECTOR_ELT of INSERT_VECTOR_ELT is often formed when vector 2453 // operations are lowered to scalars. 2454 if (N1.getOpcode() == ISD::INSERT_VECTOR_ELT) { 2455 if (N1.getOperand(2) == N2) 2456 return N1.getOperand(1); 2457 else 2458 return getNode(ISD::EXTRACT_VECTOR_ELT, VT, N1.getOperand(0), N2); 2459 } 2460 break; 2461 case ISD::EXTRACT_ELEMENT: 2462 assert(N2C && (unsigned)N2C->getZExtValue() < 2 && "Bad EXTRACT_ELEMENT!"); 2463 assert(!N1.getValueType().isVector() && !VT.isVector() && 2464 (N1.getValueType().isInteger() == VT.isInteger()) && 2465 "Wrong types for EXTRACT_ELEMENT!"); 2466 2467 // EXTRACT_ELEMENT of BUILD_PAIR is often formed while legalize is expanding 2468 // 64-bit integers into 32-bit parts. Instead of building the extract of 2469 // the BUILD_PAIR, only to have legalize rip it apart, just do it now. 2470 if (N1.getOpcode() == ISD::BUILD_PAIR) 2471 return N1.getOperand(N2C->getZExtValue()); 2472 2473 // EXTRACT_ELEMENT of a constant int is also very common. 2474 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) { 2475 unsigned ElementSize = VT.getSizeInBits(); 2476 unsigned Shift = ElementSize * N2C->getZExtValue(); 2477 APInt ShiftedVal = C->getAPIntValue().lshr(Shift); 2478 return getConstant(ShiftedVal.trunc(ElementSize), VT); 2479 } 2480 break; 2481 case ISD::EXTRACT_SUBVECTOR: 2482 if (N1.getValueType() == VT) // Trivial extraction. 2483 return N1; 2484 break; 2485 } 2486 2487 if (N1C) { 2488 if (N2C) { 2489 SDValue SV = FoldConstantArithmetic(Opcode, VT, N1C, N2C); 2490 if (SV.getNode()) return SV; 2491 } else { // Cannonicalize constant to RHS if commutative 2492 if (isCommutativeBinOp(Opcode)) { 2493 std::swap(N1C, N2C); 2494 std::swap(N1, N2); 2495 } 2496 } 2497 } 2498 2499 // Constant fold FP operations. 2500 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1.getNode()); 2501 ConstantFPSDNode *N2CFP = dyn_cast<ConstantFPSDNode>(N2.getNode()); 2502 if (N1CFP) { 2503 if (!N2CFP && isCommutativeBinOp(Opcode)) { 2504 // Cannonicalize constant to RHS if commutative 2505 std::swap(N1CFP, N2CFP); 2506 std::swap(N1, N2); 2507 } else if (N2CFP && VT != MVT::ppcf128) { 2508 APFloat V1 = N1CFP->getValueAPF(), V2 = N2CFP->getValueAPF(); 2509 APFloat::opStatus s; 2510 switch (Opcode) { 2511 case ISD::FADD: 2512 s = V1.add(V2, APFloat::rmNearestTiesToEven); 2513 if (s != APFloat::opInvalidOp) 2514 return getConstantFP(V1, VT); 2515 break; 2516 case ISD::FSUB: 2517 s = V1.subtract(V2, APFloat::rmNearestTiesToEven); 2518 if (s!=APFloat::opInvalidOp) 2519 return getConstantFP(V1, VT); 2520 break; 2521 case ISD::FMUL: 2522 s = V1.multiply(V2, APFloat::rmNearestTiesToEven); 2523 if (s!=APFloat::opInvalidOp) 2524 return getConstantFP(V1, VT); 2525 break; 2526 case ISD::FDIV: 2527 s = V1.divide(V2, APFloat::rmNearestTiesToEven); 2528 if (s!=APFloat::opInvalidOp && s!=APFloat::opDivByZero) 2529 return getConstantFP(V1, VT); 2530 break; 2531 case ISD::FREM : 2532 s = V1.mod(V2, APFloat::rmNearestTiesToEven); 2533 if (s!=APFloat::opInvalidOp && s!=APFloat::opDivByZero) 2534 return getConstantFP(V1, VT); 2535 break; 2536 case ISD::FCOPYSIGN: 2537 V1.copySign(V2); 2538 return getConstantFP(V1, VT); 2539 default: break; 2540 } 2541 } 2542 } 2543 2544 // Canonicalize an UNDEF to the RHS, even over a constant. 2545 if (N1.getOpcode() == ISD::UNDEF) { 2546 if (isCommutativeBinOp(Opcode)) { 2547 std::swap(N1, N2); 2548 } else { 2549 switch (Opcode) { 2550 case ISD::FP_ROUND_INREG: 2551 case ISD::SIGN_EXTEND_INREG: 2552 case ISD::SUB: 2553 case ISD::FSUB: 2554 case ISD::FDIV: 2555 case ISD::FREM: 2556 case ISD::SRA: 2557 return N1; // fold op(undef, arg2) -> undef 2558 case ISD::UDIV: 2559 case ISD::SDIV: 2560 case ISD::UREM: 2561 case ISD::SREM: 2562 case ISD::SRL: 2563 case ISD::SHL: 2564 if (!VT.isVector()) 2565 return getConstant(0, VT); // fold op(undef, arg2) -> 0 2566 // For vectors, we can't easily build an all zero vector, just return 2567 // the LHS. 2568 return N2; 2569 } 2570 } 2571 } 2572 2573 // Fold a bunch of operators when the RHS is undef. 2574 if (N2.getOpcode() == ISD::UNDEF) { 2575 switch (Opcode) { 2576 case ISD::XOR: 2577 if (N1.getOpcode() == ISD::UNDEF) 2578 // Handle undef ^ undef -> 0 special case. This is a common 2579 // idiom (misuse). 2580 return getConstant(0, VT); 2581 // fallthrough 2582 case ISD::ADD: 2583 case ISD::ADDC: 2584 case ISD::ADDE: 2585 case ISD::SUB: 2586 case ISD::FADD: 2587 case ISD::FSUB: 2588 case ISD::FMUL: 2589 case ISD::FDIV: 2590 case ISD::FREM: 2591 case ISD::UDIV: 2592 case ISD::SDIV: 2593 case ISD::UREM: 2594 case ISD::SREM: 2595 return N2; // fold op(arg1, undef) -> undef 2596 case ISD::MUL: 2597 case ISD::AND: 2598 case ISD::SRL: 2599 case ISD::SHL: 2600 if (!VT.isVector()) 2601 return getConstant(0, VT); // fold op(arg1, undef) -> 0 2602 // For vectors, we can't easily build an all zero vector, just return 2603 // the LHS. 2604 return N1; 2605 case ISD::OR: 2606 if (!VT.isVector()) 2607 return getConstant(VT.getIntegerVTBitMask(), VT); 2608 // For vectors, we can't easily build an all one vector, just return 2609 // the LHS. 2610 return N1; 2611 case ISD::SRA: 2612 return N1; 2613 } 2614 } 2615 2616 // Memoize this node if possible. 2617 SDNode *N; 2618 SDVTList VTs = getVTList(VT); 2619 if (VT != MVT::Flag) { 2620 SDValue Ops[] = { N1, N2 }; 2621 FoldingSetNodeID ID; 2622 AddNodeIDNode(ID, Opcode, VTs, Ops, 2); 2623 void *IP = 0; 2624 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2625 return SDValue(E, 0); 2626 N = NodeAllocator.Allocate<BinarySDNode>(); 2627 new (N) BinarySDNode(Opcode, VTs, N1, N2); 2628 CSEMap.InsertNode(N, IP); 2629 } else { 2630 N = NodeAllocator.Allocate<BinarySDNode>(); 2631 new (N) BinarySDNode(Opcode, VTs, N1, N2); 2632 } 2633 2634 AllNodes.push_back(N); 2635#ifndef NDEBUG 2636 VerifyNode(N); 2637#endif 2638 return SDValue(N, 0); 2639} 2640 2641SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, 2642 SDValue N1, SDValue N2, SDValue N3) { 2643 // Perform various simplifications. 2644 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 2645 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 2646 switch (Opcode) { 2647 case ISD::CONCAT_VECTORS: 2648 // A CONCAT_VECTOR with all operands BUILD_VECTOR can be simplified to 2649 // one big BUILD_VECTOR. 2650 if (N1.getOpcode() == ISD::BUILD_VECTOR && 2651 N2.getOpcode() == ISD::BUILD_VECTOR && 2652 N3.getOpcode() == ISD::BUILD_VECTOR) { 2653 SmallVector<SDValue, 16> Elts(N1.getNode()->op_begin(), N1.getNode()->op_end()); 2654 Elts.insert(Elts.end(), N2.getNode()->op_begin(), N2.getNode()->op_end()); 2655 Elts.insert(Elts.end(), N3.getNode()->op_begin(), N3.getNode()->op_end()); 2656 return getNode(ISD::BUILD_VECTOR, VT, &Elts[0], Elts.size()); 2657 } 2658 break; 2659 case ISD::SETCC: { 2660 // Use FoldSetCC to simplify SETCC's. 2661 SDValue Simp = FoldSetCC(VT, N1, N2, cast<CondCodeSDNode>(N3)->get()); 2662 if (Simp.getNode()) return Simp; 2663 break; 2664 } 2665 case ISD::SELECT: 2666 if (N1C) { 2667 if (N1C->getZExtValue()) 2668 return N2; // select true, X, Y -> X 2669 else 2670 return N3; // select false, X, Y -> Y 2671 } 2672 2673 if (N2 == N3) return N2; // select C, X, X -> X 2674 break; 2675 case ISD::BRCOND: 2676 if (N2C) { 2677 if (N2C->getZExtValue()) // Unconditional branch 2678 return getNode(ISD::BR, MVT::Other, N1, N3); 2679 else 2680 return N1; // Never-taken branch 2681 } 2682 break; 2683 case ISD::VECTOR_SHUFFLE: 2684 assert(VT == N1.getValueType() && VT == N2.getValueType() && 2685 VT.isVector() && N3.getValueType().isVector() && 2686 N3.getOpcode() == ISD::BUILD_VECTOR && 2687 VT.getVectorNumElements() == N3.getNumOperands() && 2688 "Illegal VECTOR_SHUFFLE node!"); 2689 break; 2690 case ISD::BIT_CONVERT: 2691 // Fold bit_convert nodes from a type to themselves. 2692 if (N1.getValueType() == VT) 2693 return N1; 2694 break; 2695 } 2696 2697 // Memoize node if it doesn't produce a flag. 2698 SDNode *N; 2699 SDVTList VTs = getVTList(VT); 2700 if (VT != MVT::Flag) { 2701 SDValue Ops[] = { N1, N2, N3 }; 2702 FoldingSetNodeID ID; 2703 AddNodeIDNode(ID, Opcode, VTs, Ops, 3); 2704 void *IP = 0; 2705 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2706 return SDValue(E, 0); 2707 N = NodeAllocator.Allocate<TernarySDNode>(); 2708 new (N) TernarySDNode(Opcode, VTs, N1, N2, N3); 2709 CSEMap.InsertNode(N, IP); 2710 } else { 2711 N = NodeAllocator.Allocate<TernarySDNode>(); 2712 new (N) TernarySDNode(Opcode, VTs, N1, N2, N3); 2713 } 2714 AllNodes.push_back(N); 2715#ifndef NDEBUG 2716 VerifyNode(N); 2717#endif 2718 return SDValue(N, 0); 2719} 2720 2721SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, 2722 SDValue N1, SDValue N2, SDValue N3, 2723 SDValue N4) { 2724 SDValue Ops[] = { N1, N2, N3, N4 }; 2725 return getNode(Opcode, VT, Ops, 4); 2726} 2727 2728SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, 2729 SDValue N1, SDValue N2, SDValue N3, 2730 SDValue N4, SDValue N5) { 2731 SDValue Ops[] = { N1, N2, N3, N4, N5 }; 2732 return getNode(Opcode, VT, Ops, 5); 2733} 2734 2735/// getMemsetValue - Vectorized representation of the memset value 2736/// operand. 2737static SDValue getMemsetValue(SDValue Value, MVT VT, SelectionDAG &DAG) { 2738 unsigned NumBits = VT.isVector() ? 2739 VT.getVectorElementType().getSizeInBits() : VT.getSizeInBits(); 2740 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) { 2741 APInt Val = APInt(NumBits, C->getZExtValue() & 255); 2742 unsigned Shift = 8; 2743 for (unsigned i = NumBits; i > 8; i >>= 1) { 2744 Val = (Val << Shift) | Val; 2745 Shift <<= 1; 2746 } 2747 if (VT.isInteger()) 2748 return DAG.getConstant(Val, VT); 2749 return DAG.getConstantFP(APFloat(Val), VT); 2750 } 2751 2752 Value = DAG.getNode(ISD::ZERO_EXTEND, VT, Value); 2753 unsigned Shift = 8; 2754 for (unsigned i = NumBits; i > 8; i >>= 1) { 2755 Value = DAG.getNode(ISD::OR, VT, 2756 DAG.getNode(ISD::SHL, VT, Value, 2757 DAG.getConstant(Shift, MVT::i8)), Value); 2758 Shift <<= 1; 2759 } 2760 2761 return Value; 2762} 2763 2764/// getMemsetStringVal - Similar to getMemsetValue. Except this is only 2765/// used when a memcpy is turned into a memset when the source is a constant 2766/// string ptr. 2767static SDValue getMemsetStringVal(MVT VT, SelectionDAG &DAG, 2768 const TargetLowering &TLI, 2769 std::string &Str, unsigned Offset) { 2770 // Handle vector with all elements zero. 2771 if (Str.empty()) { 2772 if (VT.isInteger()) 2773 return DAG.getConstant(0, VT); 2774 unsigned NumElts = VT.getVectorNumElements(); 2775 MVT EltVT = (VT.getVectorElementType() == MVT::f32) ? MVT::i32 : MVT::i64; 2776 return DAG.getNode(ISD::BIT_CONVERT, VT, 2777 DAG.getConstant(0, MVT::getVectorVT(EltVT, NumElts))); 2778 } 2779 2780 assert(!VT.isVector() && "Can't handle vector type here!"); 2781 unsigned NumBits = VT.getSizeInBits(); 2782 unsigned MSB = NumBits / 8; 2783 uint64_t Val = 0; 2784 if (TLI.isLittleEndian()) 2785 Offset = Offset + MSB - 1; 2786 for (unsigned i = 0; i != MSB; ++i) { 2787 Val = (Val << 8) | (unsigned char)Str[Offset]; 2788 Offset += TLI.isLittleEndian() ? -1 : 1; 2789 } 2790 return DAG.getConstant(Val, VT); 2791} 2792 2793/// getMemBasePlusOffset - Returns base and offset node for the 2794/// 2795static SDValue getMemBasePlusOffset(SDValue Base, unsigned Offset, 2796 SelectionDAG &DAG) { 2797 MVT VT = Base.getValueType(); 2798 return DAG.getNode(ISD::ADD, VT, Base, DAG.getConstant(Offset, VT)); 2799} 2800 2801/// isMemSrcFromString - Returns true if memcpy source is a string constant. 2802/// 2803static bool isMemSrcFromString(SDValue Src, std::string &Str) { 2804 unsigned SrcDelta = 0; 2805 GlobalAddressSDNode *G = NULL; 2806 if (Src.getOpcode() == ISD::GlobalAddress) 2807 G = cast<GlobalAddressSDNode>(Src); 2808 else if (Src.getOpcode() == ISD::ADD && 2809 Src.getOperand(0).getOpcode() == ISD::GlobalAddress && 2810 Src.getOperand(1).getOpcode() == ISD::Constant) { 2811 G = cast<GlobalAddressSDNode>(Src.getOperand(0)); 2812 SrcDelta = cast<ConstantSDNode>(Src.getOperand(1))->getZExtValue(); 2813 } 2814 if (!G) 2815 return false; 2816 2817 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal()); 2818 if (GV && GetConstantStringInfo(GV, Str, SrcDelta, false)) 2819 return true; 2820 2821 return false; 2822} 2823 2824/// MeetsMaxMemopRequirement - Determines if the number of memory ops required 2825/// to replace the memset / memcpy is below the threshold. It also returns the 2826/// types of the sequence of memory ops to perform memset / memcpy. 2827static 2828bool MeetsMaxMemopRequirement(std::vector<MVT> &MemOps, 2829 SDValue Dst, SDValue Src, 2830 unsigned Limit, uint64_t Size, unsigned &Align, 2831 std::string &Str, bool &isSrcStr, 2832 SelectionDAG &DAG, 2833 const TargetLowering &TLI) { 2834 isSrcStr = isMemSrcFromString(Src, Str); 2835 bool isSrcConst = isa<ConstantSDNode>(Src); 2836 bool AllowUnalign = TLI.allowsUnalignedMemoryAccesses(); 2837 MVT VT= TLI.getOptimalMemOpType(Size, Align, isSrcConst, isSrcStr); 2838 if (VT != MVT::iAny) { 2839 unsigned NewAlign = (unsigned) 2840 TLI.getTargetData()->getABITypeAlignment(VT.getTypeForMVT()); 2841 // If source is a string constant, this will require an unaligned load. 2842 if (NewAlign > Align && (isSrcConst || AllowUnalign)) { 2843 if (Dst.getOpcode() != ISD::FrameIndex) { 2844 // Can't change destination alignment. It requires a unaligned store. 2845 if (AllowUnalign) 2846 VT = MVT::iAny; 2847 } else { 2848 int FI = cast<FrameIndexSDNode>(Dst)->getIndex(); 2849 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 2850 if (MFI->isFixedObjectIndex(FI)) { 2851 // Can't change destination alignment. It requires a unaligned store. 2852 if (AllowUnalign) 2853 VT = MVT::iAny; 2854 } else { 2855 // Give the stack frame object a larger alignment if needed. 2856 if (MFI->getObjectAlignment(FI) < NewAlign) 2857 MFI->setObjectAlignment(FI, NewAlign); 2858 Align = NewAlign; 2859 } 2860 } 2861 } 2862 } 2863 2864 if (VT == MVT::iAny) { 2865 if (AllowUnalign) { 2866 VT = MVT::i64; 2867 } else { 2868 switch (Align & 7) { 2869 case 0: VT = MVT::i64; break; 2870 case 4: VT = MVT::i32; break; 2871 case 2: VT = MVT::i16; break; 2872 default: VT = MVT::i8; break; 2873 } 2874 } 2875 2876 MVT LVT = MVT::i64; 2877 while (!TLI.isTypeLegal(LVT)) 2878 LVT = (MVT::SimpleValueType)(LVT.getSimpleVT() - 1); 2879 assert(LVT.isInteger()); 2880 2881 if (VT.bitsGT(LVT)) 2882 VT = LVT; 2883 } 2884 2885 unsigned NumMemOps = 0; 2886 while (Size != 0) { 2887 unsigned VTSize = VT.getSizeInBits() / 8; 2888 while (VTSize > Size) { 2889 // For now, only use non-vector load / store's for the left-over pieces. 2890 if (VT.isVector()) { 2891 VT = MVT::i64; 2892 while (!TLI.isTypeLegal(VT)) 2893 VT = (MVT::SimpleValueType)(VT.getSimpleVT() - 1); 2894 VTSize = VT.getSizeInBits() / 8; 2895 } else { 2896 VT = (MVT::SimpleValueType)(VT.getSimpleVT() - 1); 2897 VTSize >>= 1; 2898 } 2899 } 2900 2901 if (++NumMemOps > Limit) 2902 return false; 2903 MemOps.push_back(VT); 2904 Size -= VTSize; 2905 } 2906 2907 return true; 2908} 2909 2910static SDValue getMemcpyLoadsAndStores(SelectionDAG &DAG, 2911 SDValue Chain, SDValue Dst, 2912 SDValue Src, uint64_t Size, 2913 unsigned Align, bool AlwaysInline, 2914 const Value *DstSV, uint64_t DstSVOff, 2915 const Value *SrcSV, uint64_t SrcSVOff){ 2916 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 2917 2918 // Expand memcpy to a series of load and store ops if the size operand falls 2919 // below a certain threshold. 2920 std::vector<MVT> MemOps; 2921 uint64_t Limit = -1ULL; 2922 if (!AlwaysInline) 2923 Limit = TLI.getMaxStoresPerMemcpy(); 2924 unsigned DstAlign = Align; // Destination alignment can change. 2925 std::string Str; 2926 bool CopyFromStr; 2927 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, Limit, Size, DstAlign, 2928 Str, CopyFromStr, DAG, TLI)) 2929 return SDValue(); 2930 2931 2932 bool isZeroStr = CopyFromStr && Str.empty(); 2933 SmallVector<SDValue, 8> OutChains; 2934 unsigned NumMemOps = MemOps.size(); 2935 uint64_t SrcOff = 0, DstOff = 0; 2936 for (unsigned i = 0; i < NumMemOps; i++) { 2937 MVT VT = MemOps[i]; 2938 unsigned VTSize = VT.getSizeInBits() / 8; 2939 SDValue Value, Store; 2940 2941 if (CopyFromStr && (isZeroStr || !VT.isVector())) { 2942 // It's unlikely a store of a vector immediate can be done in a single 2943 // instruction. It would require a load from a constantpool first. 2944 // We also handle store a vector with all zero's. 2945 // FIXME: Handle other cases where store of vector immediate is done in 2946 // a single instruction. 2947 Value = getMemsetStringVal(VT, DAG, TLI, Str, SrcOff); 2948 Store = DAG.getStore(Chain, Value, 2949 getMemBasePlusOffset(Dst, DstOff, DAG), 2950 DstSV, DstSVOff + DstOff, false, DstAlign); 2951 } else { 2952 Value = DAG.getLoad(VT, Chain, 2953 getMemBasePlusOffset(Src, SrcOff, DAG), 2954 SrcSV, SrcSVOff + SrcOff, false, Align); 2955 Store = DAG.getStore(Chain, Value, 2956 getMemBasePlusOffset(Dst, DstOff, DAG), 2957 DstSV, DstSVOff + DstOff, false, DstAlign); 2958 } 2959 OutChains.push_back(Store); 2960 SrcOff += VTSize; 2961 DstOff += VTSize; 2962 } 2963 2964 return DAG.getNode(ISD::TokenFactor, MVT::Other, 2965 &OutChains[0], OutChains.size()); 2966} 2967 2968static SDValue getMemmoveLoadsAndStores(SelectionDAG &DAG, 2969 SDValue Chain, SDValue Dst, 2970 SDValue Src, uint64_t Size, 2971 unsigned Align, bool AlwaysInline, 2972 const Value *DstSV, uint64_t DstSVOff, 2973 const Value *SrcSV, uint64_t SrcSVOff){ 2974 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 2975 2976 // Expand memmove to a series of load and store ops if the size operand falls 2977 // below a certain threshold. 2978 std::vector<MVT> MemOps; 2979 uint64_t Limit = -1ULL; 2980 if (!AlwaysInline) 2981 Limit = TLI.getMaxStoresPerMemmove(); 2982 unsigned DstAlign = Align; // Destination alignment can change. 2983 std::string Str; 2984 bool CopyFromStr; 2985 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, Limit, Size, DstAlign, 2986 Str, CopyFromStr, DAG, TLI)) 2987 return SDValue(); 2988 2989 uint64_t SrcOff = 0, DstOff = 0; 2990 2991 SmallVector<SDValue, 8> LoadValues; 2992 SmallVector<SDValue, 8> LoadChains; 2993 SmallVector<SDValue, 8> OutChains; 2994 unsigned NumMemOps = MemOps.size(); 2995 for (unsigned i = 0; i < NumMemOps; i++) { 2996 MVT VT = MemOps[i]; 2997 unsigned VTSize = VT.getSizeInBits() / 8; 2998 SDValue Value, Store; 2999 3000 Value = DAG.getLoad(VT, Chain, 3001 getMemBasePlusOffset(Src, SrcOff, DAG), 3002 SrcSV, SrcSVOff + SrcOff, false, Align); 3003 LoadValues.push_back(Value); 3004 LoadChains.push_back(Value.getValue(1)); 3005 SrcOff += VTSize; 3006 } 3007 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 3008 &LoadChains[0], LoadChains.size()); 3009 OutChains.clear(); 3010 for (unsigned i = 0; i < NumMemOps; i++) { 3011 MVT VT = MemOps[i]; 3012 unsigned VTSize = VT.getSizeInBits() / 8; 3013 SDValue Value, Store; 3014 3015 Store = DAG.getStore(Chain, LoadValues[i], 3016 getMemBasePlusOffset(Dst, DstOff, DAG), 3017 DstSV, DstSVOff + DstOff, false, DstAlign); 3018 OutChains.push_back(Store); 3019 DstOff += VTSize; 3020 } 3021 3022 return DAG.getNode(ISD::TokenFactor, MVT::Other, 3023 &OutChains[0], OutChains.size()); 3024} 3025 3026static SDValue getMemsetStores(SelectionDAG &DAG, 3027 SDValue Chain, SDValue Dst, 3028 SDValue Src, uint64_t Size, 3029 unsigned Align, 3030 const Value *DstSV, uint64_t DstSVOff) { 3031 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 3032 3033 // Expand memset to a series of load/store ops if the size operand 3034 // falls below a certain threshold. 3035 std::vector<MVT> MemOps; 3036 std::string Str; 3037 bool CopyFromStr; 3038 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, TLI.getMaxStoresPerMemset(), 3039 Size, Align, Str, CopyFromStr, DAG, TLI)) 3040 return SDValue(); 3041 3042 SmallVector<SDValue, 8> OutChains; 3043 uint64_t DstOff = 0; 3044 3045 unsigned NumMemOps = MemOps.size(); 3046 for (unsigned i = 0; i < NumMemOps; i++) { 3047 MVT VT = MemOps[i]; 3048 unsigned VTSize = VT.getSizeInBits() / 8; 3049 SDValue Value = getMemsetValue(Src, VT, DAG); 3050 SDValue Store = DAG.getStore(Chain, Value, 3051 getMemBasePlusOffset(Dst, DstOff, DAG), 3052 DstSV, DstSVOff + DstOff); 3053 OutChains.push_back(Store); 3054 DstOff += VTSize; 3055 } 3056 3057 return DAG.getNode(ISD::TokenFactor, MVT::Other, 3058 &OutChains[0], OutChains.size()); 3059} 3060 3061SDValue SelectionDAG::getMemcpy(SDValue Chain, SDValue Dst, 3062 SDValue Src, SDValue Size, 3063 unsigned Align, bool AlwaysInline, 3064 const Value *DstSV, uint64_t DstSVOff, 3065 const Value *SrcSV, uint64_t SrcSVOff) { 3066 3067 // Check to see if we should lower the memcpy to loads and stores first. 3068 // For cases within the target-specified limits, this is the best choice. 3069 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 3070 if (ConstantSize) { 3071 // Memcpy with size zero? Just return the original chain. 3072 if (ConstantSize->isNullValue()) 3073 return Chain; 3074 3075 SDValue Result = 3076 getMemcpyLoadsAndStores(*this, Chain, Dst, Src, 3077 ConstantSize->getZExtValue(), 3078 Align, false, DstSV, DstSVOff, SrcSV, SrcSVOff); 3079 if (Result.getNode()) 3080 return Result; 3081 } 3082 3083 // Then check to see if we should lower the memcpy with target-specific 3084 // code. If the target chooses to do this, this is the next best. 3085 SDValue Result = 3086 TLI.EmitTargetCodeForMemcpy(*this, Chain, Dst, Src, Size, Align, 3087 AlwaysInline, 3088 DstSV, DstSVOff, SrcSV, SrcSVOff); 3089 if (Result.getNode()) 3090 return Result; 3091 3092 // If we really need inline code and the target declined to provide it, 3093 // use a (potentially long) sequence of loads and stores. 3094 if (AlwaysInline) { 3095 assert(ConstantSize && "AlwaysInline requires a constant size!"); 3096 return getMemcpyLoadsAndStores(*this, Chain, Dst, Src, 3097 ConstantSize->getZExtValue(), Align, true, 3098 DstSV, DstSVOff, SrcSV, SrcSVOff); 3099 } 3100 3101 // Emit a library call. 3102 TargetLowering::ArgListTy Args; 3103 TargetLowering::ArgListEntry Entry; 3104 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 3105 Entry.Node = Dst; Args.push_back(Entry); 3106 Entry.Node = Src; Args.push_back(Entry); 3107 Entry.Node = Size; Args.push_back(Entry); 3108 std::pair<SDValue,SDValue> CallResult = 3109 TLI.LowerCallTo(Chain, Type::VoidTy, 3110 false, false, false, false, CallingConv::C, false, 3111 getExternalSymbol("memcpy", TLI.getPointerTy()), 3112 Args, *this); 3113 return CallResult.second; 3114} 3115 3116SDValue SelectionDAG::getMemmove(SDValue Chain, SDValue Dst, 3117 SDValue Src, SDValue Size, 3118 unsigned Align, 3119 const Value *DstSV, uint64_t DstSVOff, 3120 const Value *SrcSV, uint64_t SrcSVOff) { 3121 3122 // Check to see if we should lower the memmove to loads and stores first. 3123 // For cases within the target-specified limits, this is the best choice. 3124 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 3125 if (ConstantSize) { 3126 // Memmove with size zero? Just return the original chain. 3127 if (ConstantSize->isNullValue()) 3128 return Chain; 3129 3130 SDValue Result = 3131 getMemmoveLoadsAndStores(*this, Chain, Dst, Src, 3132 ConstantSize->getZExtValue(), 3133 Align, false, DstSV, DstSVOff, SrcSV, SrcSVOff); 3134 if (Result.getNode()) 3135 return Result; 3136 } 3137 3138 // Then check to see if we should lower the memmove with target-specific 3139 // code. If the target chooses to do this, this is the next best. 3140 SDValue Result = 3141 TLI.EmitTargetCodeForMemmove(*this, Chain, Dst, Src, Size, Align, 3142 DstSV, DstSVOff, SrcSV, SrcSVOff); 3143 if (Result.getNode()) 3144 return Result; 3145 3146 // Emit a library call. 3147 TargetLowering::ArgListTy Args; 3148 TargetLowering::ArgListEntry Entry; 3149 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 3150 Entry.Node = Dst; Args.push_back(Entry); 3151 Entry.Node = Src; Args.push_back(Entry); 3152 Entry.Node = Size; Args.push_back(Entry); 3153 std::pair<SDValue,SDValue> CallResult = 3154 TLI.LowerCallTo(Chain, Type::VoidTy, 3155 false, false, false, false, CallingConv::C, false, 3156 getExternalSymbol("memmove", TLI.getPointerTy()), 3157 Args, *this); 3158 return CallResult.second; 3159} 3160 3161SDValue SelectionDAG::getMemset(SDValue Chain, SDValue Dst, 3162 SDValue Src, SDValue Size, 3163 unsigned Align, 3164 const Value *DstSV, uint64_t DstSVOff) { 3165 3166 // Check to see if we should lower the memset to stores first. 3167 // For cases within the target-specified limits, this is the best choice. 3168 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 3169 if (ConstantSize) { 3170 // Memset with size zero? Just return the original chain. 3171 if (ConstantSize->isNullValue()) 3172 return Chain; 3173 3174 SDValue Result = 3175 getMemsetStores(*this, Chain, Dst, Src, ConstantSize->getZExtValue(), 3176 Align, DstSV, DstSVOff); 3177 if (Result.getNode()) 3178 return Result; 3179 } 3180 3181 // Then check to see if we should lower the memset with target-specific 3182 // code. If the target chooses to do this, this is the next best. 3183 SDValue Result = 3184 TLI.EmitTargetCodeForMemset(*this, Chain, Dst, Src, Size, Align, 3185 DstSV, DstSVOff); 3186 if (Result.getNode()) 3187 return Result; 3188 3189 // Emit a library call. 3190 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType(); 3191 TargetLowering::ArgListTy Args; 3192 TargetLowering::ArgListEntry Entry; 3193 Entry.Node = Dst; Entry.Ty = IntPtrTy; 3194 Args.push_back(Entry); 3195 // Extend or truncate the argument to be an i32 value for the call. 3196 if (Src.getValueType().bitsGT(MVT::i32)) 3197 Src = getNode(ISD::TRUNCATE, MVT::i32, Src); 3198 else 3199 Src = getNode(ISD::ZERO_EXTEND, MVT::i32, Src); 3200 Entry.Node = Src; Entry.Ty = Type::Int32Ty; Entry.isSExt = true; 3201 Args.push_back(Entry); 3202 Entry.Node = Size; Entry.Ty = IntPtrTy; Entry.isSExt = false; 3203 Args.push_back(Entry); 3204 std::pair<SDValue,SDValue> CallResult = 3205 TLI.LowerCallTo(Chain, Type::VoidTy, 3206 false, false, false, false, CallingConv::C, false, 3207 getExternalSymbol("memset", TLI.getPointerTy()), 3208 Args, *this); 3209 return CallResult.second; 3210} 3211 3212SDValue SelectionDAG::getAtomic(unsigned Opcode, SDValue Chain, 3213 SDValue Ptr, SDValue Cmp, 3214 SDValue Swp, const Value* PtrVal, 3215 unsigned Alignment) { 3216 assert((Opcode == ISD::ATOMIC_CMP_SWAP_8 || 3217 Opcode == ISD::ATOMIC_CMP_SWAP_16 || 3218 Opcode == ISD::ATOMIC_CMP_SWAP_32 || 3219 Opcode == ISD::ATOMIC_CMP_SWAP_64) && "Invalid Atomic Op"); 3220 assert(Cmp.getValueType() == Swp.getValueType() && "Invalid Atomic Op Types"); 3221 3222 MVT VT = Cmp.getValueType(); 3223 3224 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3225 Alignment = getMVTAlignment(VT); 3226 3227 SDVTList VTs = getVTList(VT, MVT::Other); 3228 FoldingSetNodeID ID; 3229 SDValue Ops[] = {Chain, Ptr, Cmp, Swp}; 3230 AddNodeIDNode(ID, Opcode, VTs, Ops, 4); 3231 void* IP = 0; 3232 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3233 return SDValue(E, 0); 3234 SDNode* N = NodeAllocator.Allocate<AtomicSDNode>(); 3235 new (N) AtomicSDNode(Opcode, VTs, Chain, Ptr, Cmp, Swp, PtrVal, Alignment); 3236 CSEMap.InsertNode(N, IP); 3237 AllNodes.push_back(N); 3238 return SDValue(N, 0); 3239} 3240 3241SDValue SelectionDAG::getAtomic(unsigned Opcode, SDValue Chain, 3242 SDValue Ptr, SDValue Val, 3243 const Value* PtrVal, 3244 unsigned Alignment) { 3245 assert((Opcode == ISD::ATOMIC_LOAD_ADD_8 || 3246 Opcode == ISD::ATOMIC_LOAD_SUB_8 || 3247 Opcode == ISD::ATOMIC_LOAD_AND_8 || 3248 Opcode == ISD::ATOMIC_LOAD_OR_8 || 3249 Opcode == ISD::ATOMIC_LOAD_XOR_8 || 3250 Opcode == ISD::ATOMIC_LOAD_NAND_8 || 3251 Opcode == ISD::ATOMIC_LOAD_MIN_8 || 3252 Opcode == ISD::ATOMIC_LOAD_MAX_8 || 3253 Opcode == ISD::ATOMIC_LOAD_UMIN_8 || 3254 Opcode == ISD::ATOMIC_LOAD_UMAX_8 || 3255 Opcode == ISD::ATOMIC_SWAP_8 || 3256 Opcode == ISD::ATOMIC_LOAD_ADD_16 || 3257 Opcode == ISD::ATOMIC_LOAD_SUB_16 || 3258 Opcode == ISD::ATOMIC_LOAD_AND_16 || 3259 Opcode == ISD::ATOMIC_LOAD_OR_16 || 3260 Opcode == ISD::ATOMIC_LOAD_XOR_16 || 3261 Opcode == ISD::ATOMIC_LOAD_NAND_16 || 3262 Opcode == ISD::ATOMIC_LOAD_MIN_16 || 3263 Opcode == ISD::ATOMIC_LOAD_MAX_16 || 3264 Opcode == ISD::ATOMIC_LOAD_UMIN_16 || 3265 Opcode == ISD::ATOMIC_LOAD_UMAX_16 || 3266 Opcode == ISD::ATOMIC_SWAP_16 || 3267 Opcode == ISD::ATOMIC_LOAD_ADD_32 || 3268 Opcode == ISD::ATOMIC_LOAD_SUB_32 || 3269 Opcode == ISD::ATOMIC_LOAD_AND_32 || 3270 Opcode == ISD::ATOMIC_LOAD_OR_32 || 3271 Opcode == ISD::ATOMIC_LOAD_XOR_32 || 3272 Opcode == ISD::ATOMIC_LOAD_NAND_32 || 3273 Opcode == ISD::ATOMIC_LOAD_MIN_32 || 3274 Opcode == ISD::ATOMIC_LOAD_MAX_32 || 3275 Opcode == ISD::ATOMIC_LOAD_UMIN_32 || 3276 Opcode == ISD::ATOMIC_LOAD_UMAX_32 || 3277 Opcode == ISD::ATOMIC_SWAP_32 || 3278 Opcode == ISD::ATOMIC_LOAD_ADD_64 || 3279 Opcode == ISD::ATOMIC_LOAD_SUB_64 || 3280 Opcode == ISD::ATOMIC_LOAD_AND_64 || 3281 Opcode == ISD::ATOMIC_LOAD_OR_64 || 3282 Opcode == ISD::ATOMIC_LOAD_XOR_64 || 3283 Opcode == ISD::ATOMIC_LOAD_NAND_64 || 3284 Opcode == ISD::ATOMIC_LOAD_MIN_64 || 3285 Opcode == ISD::ATOMIC_LOAD_MAX_64 || 3286 Opcode == ISD::ATOMIC_LOAD_UMIN_64 || 3287 Opcode == ISD::ATOMIC_LOAD_UMAX_64 || 3288 Opcode == ISD::ATOMIC_SWAP_64) && "Invalid Atomic Op"); 3289 3290 MVT VT = Val.getValueType(); 3291 3292 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3293 Alignment = getMVTAlignment(VT); 3294 3295 SDVTList VTs = getVTList(VT, MVT::Other); 3296 FoldingSetNodeID ID; 3297 SDValue Ops[] = {Chain, Ptr, Val}; 3298 AddNodeIDNode(ID, Opcode, VTs, Ops, 3); 3299 void* IP = 0; 3300 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3301 return SDValue(E, 0); 3302 SDNode* N = NodeAllocator.Allocate<AtomicSDNode>(); 3303 new (N) AtomicSDNode(Opcode, VTs, Chain, Ptr, Val, PtrVal, Alignment); 3304 CSEMap.InsertNode(N, IP); 3305 AllNodes.push_back(N); 3306 return SDValue(N, 0); 3307} 3308 3309/// getMergeValues - Create a MERGE_VALUES node from the given operands. 3310/// Allowed to return something different (and simpler) if Simplify is true. 3311SDValue SelectionDAG::getMergeValues(const SDValue *Ops, unsigned NumOps, 3312 bool Simplify) { 3313 if (Simplify && NumOps == 1) 3314 return Ops[0]; 3315 3316 SmallVector<MVT, 4> VTs; 3317 VTs.reserve(NumOps); 3318 for (unsigned i = 0; i < NumOps; ++i) 3319 VTs.push_back(Ops[i].getValueType()); 3320 return getNode(ISD::MERGE_VALUES, getVTList(&VTs[0], NumOps), Ops, NumOps); 3321} 3322 3323SDValue 3324SelectionDAG::getMemIntrinsicNode(unsigned Opcode, 3325 const MVT *VTs, unsigned NumVTs, 3326 const SDValue *Ops, unsigned NumOps, 3327 MVT MemVT, const Value *srcValue, int SVOff, 3328 unsigned Align, bool Vol, 3329 bool ReadMem, bool WriteMem) { 3330 return getMemIntrinsicNode(Opcode, makeVTList(VTs, NumVTs), Ops, NumOps, 3331 MemVT, srcValue, SVOff, Align, Vol, 3332 ReadMem, WriteMem); 3333} 3334 3335SDValue 3336SelectionDAG::getMemIntrinsicNode(unsigned Opcode, SDVTList VTList, 3337 const SDValue *Ops, unsigned NumOps, 3338 MVT MemVT, const Value *srcValue, int SVOff, 3339 unsigned Align, bool Vol, 3340 bool ReadMem, bool WriteMem) { 3341 // Memoize the node unless it returns a flag. 3342 MemIntrinsicSDNode *N; 3343 if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) { 3344 FoldingSetNodeID ID; 3345 AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps); 3346 void *IP = 0; 3347 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3348 return SDValue(E, 0); 3349 3350 N = NodeAllocator.Allocate<MemIntrinsicSDNode>(); 3351 new (N) MemIntrinsicSDNode(Opcode, VTList, Ops, NumOps, MemVT, 3352 srcValue, SVOff, Align, Vol, ReadMem, WriteMem); 3353 CSEMap.InsertNode(N, IP); 3354 } else { 3355 N = NodeAllocator.Allocate<MemIntrinsicSDNode>(); 3356 new (N) MemIntrinsicSDNode(Opcode, VTList, Ops, NumOps, MemVT, 3357 srcValue, SVOff, Align, Vol, ReadMem, WriteMem); 3358 } 3359 AllNodes.push_back(N); 3360 return SDValue(N, 0); 3361} 3362 3363SDValue 3364SelectionDAG::getCall(unsigned CallingConv, bool IsVarArgs, bool IsTailCall, 3365 bool IsInreg, SDVTList VTs, 3366 const SDValue *Operands, unsigned NumOperands) { 3367 // Do not include isTailCall in the folding set profile. 3368 FoldingSetNodeID ID; 3369 AddNodeIDNode(ID, ISD::CALL, VTs, Operands, NumOperands); 3370 ID.AddInteger(CallingConv); 3371 ID.AddInteger(IsVarArgs); 3372 void *IP = 0; 3373 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) { 3374 // Instead of including isTailCall in the folding set, we just 3375 // set the flag of the existing node. 3376 if (!IsTailCall) 3377 cast<CallSDNode>(E)->setNotTailCall(); 3378 return SDValue(E, 0); 3379 } 3380 SDNode *N = NodeAllocator.Allocate<CallSDNode>(); 3381 new (N) CallSDNode(CallingConv, IsVarArgs, IsTailCall, IsInreg, 3382 VTs, Operands, NumOperands); 3383 CSEMap.InsertNode(N, IP); 3384 AllNodes.push_back(N); 3385 return SDValue(N, 0); 3386} 3387 3388SDValue 3389SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, 3390 MVT VT, SDValue Chain, 3391 SDValue Ptr, SDValue Offset, 3392 const Value *SV, int SVOffset, MVT EVT, 3393 bool isVolatile, unsigned Alignment) { 3394 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3395 Alignment = getMVTAlignment(VT); 3396 3397 if (VT == EVT) { 3398 ExtType = ISD::NON_EXTLOAD; 3399 } else if (ExtType == ISD::NON_EXTLOAD) { 3400 assert(VT == EVT && "Non-extending load from different memory type!"); 3401 } else { 3402 // Extending load. 3403 if (VT.isVector()) 3404 assert(EVT.getVectorNumElements() == VT.getVectorNumElements() && 3405 "Invalid vector extload!"); 3406 else 3407 assert(EVT.bitsLT(VT) && 3408 "Should only be an extending load, not truncating!"); 3409 assert((ExtType == ISD::EXTLOAD || VT.isInteger()) && 3410 "Cannot sign/zero extend a FP/Vector load!"); 3411 assert(VT.isInteger() == EVT.isInteger() && 3412 "Cannot convert from FP to Int or Int -> FP!"); 3413 } 3414 3415 bool Indexed = AM != ISD::UNINDEXED; 3416 assert((Indexed || Offset.getOpcode() == ISD::UNDEF) && 3417 "Unindexed load with an offset!"); 3418 3419 SDVTList VTs = Indexed ? 3420 getVTList(VT, Ptr.getValueType(), MVT::Other) : getVTList(VT, MVT::Other); 3421 SDValue Ops[] = { Chain, Ptr, Offset }; 3422 FoldingSetNodeID ID; 3423 AddNodeIDNode(ID, ISD::LOAD, VTs, Ops, 3); 3424 ID.AddInteger(AM); 3425 ID.AddInteger(ExtType); 3426 ID.AddInteger(EVT.getRawBits()); 3427 ID.AddInteger(encodeMemSDNodeFlags(isVolatile, Alignment)); 3428 void *IP = 0; 3429 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3430 return SDValue(E, 0); 3431 SDNode *N = NodeAllocator.Allocate<LoadSDNode>(); 3432 new (N) LoadSDNode(Ops, VTs, AM, ExtType, EVT, SV, SVOffset, 3433 Alignment, isVolatile); 3434 CSEMap.InsertNode(N, IP); 3435 AllNodes.push_back(N); 3436 return SDValue(N, 0); 3437} 3438 3439SDValue SelectionDAG::getLoad(MVT VT, 3440 SDValue Chain, SDValue Ptr, 3441 const Value *SV, int SVOffset, 3442 bool isVolatile, unsigned Alignment) { 3443 SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType()); 3444 return getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD, VT, Chain, Ptr, Undef, 3445 SV, SVOffset, VT, isVolatile, Alignment); 3446} 3447 3448SDValue SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, MVT VT, 3449 SDValue Chain, SDValue Ptr, 3450 const Value *SV, 3451 int SVOffset, MVT EVT, 3452 bool isVolatile, unsigned Alignment) { 3453 SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType()); 3454 return getLoad(ISD::UNINDEXED, ExtType, VT, Chain, Ptr, Undef, 3455 SV, SVOffset, EVT, isVolatile, Alignment); 3456} 3457 3458SDValue 3459SelectionDAG::getIndexedLoad(SDValue OrigLoad, SDValue Base, 3460 SDValue Offset, ISD::MemIndexedMode AM) { 3461 LoadSDNode *LD = cast<LoadSDNode>(OrigLoad); 3462 assert(LD->getOffset().getOpcode() == ISD::UNDEF && 3463 "Load is already a indexed load!"); 3464 return getLoad(AM, LD->getExtensionType(), OrigLoad.getValueType(), 3465 LD->getChain(), Base, Offset, LD->getSrcValue(), 3466 LD->getSrcValueOffset(), LD->getMemoryVT(), 3467 LD->isVolatile(), LD->getAlignment()); 3468} 3469 3470SDValue SelectionDAG::getStore(SDValue Chain, SDValue Val, 3471 SDValue Ptr, const Value *SV, int SVOffset, 3472 bool isVolatile, unsigned Alignment) { 3473 MVT VT = Val.getValueType(); 3474 3475 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3476 Alignment = getMVTAlignment(VT); 3477 3478 SDVTList VTs = getVTList(MVT::Other); 3479 SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType()); 3480 SDValue Ops[] = { Chain, Val, Ptr, Undef }; 3481 FoldingSetNodeID ID; 3482 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); 3483 ID.AddInteger(ISD::UNINDEXED); 3484 ID.AddInteger(false); 3485 ID.AddInteger(VT.getRawBits()); 3486 ID.AddInteger(encodeMemSDNodeFlags(isVolatile, Alignment)); 3487 void *IP = 0; 3488 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3489 return SDValue(E, 0); 3490 SDNode *N = NodeAllocator.Allocate<StoreSDNode>(); 3491 new (N) StoreSDNode(Ops, VTs, ISD::UNINDEXED, false, 3492 VT, SV, SVOffset, Alignment, isVolatile); 3493 CSEMap.InsertNode(N, IP); 3494 AllNodes.push_back(N); 3495 return SDValue(N, 0); 3496} 3497 3498SDValue SelectionDAG::getTruncStore(SDValue Chain, SDValue Val, 3499 SDValue Ptr, const Value *SV, 3500 int SVOffset, MVT SVT, 3501 bool isVolatile, unsigned Alignment) { 3502 MVT VT = Val.getValueType(); 3503 3504 if (VT == SVT) 3505 return getStore(Chain, Val, Ptr, SV, SVOffset, isVolatile, Alignment); 3506 3507 assert(VT.bitsGT(SVT) && "Not a truncation?"); 3508 assert(VT.isInteger() == SVT.isInteger() && 3509 "Can't do FP-INT conversion!"); 3510 3511 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3512 Alignment = getMVTAlignment(VT); 3513 3514 SDVTList VTs = getVTList(MVT::Other); 3515 SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType()); 3516 SDValue Ops[] = { Chain, Val, Ptr, Undef }; 3517 FoldingSetNodeID ID; 3518 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); 3519 ID.AddInteger(ISD::UNINDEXED); 3520 ID.AddInteger(1); 3521 ID.AddInteger(SVT.getRawBits()); 3522 ID.AddInteger(encodeMemSDNodeFlags(isVolatile, Alignment)); 3523 void *IP = 0; 3524 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3525 return SDValue(E, 0); 3526 SDNode *N = NodeAllocator.Allocate<StoreSDNode>(); 3527 new (N) StoreSDNode(Ops, VTs, ISD::UNINDEXED, true, 3528 SVT, SV, SVOffset, Alignment, isVolatile); 3529 CSEMap.InsertNode(N, IP); 3530 AllNodes.push_back(N); 3531 return SDValue(N, 0); 3532} 3533 3534SDValue 3535SelectionDAG::getIndexedStore(SDValue OrigStore, SDValue Base, 3536 SDValue Offset, ISD::MemIndexedMode AM) { 3537 StoreSDNode *ST = cast<StoreSDNode>(OrigStore); 3538 assert(ST->getOffset().getOpcode() == ISD::UNDEF && 3539 "Store is already a indexed store!"); 3540 SDVTList VTs = getVTList(Base.getValueType(), MVT::Other); 3541 SDValue Ops[] = { ST->getChain(), ST->getValue(), Base, Offset }; 3542 FoldingSetNodeID ID; 3543 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); 3544 ID.AddInteger(AM); 3545 ID.AddInteger(ST->isTruncatingStore()); 3546 ID.AddInteger(ST->getMemoryVT().getRawBits()); 3547 ID.AddInteger(ST->getRawFlags()); 3548 void *IP = 0; 3549 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3550 return SDValue(E, 0); 3551 SDNode *N = NodeAllocator.Allocate<StoreSDNode>(); 3552 new (N) StoreSDNode(Ops, VTs, AM, 3553 ST->isTruncatingStore(), ST->getMemoryVT(), 3554 ST->getSrcValue(), ST->getSrcValueOffset(), 3555 ST->getAlignment(), ST->isVolatile()); 3556 CSEMap.InsertNode(N, IP); 3557 AllNodes.push_back(N); 3558 return SDValue(N, 0); 3559} 3560 3561SDValue SelectionDAG::getVAArg(MVT VT, 3562 SDValue Chain, SDValue Ptr, 3563 SDValue SV) { 3564 SDValue Ops[] = { Chain, Ptr, SV }; 3565 return getNode(ISD::VAARG, getVTList(VT, MVT::Other), Ops, 3); 3566} 3567 3568SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, 3569 const SDUse *Ops, unsigned NumOps) { 3570 switch (NumOps) { 3571 case 0: return getNode(Opcode, VT); 3572 case 1: return getNode(Opcode, VT, Ops[0]); 3573 case 2: return getNode(Opcode, VT, Ops[0], Ops[1]); 3574 case 3: return getNode(Opcode, VT, Ops[0], Ops[1], Ops[2]); 3575 default: break; 3576 } 3577 3578 // Copy from an SDUse array into an SDValue array for use with 3579 // the regular getNode logic. 3580 SmallVector<SDValue, 8> NewOps(Ops, Ops + NumOps); 3581 return getNode(Opcode, VT, &NewOps[0], NumOps); 3582} 3583 3584SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, 3585 const SDValue *Ops, unsigned NumOps) { 3586 switch (NumOps) { 3587 case 0: return getNode(Opcode, VT); 3588 case 1: return getNode(Opcode, VT, Ops[0]); 3589 case 2: return getNode(Opcode, VT, Ops[0], Ops[1]); 3590 case 3: return getNode(Opcode, VT, Ops[0], Ops[1], Ops[2]); 3591 default: break; 3592 } 3593 3594 switch (Opcode) { 3595 default: break; 3596 case ISD::SELECT_CC: { 3597 assert(NumOps == 5 && "SELECT_CC takes 5 operands!"); 3598 assert(Ops[0].getValueType() == Ops[1].getValueType() && 3599 "LHS and RHS of condition must have same type!"); 3600 assert(Ops[2].getValueType() == Ops[3].getValueType() && 3601 "True and False arms of SelectCC must have same type!"); 3602 assert(Ops[2].getValueType() == VT && 3603 "select_cc node must be of same type as true and false value!"); 3604 break; 3605 } 3606 case ISD::BR_CC: { 3607 assert(NumOps == 5 && "BR_CC takes 5 operands!"); 3608 assert(Ops[2].getValueType() == Ops[3].getValueType() && 3609 "LHS/RHS of comparison should match types!"); 3610 break; 3611 } 3612 } 3613 3614 // Memoize nodes. 3615 SDNode *N; 3616 SDVTList VTs = getVTList(VT); 3617 if (VT != MVT::Flag) { 3618 FoldingSetNodeID ID; 3619 AddNodeIDNode(ID, Opcode, VTs, Ops, NumOps); 3620 void *IP = 0; 3621 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3622 return SDValue(E, 0); 3623 N = NodeAllocator.Allocate<SDNode>(); 3624 new (N) SDNode(Opcode, VTs, Ops, NumOps); 3625 CSEMap.InsertNode(N, IP); 3626 } else { 3627 N = NodeAllocator.Allocate<SDNode>(); 3628 new (N) SDNode(Opcode, VTs, Ops, NumOps); 3629 } 3630 AllNodes.push_back(N); 3631#ifndef NDEBUG 3632 VerifyNode(N); 3633#endif 3634 return SDValue(N, 0); 3635} 3636 3637SDValue SelectionDAG::getNode(unsigned Opcode, 3638 const std::vector<MVT> &ResultTys, 3639 const SDValue *Ops, unsigned NumOps) { 3640 return getNode(Opcode, getNodeValueTypes(ResultTys), ResultTys.size(), 3641 Ops, NumOps); 3642} 3643 3644SDValue SelectionDAG::getNode(unsigned Opcode, 3645 const MVT *VTs, unsigned NumVTs, 3646 const SDValue *Ops, unsigned NumOps) { 3647 if (NumVTs == 1) 3648 return getNode(Opcode, VTs[0], Ops, NumOps); 3649 return getNode(Opcode, makeVTList(VTs, NumVTs), Ops, NumOps); 3650} 3651 3652SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, 3653 const SDValue *Ops, unsigned NumOps) { 3654 if (VTList.NumVTs == 1) 3655 return getNode(Opcode, VTList.VTs[0], Ops, NumOps); 3656 3657 switch (Opcode) { 3658 // FIXME: figure out how to safely handle things like 3659 // int foo(int x) { return 1 << (x & 255); } 3660 // int bar() { return foo(256); } 3661#if 0 3662 case ISD::SRA_PARTS: 3663 case ISD::SRL_PARTS: 3664 case ISD::SHL_PARTS: 3665 if (N3.getOpcode() == ISD::SIGN_EXTEND_INREG && 3666 cast<VTSDNode>(N3.getOperand(1))->getVT() != MVT::i1) 3667 return getNode(Opcode, VT, N1, N2, N3.getOperand(0)); 3668 else if (N3.getOpcode() == ISD::AND) 3669 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(N3.getOperand(1))) { 3670 // If the and is only masking out bits that cannot effect the shift, 3671 // eliminate the and. 3672 unsigned NumBits = VT.getSizeInBits()*2; 3673 if ((AndRHS->getValue() & (NumBits-1)) == NumBits-1) 3674 return getNode(Opcode, VT, N1, N2, N3.getOperand(0)); 3675 } 3676 break; 3677#endif 3678 } 3679 3680 // Memoize the node unless it returns a flag. 3681 SDNode *N; 3682 if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) { 3683 FoldingSetNodeID ID; 3684 AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps); 3685 void *IP = 0; 3686 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3687 return SDValue(E, 0); 3688 if (NumOps == 1) { 3689 N = NodeAllocator.Allocate<UnarySDNode>(); 3690 new (N) UnarySDNode(Opcode, VTList, Ops[0]); 3691 } else if (NumOps == 2) { 3692 N = NodeAllocator.Allocate<BinarySDNode>(); 3693 new (N) BinarySDNode(Opcode, VTList, Ops[0], Ops[1]); 3694 } else if (NumOps == 3) { 3695 N = NodeAllocator.Allocate<TernarySDNode>(); 3696 new (N) TernarySDNode(Opcode, VTList, Ops[0], Ops[1], Ops[2]); 3697 } else { 3698 N = NodeAllocator.Allocate<SDNode>(); 3699 new (N) SDNode(Opcode, VTList, Ops, NumOps); 3700 } 3701 CSEMap.InsertNode(N, IP); 3702 } else { 3703 if (NumOps == 1) { 3704 N = NodeAllocator.Allocate<UnarySDNode>(); 3705 new (N) UnarySDNode(Opcode, VTList, Ops[0]); 3706 } else if (NumOps == 2) { 3707 N = NodeAllocator.Allocate<BinarySDNode>(); 3708 new (N) BinarySDNode(Opcode, VTList, Ops[0], Ops[1]); 3709 } else if (NumOps == 3) { 3710 N = NodeAllocator.Allocate<TernarySDNode>(); 3711 new (N) TernarySDNode(Opcode, VTList, Ops[0], Ops[1], Ops[2]); 3712 } else { 3713 N = NodeAllocator.Allocate<SDNode>(); 3714 new (N) SDNode(Opcode, VTList, Ops, NumOps); 3715 } 3716 } 3717 AllNodes.push_back(N); 3718#ifndef NDEBUG 3719 VerifyNode(N); 3720#endif 3721 return SDValue(N, 0); 3722} 3723 3724SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList) { 3725 return getNode(Opcode, VTList, 0, 0); 3726} 3727 3728SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, 3729 SDValue N1) { 3730 SDValue Ops[] = { N1 }; 3731 return getNode(Opcode, VTList, Ops, 1); 3732} 3733 3734SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, 3735 SDValue N1, SDValue N2) { 3736 SDValue Ops[] = { N1, N2 }; 3737 return getNode(Opcode, VTList, Ops, 2); 3738} 3739 3740SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, 3741 SDValue N1, SDValue N2, SDValue N3) { 3742 SDValue Ops[] = { N1, N2, N3 }; 3743 return getNode(Opcode, VTList, Ops, 3); 3744} 3745 3746SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, 3747 SDValue N1, SDValue N2, SDValue N3, 3748 SDValue N4) { 3749 SDValue Ops[] = { N1, N2, N3, N4 }; 3750 return getNode(Opcode, VTList, Ops, 4); 3751} 3752 3753SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, 3754 SDValue N1, SDValue N2, SDValue N3, 3755 SDValue N4, SDValue N5) { 3756 SDValue Ops[] = { N1, N2, N3, N4, N5 }; 3757 return getNode(Opcode, VTList, Ops, 5); 3758} 3759 3760SDVTList SelectionDAG::getVTList(MVT VT) { 3761 return makeVTList(SDNode::getValueTypeList(VT), 1); 3762} 3763 3764SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2) { 3765 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 3766 E = VTList.rend(); I != E; ++I) 3767 if (I->NumVTs == 2 && I->VTs[0] == VT1 && I->VTs[1] == VT2) 3768 return *I; 3769 3770 MVT *Array = Allocator.Allocate<MVT>(2); 3771 Array[0] = VT1; 3772 Array[1] = VT2; 3773 SDVTList Result = makeVTList(Array, 2); 3774 VTList.push_back(Result); 3775 return Result; 3776} 3777 3778SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2, MVT VT3) { 3779 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 3780 E = VTList.rend(); I != E; ++I) 3781 if (I->NumVTs == 3 && I->VTs[0] == VT1 && I->VTs[1] == VT2 && 3782 I->VTs[2] == VT3) 3783 return *I; 3784 3785 MVT *Array = Allocator.Allocate<MVT>(3); 3786 Array[0] = VT1; 3787 Array[1] = VT2; 3788 Array[2] = VT3; 3789 SDVTList Result = makeVTList(Array, 3); 3790 VTList.push_back(Result); 3791 return Result; 3792} 3793 3794SDVTList SelectionDAG::getVTList(const MVT *VTs, unsigned NumVTs) { 3795 switch (NumVTs) { 3796 case 0: assert(0 && "Cannot have nodes without results!"); 3797 case 1: return getVTList(VTs[0]); 3798 case 2: return getVTList(VTs[0], VTs[1]); 3799 case 3: return getVTList(VTs[0], VTs[1], VTs[2]); 3800 default: break; 3801 } 3802 3803 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 3804 E = VTList.rend(); I != E; ++I) { 3805 if (I->NumVTs != NumVTs || VTs[0] != I->VTs[0] || VTs[1] != I->VTs[1]) 3806 continue; 3807 3808 bool NoMatch = false; 3809 for (unsigned i = 2; i != NumVTs; ++i) 3810 if (VTs[i] != I->VTs[i]) { 3811 NoMatch = true; 3812 break; 3813 } 3814 if (!NoMatch) 3815 return *I; 3816 } 3817 3818 MVT *Array = Allocator.Allocate<MVT>(NumVTs); 3819 std::copy(VTs, VTs+NumVTs, Array); 3820 SDVTList Result = makeVTList(Array, NumVTs); 3821 VTList.push_back(Result); 3822 return Result; 3823} 3824 3825 3826/// UpdateNodeOperands - *Mutate* the specified node in-place to have the 3827/// specified operands. If the resultant node already exists in the DAG, 3828/// this does not modify the specified node, instead it returns the node that 3829/// already exists. If the resultant node does not exist in the DAG, the 3830/// input node is returned. As a degenerate case, if you specify the same 3831/// input operands as the node already has, the input node is returned. 3832SDValue SelectionDAG::UpdateNodeOperands(SDValue InN, SDValue Op) { 3833 SDNode *N = InN.getNode(); 3834 assert(N->getNumOperands() == 1 && "Update with wrong number of operands"); 3835 3836 // Check to see if there is no change. 3837 if (Op == N->getOperand(0)) return InN; 3838 3839 // See if the modified node already exists. 3840 void *InsertPos = 0; 3841 if (SDNode *Existing = FindModifiedNodeSlot(N, Op, InsertPos)) 3842 return SDValue(Existing, InN.getResNo()); 3843 3844 // Nope it doesn't. Remove the node from its current place in the maps. 3845 if (InsertPos) 3846 if (!RemoveNodeFromCSEMaps(N)) 3847 InsertPos = 0; 3848 3849 // Now we update the operands. 3850 N->OperandList[0].getVal()->removeUser(0, N); 3851 N->OperandList[0] = Op; 3852 N->OperandList[0].setUser(N); 3853 Op.getNode()->addUser(0, N); 3854 3855 // If this gets put into a CSE map, add it. 3856 if (InsertPos) CSEMap.InsertNode(N, InsertPos); 3857 return InN; 3858} 3859 3860SDValue SelectionDAG:: 3861UpdateNodeOperands(SDValue InN, SDValue Op1, SDValue Op2) { 3862 SDNode *N = InN.getNode(); 3863 assert(N->getNumOperands() == 2 && "Update with wrong number of operands"); 3864 3865 // Check to see if there is no change. 3866 if (Op1 == N->getOperand(0) && Op2 == N->getOperand(1)) 3867 return InN; // No operands changed, just return the input node. 3868 3869 // See if the modified node already exists. 3870 void *InsertPos = 0; 3871 if (SDNode *Existing = FindModifiedNodeSlot(N, Op1, Op2, InsertPos)) 3872 return SDValue(Existing, InN.getResNo()); 3873 3874 // Nope it doesn't. Remove the node from its current place in the maps. 3875 if (InsertPos) 3876 if (!RemoveNodeFromCSEMaps(N)) 3877 InsertPos = 0; 3878 3879 // Now we update the operands. 3880 if (N->OperandList[0] != Op1) { 3881 N->OperandList[0].getVal()->removeUser(0, N); 3882 N->OperandList[0] = Op1; 3883 N->OperandList[0].setUser(N); 3884 Op1.getNode()->addUser(0, N); 3885 } 3886 if (N->OperandList[1] != Op2) { 3887 N->OperandList[1].getVal()->removeUser(1, N); 3888 N->OperandList[1] = Op2; 3889 N->OperandList[1].setUser(N); 3890 Op2.getNode()->addUser(1, N); 3891 } 3892 3893 // If this gets put into a CSE map, add it. 3894 if (InsertPos) CSEMap.InsertNode(N, InsertPos); 3895 return InN; 3896} 3897 3898SDValue SelectionDAG:: 3899UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, SDValue Op3) { 3900 SDValue Ops[] = { Op1, Op2, Op3 }; 3901 return UpdateNodeOperands(N, Ops, 3); 3902} 3903 3904SDValue SelectionDAG:: 3905UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, 3906 SDValue Op3, SDValue Op4) { 3907 SDValue Ops[] = { Op1, Op2, Op3, Op4 }; 3908 return UpdateNodeOperands(N, Ops, 4); 3909} 3910 3911SDValue SelectionDAG:: 3912UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, 3913 SDValue Op3, SDValue Op4, SDValue Op5) { 3914 SDValue Ops[] = { Op1, Op2, Op3, Op4, Op5 }; 3915 return UpdateNodeOperands(N, Ops, 5); 3916} 3917 3918SDValue SelectionDAG:: 3919UpdateNodeOperands(SDValue InN, const SDValue *Ops, unsigned NumOps) { 3920 SDNode *N = InN.getNode(); 3921 assert(N->getNumOperands() == NumOps && 3922 "Update with wrong number of operands"); 3923 3924 // Check to see if there is no change. 3925 bool AnyChange = false; 3926 for (unsigned i = 0; i != NumOps; ++i) { 3927 if (Ops[i] != N->getOperand(i)) { 3928 AnyChange = true; 3929 break; 3930 } 3931 } 3932 3933 // No operands changed, just return the input node. 3934 if (!AnyChange) return InN; 3935 3936 // See if the modified node already exists. 3937 void *InsertPos = 0; 3938 if (SDNode *Existing = FindModifiedNodeSlot(N, Ops, NumOps, InsertPos)) 3939 return SDValue(Existing, InN.getResNo()); 3940 3941 // Nope it doesn't. Remove the node from its current place in the maps. 3942 if (InsertPos) 3943 if (!RemoveNodeFromCSEMaps(N)) 3944 InsertPos = 0; 3945 3946 // Now we update the operands. 3947 for (unsigned i = 0; i != NumOps; ++i) { 3948 if (N->OperandList[i] != Ops[i]) { 3949 N->OperandList[i].getVal()->removeUser(i, N); 3950 N->OperandList[i] = Ops[i]; 3951 N->OperandList[i].setUser(N); 3952 Ops[i].getNode()->addUser(i, N); 3953 } 3954 } 3955 3956 // If this gets put into a CSE map, add it. 3957 if (InsertPos) CSEMap.InsertNode(N, InsertPos); 3958 return InN; 3959} 3960 3961/// DropOperands - Release the operands and set this node to have 3962/// zero operands. 3963void SDNode::DropOperands() { 3964 // Unlike the code in MorphNodeTo that does this, we don't need to 3965 // watch for dead nodes here. 3966 for (op_iterator I = op_begin(), E = op_end(); I != E; ++I) 3967 I->getVal()->removeUser(std::distance(op_begin(), I), this); 3968 3969 NumOperands = 0; 3970} 3971 3972/// SelectNodeTo - These are wrappers around MorphNodeTo that accept a 3973/// machine opcode. 3974/// 3975SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 3976 MVT VT) { 3977 SDVTList VTs = getVTList(VT); 3978 return SelectNodeTo(N, MachineOpc, VTs, 0, 0); 3979} 3980 3981SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 3982 MVT VT, SDValue Op1) { 3983 SDVTList VTs = getVTList(VT); 3984 SDValue Ops[] = { Op1 }; 3985 return SelectNodeTo(N, MachineOpc, VTs, Ops, 1); 3986} 3987 3988SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 3989 MVT VT, SDValue Op1, 3990 SDValue Op2) { 3991 SDVTList VTs = getVTList(VT); 3992 SDValue Ops[] = { Op1, Op2 }; 3993 return SelectNodeTo(N, MachineOpc, VTs, Ops, 2); 3994} 3995 3996SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 3997 MVT VT, SDValue Op1, 3998 SDValue Op2, SDValue Op3) { 3999 SDVTList VTs = getVTList(VT); 4000 SDValue Ops[] = { Op1, Op2, Op3 }; 4001 return SelectNodeTo(N, MachineOpc, VTs, Ops, 3); 4002} 4003 4004SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4005 MVT VT, const SDValue *Ops, 4006 unsigned NumOps) { 4007 SDVTList VTs = getVTList(VT); 4008 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 4009} 4010 4011SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4012 MVT VT1, MVT VT2, const SDValue *Ops, 4013 unsigned NumOps) { 4014 SDVTList VTs = getVTList(VT1, VT2); 4015 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 4016} 4017 4018SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4019 MVT VT1, MVT VT2) { 4020 SDVTList VTs = getVTList(VT1, VT2); 4021 return SelectNodeTo(N, MachineOpc, VTs, (SDValue *)0, 0); 4022} 4023 4024SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4025 MVT VT1, MVT VT2, MVT VT3, 4026 const SDValue *Ops, unsigned NumOps) { 4027 SDVTList VTs = getVTList(VT1, VT2, VT3); 4028 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 4029} 4030 4031SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4032 MVT VT1, MVT VT2, 4033 SDValue Op1) { 4034 SDVTList VTs = getVTList(VT1, VT2); 4035 SDValue Ops[] = { Op1 }; 4036 return SelectNodeTo(N, MachineOpc, VTs, Ops, 1); 4037} 4038 4039SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4040 MVT VT1, MVT VT2, 4041 SDValue Op1, SDValue Op2) { 4042 SDVTList VTs = getVTList(VT1, VT2); 4043 SDValue Ops[] = { Op1, Op2 }; 4044 return SelectNodeTo(N, MachineOpc, VTs, Ops, 2); 4045} 4046 4047SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4048 MVT VT1, MVT VT2, 4049 SDValue Op1, SDValue Op2, 4050 SDValue Op3) { 4051 SDVTList VTs = getVTList(VT1, VT2); 4052 SDValue Ops[] = { Op1, Op2, Op3 }; 4053 return SelectNodeTo(N, MachineOpc, VTs, Ops, 3); 4054} 4055 4056SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4057 SDVTList VTs, const SDValue *Ops, 4058 unsigned NumOps) { 4059 return MorphNodeTo(N, ~MachineOpc, VTs, Ops, NumOps); 4060} 4061 4062SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4063 MVT VT) { 4064 SDVTList VTs = getVTList(VT); 4065 return MorphNodeTo(N, Opc, VTs, 0, 0); 4066} 4067 4068SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4069 MVT VT, SDValue Op1) { 4070 SDVTList VTs = getVTList(VT); 4071 SDValue Ops[] = { Op1 }; 4072 return MorphNodeTo(N, Opc, VTs, Ops, 1); 4073} 4074 4075SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4076 MVT VT, SDValue Op1, 4077 SDValue Op2) { 4078 SDVTList VTs = getVTList(VT); 4079 SDValue Ops[] = { Op1, Op2 }; 4080 return MorphNodeTo(N, Opc, VTs, Ops, 2); 4081} 4082 4083SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4084 MVT VT, SDValue Op1, 4085 SDValue Op2, SDValue Op3) { 4086 SDVTList VTs = getVTList(VT); 4087 SDValue Ops[] = { Op1, Op2, Op3 }; 4088 return MorphNodeTo(N, Opc, VTs, Ops, 3); 4089} 4090 4091SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4092 MVT VT, const SDValue *Ops, 4093 unsigned NumOps) { 4094 SDVTList VTs = getVTList(VT); 4095 return MorphNodeTo(N, Opc, VTs, Ops, NumOps); 4096} 4097 4098SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4099 MVT VT1, MVT VT2, const SDValue *Ops, 4100 unsigned NumOps) { 4101 SDVTList VTs = getVTList(VT1, VT2); 4102 return MorphNodeTo(N, Opc, VTs, Ops, NumOps); 4103} 4104 4105SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4106 MVT VT1, MVT VT2) { 4107 SDVTList VTs = getVTList(VT1, VT2); 4108 return MorphNodeTo(N, Opc, VTs, (SDValue *)0, 0); 4109} 4110 4111SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4112 MVT VT1, MVT VT2, MVT VT3, 4113 const SDValue *Ops, unsigned NumOps) { 4114 SDVTList VTs = getVTList(VT1, VT2, VT3); 4115 return MorphNodeTo(N, Opc, VTs, Ops, NumOps); 4116} 4117 4118SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4119 MVT VT1, MVT VT2, 4120 SDValue Op1) { 4121 SDVTList VTs = getVTList(VT1, VT2); 4122 SDValue Ops[] = { Op1 }; 4123 return MorphNodeTo(N, Opc, VTs, Ops, 1); 4124} 4125 4126SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4127 MVT VT1, MVT VT2, 4128 SDValue Op1, SDValue Op2) { 4129 SDVTList VTs = getVTList(VT1, VT2); 4130 SDValue Ops[] = { Op1, Op2 }; 4131 return MorphNodeTo(N, Opc, VTs, Ops, 2); 4132} 4133 4134SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4135 MVT VT1, MVT VT2, 4136 SDValue Op1, SDValue Op2, 4137 SDValue Op3) { 4138 SDVTList VTs = getVTList(VT1, VT2); 4139 SDValue Ops[] = { Op1, Op2, Op3 }; 4140 return MorphNodeTo(N, Opc, VTs, Ops, 3); 4141} 4142 4143/// MorphNodeTo - These *mutate* the specified node to have the specified 4144/// return type, opcode, and operands. 4145/// 4146/// Note that MorphNodeTo returns the resultant node. If there is already a 4147/// node of the specified opcode and operands, it returns that node instead of 4148/// the current one. 4149/// 4150/// Using MorphNodeTo is faster than creating a new node and swapping it in 4151/// with ReplaceAllUsesWith both because it often avoids allocating a new 4152/// node, and because it doesn't require CSE recalculation for any of 4153/// the node's users. 4154/// 4155SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4156 SDVTList VTs, const SDValue *Ops, 4157 unsigned NumOps) { 4158 // If an identical node already exists, use it. 4159 void *IP = 0; 4160 if (VTs.VTs[VTs.NumVTs-1] != MVT::Flag) { 4161 FoldingSetNodeID ID; 4162 AddNodeIDNode(ID, Opc, VTs, Ops, NumOps); 4163 if (SDNode *ON = CSEMap.FindNodeOrInsertPos(ID, IP)) 4164 return ON; 4165 } 4166 4167 if (!RemoveNodeFromCSEMaps(N)) 4168 IP = 0; 4169 4170 // Start the morphing. 4171 N->NodeType = Opc; 4172 N->ValueList = VTs.VTs; 4173 N->NumValues = VTs.NumVTs; 4174 4175 // Clear the operands list, updating used nodes to remove this from their 4176 // use list. Keep track of any operands that become dead as a result. 4177 SmallPtrSet<SDNode*, 16> DeadNodeSet; 4178 for (SDNode::op_iterator B = N->op_begin(), I = B, E = N->op_end(); 4179 I != E; ++I) { 4180 SDNode *Used = I->getVal(); 4181 Used->removeUser(std::distance(B, I), N); 4182 if (Used->use_empty()) 4183 DeadNodeSet.insert(Used); 4184 } 4185 4186 // If NumOps is larger than the # of operands we currently have, reallocate 4187 // the operand list. 4188 if (NumOps > N->NumOperands) { 4189 if (N->OperandsNeedDelete) 4190 delete[] N->OperandList; 4191 4192 if (N->isMachineOpcode()) { 4193 // We're creating a final node that will live unmorphed for the 4194 // remainder of the current SelectionDAG iteration, so we can allocate 4195 // the operands directly out of a pool with no recycling metadata. 4196 N->OperandList = OperandAllocator.Allocate<SDUse>(NumOps); 4197 N->OperandsNeedDelete = false; 4198 } else { 4199 N->OperandList = new SDUse[NumOps]; 4200 N->OperandsNeedDelete = true; 4201 } 4202 } 4203 4204 // Assign the new operands. 4205 N->NumOperands = NumOps; 4206 for (unsigned i = 0, e = NumOps; i != e; ++i) { 4207 N->OperandList[i] = Ops[i]; 4208 N->OperandList[i].setUser(N); 4209 SDNode *ToUse = N->OperandList[i].getVal(); 4210 ToUse->addUser(i, N); 4211 } 4212 4213 // Delete any nodes that are still dead after adding the uses for the 4214 // new operands. 4215 SmallVector<SDNode *, 16> DeadNodes; 4216 for (SmallPtrSet<SDNode *, 16>::iterator I = DeadNodeSet.begin(), 4217 E = DeadNodeSet.end(); I != E; ++I) 4218 if ((*I)->use_empty()) 4219 DeadNodes.push_back(*I); 4220 RemoveDeadNodes(DeadNodes); 4221 4222 if (IP) 4223 CSEMap.InsertNode(N, IP); // Memoize the new node. 4224 return N; 4225} 4226 4227 4228/// getTargetNode - These are used for target selectors to create a new node 4229/// with specified return type(s), target opcode, and operands. 4230/// 4231/// Note that getTargetNode returns the resultant node. If there is already a 4232/// node of the specified opcode and operands, it returns that node instead of 4233/// the current one. 4234SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT) { 4235 return getNode(~Opcode, VT).getNode(); 4236} 4237SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT, SDValue Op1) { 4238 return getNode(~Opcode, VT, Op1).getNode(); 4239} 4240SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT, 4241 SDValue Op1, SDValue Op2) { 4242 return getNode(~Opcode, VT, Op1, Op2).getNode(); 4243} 4244SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT, 4245 SDValue Op1, SDValue Op2, 4246 SDValue Op3) { 4247 return getNode(~Opcode, VT, Op1, Op2, Op3).getNode(); 4248} 4249SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT, 4250 const SDValue *Ops, unsigned NumOps) { 4251 return getNode(~Opcode, VT, Ops, NumOps).getNode(); 4252} 4253SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2) { 4254 const MVT *VTs = getNodeValueTypes(VT1, VT2); 4255 SDValue Op; 4256 return getNode(~Opcode, VTs, 2, &Op, 0).getNode(); 4257} 4258SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, 4259 MVT VT2, SDValue Op1) { 4260 const MVT *VTs = getNodeValueTypes(VT1, VT2); 4261 return getNode(~Opcode, VTs, 2, &Op1, 1).getNode(); 4262} 4263SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, 4264 MVT VT2, SDValue Op1, 4265 SDValue Op2) { 4266 const MVT *VTs = getNodeValueTypes(VT1, VT2); 4267 SDValue Ops[] = { Op1, Op2 }; 4268 return getNode(~Opcode, VTs, 2, Ops, 2).getNode(); 4269} 4270SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, 4271 MVT VT2, SDValue Op1, 4272 SDValue Op2, SDValue Op3) { 4273 const MVT *VTs = getNodeValueTypes(VT1, VT2); 4274 SDValue Ops[] = { Op1, Op2, Op3 }; 4275 return getNode(~Opcode, VTs, 2, Ops, 3).getNode(); 4276} 4277SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, 4278 const SDValue *Ops, unsigned NumOps) { 4279 const MVT *VTs = getNodeValueTypes(VT1, VT2); 4280 return getNode(~Opcode, VTs, 2, Ops, NumOps).getNode(); 4281} 4282SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3, 4283 SDValue Op1, SDValue Op2) { 4284 const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3); 4285 SDValue Ops[] = { Op1, Op2 }; 4286 return getNode(~Opcode, VTs, 3, Ops, 2).getNode(); 4287} 4288SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3, 4289 SDValue Op1, SDValue Op2, 4290 SDValue Op3) { 4291 const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3); 4292 SDValue Ops[] = { Op1, Op2, Op3 }; 4293 return getNode(~Opcode, VTs, 3, Ops, 3).getNode(); 4294} 4295SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3, 4296 const SDValue *Ops, unsigned NumOps) { 4297 const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3); 4298 return getNode(~Opcode, VTs, 3, Ops, NumOps).getNode(); 4299} 4300SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, 4301 MVT VT2, MVT VT3, MVT VT4, 4302 const SDValue *Ops, unsigned NumOps) { 4303 std::vector<MVT> VTList; 4304 VTList.push_back(VT1); 4305 VTList.push_back(VT2); 4306 VTList.push_back(VT3); 4307 VTList.push_back(VT4); 4308 const MVT *VTs = getNodeValueTypes(VTList); 4309 return getNode(~Opcode, VTs, 4, Ops, NumOps).getNode(); 4310} 4311SDNode *SelectionDAG::getTargetNode(unsigned Opcode, 4312 const std::vector<MVT> &ResultTys, 4313 const SDValue *Ops, unsigned NumOps) { 4314 const MVT *VTs = getNodeValueTypes(ResultTys); 4315 return getNode(~Opcode, VTs, ResultTys.size(), 4316 Ops, NumOps).getNode(); 4317} 4318 4319/// getNodeIfExists - Get the specified node if it's already available, or 4320/// else return NULL. 4321SDNode *SelectionDAG::getNodeIfExists(unsigned Opcode, SDVTList VTList, 4322 const SDValue *Ops, unsigned NumOps) { 4323 if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) { 4324 FoldingSetNodeID ID; 4325 AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps); 4326 void *IP = 0; 4327 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 4328 return E; 4329 } 4330 return NULL; 4331} 4332 4333 4334/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. 4335/// This can cause recursive merging of nodes in the DAG. 4336/// 4337/// This version assumes From has a single result value. 4338/// 4339void SelectionDAG::ReplaceAllUsesWith(SDValue FromN, SDValue To, 4340 DAGUpdateListener *UpdateListener) { 4341 SDNode *From = FromN.getNode(); 4342 assert(From->getNumValues() == 1 && FromN.getResNo() == 0 && 4343 "Cannot replace with this method!"); 4344 assert(From != To.getNode() && "Cannot replace uses of with self"); 4345 4346 while (!From->use_empty()) { 4347 SDNode::use_iterator UI = From->use_begin(); 4348 SDNode *U = *UI; 4349 4350 // This node is about to morph, remove its old self from the CSE maps. 4351 RemoveNodeFromCSEMaps(U); 4352 int operandNum = 0; 4353 for (SDNode::op_iterator I = U->op_begin(), E = U->op_end(); 4354 I != E; ++I, ++operandNum) 4355 if (I->getVal() == From) { 4356 From->removeUser(operandNum, U); 4357 *I = To; 4358 I->setUser(U); 4359 To.getNode()->addUser(operandNum, U); 4360 } 4361 4362 // Now that we have modified U, add it back to the CSE maps. If it already 4363 // exists there, recursively merge the results together. 4364 if (SDNode *Existing = AddNonLeafNodeToCSEMaps(U)) { 4365 ReplaceAllUsesWith(U, Existing, UpdateListener); 4366 // U is now dead. Inform the listener if it exists and delete it. 4367 if (UpdateListener) 4368 UpdateListener->NodeDeleted(U, Existing); 4369 DeleteNodeNotInCSEMaps(U); 4370 } else { 4371 // If the node doesn't already exist, we updated it. Inform a listener if 4372 // it exists. 4373 if (UpdateListener) 4374 UpdateListener->NodeUpdated(U); 4375 } 4376 } 4377} 4378 4379/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. 4380/// This can cause recursive merging of nodes in the DAG. 4381/// 4382/// This version assumes From/To have matching types and numbers of result 4383/// values. 4384/// 4385void SelectionDAG::ReplaceAllUsesWith(SDNode *From, SDNode *To, 4386 DAGUpdateListener *UpdateListener) { 4387 assert(From->getVTList().VTs == To->getVTList().VTs && 4388 From->getNumValues() == To->getNumValues() && 4389 "Cannot use this version of ReplaceAllUsesWith!"); 4390 4391 // Handle the trivial case. 4392 if (From == To) 4393 return; 4394 4395 while (!From->use_empty()) { 4396 SDNode::use_iterator UI = From->use_begin(); 4397 SDNode *U = *UI; 4398 4399 // This node is about to morph, remove its old self from the CSE maps. 4400 RemoveNodeFromCSEMaps(U); 4401 int operandNum = 0; 4402 for (SDNode::op_iterator I = U->op_begin(), E = U->op_end(); 4403 I != E; ++I, ++operandNum) 4404 if (I->getVal() == From) { 4405 From->removeUser(operandNum, U); 4406 I->getSDValue().setNode(To); 4407 To->addUser(operandNum, U); 4408 } 4409 4410 // Now that we have modified U, add it back to the CSE maps. If it already 4411 // exists there, recursively merge the results together. 4412 if (SDNode *Existing = AddNonLeafNodeToCSEMaps(U)) { 4413 ReplaceAllUsesWith(U, Existing, UpdateListener); 4414 // U is now dead. Inform the listener if it exists and delete it. 4415 if (UpdateListener) 4416 UpdateListener->NodeDeleted(U, Existing); 4417 DeleteNodeNotInCSEMaps(U); 4418 } else { 4419 // If the node doesn't already exist, we updated it. Inform a listener if 4420 // it exists. 4421 if (UpdateListener) 4422 UpdateListener->NodeUpdated(U); 4423 } 4424 } 4425} 4426 4427/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. 4428/// This can cause recursive merging of nodes in the DAG. 4429/// 4430/// This version can replace From with any result values. To must match the 4431/// number and types of values returned by From. 4432void SelectionDAG::ReplaceAllUsesWith(SDNode *From, 4433 const SDValue *To, 4434 DAGUpdateListener *UpdateListener) { 4435 if (From->getNumValues() == 1) // Handle the simple case efficiently. 4436 return ReplaceAllUsesWith(SDValue(From, 0), To[0], UpdateListener); 4437 4438 while (!From->use_empty()) { 4439 SDNode::use_iterator UI = From->use_begin(); 4440 SDNode *U = *UI; 4441 4442 // This node is about to morph, remove its old self from the CSE maps. 4443 RemoveNodeFromCSEMaps(U); 4444 int operandNum = 0; 4445 for (SDNode::op_iterator I = U->op_begin(), E = U->op_end(); 4446 I != E; ++I, ++operandNum) 4447 if (I->getVal() == From) { 4448 const SDValue &ToOp = To[I->getSDValue().getResNo()]; 4449 From->removeUser(operandNum, U); 4450 *I = ToOp; 4451 I->setUser(U); 4452 ToOp.getNode()->addUser(operandNum, U); 4453 } 4454 4455 // Now that we have modified U, add it back to the CSE maps. If it already 4456 // exists there, recursively merge the results together. 4457 if (SDNode *Existing = AddNonLeafNodeToCSEMaps(U)) { 4458 ReplaceAllUsesWith(U, Existing, UpdateListener); 4459 // U is now dead. Inform the listener if it exists and delete it. 4460 if (UpdateListener) 4461 UpdateListener->NodeDeleted(U, Existing); 4462 DeleteNodeNotInCSEMaps(U); 4463 } else { 4464 // If the node doesn't already exist, we updated it. Inform a listener if 4465 // it exists. 4466 if (UpdateListener) 4467 UpdateListener->NodeUpdated(U); 4468 } 4469 } 4470} 4471 4472/// ReplaceAllUsesOfValueWith - Replace any uses of From with To, leaving 4473/// uses of other values produced by From.getVal() alone. The Deleted vector is 4474/// handled the same way as for ReplaceAllUsesWith. 4475void SelectionDAG::ReplaceAllUsesOfValueWith(SDValue From, SDValue To, 4476 DAGUpdateListener *UpdateListener){ 4477 // Handle the really simple, really trivial case efficiently. 4478 if (From == To) return; 4479 4480 // Handle the simple, trivial, case efficiently. 4481 if (From.getNode()->getNumValues() == 1) { 4482 ReplaceAllUsesWith(From, To, UpdateListener); 4483 return; 4484 } 4485 4486 // Get all of the users of From.getNode(). We want these in a nice, 4487 // deterministically ordered and uniqued set, so we use a SmallSetVector. 4488 SmallSetVector<SDNode*, 16> Users(From.getNode()->use_begin(), From.getNode()->use_end()); 4489 4490 while (!Users.empty()) { 4491 // We know that this user uses some value of From. If it is the right 4492 // value, update it. 4493 SDNode *User = Users.back(); 4494 Users.pop_back(); 4495 4496 // Scan for an operand that matches From. 4497 SDNode::op_iterator Op = User->op_begin(), E = User->op_end(); 4498 for (; Op != E; ++Op) 4499 if (*Op == From) break; 4500 4501 // If there are no matches, the user must use some other result of From. 4502 if (Op == E) continue; 4503 4504 // Okay, we know this user needs to be updated. Remove its old self 4505 // from the CSE maps. 4506 RemoveNodeFromCSEMaps(User); 4507 4508 // Update all operands that match "From" in case there are multiple uses. 4509 for (; Op != E; ++Op) { 4510 if (*Op == From) { 4511 From.getNode()->removeUser(Op-User->op_begin(), User); 4512 *Op = To; 4513 Op->setUser(User); 4514 To.getNode()->addUser(Op-User->op_begin(), User); 4515 } 4516 } 4517 4518 // Now that we have modified User, add it back to the CSE maps. If it 4519 // already exists there, recursively merge the results together. 4520 SDNode *Existing = AddNonLeafNodeToCSEMaps(User); 4521 if (!Existing) { 4522 if (UpdateListener) UpdateListener->NodeUpdated(User); 4523 continue; // Continue on to next user. 4524 } 4525 4526 // If there was already an existing matching node, use ReplaceAllUsesWith 4527 // to replace the dead one with the existing one. This can cause 4528 // recursive merging of other unrelated nodes down the line. 4529 ReplaceAllUsesWith(User, Existing, UpdateListener); 4530 4531 // User is now dead. Notify a listener if present. 4532 if (UpdateListener) UpdateListener->NodeDeleted(User, Existing); 4533 DeleteNodeNotInCSEMaps(User); 4534 } 4535} 4536 4537/// ReplaceAllUsesOfValuesWith - Replace any uses of From with To, leaving 4538/// uses of other values produced by From.getVal() alone. The same value may 4539/// appear in both the From and To list. The Deleted vector is 4540/// handled the same way as for ReplaceAllUsesWith. 4541void SelectionDAG::ReplaceAllUsesOfValuesWith(const SDValue *From, 4542 const SDValue *To, 4543 unsigned Num, 4544 DAGUpdateListener *UpdateListener){ 4545 // Handle the simple, trivial case efficiently. 4546 if (Num == 1) 4547 return ReplaceAllUsesOfValueWith(*From, *To, UpdateListener); 4548 4549 SmallVector<std::pair<SDNode *, unsigned>, 16> Users; 4550 for (unsigned i = 0; i != Num; ++i) 4551 for (SDNode::use_iterator UI = From[i].getNode()->use_begin(), 4552 E = From[i].getNode()->use_end(); UI != E; ++UI) 4553 Users.push_back(std::make_pair(*UI, i)); 4554 4555 while (!Users.empty()) { 4556 // We know that this user uses some value of From. If it is the right 4557 // value, update it. 4558 SDNode *User = Users.back().first; 4559 unsigned i = Users.back().second; 4560 Users.pop_back(); 4561 4562 // Scan for an operand that matches From. 4563 SDNode::op_iterator Op = User->op_begin(), E = User->op_end(); 4564 for (; Op != E; ++Op) 4565 if (*Op == From[i]) break; 4566 4567 // If there are no matches, the user must use some other result of From. 4568 if (Op == E) continue; 4569 4570 // Okay, we know this user needs to be updated. Remove its old self 4571 // from the CSE maps. 4572 RemoveNodeFromCSEMaps(User); 4573 4574 // Update all operands that match "From" in case there are multiple uses. 4575 for (; Op != E; ++Op) { 4576 if (*Op == From[i]) { 4577 From[i].getNode()->removeUser(Op-User->op_begin(), User); 4578 *Op = To[i]; 4579 Op->setUser(User); 4580 To[i].getNode()->addUser(Op-User->op_begin(), User); 4581 } 4582 } 4583 4584 // Now that we have modified User, add it back to the CSE maps. If it 4585 // already exists there, recursively merge the results together. 4586 SDNode *Existing = AddNonLeafNodeToCSEMaps(User); 4587 if (!Existing) { 4588 if (UpdateListener) UpdateListener->NodeUpdated(User); 4589 continue; // Continue on to next user. 4590 } 4591 4592 // If there was already an existing matching node, use ReplaceAllUsesWith 4593 // to replace the dead one with the existing one. This can cause 4594 // recursive merging of other unrelated nodes down the line. 4595 ReplaceAllUsesWith(User, Existing, UpdateListener); 4596 4597 // User is now dead. Notify a listener if present. 4598 if (UpdateListener) UpdateListener->NodeDeleted(User, Existing); 4599 DeleteNodeNotInCSEMaps(User); 4600 } 4601} 4602 4603/// AssignTopologicalOrder - Assign a unique node id for each node in the DAG 4604/// based on their topological order. It returns the maximum id and a vector 4605/// of the SDNodes* in assigned order by reference. 4606unsigned SelectionDAG::AssignTopologicalOrder() { 4607 4608 unsigned DAGSize = 0; 4609 4610 // SortedPos tracks the progress of the algorithm. Nodes before it are 4611 // sorted, nodes after it are unsorted. When the algorithm completes 4612 // it is at the end of the list. 4613 allnodes_iterator SortedPos = allnodes_begin(); 4614 4615 // Visit all the nodes. Add nodes with no operands to the TopOrder result 4616 // array immediately. Annotate nodes that do have operands with their 4617 // operand count. Before we do this, the Node Id fields of the nodes 4618 // may contain arbitrary values. After, the Node Id fields for nodes 4619 // before SortedPos will contain the topological sort index, and the 4620 // Node Id fields for nodes At SortedPos and after will contain the 4621 // count of outstanding operands. 4622 for (allnodes_iterator I = allnodes_begin(),E = allnodes_end(); I != E; ) { 4623 SDNode *N = I++; 4624 unsigned Degree = N->getNumOperands(); 4625 if (Degree == 0) { 4626 // A node with no uses, add it to the result array immediately. 4627 N->setNodeId(DAGSize++); 4628 allnodes_iterator Q = N; 4629 if (Q != SortedPos) 4630 SortedPos = AllNodes.insert(SortedPos, AllNodes.remove(Q)); 4631 ++SortedPos; 4632 } else { 4633 // Temporarily use the Node Id as scratch space for the degree count. 4634 N->setNodeId(Degree); 4635 } 4636 } 4637 4638 // Visit all the nodes. As we iterate, moves nodes into sorted order, 4639 // such that by the time the end is reached all nodes will be sorted. 4640 for (allnodes_iterator I = allnodes_begin(),E = allnodes_end(); I != E; ++I) { 4641 SDNode *N = I; 4642 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 4643 UI != UE; ++UI) { 4644 SDNode *P = *UI; 4645 unsigned Degree = P->getNodeId(); 4646 --Degree; 4647 if (Degree == 0) { 4648 // All of P's operands are sorted, so P may sorted now. 4649 P->setNodeId(DAGSize++); 4650 if (P != SortedPos) 4651 SortedPos = AllNodes.insert(SortedPos, AllNodes.remove(P)); 4652 ++SortedPos; 4653 } else { 4654 // Update P's outstanding operand count. 4655 P->setNodeId(Degree); 4656 } 4657 } 4658 } 4659 4660 assert(SortedPos == AllNodes.end() && 4661 "Topological sort incomplete!"); 4662 assert(AllNodes.front().getOpcode() == ISD::EntryToken && 4663 "First node in topological sort is not the entry token!"); 4664 assert(AllNodes.front().getNodeId() == 0 && 4665 "First node in topological sort has non-zero id!"); 4666 assert(AllNodes.front().getNumOperands() == 0 && 4667 "First node in topological sort has operands!"); 4668 assert(AllNodes.back().getNodeId() == (int)DAGSize-1 && 4669 "Last node in topologic sort has unexpected id!"); 4670 assert(AllNodes.back().use_empty() && 4671 "Last node in topologic sort has users!"); 4672 assert(DAGSize == allnodes_size() && "TopOrder result count mismatch!"); 4673 return DAGSize; 4674} 4675 4676 4677 4678//===----------------------------------------------------------------------===// 4679// SDNode Class 4680//===----------------------------------------------------------------------===// 4681 4682// Out-of-line virtual method to give class a home. 4683void SDNode::ANCHOR() {} 4684void UnarySDNode::ANCHOR() {} 4685void BinarySDNode::ANCHOR() {} 4686void TernarySDNode::ANCHOR() {} 4687void HandleSDNode::ANCHOR() {} 4688void ConstantSDNode::ANCHOR() {} 4689void ConstantFPSDNode::ANCHOR() {} 4690void GlobalAddressSDNode::ANCHOR() {} 4691void FrameIndexSDNode::ANCHOR() {} 4692void JumpTableSDNode::ANCHOR() {} 4693void ConstantPoolSDNode::ANCHOR() {} 4694void BasicBlockSDNode::ANCHOR() {} 4695void SrcValueSDNode::ANCHOR() {} 4696void MemOperandSDNode::ANCHOR() {} 4697void RegisterSDNode::ANCHOR() {} 4698void DbgStopPointSDNode::ANCHOR() {} 4699void LabelSDNode::ANCHOR() {} 4700void ExternalSymbolSDNode::ANCHOR() {} 4701void CondCodeSDNode::ANCHOR() {} 4702void ARG_FLAGSSDNode::ANCHOR() {} 4703void VTSDNode::ANCHOR() {} 4704void MemSDNode::ANCHOR() {} 4705void LoadSDNode::ANCHOR() {} 4706void StoreSDNode::ANCHOR() {} 4707void AtomicSDNode::ANCHOR() {} 4708void MemIntrinsicSDNode::ANCHOR() {} 4709void CallSDNode::ANCHOR() {} 4710 4711HandleSDNode::~HandleSDNode() { 4712 DropOperands(); 4713} 4714 4715GlobalAddressSDNode::GlobalAddressSDNode(bool isTarget, const GlobalValue *GA, 4716 MVT VT, int64_t o) 4717 : SDNode(isa<GlobalVariable>(GA) && 4718 cast<GlobalVariable>(GA)->isThreadLocal() ? 4719 // Thread Local 4720 (isTarget ? ISD::TargetGlobalTLSAddress : ISD::GlobalTLSAddress) : 4721 // Non Thread Local 4722 (isTarget ? ISD::TargetGlobalAddress : ISD::GlobalAddress), 4723 getSDVTList(VT)), Offset(o) { 4724 TheGlobal = const_cast<GlobalValue*>(GA); 4725} 4726 4727MemSDNode::MemSDNode(unsigned Opc, SDVTList VTs, MVT memvt, 4728 const Value *srcValue, int SVO, 4729 unsigned alignment, bool vol) 4730 : SDNode(Opc, VTs), MemoryVT(memvt), SrcValue(srcValue), SVOffset(SVO), 4731 Flags(encodeMemSDNodeFlags(vol, alignment)) { 4732 4733 assert(isPowerOf2_32(alignment) && "Alignment is not a power of 2!"); 4734 assert(getAlignment() == alignment && "Alignment representation error!"); 4735 assert(isVolatile() == vol && "Volatile representation error!"); 4736} 4737 4738MemSDNode::MemSDNode(unsigned Opc, SDVTList VTs, const SDValue *Ops, 4739 unsigned NumOps, MVT memvt, const Value *srcValue, 4740 int SVO, unsigned alignment, bool vol) 4741 : SDNode(Opc, VTs, Ops, NumOps), 4742 MemoryVT(memvt), SrcValue(srcValue), SVOffset(SVO), 4743 Flags(vol | ((Log2_32(alignment) + 1) << 1)) { 4744 assert(isPowerOf2_32(alignment) && "Alignment is not a power of 2!"); 4745 assert(getAlignment() == alignment && "Alignment representation error!"); 4746 assert(isVolatile() == vol && "Volatile representation error!"); 4747} 4748 4749/// getMemOperand - Return a MachineMemOperand object describing the memory 4750/// reference performed by this memory reference. 4751MachineMemOperand MemSDNode::getMemOperand() const { 4752 int Flags = 0; 4753 if (isa<LoadSDNode>(this)) 4754 Flags = MachineMemOperand::MOLoad; 4755 else if (isa<StoreSDNode>(this)) 4756 Flags = MachineMemOperand::MOStore; 4757 else if (isa<AtomicSDNode>(this)) { 4758 Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore; 4759 } 4760 else { 4761 const MemIntrinsicSDNode* MemIntrinNode = dyn_cast<MemIntrinsicSDNode>(this); 4762 assert(MemIntrinNode && "Unknown MemSDNode opcode!"); 4763 if (MemIntrinNode->readMem()) Flags |= MachineMemOperand::MOLoad; 4764 if (MemIntrinNode->writeMem()) Flags |= MachineMemOperand::MOStore; 4765 } 4766 4767 int Size = (getMemoryVT().getSizeInBits() + 7) >> 3; 4768 if (isVolatile()) Flags |= MachineMemOperand::MOVolatile; 4769 4770 // Check if the memory reference references a frame index 4771 const FrameIndexSDNode *FI = 4772 dyn_cast<const FrameIndexSDNode>(getBasePtr().getNode()); 4773 if (!getSrcValue() && FI) 4774 return MachineMemOperand(PseudoSourceValue::getFixedStack(FI->getIndex()), 4775 Flags, 0, Size, getAlignment()); 4776 else 4777 return MachineMemOperand(getSrcValue(), Flags, getSrcValueOffset(), 4778 Size, getAlignment()); 4779} 4780 4781/// Profile - Gather unique data for the node. 4782/// 4783void SDNode::Profile(FoldingSetNodeID &ID) const { 4784 AddNodeIDNode(ID, this); 4785} 4786 4787/// getValueTypeList - Return a pointer to the specified value type. 4788/// 4789const MVT *SDNode::getValueTypeList(MVT VT) { 4790 if (VT.isExtended()) { 4791 static std::set<MVT, MVT::compareRawBits> EVTs; 4792 return &(*EVTs.insert(VT).first); 4793 } else { 4794 static MVT VTs[MVT::LAST_VALUETYPE]; 4795 VTs[VT.getSimpleVT()] = VT; 4796 return &VTs[VT.getSimpleVT()]; 4797 } 4798} 4799 4800/// hasNUsesOfValue - Return true if there are exactly NUSES uses of the 4801/// indicated value. This method ignores uses of other values defined by this 4802/// operation. 4803bool SDNode::hasNUsesOfValue(unsigned NUses, unsigned Value) const { 4804 assert(Value < getNumValues() && "Bad value!"); 4805 4806 // TODO: Only iterate over uses of a given value of the node 4807 for (SDNode::use_iterator UI = use_begin(), E = use_end(); UI != E; ++UI) { 4808 if (UI.getUse().getSDValue().getResNo() == Value) { 4809 if (NUses == 0) 4810 return false; 4811 --NUses; 4812 } 4813 } 4814 4815 // Found exactly the right number of uses? 4816 return NUses == 0; 4817} 4818 4819 4820/// hasAnyUseOfValue - Return true if there are any use of the indicated 4821/// value. This method ignores uses of other values defined by this operation. 4822bool SDNode::hasAnyUseOfValue(unsigned Value) const { 4823 assert(Value < getNumValues() && "Bad value!"); 4824 4825 for (SDNode::use_iterator UI = use_begin(), E = use_end(); UI != E; ++UI) 4826 if (UI.getUse().getSDValue().getResNo() == Value) 4827 return true; 4828 4829 return false; 4830} 4831 4832 4833/// isOnlyUserOf - Return true if this node is the only use of N. 4834/// 4835bool SDNode::isOnlyUserOf(SDNode *N) const { 4836 bool Seen = false; 4837 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 4838 SDNode *User = *I; 4839 if (User == this) 4840 Seen = true; 4841 else 4842 return false; 4843 } 4844 4845 return Seen; 4846} 4847 4848/// isOperand - Return true if this node is an operand of N. 4849/// 4850bool SDValue::isOperandOf(SDNode *N) const { 4851 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 4852 if (*this == N->getOperand(i)) 4853 return true; 4854 return false; 4855} 4856 4857bool SDNode::isOperandOf(SDNode *N) const { 4858 for (unsigned i = 0, e = N->NumOperands; i != e; ++i) 4859 if (this == N->OperandList[i].getVal()) 4860 return true; 4861 return false; 4862} 4863 4864/// reachesChainWithoutSideEffects - Return true if this operand (which must 4865/// be a chain) reaches the specified operand without crossing any 4866/// side-effecting instructions. In practice, this looks through token 4867/// factors and non-volatile loads. In order to remain efficient, this only 4868/// looks a couple of nodes in, it does not do an exhaustive search. 4869bool SDValue::reachesChainWithoutSideEffects(SDValue Dest, 4870 unsigned Depth) const { 4871 if (*this == Dest) return true; 4872 4873 // Don't search too deeply, we just want to be able to see through 4874 // TokenFactor's etc. 4875 if (Depth == 0) return false; 4876 4877 // If this is a token factor, all inputs to the TF happen in parallel. If any 4878 // of the operands of the TF reach dest, then we can do the xform. 4879 if (getOpcode() == ISD::TokenFactor) { 4880 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) 4881 if (getOperand(i).reachesChainWithoutSideEffects(Dest, Depth-1)) 4882 return true; 4883 return false; 4884 } 4885 4886 // Loads don't have side effects, look through them. 4887 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(*this)) { 4888 if (!Ld->isVolatile()) 4889 return Ld->getChain().reachesChainWithoutSideEffects(Dest, Depth-1); 4890 } 4891 return false; 4892} 4893 4894 4895static void findPredecessor(SDNode *N, const SDNode *P, bool &found, 4896 SmallPtrSet<SDNode *, 32> &Visited) { 4897 if (found || !Visited.insert(N)) 4898 return; 4899 4900 for (unsigned i = 0, e = N->getNumOperands(); !found && i != e; ++i) { 4901 SDNode *Op = N->getOperand(i).getNode(); 4902 if (Op == P) { 4903 found = true; 4904 return; 4905 } 4906 findPredecessor(Op, P, found, Visited); 4907 } 4908} 4909 4910/// isPredecessorOf - Return true if this node is a predecessor of N. This node 4911/// is either an operand of N or it can be reached by recursively traversing 4912/// up the operands. 4913/// NOTE: this is an expensive method. Use it carefully. 4914bool SDNode::isPredecessorOf(SDNode *N) const { 4915 SmallPtrSet<SDNode *, 32> Visited; 4916 bool found = false; 4917 findPredecessor(N, this, found, Visited); 4918 return found; 4919} 4920 4921uint64_t SDNode::getConstantOperandVal(unsigned Num) const { 4922 assert(Num < NumOperands && "Invalid child # of SDNode!"); 4923 return cast<ConstantSDNode>(OperandList[Num])->getZExtValue(); 4924} 4925 4926std::string SDNode::getOperationName(const SelectionDAG *G) const { 4927 switch (getOpcode()) { 4928 default: 4929 if (getOpcode() < ISD::BUILTIN_OP_END) 4930 return "<<Unknown DAG Node>>"; 4931 if (isMachineOpcode()) { 4932 if (G) 4933 if (const TargetInstrInfo *TII = G->getTarget().getInstrInfo()) 4934 if (getMachineOpcode() < TII->getNumOpcodes()) 4935 return TII->get(getMachineOpcode()).getName(); 4936 return "<<Unknown Machine Node>>"; 4937 } 4938 if (G) { 4939 TargetLowering &TLI = G->getTargetLoweringInfo(); 4940 const char *Name = TLI.getTargetNodeName(getOpcode()); 4941 if (Name) return Name; 4942 return "<<Unknown Target Node>>"; 4943 } 4944 return "<<Unknown Node>>"; 4945 4946#ifndef NDEBUG 4947 case ISD::DELETED_NODE: 4948 return "<<Deleted Node!>>"; 4949#endif 4950 case ISD::PREFETCH: return "Prefetch"; 4951 case ISD::MEMBARRIER: return "MemBarrier"; 4952 case ISD::ATOMIC_CMP_SWAP_8: return "AtomicCmpSwap8"; 4953 case ISD::ATOMIC_SWAP_8: return "AtomicSwap8"; 4954 case ISD::ATOMIC_LOAD_ADD_8: return "AtomicLoadAdd8"; 4955 case ISD::ATOMIC_LOAD_SUB_8: return "AtomicLoadSub8"; 4956 case ISD::ATOMIC_LOAD_AND_8: return "AtomicLoadAnd8"; 4957 case ISD::ATOMIC_LOAD_OR_8: return "AtomicLoadOr8"; 4958 case ISD::ATOMIC_LOAD_XOR_8: return "AtomicLoadXor8"; 4959 case ISD::ATOMIC_LOAD_NAND_8: return "AtomicLoadNand8"; 4960 case ISD::ATOMIC_LOAD_MIN_8: return "AtomicLoadMin8"; 4961 case ISD::ATOMIC_LOAD_MAX_8: return "AtomicLoadMax8"; 4962 case ISD::ATOMIC_LOAD_UMIN_8: return "AtomicLoadUMin8"; 4963 case ISD::ATOMIC_LOAD_UMAX_8: return "AtomicLoadUMax8"; 4964 case ISD::ATOMIC_CMP_SWAP_16: return "AtomicCmpSwap16"; 4965 case ISD::ATOMIC_SWAP_16: return "AtomicSwap16"; 4966 case ISD::ATOMIC_LOAD_ADD_16: return "AtomicLoadAdd16"; 4967 case ISD::ATOMIC_LOAD_SUB_16: return "AtomicLoadSub16"; 4968 case ISD::ATOMIC_LOAD_AND_16: return "AtomicLoadAnd16"; 4969 case ISD::ATOMIC_LOAD_OR_16: return "AtomicLoadOr16"; 4970 case ISD::ATOMIC_LOAD_XOR_16: return "AtomicLoadXor16"; 4971 case ISD::ATOMIC_LOAD_NAND_16: return "AtomicLoadNand16"; 4972 case ISD::ATOMIC_LOAD_MIN_16: return "AtomicLoadMin16"; 4973 case ISD::ATOMIC_LOAD_MAX_16: return "AtomicLoadMax16"; 4974 case ISD::ATOMIC_LOAD_UMIN_16: return "AtomicLoadUMin16"; 4975 case ISD::ATOMIC_LOAD_UMAX_16: return "AtomicLoadUMax16"; 4976 case ISD::ATOMIC_CMP_SWAP_32: return "AtomicCmpSwap32"; 4977 case ISD::ATOMIC_SWAP_32: return "AtomicSwap32"; 4978 case ISD::ATOMIC_LOAD_ADD_32: return "AtomicLoadAdd32"; 4979 case ISD::ATOMIC_LOAD_SUB_32: return "AtomicLoadSub32"; 4980 case ISD::ATOMIC_LOAD_AND_32: return "AtomicLoadAnd32"; 4981 case ISD::ATOMIC_LOAD_OR_32: return "AtomicLoadOr32"; 4982 case ISD::ATOMIC_LOAD_XOR_32: return "AtomicLoadXor32"; 4983 case ISD::ATOMIC_LOAD_NAND_32: return "AtomicLoadNand32"; 4984 case ISD::ATOMIC_LOAD_MIN_32: return "AtomicLoadMin32"; 4985 case ISD::ATOMIC_LOAD_MAX_32: return "AtomicLoadMax32"; 4986 case ISD::ATOMIC_LOAD_UMIN_32: return "AtomicLoadUMin32"; 4987 case ISD::ATOMIC_LOAD_UMAX_32: return "AtomicLoadUMax32"; 4988 case ISD::ATOMIC_CMP_SWAP_64: return "AtomicCmpSwap64"; 4989 case ISD::ATOMIC_SWAP_64: return "AtomicSwap64"; 4990 case ISD::ATOMIC_LOAD_ADD_64: return "AtomicLoadAdd64"; 4991 case ISD::ATOMIC_LOAD_SUB_64: return "AtomicLoadSub64"; 4992 case ISD::ATOMIC_LOAD_AND_64: return "AtomicLoadAnd64"; 4993 case ISD::ATOMIC_LOAD_OR_64: return "AtomicLoadOr64"; 4994 case ISD::ATOMIC_LOAD_XOR_64: return "AtomicLoadXor64"; 4995 case ISD::ATOMIC_LOAD_NAND_64: return "AtomicLoadNand64"; 4996 case ISD::ATOMIC_LOAD_MIN_64: return "AtomicLoadMin64"; 4997 case ISD::ATOMIC_LOAD_MAX_64: return "AtomicLoadMax64"; 4998 case ISD::ATOMIC_LOAD_UMIN_64: return "AtomicLoadUMin64"; 4999 case ISD::ATOMIC_LOAD_UMAX_64: return "AtomicLoadUMax64"; 5000 case ISD::PCMARKER: return "PCMarker"; 5001 case ISD::READCYCLECOUNTER: return "ReadCycleCounter"; 5002 case ISD::SRCVALUE: return "SrcValue"; 5003 case ISD::MEMOPERAND: return "MemOperand"; 5004 case ISD::EntryToken: return "EntryToken"; 5005 case ISD::TokenFactor: return "TokenFactor"; 5006 case ISD::AssertSext: return "AssertSext"; 5007 case ISD::AssertZext: return "AssertZext"; 5008 5009 case ISD::BasicBlock: return "BasicBlock"; 5010 case ISD::ARG_FLAGS: return "ArgFlags"; 5011 case ISD::VALUETYPE: return "ValueType"; 5012 case ISD::Register: return "Register"; 5013 5014 case ISD::Constant: return "Constant"; 5015 case ISD::ConstantFP: return "ConstantFP"; 5016 case ISD::GlobalAddress: return "GlobalAddress"; 5017 case ISD::GlobalTLSAddress: return "GlobalTLSAddress"; 5018 case ISD::FrameIndex: return "FrameIndex"; 5019 case ISD::JumpTable: return "JumpTable"; 5020 case ISD::GLOBAL_OFFSET_TABLE: return "GLOBAL_OFFSET_TABLE"; 5021 case ISD::RETURNADDR: return "RETURNADDR"; 5022 case ISD::FRAMEADDR: return "FRAMEADDR"; 5023 case ISD::FRAME_TO_ARGS_OFFSET: return "FRAME_TO_ARGS_OFFSET"; 5024 case ISD::EXCEPTIONADDR: return "EXCEPTIONADDR"; 5025 case ISD::EHSELECTION: return "EHSELECTION"; 5026 case ISD::EH_RETURN: return "EH_RETURN"; 5027 case ISD::ConstantPool: return "ConstantPool"; 5028 case ISD::ExternalSymbol: return "ExternalSymbol"; 5029 case ISD::INTRINSIC_WO_CHAIN: { 5030 unsigned IID = cast<ConstantSDNode>(getOperand(0))->getZExtValue(); 5031 return Intrinsic::getName((Intrinsic::ID)IID); 5032 } 5033 case ISD::INTRINSIC_VOID: 5034 case ISD::INTRINSIC_W_CHAIN: { 5035 unsigned IID = cast<ConstantSDNode>(getOperand(1))->getZExtValue(); 5036 return Intrinsic::getName((Intrinsic::ID)IID); 5037 } 5038 5039 case ISD::BUILD_VECTOR: return "BUILD_VECTOR"; 5040 case ISD::TargetConstant: return "TargetConstant"; 5041 case ISD::TargetConstantFP:return "TargetConstantFP"; 5042 case ISD::TargetGlobalAddress: return "TargetGlobalAddress"; 5043 case ISD::TargetGlobalTLSAddress: return "TargetGlobalTLSAddress"; 5044 case ISD::TargetFrameIndex: return "TargetFrameIndex"; 5045 case ISD::TargetJumpTable: return "TargetJumpTable"; 5046 case ISD::TargetConstantPool: return "TargetConstantPool"; 5047 case ISD::TargetExternalSymbol: return "TargetExternalSymbol"; 5048 5049 case ISD::CopyToReg: return "CopyToReg"; 5050 case ISD::CopyFromReg: return "CopyFromReg"; 5051 case ISD::UNDEF: return "undef"; 5052 case ISD::MERGE_VALUES: return "merge_values"; 5053 case ISD::INLINEASM: return "inlineasm"; 5054 case ISD::DBG_LABEL: return "dbg_label"; 5055 case ISD::EH_LABEL: return "eh_label"; 5056 case ISD::DECLARE: return "declare"; 5057 case ISD::HANDLENODE: return "handlenode"; 5058 case ISD::FORMAL_ARGUMENTS: return "formal_arguments"; 5059 case ISD::CALL: return "call"; 5060 5061 // Unary operators 5062 case ISD::FABS: return "fabs"; 5063 case ISD::FNEG: return "fneg"; 5064 case ISD::FSQRT: return "fsqrt"; 5065 case ISD::FSIN: return "fsin"; 5066 case ISD::FCOS: return "fcos"; 5067 case ISD::FPOWI: return "fpowi"; 5068 case ISD::FPOW: return "fpow"; 5069 case ISD::FTRUNC: return "ftrunc"; 5070 case ISD::FFLOOR: return "ffloor"; 5071 case ISD::FCEIL: return "fceil"; 5072 case ISD::FRINT: return "frint"; 5073 case ISD::FNEARBYINT: return "fnearbyint"; 5074 5075 // Binary operators 5076 case ISD::ADD: return "add"; 5077 case ISD::SUB: return "sub"; 5078 case ISD::MUL: return "mul"; 5079 case ISD::MULHU: return "mulhu"; 5080 case ISD::MULHS: return "mulhs"; 5081 case ISD::SDIV: return "sdiv"; 5082 case ISD::UDIV: return "udiv"; 5083 case ISD::SREM: return "srem"; 5084 case ISD::UREM: return "urem"; 5085 case ISD::SMUL_LOHI: return "smul_lohi"; 5086 case ISD::UMUL_LOHI: return "umul_lohi"; 5087 case ISD::SDIVREM: return "sdivrem"; 5088 case ISD::UDIVREM: return "udivrem"; 5089 case ISD::AND: return "and"; 5090 case ISD::OR: return "or"; 5091 case ISD::XOR: return "xor"; 5092 case ISD::SHL: return "shl"; 5093 case ISD::SRA: return "sra"; 5094 case ISD::SRL: return "srl"; 5095 case ISD::ROTL: return "rotl"; 5096 case ISD::ROTR: return "rotr"; 5097 case ISD::FADD: return "fadd"; 5098 case ISD::FSUB: return "fsub"; 5099 case ISD::FMUL: return "fmul"; 5100 case ISD::FDIV: return "fdiv"; 5101 case ISD::FREM: return "frem"; 5102 case ISD::FCOPYSIGN: return "fcopysign"; 5103 case ISD::FGETSIGN: return "fgetsign"; 5104 5105 case ISD::SETCC: return "setcc"; 5106 case ISD::VSETCC: return "vsetcc"; 5107 case ISD::SELECT: return "select"; 5108 case ISD::SELECT_CC: return "select_cc"; 5109 case ISD::INSERT_VECTOR_ELT: return "insert_vector_elt"; 5110 case ISD::EXTRACT_VECTOR_ELT: return "extract_vector_elt"; 5111 case ISD::CONCAT_VECTORS: return "concat_vectors"; 5112 case ISD::EXTRACT_SUBVECTOR: return "extract_subvector"; 5113 case ISD::SCALAR_TO_VECTOR: return "scalar_to_vector"; 5114 case ISD::VECTOR_SHUFFLE: return "vector_shuffle"; 5115 case ISD::CARRY_FALSE: return "carry_false"; 5116 case ISD::ADDC: return "addc"; 5117 case ISD::ADDE: return "adde"; 5118 case ISD::SUBC: return "subc"; 5119 case ISD::SUBE: return "sube"; 5120 case ISD::SHL_PARTS: return "shl_parts"; 5121 case ISD::SRA_PARTS: return "sra_parts"; 5122 case ISD::SRL_PARTS: return "srl_parts"; 5123 5124 case ISD::EXTRACT_SUBREG: return "extract_subreg"; 5125 case ISD::INSERT_SUBREG: return "insert_subreg"; 5126 5127 // Conversion operators. 5128 case ISD::SIGN_EXTEND: return "sign_extend"; 5129 case ISD::ZERO_EXTEND: return "zero_extend"; 5130 case ISD::ANY_EXTEND: return "any_extend"; 5131 case ISD::SIGN_EXTEND_INREG: return "sign_extend_inreg"; 5132 case ISD::TRUNCATE: return "truncate"; 5133 case ISD::FP_ROUND: return "fp_round"; 5134 case ISD::FLT_ROUNDS_: return "flt_rounds"; 5135 case ISD::FP_ROUND_INREG: return "fp_round_inreg"; 5136 case ISD::FP_EXTEND: return "fp_extend"; 5137 5138 case ISD::SINT_TO_FP: return "sint_to_fp"; 5139 case ISD::UINT_TO_FP: return "uint_to_fp"; 5140 case ISD::FP_TO_SINT: return "fp_to_sint"; 5141 case ISD::FP_TO_UINT: return "fp_to_uint"; 5142 case ISD::BIT_CONVERT: return "bit_convert"; 5143 5144 // Control flow instructions 5145 case ISD::BR: return "br"; 5146 case ISD::BRIND: return "brind"; 5147 case ISD::BR_JT: return "br_jt"; 5148 case ISD::BRCOND: return "brcond"; 5149 case ISD::BR_CC: return "br_cc"; 5150 case ISD::RET: return "ret"; 5151 case ISD::CALLSEQ_START: return "callseq_start"; 5152 case ISD::CALLSEQ_END: return "callseq_end"; 5153 5154 // Other operators 5155 case ISD::LOAD: return "load"; 5156 case ISD::STORE: return "store"; 5157 case ISD::VAARG: return "vaarg"; 5158 case ISD::VACOPY: return "vacopy"; 5159 case ISD::VAEND: return "vaend"; 5160 case ISD::VASTART: return "vastart"; 5161 case ISD::DYNAMIC_STACKALLOC: return "dynamic_stackalloc"; 5162 case ISD::EXTRACT_ELEMENT: return "extract_element"; 5163 case ISD::BUILD_PAIR: return "build_pair"; 5164 case ISD::STACKSAVE: return "stacksave"; 5165 case ISD::STACKRESTORE: return "stackrestore"; 5166 case ISD::TRAP: return "trap"; 5167 5168 // Bit manipulation 5169 case ISD::BSWAP: return "bswap"; 5170 case ISD::CTPOP: return "ctpop"; 5171 case ISD::CTTZ: return "cttz"; 5172 case ISD::CTLZ: return "ctlz"; 5173 5174 // Debug info 5175 case ISD::DBG_STOPPOINT: return "dbg_stoppoint"; 5176 case ISD::DEBUG_LOC: return "debug_loc"; 5177 5178 // Trampolines 5179 case ISD::TRAMPOLINE: return "trampoline"; 5180 5181 case ISD::CONDCODE: 5182 switch (cast<CondCodeSDNode>(this)->get()) { 5183 default: assert(0 && "Unknown setcc condition!"); 5184 case ISD::SETOEQ: return "setoeq"; 5185 case ISD::SETOGT: return "setogt"; 5186 case ISD::SETOGE: return "setoge"; 5187 case ISD::SETOLT: return "setolt"; 5188 case ISD::SETOLE: return "setole"; 5189 case ISD::SETONE: return "setone"; 5190 5191 case ISD::SETO: return "seto"; 5192 case ISD::SETUO: return "setuo"; 5193 case ISD::SETUEQ: return "setue"; 5194 case ISD::SETUGT: return "setugt"; 5195 case ISD::SETUGE: return "setuge"; 5196 case ISD::SETULT: return "setult"; 5197 case ISD::SETULE: return "setule"; 5198 case ISD::SETUNE: return "setune"; 5199 5200 case ISD::SETEQ: return "seteq"; 5201 case ISD::SETGT: return "setgt"; 5202 case ISD::SETGE: return "setge"; 5203 case ISD::SETLT: return "setlt"; 5204 case ISD::SETLE: return "setle"; 5205 case ISD::SETNE: return "setne"; 5206 } 5207 } 5208} 5209 5210const char *SDNode::getIndexedModeName(ISD::MemIndexedMode AM) { 5211 switch (AM) { 5212 default: 5213 return ""; 5214 case ISD::PRE_INC: 5215 return "<pre-inc>"; 5216 case ISD::PRE_DEC: 5217 return "<pre-dec>"; 5218 case ISD::POST_INC: 5219 return "<post-inc>"; 5220 case ISD::POST_DEC: 5221 return "<post-dec>"; 5222 } 5223} 5224 5225std::string ISD::ArgFlagsTy::getArgFlagsString() { 5226 std::string S = "< "; 5227 5228 if (isZExt()) 5229 S += "zext "; 5230 if (isSExt()) 5231 S += "sext "; 5232 if (isInReg()) 5233 S += "inreg "; 5234 if (isSRet()) 5235 S += "sret "; 5236 if (isByVal()) 5237 S += "byval "; 5238 if (isNest()) 5239 S += "nest "; 5240 if (getByValAlign()) 5241 S += "byval-align:" + utostr(getByValAlign()) + " "; 5242 if (getOrigAlign()) 5243 S += "orig-align:" + utostr(getOrigAlign()) + " "; 5244 if (getByValSize()) 5245 S += "byval-size:" + utostr(getByValSize()) + " "; 5246 return S + ">"; 5247} 5248 5249void SDNode::dump() const { dump(0); } 5250void SDNode::dump(const SelectionDAG *G) const { 5251 print(errs(), G); 5252 errs().flush(); 5253} 5254 5255void SDNode::print(raw_ostream &OS, const SelectionDAG *G) const { 5256 OS << (void*)this << ": "; 5257 5258 for (unsigned i = 0, e = getNumValues(); i != e; ++i) { 5259 if (i) OS << ","; 5260 if (getValueType(i) == MVT::Other) 5261 OS << "ch"; 5262 else 5263 OS << getValueType(i).getMVTString(); 5264 } 5265 OS << " = " << getOperationName(G); 5266 5267 OS << " "; 5268 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 5269 if (i) OS << ", "; 5270 OS << (void*)getOperand(i).getNode(); 5271 if (unsigned RN = getOperand(i).getResNo()) 5272 OS << ":" << RN; 5273 } 5274 5275 if (!isTargetOpcode() && getOpcode() == ISD::VECTOR_SHUFFLE) { 5276 SDNode *Mask = getOperand(2).getNode(); 5277 OS << "<"; 5278 for (unsigned i = 0, e = Mask->getNumOperands(); i != e; ++i) { 5279 if (i) OS << ","; 5280 if (Mask->getOperand(i).getOpcode() == ISD::UNDEF) 5281 OS << "u"; 5282 else 5283 OS << cast<ConstantSDNode>(Mask->getOperand(i))->getZExtValue(); 5284 } 5285 OS << ">"; 5286 } 5287 5288 if (const ConstantSDNode *CSDN = dyn_cast<ConstantSDNode>(this)) { 5289 OS << '<' << CSDN->getAPIntValue() << '>'; 5290 } else if (const ConstantFPSDNode *CSDN = dyn_cast<ConstantFPSDNode>(this)) { 5291 if (&CSDN->getValueAPF().getSemantics()==&APFloat::IEEEsingle) 5292 OS << '<' << CSDN->getValueAPF().convertToFloat() << '>'; 5293 else if (&CSDN->getValueAPF().getSemantics()==&APFloat::IEEEdouble) 5294 OS << '<' << CSDN->getValueAPF().convertToDouble() << '>'; 5295 else { 5296 OS << "<APFloat("; 5297 CSDN->getValueAPF().bitcastToAPInt().dump(); 5298 OS << ")>"; 5299 } 5300 } else if (const GlobalAddressSDNode *GADN = 5301 dyn_cast<GlobalAddressSDNode>(this)) { 5302 int64_t offset = GADN->getOffset(); 5303 OS << '<'; 5304 WriteAsOperand(OS, GADN->getGlobal()); 5305 OS << '>'; 5306 if (offset > 0) 5307 OS << " + " << offset; 5308 else 5309 OS << " " << offset; 5310 } else if (const FrameIndexSDNode *FIDN = dyn_cast<FrameIndexSDNode>(this)) { 5311 OS << "<" << FIDN->getIndex() << ">"; 5312 } else if (const JumpTableSDNode *JTDN = dyn_cast<JumpTableSDNode>(this)) { 5313 OS << "<" << JTDN->getIndex() << ">"; 5314 } else if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(this)){ 5315 int offset = CP->getOffset(); 5316 if (CP->isMachineConstantPoolEntry()) 5317 OS << "<" << *CP->getMachineCPVal() << ">"; 5318 else 5319 OS << "<" << *CP->getConstVal() << ">"; 5320 if (offset > 0) 5321 OS << " + " << offset; 5322 else 5323 OS << " " << offset; 5324 } else if (const BasicBlockSDNode *BBDN = dyn_cast<BasicBlockSDNode>(this)) { 5325 OS << "<"; 5326 const Value *LBB = (const Value*)BBDN->getBasicBlock()->getBasicBlock(); 5327 if (LBB) 5328 OS << LBB->getName() << " "; 5329 OS << (const void*)BBDN->getBasicBlock() << ">"; 5330 } else if (const RegisterSDNode *R = dyn_cast<RegisterSDNode>(this)) { 5331 if (G && R->getReg() && 5332 TargetRegisterInfo::isPhysicalRegister(R->getReg())) { 5333 OS << " " << G->getTarget().getRegisterInfo()->getName(R->getReg()); 5334 } else { 5335 OS << " #" << R->getReg(); 5336 } 5337 } else if (const ExternalSymbolSDNode *ES = 5338 dyn_cast<ExternalSymbolSDNode>(this)) { 5339 OS << "'" << ES->getSymbol() << "'"; 5340 } else if (const SrcValueSDNode *M = dyn_cast<SrcValueSDNode>(this)) { 5341 if (M->getValue()) 5342 OS << "<" << M->getValue() << ">"; 5343 else 5344 OS << "<null>"; 5345 } else if (const MemOperandSDNode *M = dyn_cast<MemOperandSDNode>(this)) { 5346 if (M->MO.getValue()) 5347 OS << "<" << M->MO.getValue() << ":" << M->MO.getOffset() << ">"; 5348 else 5349 OS << "<null:" << M->MO.getOffset() << ">"; 5350 } else if (const ARG_FLAGSSDNode *N = dyn_cast<ARG_FLAGSSDNode>(this)) { 5351 OS << N->getArgFlags().getArgFlagsString(); 5352 } else if (const VTSDNode *N = dyn_cast<VTSDNode>(this)) { 5353 OS << ":" << N->getVT().getMVTString(); 5354 } 5355 else if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(this)) { 5356 const Value *SrcValue = LD->getSrcValue(); 5357 int SrcOffset = LD->getSrcValueOffset(); 5358 OS << " <"; 5359 if (SrcValue) 5360 OS << SrcValue; 5361 else 5362 OS << "null"; 5363 OS << ":" << SrcOffset << ">"; 5364 5365 bool doExt = true; 5366 switch (LD->getExtensionType()) { 5367 default: doExt = false; break; 5368 case ISD::EXTLOAD: OS << " <anyext "; break; 5369 case ISD::SEXTLOAD: OS << " <sext "; break; 5370 case ISD::ZEXTLOAD: OS << " <zext "; break; 5371 } 5372 if (doExt) 5373 OS << LD->getMemoryVT().getMVTString() << ">"; 5374 5375 const char *AM = getIndexedModeName(LD->getAddressingMode()); 5376 if (*AM) 5377 OS << " " << AM; 5378 if (LD->isVolatile()) 5379 OS << " <volatile>"; 5380 OS << " alignment=" << LD->getAlignment(); 5381 } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(this)) { 5382 const Value *SrcValue = ST->getSrcValue(); 5383 int SrcOffset = ST->getSrcValueOffset(); 5384 OS << " <"; 5385 if (SrcValue) 5386 OS << SrcValue; 5387 else 5388 OS << "null"; 5389 OS << ":" << SrcOffset << ">"; 5390 5391 if (ST->isTruncatingStore()) 5392 OS << " <trunc " << ST->getMemoryVT().getMVTString() << ">"; 5393 5394 const char *AM = getIndexedModeName(ST->getAddressingMode()); 5395 if (*AM) 5396 OS << " " << AM; 5397 if (ST->isVolatile()) 5398 OS << " <volatile>"; 5399 OS << " alignment=" << ST->getAlignment(); 5400 } else if (const AtomicSDNode* AT = dyn_cast<AtomicSDNode>(this)) { 5401 const Value *SrcValue = AT->getSrcValue(); 5402 int SrcOffset = AT->getSrcValueOffset(); 5403 OS << " <"; 5404 if (SrcValue) 5405 OS << SrcValue; 5406 else 5407 OS << "null"; 5408 OS << ":" << SrcOffset << ">"; 5409 if (AT->isVolatile()) 5410 OS << " <volatile>"; 5411 OS << " alignment=" << AT->getAlignment(); 5412 } 5413} 5414 5415static void DumpNodes(const SDNode *N, unsigned indent, const SelectionDAG *G) { 5416 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 5417 if (N->getOperand(i).getNode()->hasOneUse()) 5418 DumpNodes(N->getOperand(i).getNode(), indent+2, G); 5419 else 5420 cerr << "\n" << std::string(indent+2, ' ') 5421 << (void*)N->getOperand(i).getNode() << ": <multiple use>"; 5422 5423 5424 cerr << "\n" << std::string(indent, ' '); 5425 N->dump(G); 5426} 5427 5428void SelectionDAG::dump() const { 5429 cerr << "SelectionDAG has " << AllNodes.size() << " nodes:"; 5430 5431 for (allnodes_const_iterator I = allnodes_begin(), E = allnodes_end(); 5432 I != E; ++I) { 5433 const SDNode *N = I; 5434 if (!N->hasOneUse() && N != getRoot().getNode()) 5435 DumpNodes(N, 2, this); 5436 } 5437 5438 if (getRoot().getNode()) DumpNodes(getRoot().getNode(), 2, this); 5439 5440 cerr << "\n\n"; 5441} 5442 5443const Type *ConstantPoolSDNode::getType() const { 5444 if (isMachineConstantPoolEntry()) 5445 return Val.MachineCPVal->getType(); 5446 return Val.ConstVal->getType(); 5447} 5448