SelectionDAG.cpp revision 206ad10c14e5dda3bf7b2dc8faf84b2f75124844
1//===-- SelectionDAG.cpp - Implement the SelectionDAG data structures -----===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAG class. 11// 12//===----------------------------------------------------------------------===// 13#include "llvm/CodeGen/SelectionDAG.h" 14#include "llvm/Constants.h" 15#include "llvm/Analysis/ValueTracking.h" 16#include "llvm/GlobalAlias.h" 17#include "llvm/GlobalVariable.h" 18#include "llvm/Intrinsics.h" 19#include "llvm/DerivedTypes.h" 20#include "llvm/Assembly/Writer.h" 21#include "llvm/CallingConv.h" 22#include "llvm/CodeGen/MachineBasicBlock.h" 23#include "llvm/CodeGen/MachineConstantPool.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/MachineModuleInfo.h" 26#include "llvm/CodeGen/PseudoSourceValue.h" 27#include "llvm/Target/TargetRegisterInfo.h" 28#include "llvm/Target/TargetData.h" 29#include "llvm/Target/TargetLowering.h" 30#include "llvm/Target/TargetOptions.h" 31#include "llvm/Target/TargetInstrInfo.h" 32#include "llvm/Target/TargetMachine.h" 33#include "llvm/Support/CommandLine.h" 34#include "llvm/Support/ErrorHandling.h" 35#include "llvm/Support/ManagedStatic.h" 36#include "llvm/Support/MathExtras.h" 37#include "llvm/Support/raw_ostream.h" 38#include "llvm/System/Mutex.h" 39#include "llvm/ADT/SetVector.h" 40#include "llvm/ADT/SmallPtrSet.h" 41#include "llvm/ADT/SmallSet.h" 42#include "llvm/ADT/SmallVector.h" 43#include "llvm/ADT/StringExtras.h" 44#include <algorithm> 45#include <cmath> 46using namespace llvm; 47 48/// makeVTList - Return an instance of the SDVTList struct initialized with the 49/// specified members. 50static SDVTList makeVTList(const MVT *VTs, unsigned NumVTs) { 51 SDVTList Res = {VTs, NumVTs}; 52 return Res; 53} 54 55static const fltSemantics *MVTToAPFloatSemantics(MVT VT) { 56 switch (VT.getSimpleVT()) { 57 default: llvm_unreachable("Unknown FP format"); 58 case MVT::f32: return &APFloat::IEEEsingle; 59 case MVT::f64: return &APFloat::IEEEdouble; 60 case MVT::f80: return &APFloat::x87DoubleExtended; 61 case MVT::f128: return &APFloat::IEEEquad; 62 case MVT::ppcf128: return &APFloat::PPCDoubleDouble; 63 } 64} 65 66SelectionDAG::DAGUpdateListener::~DAGUpdateListener() {} 67 68//===----------------------------------------------------------------------===// 69// ConstantFPSDNode Class 70//===----------------------------------------------------------------------===// 71 72/// isExactlyValue - We don't rely on operator== working on double values, as 73/// it returns true for things that are clearly not equal, like -0.0 and 0.0. 74/// As such, this method can be used to do an exact bit-for-bit comparison of 75/// two floating point values. 76bool ConstantFPSDNode::isExactlyValue(const APFloat& V) const { 77 return getValueAPF().bitwiseIsEqual(V); 78} 79 80bool ConstantFPSDNode::isValueValidForType(MVT VT, 81 const APFloat& Val) { 82 assert(VT.isFloatingPoint() && "Can only convert between FP types"); 83 84 // PPC long double cannot be converted to any other type. 85 if (VT == MVT::ppcf128 || 86 &Val.getSemantics() == &APFloat::PPCDoubleDouble) 87 return false; 88 89 // convert modifies in place, so make a copy. 90 APFloat Val2 = APFloat(Val); 91 bool losesInfo; 92 (void) Val2.convert(*MVTToAPFloatSemantics(VT), APFloat::rmNearestTiesToEven, 93 &losesInfo); 94 return !losesInfo; 95} 96 97//===----------------------------------------------------------------------===// 98// ISD Namespace 99//===----------------------------------------------------------------------===// 100 101/// isBuildVectorAllOnes - Return true if the specified node is a 102/// BUILD_VECTOR where all of the elements are ~0 or undef. 103bool ISD::isBuildVectorAllOnes(const SDNode *N) { 104 // Look through a bit convert. 105 if (N->getOpcode() == ISD::BIT_CONVERT) 106 N = N->getOperand(0).getNode(); 107 108 if (N->getOpcode() != ISD::BUILD_VECTOR) return false; 109 110 unsigned i = 0, e = N->getNumOperands(); 111 112 // Skip over all of the undef values. 113 while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF) 114 ++i; 115 116 // Do not accept an all-undef vector. 117 if (i == e) return false; 118 119 // Do not accept build_vectors that aren't all constants or which have non-~0 120 // elements. 121 SDValue NotZero = N->getOperand(i); 122 if (isa<ConstantSDNode>(NotZero)) { 123 if (!cast<ConstantSDNode>(NotZero)->isAllOnesValue()) 124 return false; 125 } else if (isa<ConstantFPSDNode>(NotZero)) { 126 if (!cast<ConstantFPSDNode>(NotZero)->getValueAPF(). 127 bitcastToAPInt().isAllOnesValue()) 128 return false; 129 } else 130 return false; 131 132 // Okay, we have at least one ~0 value, check to see if the rest match or are 133 // undefs. 134 for (++i; i != e; ++i) 135 if (N->getOperand(i) != NotZero && 136 N->getOperand(i).getOpcode() != ISD::UNDEF) 137 return false; 138 return true; 139} 140 141 142/// isBuildVectorAllZeros - Return true if the specified node is a 143/// BUILD_VECTOR where all of the elements are 0 or undef. 144bool ISD::isBuildVectorAllZeros(const SDNode *N) { 145 // Look through a bit convert. 146 if (N->getOpcode() == ISD::BIT_CONVERT) 147 N = N->getOperand(0).getNode(); 148 149 if (N->getOpcode() != ISD::BUILD_VECTOR) return false; 150 151 unsigned i = 0, e = N->getNumOperands(); 152 153 // Skip over all of the undef values. 154 while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF) 155 ++i; 156 157 // Do not accept an all-undef vector. 158 if (i == e) return false; 159 160 // Do not accept build_vectors that aren't all constants or which have non-0 161 // elements. 162 SDValue Zero = N->getOperand(i); 163 if (isa<ConstantSDNode>(Zero)) { 164 if (!cast<ConstantSDNode>(Zero)->isNullValue()) 165 return false; 166 } else if (isa<ConstantFPSDNode>(Zero)) { 167 if (!cast<ConstantFPSDNode>(Zero)->getValueAPF().isPosZero()) 168 return false; 169 } else 170 return false; 171 172 // Okay, we have at least one 0 value, check to see if the rest match or are 173 // undefs. 174 for (++i; i != e; ++i) 175 if (N->getOperand(i) != Zero && 176 N->getOperand(i).getOpcode() != ISD::UNDEF) 177 return false; 178 return true; 179} 180 181/// isScalarToVector - Return true if the specified node is a 182/// ISD::SCALAR_TO_VECTOR node or a BUILD_VECTOR node where only the low 183/// element is not an undef. 184bool ISD::isScalarToVector(const SDNode *N) { 185 if (N->getOpcode() == ISD::SCALAR_TO_VECTOR) 186 return true; 187 188 if (N->getOpcode() != ISD::BUILD_VECTOR) 189 return false; 190 if (N->getOperand(0).getOpcode() == ISD::UNDEF) 191 return false; 192 unsigned NumElems = N->getNumOperands(); 193 for (unsigned i = 1; i < NumElems; ++i) { 194 SDValue V = N->getOperand(i); 195 if (V.getOpcode() != ISD::UNDEF) 196 return false; 197 } 198 return true; 199} 200 201 202/// isDebugLabel - Return true if the specified node represents a debug 203/// label (i.e. ISD::DBG_LABEL or TargetInstrInfo::DBG_LABEL node). 204bool ISD::isDebugLabel(const SDNode *N) { 205 SDValue Zero; 206 if (N->getOpcode() == ISD::DBG_LABEL) 207 return true; 208 if (N->isMachineOpcode() && 209 N->getMachineOpcode() == TargetInstrInfo::DBG_LABEL) 210 return true; 211 return false; 212} 213 214/// getSetCCSwappedOperands - Return the operation corresponding to (Y op X) 215/// when given the operation for (X op Y). 216ISD::CondCode ISD::getSetCCSwappedOperands(ISD::CondCode Operation) { 217 // To perform this operation, we just need to swap the L and G bits of the 218 // operation. 219 unsigned OldL = (Operation >> 2) & 1; 220 unsigned OldG = (Operation >> 1) & 1; 221 return ISD::CondCode((Operation & ~6) | // Keep the N, U, E bits 222 (OldL << 1) | // New G bit 223 (OldG << 2)); // New L bit. 224} 225 226/// getSetCCInverse - Return the operation corresponding to !(X op Y), where 227/// 'op' is a valid SetCC operation. 228ISD::CondCode ISD::getSetCCInverse(ISD::CondCode Op, bool isInteger) { 229 unsigned Operation = Op; 230 if (isInteger) 231 Operation ^= 7; // Flip L, G, E bits, but not U. 232 else 233 Operation ^= 15; // Flip all of the condition bits. 234 235 if (Operation > ISD::SETTRUE2) 236 Operation &= ~8; // Don't let N and U bits get set. 237 238 return ISD::CondCode(Operation); 239} 240 241 242/// isSignedOp - For an integer comparison, return 1 if the comparison is a 243/// signed operation and 2 if the result is an unsigned comparison. Return zero 244/// if the operation does not depend on the sign of the input (setne and seteq). 245static int isSignedOp(ISD::CondCode Opcode) { 246 switch (Opcode) { 247 default: llvm_unreachable("Illegal integer setcc operation!"); 248 case ISD::SETEQ: 249 case ISD::SETNE: return 0; 250 case ISD::SETLT: 251 case ISD::SETLE: 252 case ISD::SETGT: 253 case ISD::SETGE: return 1; 254 case ISD::SETULT: 255 case ISD::SETULE: 256 case ISD::SETUGT: 257 case ISD::SETUGE: return 2; 258 } 259} 260 261/// getSetCCOrOperation - Return the result of a logical OR between different 262/// comparisons of identical values: ((X op1 Y) | (X op2 Y)). This function 263/// returns SETCC_INVALID if it is not possible to represent the resultant 264/// comparison. 265ISD::CondCode ISD::getSetCCOrOperation(ISD::CondCode Op1, ISD::CondCode Op2, 266 bool isInteger) { 267 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 268 // Cannot fold a signed integer setcc with an unsigned integer setcc. 269 return ISD::SETCC_INVALID; 270 271 unsigned Op = Op1 | Op2; // Combine all of the condition bits. 272 273 // If the N and U bits get set then the resultant comparison DOES suddenly 274 // care about orderedness, and is true when ordered. 275 if (Op > ISD::SETTRUE2) 276 Op &= ~16; // Clear the U bit if the N bit is set. 277 278 // Canonicalize illegal integer setcc's. 279 if (isInteger && Op == ISD::SETUNE) // e.g. SETUGT | SETULT 280 Op = ISD::SETNE; 281 282 return ISD::CondCode(Op); 283} 284 285/// getSetCCAndOperation - Return the result of a logical AND between different 286/// comparisons of identical values: ((X op1 Y) & (X op2 Y)). This 287/// function returns zero if it is not possible to represent the resultant 288/// comparison. 289ISD::CondCode ISD::getSetCCAndOperation(ISD::CondCode Op1, ISD::CondCode Op2, 290 bool isInteger) { 291 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 292 // Cannot fold a signed setcc with an unsigned setcc. 293 return ISD::SETCC_INVALID; 294 295 // Combine all of the condition bits. 296 ISD::CondCode Result = ISD::CondCode(Op1 & Op2); 297 298 // Canonicalize illegal integer setcc's. 299 if (isInteger) { 300 switch (Result) { 301 default: break; 302 case ISD::SETUO : Result = ISD::SETFALSE; break; // SETUGT & SETULT 303 case ISD::SETOEQ: // SETEQ & SETU[LG]E 304 case ISD::SETUEQ: Result = ISD::SETEQ ; break; // SETUGE & SETULE 305 case ISD::SETOLT: Result = ISD::SETULT ; break; // SETULT & SETNE 306 case ISD::SETOGT: Result = ISD::SETUGT ; break; // SETUGT & SETNE 307 } 308 } 309 310 return Result; 311} 312 313const TargetMachine &SelectionDAG::getTarget() const { 314 return MF->getTarget(); 315} 316 317//===----------------------------------------------------------------------===// 318// SDNode Profile Support 319//===----------------------------------------------------------------------===// 320 321/// AddNodeIDOpcode - Add the node opcode to the NodeID data. 322/// 323static void AddNodeIDOpcode(FoldingSetNodeID &ID, unsigned OpC) { 324 ID.AddInteger(OpC); 325} 326 327/// AddNodeIDValueTypes - Value type lists are intern'd so we can represent them 328/// solely with their pointer. 329static void AddNodeIDValueTypes(FoldingSetNodeID &ID, SDVTList VTList) { 330 ID.AddPointer(VTList.VTs); 331} 332 333/// AddNodeIDOperands - Various routines for adding operands to the NodeID data. 334/// 335static void AddNodeIDOperands(FoldingSetNodeID &ID, 336 const SDValue *Ops, unsigned NumOps) { 337 for (; NumOps; --NumOps, ++Ops) { 338 ID.AddPointer(Ops->getNode()); 339 ID.AddInteger(Ops->getResNo()); 340 } 341} 342 343/// AddNodeIDOperands - Various routines for adding operands to the NodeID data. 344/// 345static void AddNodeIDOperands(FoldingSetNodeID &ID, 346 const SDUse *Ops, unsigned NumOps) { 347 for (; NumOps; --NumOps, ++Ops) { 348 ID.AddPointer(Ops->getNode()); 349 ID.AddInteger(Ops->getResNo()); 350 } 351} 352 353static void AddNodeIDNode(FoldingSetNodeID &ID, 354 unsigned short OpC, SDVTList VTList, 355 const SDValue *OpList, unsigned N) { 356 AddNodeIDOpcode(ID, OpC); 357 AddNodeIDValueTypes(ID, VTList); 358 AddNodeIDOperands(ID, OpList, N); 359} 360 361/// AddNodeIDCustom - If this is an SDNode with special info, add this info to 362/// the NodeID data. 363static void AddNodeIDCustom(FoldingSetNodeID &ID, const SDNode *N) { 364 switch (N->getOpcode()) { 365 case ISD::TargetExternalSymbol: 366 case ISD::ExternalSymbol: 367 llvm_unreachable("Should only be used on nodes with operands"); 368 default: break; // Normal nodes don't need extra info. 369 case ISD::ARG_FLAGS: 370 ID.AddInteger(cast<ARG_FLAGSSDNode>(N)->getArgFlags().getRawBits()); 371 break; 372 case ISD::TargetConstant: 373 case ISD::Constant: 374 ID.AddPointer(cast<ConstantSDNode>(N)->getConstantIntValue()); 375 break; 376 case ISD::TargetConstantFP: 377 case ISD::ConstantFP: { 378 ID.AddPointer(cast<ConstantFPSDNode>(N)->getConstantFPValue()); 379 break; 380 } 381 case ISD::TargetGlobalAddress: 382 case ISD::GlobalAddress: 383 case ISD::TargetGlobalTLSAddress: 384 case ISD::GlobalTLSAddress: { 385 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(N); 386 ID.AddPointer(GA->getGlobal()); 387 ID.AddInteger(GA->getOffset()); 388 ID.AddInteger(GA->getTargetFlags()); 389 break; 390 } 391 case ISD::BasicBlock: 392 ID.AddPointer(cast<BasicBlockSDNode>(N)->getBasicBlock()); 393 break; 394 case ISD::Register: 395 ID.AddInteger(cast<RegisterSDNode>(N)->getReg()); 396 break; 397 case ISD::DBG_STOPPOINT: { 398 const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(N); 399 ID.AddInteger(DSP->getLine()); 400 ID.AddInteger(DSP->getColumn()); 401 ID.AddPointer(DSP->getCompileUnit()); 402 break; 403 } 404 case ISD::SRCVALUE: 405 ID.AddPointer(cast<SrcValueSDNode>(N)->getValue()); 406 break; 407 case ISD::MEMOPERAND: { 408 const MachineMemOperand &MO = cast<MemOperandSDNode>(N)->MO; 409 MO.Profile(ID); 410 break; 411 } 412 case ISD::FrameIndex: 413 case ISD::TargetFrameIndex: 414 ID.AddInteger(cast<FrameIndexSDNode>(N)->getIndex()); 415 break; 416 case ISD::JumpTable: 417 case ISD::TargetJumpTable: 418 ID.AddInteger(cast<JumpTableSDNode>(N)->getIndex()); 419 ID.AddInteger(cast<JumpTableSDNode>(N)->getTargetFlags()); 420 break; 421 case ISD::ConstantPool: 422 case ISD::TargetConstantPool: { 423 const ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(N); 424 ID.AddInteger(CP->getAlignment()); 425 ID.AddInteger(CP->getOffset()); 426 if (CP->isMachineConstantPoolEntry()) 427 CP->getMachineCPVal()->AddSelectionDAGCSEId(ID); 428 else 429 ID.AddPointer(CP->getConstVal()); 430 ID.AddInteger(CP->getTargetFlags()); 431 break; 432 } 433 case ISD::CALL: { 434 const CallSDNode *Call = cast<CallSDNode>(N); 435 ID.AddInteger(Call->getCallingConv()); 436 ID.AddInteger(Call->isVarArg()); 437 break; 438 } 439 case ISD::LOAD: { 440 const LoadSDNode *LD = cast<LoadSDNode>(N); 441 ID.AddInteger(LD->getMemoryVT().getRawBits()); 442 ID.AddInteger(LD->getRawSubclassData()); 443 break; 444 } 445 case ISD::STORE: { 446 const StoreSDNode *ST = cast<StoreSDNode>(N); 447 ID.AddInteger(ST->getMemoryVT().getRawBits()); 448 ID.AddInteger(ST->getRawSubclassData()); 449 break; 450 } 451 case ISD::ATOMIC_CMP_SWAP: 452 case ISD::ATOMIC_SWAP: 453 case ISD::ATOMIC_LOAD_ADD: 454 case ISD::ATOMIC_LOAD_SUB: 455 case ISD::ATOMIC_LOAD_AND: 456 case ISD::ATOMIC_LOAD_OR: 457 case ISD::ATOMIC_LOAD_XOR: 458 case ISD::ATOMIC_LOAD_NAND: 459 case ISD::ATOMIC_LOAD_MIN: 460 case ISD::ATOMIC_LOAD_MAX: 461 case ISD::ATOMIC_LOAD_UMIN: 462 case ISD::ATOMIC_LOAD_UMAX: { 463 const AtomicSDNode *AT = cast<AtomicSDNode>(N); 464 ID.AddInteger(AT->getMemoryVT().getRawBits()); 465 ID.AddInteger(AT->getRawSubclassData()); 466 break; 467 } 468 case ISD::VECTOR_SHUFFLE: { 469 const ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N); 470 for (unsigned i = 0, e = N->getValueType(0).getVectorNumElements(); 471 i != e; ++i) 472 ID.AddInteger(SVN->getMaskElt(i)); 473 break; 474 } 475 } // end switch (N->getOpcode()) 476} 477 478/// AddNodeIDNode - Generic routine for adding a nodes info to the NodeID 479/// data. 480static void AddNodeIDNode(FoldingSetNodeID &ID, const SDNode *N) { 481 AddNodeIDOpcode(ID, N->getOpcode()); 482 // Add the return value info. 483 AddNodeIDValueTypes(ID, N->getVTList()); 484 // Add the operand info. 485 AddNodeIDOperands(ID, N->op_begin(), N->getNumOperands()); 486 487 // Handle SDNode leafs with special info. 488 AddNodeIDCustom(ID, N); 489} 490 491/// encodeMemSDNodeFlags - Generic routine for computing a value for use in 492/// the CSE map that carries alignment, volatility, indexing mode, and 493/// extension/truncation information. 494/// 495static inline unsigned 496encodeMemSDNodeFlags(int ConvType, ISD::MemIndexedMode AM, 497 bool isVolatile, unsigned Alignment) { 498 assert((ConvType & 3) == ConvType && 499 "ConvType may not require more than 2 bits!"); 500 assert((AM & 7) == AM && 501 "AM may not require more than 3 bits!"); 502 return ConvType | 503 (AM << 2) | 504 (isVolatile << 5) | 505 ((Log2_32(Alignment) + 1) << 6); 506} 507 508//===----------------------------------------------------------------------===// 509// SelectionDAG Class 510//===----------------------------------------------------------------------===// 511 512/// doNotCSE - Return true if CSE should not be performed for this node. 513static bool doNotCSE(SDNode *N) { 514 if (N->getValueType(0) == MVT::Flag) 515 return true; // Never CSE anything that produces a flag. 516 517 switch (N->getOpcode()) { 518 default: break; 519 case ISD::HANDLENODE: 520 case ISD::DBG_LABEL: 521 case ISD::DBG_STOPPOINT: 522 case ISD::EH_LABEL: 523 case ISD::DECLARE: 524 return true; // Never CSE these nodes. 525 } 526 527 // Check that remaining values produced are not flags. 528 for (unsigned i = 1, e = N->getNumValues(); i != e; ++i) 529 if (N->getValueType(i) == MVT::Flag) 530 return true; // Never CSE anything that produces a flag. 531 532 return false; 533} 534 535/// RemoveDeadNodes - This method deletes all unreachable nodes in the 536/// SelectionDAG. 537void SelectionDAG::RemoveDeadNodes() { 538 // Create a dummy node (which is not added to allnodes), that adds a reference 539 // to the root node, preventing it from being deleted. 540 HandleSDNode Dummy(getRoot()); 541 542 SmallVector<SDNode*, 128> DeadNodes; 543 544 // Add all obviously-dead nodes to the DeadNodes worklist. 545 for (allnodes_iterator I = allnodes_begin(), E = allnodes_end(); I != E; ++I) 546 if (I->use_empty()) 547 DeadNodes.push_back(I); 548 549 RemoveDeadNodes(DeadNodes); 550 551 // If the root changed (e.g. it was a dead load, update the root). 552 setRoot(Dummy.getValue()); 553} 554 555/// RemoveDeadNodes - This method deletes the unreachable nodes in the 556/// given list, and any nodes that become unreachable as a result. 557void SelectionDAG::RemoveDeadNodes(SmallVectorImpl<SDNode *> &DeadNodes, 558 DAGUpdateListener *UpdateListener) { 559 560 // Process the worklist, deleting the nodes and adding their uses to the 561 // worklist. 562 while (!DeadNodes.empty()) { 563 SDNode *N = DeadNodes.pop_back_val(); 564 565 if (UpdateListener) 566 UpdateListener->NodeDeleted(N, 0); 567 568 // Take the node out of the appropriate CSE map. 569 RemoveNodeFromCSEMaps(N); 570 571 // Next, brutally remove the operand list. This is safe to do, as there are 572 // no cycles in the graph. 573 for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ) { 574 SDUse &Use = *I++; 575 SDNode *Operand = Use.getNode(); 576 Use.set(SDValue()); 577 578 // Now that we removed this operand, see if there are no uses of it left. 579 if (Operand->use_empty()) 580 DeadNodes.push_back(Operand); 581 } 582 583 DeallocateNode(N); 584 } 585} 586 587void SelectionDAG::RemoveDeadNode(SDNode *N, DAGUpdateListener *UpdateListener){ 588 SmallVector<SDNode*, 16> DeadNodes(1, N); 589 RemoveDeadNodes(DeadNodes, UpdateListener); 590} 591 592void SelectionDAG::DeleteNode(SDNode *N) { 593 // First take this out of the appropriate CSE map. 594 RemoveNodeFromCSEMaps(N); 595 596 // Finally, remove uses due to operands of this node, remove from the 597 // AllNodes list, and delete the node. 598 DeleteNodeNotInCSEMaps(N); 599} 600 601void SelectionDAG::DeleteNodeNotInCSEMaps(SDNode *N) { 602 assert(N != AllNodes.begin() && "Cannot delete the entry node!"); 603 assert(N->use_empty() && "Cannot delete a node that is not dead!"); 604 605 // Drop all of the operands and decrement used node's use counts. 606 N->DropOperands(); 607 608 DeallocateNode(N); 609} 610 611void SelectionDAG::DeallocateNode(SDNode *N) { 612 if (N->OperandsNeedDelete) 613 delete[] N->OperandList; 614 615 // Set the opcode to DELETED_NODE to help catch bugs when node 616 // memory is reallocated. 617 N->NodeType = ISD::DELETED_NODE; 618 619 NodeAllocator.Deallocate(AllNodes.remove(N)); 620} 621 622/// RemoveNodeFromCSEMaps - Take the specified node out of the CSE map that 623/// correspond to it. This is useful when we're about to delete or repurpose 624/// the node. We don't want future request for structurally identical nodes 625/// to return N anymore. 626bool SelectionDAG::RemoveNodeFromCSEMaps(SDNode *N) { 627 bool Erased = false; 628 switch (N->getOpcode()) { 629 case ISD::EntryToken: 630 llvm_unreachable("EntryToken should not be in CSEMaps!"); 631 return false; 632 case ISD::HANDLENODE: return false; // noop. 633 case ISD::CONDCODE: 634 assert(CondCodeNodes[cast<CondCodeSDNode>(N)->get()] && 635 "Cond code doesn't exist!"); 636 Erased = CondCodeNodes[cast<CondCodeSDNode>(N)->get()] != 0; 637 CondCodeNodes[cast<CondCodeSDNode>(N)->get()] = 0; 638 break; 639 case ISD::ExternalSymbol: 640 Erased = ExternalSymbols.erase(cast<ExternalSymbolSDNode>(N)->getSymbol()); 641 break; 642 case ISD::TargetExternalSymbol: { 643 ExternalSymbolSDNode *ESN = cast<ExternalSymbolSDNode>(N); 644 Erased = TargetExternalSymbols.erase( 645 std::pair<std::string,unsigned char>(ESN->getSymbol(), 646 ESN->getTargetFlags())); 647 break; 648 } 649 case ISD::VALUETYPE: { 650 MVT VT = cast<VTSDNode>(N)->getVT(); 651 if (VT.isExtended()) { 652 Erased = ExtendedValueTypeNodes.erase(VT); 653 } else { 654 Erased = ValueTypeNodes[VT.getSimpleVT()] != 0; 655 ValueTypeNodes[VT.getSimpleVT()] = 0; 656 } 657 break; 658 } 659 default: 660 // Remove it from the CSE Map. 661 Erased = CSEMap.RemoveNode(N); 662 break; 663 } 664#ifndef NDEBUG 665 // Verify that the node was actually in one of the CSE maps, unless it has a 666 // flag result (which cannot be CSE'd) or is one of the special cases that are 667 // not subject to CSE. 668 if (!Erased && N->getValueType(N->getNumValues()-1) != MVT::Flag && 669 !N->isMachineOpcode() && !doNotCSE(N)) { 670 N->dump(this); 671 cerr << "\n"; 672 llvm_unreachable("Node is not in map!"); 673 } 674#endif 675 return Erased; 676} 677 678/// AddModifiedNodeToCSEMaps - The specified node has been removed from the CSE 679/// maps and modified in place. Add it back to the CSE maps, unless an identical 680/// node already exists, in which case transfer all its users to the existing 681/// node. This transfer can potentially trigger recursive merging. 682/// 683void 684SelectionDAG::AddModifiedNodeToCSEMaps(SDNode *N, 685 DAGUpdateListener *UpdateListener) { 686 // For node types that aren't CSE'd, just act as if no identical node 687 // already exists. 688 if (!doNotCSE(N)) { 689 SDNode *Existing = CSEMap.GetOrInsertNode(N); 690 if (Existing != N) { 691 // If there was already an existing matching node, use ReplaceAllUsesWith 692 // to replace the dead one with the existing one. This can cause 693 // recursive merging of other unrelated nodes down the line. 694 ReplaceAllUsesWith(N, Existing, UpdateListener); 695 696 // N is now dead. Inform the listener if it exists and delete it. 697 if (UpdateListener) 698 UpdateListener->NodeDeleted(N, Existing); 699 DeleteNodeNotInCSEMaps(N); 700 return; 701 } 702 } 703 704 // If the node doesn't already exist, we updated it. Inform a listener if 705 // it exists. 706 if (UpdateListener) 707 UpdateListener->NodeUpdated(N); 708} 709 710/// FindModifiedNodeSlot - Find a slot for the specified node if its operands 711/// were replaced with those specified. If this node is never memoized, 712/// return null, otherwise return a pointer to the slot it would take. If a 713/// node already exists with these operands, the slot will be non-null. 714SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, SDValue Op, 715 void *&InsertPos) { 716 if (doNotCSE(N)) 717 return 0; 718 719 SDValue Ops[] = { Op }; 720 FoldingSetNodeID ID; 721 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, 1); 722 AddNodeIDCustom(ID, N); 723 return CSEMap.FindNodeOrInsertPos(ID, InsertPos); 724} 725 726/// FindModifiedNodeSlot - Find a slot for the specified node if its operands 727/// were replaced with those specified. If this node is never memoized, 728/// return null, otherwise return a pointer to the slot it would take. If a 729/// node already exists with these operands, the slot will be non-null. 730SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, 731 SDValue Op1, SDValue Op2, 732 void *&InsertPos) { 733 if (doNotCSE(N)) 734 return 0; 735 736 SDValue Ops[] = { Op1, Op2 }; 737 FoldingSetNodeID ID; 738 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, 2); 739 AddNodeIDCustom(ID, N); 740 return CSEMap.FindNodeOrInsertPos(ID, InsertPos); 741} 742 743 744/// FindModifiedNodeSlot - Find a slot for the specified node if its operands 745/// were replaced with those specified. If this node is never memoized, 746/// return null, otherwise return a pointer to the slot it would take. If a 747/// node already exists with these operands, the slot will be non-null. 748SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, 749 const SDValue *Ops,unsigned NumOps, 750 void *&InsertPos) { 751 if (doNotCSE(N)) 752 return 0; 753 754 FoldingSetNodeID ID; 755 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, NumOps); 756 AddNodeIDCustom(ID, N); 757 return CSEMap.FindNodeOrInsertPos(ID, InsertPos); 758} 759 760/// VerifyNode - Sanity check the given node. Aborts if it is invalid. 761void SelectionDAG::VerifyNode(SDNode *N) { 762 switch (N->getOpcode()) { 763 default: 764 break; 765 case ISD::BUILD_PAIR: { 766 MVT VT = N->getValueType(0); 767 assert(N->getNumValues() == 1 && "Too many results!"); 768 assert(!VT.isVector() && (VT.isInteger() || VT.isFloatingPoint()) && 769 "Wrong return type!"); 770 assert(N->getNumOperands() == 2 && "Wrong number of operands!"); 771 assert(N->getOperand(0).getValueType() == N->getOperand(1).getValueType() && 772 "Mismatched operand types!"); 773 assert(N->getOperand(0).getValueType().isInteger() == VT.isInteger() && 774 "Wrong operand type!"); 775 assert(VT.getSizeInBits() == 2 * N->getOperand(0).getValueSizeInBits() && 776 "Wrong return type size"); 777 break; 778 } 779 case ISD::BUILD_VECTOR: { 780 assert(N->getNumValues() == 1 && "Too many results!"); 781 assert(N->getValueType(0).isVector() && "Wrong return type!"); 782 assert(N->getNumOperands() == N->getValueType(0).getVectorNumElements() && 783 "Wrong number of operands!"); 784 MVT EltVT = N->getValueType(0).getVectorElementType(); 785 for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ++I) 786 assert((I->getValueType() == EltVT || 787 (EltVT.isInteger() && I->getValueType().isInteger() && 788 EltVT.bitsLE(I->getValueType()))) && 789 "Wrong operand type!"); 790 break; 791 } 792 } 793} 794 795/// getMVTAlignment - Compute the default alignment value for the 796/// given type. 797/// 798unsigned SelectionDAG::getMVTAlignment(MVT VT) const { 799 const Type *Ty = VT == MVT::iPTR ? 800 PointerType::get(Type::Int8Ty, 0) : 801 VT.getTypeForMVT(); 802 803 return TLI.getTargetData()->getABITypeAlignment(Ty); 804} 805 806// EntryNode could meaningfully have debug info if we can find it... 807SelectionDAG::SelectionDAG(TargetLowering &tli, FunctionLoweringInfo &fli) 808 : TLI(tli), FLI(fli), DW(0), 809 EntryNode(ISD::EntryToken, DebugLoc::getUnknownLoc(), 810 getVTList(MVT::Other)), Root(getEntryNode()) { 811 AllNodes.push_back(&EntryNode); 812} 813 814void SelectionDAG::init(MachineFunction &mf, MachineModuleInfo *mmi, 815 DwarfWriter *dw) { 816 MF = &mf; 817 MMI = mmi; 818 DW = dw; 819 Context = &mf.getFunction()->getContext(); 820} 821 822SelectionDAG::~SelectionDAG() { 823 allnodes_clear(); 824} 825 826void SelectionDAG::allnodes_clear() { 827 assert(&*AllNodes.begin() == &EntryNode); 828 AllNodes.remove(AllNodes.begin()); 829 while (!AllNodes.empty()) 830 DeallocateNode(AllNodes.begin()); 831} 832 833void SelectionDAG::clear() { 834 allnodes_clear(); 835 OperandAllocator.Reset(); 836 CSEMap.clear(); 837 838 ExtendedValueTypeNodes.clear(); 839 ExternalSymbols.clear(); 840 TargetExternalSymbols.clear(); 841 std::fill(CondCodeNodes.begin(), CondCodeNodes.end(), 842 static_cast<CondCodeSDNode*>(0)); 843 std::fill(ValueTypeNodes.begin(), ValueTypeNodes.end(), 844 static_cast<SDNode*>(0)); 845 846 EntryNode.UseList = 0; 847 AllNodes.push_back(&EntryNode); 848 Root = getEntryNode(); 849} 850 851SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, DebugLoc DL, MVT VT) { 852 if (Op.getValueType() == VT) return Op; 853 APInt Imm = APInt::getLowBitsSet(Op.getValueSizeInBits(), 854 VT.getSizeInBits()); 855 return getNode(ISD::AND, DL, Op.getValueType(), Op, 856 getConstant(Imm, Op.getValueType())); 857} 858 859/// getNOT - Create a bitwise NOT operation as (XOR Val, -1). 860/// 861SDValue SelectionDAG::getNOT(DebugLoc DL, SDValue Val, MVT VT) { 862 MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 863 SDValue NegOne = 864 getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT); 865 return getNode(ISD::XOR, DL, VT, Val, NegOne); 866} 867 868SDValue SelectionDAG::getConstant(uint64_t Val, MVT VT, bool isT) { 869 MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 870 assert((EltVT.getSizeInBits() >= 64 || 871 (uint64_t)((int64_t)Val >> EltVT.getSizeInBits()) + 1 < 2) && 872 "getConstant with a uint64_t value that doesn't fit in the type!"); 873 return getConstant(APInt(EltVT.getSizeInBits(), Val), VT, isT); 874} 875 876SDValue SelectionDAG::getConstant(const APInt &Val, MVT VT, bool isT) { 877 return getConstant(*ConstantInt::get(*Context, Val), VT, isT); 878} 879 880SDValue SelectionDAG::getConstant(const ConstantInt &Val, MVT VT, bool isT) { 881 assert(VT.isInteger() && "Cannot create FP integer constant!"); 882 883 MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 884 assert(Val.getBitWidth() == EltVT.getSizeInBits() && 885 "APInt size does not match type size!"); 886 887 unsigned Opc = isT ? ISD::TargetConstant : ISD::Constant; 888 FoldingSetNodeID ID; 889 AddNodeIDNode(ID, Opc, getVTList(EltVT), 0, 0); 890 ID.AddPointer(&Val); 891 void *IP = 0; 892 SDNode *N = NULL; 893 if ((N = CSEMap.FindNodeOrInsertPos(ID, IP))) 894 if (!VT.isVector()) 895 return SDValue(N, 0); 896 if (!N) { 897 N = NodeAllocator.Allocate<ConstantSDNode>(); 898 new (N) ConstantSDNode(isT, &Val, EltVT); 899 CSEMap.InsertNode(N, IP); 900 AllNodes.push_back(N); 901 } 902 903 SDValue Result(N, 0); 904 if (VT.isVector()) { 905 SmallVector<SDValue, 8> Ops; 906 Ops.assign(VT.getVectorNumElements(), Result); 907 Result = getNode(ISD::BUILD_VECTOR, DebugLoc::getUnknownLoc(), 908 VT, &Ops[0], Ops.size()); 909 } 910 return Result; 911} 912 913SDValue SelectionDAG::getIntPtrConstant(uint64_t Val, bool isTarget) { 914 return getConstant(Val, TLI.getPointerTy(), isTarget); 915} 916 917 918SDValue SelectionDAG::getConstantFP(const APFloat& V, MVT VT, bool isTarget) { 919 return getConstantFP(*ConstantFP::get(*getContext(), V), VT, isTarget); 920} 921 922SDValue SelectionDAG::getConstantFP(const ConstantFP& V, MVT VT, bool isTarget){ 923 assert(VT.isFloatingPoint() && "Cannot create integer FP constant!"); 924 925 MVT EltVT = 926 VT.isVector() ? VT.getVectorElementType() : VT; 927 928 // Do the map lookup using the actual bit pattern for the floating point 929 // value, so that we don't have problems with 0.0 comparing equal to -0.0, and 930 // we don't have issues with SNANs. 931 unsigned Opc = isTarget ? ISD::TargetConstantFP : ISD::ConstantFP; 932 FoldingSetNodeID ID; 933 AddNodeIDNode(ID, Opc, getVTList(EltVT), 0, 0); 934 ID.AddPointer(&V); 935 void *IP = 0; 936 SDNode *N = NULL; 937 if ((N = CSEMap.FindNodeOrInsertPos(ID, IP))) 938 if (!VT.isVector()) 939 return SDValue(N, 0); 940 if (!N) { 941 N = NodeAllocator.Allocate<ConstantFPSDNode>(); 942 new (N) ConstantFPSDNode(isTarget, &V, EltVT); 943 CSEMap.InsertNode(N, IP); 944 AllNodes.push_back(N); 945 } 946 947 SDValue Result(N, 0); 948 if (VT.isVector()) { 949 SmallVector<SDValue, 8> Ops; 950 Ops.assign(VT.getVectorNumElements(), Result); 951 // FIXME DebugLoc info might be appropriate here 952 Result = getNode(ISD::BUILD_VECTOR, DebugLoc::getUnknownLoc(), 953 VT, &Ops[0], Ops.size()); 954 } 955 return Result; 956} 957 958SDValue SelectionDAG::getConstantFP(double Val, MVT VT, bool isTarget) { 959 MVT EltVT = 960 VT.isVector() ? VT.getVectorElementType() : VT; 961 if (EltVT==MVT::f32) 962 return getConstantFP(APFloat((float)Val), VT, isTarget); 963 else 964 return getConstantFP(APFloat(Val), VT, isTarget); 965} 966 967SDValue SelectionDAG::getGlobalAddress(const GlobalValue *GV, 968 MVT VT, int64_t Offset, 969 bool isTargetGA, 970 unsigned char TargetFlags) { 971 assert((TargetFlags == 0 || isTargetGA) && 972 "Cannot set target flags on target-independent globals"); 973 974 // Truncate (with sign-extension) the offset value to the pointer size. 975 unsigned BitWidth = TLI.getPointerTy().getSizeInBits(); 976 if (BitWidth < 64) 977 Offset = (Offset << (64 - BitWidth) >> (64 - BitWidth)); 978 979 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV); 980 if (!GVar) { 981 // If GV is an alias then use the aliasee for determining thread-localness. 982 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) 983 GVar = dyn_cast_or_null<GlobalVariable>(GA->resolveAliasedGlobal(false)); 984 } 985 986 unsigned Opc; 987 if (GVar && GVar->isThreadLocal()) 988 Opc = isTargetGA ? ISD::TargetGlobalTLSAddress : ISD::GlobalTLSAddress; 989 else 990 Opc = isTargetGA ? ISD::TargetGlobalAddress : ISD::GlobalAddress; 991 992 FoldingSetNodeID ID; 993 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 994 ID.AddPointer(GV); 995 ID.AddInteger(Offset); 996 ID.AddInteger(TargetFlags); 997 void *IP = 0; 998 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 999 return SDValue(E, 0); 1000 SDNode *N = NodeAllocator.Allocate<GlobalAddressSDNode>(); 1001 new (N) GlobalAddressSDNode(Opc, GV, VT, Offset, TargetFlags); 1002 CSEMap.InsertNode(N, IP); 1003 AllNodes.push_back(N); 1004 return SDValue(N, 0); 1005} 1006 1007SDValue SelectionDAG::getFrameIndex(int FI, MVT VT, bool isTarget) { 1008 unsigned Opc = isTarget ? ISD::TargetFrameIndex : ISD::FrameIndex; 1009 FoldingSetNodeID ID; 1010 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 1011 ID.AddInteger(FI); 1012 void *IP = 0; 1013 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1014 return SDValue(E, 0); 1015 SDNode *N = NodeAllocator.Allocate<FrameIndexSDNode>(); 1016 new (N) FrameIndexSDNode(FI, VT, isTarget); 1017 CSEMap.InsertNode(N, IP); 1018 AllNodes.push_back(N); 1019 return SDValue(N, 0); 1020} 1021 1022SDValue SelectionDAG::getJumpTable(int JTI, MVT VT, bool isTarget, 1023 unsigned char TargetFlags) { 1024 assert((TargetFlags == 0 || isTarget) && 1025 "Cannot set target flags on target-independent jump tables"); 1026 unsigned Opc = isTarget ? ISD::TargetJumpTable : ISD::JumpTable; 1027 FoldingSetNodeID ID; 1028 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 1029 ID.AddInteger(JTI); 1030 ID.AddInteger(TargetFlags); 1031 void *IP = 0; 1032 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1033 return SDValue(E, 0); 1034 SDNode *N = NodeAllocator.Allocate<JumpTableSDNode>(); 1035 new (N) JumpTableSDNode(JTI, VT, isTarget, TargetFlags); 1036 CSEMap.InsertNode(N, IP); 1037 AllNodes.push_back(N); 1038 return SDValue(N, 0); 1039} 1040 1041SDValue SelectionDAG::getConstantPool(Constant *C, MVT VT, 1042 unsigned Alignment, int Offset, 1043 bool isTarget, 1044 unsigned char TargetFlags) { 1045 assert((TargetFlags == 0 || isTarget) && 1046 "Cannot set target flags on target-independent globals"); 1047 if (Alignment == 0) 1048 Alignment = TLI.getTargetData()->getPrefTypeAlignment(C->getType()); 1049 unsigned Opc = isTarget ? ISD::TargetConstantPool : ISD::ConstantPool; 1050 FoldingSetNodeID ID; 1051 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 1052 ID.AddInteger(Alignment); 1053 ID.AddInteger(Offset); 1054 ID.AddPointer(C); 1055 ID.AddInteger(TargetFlags); 1056 void *IP = 0; 1057 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1058 return SDValue(E, 0); 1059 SDNode *N = NodeAllocator.Allocate<ConstantPoolSDNode>(); 1060 new (N) ConstantPoolSDNode(isTarget, C, VT, Offset, Alignment, TargetFlags); 1061 CSEMap.InsertNode(N, IP); 1062 AllNodes.push_back(N); 1063 return SDValue(N, 0); 1064} 1065 1066 1067SDValue SelectionDAG::getConstantPool(MachineConstantPoolValue *C, MVT VT, 1068 unsigned Alignment, int Offset, 1069 bool isTarget, 1070 unsigned char TargetFlags) { 1071 assert((TargetFlags == 0 || isTarget) && 1072 "Cannot set target flags on target-independent globals"); 1073 if (Alignment == 0) 1074 Alignment = TLI.getTargetData()->getPrefTypeAlignment(C->getType()); 1075 unsigned Opc = isTarget ? ISD::TargetConstantPool : ISD::ConstantPool; 1076 FoldingSetNodeID ID; 1077 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 1078 ID.AddInteger(Alignment); 1079 ID.AddInteger(Offset); 1080 C->AddSelectionDAGCSEId(ID); 1081 ID.AddInteger(TargetFlags); 1082 void *IP = 0; 1083 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1084 return SDValue(E, 0); 1085 SDNode *N = NodeAllocator.Allocate<ConstantPoolSDNode>(); 1086 new (N) ConstantPoolSDNode(isTarget, C, VT, Offset, Alignment, TargetFlags); 1087 CSEMap.InsertNode(N, IP); 1088 AllNodes.push_back(N); 1089 return SDValue(N, 0); 1090} 1091 1092SDValue SelectionDAG::getBasicBlock(MachineBasicBlock *MBB) { 1093 FoldingSetNodeID ID; 1094 AddNodeIDNode(ID, ISD::BasicBlock, getVTList(MVT::Other), 0, 0); 1095 ID.AddPointer(MBB); 1096 void *IP = 0; 1097 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1098 return SDValue(E, 0); 1099 SDNode *N = NodeAllocator.Allocate<BasicBlockSDNode>(); 1100 new (N) BasicBlockSDNode(MBB); 1101 CSEMap.InsertNode(N, IP); 1102 AllNodes.push_back(N); 1103 return SDValue(N, 0); 1104} 1105 1106SDValue SelectionDAG::getArgFlags(ISD::ArgFlagsTy Flags) { 1107 FoldingSetNodeID ID; 1108 AddNodeIDNode(ID, ISD::ARG_FLAGS, getVTList(MVT::Other), 0, 0); 1109 ID.AddInteger(Flags.getRawBits()); 1110 void *IP = 0; 1111 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1112 return SDValue(E, 0); 1113 SDNode *N = NodeAllocator.Allocate<ARG_FLAGSSDNode>(); 1114 new (N) ARG_FLAGSSDNode(Flags); 1115 CSEMap.InsertNode(N, IP); 1116 AllNodes.push_back(N); 1117 return SDValue(N, 0); 1118} 1119 1120SDValue SelectionDAG::getValueType(MVT VT) { 1121 if (VT.isSimple() && (unsigned)VT.getSimpleVT() >= ValueTypeNodes.size()) 1122 ValueTypeNodes.resize(VT.getSimpleVT()+1); 1123 1124 SDNode *&N = VT.isExtended() ? 1125 ExtendedValueTypeNodes[VT] : ValueTypeNodes[VT.getSimpleVT()]; 1126 1127 if (N) return SDValue(N, 0); 1128 N = NodeAllocator.Allocate<VTSDNode>(); 1129 new (N) VTSDNode(VT); 1130 AllNodes.push_back(N); 1131 return SDValue(N, 0); 1132} 1133 1134SDValue SelectionDAG::getExternalSymbol(const char *Sym, MVT VT) { 1135 SDNode *&N = ExternalSymbols[Sym]; 1136 if (N) return SDValue(N, 0); 1137 N = NodeAllocator.Allocate<ExternalSymbolSDNode>(); 1138 new (N) ExternalSymbolSDNode(false, Sym, 0, VT); 1139 AllNodes.push_back(N); 1140 return SDValue(N, 0); 1141} 1142 1143SDValue SelectionDAG::getTargetExternalSymbol(const char *Sym, MVT VT, 1144 unsigned char TargetFlags) { 1145 SDNode *&N = 1146 TargetExternalSymbols[std::pair<std::string,unsigned char>(Sym, 1147 TargetFlags)]; 1148 if (N) return SDValue(N, 0); 1149 N = NodeAllocator.Allocate<ExternalSymbolSDNode>(); 1150 new (N) ExternalSymbolSDNode(true, Sym, TargetFlags, VT); 1151 AllNodes.push_back(N); 1152 return SDValue(N, 0); 1153} 1154 1155SDValue SelectionDAG::getCondCode(ISD::CondCode Cond) { 1156 if ((unsigned)Cond >= CondCodeNodes.size()) 1157 CondCodeNodes.resize(Cond+1); 1158 1159 if (CondCodeNodes[Cond] == 0) { 1160 CondCodeSDNode *N = NodeAllocator.Allocate<CondCodeSDNode>(); 1161 new (N) CondCodeSDNode(Cond); 1162 CondCodeNodes[Cond] = N; 1163 AllNodes.push_back(N); 1164 } 1165 return SDValue(CondCodeNodes[Cond], 0); 1166} 1167 1168// commuteShuffle - swaps the values of N1 and N2, and swaps all indices in 1169// the shuffle mask M that point at N1 to point at N2, and indices that point 1170// N2 to point at N1. 1171static void commuteShuffle(SDValue &N1, SDValue &N2, SmallVectorImpl<int> &M) { 1172 std::swap(N1, N2); 1173 int NElts = M.size(); 1174 for (int i = 0; i != NElts; ++i) { 1175 if (M[i] >= NElts) 1176 M[i] -= NElts; 1177 else if (M[i] >= 0) 1178 M[i] += NElts; 1179 } 1180} 1181 1182SDValue SelectionDAG::getVectorShuffle(MVT VT, DebugLoc dl, SDValue N1, 1183 SDValue N2, const int *Mask) { 1184 assert(N1.getValueType() == N2.getValueType() && "Invalid VECTOR_SHUFFLE"); 1185 assert(VT.isVector() && N1.getValueType().isVector() && 1186 "Vector Shuffle VTs must be a vectors"); 1187 assert(VT.getVectorElementType() == N1.getValueType().getVectorElementType() 1188 && "Vector Shuffle VTs must have same element type"); 1189 1190 // Canonicalize shuffle undef, undef -> undef 1191 if (N1.getOpcode() == ISD::UNDEF && N2.getOpcode() == ISD::UNDEF) 1192 return getUNDEF(VT); 1193 1194 // Validate that all indices in Mask are within the range of the elements 1195 // input to the shuffle. 1196 unsigned NElts = VT.getVectorNumElements(); 1197 SmallVector<int, 8> MaskVec; 1198 for (unsigned i = 0; i != NElts; ++i) { 1199 assert(Mask[i] < (int)(NElts * 2) && "Index out of range"); 1200 MaskVec.push_back(Mask[i]); 1201 } 1202 1203 // Canonicalize shuffle v, v -> v, undef 1204 if (N1 == N2) { 1205 N2 = getUNDEF(VT); 1206 for (unsigned i = 0; i != NElts; ++i) 1207 if (MaskVec[i] >= (int)NElts) MaskVec[i] -= NElts; 1208 } 1209 1210 // Canonicalize shuffle undef, v -> v, undef. Commute the shuffle mask. 1211 if (N1.getOpcode() == ISD::UNDEF) 1212 commuteShuffle(N1, N2, MaskVec); 1213 1214 // Canonicalize all index into lhs, -> shuffle lhs, undef 1215 // Canonicalize all index into rhs, -> shuffle rhs, undef 1216 bool AllLHS = true, AllRHS = true; 1217 bool N2Undef = N2.getOpcode() == ISD::UNDEF; 1218 for (unsigned i = 0; i != NElts; ++i) { 1219 if (MaskVec[i] >= (int)NElts) { 1220 if (N2Undef) 1221 MaskVec[i] = -1; 1222 else 1223 AllLHS = false; 1224 } else if (MaskVec[i] >= 0) { 1225 AllRHS = false; 1226 } 1227 } 1228 if (AllLHS && AllRHS) 1229 return getUNDEF(VT); 1230 if (AllLHS && !N2Undef) 1231 N2 = getUNDEF(VT); 1232 if (AllRHS) { 1233 N1 = getUNDEF(VT); 1234 commuteShuffle(N1, N2, MaskVec); 1235 } 1236 1237 // If Identity shuffle, or all shuffle in to undef, return that node. 1238 bool AllUndef = true; 1239 bool Identity = true; 1240 for (unsigned i = 0; i != NElts; ++i) { 1241 if (MaskVec[i] >= 0 && MaskVec[i] != (int)i) Identity = false; 1242 if (MaskVec[i] >= 0) AllUndef = false; 1243 } 1244 if (Identity && NElts == N1.getValueType().getVectorNumElements()) 1245 return N1; 1246 if (AllUndef) 1247 return getUNDEF(VT); 1248 1249 FoldingSetNodeID ID; 1250 SDValue Ops[2] = { N1, N2 }; 1251 AddNodeIDNode(ID, ISD::VECTOR_SHUFFLE, getVTList(VT), Ops, 2); 1252 for (unsigned i = 0; i != NElts; ++i) 1253 ID.AddInteger(MaskVec[i]); 1254 1255 void* IP = 0; 1256 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1257 return SDValue(E, 0); 1258 1259 // Allocate the mask array for the node out of the BumpPtrAllocator, since 1260 // SDNode doesn't have access to it. This memory will be "leaked" when 1261 // the node is deallocated, but recovered when the NodeAllocator is released. 1262 int *MaskAlloc = OperandAllocator.Allocate<int>(NElts); 1263 memcpy(MaskAlloc, &MaskVec[0], NElts * sizeof(int)); 1264 1265 ShuffleVectorSDNode *N = NodeAllocator.Allocate<ShuffleVectorSDNode>(); 1266 new (N) ShuffleVectorSDNode(VT, dl, N1, N2, MaskAlloc); 1267 CSEMap.InsertNode(N, IP); 1268 AllNodes.push_back(N); 1269 return SDValue(N, 0); 1270} 1271 1272SDValue SelectionDAG::getConvertRndSat(MVT VT, DebugLoc dl, 1273 SDValue Val, SDValue DTy, 1274 SDValue STy, SDValue Rnd, SDValue Sat, 1275 ISD::CvtCode Code) { 1276 // If the src and dest types are the same and the conversion is between 1277 // integer types of the same sign or two floats, no conversion is necessary. 1278 if (DTy == STy && 1279 (Code == ISD::CVT_UU || Code == ISD::CVT_SS || Code == ISD::CVT_FF)) 1280 return Val; 1281 1282 FoldingSetNodeID ID; 1283 void* IP = 0; 1284 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1285 return SDValue(E, 0); 1286 CvtRndSatSDNode *N = NodeAllocator.Allocate<CvtRndSatSDNode>(); 1287 SDValue Ops[] = { Val, DTy, STy, Rnd, Sat }; 1288 new (N) CvtRndSatSDNode(VT, dl, Ops, 5, Code); 1289 CSEMap.InsertNode(N, IP); 1290 AllNodes.push_back(N); 1291 return SDValue(N, 0); 1292} 1293 1294SDValue SelectionDAG::getRegister(unsigned RegNo, MVT VT) { 1295 FoldingSetNodeID ID; 1296 AddNodeIDNode(ID, ISD::Register, getVTList(VT), 0, 0); 1297 ID.AddInteger(RegNo); 1298 void *IP = 0; 1299 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1300 return SDValue(E, 0); 1301 SDNode *N = NodeAllocator.Allocate<RegisterSDNode>(); 1302 new (N) RegisterSDNode(RegNo, VT); 1303 CSEMap.InsertNode(N, IP); 1304 AllNodes.push_back(N); 1305 return SDValue(N, 0); 1306} 1307 1308SDValue SelectionDAG::getDbgStopPoint(DebugLoc DL, SDValue Root, 1309 unsigned Line, unsigned Col, 1310 Value *CU) { 1311 SDNode *N = NodeAllocator.Allocate<DbgStopPointSDNode>(); 1312 new (N) DbgStopPointSDNode(Root, Line, Col, CU); 1313 N->setDebugLoc(DL); 1314 AllNodes.push_back(N); 1315 return SDValue(N, 0); 1316} 1317 1318SDValue SelectionDAG::getLabel(unsigned Opcode, DebugLoc dl, 1319 SDValue Root, 1320 unsigned LabelID) { 1321 FoldingSetNodeID ID; 1322 SDValue Ops[] = { Root }; 1323 AddNodeIDNode(ID, Opcode, getVTList(MVT::Other), &Ops[0], 1); 1324 ID.AddInteger(LabelID); 1325 void *IP = 0; 1326 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1327 return SDValue(E, 0); 1328 SDNode *N = NodeAllocator.Allocate<LabelSDNode>(); 1329 new (N) LabelSDNode(Opcode, dl, Root, LabelID); 1330 CSEMap.InsertNode(N, IP); 1331 AllNodes.push_back(N); 1332 return SDValue(N, 0); 1333} 1334 1335SDValue SelectionDAG::getSrcValue(const Value *V) { 1336 assert((!V || isa<PointerType>(V->getType())) && 1337 "SrcValue is not a pointer?"); 1338 1339 FoldingSetNodeID ID; 1340 AddNodeIDNode(ID, ISD::SRCVALUE, getVTList(MVT::Other), 0, 0); 1341 ID.AddPointer(V); 1342 1343 void *IP = 0; 1344 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1345 return SDValue(E, 0); 1346 1347 SDNode *N = NodeAllocator.Allocate<SrcValueSDNode>(); 1348 new (N) SrcValueSDNode(V); 1349 CSEMap.InsertNode(N, IP); 1350 AllNodes.push_back(N); 1351 return SDValue(N, 0); 1352} 1353 1354SDValue SelectionDAG::getMemOperand(const MachineMemOperand &MO) { 1355#ifndef NDEBUG 1356 const Value *v = MO.getValue(); 1357 assert((!v || isa<PointerType>(v->getType())) && 1358 "SrcValue is not a pointer?"); 1359#endif 1360 1361 FoldingSetNodeID ID; 1362 AddNodeIDNode(ID, ISD::MEMOPERAND, getVTList(MVT::Other), 0, 0); 1363 MO.Profile(ID); 1364 1365 void *IP = 0; 1366 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1367 return SDValue(E, 0); 1368 1369 SDNode *N = NodeAllocator.Allocate<MemOperandSDNode>(); 1370 new (N) MemOperandSDNode(MO); 1371 CSEMap.InsertNode(N, IP); 1372 AllNodes.push_back(N); 1373 return SDValue(N, 0); 1374} 1375 1376/// getShiftAmountOperand - Return the specified value casted to 1377/// the target's desired shift amount type. 1378SDValue SelectionDAG::getShiftAmountOperand(SDValue Op) { 1379 MVT OpTy = Op.getValueType(); 1380 MVT ShTy = TLI.getShiftAmountTy(); 1381 if (OpTy == ShTy || OpTy.isVector()) return Op; 1382 1383 ISD::NodeType Opcode = OpTy.bitsGT(ShTy) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; 1384 return getNode(Opcode, Op.getDebugLoc(), ShTy, Op); 1385} 1386 1387/// CreateStackTemporary - Create a stack temporary, suitable for holding the 1388/// specified value type. 1389SDValue SelectionDAG::CreateStackTemporary(MVT VT, unsigned minAlign) { 1390 MachineFrameInfo *FrameInfo = getMachineFunction().getFrameInfo(); 1391 unsigned ByteSize = VT.getStoreSizeInBits()/8; 1392 const Type *Ty = VT.getTypeForMVT(); 1393 unsigned StackAlign = 1394 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), minAlign); 1395 1396 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, StackAlign); 1397 return getFrameIndex(FrameIdx, TLI.getPointerTy()); 1398} 1399 1400/// CreateStackTemporary - Create a stack temporary suitable for holding 1401/// either of the specified value types. 1402SDValue SelectionDAG::CreateStackTemporary(MVT VT1, MVT VT2) { 1403 unsigned Bytes = std::max(VT1.getStoreSizeInBits(), 1404 VT2.getStoreSizeInBits())/8; 1405 const Type *Ty1 = VT1.getTypeForMVT(); 1406 const Type *Ty2 = VT2.getTypeForMVT(); 1407 const TargetData *TD = TLI.getTargetData(); 1408 unsigned Align = std::max(TD->getPrefTypeAlignment(Ty1), 1409 TD->getPrefTypeAlignment(Ty2)); 1410 1411 MachineFrameInfo *FrameInfo = getMachineFunction().getFrameInfo(); 1412 int FrameIdx = FrameInfo->CreateStackObject(Bytes, Align); 1413 return getFrameIndex(FrameIdx, TLI.getPointerTy()); 1414} 1415 1416SDValue SelectionDAG::FoldSetCC(MVT VT, SDValue N1, 1417 SDValue N2, ISD::CondCode Cond, DebugLoc dl) { 1418 // These setcc operations always fold. 1419 switch (Cond) { 1420 default: break; 1421 case ISD::SETFALSE: 1422 case ISD::SETFALSE2: return getConstant(0, VT); 1423 case ISD::SETTRUE: 1424 case ISD::SETTRUE2: return getConstant(1, VT); 1425 1426 case ISD::SETOEQ: 1427 case ISD::SETOGT: 1428 case ISD::SETOGE: 1429 case ISD::SETOLT: 1430 case ISD::SETOLE: 1431 case ISD::SETONE: 1432 case ISD::SETO: 1433 case ISD::SETUO: 1434 case ISD::SETUEQ: 1435 case ISD::SETUNE: 1436 assert(!N1.getValueType().isInteger() && "Illegal setcc for integer!"); 1437 break; 1438 } 1439 1440 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode())) { 1441 const APInt &C2 = N2C->getAPIntValue(); 1442 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) { 1443 const APInt &C1 = N1C->getAPIntValue(); 1444 1445 switch (Cond) { 1446 default: llvm_unreachable("Unknown integer setcc!"); 1447 case ISD::SETEQ: return getConstant(C1 == C2, VT); 1448 case ISD::SETNE: return getConstant(C1 != C2, VT); 1449 case ISD::SETULT: return getConstant(C1.ult(C2), VT); 1450 case ISD::SETUGT: return getConstant(C1.ugt(C2), VT); 1451 case ISD::SETULE: return getConstant(C1.ule(C2), VT); 1452 case ISD::SETUGE: return getConstant(C1.uge(C2), VT); 1453 case ISD::SETLT: return getConstant(C1.slt(C2), VT); 1454 case ISD::SETGT: return getConstant(C1.sgt(C2), VT); 1455 case ISD::SETLE: return getConstant(C1.sle(C2), VT); 1456 case ISD::SETGE: return getConstant(C1.sge(C2), VT); 1457 } 1458 } 1459 } 1460 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.getNode())) { 1461 if (ConstantFPSDNode *N2C = dyn_cast<ConstantFPSDNode>(N2.getNode())) { 1462 // No compile time operations on this type yet. 1463 if (N1C->getValueType(0) == MVT::ppcf128) 1464 return SDValue(); 1465 1466 APFloat::cmpResult R = N1C->getValueAPF().compare(N2C->getValueAPF()); 1467 switch (Cond) { 1468 default: break; 1469 case ISD::SETEQ: if (R==APFloat::cmpUnordered) 1470 return getUNDEF(VT); 1471 // fall through 1472 case ISD::SETOEQ: return getConstant(R==APFloat::cmpEqual, VT); 1473 case ISD::SETNE: if (R==APFloat::cmpUnordered) 1474 return getUNDEF(VT); 1475 // fall through 1476 case ISD::SETONE: return getConstant(R==APFloat::cmpGreaterThan || 1477 R==APFloat::cmpLessThan, VT); 1478 case ISD::SETLT: if (R==APFloat::cmpUnordered) 1479 return getUNDEF(VT); 1480 // fall through 1481 case ISD::SETOLT: return getConstant(R==APFloat::cmpLessThan, VT); 1482 case ISD::SETGT: if (R==APFloat::cmpUnordered) 1483 return getUNDEF(VT); 1484 // fall through 1485 case ISD::SETOGT: return getConstant(R==APFloat::cmpGreaterThan, VT); 1486 case ISD::SETLE: if (R==APFloat::cmpUnordered) 1487 return getUNDEF(VT); 1488 // fall through 1489 case ISD::SETOLE: return getConstant(R==APFloat::cmpLessThan || 1490 R==APFloat::cmpEqual, VT); 1491 case ISD::SETGE: if (R==APFloat::cmpUnordered) 1492 return getUNDEF(VT); 1493 // fall through 1494 case ISD::SETOGE: return getConstant(R==APFloat::cmpGreaterThan || 1495 R==APFloat::cmpEqual, VT); 1496 case ISD::SETO: return getConstant(R!=APFloat::cmpUnordered, VT); 1497 case ISD::SETUO: return getConstant(R==APFloat::cmpUnordered, VT); 1498 case ISD::SETUEQ: return getConstant(R==APFloat::cmpUnordered || 1499 R==APFloat::cmpEqual, VT); 1500 case ISD::SETUNE: return getConstant(R!=APFloat::cmpEqual, VT); 1501 case ISD::SETULT: return getConstant(R==APFloat::cmpUnordered || 1502 R==APFloat::cmpLessThan, VT); 1503 case ISD::SETUGT: return getConstant(R==APFloat::cmpGreaterThan || 1504 R==APFloat::cmpUnordered, VT); 1505 case ISD::SETULE: return getConstant(R!=APFloat::cmpGreaterThan, VT); 1506 case ISD::SETUGE: return getConstant(R!=APFloat::cmpLessThan, VT); 1507 } 1508 } else { 1509 // Ensure that the constant occurs on the RHS. 1510 return getSetCC(dl, VT, N2, N1, ISD::getSetCCSwappedOperands(Cond)); 1511 } 1512 } 1513 1514 // Could not fold it. 1515 return SDValue(); 1516} 1517 1518/// SignBitIsZero - Return true if the sign bit of Op is known to be zero. We 1519/// use this predicate to simplify operations downstream. 1520bool SelectionDAG::SignBitIsZero(SDValue Op, unsigned Depth) const { 1521 // This predicate is not safe for vector operations. 1522 if (Op.getValueType().isVector()) 1523 return false; 1524 1525 unsigned BitWidth = Op.getValueSizeInBits(); 1526 return MaskedValueIsZero(Op, APInt::getSignBit(BitWidth), Depth); 1527} 1528 1529/// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero. We use 1530/// this predicate to simplify operations downstream. Mask is known to be zero 1531/// for bits that V cannot have. 1532bool SelectionDAG::MaskedValueIsZero(SDValue Op, const APInt &Mask, 1533 unsigned Depth) const { 1534 APInt KnownZero, KnownOne; 1535 ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth); 1536 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1537 return (KnownZero & Mask) == Mask; 1538} 1539 1540/// ComputeMaskedBits - Determine which of the bits specified in Mask are 1541/// known to be either zero or one and return them in the KnownZero/KnownOne 1542/// bitsets. This code only analyzes bits in Mask, in order to short-circuit 1543/// processing. 1544void SelectionDAG::ComputeMaskedBits(SDValue Op, const APInt &Mask, 1545 APInt &KnownZero, APInt &KnownOne, 1546 unsigned Depth) const { 1547 unsigned BitWidth = Mask.getBitWidth(); 1548 assert(BitWidth == Op.getValueType().getSizeInBits() && 1549 "Mask size mismatches value type size!"); 1550 1551 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything. 1552 if (Depth == 6 || Mask == 0) 1553 return; // Limit search depth. 1554 1555 APInt KnownZero2, KnownOne2; 1556 1557 switch (Op.getOpcode()) { 1558 case ISD::Constant: 1559 // We know all of the bits for a constant! 1560 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & Mask; 1561 KnownZero = ~KnownOne & Mask; 1562 return; 1563 case ISD::AND: 1564 // If either the LHS or the RHS are Zero, the result is zero. 1565 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1566 ComputeMaskedBits(Op.getOperand(0), Mask & ~KnownZero, 1567 KnownZero2, KnownOne2, Depth+1); 1568 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1569 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1570 1571 // Output known-1 bits are only known if set in both the LHS & RHS. 1572 KnownOne &= KnownOne2; 1573 // Output known-0 are known to be clear if zero in either the LHS | RHS. 1574 KnownZero |= KnownZero2; 1575 return; 1576 case ISD::OR: 1577 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1578 ComputeMaskedBits(Op.getOperand(0), Mask & ~KnownOne, 1579 KnownZero2, KnownOne2, Depth+1); 1580 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1581 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1582 1583 // Output known-0 bits are only known if clear in both the LHS & RHS. 1584 KnownZero &= KnownZero2; 1585 // Output known-1 are known to be set if set in either the LHS | RHS. 1586 KnownOne |= KnownOne2; 1587 return; 1588 case ISD::XOR: { 1589 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1590 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1); 1591 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1592 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1593 1594 // Output known-0 bits are known if clear or set in both the LHS & RHS. 1595 APInt KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 1596 // Output known-1 are known to be set if set in only one of the LHS, RHS. 1597 KnownOne = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 1598 KnownZero = KnownZeroOut; 1599 return; 1600 } 1601 case ISD::MUL: { 1602 APInt Mask2 = APInt::getAllOnesValue(BitWidth); 1603 ComputeMaskedBits(Op.getOperand(1), Mask2, KnownZero, KnownOne, Depth+1); 1604 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero2, KnownOne2, Depth+1); 1605 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1606 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1607 1608 // If low bits are zero in either operand, output low known-0 bits. 1609 // Also compute a conserative estimate for high known-0 bits. 1610 // More trickiness is possible, but this is sufficient for the 1611 // interesting case of alignment computation. 1612 KnownOne.clear(); 1613 unsigned TrailZ = KnownZero.countTrailingOnes() + 1614 KnownZero2.countTrailingOnes(); 1615 unsigned LeadZ = std::max(KnownZero.countLeadingOnes() + 1616 KnownZero2.countLeadingOnes(), 1617 BitWidth) - BitWidth; 1618 1619 TrailZ = std::min(TrailZ, BitWidth); 1620 LeadZ = std::min(LeadZ, BitWidth); 1621 KnownZero = APInt::getLowBitsSet(BitWidth, TrailZ) | 1622 APInt::getHighBitsSet(BitWidth, LeadZ); 1623 KnownZero &= Mask; 1624 return; 1625 } 1626 case ISD::UDIV: { 1627 // For the purposes of computing leading zeros we can conservatively 1628 // treat a udiv as a logical right shift by the power of 2 known to 1629 // be less than the denominator. 1630 APInt AllOnes = APInt::getAllOnesValue(BitWidth); 1631 ComputeMaskedBits(Op.getOperand(0), 1632 AllOnes, KnownZero2, KnownOne2, Depth+1); 1633 unsigned LeadZ = KnownZero2.countLeadingOnes(); 1634 1635 KnownOne2.clear(); 1636 KnownZero2.clear(); 1637 ComputeMaskedBits(Op.getOperand(1), 1638 AllOnes, KnownZero2, KnownOne2, Depth+1); 1639 unsigned RHSUnknownLeadingOnes = KnownOne2.countLeadingZeros(); 1640 if (RHSUnknownLeadingOnes != BitWidth) 1641 LeadZ = std::min(BitWidth, 1642 LeadZ + BitWidth - RHSUnknownLeadingOnes - 1); 1643 1644 KnownZero = APInt::getHighBitsSet(BitWidth, LeadZ) & Mask; 1645 return; 1646 } 1647 case ISD::SELECT: 1648 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero, KnownOne, Depth+1); 1649 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero2, KnownOne2, Depth+1); 1650 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1651 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1652 1653 // Only known if known in both the LHS and RHS. 1654 KnownOne &= KnownOne2; 1655 KnownZero &= KnownZero2; 1656 return; 1657 case ISD::SELECT_CC: 1658 ComputeMaskedBits(Op.getOperand(3), Mask, KnownZero, KnownOne, Depth+1); 1659 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero2, KnownOne2, Depth+1); 1660 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1661 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1662 1663 // Only known if known in both the LHS and RHS. 1664 KnownOne &= KnownOne2; 1665 KnownZero &= KnownZero2; 1666 return; 1667 case ISD::SADDO: 1668 case ISD::UADDO: 1669 case ISD::SSUBO: 1670 case ISD::USUBO: 1671 case ISD::SMULO: 1672 case ISD::UMULO: 1673 if (Op.getResNo() != 1) 1674 return; 1675 // The boolean result conforms to getBooleanContents. Fall through. 1676 case ISD::SETCC: 1677 // If we know the result of a setcc has the top bits zero, use this info. 1678 if (TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent && 1679 BitWidth > 1) 1680 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1); 1681 return; 1682 case ISD::SHL: 1683 // (shl X, C1) & C2 == 0 iff (X & C2 >>u C1) == 0 1684 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1685 unsigned ShAmt = SA->getZExtValue(); 1686 1687 // If the shift count is an invalid immediate, don't do anything. 1688 if (ShAmt >= BitWidth) 1689 return; 1690 1691 ComputeMaskedBits(Op.getOperand(0), Mask.lshr(ShAmt), 1692 KnownZero, KnownOne, Depth+1); 1693 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1694 KnownZero <<= ShAmt; 1695 KnownOne <<= ShAmt; 1696 // low bits known zero. 1697 KnownZero |= APInt::getLowBitsSet(BitWidth, ShAmt); 1698 } 1699 return; 1700 case ISD::SRL: 1701 // (ushr X, C1) & C2 == 0 iff (-1 >> C1) & C2 == 0 1702 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1703 unsigned ShAmt = SA->getZExtValue(); 1704 1705 // If the shift count is an invalid immediate, don't do anything. 1706 if (ShAmt >= BitWidth) 1707 return; 1708 1709 ComputeMaskedBits(Op.getOperand(0), (Mask << ShAmt), 1710 KnownZero, KnownOne, Depth+1); 1711 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1712 KnownZero = KnownZero.lshr(ShAmt); 1713 KnownOne = KnownOne.lshr(ShAmt); 1714 1715 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt) & Mask; 1716 KnownZero |= HighBits; // High bits known zero. 1717 } 1718 return; 1719 case ISD::SRA: 1720 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1721 unsigned ShAmt = SA->getZExtValue(); 1722 1723 // If the shift count is an invalid immediate, don't do anything. 1724 if (ShAmt >= BitWidth) 1725 return; 1726 1727 APInt InDemandedMask = (Mask << ShAmt); 1728 // If any of the demanded bits are produced by the sign extension, we also 1729 // demand the input sign bit. 1730 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt) & Mask; 1731 if (HighBits.getBoolValue()) 1732 InDemandedMask |= APInt::getSignBit(BitWidth); 1733 1734 ComputeMaskedBits(Op.getOperand(0), InDemandedMask, KnownZero, KnownOne, 1735 Depth+1); 1736 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1737 KnownZero = KnownZero.lshr(ShAmt); 1738 KnownOne = KnownOne.lshr(ShAmt); 1739 1740 // Handle the sign bits. 1741 APInt SignBit = APInt::getSignBit(BitWidth); 1742 SignBit = SignBit.lshr(ShAmt); // Adjust to where it is now in the mask. 1743 1744 if (KnownZero.intersects(SignBit)) { 1745 KnownZero |= HighBits; // New bits are known zero. 1746 } else if (KnownOne.intersects(SignBit)) { 1747 KnownOne |= HighBits; // New bits are known one. 1748 } 1749 } 1750 return; 1751 case ISD::SIGN_EXTEND_INREG: { 1752 MVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1753 unsigned EBits = EVT.getSizeInBits(); 1754 1755 // Sign extension. Compute the demanded bits in the result that are not 1756 // present in the input. 1757 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - EBits) & Mask; 1758 1759 APInt InSignBit = APInt::getSignBit(EBits); 1760 APInt InputDemandedBits = Mask & APInt::getLowBitsSet(BitWidth, EBits); 1761 1762 // If the sign extended bits are demanded, we know that the sign 1763 // bit is demanded. 1764 InSignBit.zext(BitWidth); 1765 if (NewBits.getBoolValue()) 1766 InputDemandedBits |= InSignBit; 1767 1768 ComputeMaskedBits(Op.getOperand(0), InputDemandedBits, 1769 KnownZero, KnownOne, Depth+1); 1770 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1771 1772 // If the sign bit of the input is known set or clear, then we know the 1773 // top bits of the result. 1774 if (KnownZero.intersects(InSignBit)) { // Input sign bit known clear 1775 KnownZero |= NewBits; 1776 KnownOne &= ~NewBits; 1777 } else if (KnownOne.intersects(InSignBit)) { // Input sign bit known set 1778 KnownOne |= NewBits; 1779 KnownZero &= ~NewBits; 1780 } else { // Input sign bit unknown 1781 KnownZero &= ~NewBits; 1782 KnownOne &= ~NewBits; 1783 } 1784 return; 1785 } 1786 case ISD::CTTZ: 1787 case ISD::CTLZ: 1788 case ISD::CTPOP: { 1789 unsigned LowBits = Log2_32(BitWidth)+1; 1790 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - LowBits); 1791 KnownOne.clear(); 1792 return; 1793 } 1794 case ISD::LOAD: { 1795 if (ISD::isZEXTLoad(Op.getNode())) { 1796 LoadSDNode *LD = cast<LoadSDNode>(Op); 1797 MVT VT = LD->getMemoryVT(); 1798 unsigned MemBits = VT.getSizeInBits(); 1799 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits) & Mask; 1800 } 1801 return; 1802 } 1803 case ISD::ZERO_EXTEND: { 1804 MVT InVT = Op.getOperand(0).getValueType(); 1805 unsigned InBits = InVT.getSizeInBits(); 1806 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - InBits) & Mask; 1807 APInt InMask = Mask; 1808 InMask.trunc(InBits); 1809 KnownZero.trunc(InBits); 1810 KnownOne.trunc(InBits); 1811 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1812 KnownZero.zext(BitWidth); 1813 KnownOne.zext(BitWidth); 1814 KnownZero |= NewBits; 1815 return; 1816 } 1817 case ISD::SIGN_EXTEND: { 1818 MVT InVT = Op.getOperand(0).getValueType(); 1819 unsigned InBits = InVT.getSizeInBits(); 1820 APInt InSignBit = APInt::getSignBit(InBits); 1821 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - InBits) & Mask; 1822 APInt InMask = Mask; 1823 InMask.trunc(InBits); 1824 1825 // If any of the sign extended bits are demanded, we know that the sign 1826 // bit is demanded. Temporarily set this bit in the mask for our callee. 1827 if (NewBits.getBoolValue()) 1828 InMask |= InSignBit; 1829 1830 KnownZero.trunc(InBits); 1831 KnownOne.trunc(InBits); 1832 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1833 1834 // Note if the sign bit is known to be zero or one. 1835 bool SignBitKnownZero = KnownZero.isNegative(); 1836 bool SignBitKnownOne = KnownOne.isNegative(); 1837 assert(!(SignBitKnownZero && SignBitKnownOne) && 1838 "Sign bit can't be known to be both zero and one!"); 1839 1840 // If the sign bit wasn't actually demanded by our caller, we don't 1841 // want it set in the KnownZero and KnownOne result values. Reset the 1842 // mask and reapply it to the result values. 1843 InMask = Mask; 1844 InMask.trunc(InBits); 1845 KnownZero &= InMask; 1846 KnownOne &= InMask; 1847 1848 KnownZero.zext(BitWidth); 1849 KnownOne.zext(BitWidth); 1850 1851 // If the sign bit is known zero or one, the top bits match. 1852 if (SignBitKnownZero) 1853 KnownZero |= NewBits; 1854 else if (SignBitKnownOne) 1855 KnownOne |= NewBits; 1856 return; 1857 } 1858 case ISD::ANY_EXTEND: { 1859 MVT InVT = Op.getOperand(0).getValueType(); 1860 unsigned InBits = InVT.getSizeInBits(); 1861 APInt InMask = Mask; 1862 InMask.trunc(InBits); 1863 KnownZero.trunc(InBits); 1864 KnownOne.trunc(InBits); 1865 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1866 KnownZero.zext(BitWidth); 1867 KnownOne.zext(BitWidth); 1868 return; 1869 } 1870 case ISD::TRUNCATE: { 1871 MVT InVT = Op.getOperand(0).getValueType(); 1872 unsigned InBits = InVT.getSizeInBits(); 1873 APInt InMask = Mask; 1874 InMask.zext(InBits); 1875 KnownZero.zext(InBits); 1876 KnownOne.zext(InBits); 1877 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1878 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1879 KnownZero.trunc(BitWidth); 1880 KnownOne.trunc(BitWidth); 1881 break; 1882 } 1883 case ISD::AssertZext: { 1884 MVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1885 APInt InMask = APInt::getLowBitsSet(BitWidth, VT.getSizeInBits()); 1886 ComputeMaskedBits(Op.getOperand(0), Mask & InMask, KnownZero, 1887 KnownOne, Depth+1); 1888 KnownZero |= (~InMask) & Mask; 1889 return; 1890 } 1891 case ISD::FGETSIGN: 1892 // All bits are zero except the low bit. 1893 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - 1); 1894 return; 1895 1896 case ISD::SUB: { 1897 if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) { 1898 // We know that the top bits of C-X are clear if X contains less bits 1899 // than C (i.e. no wrap-around can happen). For example, 20-X is 1900 // positive if we can prove that X is >= 0 and < 16. 1901 if (CLHS->getAPIntValue().isNonNegative()) { 1902 unsigned NLZ = (CLHS->getAPIntValue()+1).countLeadingZeros(); 1903 // NLZ can't be BitWidth with no sign bit 1904 APInt MaskV = APInt::getHighBitsSet(BitWidth, NLZ+1); 1905 ComputeMaskedBits(Op.getOperand(1), MaskV, KnownZero2, KnownOne2, 1906 Depth+1); 1907 1908 // If all of the MaskV bits are known to be zero, then we know the 1909 // output top bits are zero, because we now know that the output is 1910 // from [0-C]. 1911 if ((KnownZero2 & MaskV) == MaskV) { 1912 unsigned NLZ2 = CLHS->getAPIntValue().countLeadingZeros(); 1913 // Top bits known zero. 1914 KnownZero = APInt::getHighBitsSet(BitWidth, NLZ2) & Mask; 1915 } 1916 } 1917 } 1918 } 1919 // fall through 1920 case ISD::ADD: { 1921 // Output known-0 bits are known if clear or set in both the low clear bits 1922 // common to both LHS & RHS. For example, 8+(X<<3) is known to have the 1923 // low 3 bits clear. 1924 APInt Mask2 = APInt::getLowBitsSet(BitWidth, Mask.countTrailingOnes()); 1925 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero2, KnownOne2, Depth+1); 1926 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1927 unsigned KnownZeroOut = KnownZero2.countTrailingOnes(); 1928 1929 ComputeMaskedBits(Op.getOperand(1), Mask2, KnownZero2, KnownOne2, Depth+1); 1930 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1931 KnownZeroOut = std::min(KnownZeroOut, 1932 KnownZero2.countTrailingOnes()); 1933 1934 KnownZero |= APInt::getLowBitsSet(BitWidth, KnownZeroOut); 1935 return; 1936 } 1937 case ISD::SREM: 1938 if (ConstantSDNode *Rem = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1939 const APInt &RA = Rem->getAPIntValue(); 1940 if (RA.isPowerOf2() || (-RA).isPowerOf2()) { 1941 APInt LowBits = RA.isStrictlyPositive() ? (RA - 1) : ~RA; 1942 APInt Mask2 = LowBits | APInt::getSignBit(BitWidth); 1943 ComputeMaskedBits(Op.getOperand(0), Mask2,KnownZero2,KnownOne2,Depth+1); 1944 1945 // If the sign bit of the first operand is zero, the sign bit of 1946 // the result is zero. If the first operand has no one bits below 1947 // the second operand's single 1 bit, its sign will be zero. 1948 if (KnownZero2[BitWidth-1] || ((KnownZero2 & LowBits) == LowBits)) 1949 KnownZero2 |= ~LowBits; 1950 1951 KnownZero |= KnownZero2 & Mask; 1952 1953 assert((KnownZero & KnownOne) == 0&&"Bits known to be one AND zero?"); 1954 } 1955 } 1956 return; 1957 case ISD::UREM: { 1958 if (ConstantSDNode *Rem = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1959 const APInt &RA = Rem->getAPIntValue(); 1960 if (RA.isPowerOf2()) { 1961 APInt LowBits = (RA - 1); 1962 APInt Mask2 = LowBits & Mask; 1963 KnownZero |= ~LowBits & Mask; 1964 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero, KnownOne,Depth+1); 1965 assert((KnownZero & KnownOne) == 0&&"Bits known to be one AND zero?"); 1966 break; 1967 } 1968 } 1969 1970 // Since the result is less than or equal to either operand, any leading 1971 // zero bits in either operand must also exist in the result. 1972 APInt AllOnes = APInt::getAllOnesValue(BitWidth); 1973 ComputeMaskedBits(Op.getOperand(0), AllOnes, KnownZero, KnownOne, 1974 Depth+1); 1975 ComputeMaskedBits(Op.getOperand(1), AllOnes, KnownZero2, KnownOne2, 1976 Depth+1); 1977 1978 uint32_t Leaders = std::max(KnownZero.countLeadingOnes(), 1979 KnownZero2.countLeadingOnes()); 1980 KnownOne.clear(); 1981 KnownZero = APInt::getHighBitsSet(BitWidth, Leaders) & Mask; 1982 return; 1983 } 1984 default: 1985 // Allow the target to implement this method for its nodes. 1986 if (Op.getOpcode() >= ISD::BUILTIN_OP_END) { 1987 case ISD::INTRINSIC_WO_CHAIN: 1988 case ISD::INTRINSIC_W_CHAIN: 1989 case ISD::INTRINSIC_VOID: 1990 TLI.computeMaskedBitsForTargetNode(Op, Mask, KnownZero, KnownOne, *this, 1991 Depth); 1992 } 1993 return; 1994 } 1995} 1996 1997/// ComputeNumSignBits - Return the number of times the sign bit of the 1998/// register is replicated into the other bits. We know that at least 1 bit 1999/// is always equal to the sign bit (itself), but other cases can give us 2000/// information. For example, immediately after an "SRA X, 2", we know that 2001/// the top 3 bits are all equal to each other, so we return 3. 2002unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, unsigned Depth) const{ 2003 MVT VT = Op.getValueType(); 2004 assert(VT.isInteger() && "Invalid VT!"); 2005 unsigned VTBits = VT.getSizeInBits(); 2006 unsigned Tmp, Tmp2; 2007 unsigned FirstAnswer = 1; 2008 2009 if (Depth == 6) 2010 return 1; // Limit search depth. 2011 2012 switch (Op.getOpcode()) { 2013 default: break; 2014 case ISD::AssertSext: 2015 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); 2016 return VTBits-Tmp+1; 2017 case ISD::AssertZext: 2018 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); 2019 return VTBits-Tmp; 2020 2021 case ISD::Constant: { 2022 const APInt &Val = cast<ConstantSDNode>(Op)->getAPIntValue(); 2023 // If negative, return # leading ones. 2024 if (Val.isNegative()) 2025 return Val.countLeadingOnes(); 2026 2027 // Return # leading zeros. 2028 return Val.countLeadingZeros(); 2029 } 2030 2031 case ISD::SIGN_EXTEND: 2032 Tmp = VTBits-Op.getOperand(0).getValueType().getSizeInBits(); 2033 return ComputeNumSignBits(Op.getOperand(0), Depth+1) + Tmp; 2034 2035 case ISD::SIGN_EXTEND_INREG: 2036 // Max of the input and what this extends. 2037 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); 2038 Tmp = VTBits-Tmp+1; 2039 2040 Tmp2 = ComputeNumSignBits(Op.getOperand(0), Depth+1); 2041 return std::max(Tmp, Tmp2); 2042 2043 case ISD::SRA: 2044 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 2045 // SRA X, C -> adds C sign bits. 2046 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 2047 Tmp += C->getZExtValue(); 2048 if (Tmp > VTBits) Tmp = VTBits; 2049 } 2050 return Tmp; 2051 case ISD::SHL: 2052 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 2053 // shl destroys sign bits. 2054 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 2055 if (C->getZExtValue() >= VTBits || // Bad shift. 2056 C->getZExtValue() >= Tmp) break; // Shifted all sign bits out. 2057 return Tmp - C->getZExtValue(); 2058 } 2059 break; 2060 case ISD::AND: 2061 case ISD::OR: 2062 case ISD::XOR: // NOT is handled here. 2063 // Logical binary ops preserve the number of sign bits at the worst. 2064 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 2065 if (Tmp != 1) { 2066 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 2067 FirstAnswer = std::min(Tmp, Tmp2); 2068 // We computed what we know about the sign bits as our first 2069 // answer. Now proceed to the generic code that uses 2070 // ComputeMaskedBits, and pick whichever answer is better. 2071 } 2072 break; 2073 2074 case ISD::SELECT: 2075 Tmp = ComputeNumSignBits(Op.getOperand(1), Depth+1); 2076 if (Tmp == 1) return 1; // Early out. 2077 Tmp2 = ComputeNumSignBits(Op.getOperand(2), Depth+1); 2078 return std::min(Tmp, Tmp2); 2079 2080 case ISD::SADDO: 2081 case ISD::UADDO: 2082 case ISD::SSUBO: 2083 case ISD::USUBO: 2084 case ISD::SMULO: 2085 case ISD::UMULO: 2086 if (Op.getResNo() != 1) 2087 break; 2088 // The boolean result conforms to getBooleanContents. Fall through. 2089 case ISD::SETCC: 2090 // If setcc returns 0/-1, all bits are sign bits. 2091 if (TLI.getBooleanContents() == 2092 TargetLowering::ZeroOrNegativeOneBooleanContent) 2093 return VTBits; 2094 break; 2095 case ISD::ROTL: 2096 case ISD::ROTR: 2097 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 2098 unsigned RotAmt = C->getZExtValue() & (VTBits-1); 2099 2100 // Handle rotate right by N like a rotate left by 32-N. 2101 if (Op.getOpcode() == ISD::ROTR) 2102 RotAmt = (VTBits-RotAmt) & (VTBits-1); 2103 2104 // If we aren't rotating out all of the known-in sign bits, return the 2105 // number that are left. This handles rotl(sext(x), 1) for example. 2106 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 2107 if (Tmp > RotAmt+1) return Tmp-RotAmt; 2108 } 2109 break; 2110 case ISD::ADD: 2111 // Add can have at most one carry bit. Thus we know that the output 2112 // is, at worst, one more bit than the inputs. 2113 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 2114 if (Tmp == 1) return 1; // Early out. 2115 2116 // Special case decrementing a value (ADD X, -1): 2117 if (ConstantSDNode *CRHS = dyn_cast<ConstantSDNode>(Op.getOperand(1))) 2118 if (CRHS->isAllOnesValue()) { 2119 APInt KnownZero, KnownOne; 2120 APInt Mask = APInt::getAllOnesValue(VTBits); 2121 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1); 2122 2123 // If the input is known to be 0 or 1, the output is 0/-1, which is all 2124 // sign bits set. 2125 if ((KnownZero | APInt(VTBits, 1)) == Mask) 2126 return VTBits; 2127 2128 // If we are subtracting one from a positive number, there is no carry 2129 // out of the result. 2130 if (KnownZero.isNegative()) 2131 return Tmp; 2132 } 2133 2134 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 2135 if (Tmp2 == 1) return 1; 2136 return std::min(Tmp, Tmp2)-1; 2137 break; 2138 2139 case ISD::SUB: 2140 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 2141 if (Tmp2 == 1) return 1; 2142 2143 // Handle NEG. 2144 if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) 2145 if (CLHS->isNullValue()) { 2146 APInt KnownZero, KnownOne; 2147 APInt Mask = APInt::getAllOnesValue(VTBits); 2148 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 2149 // If the input is known to be 0 or 1, the output is 0/-1, which is all 2150 // sign bits set. 2151 if ((KnownZero | APInt(VTBits, 1)) == Mask) 2152 return VTBits; 2153 2154 // If the input is known to be positive (the sign bit is known clear), 2155 // the output of the NEG has the same number of sign bits as the input. 2156 if (KnownZero.isNegative()) 2157 return Tmp2; 2158 2159 // Otherwise, we treat this like a SUB. 2160 } 2161 2162 // Sub can have at most one carry bit. Thus we know that the output 2163 // is, at worst, one more bit than the inputs. 2164 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 2165 if (Tmp == 1) return 1; // Early out. 2166 return std::min(Tmp, Tmp2)-1; 2167 break; 2168 case ISD::TRUNCATE: 2169 // FIXME: it's tricky to do anything useful for this, but it is an important 2170 // case for targets like X86. 2171 break; 2172 } 2173 2174 // Handle LOADX separately here. EXTLOAD case will fallthrough. 2175 if (Op.getOpcode() == ISD::LOAD) { 2176 LoadSDNode *LD = cast<LoadSDNode>(Op); 2177 unsigned ExtType = LD->getExtensionType(); 2178 switch (ExtType) { 2179 default: break; 2180 case ISD::SEXTLOAD: // '17' bits known 2181 Tmp = LD->getMemoryVT().getSizeInBits(); 2182 return VTBits-Tmp+1; 2183 case ISD::ZEXTLOAD: // '16' bits known 2184 Tmp = LD->getMemoryVT().getSizeInBits(); 2185 return VTBits-Tmp; 2186 } 2187 } 2188 2189 // Allow the target to implement this method for its nodes. 2190 if (Op.getOpcode() >= ISD::BUILTIN_OP_END || 2191 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 2192 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 2193 Op.getOpcode() == ISD::INTRINSIC_VOID) { 2194 unsigned NumBits = TLI.ComputeNumSignBitsForTargetNode(Op, Depth); 2195 if (NumBits > 1) FirstAnswer = std::max(FirstAnswer, NumBits); 2196 } 2197 2198 // Finally, if we can prove that the top bits of the result are 0's or 1's, 2199 // use this information. 2200 APInt KnownZero, KnownOne; 2201 APInt Mask = APInt::getAllOnesValue(VTBits); 2202 ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth); 2203 2204 if (KnownZero.isNegative()) { // sign bit is 0 2205 Mask = KnownZero; 2206 } else if (KnownOne.isNegative()) { // sign bit is 1; 2207 Mask = KnownOne; 2208 } else { 2209 // Nothing known. 2210 return FirstAnswer; 2211 } 2212 2213 // Okay, we know that the sign bit in Mask is set. Use CLZ to determine 2214 // the number of identical bits in the top of the input value. 2215 Mask = ~Mask; 2216 Mask <<= Mask.getBitWidth()-VTBits; 2217 // Return # leading zeros. We use 'min' here in case Val was zero before 2218 // shifting. We don't want to return '64' as for an i32 "0". 2219 return std::max(FirstAnswer, std::min(VTBits, Mask.countLeadingZeros())); 2220} 2221 2222 2223bool SelectionDAG::isVerifiedDebugInfoDesc(SDValue Op) const { 2224 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op); 2225 if (!GA) return false; 2226 if (GA->getOffset() != 0) return false; 2227 GlobalVariable *GV = dyn_cast<GlobalVariable>(GA->getGlobal()); 2228 if (!GV) return false; 2229 MachineModuleInfo *MMI = getMachineModuleInfo(); 2230 return MMI && MMI->hasDebugInfo(); 2231} 2232 2233 2234/// getShuffleScalarElt - Returns the scalar element that will make up the ith 2235/// element of the result of the vector shuffle. 2236SDValue SelectionDAG::getShuffleScalarElt(const ShuffleVectorSDNode *N, 2237 unsigned i) { 2238 MVT VT = N->getValueType(0); 2239 DebugLoc dl = N->getDebugLoc(); 2240 if (N->getMaskElt(i) < 0) 2241 return getUNDEF(VT.getVectorElementType()); 2242 unsigned Index = N->getMaskElt(i); 2243 unsigned NumElems = VT.getVectorNumElements(); 2244 SDValue V = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1); 2245 Index %= NumElems; 2246 2247 if (V.getOpcode() == ISD::BIT_CONVERT) { 2248 V = V.getOperand(0); 2249 MVT VVT = V.getValueType(); 2250 if (!VVT.isVector() || VVT.getVectorNumElements() != (unsigned)NumElems) 2251 return SDValue(); 2252 } 2253 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) 2254 return (Index == 0) ? V.getOperand(0) 2255 : getUNDEF(VT.getVectorElementType()); 2256 if (V.getOpcode() == ISD::BUILD_VECTOR) 2257 return V.getOperand(Index); 2258 if (const ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(V)) 2259 return getShuffleScalarElt(SVN, Index); 2260 return SDValue(); 2261} 2262 2263 2264/// getNode - Gets or creates the specified node. 2265/// 2266SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT) { 2267 FoldingSetNodeID ID; 2268 AddNodeIDNode(ID, Opcode, getVTList(VT), 0, 0); 2269 void *IP = 0; 2270 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2271 return SDValue(E, 0); 2272 SDNode *N = NodeAllocator.Allocate<SDNode>(); 2273 new (N) SDNode(Opcode, DL, getVTList(VT)); 2274 CSEMap.InsertNode(N, IP); 2275 2276 AllNodes.push_back(N); 2277#ifndef NDEBUG 2278 VerifyNode(N); 2279#endif 2280 return SDValue(N, 0); 2281} 2282 2283SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, 2284 MVT VT, SDValue Operand) { 2285 // Constant fold unary operations with an integer constant operand. 2286 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Operand.getNode())) { 2287 const APInt &Val = C->getAPIntValue(); 2288 unsigned BitWidth = VT.getSizeInBits(); 2289 switch (Opcode) { 2290 default: break; 2291 case ISD::SIGN_EXTEND: 2292 return getConstant(APInt(Val).sextOrTrunc(BitWidth), VT); 2293 case ISD::ANY_EXTEND: 2294 case ISD::ZERO_EXTEND: 2295 case ISD::TRUNCATE: 2296 return getConstant(APInt(Val).zextOrTrunc(BitWidth), VT); 2297 case ISD::UINT_TO_FP: 2298 case ISD::SINT_TO_FP: { 2299 const uint64_t zero[] = {0, 0}; 2300 // No compile time operations on this type. 2301 if (VT==MVT::ppcf128) 2302 break; 2303 APFloat apf = APFloat(APInt(BitWidth, 2, zero)); 2304 (void)apf.convertFromAPInt(Val, 2305 Opcode==ISD::SINT_TO_FP, 2306 APFloat::rmNearestTiesToEven); 2307 return getConstantFP(apf, VT); 2308 } 2309 case ISD::BIT_CONVERT: 2310 if (VT == MVT::f32 && C->getValueType(0) == MVT::i32) 2311 return getConstantFP(Val.bitsToFloat(), VT); 2312 else if (VT == MVT::f64 && C->getValueType(0) == MVT::i64) 2313 return getConstantFP(Val.bitsToDouble(), VT); 2314 break; 2315 case ISD::BSWAP: 2316 return getConstant(Val.byteSwap(), VT); 2317 case ISD::CTPOP: 2318 return getConstant(Val.countPopulation(), VT); 2319 case ISD::CTLZ: 2320 return getConstant(Val.countLeadingZeros(), VT); 2321 case ISD::CTTZ: 2322 return getConstant(Val.countTrailingZeros(), VT); 2323 } 2324 } 2325 2326 // Constant fold unary operations with a floating point constant operand. 2327 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Operand.getNode())) { 2328 APFloat V = C->getValueAPF(); // make copy 2329 if (VT != MVT::ppcf128 && Operand.getValueType() != MVT::ppcf128) { 2330 switch (Opcode) { 2331 case ISD::FNEG: 2332 V.changeSign(); 2333 return getConstantFP(V, VT); 2334 case ISD::FABS: 2335 V.clearSign(); 2336 return getConstantFP(V, VT); 2337 case ISD::FP_ROUND: 2338 case ISD::FP_EXTEND: { 2339 bool ignored; 2340 // This can return overflow, underflow, or inexact; we don't care. 2341 // FIXME need to be more flexible about rounding mode. 2342 (void)V.convert(*MVTToAPFloatSemantics(VT), 2343 APFloat::rmNearestTiesToEven, &ignored); 2344 return getConstantFP(V, VT); 2345 } 2346 case ISD::FP_TO_SINT: 2347 case ISD::FP_TO_UINT: { 2348 integerPart x[2]; 2349 bool ignored; 2350 assert(integerPartWidth >= 64); 2351 // FIXME need to be more flexible about rounding mode. 2352 APFloat::opStatus s = V.convertToInteger(x, VT.getSizeInBits(), 2353 Opcode==ISD::FP_TO_SINT, 2354 APFloat::rmTowardZero, &ignored); 2355 if (s==APFloat::opInvalidOp) // inexact is OK, in fact usual 2356 break; 2357 APInt api(VT.getSizeInBits(), 2, x); 2358 return getConstant(api, VT); 2359 } 2360 case ISD::BIT_CONVERT: 2361 if (VT == MVT::i32 && C->getValueType(0) == MVT::f32) 2362 return getConstant((uint32_t)V.bitcastToAPInt().getZExtValue(), VT); 2363 else if (VT == MVT::i64 && C->getValueType(0) == MVT::f64) 2364 return getConstant(V.bitcastToAPInt().getZExtValue(), VT); 2365 break; 2366 } 2367 } 2368 } 2369 2370 unsigned OpOpcode = Operand.getNode()->getOpcode(); 2371 switch (Opcode) { 2372 case ISD::TokenFactor: 2373 case ISD::MERGE_VALUES: 2374 case ISD::CONCAT_VECTORS: 2375 return Operand; // Factor, merge or concat of one node? No need. 2376 case ISD::FP_ROUND: llvm_unreachable("Invalid method to make FP_ROUND node"); 2377 case ISD::FP_EXTEND: 2378 assert(VT.isFloatingPoint() && 2379 Operand.getValueType().isFloatingPoint() && "Invalid FP cast!"); 2380 if (Operand.getValueType() == VT) return Operand; // noop conversion. 2381 if (Operand.getOpcode() == ISD::UNDEF) 2382 return getUNDEF(VT); 2383 break; 2384 case ISD::SIGN_EXTEND: 2385 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2386 "Invalid SIGN_EXTEND!"); 2387 if (Operand.getValueType() == VT) return Operand; // noop extension 2388 assert(Operand.getValueType().bitsLT(VT) 2389 && "Invalid sext node, dst < src!"); 2390 if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND) 2391 return getNode(OpOpcode, DL, VT, Operand.getNode()->getOperand(0)); 2392 break; 2393 case ISD::ZERO_EXTEND: 2394 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2395 "Invalid ZERO_EXTEND!"); 2396 if (Operand.getValueType() == VT) return Operand; // noop extension 2397 assert(Operand.getValueType().bitsLT(VT) 2398 && "Invalid zext node, dst < src!"); 2399 if (OpOpcode == ISD::ZERO_EXTEND) // (zext (zext x)) -> (zext x) 2400 return getNode(ISD::ZERO_EXTEND, DL, VT, 2401 Operand.getNode()->getOperand(0)); 2402 break; 2403 case ISD::ANY_EXTEND: 2404 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2405 "Invalid ANY_EXTEND!"); 2406 if (Operand.getValueType() == VT) return Operand; // noop extension 2407 assert(Operand.getValueType().bitsLT(VT) 2408 && "Invalid anyext node, dst < src!"); 2409 if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND) 2410 // (ext (zext x)) -> (zext x) and (ext (sext x)) -> (sext x) 2411 return getNode(OpOpcode, DL, VT, Operand.getNode()->getOperand(0)); 2412 break; 2413 case ISD::TRUNCATE: 2414 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2415 "Invalid TRUNCATE!"); 2416 if (Operand.getValueType() == VT) return Operand; // noop truncate 2417 assert(Operand.getValueType().bitsGT(VT) 2418 && "Invalid truncate node, src < dst!"); 2419 if (OpOpcode == ISD::TRUNCATE) 2420 return getNode(ISD::TRUNCATE, DL, VT, Operand.getNode()->getOperand(0)); 2421 else if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND || 2422 OpOpcode == ISD::ANY_EXTEND) { 2423 // If the source is smaller than the dest, we still need an extend. 2424 if (Operand.getNode()->getOperand(0).getValueType().bitsLT(VT)) 2425 return getNode(OpOpcode, DL, VT, Operand.getNode()->getOperand(0)); 2426 else if (Operand.getNode()->getOperand(0).getValueType().bitsGT(VT)) 2427 return getNode(ISD::TRUNCATE, DL, VT, Operand.getNode()->getOperand(0)); 2428 else 2429 return Operand.getNode()->getOperand(0); 2430 } 2431 break; 2432 case ISD::BIT_CONVERT: 2433 // Basic sanity checking. 2434 assert(VT.getSizeInBits() == Operand.getValueType().getSizeInBits() 2435 && "Cannot BIT_CONVERT between types of different sizes!"); 2436 if (VT == Operand.getValueType()) return Operand; // noop conversion. 2437 if (OpOpcode == ISD::BIT_CONVERT) // bitconv(bitconv(x)) -> bitconv(x) 2438 return getNode(ISD::BIT_CONVERT, DL, VT, Operand.getOperand(0)); 2439 if (OpOpcode == ISD::UNDEF) 2440 return getUNDEF(VT); 2441 break; 2442 case ISD::SCALAR_TO_VECTOR: 2443 assert(VT.isVector() && !Operand.getValueType().isVector() && 2444 (VT.getVectorElementType() == Operand.getValueType() || 2445 (VT.getVectorElementType().isInteger() && 2446 Operand.getValueType().isInteger() && 2447 VT.getVectorElementType().bitsLE(Operand.getValueType()))) && 2448 "Illegal SCALAR_TO_VECTOR node!"); 2449 if (OpOpcode == ISD::UNDEF) 2450 return getUNDEF(VT); 2451 // scalar_to_vector(extract_vector_elt V, 0) -> V, top bits are undefined. 2452 if (OpOpcode == ISD::EXTRACT_VECTOR_ELT && 2453 isa<ConstantSDNode>(Operand.getOperand(1)) && 2454 Operand.getConstantOperandVal(1) == 0 && 2455 Operand.getOperand(0).getValueType() == VT) 2456 return Operand.getOperand(0); 2457 break; 2458 case ISD::FNEG: 2459 // -(X-Y) -> (Y-X) is unsafe because when X==Y, -0.0 != +0.0 2460 if (UnsafeFPMath && OpOpcode == ISD::FSUB) 2461 return getNode(ISD::FSUB, DL, VT, Operand.getNode()->getOperand(1), 2462 Operand.getNode()->getOperand(0)); 2463 if (OpOpcode == ISD::FNEG) // --X -> X 2464 return Operand.getNode()->getOperand(0); 2465 break; 2466 case ISD::FABS: 2467 if (OpOpcode == ISD::FNEG) // abs(-X) -> abs(X) 2468 return getNode(ISD::FABS, DL, VT, Operand.getNode()->getOperand(0)); 2469 break; 2470 } 2471 2472 SDNode *N; 2473 SDVTList VTs = getVTList(VT); 2474 if (VT != MVT::Flag) { // Don't CSE flag producing nodes 2475 FoldingSetNodeID ID; 2476 SDValue Ops[1] = { Operand }; 2477 AddNodeIDNode(ID, Opcode, VTs, Ops, 1); 2478 void *IP = 0; 2479 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2480 return SDValue(E, 0); 2481 N = NodeAllocator.Allocate<UnarySDNode>(); 2482 new (N) UnarySDNode(Opcode, DL, VTs, Operand); 2483 CSEMap.InsertNode(N, IP); 2484 } else { 2485 N = NodeAllocator.Allocate<UnarySDNode>(); 2486 new (N) UnarySDNode(Opcode, DL, VTs, Operand); 2487 } 2488 2489 AllNodes.push_back(N); 2490#ifndef NDEBUG 2491 VerifyNode(N); 2492#endif 2493 return SDValue(N, 0); 2494} 2495 2496SDValue SelectionDAG::FoldConstantArithmetic(unsigned Opcode, 2497 MVT VT, 2498 ConstantSDNode *Cst1, 2499 ConstantSDNode *Cst2) { 2500 const APInt &C1 = Cst1->getAPIntValue(), &C2 = Cst2->getAPIntValue(); 2501 2502 switch (Opcode) { 2503 case ISD::ADD: return getConstant(C1 + C2, VT); 2504 case ISD::SUB: return getConstant(C1 - C2, VT); 2505 case ISD::MUL: return getConstant(C1 * C2, VT); 2506 case ISD::UDIV: 2507 if (C2.getBoolValue()) return getConstant(C1.udiv(C2), VT); 2508 break; 2509 case ISD::UREM: 2510 if (C2.getBoolValue()) return getConstant(C1.urem(C2), VT); 2511 break; 2512 case ISD::SDIV: 2513 if (C2.getBoolValue()) return getConstant(C1.sdiv(C2), VT); 2514 break; 2515 case ISD::SREM: 2516 if (C2.getBoolValue()) return getConstant(C1.srem(C2), VT); 2517 break; 2518 case ISD::AND: return getConstant(C1 & C2, VT); 2519 case ISD::OR: return getConstant(C1 | C2, VT); 2520 case ISD::XOR: return getConstant(C1 ^ C2, VT); 2521 case ISD::SHL: return getConstant(C1 << C2, VT); 2522 case ISD::SRL: return getConstant(C1.lshr(C2), VT); 2523 case ISD::SRA: return getConstant(C1.ashr(C2), VT); 2524 case ISD::ROTL: return getConstant(C1.rotl(C2), VT); 2525 case ISD::ROTR: return getConstant(C1.rotr(C2), VT); 2526 default: break; 2527 } 2528 2529 return SDValue(); 2530} 2531 2532SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, 2533 SDValue N1, SDValue N2) { 2534 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 2535 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 2536 switch (Opcode) { 2537 default: break; 2538 case ISD::TokenFactor: 2539 assert(VT == MVT::Other && N1.getValueType() == MVT::Other && 2540 N2.getValueType() == MVT::Other && "Invalid token factor!"); 2541 // Fold trivial token factors. 2542 if (N1.getOpcode() == ISD::EntryToken) return N2; 2543 if (N2.getOpcode() == ISD::EntryToken) return N1; 2544 if (N1 == N2) return N1; 2545 break; 2546 case ISD::CONCAT_VECTORS: 2547 // A CONCAT_VECTOR with all operands BUILD_VECTOR can be simplified to 2548 // one big BUILD_VECTOR. 2549 if (N1.getOpcode() == ISD::BUILD_VECTOR && 2550 N2.getOpcode() == ISD::BUILD_VECTOR) { 2551 SmallVector<SDValue, 16> Elts(N1.getNode()->op_begin(), N1.getNode()->op_end()); 2552 Elts.insert(Elts.end(), N2.getNode()->op_begin(), N2.getNode()->op_end()); 2553 return getNode(ISD::BUILD_VECTOR, DL, VT, &Elts[0], Elts.size()); 2554 } 2555 break; 2556 case ISD::AND: 2557 assert(VT.isInteger() && N1.getValueType() == N2.getValueType() && 2558 N1.getValueType() == VT && "Binary operator types must match!"); 2559 // (X & 0) -> 0. This commonly occurs when legalizing i64 values, so it's 2560 // worth handling here. 2561 if (N2C && N2C->isNullValue()) 2562 return N2; 2563 if (N2C && N2C->isAllOnesValue()) // X & -1 -> X 2564 return N1; 2565 break; 2566 case ISD::OR: 2567 case ISD::XOR: 2568 case ISD::ADD: 2569 case ISD::SUB: 2570 assert(VT.isInteger() && N1.getValueType() == N2.getValueType() && 2571 N1.getValueType() == VT && "Binary operator types must match!"); 2572 // (X ^|+- 0) -> X. This commonly occurs when legalizing i64 values, so 2573 // it's worth handling here. 2574 if (N2C && N2C->isNullValue()) 2575 return N1; 2576 break; 2577 case ISD::UDIV: 2578 case ISD::UREM: 2579 case ISD::MULHU: 2580 case ISD::MULHS: 2581 case ISD::MUL: 2582 case ISD::SDIV: 2583 case ISD::SREM: 2584 assert(VT.isInteger() && "This operator does not apply to FP types!"); 2585 // fall through 2586 case ISD::FADD: 2587 case ISD::FSUB: 2588 case ISD::FMUL: 2589 case ISD::FDIV: 2590 case ISD::FREM: 2591 if (UnsafeFPMath) { 2592 if (Opcode == ISD::FADD) { 2593 // 0+x --> x 2594 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) 2595 if (CFP->getValueAPF().isZero()) 2596 return N2; 2597 // x+0 --> x 2598 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N2)) 2599 if (CFP->getValueAPF().isZero()) 2600 return N1; 2601 } else if (Opcode == ISD::FSUB) { 2602 // x-0 --> x 2603 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N2)) 2604 if (CFP->getValueAPF().isZero()) 2605 return N1; 2606 } 2607 } 2608 assert(N1.getValueType() == N2.getValueType() && 2609 N1.getValueType() == VT && "Binary operator types must match!"); 2610 break; 2611 case ISD::FCOPYSIGN: // N1 and result must match. N1/N2 need not match. 2612 assert(N1.getValueType() == VT && 2613 N1.getValueType().isFloatingPoint() && 2614 N2.getValueType().isFloatingPoint() && 2615 "Invalid FCOPYSIGN!"); 2616 break; 2617 case ISD::SHL: 2618 case ISD::SRA: 2619 case ISD::SRL: 2620 case ISD::ROTL: 2621 case ISD::ROTR: 2622 assert(VT == N1.getValueType() && 2623 "Shift operators return type must be the same as their first arg"); 2624 assert(VT.isInteger() && N2.getValueType().isInteger() && 2625 "Shifts only work on integers"); 2626 2627 // Always fold shifts of i1 values so the code generator doesn't need to 2628 // handle them. Since we know the size of the shift has to be less than the 2629 // size of the value, the shift/rotate count is guaranteed to be zero. 2630 if (VT == MVT::i1) 2631 return N1; 2632 break; 2633 case ISD::FP_ROUND_INREG: { 2634 MVT EVT = cast<VTSDNode>(N2)->getVT(); 2635 assert(VT == N1.getValueType() && "Not an inreg round!"); 2636 assert(VT.isFloatingPoint() && EVT.isFloatingPoint() && 2637 "Cannot FP_ROUND_INREG integer types"); 2638 assert(EVT.bitsLE(VT) && "Not rounding down!"); 2639 if (cast<VTSDNode>(N2)->getVT() == VT) return N1; // Not actually rounding. 2640 break; 2641 } 2642 case ISD::FP_ROUND: 2643 assert(VT.isFloatingPoint() && 2644 N1.getValueType().isFloatingPoint() && 2645 VT.bitsLE(N1.getValueType()) && 2646 isa<ConstantSDNode>(N2) && "Invalid FP_ROUND!"); 2647 if (N1.getValueType() == VT) return N1; // noop conversion. 2648 break; 2649 case ISD::AssertSext: 2650 case ISD::AssertZext: { 2651 MVT EVT = cast<VTSDNode>(N2)->getVT(); 2652 assert(VT == N1.getValueType() && "Not an inreg extend!"); 2653 assert(VT.isInteger() && EVT.isInteger() && 2654 "Cannot *_EXTEND_INREG FP types"); 2655 assert(EVT.bitsLE(VT) && "Not extending!"); 2656 if (VT == EVT) return N1; // noop assertion. 2657 break; 2658 } 2659 case ISD::SIGN_EXTEND_INREG: { 2660 MVT EVT = cast<VTSDNode>(N2)->getVT(); 2661 assert(VT == N1.getValueType() && "Not an inreg extend!"); 2662 assert(VT.isInteger() && EVT.isInteger() && 2663 "Cannot *_EXTEND_INREG FP types"); 2664 assert(EVT.bitsLE(VT) && "Not extending!"); 2665 if (EVT == VT) return N1; // Not actually extending 2666 2667 if (N1C) { 2668 APInt Val = N1C->getAPIntValue(); 2669 unsigned FromBits = cast<VTSDNode>(N2)->getVT().getSizeInBits(); 2670 Val <<= Val.getBitWidth()-FromBits; 2671 Val = Val.ashr(Val.getBitWidth()-FromBits); 2672 return getConstant(Val, VT); 2673 } 2674 break; 2675 } 2676 case ISD::EXTRACT_VECTOR_ELT: 2677 // EXTRACT_VECTOR_ELT of an UNDEF is an UNDEF. 2678 if (N1.getOpcode() == ISD::UNDEF) 2679 return getUNDEF(VT); 2680 2681 // EXTRACT_VECTOR_ELT of CONCAT_VECTORS is often formed while lowering is 2682 // expanding copies of large vectors from registers. 2683 if (N2C && 2684 N1.getOpcode() == ISD::CONCAT_VECTORS && 2685 N1.getNumOperands() > 0) { 2686 unsigned Factor = 2687 N1.getOperand(0).getValueType().getVectorNumElements(); 2688 return getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, 2689 N1.getOperand(N2C->getZExtValue() / Factor), 2690 getConstant(N2C->getZExtValue() % Factor, 2691 N2.getValueType())); 2692 } 2693 2694 // EXTRACT_VECTOR_ELT of BUILD_VECTOR is often formed while lowering is 2695 // expanding large vector constants. 2696 if (N2C && N1.getOpcode() == ISD::BUILD_VECTOR) { 2697 SDValue Elt = N1.getOperand(N2C->getZExtValue()); 2698 MVT VEltTy = N1.getValueType().getVectorElementType(); 2699 if (Elt.getValueType() != VEltTy) { 2700 // If the vector element type is not legal, the BUILD_VECTOR operands 2701 // are promoted and implicitly truncated. Make that explicit here. 2702 Elt = getNode(ISD::TRUNCATE, DL, VEltTy, Elt); 2703 } 2704 if (VT != VEltTy) { 2705 // If the vector element type is not legal, the EXTRACT_VECTOR_ELT 2706 // result is implicitly extended. 2707 Elt = getNode(ISD::ANY_EXTEND, DL, VT, Elt); 2708 } 2709 return Elt; 2710 } 2711 2712 // EXTRACT_VECTOR_ELT of INSERT_VECTOR_ELT is often formed when vector 2713 // operations are lowered to scalars. 2714 if (N1.getOpcode() == ISD::INSERT_VECTOR_ELT) { 2715 // If the indices are the same, return the inserted element. 2716 if (N1.getOperand(2) == N2) 2717 return N1.getOperand(1); 2718 // If the indices are known different, extract the element from 2719 // the original vector. 2720 else if (isa<ConstantSDNode>(N1.getOperand(2)) && 2721 isa<ConstantSDNode>(N2)) 2722 return getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, N1.getOperand(0), N2); 2723 } 2724 break; 2725 case ISD::EXTRACT_ELEMENT: 2726 assert(N2C && (unsigned)N2C->getZExtValue() < 2 && "Bad EXTRACT_ELEMENT!"); 2727 assert(!N1.getValueType().isVector() && !VT.isVector() && 2728 (N1.getValueType().isInteger() == VT.isInteger()) && 2729 "Wrong types for EXTRACT_ELEMENT!"); 2730 2731 // EXTRACT_ELEMENT of BUILD_PAIR is often formed while legalize is expanding 2732 // 64-bit integers into 32-bit parts. Instead of building the extract of 2733 // the BUILD_PAIR, only to have legalize rip it apart, just do it now. 2734 if (N1.getOpcode() == ISD::BUILD_PAIR) 2735 return N1.getOperand(N2C->getZExtValue()); 2736 2737 // EXTRACT_ELEMENT of a constant int is also very common. 2738 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) { 2739 unsigned ElementSize = VT.getSizeInBits(); 2740 unsigned Shift = ElementSize * N2C->getZExtValue(); 2741 APInt ShiftedVal = C->getAPIntValue().lshr(Shift); 2742 return getConstant(ShiftedVal.trunc(ElementSize), VT); 2743 } 2744 break; 2745 case ISD::EXTRACT_SUBVECTOR: 2746 if (N1.getValueType() == VT) // Trivial extraction. 2747 return N1; 2748 break; 2749 } 2750 2751 if (N1C) { 2752 if (N2C) { 2753 SDValue SV = FoldConstantArithmetic(Opcode, VT, N1C, N2C); 2754 if (SV.getNode()) return SV; 2755 } else { // Cannonicalize constant to RHS if commutative 2756 if (isCommutativeBinOp(Opcode)) { 2757 std::swap(N1C, N2C); 2758 std::swap(N1, N2); 2759 } 2760 } 2761 } 2762 2763 // Constant fold FP operations. 2764 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1.getNode()); 2765 ConstantFPSDNode *N2CFP = dyn_cast<ConstantFPSDNode>(N2.getNode()); 2766 if (N1CFP) { 2767 if (!N2CFP && isCommutativeBinOp(Opcode)) { 2768 // Cannonicalize constant to RHS if commutative 2769 std::swap(N1CFP, N2CFP); 2770 std::swap(N1, N2); 2771 } else if (N2CFP && VT != MVT::ppcf128) { 2772 APFloat V1 = N1CFP->getValueAPF(), V2 = N2CFP->getValueAPF(); 2773 APFloat::opStatus s; 2774 switch (Opcode) { 2775 case ISD::FADD: 2776 s = V1.add(V2, APFloat::rmNearestTiesToEven); 2777 if (s != APFloat::opInvalidOp) 2778 return getConstantFP(V1, VT); 2779 break; 2780 case ISD::FSUB: 2781 s = V1.subtract(V2, APFloat::rmNearestTiesToEven); 2782 if (s!=APFloat::opInvalidOp) 2783 return getConstantFP(V1, VT); 2784 break; 2785 case ISD::FMUL: 2786 s = V1.multiply(V2, APFloat::rmNearestTiesToEven); 2787 if (s!=APFloat::opInvalidOp) 2788 return getConstantFP(V1, VT); 2789 break; 2790 case ISD::FDIV: 2791 s = V1.divide(V2, APFloat::rmNearestTiesToEven); 2792 if (s!=APFloat::opInvalidOp && s!=APFloat::opDivByZero) 2793 return getConstantFP(V1, VT); 2794 break; 2795 case ISD::FREM : 2796 s = V1.mod(V2, APFloat::rmNearestTiesToEven); 2797 if (s!=APFloat::opInvalidOp && s!=APFloat::opDivByZero) 2798 return getConstantFP(V1, VT); 2799 break; 2800 case ISD::FCOPYSIGN: 2801 V1.copySign(V2); 2802 return getConstantFP(V1, VT); 2803 default: break; 2804 } 2805 } 2806 } 2807 2808 // Canonicalize an UNDEF to the RHS, even over a constant. 2809 if (N1.getOpcode() == ISD::UNDEF) { 2810 if (isCommutativeBinOp(Opcode)) { 2811 std::swap(N1, N2); 2812 } else { 2813 switch (Opcode) { 2814 case ISD::FP_ROUND_INREG: 2815 case ISD::SIGN_EXTEND_INREG: 2816 case ISD::SUB: 2817 case ISD::FSUB: 2818 case ISD::FDIV: 2819 case ISD::FREM: 2820 case ISD::SRA: 2821 return N1; // fold op(undef, arg2) -> undef 2822 case ISD::UDIV: 2823 case ISD::SDIV: 2824 case ISD::UREM: 2825 case ISD::SREM: 2826 case ISD::SRL: 2827 case ISD::SHL: 2828 if (!VT.isVector()) 2829 return getConstant(0, VT); // fold op(undef, arg2) -> 0 2830 // For vectors, we can't easily build an all zero vector, just return 2831 // the LHS. 2832 return N2; 2833 } 2834 } 2835 } 2836 2837 // Fold a bunch of operators when the RHS is undef. 2838 if (N2.getOpcode() == ISD::UNDEF) { 2839 switch (Opcode) { 2840 case ISD::XOR: 2841 if (N1.getOpcode() == ISD::UNDEF) 2842 // Handle undef ^ undef -> 0 special case. This is a common 2843 // idiom (misuse). 2844 return getConstant(0, VT); 2845 // fallthrough 2846 case ISD::ADD: 2847 case ISD::ADDC: 2848 case ISD::ADDE: 2849 case ISD::SUB: 2850 case ISD::UDIV: 2851 case ISD::SDIV: 2852 case ISD::UREM: 2853 case ISD::SREM: 2854 return N2; // fold op(arg1, undef) -> undef 2855 case ISD::FADD: 2856 case ISD::FSUB: 2857 case ISD::FMUL: 2858 case ISD::FDIV: 2859 case ISD::FREM: 2860 if (UnsafeFPMath) 2861 return N2; 2862 break; 2863 case ISD::MUL: 2864 case ISD::AND: 2865 case ISD::SRL: 2866 case ISD::SHL: 2867 if (!VT.isVector()) 2868 return getConstant(0, VT); // fold op(arg1, undef) -> 0 2869 // For vectors, we can't easily build an all zero vector, just return 2870 // the LHS. 2871 return N1; 2872 case ISD::OR: 2873 if (!VT.isVector()) 2874 return getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT); 2875 // For vectors, we can't easily build an all one vector, just return 2876 // the LHS. 2877 return N1; 2878 case ISD::SRA: 2879 return N1; 2880 } 2881 } 2882 2883 // Memoize this node if possible. 2884 SDNode *N; 2885 SDVTList VTs = getVTList(VT); 2886 if (VT != MVT::Flag) { 2887 SDValue Ops[] = { N1, N2 }; 2888 FoldingSetNodeID ID; 2889 AddNodeIDNode(ID, Opcode, VTs, Ops, 2); 2890 void *IP = 0; 2891 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2892 return SDValue(E, 0); 2893 N = NodeAllocator.Allocate<BinarySDNode>(); 2894 new (N) BinarySDNode(Opcode, DL, VTs, N1, N2); 2895 CSEMap.InsertNode(N, IP); 2896 } else { 2897 N = NodeAllocator.Allocate<BinarySDNode>(); 2898 new (N) BinarySDNode(Opcode, DL, VTs, N1, N2); 2899 } 2900 2901 AllNodes.push_back(N); 2902#ifndef NDEBUG 2903 VerifyNode(N); 2904#endif 2905 return SDValue(N, 0); 2906} 2907 2908SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, 2909 SDValue N1, SDValue N2, SDValue N3) { 2910 // Perform various simplifications. 2911 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 2912 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 2913 switch (Opcode) { 2914 case ISD::CONCAT_VECTORS: 2915 // A CONCAT_VECTOR with all operands BUILD_VECTOR can be simplified to 2916 // one big BUILD_VECTOR. 2917 if (N1.getOpcode() == ISD::BUILD_VECTOR && 2918 N2.getOpcode() == ISD::BUILD_VECTOR && 2919 N3.getOpcode() == ISD::BUILD_VECTOR) { 2920 SmallVector<SDValue, 16> Elts(N1.getNode()->op_begin(), N1.getNode()->op_end()); 2921 Elts.insert(Elts.end(), N2.getNode()->op_begin(), N2.getNode()->op_end()); 2922 Elts.insert(Elts.end(), N3.getNode()->op_begin(), N3.getNode()->op_end()); 2923 return getNode(ISD::BUILD_VECTOR, DL, VT, &Elts[0], Elts.size()); 2924 } 2925 break; 2926 case ISD::SETCC: { 2927 // Use FoldSetCC to simplify SETCC's. 2928 SDValue Simp = FoldSetCC(VT, N1, N2, cast<CondCodeSDNode>(N3)->get(), DL); 2929 if (Simp.getNode()) return Simp; 2930 break; 2931 } 2932 case ISD::SELECT: 2933 if (N1C) { 2934 if (N1C->getZExtValue()) 2935 return N2; // select true, X, Y -> X 2936 else 2937 return N3; // select false, X, Y -> Y 2938 } 2939 2940 if (N2 == N3) return N2; // select C, X, X -> X 2941 break; 2942 case ISD::BRCOND: 2943 if (N2C) { 2944 if (N2C->getZExtValue()) // Unconditional branch 2945 return getNode(ISD::BR, DL, MVT::Other, N1, N3); 2946 else 2947 return N1; // Never-taken branch 2948 } 2949 break; 2950 case ISD::VECTOR_SHUFFLE: 2951 llvm_unreachable("should use getVectorShuffle constructor!"); 2952 break; 2953 case ISD::BIT_CONVERT: 2954 // Fold bit_convert nodes from a type to themselves. 2955 if (N1.getValueType() == VT) 2956 return N1; 2957 break; 2958 } 2959 2960 // Memoize node if it doesn't produce a flag. 2961 SDNode *N; 2962 SDVTList VTs = getVTList(VT); 2963 if (VT != MVT::Flag) { 2964 SDValue Ops[] = { N1, N2, N3 }; 2965 FoldingSetNodeID ID; 2966 AddNodeIDNode(ID, Opcode, VTs, Ops, 3); 2967 void *IP = 0; 2968 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2969 return SDValue(E, 0); 2970 N = NodeAllocator.Allocate<TernarySDNode>(); 2971 new (N) TernarySDNode(Opcode, DL, VTs, N1, N2, N3); 2972 CSEMap.InsertNode(N, IP); 2973 } else { 2974 N = NodeAllocator.Allocate<TernarySDNode>(); 2975 new (N) TernarySDNode(Opcode, DL, VTs, N1, N2, N3); 2976 } 2977 AllNodes.push_back(N); 2978#ifndef NDEBUG 2979 VerifyNode(N); 2980#endif 2981 return SDValue(N, 0); 2982} 2983 2984SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, 2985 SDValue N1, SDValue N2, SDValue N3, 2986 SDValue N4) { 2987 SDValue Ops[] = { N1, N2, N3, N4 }; 2988 return getNode(Opcode, DL, VT, Ops, 4); 2989} 2990 2991SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, 2992 SDValue N1, SDValue N2, SDValue N3, 2993 SDValue N4, SDValue N5) { 2994 SDValue Ops[] = { N1, N2, N3, N4, N5 }; 2995 return getNode(Opcode, DL, VT, Ops, 5); 2996} 2997 2998/// getMemsetValue - Vectorized representation of the memset value 2999/// operand. 3000static SDValue getMemsetValue(SDValue Value, MVT VT, SelectionDAG &DAG, 3001 DebugLoc dl) { 3002 unsigned NumBits = VT.isVector() ? 3003 VT.getVectorElementType().getSizeInBits() : VT.getSizeInBits(); 3004 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) { 3005 APInt Val = APInt(NumBits, C->getZExtValue() & 255); 3006 unsigned Shift = 8; 3007 for (unsigned i = NumBits; i > 8; i >>= 1) { 3008 Val = (Val << Shift) | Val; 3009 Shift <<= 1; 3010 } 3011 if (VT.isInteger()) 3012 return DAG.getConstant(Val, VT); 3013 return DAG.getConstantFP(APFloat(Val), VT); 3014 } 3015 3016 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 3017 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Value); 3018 unsigned Shift = 8; 3019 for (unsigned i = NumBits; i > 8; i >>= 1) { 3020 Value = DAG.getNode(ISD::OR, dl, VT, 3021 DAG.getNode(ISD::SHL, dl, VT, Value, 3022 DAG.getConstant(Shift, 3023 TLI.getShiftAmountTy())), 3024 Value); 3025 Shift <<= 1; 3026 } 3027 3028 return Value; 3029} 3030 3031/// getMemsetStringVal - Similar to getMemsetValue. Except this is only 3032/// used when a memcpy is turned into a memset when the source is a constant 3033/// string ptr. 3034static SDValue getMemsetStringVal(MVT VT, DebugLoc dl, SelectionDAG &DAG, 3035 const TargetLowering &TLI, 3036 std::string &Str, unsigned Offset) { 3037 // Handle vector with all elements zero. 3038 if (Str.empty()) { 3039 if (VT.isInteger()) 3040 return DAG.getConstant(0, VT); 3041 unsigned NumElts = VT.getVectorNumElements(); 3042 MVT EltVT = (VT.getVectorElementType() == MVT::f32) ? MVT::i32 : MVT::i64; 3043 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 3044 DAG.getConstant(0, MVT::getVectorVT(EltVT, NumElts))); 3045 } 3046 3047 assert(!VT.isVector() && "Can't handle vector type here!"); 3048 unsigned NumBits = VT.getSizeInBits(); 3049 unsigned MSB = NumBits / 8; 3050 uint64_t Val = 0; 3051 if (TLI.isLittleEndian()) 3052 Offset = Offset + MSB - 1; 3053 for (unsigned i = 0; i != MSB; ++i) { 3054 Val = (Val << 8) | (unsigned char)Str[Offset]; 3055 Offset += TLI.isLittleEndian() ? -1 : 1; 3056 } 3057 return DAG.getConstant(Val, VT); 3058} 3059 3060/// getMemBasePlusOffset - Returns base and offset node for the 3061/// 3062static SDValue getMemBasePlusOffset(SDValue Base, unsigned Offset, 3063 SelectionDAG &DAG) { 3064 MVT VT = Base.getValueType(); 3065 return DAG.getNode(ISD::ADD, Base.getDebugLoc(), 3066 VT, Base, DAG.getConstant(Offset, VT)); 3067} 3068 3069/// isMemSrcFromString - Returns true if memcpy source is a string constant. 3070/// 3071static bool isMemSrcFromString(SDValue Src, std::string &Str) { 3072 unsigned SrcDelta = 0; 3073 GlobalAddressSDNode *G = NULL; 3074 if (Src.getOpcode() == ISD::GlobalAddress) 3075 G = cast<GlobalAddressSDNode>(Src); 3076 else if (Src.getOpcode() == ISD::ADD && 3077 Src.getOperand(0).getOpcode() == ISD::GlobalAddress && 3078 Src.getOperand(1).getOpcode() == ISD::Constant) { 3079 G = cast<GlobalAddressSDNode>(Src.getOperand(0)); 3080 SrcDelta = cast<ConstantSDNode>(Src.getOperand(1))->getZExtValue(); 3081 } 3082 if (!G) 3083 return false; 3084 3085 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal()); 3086 if (GV && GetConstantStringInfo(GV, Str, SrcDelta, false)) 3087 return true; 3088 3089 return false; 3090} 3091 3092/// MeetsMaxMemopRequirement - Determines if the number of memory ops required 3093/// to replace the memset / memcpy is below the threshold. It also returns the 3094/// types of the sequence of memory ops to perform memset / memcpy. 3095static 3096bool MeetsMaxMemopRequirement(std::vector<MVT> &MemOps, 3097 SDValue Dst, SDValue Src, 3098 unsigned Limit, uint64_t Size, unsigned &Align, 3099 std::string &Str, bool &isSrcStr, 3100 SelectionDAG &DAG, 3101 const TargetLowering &TLI) { 3102 isSrcStr = isMemSrcFromString(Src, Str); 3103 bool isSrcConst = isa<ConstantSDNode>(Src); 3104 bool AllowUnalign = TLI.allowsUnalignedMemoryAccesses(); 3105 MVT VT = TLI.getOptimalMemOpType(Size, Align, isSrcConst, isSrcStr, DAG); 3106 if (VT != MVT::iAny) { 3107 unsigned NewAlign = (unsigned) 3108 TLI.getTargetData()->getABITypeAlignment(VT.getTypeForMVT()); 3109 // If source is a string constant, this will require an unaligned load. 3110 if (NewAlign > Align && (isSrcConst || AllowUnalign)) { 3111 if (Dst.getOpcode() != ISD::FrameIndex) { 3112 // Can't change destination alignment. It requires a unaligned store. 3113 if (AllowUnalign) 3114 VT = MVT::iAny; 3115 } else { 3116 int FI = cast<FrameIndexSDNode>(Dst)->getIndex(); 3117 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 3118 if (MFI->isFixedObjectIndex(FI)) { 3119 // Can't change destination alignment. It requires a unaligned store. 3120 if (AllowUnalign) 3121 VT = MVT::iAny; 3122 } else { 3123 // Give the stack frame object a larger alignment if needed. 3124 if (MFI->getObjectAlignment(FI) < NewAlign) 3125 MFI->setObjectAlignment(FI, NewAlign); 3126 Align = NewAlign; 3127 } 3128 } 3129 } 3130 } 3131 3132 if (VT == MVT::iAny) { 3133 if (AllowUnalign) { 3134 VT = MVT::i64; 3135 } else { 3136 switch (Align & 7) { 3137 case 0: VT = MVT::i64; break; 3138 case 4: VT = MVT::i32; break; 3139 case 2: VT = MVT::i16; break; 3140 default: VT = MVT::i8; break; 3141 } 3142 } 3143 3144 MVT LVT = MVT::i64; 3145 while (!TLI.isTypeLegal(LVT)) 3146 LVT = (MVT::SimpleValueType)(LVT.getSimpleVT() - 1); 3147 assert(LVT.isInteger()); 3148 3149 if (VT.bitsGT(LVT)) 3150 VT = LVT; 3151 } 3152 3153 unsigned NumMemOps = 0; 3154 while (Size != 0) { 3155 unsigned VTSize = VT.getSizeInBits() / 8; 3156 while (VTSize > Size) { 3157 // For now, only use non-vector load / store's for the left-over pieces. 3158 if (VT.isVector()) { 3159 VT = MVT::i64; 3160 while (!TLI.isTypeLegal(VT)) 3161 VT = (MVT::SimpleValueType)(VT.getSimpleVT() - 1); 3162 VTSize = VT.getSizeInBits() / 8; 3163 } else { 3164 // This can result in a type that is not legal on the target, e.g. 3165 // 1 or 2 bytes on PPC. 3166 VT = (MVT::SimpleValueType)(VT.getSimpleVT() - 1); 3167 VTSize >>= 1; 3168 } 3169 } 3170 3171 if (++NumMemOps > Limit) 3172 return false; 3173 MemOps.push_back(VT); 3174 Size -= VTSize; 3175 } 3176 3177 return true; 3178} 3179 3180static SDValue getMemcpyLoadsAndStores(SelectionDAG &DAG, DebugLoc dl, 3181 SDValue Chain, SDValue Dst, 3182 SDValue Src, uint64_t Size, 3183 unsigned Align, bool AlwaysInline, 3184 const Value *DstSV, uint64_t DstSVOff, 3185 const Value *SrcSV, uint64_t SrcSVOff){ 3186 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 3187 3188 // Expand memcpy to a series of load and store ops if the size operand falls 3189 // below a certain threshold. 3190 std::vector<MVT> MemOps; 3191 uint64_t Limit = -1ULL; 3192 if (!AlwaysInline) 3193 Limit = TLI.getMaxStoresPerMemcpy(); 3194 unsigned DstAlign = Align; // Destination alignment can change. 3195 std::string Str; 3196 bool CopyFromStr; 3197 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, Limit, Size, DstAlign, 3198 Str, CopyFromStr, DAG, TLI)) 3199 return SDValue(); 3200 3201 3202 bool isZeroStr = CopyFromStr && Str.empty(); 3203 SmallVector<SDValue, 8> OutChains; 3204 unsigned NumMemOps = MemOps.size(); 3205 uint64_t SrcOff = 0, DstOff = 0; 3206 for (unsigned i = 0; i < NumMemOps; i++) { 3207 MVT VT = MemOps[i]; 3208 unsigned VTSize = VT.getSizeInBits() / 8; 3209 SDValue Value, Store; 3210 3211 if (CopyFromStr && (isZeroStr || !VT.isVector())) { 3212 // It's unlikely a store of a vector immediate can be done in a single 3213 // instruction. It would require a load from a constantpool first. 3214 // We also handle store a vector with all zero's. 3215 // FIXME: Handle other cases where store of vector immediate is done in 3216 // a single instruction. 3217 Value = getMemsetStringVal(VT, dl, DAG, TLI, Str, SrcOff); 3218 Store = DAG.getStore(Chain, dl, Value, 3219 getMemBasePlusOffset(Dst, DstOff, DAG), 3220 DstSV, DstSVOff + DstOff, false, DstAlign); 3221 } else { 3222 // The type might not be legal for the target. This should only happen 3223 // if the type is smaller than a legal type, as on PPC, so the right 3224 // thing to do is generate a LoadExt/StoreTrunc pair. These simplify 3225 // to Load/Store if NVT==VT. 3226 // FIXME does the case above also need this? 3227 MVT NVT = TLI.getTypeToTransformTo(VT); 3228 assert(NVT.bitsGE(VT)); 3229 Value = DAG.getExtLoad(ISD::EXTLOAD, dl, NVT, Chain, 3230 getMemBasePlusOffset(Src, SrcOff, DAG), 3231 SrcSV, SrcSVOff + SrcOff, VT, false, Align); 3232 Store = DAG.getTruncStore(Chain, dl, Value, 3233 getMemBasePlusOffset(Dst, DstOff, DAG), 3234 DstSV, DstSVOff + DstOff, VT, false, DstAlign); 3235 } 3236 OutChains.push_back(Store); 3237 SrcOff += VTSize; 3238 DstOff += VTSize; 3239 } 3240 3241 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3242 &OutChains[0], OutChains.size()); 3243} 3244 3245static SDValue getMemmoveLoadsAndStores(SelectionDAG &DAG, DebugLoc dl, 3246 SDValue Chain, SDValue Dst, 3247 SDValue Src, uint64_t Size, 3248 unsigned Align, bool AlwaysInline, 3249 const Value *DstSV, uint64_t DstSVOff, 3250 const Value *SrcSV, uint64_t SrcSVOff){ 3251 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 3252 3253 // Expand memmove to a series of load and store ops if the size operand falls 3254 // below a certain threshold. 3255 std::vector<MVT> MemOps; 3256 uint64_t Limit = -1ULL; 3257 if (!AlwaysInline) 3258 Limit = TLI.getMaxStoresPerMemmove(); 3259 unsigned DstAlign = Align; // Destination alignment can change. 3260 std::string Str; 3261 bool CopyFromStr; 3262 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, Limit, Size, DstAlign, 3263 Str, CopyFromStr, DAG, TLI)) 3264 return SDValue(); 3265 3266 uint64_t SrcOff = 0, DstOff = 0; 3267 3268 SmallVector<SDValue, 8> LoadValues; 3269 SmallVector<SDValue, 8> LoadChains; 3270 SmallVector<SDValue, 8> OutChains; 3271 unsigned NumMemOps = MemOps.size(); 3272 for (unsigned i = 0; i < NumMemOps; i++) { 3273 MVT VT = MemOps[i]; 3274 unsigned VTSize = VT.getSizeInBits() / 8; 3275 SDValue Value, Store; 3276 3277 Value = DAG.getLoad(VT, dl, Chain, 3278 getMemBasePlusOffset(Src, SrcOff, DAG), 3279 SrcSV, SrcSVOff + SrcOff, false, Align); 3280 LoadValues.push_back(Value); 3281 LoadChains.push_back(Value.getValue(1)); 3282 SrcOff += VTSize; 3283 } 3284 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3285 &LoadChains[0], LoadChains.size()); 3286 OutChains.clear(); 3287 for (unsigned i = 0; i < NumMemOps; i++) { 3288 MVT VT = MemOps[i]; 3289 unsigned VTSize = VT.getSizeInBits() / 8; 3290 SDValue Value, Store; 3291 3292 Store = DAG.getStore(Chain, dl, LoadValues[i], 3293 getMemBasePlusOffset(Dst, DstOff, DAG), 3294 DstSV, DstSVOff + DstOff, false, DstAlign); 3295 OutChains.push_back(Store); 3296 DstOff += VTSize; 3297 } 3298 3299 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3300 &OutChains[0], OutChains.size()); 3301} 3302 3303static SDValue getMemsetStores(SelectionDAG &DAG, DebugLoc dl, 3304 SDValue Chain, SDValue Dst, 3305 SDValue Src, uint64_t Size, 3306 unsigned Align, 3307 const Value *DstSV, uint64_t DstSVOff) { 3308 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 3309 3310 // Expand memset to a series of load/store ops if the size operand 3311 // falls below a certain threshold. 3312 std::vector<MVT> MemOps; 3313 std::string Str; 3314 bool CopyFromStr; 3315 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, TLI.getMaxStoresPerMemset(), 3316 Size, Align, Str, CopyFromStr, DAG, TLI)) 3317 return SDValue(); 3318 3319 SmallVector<SDValue, 8> OutChains; 3320 uint64_t DstOff = 0; 3321 3322 unsigned NumMemOps = MemOps.size(); 3323 for (unsigned i = 0; i < NumMemOps; i++) { 3324 MVT VT = MemOps[i]; 3325 unsigned VTSize = VT.getSizeInBits() / 8; 3326 SDValue Value = getMemsetValue(Src, VT, DAG, dl); 3327 SDValue Store = DAG.getStore(Chain, dl, Value, 3328 getMemBasePlusOffset(Dst, DstOff, DAG), 3329 DstSV, DstSVOff + DstOff); 3330 OutChains.push_back(Store); 3331 DstOff += VTSize; 3332 } 3333 3334 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3335 &OutChains[0], OutChains.size()); 3336} 3337 3338SDValue SelectionDAG::getMemcpy(SDValue Chain, DebugLoc dl, SDValue Dst, 3339 SDValue Src, SDValue Size, 3340 unsigned Align, bool AlwaysInline, 3341 const Value *DstSV, uint64_t DstSVOff, 3342 const Value *SrcSV, uint64_t SrcSVOff) { 3343 3344 // Check to see if we should lower the memcpy to loads and stores first. 3345 // For cases within the target-specified limits, this is the best choice. 3346 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 3347 if (ConstantSize) { 3348 // Memcpy with size zero? Just return the original chain. 3349 if (ConstantSize->isNullValue()) 3350 return Chain; 3351 3352 SDValue Result = 3353 getMemcpyLoadsAndStores(*this, dl, Chain, Dst, Src, 3354 ConstantSize->getZExtValue(), 3355 Align, false, DstSV, DstSVOff, SrcSV, SrcSVOff); 3356 if (Result.getNode()) 3357 return Result; 3358 } 3359 3360 // Then check to see if we should lower the memcpy with target-specific 3361 // code. If the target chooses to do this, this is the next best. 3362 SDValue Result = 3363 TLI.EmitTargetCodeForMemcpy(*this, dl, Chain, Dst, Src, Size, Align, 3364 AlwaysInline, 3365 DstSV, DstSVOff, SrcSV, SrcSVOff); 3366 if (Result.getNode()) 3367 return Result; 3368 3369 // If we really need inline code and the target declined to provide it, 3370 // use a (potentially long) sequence of loads and stores. 3371 if (AlwaysInline) { 3372 assert(ConstantSize && "AlwaysInline requires a constant size!"); 3373 return getMemcpyLoadsAndStores(*this, dl, Chain, Dst, Src, 3374 ConstantSize->getZExtValue(), Align, true, 3375 DstSV, DstSVOff, SrcSV, SrcSVOff); 3376 } 3377 3378 // Emit a library call. 3379 TargetLowering::ArgListTy Args; 3380 TargetLowering::ArgListEntry Entry; 3381 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 3382 Entry.Node = Dst; Args.push_back(Entry); 3383 Entry.Node = Src; Args.push_back(Entry); 3384 Entry.Node = Size; Args.push_back(Entry); 3385 // FIXME: pass in DebugLoc 3386 std::pair<SDValue,SDValue> CallResult = 3387 TLI.LowerCallTo(Chain, Type::VoidTy, 3388 false, false, false, false, 0, CallingConv::C, false, 3389 getExternalSymbol(TLI.getLibcallName(RTLIB::MEMCPY), 3390 TLI.getPointerTy()), 3391 Args, *this, dl); 3392 return CallResult.second; 3393} 3394 3395SDValue SelectionDAG::getMemmove(SDValue Chain, DebugLoc dl, SDValue Dst, 3396 SDValue Src, SDValue Size, 3397 unsigned Align, 3398 const Value *DstSV, uint64_t DstSVOff, 3399 const Value *SrcSV, uint64_t SrcSVOff) { 3400 3401 // Check to see if we should lower the memmove to loads and stores first. 3402 // For cases within the target-specified limits, this is the best choice. 3403 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 3404 if (ConstantSize) { 3405 // Memmove with size zero? Just return the original chain. 3406 if (ConstantSize->isNullValue()) 3407 return Chain; 3408 3409 SDValue Result = 3410 getMemmoveLoadsAndStores(*this, dl, Chain, Dst, Src, 3411 ConstantSize->getZExtValue(), 3412 Align, false, DstSV, DstSVOff, SrcSV, SrcSVOff); 3413 if (Result.getNode()) 3414 return Result; 3415 } 3416 3417 // Then check to see if we should lower the memmove with target-specific 3418 // code. If the target chooses to do this, this is the next best. 3419 SDValue Result = 3420 TLI.EmitTargetCodeForMemmove(*this, dl, Chain, Dst, Src, Size, Align, 3421 DstSV, DstSVOff, SrcSV, SrcSVOff); 3422 if (Result.getNode()) 3423 return Result; 3424 3425 // Emit a library call. 3426 TargetLowering::ArgListTy Args; 3427 TargetLowering::ArgListEntry Entry; 3428 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 3429 Entry.Node = Dst; Args.push_back(Entry); 3430 Entry.Node = Src; Args.push_back(Entry); 3431 Entry.Node = Size; Args.push_back(Entry); 3432 // FIXME: pass in DebugLoc 3433 std::pair<SDValue,SDValue> CallResult = 3434 TLI.LowerCallTo(Chain, Type::VoidTy, 3435 false, false, false, false, 0, CallingConv::C, false, 3436 getExternalSymbol(TLI.getLibcallName(RTLIB::MEMMOVE), 3437 TLI.getPointerTy()), 3438 Args, *this, dl); 3439 return CallResult.second; 3440} 3441 3442SDValue SelectionDAG::getMemset(SDValue Chain, DebugLoc dl, SDValue Dst, 3443 SDValue Src, SDValue Size, 3444 unsigned Align, 3445 const Value *DstSV, uint64_t DstSVOff) { 3446 3447 // Check to see if we should lower the memset to stores first. 3448 // For cases within the target-specified limits, this is the best choice. 3449 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 3450 if (ConstantSize) { 3451 // Memset with size zero? Just return the original chain. 3452 if (ConstantSize->isNullValue()) 3453 return Chain; 3454 3455 SDValue Result = 3456 getMemsetStores(*this, dl, Chain, Dst, Src, ConstantSize->getZExtValue(), 3457 Align, DstSV, DstSVOff); 3458 if (Result.getNode()) 3459 return Result; 3460 } 3461 3462 // Then check to see if we should lower the memset with target-specific 3463 // code. If the target chooses to do this, this is the next best. 3464 SDValue Result = 3465 TLI.EmitTargetCodeForMemset(*this, dl, Chain, Dst, Src, Size, Align, 3466 DstSV, DstSVOff); 3467 if (Result.getNode()) 3468 return Result; 3469 3470 // Emit a library call. 3471 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType(); 3472 TargetLowering::ArgListTy Args; 3473 TargetLowering::ArgListEntry Entry; 3474 Entry.Node = Dst; Entry.Ty = IntPtrTy; 3475 Args.push_back(Entry); 3476 // Extend or truncate the argument to be an i32 value for the call. 3477 if (Src.getValueType().bitsGT(MVT::i32)) 3478 Src = getNode(ISD::TRUNCATE, dl, MVT::i32, Src); 3479 else 3480 Src = getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Src); 3481 Entry.Node = Src; Entry.Ty = Type::Int32Ty; Entry.isSExt = true; 3482 Args.push_back(Entry); 3483 Entry.Node = Size; Entry.Ty = IntPtrTy; Entry.isSExt = false; 3484 Args.push_back(Entry); 3485 // FIXME: pass in DebugLoc 3486 std::pair<SDValue,SDValue> CallResult = 3487 TLI.LowerCallTo(Chain, Type::VoidTy, 3488 false, false, false, false, 0, CallingConv::C, false, 3489 getExternalSymbol(TLI.getLibcallName(RTLIB::MEMSET), 3490 TLI.getPointerTy()), 3491 Args, *this, dl); 3492 return CallResult.second; 3493} 3494 3495SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, MVT MemVT, 3496 SDValue Chain, 3497 SDValue Ptr, SDValue Cmp, 3498 SDValue Swp, const Value* PtrVal, 3499 unsigned Alignment) { 3500 assert(Opcode == ISD::ATOMIC_CMP_SWAP && "Invalid Atomic Op"); 3501 assert(Cmp.getValueType() == Swp.getValueType() && "Invalid Atomic Op Types"); 3502 3503 MVT VT = Cmp.getValueType(); 3504 3505 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3506 Alignment = getMVTAlignment(MemVT); 3507 3508 SDVTList VTs = getVTList(VT, MVT::Other); 3509 FoldingSetNodeID ID; 3510 ID.AddInteger(MemVT.getRawBits()); 3511 SDValue Ops[] = {Chain, Ptr, Cmp, Swp}; 3512 AddNodeIDNode(ID, Opcode, VTs, Ops, 4); 3513 void* IP = 0; 3514 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3515 return SDValue(E, 0); 3516 SDNode* N = NodeAllocator.Allocate<AtomicSDNode>(); 3517 new (N) AtomicSDNode(Opcode, dl, VTs, MemVT, 3518 Chain, Ptr, Cmp, Swp, PtrVal, Alignment); 3519 CSEMap.InsertNode(N, IP); 3520 AllNodes.push_back(N); 3521 return SDValue(N, 0); 3522} 3523 3524SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, MVT MemVT, 3525 SDValue Chain, 3526 SDValue Ptr, SDValue Val, 3527 const Value* PtrVal, 3528 unsigned Alignment) { 3529 assert((Opcode == ISD::ATOMIC_LOAD_ADD || 3530 Opcode == ISD::ATOMIC_LOAD_SUB || 3531 Opcode == ISD::ATOMIC_LOAD_AND || 3532 Opcode == ISD::ATOMIC_LOAD_OR || 3533 Opcode == ISD::ATOMIC_LOAD_XOR || 3534 Opcode == ISD::ATOMIC_LOAD_NAND || 3535 Opcode == ISD::ATOMIC_LOAD_MIN || 3536 Opcode == ISD::ATOMIC_LOAD_MAX || 3537 Opcode == ISD::ATOMIC_LOAD_UMIN || 3538 Opcode == ISD::ATOMIC_LOAD_UMAX || 3539 Opcode == ISD::ATOMIC_SWAP) && 3540 "Invalid Atomic Op"); 3541 3542 MVT VT = Val.getValueType(); 3543 3544 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3545 Alignment = getMVTAlignment(MemVT); 3546 3547 SDVTList VTs = getVTList(VT, MVT::Other); 3548 FoldingSetNodeID ID; 3549 ID.AddInteger(MemVT.getRawBits()); 3550 SDValue Ops[] = {Chain, Ptr, Val}; 3551 AddNodeIDNode(ID, Opcode, VTs, Ops, 3); 3552 void* IP = 0; 3553 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3554 return SDValue(E, 0); 3555 SDNode* N = NodeAllocator.Allocate<AtomicSDNode>(); 3556 new (N) AtomicSDNode(Opcode, dl, VTs, MemVT, 3557 Chain, Ptr, Val, PtrVal, Alignment); 3558 CSEMap.InsertNode(N, IP); 3559 AllNodes.push_back(N); 3560 return SDValue(N, 0); 3561} 3562 3563/// getMergeValues - Create a MERGE_VALUES node from the given operands. 3564/// Allowed to return something different (and simpler) if Simplify is true. 3565SDValue SelectionDAG::getMergeValues(const SDValue *Ops, unsigned NumOps, 3566 DebugLoc dl) { 3567 if (NumOps == 1) 3568 return Ops[0]; 3569 3570 SmallVector<MVT, 4> VTs; 3571 VTs.reserve(NumOps); 3572 for (unsigned i = 0; i < NumOps; ++i) 3573 VTs.push_back(Ops[i].getValueType()); 3574 return getNode(ISD::MERGE_VALUES, dl, getVTList(&VTs[0], NumOps), 3575 Ops, NumOps); 3576} 3577 3578SDValue 3579SelectionDAG::getMemIntrinsicNode(unsigned Opcode, DebugLoc dl, 3580 const MVT *VTs, unsigned NumVTs, 3581 const SDValue *Ops, unsigned NumOps, 3582 MVT MemVT, const Value *srcValue, int SVOff, 3583 unsigned Align, bool Vol, 3584 bool ReadMem, bool WriteMem) { 3585 return getMemIntrinsicNode(Opcode, dl, makeVTList(VTs, NumVTs), Ops, NumOps, 3586 MemVT, srcValue, SVOff, Align, Vol, 3587 ReadMem, WriteMem); 3588} 3589 3590SDValue 3591SelectionDAG::getMemIntrinsicNode(unsigned Opcode, DebugLoc dl, SDVTList VTList, 3592 const SDValue *Ops, unsigned NumOps, 3593 MVT MemVT, const Value *srcValue, int SVOff, 3594 unsigned Align, bool Vol, 3595 bool ReadMem, bool WriteMem) { 3596 // Memoize the node unless it returns a flag. 3597 MemIntrinsicSDNode *N; 3598 if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) { 3599 FoldingSetNodeID ID; 3600 AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps); 3601 void *IP = 0; 3602 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3603 return SDValue(E, 0); 3604 3605 N = NodeAllocator.Allocate<MemIntrinsicSDNode>(); 3606 new (N) MemIntrinsicSDNode(Opcode, dl, VTList, Ops, NumOps, MemVT, 3607 srcValue, SVOff, Align, Vol, ReadMem, WriteMem); 3608 CSEMap.InsertNode(N, IP); 3609 } else { 3610 N = NodeAllocator.Allocate<MemIntrinsicSDNode>(); 3611 new (N) MemIntrinsicSDNode(Opcode, dl, VTList, Ops, NumOps, MemVT, 3612 srcValue, SVOff, Align, Vol, ReadMem, WriteMem); 3613 } 3614 AllNodes.push_back(N); 3615 return SDValue(N, 0); 3616} 3617 3618SDValue 3619SelectionDAG::getCall(unsigned CallingConv, DebugLoc dl, bool IsVarArgs, 3620 bool IsTailCall, bool IsInreg, SDVTList VTs, 3621 const SDValue *Operands, unsigned NumOperands, 3622 unsigned NumFixedArgs) { 3623 // Do not include isTailCall in the folding set profile. 3624 FoldingSetNodeID ID; 3625 AddNodeIDNode(ID, ISD::CALL, VTs, Operands, NumOperands); 3626 ID.AddInteger(CallingConv); 3627 ID.AddInteger(IsVarArgs); 3628 void *IP = 0; 3629 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) { 3630 // Instead of including isTailCall in the folding set, we just 3631 // set the flag of the existing node. 3632 if (!IsTailCall) 3633 cast<CallSDNode>(E)->setNotTailCall(); 3634 return SDValue(E, 0); 3635 } 3636 SDNode *N = NodeAllocator.Allocate<CallSDNode>(); 3637 new (N) CallSDNode(CallingConv, dl, IsVarArgs, IsTailCall, IsInreg, 3638 VTs, Operands, NumOperands, NumFixedArgs); 3639 CSEMap.InsertNode(N, IP); 3640 AllNodes.push_back(N); 3641 return SDValue(N, 0); 3642} 3643 3644SDValue 3645SelectionDAG::getLoad(ISD::MemIndexedMode AM, DebugLoc dl, 3646 ISD::LoadExtType ExtType, MVT VT, SDValue Chain, 3647 SDValue Ptr, SDValue Offset, 3648 const Value *SV, int SVOffset, MVT EVT, 3649 bool isVolatile, unsigned Alignment) { 3650 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3651 Alignment = getMVTAlignment(VT); 3652 3653 if (VT == EVT) { 3654 ExtType = ISD::NON_EXTLOAD; 3655 } else if (ExtType == ISD::NON_EXTLOAD) { 3656 assert(VT == EVT && "Non-extending load from different memory type!"); 3657 } else { 3658 // Extending load. 3659 if (VT.isVector()) 3660 assert(EVT.getVectorNumElements() == VT.getVectorNumElements() && 3661 "Invalid vector extload!"); 3662 else 3663 assert(EVT.bitsLT(VT) && 3664 "Should only be an extending load, not truncating!"); 3665 assert((ExtType == ISD::EXTLOAD || VT.isInteger()) && 3666 "Cannot sign/zero extend a FP/Vector load!"); 3667 assert(VT.isInteger() == EVT.isInteger() && 3668 "Cannot convert from FP to Int or Int -> FP!"); 3669 } 3670 3671 bool Indexed = AM != ISD::UNINDEXED; 3672 assert((Indexed || Offset.getOpcode() == ISD::UNDEF) && 3673 "Unindexed load with an offset!"); 3674 3675 SDVTList VTs = Indexed ? 3676 getVTList(VT, Ptr.getValueType(), MVT::Other) : getVTList(VT, MVT::Other); 3677 SDValue Ops[] = { Chain, Ptr, Offset }; 3678 FoldingSetNodeID ID; 3679 AddNodeIDNode(ID, ISD::LOAD, VTs, Ops, 3); 3680 ID.AddInteger(EVT.getRawBits()); 3681 ID.AddInteger(encodeMemSDNodeFlags(ExtType, AM, isVolatile, Alignment)); 3682 void *IP = 0; 3683 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3684 return SDValue(E, 0); 3685 SDNode *N = NodeAllocator.Allocate<LoadSDNode>(); 3686 new (N) LoadSDNode(Ops, dl, VTs, AM, ExtType, EVT, SV, SVOffset, 3687 Alignment, isVolatile); 3688 CSEMap.InsertNode(N, IP); 3689 AllNodes.push_back(N); 3690 return SDValue(N, 0); 3691} 3692 3693SDValue SelectionDAG::getLoad(MVT VT, DebugLoc dl, 3694 SDValue Chain, SDValue Ptr, 3695 const Value *SV, int SVOffset, 3696 bool isVolatile, unsigned Alignment) { 3697 SDValue Undef = getUNDEF(Ptr.getValueType()); 3698 return getLoad(ISD::UNINDEXED, dl, ISD::NON_EXTLOAD, VT, Chain, Ptr, Undef, 3699 SV, SVOffset, VT, isVolatile, Alignment); 3700} 3701 3702SDValue SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, DebugLoc dl, MVT VT, 3703 SDValue Chain, SDValue Ptr, 3704 const Value *SV, 3705 int SVOffset, MVT EVT, 3706 bool isVolatile, unsigned Alignment) { 3707 SDValue Undef = getUNDEF(Ptr.getValueType()); 3708 return getLoad(ISD::UNINDEXED, dl, ExtType, VT, Chain, Ptr, Undef, 3709 SV, SVOffset, EVT, isVolatile, Alignment); 3710} 3711 3712SDValue 3713SelectionDAG::getIndexedLoad(SDValue OrigLoad, DebugLoc dl, SDValue Base, 3714 SDValue Offset, ISD::MemIndexedMode AM) { 3715 LoadSDNode *LD = cast<LoadSDNode>(OrigLoad); 3716 assert(LD->getOffset().getOpcode() == ISD::UNDEF && 3717 "Load is already a indexed load!"); 3718 return getLoad(AM, dl, LD->getExtensionType(), OrigLoad.getValueType(), 3719 LD->getChain(), Base, Offset, LD->getSrcValue(), 3720 LD->getSrcValueOffset(), LD->getMemoryVT(), 3721 LD->isVolatile(), LD->getAlignment()); 3722} 3723 3724SDValue SelectionDAG::getStore(SDValue Chain, DebugLoc dl, SDValue Val, 3725 SDValue Ptr, const Value *SV, int SVOffset, 3726 bool isVolatile, unsigned Alignment) { 3727 MVT VT = Val.getValueType(); 3728 3729 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3730 Alignment = getMVTAlignment(VT); 3731 3732 SDVTList VTs = getVTList(MVT::Other); 3733 SDValue Undef = getUNDEF(Ptr.getValueType()); 3734 SDValue Ops[] = { Chain, Val, Ptr, Undef }; 3735 FoldingSetNodeID ID; 3736 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); 3737 ID.AddInteger(VT.getRawBits()); 3738 ID.AddInteger(encodeMemSDNodeFlags(false, ISD::UNINDEXED, 3739 isVolatile, Alignment)); 3740 void *IP = 0; 3741 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3742 return SDValue(E, 0); 3743 SDNode *N = NodeAllocator.Allocate<StoreSDNode>(); 3744 new (N) StoreSDNode(Ops, dl, VTs, ISD::UNINDEXED, false, 3745 VT, SV, SVOffset, Alignment, isVolatile); 3746 CSEMap.InsertNode(N, IP); 3747 AllNodes.push_back(N); 3748 return SDValue(N, 0); 3749} 3750 3751SDValue SelectionDAG::getTruncStore(SDValue Chain, DebugLoc dl, SDValue Val, 3752 SDValue Ptr, const Value *SV, 3753 int SVOffset, MVT SVT, 3754 bool isVolatile, unsigned Alignment) { 3755 MVT VT = Val.getValueType(); 3756 3757 if (VT == SVT) 3758 return getStore(Chain, dl, Val, Ptr, SV, SVOffset, isVolatile, Alignment); 3759 3760 assert(VT.bitsGT(SVT) && "Not a truncation?"); 3761 assert(VT.isInteger() == SVT.isInteger() && 3762 "Can't do FP-INT conversion!"); 3763 3764 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3765 Alignment = getMVTAlignment(VT); 3766 3767 SDVTList VTs = getVTList(MVT::Other); 3768 SDValue Undef = getUNDEF(Ptr.getValueType()); 3769 SDValue Ops[] = { Chain, Val, Ptr, Undef }; 3770 FoldingSetNodeID ID; 3771 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); 3772 ID.AddInteger(SVT.getRawBits()); 3773 ID.AddInteger(encodeMemSDNodeFlags(true, ISD::UNINDEXED, 3774 isVolatile, Alignment)); 3775 void *IP = 0; 3776 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3777 return SDValue(E, 0); 3778 SDNode *N = NodeAllocator.Allocate<StoreSDNode>(); 3779 new (N) StoreSDNode(Ops, dl, VTs, ISD::UNINDEXED, true, 3780 SVT, SV, SVOffset, Alignment, isVolatile); 3781 CSEMap.InsertNode(N, IP); 3782 AllNodes.push_back(N); 3783 return SDValue(N, 0); 3784} 3785 3786SDValue 3787SelectionDAG::getIndexedStore(SDValue OrigStore, DebugLoc dl, SDValue Base, 3788 SDValue Offset, ISD::MemIndexedMode AM) { 3789 StoreSDNode *ST = cast<StoreSDNode>(OrigStore); 3790 assert(ST->getOffset().getOpcode() == ISD::UNDEF && 3791 "Store is already a indexed store!"); 3792 SDVTList VTs = getVTList(Base.getValueType(), MVT::Other); 3793 SDValue Ops[] = { ST->getChain(), ST->getValue(), Base, Offset }; 3794 FoldingSetNodeID ID; 3795 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); 3796 ID.AddInteger(ST->getMemoryVT().getRawBits()); 3797 ID.AddInteger(ST->getRawSubclassData()); 3798 void *IP = 0; 3799 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3800 return SDValue(E, 0); 3801 SDNode *N = NodeAllocator.Allocate<StoreSDNode>(); 3802 new (N) StoreSDNode(Ops, dl, VTs, AM, 3803 ST->isTruncatingStore(), ST->getMemoryVT(), 3804 ST->getSrcValue(), ST->getSrcValueOffset(), 3805 ST->getAlignment(), ST->isVolatile()); 3806 CSEMap.InsertNode(N, IP); 3807 AllNodes.push_back(N); 3808 return SDValue(N, 0); 3809} 3810 3811SDValue SelectionDAG::getVAArg(MVT VT, DebugLoc dl, 3812 SDValue Chain, SDValue Ptr, 3813 SDValue SV) { 3814 SDValue Ops[] = { Chain, Ptr, SV }; 3815 return getNode(ISD::VAARG, dl, getVTList(VT, MVT::Other), Ops, 3); 3816} 3817 3818SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, 3819 const SDUse *Ops, unsigned NumOps) { 3820 switch (NumOps) { 3821 case 0: return getNode(Opcode, DL, VT); 3822 case 1: return getNode(Opcode, DL, VT, Ops[0]); 3823 case 2: return getNode(Opcode, DL, VT, Ops[0], Ops[1]); 3824 case 3: return getNode(Opcode, DL, VT, Ops[0], Ops[1], Ops[2]); 3825 default: break; 3826 } 3827 3828 // Copy from an SDUse array into an SDValue array for use with 3829 // the regular getNode logic. 3830 SmallVector<SDValue, 8> NewOps(Ops, Ops + NumOps); 3831 return getNode(Opcode, DL, VT, &NewOps[0], NumOps); 3832} 3833 3834SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, 3835 const SDValue *Ops, unsigned NumOps) { 3836 switch (NumOps) { 3837 case 0: return getNode(Opcode, DL, VT); 3838 case 1: return getNode(Opcode, DL, VT, Ops[0]); 3839 case 2: return getNode(Opcode, DL, VT, Ops[0], Ops[1]); 3840 case 3: return getNode(Opcode, DL, VT, Ops[0], Ops[1], Ops[2]); 3841 default: break; 3842 } 3843 3844 switch (Opcode) { 3845 default: break; 3846 case ISD::SELECT_CC: { 3847 assert(NumOps == 5 && "SELECT_CC takes 5 operands!"); 3848 assert(Ops[0].getValueType() == Ops[1].getValueType() && 3849 "LHS and RHS of condition must have same type!"); 3850 assert(Ops[2].getValueType() == Ops[3].getValueType() && 3851 "True and False arms of SelectCC must have same type!"); 3852 assert(Ops[2].getValueType() == VT && 3853 "select_cc node must be of same type as true and false value!"); 3854 break; 3855 } 3856 case ISD::BR_CC: { 3857 assert(NumOps == 5 && "BR_CC takes 5 operands!"); 3858 assert(Ops[2].getValueType() == Ops[3].getValueType() && 3859 "LHS/RHS of comparison should match types!"); 3860 break; 3861 } 3862 } 3863 3864 // Memoize nodes. 3865 SDNode *N; 3866 SDVTList VTs = getVTList(VT); 3867 3868 if (VT != MVT::Flag) { 3869 FoldingSetNodeID ID; 3870 AddNodeIDNode(ID, Opcode, VTs, Ops, NumOps); 3871 void *IP = 0; 3872 3873 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3874 return SDValue(E, 0); 3875 3876 N = NodeAllocator.Allocate<SDNode>(); 3877 new (N) SDNode(Opcode, DL, VTs, Ops, NumOps); 3878 CSEMap.InsertNode(N, IP); 3879 } else { 3880 N = NodeAllocator.Allocate<SDNode>(); 3881 new (N) SDNode(Opcode, DL, VTs, Ops, NumOps); 3882 } 3883 3884 AllNodes.push_back(N); 3885#ifndef NDEBUG 3886 VerifyNode(N); 3887#endif 3888 return SDValue(N, 0); 3889} 3890 3891SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, 3892 const std::vector<MVT> &ResultTys, 3893 const SDValue *Ops, unsigned NumOps) { 3894 return getNode(Opcode, DL, getVTList(&ResultTys[0], ResultTys.size()), 3895 Ops, NumOps); 3896} 3897 3898SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, 3899 const MVT *VTs, unsigned NumVTs, 3900 const SDValue *Ops, unsigned NumOps) { 3901 if (NumVTs == 1) 3902 return getNode(Opcode, DL, VTs[0], Ops, NumOps); 3903 return getNode(Opcode, DL, makeVTList(VTs, NumVTs), Ops, NumOps); 3904} 3905 3906SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, 3907 const SDValue *Ops, unsigned NumOps) { 3908 if (VTList.NumVTs == 1) 3909 return getNode(Opcode, DL, VTList.VTs[0], Ops, NumOps); 3910 3911#if 0 3912 switch (Opcode) { 3913 // FIXME: figure out how to safely handle things like 3914 // int foo(int x) { return 1 << (x & 255); } 3915 // int bar() { return foo(256); } 3916 case ISD::SRA_PARTS: 3917 case ISD::SRL_PARTS: 3918 case ISD::SHL_PARTS: 3919 if (N3.getOpcode() == ISD::SIGN_EXTEND_INREG && 3920 cast<VTSDNode>(N3.getOperand(1))->getVT() != MVT::i1) 3921 return getNode(Opcode, DL, VT, N1, N2, N3.getOperand(0)); 3922 else if (N3.getOpcode() == ISD::AND) 3923 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(N3.getOperand(1))) { 3924 // If the and is only masking out bits that cannot effect the shift, 3925 // eliminate the and. 3926 unsigned NumBits = VT.getSizeInBits()*2; 3927 if ((AndRHS->getValue() & (NumBits-1)) == NumBits-1) 3928 return getNode(Opcode, DL, VT, N1, N2, N3.getOperand(0)); 3929 } 3930 break; 3931 } 3932#endif 3933 3934 // Memoize the node unless it returns a flag. 3935 SDNode *N; 3936 if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) { 3937 FoldingSetNodeID ID; 3938 AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps); 3939 void *IP = 0; 3940 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3941 return SDValue(E, 0); 3942 if (NumOps == 1) { 3943 N = NodeAllocator.Allocate<UnarySDNode>(); 3944 new (N) UnarySDNode(Opcode, DL, VTList, Ops[0]); 3945 } else if (NumOps == 2) { 3946 N = NodeAllocator.Allocate<BinarySDNode>(); 3947 new (N) BinarySDNode(Opcode, DL, VTList, Ops[0], Ops[1]); 3948 } else if (NumOps == 3) { 3949 N = NodeAllocator.Allocate<TernarySDNode>(); 3950 new (N) TernarySDNode(Opcode, DL, VTList, Ops[0], Ops[1], Ops[2]); 3951 } else { 3952 N = NodeAllocator.Allocate<SDNode>(); 3953 new (N) SDNode(Opcode, DL, VTList, Ops, NumOps); 3954 } 3955 CSEMap.InsertNode(N, IP); 3956 } else { 3957 if (NumOps == 1) { 3958 N = NodeAllocator.Allocate<UnarySDNode>(); 3959 new (N) UnarySDNode(Opcode, DL, VTList, Ops[0]); 3960 } else if (NumOps == 2) { 3961 N = NodeAllocator.Allocate<BinarySDNode>(); 3962 new (N) BinarySDNode(Opcode, DL, VTList, Ops[0], Ops[1]); 3963 } else if (NumOps == 3) { 3964 N = NodeAllocator.Allocate<TernarySDNode>(); 3965 new (N) TernarySDNode(Opcode, DL, VTList, Ops[0], Ops[1], Ops[2]); 3966 } else { 3967 N = NodeAllocator.Allocate<SDNode>(); 3968 new (N) SDNode(Opcode, DL, VTList, Ops, NumOps); 3969 } 3970 } 3971 AllNodes.push_back(N); 3972#ifndef NDEBUG 3973 VerifyNode(N); 3974#endif 3975 return SDValue(N, 0); 3976} 3977 3978SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList) { 3979 return getNode(Opcode, DL, VTList, 0, 0); 3980} 3981 3982SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, 3983 SDValue N1) { 3984 SDValue Ops[] = { N1 }; 3985 return getNode(Opcode, DL, VTList, Ops, 1); 3986} 3987 3988SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, 3989 SDValue N1, SDValue N2) { 3990 SDValue Ops[] = { N1, N2 }; 3991 return getNode(Opcode, DL, VTList, Ops, 2); 3992} 3993 3994SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, 3995 SDValue N1, SDValue N2, SDValue N3) { 3996 SDValue Ops[] = { N1, N2, N3 }; 3997 return getNode(Opcode, DL, VTList, Ops, 3); 3998} 3999 4000SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, 4001 SDValue N1, SDValue N2, SDValue N3, 4002 SDValue N4) { 4003 SDValue Ops[] = { N1, N2, N3, N4 }; 4004 return getNode(Opcode, DL, VTList, Ops, 4); 4005} 4006 4007SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, 4008 SDValue N1, SDValue N2, SDValue N3, 4009 SDValue N4, SDValue N5) { 4010 SDValue Ops[] = { N1, N2, N3, N4, N5 }; 4011 return getNode(Opcode, DL, VTList, Ops, 5); 4012} 4013 4014SDVTList SelectionDAG::getVTList(MVT VT) { 4015 return makeVTList(SDNode::getValueTypeList(VT), 1); 4016} 4017 4018SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2) { 4019 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 4020 E = VTList.rend(); I != E; ++I) 4021 if (I->NumVTs == 2 && I->VTs[0] == VT1 && I->VTs[1] == VT2) 4022 return *I; 4023 4024 MVT *Array = Allocator.Allocate<MVT>(2); 4025 Array[0] = VT1; 4026 Array[1] = VT2; 4027 SDVTList Result = makeVTList(Array, 2); 4028 VTList.push_back(Result); 4029 return Result; 4030} 4031 4032SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2, MVT VT3) { 4033 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 4034 E = VTList.rend(); I != E; ++I) 4035 if (I->NumVTs == 3 && I->VTs[0] == VT1 && I->VTs[1] == VT2 && 4036 I->VTs[2] == VT3) 4037 return *I; 4038 4039 MVT *Array = Allocator.Allocate<MVT>(3); 4040 Array[0] = VT1; 4041 Array[1] = VT2; 4042 Array[2] = VT3; 4043 SDVTList Result = makeVTList(Array, 3); 4044 VTList.push_back(Result); 4045 return Result; 4046} 4047 4048SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2, MVT VT3, MVT VT4) { 4049 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 4050 E = VTList.rend(); I != E; ++I) 4051 if (I->NumVTs == 4 && I->VTs[0] == VT1 && I->VTs[1] == VT2 && 4052 I->VTs[2] == VT3 && I->VTs[3] == VT4) 4053 return *I; 4054 4055 MVT *Array = Allocator.Allocate<MVT>(3); 4056 Array[0] = VT1; 4057 Array[1] = VT2; 4058 Array[2] = VT3; 4059 Array[3] = VT4; 4060 SDVTList Result = makeVTList(Array, 4); 4061 VTList.push_back(Result); 4062 return Result; 4063} 4064 4065SDVTList SelectionDAG::getVTList(const MVT *VTs, unsigned NumVTs) { 4066 switch (NumVTs) { 4067 case 0: llvm_unreachable("Cannot have nodes without results!"); 4068 case 1: return getVTList(VTs[0]); 4069 case 2: return getVTList(VTs[0], VTs[1]); 4070 case 3: return getVTList(VTs[0], VTs[1], VTs[2]); 4071 default: break; 4072 } 4073 4074 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 4075 E = VTList.rend(); I != E; ++I) { 4076 if (I->NumVTs != NumVTs || VTs[0] != I->VTs[0] || VTs[1] != I->VTs[1]) 4077 continue; 4078 4079 bool NoMatch = false; 4080 for (unsigned i = 2; i != NumVTs; ++i) 4081 if (VTs[i] != I->VTs[i]) { 4082 NoMatch = true; 4083 break; 4084 } 4085 if (!NoMatch) 4086 return *I; 4087 } 4088 4089 MVT *Array = Allocator.Allocate<MVT>(NumVTs); 4090 std::copy(VTs, VTs+NumVTs, Array); 4091 SDVTList Result = makeVTList(Array, NumVTs); 4092 VTList.push_back(Result); 4093 return Result; 4094} 4095 4096 4097/// UpdateNodeOperands - *Mutate* the specified node in-place to have the 4098/// specified operands. If the resultant node already exists in the DAG, 4099/// this does not modify the specified node, instead it returns the node that 4100/// already exists. If the resultant node does not exist in the DAG, the 4101/// input node is returned. As a degenerate case, if you specify the same 4102/// input operands as the node already has, the input node is returned. 4103SDValue SelectionDAG::UpdateNodeOperands(SDValue InN, SDValue Op) { 4104 SDNode *N = InN.getNode(); 4105 assert(N->getNumOperands() == 1 && "Update with wrong number of operands"); 4106 4107 // Check to see if there is no change. 4108 if (Op == N->getOperand(0)) return InN; 4109 4110 // See if the modified node already exists. 4111 void *InsertPos = 0; 4112 if (SDNode *Existing = FindModifiedNodeSlot(N, Op, InsertPos)) 4113 return SDValue(Existing, InN.getResNo()); 4114 4115 // Nope it doesn't. Remove the node from its current place in the maps. 4116 if (InsertPos) 4117 if (!RemoveNodeFromCSEMaps(N)) 4118 InsertPos = 0; 4119 4120 // Now we update the operands. 4121 N->OperandList[0].set(Op); 4122 4123 // If this gets put into a CSE map, add it. 4124 if (InsertPos) CSEMap.InsertNode(N, InsertPos); 4125 return InN; 4126} 4127 4128SDValue SelectionDAG:: 4129UpdateNodeOperands(SDValue InN, SDValue Op1, SDValue Op2) { 4130 SDNode *N = InN.getNode(); 4131 assert(N->getNumOperands() == 2 && "Update with wrong number of operands"); 4132 4133 // Check to see if there is no change. 4134 if (Op1 == N->getOperand(0) && Op2 == N->getOperand(1)) 4135 return InN; // No operands changed, just return the input node. 4136 4137 // See if the modified node already exists. 4138 void *InsertPos = 0; 4139 if (SDNode *Existing = FindModifiedNodeSlot(N, Op1, Op2, InsertPos)) 4140 return SDValue(Existing, InN.getResNo()); 4141 4142 // Nope it doesn't. Remove the node from its current place in the maps. 4143 if (InsertPos) 4144 if (!RemoveNodeFromCSEMaps(N)) 4145 InsertPos = 0; 4146 4147 // Now we update the operands. 4148 if (N->OperandList[0] != Op1) 4149 N->OperandList[0].set(Op1); 4150 if (N->OperandList[1] != Op2) 4151 N->OperandList[1].set(Op2); 4152 4153 // If this gets put into a CSE map, add it. 4154 if (InsertPos) CSEMap.InsertNode(N, InsertPos); 4155 return InN; 4156} 4157 4158SDValue SelectionDAG:: 4159UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, SDValue Op3) { 4160 SDValue Ops[] = { Op1, Op2, Op3 }; 4161 return UpdateNodeOperands(N, Ops, 3); 4162} 4163 4164SDValue SelectionDAG:: 4165UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, 4166 SDValue Op3, SDValue Op4) { 4167 SDValue Ops[] = { Op1, Op2, Op3, Op4 }; 4168 return UpdateNodeOperands(N, Ops, 4); 4169} 4170 4171SDValue SelectionDAG:: 4172UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, 4173 SDValue Op3, SDValue Op4, SDValue Op5) { 4174 SDValue Ops[] = { Op1, Op2, Op3, Op4, Op5 }; 4175 return UpdateNodeOperands(N, Ops, 5); 4176} 4177 4178SDValue SelectionDAG:: 4179UpdateNodeOperands(SDValue InN, const SDValue *Ops, unsigned NumOps) { 4180 SDNode *N = InN.getNode(); 4181 assert(N->getNumOperands() == NumOps && 4182 "Update with wrong number of operands"); 4183 4184 // Check to see if there is no change. 4185 bool AnyChange = false; 4186 for (unsigned i = 0; i != NumOps; ++i) { 4187 if (Ops[i] != N->getOperand(i)) { 4188 AnyChange = true; 4189 break; 4190 } 4191 } 4192 4193 // No operands changed, just return the input node. 4194 if (!AnyChange) return InN; 4195 4196 // See if the modified node already exists. 4197 void *InsertPos = 0; 4198 if (SDNode *Existing = FindModifiedNodeSlot(N, Ops, NumOps, InsertPos)) 4199 return SDValue(Existing, InN.getResNo()); 4200 4201 // Nope it doesn't. Remove the node from its current place in the maps. 4202 if (InsertPos) 4203 if (!RemoveNodeFromCSEMaps(N)) 4204 InsertPos = 0; 4205 4206 // Now we update the operands. 4207 for (unsigned i = 0; i != NumOps; ++i) 4208 if (N->OperandList[i] != Ops[i]) 4209 N->OperandList[i].set(Ops[i]); 4210 4211 // If this gets put into a CSE map, add it. 4212 if (InsertPos) CSEMap.InsertNode(N, InsertPos); 4213 return InN; 4214} 4215 4216/// DropOperands - Release the operands and set this node to have 4217/// zero operands. 4218void SDNode::DropOperands() { 4219 // Unlike the code in MorphNodeTo that does this, we don't need to 4220 // watch for dead nodes here. 4221 for (op_iterator I = op_begin(), E = op_end(); I != E; ) { 4222 SDUse &Use = *I++; 4223 Use.set(SDValue()); 4224 } 4225} 4226 4227/// SelectNodeTo - These are wrappers around MorphNodeTo that accept a 4228/// machine opcode. 4229/// 4230SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4231 MVT VT) { 4232 SDVTList VTs = getVTList(VT); 4233 return SelectNodeTo(N, MachineOpc, VTs, 0, 0); 4234} 4235 4236SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4237 MVT VT, SDValue Op1) { 4238 SDVTList VTs = getVTList(VT); 4239 SDValue Ops[] = { Op1 }; 4240 return SelectNodeTo(N, MachineOpc, VTs, Ops, 1); 4241} 4242 4243SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4244 MVT VT, SDValue Op1, 4245 SDValue Op2) { 4246 SDVTList VTs = getVTList(VT); 4247 SDValue Ops[] = { Op1, Op2 }; 4248 return SelectNodeTo(N, MachineOpc, VTs, Ops, 2); 4249} 4250 4251SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4252 MVT VT, SDValue Op1, 4253 SDValue Op2, SDValue Op3) { 4254 SDVTList VTs = getVTList(VT); 4255 SDValue Ops[] = { Op1, Op2, Op3 }; 4256 return SelectNodeTo(N, MachineOpc, VTs, Ops, 3); 4257} 4258 4259SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4260 MVT VT, const SDValue *Ops, 4261 unsigned NumOps) { 4262 SDVTList VTs = getVTList(VT); 4263 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 4264} 4265 4266SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4267 MVT VT1, MVT VT2, const SDValue *Ops, 4268 unsigned NumOps) { 4269 SDVTList VTs = getVTList(VT1, VT2); 4270 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 4271} 4272 4273SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4274 MVT VT1, MVT VT2) { 4275 SDVTList VTs = getVTList(VT1, VT2); 4276 return SelectNodeTo(N, MachineOpc, VTs, (SDValue *)0, 0); 4277} 4278 4279SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4280 MVT VT1, MVT VT2, MVT VT3, 4281 const SDValue *Ops, unsigned NumOps) { 4282 SDVTList VTs = getVTList(VT1, VT2, VT3); 4283 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 4284} 4285 4286SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4287 MVT VT1, MVT VT2, MVT VT3, MVT VT4, 4288 const SDValue *Ops, unsigned NumOps) { 4289 SDVTList VTs = getVTList(VT1, VT2, VT3, VT4); 4290 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 4291} 4292 4293SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4294 MVT VT1, MVT VT2, 4295 SDValue Op1) { 4296 SDVTList VTs = getVTList(VT1, VT2); 4297 SDValue Ops[] = { Op1 }; 4298 return SelectNodeTo(N, MachineOpc, VTs, Ops, 1); 4299} 4300 4301SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4302 MVT VT1, MVT VT2, 4303 SDValue Op1, SDValue Op2) { 4304 SDVTList VTs = getVTList(VT1, VT2); 4305 SDValue Ops[] = { Op1, Op2 }; 4306 return SelectNodeTo(N, MachineOpc, VTs, Ops, 2); 4307} 4308 4309SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4310 MVT VT1, MVT VT2, 4311 SDValue Op1, SDValue Op2, 4312 SDValue Op3) { 4313 SDVTList VTs = getVTList(VT1, VT2); 4314 SDValue Ops[] = { Op1, Op2, Op3 }; 4315 return SelectNodeTo(N, MachineOpc, VTs, Ops, 3); 4316} 4317 4318SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4319 MVT VT1, MVT VT2, MVT VT3, 4320 SDValue Op1, SDValue Op2, 4321 SDValue Op3) { 4322 SDVTList VTs = getVTList(VT1, VT2, VT3); 4323 SDValue Ops[] = { Op1, Op2, Op3 }; 4324 return SelectNodeTo(N, MachineOpc, VTs, Ops, 3); 4325} 4326 4327SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4328 SDVTList VTs, const SDValue *Ops, 4329 unsigned NumOps) { 4330 return MorphNodeTo(N, ~MachineOpc, VTs, Ops, NumOps); 4331} 4332 4333SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4334 MVT VT) { 4335 SDVTList VTs = getVTList(VT); 4336 return MorphNodeTo(N, Opc, VTs, 0, 0); 4337} 4338 4339SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4340 MVT VT, SDValue Op1) { 4341 SDVTList VTs = getVTList(VT); 4342 SDValue Ops[] = { Op1 }; 4343 return MorphNodeTo(N, Opc, VTs, Ops, 1); 4344} 4345 4346SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4347 MVT VT, SDValue Op1, 4348 SDValue Op2) { 4349 SDVTList VTs = getVTList(VT); 4350 SDValue Ops[] = { Op1, Op2 }; 4351 return MorphNodeTo(N, Opc, VTs, Ops, 2); 4352} 4353 4354SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4355 MVT VT, SDValue Op1, 4356 SDValue Op2, SDValue Op3) { 4357 SDVTList VTs = getVTList(VT); 4358 SDValue Ops[] = { Op1, Op2, Op3 }; 4359 return MorphNodeTo(N, Opc, VTs, Ops, 3); 4360} 4361 4362SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4363 MVT VT, const SDValue *Ops, 4364 unsigned NumOps) { 4365 SDVTList VTs = getVTList(VT); 4366 return MorphNodeTo(N, Opc, VTs, Ops, NumOps); 4367} 4368 4369SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4370 MVT VT1, MVT VT2, const SDValue *Ops, 4371 unsigned NumOps) { 4372 SDVTList VTs = getVTList(VT1, VT2); 4373 return MorphNodeTo(N, Opc, VTs, Ops, NumOps); 4374} 4375 4376SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4377 MVT VT1, MVT VT2) { 4378 SDVTList VTs = getVTList(VT1, VT2); 4379 return MorphNodeTo(N, Opc, VTs, (SDValue *)0, 0); 4380} 4381 4382SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4383 MVT VT1, MVT VT2, MVT VT3, 4384 const SDValue *Ops, unsigned NumOps) { 4385 SDVTList VTs = getVTList(VT1, VT2, VT3); 4386 return MorphNodeTo(N, Opc, VTs, Ops, NumOps); 4387} 4388 4389SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4390 MVT VT1, MVT VT2, 4391 SDValue Op1) { 4392 SDVTList VTs = getVTList(VT1, VT2); 4393 SDValue Ops[] = { Op1 }; 4394 return MorphNodeTo(N, Opc, VTs, Ops, 1); 4395} 4396 4397SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4398 MVT VT1, MVT VT2, 4399 SDValue Op1, SDValue Op2) { 4400 SDVTList VTs = getVTList(VT1, VT2); 4401 SDValue Ops[] = { Op1, Op2 }; 4402 return MorphNodeTo(N, Opc, VTs, Ops, 2); 4403} 4404 4405SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4406 MVT VT1, MVT VT2, 4407 SDValue Op1, SDValue Op2, 4408 SDValue Op3) { 4409 SDVTList VTs = getVTList(VT1, VT2); 4410 SDValue Ops[] = { Op1, Op2, Op3 }; 4411 return MorphNodeTo(N, Opc, VTs, Ops, 3); 4412} 4413 4414/// MorphNodeTo - These *mutate* the specified node to have the specified 4415/// return type, opcode, and operands. 4416/// 4417/// Note that MorphNodeTo returns the resultant node. If there is already a 4418/// node of the specified opcode and operands, it returns that node instead of 4419/// the current one. Note that the DebugLoc need not be the same. 4420/// 4421/// Using MorphNodeTo is faster than creating a new node and swapping it in 4422/// with ReplaceAllUsesWith both because it often avoids allocating a new 4423/// node, and because it doesn't require CSE recalculation for any of 4424/// the node's users. 4425/// 4426SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4427 SDVTList VTs, const SDValue *Ops, 4428 unsigned NumOps) { 4429 // If an identical node already exists, use it. 4430 void *IP = 0; 4431 if (VTs.VTs[VTs.NumVTs-1] != MVT::Flag) { 4432 FoldingSetNodeID ID; 4433 AddNodeIDNode(ID, Opc, VTs, Ops, NumOps); 4434 if (SDNode *ON = CSEMap.FindNodeOrInsertPos(ID, IP)) 4435 return ON; 4436 } 4437 4438 if (!RemoveNodeFromCSEMaps(N)) 4439 IP = 0; 4440 4441 // Start the morphing. 4442 N->NodeType = Opc; 4443 N->ValueList = VTs.VTs; 4444 N->NumValues = VTs.NumVTs; 4445 4446 // Clear the operands list, updating used nodes to remove this from their 4447 // use list. Keep track of any operands that become dead as a result. 4448 SmallPtrSet<SDNode*, 16> DeadNodeSet; 4449 for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ) { 4450 SDUse &Use = *I++; 4451 SDNode *Used = Use.getNode(); 4452 Use.set(SDValue()); 4453 if (Used->use_empty()) 4454 DeadNodeSet.insert(Used); 4455 } 4456 4457 // If NumOps is larger than the # of operands we currently have, reallocate 4458 // the operand list. 4459 if (NumOps > N->NumOperands) { 4460 if (N->OperandsNeedDelete) 4461 delete[] N->OperandList; 4462 4463 if (N->isMachineOpcode()) { 4464 // We're creating a final node that will live unmorphed for the 4465 // remainder of the current SelectionDAG iteration, so we can allocate 4466 // the operands directly out of a pool with no recycling metadata. 4467 N->OperandList = OperandAllocator.Allocate<SDUse>(NumOps); 4468 N->OperandsNeedDelete = false; 4469 } else { 4470 N->OperandList = new SDUse[NumOps]; 4471 N->OperandsNeedDelete = true; 4472 } 4473 } 4474 4475 // Assign the new operands. 4476 N->NumOperands = NumOps; 4477 for (unsigned i = 0, e = NumOps; i != e; ++i) { 4478 N->OperandList[i].setUser(N); 4479 N->OperandList[i].setInitial(Ops[i]); 4480 } 4481 4482 // Delete any nodes that are still dead after adding the uses for the 4483 // new operands. 4484 SmallVector<SDNode *, 16> DeadNodes; 4485 for (SmallPtrSet<SDNode *, 16>::iterator I = DeadNodeSet.begin(), 4486 E = DeadNodeSet.end(); I != E; ++I) 4487 if ((*I)->use_empty()) 4488 DeadNodes.push_back(*I); 4489 RemoveDeadNodes(DeadNodes); 4490 4491 if (IP) 4492 CSEMap.InsertNode(N, IP); // Memoize the new node. 4493 return N; 4494} 4495 4496 4497/// getTargetNode - These are used for target selectors to create a new node 4498/// with specified return type(s), target opcode, and operands. 4499/// 4500/// Note that getTargetNode returns the resultant node. If there is already a 4501/// node of the specified opcode and operands, it returns that node instead of 4502/// the current one. 4503SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT) { 4504 return getNode(~Opcode, dl, VT).getNode(); 4505} 4506 4507SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, 4508 SDValue Op1) { 4509 return getNode(~Opcode, dl, VT, Op1).getNode(); 4510} 4511 4512SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, 4513 SDValue Op1, SDValue Op2) { 4514 return getNode(~Opcode, dl, VT, Op1, Op2).getNode(); 4515} 4516 4517SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, 4518 SDValue Op1, SDValue Op2, 4519 SDValue Op3) { 4520 return getNode(~Opcode, dl, VT, Op1, Op2, Op3).getNode(); 4521} 4522 4523SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, 4524 const SDValue *Ops, unsigned NumOps) { 4525 return getNode(~Opcode, dl, VT, Ops, NumOps).getNode(); 4526} 4527 4528SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, 4529 MVT VT1, MVT VT2) { 4530 SDVTList VTs = getVTList(VT1, VT2); 4531 SDValue Op; 4532 return getNode(~Opcode, dl, VTs, &Op, 0).getNode(); 4533} 4534 4535SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, 4536 MVT VT2, SDValue Op1) { 4537 SDVTList VTs = getVTList(VT1, VT2); 4538 return getNode(~Opcode, dl, VTs, &Op1, 1).getNode(); 4539} 4540 4541SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, 4542 MVT VT2, SDValue Op1, 4543 SDValue Op2) { 4544 SDVTList VTs = getVTList(VT1, VT2); 4545 SDValue Ops[] = { Op1, Op2 }; 4546 return getNode(~Opcode, dl, VTs, Ops, 2).getNode(); 4547} 4548 4549SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, 4550 MVT VT2, SDValue Op1, 4551 SDValue Op2, SDValue Op3) { 4552 SDVTList VTs = getVTList(VT1, VT2); 4553 SDValue Ops[] = { Op1, Op2, Op3 }; 4554 return getNode(~Opcode, dl, VTs, Ops, 3).getNode(); 4555} 4556 4557SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, 4558 MVT VT1, MVT VT2, 4559 const SDValue *Ops, unsigned NumOps) { 4560 SDVTList VTs = getVTList(VT1, VT2); 4561 return getNode(~Opcode, dl, VTs, Ops, NumOps).getNode(); 4562} 4563 4564SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, 4565 MVT VT1, MVT VT2, MVT VT3, 4566 SDValue Op1, SDValue Op2) { 4567 SDVTList VTs = getVTList(VT1, VT2, VT3); 4568 SDValue Ops[] = { Op1, Op2 }; 4569 return getNode(~Opcode, dl, VTs, Ops, 2).getNode(); 4570} 4571 4572SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, 4573 MVT VT1, MVT VT2, MVT VT3, 4574 SDValue Op1, SDValue Op2, 4575 SDValue Op3) { 4576 SDVTList VTs = getVTList(VT1, VT2, VT3); 4577 SDValue Ops[] = { Op1, Op2, Op3 }; 4578 return getNode(~Opcode, dl, VTs, Ops, 3).getNode(); 4579} 4580 4581SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, 4582 MVT VT1, MVT VT2, MVT VT3, 4583 const SDValue *Ops, unsigned NumOps) { 4584 SDVTList VTs = getVTList(VT1, VT2, VT3); 4585 return getNode(~Opcode, dl, VTs, Ops, NumOps).getNode(); 4586} 4587 4588SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, 4589 MVT VT2, MVT VT3, MVT VT4, 4590 const SDValue *Ops, unsigned NumOps) { 4591 SDVTList VTs = getVTList(VT1, VT2, VT3, VT4); 4592 return getNode(~Opcode, dl, VTs, Ops, NumOps).getNode(); 4593} 4594 4595SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, 4596 const std::vector<MVT> &ResultTys, 4597 const SDValue *Ops, unsigned NumOps) { 4598 return getNode(~Opcode, dl, ResultTys, Ops, NumOps).getNode(); 4599} 4600 4601/// getNodeIfExists - Get the specified node if it's already available, or 4602/// else return NULL. 4603SDNode *SelectionDAG::getNodeIfExists(unsigned Opcode, SDVTList VTList, 4604 const SDValue *Ops, unsigned NumOps) { 4605 if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) { 4606 FoldingSetNodeID ID; 4607 AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps); 4608 void *IP = 0; 4609 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 4610 return E; 4611 } 4612 return NULL; 4613} 4614 4615/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. 4616/// This can cause recursive merging of nodes in the DAG. 4617/// 4618/// This version assumes From has a single result value. 4619/// 4620void SelectionDAG::ReplaceAllUsesWith(SDValue FromN, SDValue To, 4621 DAGUpdateListener *UpdateListener) { 4622 SDNode *From = FromN.getNode(); 4623 assert(From->getNumValues() == 1 && FromN.getResNo() == 0 && 4624 "Cannot replace with this method!"); 4625 assert(From != To.getNode() && "Cannot replace uses of with self"); 4626 4627 // Iterate over all the existing uses of From. New uses will be added 4628 // to the beginning of the use list, which we avoid visiting. 4629 // This specifically avoids visiting uses of From that arise while the 4630 // replacement is happening, because any such uses would be the result 4631 // of CSE: If an existing node looks like From after one of its operands 4632 // is replaced by To, we don't want to replace of all its users with To 4633 // too. See PR3018 for more info. 4634 SDNode::use_iterator UI = From->use_begin(), UE = From->use_end(); 4635 while (UI != UE) { 4636 SDNode *User = *UI; 4637 4638 // This node is about to morph, remove its old self from the CSE maps. 4639 RemoveNodeFromCSEMaps(User); 4640 4641 // A user can appear in a use list multiple times, and when this 4642 // happens the uses are usually next to each other in the list. 4643 // To help reduce the number of CSE recomputations, process all 4644 // the uses of this user that we can find this way. 4645 do { 4646 SDUse &Use = UI.getUse(); 4647 ++UI; 4648 Use.set(To); 4649 } while (UI != UE && *UI == User); 4650 4651 // Now that we have modified User, add it back to the CSE maps. If it 4652 // already exists there, recursively merge the results together. 4653 AddModifiedNodeToCSEMaps(User, UpdateListener); 4654 } 4655} 4656 4657/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. 4658/// This can cause recursive merging of nodes in the DAG. 4659/// 4660/// This version assumes that for each value of From, there is a 4661/// corresponding value in To in the same position with the same type. 4662/// 4663void SelectionDAG::ReplaceAllUsesWith(SDNode *From, SDNode *To, 4664 DAGUpdateListener *UpdateListener) { 4665#ifndef NDEBUG 4666 for (unsigned i = 0, e = From->getNumValues(); i != e; ++i) 4667 assert((!From->hasAnyUseOfValue(i) || 4668 From->getValueType(i) == To->getValueType(i)) && 4669 "Cannot use this version of ReplaceAllUsesWith!"); 4670#endif 4671 4672 // Handle the trivial case. 4673 if (From == To) 4674 return; 4675 4676 // Iterate over just the existing users of From. See the comments in 4677 // the ReplaceAllUsesWith above. 4678 SDNode::use_iterator UI = From->use_begin(), UE = From->use_end(); 4679 while (UI != UE) { 4680 SDNode *User = *UI; 4681 4682 // This node is about to morph, remove its old self from the CSE maps. 4683 RemoveNodeFromCSEMaps(User); 4684 4685 // A user can appear in a use list multiple times, and when this 4686 // happens the uses are usually next to each other in the list. 4687 // To help reduce the number of CSE recomputations, process all 4688 // the uses of this user that we can find this way. 4689 do { 4690 SDUse &Use = UI.getUse(); 4691 ++UI; 4692 Use.setNode(To); 4693 } while (UI != UE && *UI == User); 4694 4695 // Now that we have modified User, add it back to the CSE maps. If it 4696 // already exists there, recursively merge the results together. 4697 AddModifiedNodeToCSEMaps(User, UpdateListener); 4698 } 4699} 4700 4701/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. 4702/// This can cause recursive merging of nodes in the DAG. 4703/// 4704/// This version can replace From with any result values. To must match the 4705/// number and types of values returned by From. 4706void SelectionDAG::ReplaceAllUsesWith(SDNode *From, 4707 const SDValue *To, 4708 DAGUpdateListener *UpdateListener) { 4709 if (From->getNumValues() == 1) // Handle the simple case efficiently. 4710 return ReplaceAllUsesWith(SDValue(From, 0), To[0], UpdateListener); 4711 4712 // Iterate over just the existing users of From. See the comments in 4713 // the ReplaceAllUsesWith above. 4714 SDNode::use_iterator UI = From->use_begin(), UE = From->use_end(); 4715 while (UI != UE) { 4716 SDNode *User = *UI; 4717 4718 // This node is about to morph, remove its old self from the CSE maps. 4719 RemoveNodeFromCSEMaps(User); 4720 4721 // A user can appear in a use list multiple times, and when this 4722 // happens the uses are usually next to each other in the list. 4723 // To help reduce the number of CSE recomputations, process all 4724 // the uses of this user that we can find this way. 4725 do { 4726 SDUse &Use = UI.getUse(); 4727 const SDValue &ToOp = To[Use.getResNo()]; 4728 ++UI; 4729 Use.set(ToOp); 4730 } while (UI != UE && *UI == User); 4731 4732 // Now that we have modified User, add it back to the CSE maps. If it 4733 // already exists there, recursively merge the results together. 4734 AddModifiedNodeToCSEMaps(User, UpdateListener); 4735 } 4736} 4737 4738/// ReplaceAllUsesOfValueWith - Replace any uses of From with To, leaving 4739/// uses of other values produced by From.getNode() alone. The Deleted 4740/// vector is handled the same way as for ReplaceAllUsesWith. 4741void SelectionDAG::ReplaceAllUsesOfValueWith(SDValue From, SDValue To, 4742 DAGUpdateListener *UpdateListener){ 4743 // Handle the really simple, really trivial case efficiently. 4744 if (From == To) return; 4745 4746 // Handle the simple, trivial, case efficiently. 4747 if (From.getNode()->getNumValues() == 1) { 4748 ReplaceAllUsesWith(From, To, UpdateListener); 4749 return; 4750 } 4751 4752 // Iterate over just the existing users of From. See the comments in 4753 // the ReplaceAllUsesWith above. 4754 SDNode::use_iterator UI = From.getNode()->use_begin(), 4755 UE = From.getNode()->use_end(); 4756 while (UI != UE) { 4757 SDNode *User = *UI; 4758 bool UserRemovedFromCSEMaps = false; 4759 4760 // A user can appear in a use list multiple times, and when this 4761 // happens the uses are usually next to each other in the list. 4762 // To help reduce the number of CSE recomputations, process all 4763 // the uses of this user that we can find this way. 4764 do { 4765 SDUse &Use = UI.getUse(); 4766 4767 // Skip uses of different values from the same node. 4768 if (Use.getResNo() != From.getResNo()) { 4769 ++UI; 4770 continue; 4771 } 4772 4773 // If this node hasn't been modified yet, it's still in the CSE maps, 4774 // so remove its old self from the CSE maps. 4775 if (!UserRemovedFromCSEMaps) { 4776 RemoveNodeFromCSEMaps(User); 4777 UserRemovedFromCSEMaps = true; 4778 } 4779 4780 ++UI; 4781 Use.set(To); 4782 } while (UI != UE && *UI == User); 4783 4784 // We are iterating over all uses of the From node, so if a use 4785 // doesn't use the specific value, no changes are made. 4786 if (!UserRemovedFromCSEMaps) 4787 continue; 4788 4789 // Now that we have modified User, add it back to the CSE maps. If it 4790 // already exists there, recursively merge the results together. 4791 AddModifiedNodeToCSEMaps(User, UpdateListener); 4792 } 4793} 4794 4795namespace { 4796 /// UseMemo - This class is used by SelectionDAG::ReplaceAllUsesOfValuesWith 4797 /// to record information about a use. 4798 struct UseMemo { 4799 SDNode *User; 4800 unsigned Index; 4801 SDUse *Use; 4802 }; 4803 4804 /// operator< - Sort Memos by User. 4805 bool operator<(const UseMemo &L, const UseMemo &R) { 4806 return (intptr_t)L.User < (intptr_t)R.User; 4807 } 4808} 4809 4810/// ReplaceAllUsesOfValuesWith - Replace any uses of From with To, leaving 4811/// uses of other values produced by From.getNode() alone. The same value 4812/// may appear in both the From and To list. The Deleted vector is 4813/// handled the same way as for ReplaceAllUsesWith. 4814void SelectionDAG::ReplaceAllUsesOfValuesWith(const SDValue *From, 4815 const SDValue *To, 4816 unsigned Num, 4817 DAGUpdateListener *UpdateListener){ 4818 // Handle the simple, trivial case efficiently. 4819 if (Num == 1) 4820 return ReplaceAllUsesOfValueWith(*From, *To, UpdateListener); 4821 4822 // Read up all the uses and make records of them. This helps 4823 // processing new uses that are introduced during the 4824 // replacement process. 4825 SmallVector<UseMemo, 4> Uses; 4826 for (unsigned i = 0; i != Num; ++i) { 4827 unsigned FromResNo = From[i].getResNo(); 4828 SDNode *FromNode = From[i].getNode(); 4829 for (SDNode::use_iterator UI = FromNode->use_begin(), 4830 E = FromNode->use_end(); UI != E; ++UI) { 4831 SDUse &Use = UI.getUse(); 4832 if (Use.getResNo() == FromResNo) { 4833 UseMemo Memo = { *UI, i, &Use }; 4834 Uses.push_back(Memo); 4835 } 4836 } 4837 } 4838 4839 // Sort the uses, so that all the uses from a given User are together. 4840 std::sort(Uses.begin(), Uses.end()); 4841 4842 for (unsigned UseIndex = 0, UseIndexEnd = Uses.size(); 4843 UseIndex != UseIndexEnd; ) { 4844 // We know that this user uses some value of From. If it is the right 4845 // value, update it. 4846 SDNode *User = Uses[UseIndex].User; 4847 4848 // This node is about to morph, remove its old self from the CSE maps. 4849 RemoveNodeFromCSEMaps(User); 4850 4851 // The Uses array is sorted, so all the uses for a given User 4852 // are next to each other in the list. 4853 // To help reduce the number of CSE recomputations, process all 4854 // the uses of this user that we can find this way. 4855 do { 4856 unsigned i = Uses[UseIndex].Index; 4857 SDUse &Use = *Uses[UseIndex].Use; 4858 ++UseIndex; 4859 4860 Use.set(To[i]); 4861 } while (UseIndex != UseIndexEnd && Uses[UseIndex].User == User); 4862 4863 // Now that we have modified User, add it back to the CSE maps. If it 4864 // already exists there, recursively merge the results together. 4865 AddModifiedNodeToCSEMaps(User, UpdateListener); 4866 } 4867} 4868 4869/// AssignTopologicalOrder - Assign a unique node id for each node in the DAG 4870/// based on their topological order. It returns the maximum id and a vector 4871/// of the SDNodes* in assigned order by reference. 4872unsigned SelectionDAG::AssignTopologicalOrder() { 4873 4874 unsigned DAGSize = 0; 4875 4876 // SortedPos tracks the progress of the algorithm. Nodes before it are 4877 // sorted, nodes after it are unsorted. When the algorithm completes 4878 // it is at the end of the list. 4879 allnodes_iterator SortedPos = allnodes_begin(); 4880 4881 // Visit all the nodes. Move nodes with no operands to the front of 4882 // the list immediately. Annotate nodes that do have operands with their 4883 // operand count. Before we do this, the Node Id fields of the nodes 4884 // may contain arbitrary values. After, the Node Id fields for nodes 4885 // before SortedPos will contain the topological sort index, and the 4886 // Node Id fields for nodes At SortedPos and after will contain the 4887 // count of outstanding operands. 4888 for (allnodes_iterator I = allnodes_begin(),E = allnodes_end(); I != E; ) { 4889 SDNode *N = I++; 4890 unsigned Degree = N->getNumOperands(); 4891 if (Degree == 0) { 4892 // A node with no uses, add it to the result array immediately. 4893 N->setNodeId(DAGSize++); 4894 allnodes_iterator Q = N; 4895 if (Q != SortedPos) 4896 SortedPos = AllNodes.insert(SortedPos, AllNodes.remove(Q)); 4897 ++SortedPos; 4898 } else { 4899 // Temporarily use the Node Id as scratch space for the degree count. 4900 N->setNodeId(Degree); 4901 } 4902 } 4903 4904 // Visit all the nodes. As we iterate, moves nodes into sorted order, 4905 // such that by the time the end is reached all nodes will be sorted. 4906 for (allnodes_iterator I = allnodes_begin(),E = allnodes_end(); I != E; ++I) { 4907 SDNode *N = I; 4908 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 4909 UI != UE; ++UI) { 4910 SDNode *P = *UI; 4911 unsigned Degree = P->getNodeId(); 4912 --Degree; 4913 if (Degree == 0) { 4914 // All of P's operands are sorted, so P may sorted now. 4915 P->setNodeId(DAGSize++); 4916 if (P != SortedPos) 4917 SortedPos = AllNodes.insert(SortedPos, AllNodes.remove(P)); 4918 ++SortedPos; 4919 } else { 4920 // Update P's outstanding operand count. 4921 P->setNodeId(Degree); 4922 } 4923 } 4924 } 4925 4926 assert(SortedPos == AllNodes.end() && 4927 "Topological sort incomplete!"); 4928 assert(AllNodes.front().getOpcode() == ISD::EntryToken && 4929 "First node in topological sort is not the entry token!"); 4930 assert(AllNodes.front().getNodeId() == 0 && 4931 "First node in topological sort has non-zero id!"); 4932 assert(AllNodes.front().getNumOperands() == 0 && 4933 "First node in topological sort has operands!"); 4934 assert(AllNodes.back().getNodeId() == (int)DAGSize-1 && 4935 "Last node in topologic sort has unexpected id!"); 4936 assert(AllNodes.back().use_empty() && 4937 "Last node in topologic sort has users!"); 4938 assert(DAGSize == allnodes_size() && "Node count mismatch!"); 4939 return DAGSize; 4940} 4941 4942 4943 4944//===----------------------------------------------------------------------===// 4945// SDNode Class 4946//===----------------------------------------------------------------------===// 4947 4948HandleSDNode::~HandleSDNode() { 4949 DropOperands(); 4950} 4951 4952GlobalAddressSDNode::GlobalAddressSDNode(unsigned Opc, const GlobalValue *GA, 4953 MVT VT, int64_t o, unsigned char TF) 4954 : SDNode(Opc, DebugLoc::getUnknownLoc(), getSDVTList(VT)), 4955 Offset(o), TargetFlags(TF) { 4956 TheGlobal = const_cast<GlobalValue*>(GA); 4957} 4958 4959MemSDNode::MemSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, MVT memvt, 4960 const Value *srcValue, int SVO, 4961 unsigned alignment, bool vol) 4962 : SDNode(Opc, dl, VTs), MemoryVT(memvt), SrcValue(srcValue), SVOffset(SVO) { 4963 SubclassData = encodeMemSDNodeFlags(0, ISD::UNINDEXED, vol, alignment); 4964 assert(isPowerOf2_32(alignment) && "Alignment is not a power of 2!"); 4965 assert(getAlignment() == alignment && "Alignment representation error!"); 4966 assert(isVolatile() == vol && "Volatile representation error!"); 4967} 4968 4969MemSDNode::MemSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, 4970 const SDValue *Ops, 4971 unsigned NumOps, MVT memvt, const Value *srcValue, 4972 int SVO, unsigned alignment, bool vol) 4973 : SDNode(Opc, dl, VTs, Ops, NumOps), 4974 MemoryVT(memvt), SrcValue(srcValue), SVOffset(SVO) { 4975 SubclassData = encodeMemSDNodeFlags(0, ISD::UNINDEXED, vol, alignment); 4976 assert(isPowerOf2_32(alignment) && "Alignment is not a power of 2!"); 4977 assert(getAlignment() == alignment && "Alignment representation error!"); 4978 assert(isVolatile() == vol && "Volatile representation error!"); 4979} 4980 4981/// getMemOperand - Return a MachineMemOperand object describing the memory 4982/// reference performed by this memory reference. 4983MachineMemOperand MemSDNode::getMemOperand() const { 4984 int Flags = 0; 4985 if (isa<LoadSDNode>(this)) 4986 Flags = MachineMemOperand::MOLoad; 4987 else if (isa<StoreSDNode>(this)) 4988 Flags = MachineMemOperand::MOStore; 4989 else if (isa<AtomicSDNode>(this)) { 4990 Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore; 4991 } 4992 else { 4993 const MemIntrinsicSDNode* MemIntrinNode = dyn_cast<MemIntrinsicSDNode>(this); 4994 assert(MemIntrinNode && "Unknown MemSDNode opcode!"); 4995 if (MemIntrinNode->readMem()) Flags |= MachineMemOperand::MOLoad; 4996 if (MemIntrinNode->writeMem()) Flags |= MachineMemOperand::MOStore; 4997 } 4998 4999 int Size = (getMemoryVT().getSizeInBits() + 7) >> 3; 5000 if (isVolatile()) Flags |= MachineMemOperand::MOVolatile; 5001 5002 // Check if the memory reference references a frame index 5003 const FrameIndexSDNode *FI = 5004 dyn_cast<const FrameIndexSDNode>(getBasePtr().getNode()); 5005 if (!getSrcValue() && FI) 5006 return MachineMemOperand(PseudoSourceValue::getFixedStack(FI->getIndex()), 5007 Flags, 0, Size, getAlignment()); 5008 else 5009 return MachineMemOperand(getSrcValue(), Flags, getSrcValueOffset(), 5010 Size, getAlignment()); 5011} 5012 5013/// Profile - Gather unique data for the node. 5014/// 5015void SDNode::Profile(FoldingSetNodeID &ID) const { 5016 AddNodeIDNode(ID, this); 5017} 5018 5019static ManagedStatic<std::set<MVT, MVT::compareRawBits> > EVTs; 5020static MVT VTs[MVT::LAST_VALUETYPE]; 5021static ManagedStatic<sys::SmartMutex<true> > VTMutex; 5022 5023/// getValueTypeList - Return a pointer to the specified value type. 5024/// 5025const MVT *SDNode::getValueTypeList(MVT VT) { 5026 sys::SmartScopedLock<true> Lock(*VTMutex); 5027 if (VT.isExtended()) { 5028 return &(*EVTs->insert(VT).first); 5029 } else { 5030 VTs[VT.getSimpleVT()] = VT; 5031 return &VTs[VT.getSimpleVT()]; 5032 } 5033} 5034 5035/// hasNUsesOfValue - Return true if there are exactly NUSES uses of the 5036/// indicated value. This method ignores uses of other values defined by this 5037/// operation. 5038bool SDNode::hasNUsesOfValue(unsigned NUses, unsigned Value) const { 5039 assert(Value < getNumValues() && "Bad value!"); 5040 5041 // TODO: Only iterate over uses of a given value of the node 5042 for (SDNode::use_iterator UI = use_begin(), E = use_end(); UI != E; ++UI) { 5043 if (UI.getUse().getResNo() == Value) { 5044 if (NUses == 0) 5045 return false; 5046 --NUses; 5047 } 5048 } 5049 5050 // Found exactly the right number of uses? 5051 return NUses == 0; 5052} 5053 5054 5055/// hasAnyUseOfValue - Return true if there are any use of the indicated 5056/// value. This method ignores uses of other values defined by this operation. 5057bool SDNode::hasAnyUseOfValue(unsigned Value) const { 5058 assert(Value < getNumValues() && "Bad value!"); 5059 5060 for (SDNode::use_iterator UI = use_begin(), E = use_end(); UI != E; ++UI) 5061 if (UI.getUse().getResNo() == Value) 5062 return true; 5063 5064 return false; 5065} 5066 5067 5068/// isOnlyUserOf - Return true if this node is the only use of N. 5069/// 5070bool SDNode::isOnlyUserOf(SDNode *N) const { 5071 bool Seen = false; 5072 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 5073 SDNode *User = *I; 5074 if (User == this) 5075 Seen = true; 5076 else 5077 return false; 5078 } 5079 5080 return Seen; 5081} 5082 5083/// isOperand - Return true if this node is an operand of N. 5084/// 5085bool SDValue::isOperandOf(SDNode *N) const { 5086 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 5087 if (*this == N->getOperand(i)) 5088 return true; 5089 return false; 5090} 5091 5092bool SDNode::isOperandOf(SDNode *N) const { 5093 for (unsigned i = 0, e = N->NumOperands; i != e; ++i) 5094 if (this == N->OperandList[i].getNode()) 5095 return true; 5096 return false; 5097} 5098 5099/// reachesChainWithoutSideEffects - Return true if this operand (which must 5100/// be a chain) reaches the specified operand without crossing any 5101/// side-effecting instructions. In practice, this looks through token 5102/// factors and non-volatile loads. In order to remain efficient, this only 5103/// looks a couple of nodes in, it does not do an exhaustive search. 5104bool SDValue::reachesChainWithoutSideEffects(SDValue Dest, 5105 unsigned Depth) const { 5106 if (*this == Dest) return true; 5107 5108 // Don't search too deeply, we just want to be able to see through 5109 // TokenFactor's etc. 5110 if (Depth == 0) return false; 5111 5112 // If this is a token factor, all inputs to the TF happen in parallel. If any 5113 // of the operands of the TF reach dest, then we can do the xform. 5114 if (getOpcode() == ISD::TokenFactor) { 5115 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) 5116 if (getOperand(i).reachesChainWithoutSideEffects(Dest, Depth-1)) 5117 return true; 5118 return false; 5119 } 5120 5121 // Loads don't have side effects, look through them. 5122 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(*this)) { 5123 if (!Ld->isVolatile()) 5124 return Ld->getChain().reachesChainWithoutSideEffects(Dest, Depth-1); 5125 } 5126 return false; 5127} 5128 5129 5130static void findPredecessor(SDNode *N, const SDNode *P, bool &found, 5131 SmallPtrSet<SDNode *, 32> &Visited) { 5132 if (found || !Visited.insert(N)) 5133 return; 5134 5135 for (unsigned i = 0, e = N->getNumOperands(); !found && i != e; ++i) { 5136 SDNode *Op = N->getOperand(i).getNode(); 5137 if (Op == P) { 5138 found = true; 5139 return; 5140 } 5141 findPredecessor(Op, P, found, Visited); 5142 } 5143} 5144 5145/// isPredecessorOf - Return true if this node is a predecessor of N. This node 5146/// is either an operand of N or it can be reached by recursively traversing 5147/// up the operands. 5148/// NOTE: this is an expensive method. Use it carefully. 5149bool SDNode::isPredecessorOf(SDNode *N) const { 5150 SmallPtrSet<SDNode *, 32> Visited; 5151 bool found = false; 5152 findPredecessor(N, this, found, Visited); 5153 return found; 5154} 5155 5156uint64_t SDNode::getConstantOperandVal(unsigned Num) const { 5157 assert(Num < NumOperands && "Invalid child # of SDNode!"); 5158 return cast<ConstantSDNode>(OperandList[Num])->getZExtValue(); 5159} 5160 5161std::string SDNode::getOperationName(const SelectionDAG *G) const { 5162 switch (getOpcode()) { 5163 default: 5164 if (getOpcode() < ISD::BUILTIN_OP_END) 5165 return "<<Unknown DAG Node>>"; 5166 if (isMachineOpcode()) { 5167 if (G) 5168 if (const TargetInstrInfo *TII = G->getTarget().getInstrInfo()) 5169 if (getMachineOpcode() < TII->getNumOpcodes()) 5170 return TII->get(getMachineOpcode()).getName(); 5171 return "<<Unknown Machine Node>>"; 5172 } 5173 if (G) { 5174 const TargetLowering &TLI = G->getTargetLoweringInfo(); 5175 const char *Name = TLI.getTargetNodeName(getOpcode()); 5176 if (Name) return Name; 5177 return "<<Unknown Target Node>>"; 5178 } 5179 return "<<Unknown Node>>"; 5180 5181#ifndef NDEBUG 5182 case ISD::DELETED_NODE: 5183 return "<<Deleted Node!>>"; 5184#endif 5185 case ISD::PREFETCH: return "Prefetch"; 5186 case ISD::MEMBARRIER: return "MemBarrier"; 5187 case ISD::ATOMIC_CMP_SWAP: return "AtomicCmpSwap"; 5188 case ISD::ATOMIC_SWAP: return "AtomicSwap"; 5189 case ISD::ATOMIC_LOAD_ADD: return "AtomicLoadAdd"; 5190 case ISD::ATOMIC_LOAD_SUB: return "AtomicLoadSub"; 5191 case ISD::ATOMIC_LOAD_AND: return "AtomicLoadAnd"; 5192 case ISD::ATOMIC_LOAD_OR: return "AtomicLoadOr"; 5193 case ISD::ATOMIC_LOAD_XOR: return "AtomicLoadXor"; 5194 case ISD::ATOMIC_LOAD_NAND: return "AtomicLoadNand"; 5195 case ISD::ATOMIC_LOAD_MIN: return "AtomicLoadMin"; 5196 case ISD::ATOMIC_LOAD_MAX: return "AtomicLoadMax"; 5197 case ISD::ATOMIC_LOAD_UMIN: return "AtomicLoadUMin"; 5198 case ISD::ATOMIC_LOAD_UMAX: return "AtomicLoadUMax"; 5199 case ISD::PCMARKER: return "PCMarker"; 5200 case ISD::READCYCLECOUNTER: return "ReadCycleCounter"; 5201 case ISD::SRCVALUE: return "SrcValue"; 5202 case ISD::MEMOPERAND: return "MemOperand"; 5203 case ISD::EntryToken: return "EntryToken"; 5204 case ISD::TokenFactor: return "TokenFactor"; 5205 case ISD::AssertSext: return "AssertSext"; 5206 case ISD::AssertZext: return "AssertZext"; 5207 5208 case ISD::BasicBlock: return "BasicBlock"; 5209 case ISD::ARG_FLAGS: return "ArgFlags"; 5210 case ISD::VALUETYPE: return "ValueType"; 5211 case ISD::Register: return "Register"; 5212 5213 case ISD::Constant: return "Constant"; 5214 case ISD::ConstantFP: return "ConstantFP"; 5215 case ISD::GlobalAddress: return "GlobalAddress"; 5216 case ISD::GlobalTLSAddress: return "GlobalTLSAddress"; 5217 case ISD::FrameIndex: return "FrameIndex"; 5218 case ISD::JumpTable: return "JumpTable"; 5219 case ISD::GLOBAL_OFFSET_TABLE: return "GLOBAL_OFFSET_TABLE"; 5220 case ISD::RETURNADDR: return "RETURNADDR"; 5221 case ISD::FRAMEADDR: return "FRAMEADDR"; 5222 case ISD::FRAME_TO_ARGS_OFFSET: return "FRAME_TO_ARGS_OFFSET"; 5223 case ISD::EXCEPTIONADDR: return "EXCEPTIONADDR"; 5224 case ISD::EHSELECTION: return "EHSELECTION"; 5225 case ISD::EH_RETURN: return "EH_RETURN"; 5226 case ISD::ConstantPool: return "ConstantPool"; 5227 case ISD::ExternalSymbol: return "ExternalSymbol"; 5228 case ISD::INTRINSIC_WO_CHAIN: { 5229 unsigned IID = cast<ConstantSDNode>(getOperand(0))->getZExtValue(); 5230 return Intrinsic::getName((Intrinsic::ID)IID); 5231 } 5232 case ISD::INTRINSIC_VOID: 5233 case ISD::INTRINSIC_W_CHAIN: { 5234 unsigned IID = cast<ConstantSDNode>(getOperand(1))->getZExtValue(); 5235 return Intrinsic::getName((Intrinsic::ID)IID); 5236 } 5237 5238 case ISD::BUILD_VECTOR: return "BUILD_VECTOR"; 5239 case ISD::TargetConstant: return "TargetConstant"; 5240 case ISD::TargetConstantFP:return "TargetConstantFP"; 5241 case ISD::TargetGlobalAddress: return "TargetGlobalAddress"; 5242 case ISD::TargetGlobalTLSAddress: return "TargetGlobalTLSAddress"; 5243 case ISD::TargetFrameIndex: return "TargetFrameIndex"; 5244 case ISD::TargetJumpTable: return "TargetJumpTable"; 5245 case ISD::TargetConstantPool: return "TargetConstantPool"; 5246 case ISD::TargetExternalSymbol: return "TargetExternalSymbol"; 5247 5248 case ISD::CopyToReg: return "CopyToReg"; 5249 case ISD::CopyFromReg: return "CopyFromReg"; 5250 case ISD::UNDEF: return "undef"; 5251 case ISD::MERGE_VALUES: return "merge_values"; 5252 case ISD::INLINEASM: return "inlineasm"; 5253 case ISD::DBG_LABEL: return "dbg_label"; 5254 case ISD::EH_LABEL: return "eh_label"; 5255 case ISD::DECLARE: return "declare"; 5256 case ISD::HANDLENODE: return "handlenode"; 5257 case ISD::FORMAL_ARGUMENTS: return "formal_arguments"; 5258 case ISD::CALL: return "call"; 5259 5260 // Unary operators 5261 case ISD::FABS: return "fabs"; 5262 case ISD::FNEG: return "fneg"; 5263 case ISD::FSQRT: return "fsqrt"; 5264 case ISD::FSIN: return "fsin"; 5265 case ISD::FCOS: return "fcos"; 5266 case ISD::FPOWI: return "fpowi"; 5267 case ISD::FPOW: return "fpow"; 5268 case ISD::FTRUNC: return "ftrunc"; 5269 case ISD::FFLOOR: return "ffloor"; 5270 case ISD::FCEIL: return "fceil"; 5271 case ISD::FRINT: return "frint"; 5272 case ISD::FNEARBYINT: return "fnearbyint"; 5273 5274 // Binary operators 5275 case ISD::ADD: return "add"; 5276 case ISD::SUB: return "sub"; 5277 case ISD::MUL: return "mul"; 5278 case ISD::MULHU: return "mulhu"; 5279 case ISD::MULHS: return "mulhs"; 5280 case ISD::SDIV: return "sdiv"; 5281 case ISD::UDIV: return "udiv"; 5282 case ISD::SREM: return "srem"; 5283 case ISD::UREM: return "urem"; 5284 case ISD::SMUL_LOHI: return "smul_lohi"; 5285 case ISD::UMUL_LOHI: return "umul_lohi"; 5286 case ISD::SDIVREM: return "sdivrem"; 5287 case ISD::UDIVREM: return "udivrem"; 5288 case ISD::AND: return "and"; 5289 case ISD::OR: return "or"; 5290 case ISD::XOR: return "xor"; 5291 case ISD::SHL: return "shl"; 5292 case ISD::SRA: return "sra"; 5293 case ISD::SRL: return "srl"; 5294 case ISD::ROTL: return "rotl"; 5295 case ISD::ROTR: return "rotr"; 5296 case ISD::FADD: return "fadd"; 5297 case ISD::FSUB: return "fsub"; 5298 case ISD::FMUL: return "fmul"; 5299 case ISD::FDIV: return "fdiv"; 5300 case ISD::FREM: return "frem"; 5301 case ISD::FCOPYSIGN: return "fcopysign"; 5302 case ISD::FGETSIGN: return "fgetsign"; 5303 5304 case ISD::SETCC: return "setcc"; 5305 case ISD::VSETCC: return "vsetcc"; 5306 case ISD::SELECT: return "select"; 5307 case ISD::SELECT_CC: return "select_cc"; 5308 case ISD::INSERT_VECTOR_ELT: return "insert_vector_elt"; 5309 case ISD::EXTRACT_VECTOR_ELT: return "extract_vector_elt"; 5310 case ISD::CONCAT_VECTORS: return "concat_vectors"; 5311 case ISD::EXTRACT_SUBVECTOR: return "extract_subvector"; 5312 case ISD::SCALAR_TO_VECTOR: return "scalar_to_vector"; 5313 case ISD::VECTOR_SHUFFLE: return "vector_shuffle"; 5314 case ISD::CARRY_FALSE: return "carry_false"; 5315 case ISD::ADDC: return "addc"; 5316 case ISD::ADDE: return "adde"; 5317 case ISD::SADDO: return "saddo"; 5318 case ISD::UADDO: return "uaddo"; 5319 case ISD::SSUBO: return "ssubo"; 5320 case ISD::USUBO: return "usubo"; 5321 case ISD::SMULO: return "smulo"; 5322 case ISD::UMULO: return "umulo"; 5323 case ISD::SUBC: return "subc"; 5324 case ISD::SUBE: return "sube"; 5325 case ISD::SHL_PARTS: return "shl_parts"; 5326 case ISD::SRA_PARTS: return "sra_parts"; 5327 case ISD::SRL_PARTS: return "srl_parts"; 5328 5329 // Conversion operators. 5330 case ISD::SIGN_EXTEND: return "sign_extend"; 5331 case ISD::ZERO_EXTEND: return "zero_extend"; 5332 case ISD::ANY_EXTEND: return "any_extend"; 5333 case ISD::SIGN_EXTEND_INREG: return "sign_extend_inreg"; 5334 case ISD::TRUNCATE: return "truncate"; 5335 case ISD::FP_ROUND: return "fp_round"; 5336 case ISD::FLT_ROUNDS_: return "flt_rounds"; 5337 case ISD::FP_ROUND_INREG: return "fp_round_inreg"; 5338 case ISD::FP_EXTEND: return "fp_extend"; 5339 5340 case ISD::SINT_TO_FP: return "sint_to_fp"; 5341 case ISD::UINT_TO_FP: return "uint_to_fp"; 5342 case ISD::FP_TO_SINT: return "fp_to_sint"; 5343 case ISD::FP_TO_UINT: return "fp_to_uint"; 5344 case ISD::BIT_CONVERT: return "bit_convert"; 5345 5346 case ISD::CONVERT_RNDSAT: { 5347 switch (cast<CvtRndSatSDNode>(this)->getCvtCode()) { 5348 default: llvm_unreachable("Unknown cvt code!"); 5349 case ISD::CVT_FF: return "cvt_ff"; 5350 case ISD::CVT_FS: return "cvt_fs"; 5351 case ISD::CVT_FU: return "cvt_fu"; 5352 case ISD::CVT_SF: return "cvt_sf"; 5353 case ISD::CVT_UF: return "cvt_uf"; 5354 case ISD::CVT_SS: return "cvt_ss"; 5355 case ISD::CVT_SU: return "cvt_su"; 5356 case ISD::CVT_US: return "cvt_us"; 5357 case ISD::CVT_UU: return "cvt_uu"; 5358 } 5359 } 5360 5361 // Control flow instructions 5362 case ISD::BR: return "br"; 5363 case ISD::BRIND: return "brind"; 5364 case ISD::BR_JT: return "br_jt"; 5365 case ISD::BRCOND: return "brcond"; 5366 case ISD::BR_CC: return "br_cc"; 5367 case ISD::RET: return "ret"; 5368 case ISD::CALLSEQ_START: return "callseq_start"; 5369 case ISD::CALLSEQ_END: return "callseq_end"; 5370 5371 // Other operators 5372 case ISD::LOAD: return "load"; 5373 case ISD::STORE: return "store"; 5374 case ISD::VAARG: return "vaarg"; 5375 case ISD::VACOPY: return "vacopy"; 5376 case ISD::VAEND: return "vaend"; 5377 case ISD::VASTART: return "vastart"; 5378 case ISD::DYNAMIC_STACKALLOC: return "dynamic_stackalloc"; 5379 case ISD::EXTRACT_ELEMENT: return "extract_element"; 5380 case ISD::BUILD_PAIR: return "build_pair"; 5381 case ISD::STACKSAVE: return "stacksave"; 5382 case ISD::STACKRESTORE: return "stackrestore"; 5383 case ISD::TRAP: return "trap"; 5384 5385 // Bit manipulation 5386 case ISD::BSWAP: return "bswap"; 5387 case ISD::CTPOP: return "ctpop"; 5388 case ISD::CTTZ: return "cttz"; 5389 case ISD::CTLZ: return "ctlz"; 5390 5391 // Debug info 5392 case ISD::DBG_STOPPOINT: return "dbg_stoppoint"; 5393 case ISD::DEBUG_LOC: return "debug_loc"; 5394 5395 // Trampolines 5396 case ISD::TRAMPOLINE: return "trampoline"; 5397 5398 case ISD::CONDCODE: 5399 switch (cast<CondCodeSDNode>(this)->get()) { 5400 default: llvm_unreachable("Unknown setcc condition!"); 5401 case ISD::SETOEQ: return "setoeq"; 5402 case ISD::SETOGT: return "setogt"; 5403 case ISD::SETOGE: return "setoge"; 5404 case ISD::SETOLT: return "setolt"; 5405 case ISD::SETOLE: return "setole"; 5406 case ISD::SETONE: return "setone"; 5407 5408 case ISD::SETO: return "seto"; 5409 case ISD::SETUO: return "setuo"; 5410 case ISD::SETUEQ: return "setue"; 5411 case ISD::SETUGT: return "setugt"; 5412 case ISD::SETUGE: return "setuge"; 5413 case ISD::SETULT: return "setult"; 5414 case ISD::SETULE: return "setule"; 5415 case ISD::SETUNE: return "setune"; 5416 5417 case ISD::SETEQ: return "seteq"; 5418 case ISD::SETGT: return "setgt"; 5419 case ISD::SETGE: return "setge"; 5420 case ISD::SETLT: return "setlt"; 5421 case ISD::SETLE: return "setle"; 5422 case ISD::SETNE: return "setne"; 5423 } 5424 } 5425} 5426 5427const char *SDNode::getIndexedModeName(ISD::MemIndexedMode AM) { 5428 switch (AM) { 5429 default: 5430 return ""; 5431 case ISD::PRE_INC: 5432 return "<pre-inc>"; 5433 case ISD::PRE_DEC: 5434 return "<pre-dec>"; 5435 case ISD::POST_INC: 5436 return "<post-inc>"; 5437 case ISD::POST_DEC: 5438 return "<post-dec>"; 5439 } 5440} 5441 5442std::string ISD::ArgFlagsTy::getArgFlagsString() { 5443 std::string S = "< "; 5444 5445 if (isZExt()) 5446 S += "zext "; 5447 if (isSExt()) 5448 S += "sext "; 5449 if (isInReg()) 5450 S += "inreg "; 5451 if (isSRet()) 5452 S += "sret "; 5453 if (isByVal()) 5454 S += "byval "; 5455 if (isNest()) 5456 S += "nest "; 5457 if (getByValAlign()) 5458 S += "byval-align:" + utostr(getByValAlign()) + " "; 5459 if (getOrigAlign()) 5460 S += "orig-align:" + utostr(getOrigAlign()) + " "; 5461 if (getByValSize()) 5462 S += "byval-size:" + utostr(getByValSize()) + " "; 5463 return S + ">"; 5464} 5465 5466void SDNode::dump() const { dump(0); } 5467void SDNode::dump(const SelectionDAG *G) const { 5468 print(errs(), G); 5469} 5470 5471void SDNode::print_types(raw_ostream &OS, const SelectionDAG *G) const { 5472 OS << (void*)this << ": "; 5473 5474 for (unsigned i = 0, e = getNumValues(); i != e; ++i) { 5475 if (i) OS << ","; 5476 if (getValueType(i) == MVT::Other) 5477 OS << "ch"; 5478 else 5479 OS << getValueType(i).getMVTString(); 5480 } 5481 OS << " = " << getOperationName(G); 5482} 5483 5484void SDNode::print_details(raw_ostream &OS, const SelectionDAG *G) const { 5485 if (!isTargetOpcode() && getOpcode() == ISD::VECTOR_SHUFFLE) { 5486 const ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(this); 5487 OS << "<"; 5488 for (unsigned i = 0, e = ValueList[0].getVectorNumElements(); i != e; ++i) { 5489 int Idx = SVN->getMaskElt(i); 5490 if (i) OS << ","; 5491 if (Idx < 0) 5492 OS << "u"; 5493 else 5494 OS << Idx; 5495 } 5496 OS << ">"; 5497 } 5498 5499 if (const ConstantSDNode *CSDN = dyn_cast<ConstantSDNode>(this)) { 5500 OS << '<' << CSDN->getAPIntValue() << '>'; 5501 } else if (const ConstantFPSDNode *CSDN = dyn_cast<ConstantFPSDNode>(this)) { 5502 if (&CSDN->getValueAPF().getSemantics()==&APFloat::IEEEsingle) 5503 OS << '<' << CSDN->getValueAPF().convertToFloat() << '>'; 5504 else if (&CSDN->getValueAPF().getSemantics()==&APFloat::IEEEdouble) 5505 OS << '<' << CSDN->getValueAPF().convertToDouble() << '>'; 5506 else { 5507 OS << "<APFloat("; 5508 CSDN->getValueAPF().bitcastToAPInt().dump(); 5509 OS << ")>"; 5510 } 5511 } else if (const GlobalAddressSDNode *GADN = 5512 dyn_cast<GlobalAddressSDNode>(this)) { 5513 int64_t offset = GADN->getOffset(); 5514 OS << '<'; 5515 WriteAsOperand(OS, GADN->getGlobal()); 5516 OS << '>'; 5517 if (offset > 0) 5518 OS << " + " << offset; 5519 else 5520 OS << " " << offset; 5521 if (unsigned int TF = GADN->getTargetFlags()) 5522 OS << " [TF=" << TF << ']'; 5523 } else if (const FrameIndexSDNode *FIDN = dyn_cast<FrameIndexSDNode>(this)) { 5524 OS << "<" << FIDN->getIndex() << ">"; 5525 } else if (const JumpTableSDNode *JTDN = dyn_cast<JumpTableSDNode>(this)) { 5526 OS << "<" << JTDN->getIndex() << ">"; 5527 if (unsigned int TF = JTDN->getTargetFlags()) 5528 OS << " [TF=" << TF << ']'; 5529 } else if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(this)){ 5530 int offset = CP->getOffset(); 5531 if (CP->isMachineConstantPoolEntry()) 5532 OS << "<" << *CP->getMachineCPVal() << ">"; 5533 else 5534 OS << "<" << *CP->getConstVal() << ">"; 5535 if (offset > 0) 5536 OS << " + " << offset; 5537 else 5538 OS << " " << offset; 5539 if (unsigned int TF = CP->getTargetFlags()) 5540 OS << " [TF=" << TF << ']'; 5541 } else if (const BasicBlockSDNode *BBDN = dyn_cast<BasicBlockSDNode>(this)) { 5542 OS << "<"; 5543 const Value *LBB = (const Value*)BBDN->getBasicBlock()->getBasicBlock(); 5544 if (LBB) 5545 OS << LBB->getName() << " "; 5546 OS << (const void*)BBDN->getBasicBlock() << ">"; 5547 } else if (const RegisterSDNode *R = dyn_cast<RegisterSDNode>(this)) { 5548 if (G && R->getReg() && 5549 TargetRegisterInfo::isPhysicalRegister(R->getReg())) { 5550 OS << " " << G->getTarget().getRegisterInfo()->getName(R->getReg()); 5551 } else { 5552 OS << " #" << R->getReg(); 5553 } 5554 } else if (const ExternalSymbolSDNode *ES = 5555 dyn_cast<ExternalSymbolSDNode>(this)) { 5556 OS << "'" << ES->getSymbol() << "'"; 5557 if (unsigned int TF = ES->getTargetFlags()) 5558 OS << " [TF=" << TF << ']'; 5559 } else if (const SrcValueSDNode *M = dyn_cast<SrcValueSDNode>(this)) { 5560 if (M->getValue()) 5561 OS << "<" << M->getValue() << ">"; 5562 else 5563 OS << "<null>"; 5564 } else if (const MemOperandSDNode *M = dyn_cast<MemOperandSDNode>(this)) { 5565 if (M->MO.getValue()) 5566 OS << "<" << M->MO.getValue() << ":" << M->MO.getOffset() << ">"; 5567 else 5568 OS << "<null:" << M->MO.getOffset() << ">"; 5569 } else if (const ARG_FLAGSSDNode *N = dyn_cast<ARG_FLAGSSDNode>(this)) { 5570 OS << N->getArgFlags().getArgFlagsString(); 5571 } else if (const VTSDNode *N = dyn_cast<VTSDNode>(this)) { 5572 OS << ":" << N->getVT().getMVTString(); 5573 } 5574 else if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(this)) { 5575 const Value *SrcValue = LD->getSrcValue(); 5576 int SrcOffset = LD->getSrcValueOffset(); 5577 OS << " <"; 5578 if (SrcValue) 5579 OS << SrcValue; 5580 else 5581 OS << "null"; 5582 OS << ":" << SrcOffset << ">"; 5583 5584 bool doExt = true; 5585 switch (LD->getExtensionType()) { 5586 default: doExt = false; break; 5587 case ISD::EXTLOAD: OS << " <anyext "; break; 5588 case ISD::SEXTLOAD: OS << " <sext "; break; 5589 case ISD::ZEXTLOAD: OS << " <zext "; break; 5590 } 5591 if (doExt) 5592 OS << LD->getMemoryVT().getMVTString() << ">"; 5593 5594 const char *AM = getIndexedModeName(LD->getAddressingMode()); 5595 if (*AM) 5596 OS << " " << AM; 5597 if (LD->isVolatile()) 5598 OS << " <volatile>"; 5599 OS << " alignment=" << LD->getAlignment(); 5600 } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(this)) { 5601 const Value *SrcValue = ST->getSrcValue(); 5602 int SrcOffset = ST->getSrcValueOffset(); 5603 OS << " <"; 5604 if (SrcValue) 5605 OS << SrcValue; 5606 else 5607 OS << "null"; 5608 OS << ":" << SrcOffset << ">"; 5609 5610 if (ST->isTruncatingStore()) 5611 OS << " <trunc " << ST->getMemoryVT().getMVTString() << ">"; 5612 5613 const char *AM = getIndexedModeName(ST->getAddressingMode()); 5614 if (*AM) 5615 OS << " " << AM; 5616 if (ST->isVolatile()) 5617 OS << " <volatile>"; 5618 OS << " alignment=" << ST->getAlignment(); 5619 } else if (const AtomicSDNode* AT = dyn_cast<AtomicSDNode>(this)) { 5620 const Value *SrcValue = AT->getSrcValue(); 5621 int SrcOffset = AT->getSrcValueOffset(); 5622 OS << " <"; 5623 if (SrcValue) 5624 OS << SrcValue; 5625 else 5626 OS << "null"; 5627 OS << ":" << SrcOffset << ">"; 5628 if (AT->isVolatile()) 5629 OS << " <volatile>"; 5630 OS << " alignment=" << AT->getAlignment(); 5631 } 5632} 5633 5634void SDNode::print(raw_ostream &OS, const SelectionDAG *G) const { 5635 print_types(OS, G); 5636 OS << " "; 5637 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 5638 if (i) OS << ", "; 5639 OS << (void*)getOperand(i).getNode(); 5640 if (unsigned RN = getOperand(i).getResNo()) 5641 OS << ":" << RN; 5642 } 5643 print_details(OS, G); 5644} 5645 5646static void DumpNodes(const SDNode *N, unsigned indent, const SelectionDAG *G) { 5647 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 5648 if (N->getOperand(i).getNode()->hasOneUse()) 5649 DumpNodes(N->getOperand(i).getNode(), indent+2, G); 5650 else 5651 cerr << "\n" << std::string(indent+2, ' ') 5652 << (void*)N->getOperand(i).getNode() << ": <multiple use>"; 5653 5654 5655 cerr << "\n" << std::string(indent, ' '); 5656 N->dump(G); 5657} 5658 5659void SelectionDAG::dump() const { 5660 cerr << "SelectionDAG has " << AllNodes.size() << " nodes:"; 5661 5662 for (allnodes_const_iterator I = allnodes_begin(), E = allnodes_end(); 5663 I != E; ++I) { 5664 const SDNode *N = I; 5665 if (!N->hasOneUse() && N != getRoot().getNode()) 5666 DumpNodes(N, 2, this); 5667 } 5668 5669 if (getRoot().getNode()) DumpNodes(getRoot().getNode(), 2, this); 5670 5671 cerr << "\n\n"; 5672} 5673 5674void SDNode::printr(raw_ostream &OS, const SelectionDAG *G) const { 5675 print_types(OS, G); 5676 print_details(OS, G); 5677} 5678 5679typedef SmallPtrSet<const SDNode *, 128> VisitedSDNodeSet; 5680static void DumpNodesr(raw_ostream &OS, const SDNode *N, unsigned indent, 5681 const SelectionDAG *G, VisitedSDNodeSet &once) { 5682 if (!once.insert(N)) // If we've been here before, return now. 5683 return; 5684 // Dump the current SDNode, but don't end the line yet. 5685 OS << std::string(indent, ' '); 5686 N->printr(OS, G); 5687 // Having printed this SDNode, walk the children: 5688 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 5689 const SDNode *child = N->getOperand(i).getNode(); 5690 if (i) OS << ","; 5691 OS << " "; 5692 if (child->getNumOperands() == 0) { 5693 // This child has no grandchildren; print it inline right here. 5694 child->printr(OS, G); 5695 once.insert(child); 5696 } else { // Just the address. FIXME: also print the child's opcode 5697 OS << (void*)child; 5698 if (unsigned RN = N->getOperand(i).getResNo()) 5699 OS << ":" << RN; 5700 } 5701 } 5702 OS << "\n"; 5703 // Dump children that have grandchildren on their own line(s). 5704 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 5705 const SDNode *child = N->getOperand(i).getNode(); 5706 DumpNodesr(OS, child, indent+2, G, once); 5707 } 5708} 5709 5710void SDNode::dumpr() const { 5711 VisitedSDNodeSet once; 5712 DumpNodesr(errs(), this, 0, 0, once); 5713} 5714 5715 5716// getAddressSpace - Return the address space this GlobalAddress belongs to. 5717unsigned GlobalAddressSDNode::getAddressSpace() const { 5718 return getGlobal()->getType()->getAddressSpace(); 5719} 5720 5721 5722const Type *ConstantPoolSDNode::getType() const { 5723 if (isMachineConstantPoolEntry()) 5724 return Val.MachineCPVal->getType(); 5725 return Val.ConstVal->getType(); 5726} 5727 5728bool BuildVectorSDNode::isConstantSplat(APInt &SplatValue, 5729 APInt &SplatUndef, 5730 unsigned &SplatBitSize, 5731 bool &HasAnyUndefs, 5732 unsigned MinSplatBits) { 5733 MVT VT = getValueType(0); 5734 assert(VT.isVector() && "Expected a vector type"); 5735 unsigned sz = VT.getSizeInBits(); 5736 if (MinSplatBits > sz) 5737 return false; 5738 5739 SplatValue = APInt(sz, 0); 5740 SplatUndef = APInt(sz, 0); 5741 5742 // Get the bits. Bits with undefined values (when the corresponding element 5743 // of the vector is an ISD::UNDEF value) are set in SplatUndef and cleared 5744 // in SplatValue. If any of the values are not constant, give up and return 5745 // false. 5746 unsigned int nOps = getNumOperands(); 5747 assert(nOps > 0 && "isConstantSplat has 0-size build vector"); 5748 unsigned EltBitSize = VT.getVectorElementType().getSizeInBits(); 5749 for (unsigned i = 0; i < nOps; ++i) { 5750 SDValue OpVal = getOperand(i); 5751 unsigned BitPos = i * EltBitSize; 5752 5753 if (OpVal.getOpcode() == ISD::UNDEF) 5754 SplatUndef |= APInt::getBitsSet(sz, BitPos, BitPos +EltBitSize); 5755 else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) 5756 SplatValue |= (APInt(CN->getAPIntValue()).zextOrTrunc(EltBitSize). 5757 zextOrTrunc(sz) << BitPos); 5758 else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) 5759 SplatValue |= CN->getValueAPF().bitcastToAPInt().zextOrTrunc(sz) <<BitPos; 5760 else 5761 return false; 5762 } 5763 5764 // The build_vector is all constants or undefs. Find the smallest element 5765 // size that splats the vector. 5766 5767 HasAnyUndefs = (SplatUndef != 0); 5768 while (sz > 8) { 5769 5770 unsigned HalfSize = sz / 2; 5771 APInt HighValue = APInt(SplatValue).lshr(HalfSize).trunc(HalfSize); 5772 APInt LowValue = APInt(SplatValue).trunc(HalfSize); 5773 APInt HighUndef = APInt(SplatUndef).lshr(HalfSize).trunc(HalfSize); 5774 APInt LowUndef = APInt(SplatUndef).trunc(HalfSize); 5775 5776 // If the two halves do not match (ignoring undef bits), stop here. 5777 if ((HighValue & ~LowUndef) != (LowValue & ~HighUndef) || 5778 MinSplatBits > HalfSize) 5779 break; 5780 5781 SplatValue = HighValue | LowValue; 5782 SplatUndef = HighUndef & LowUndef; 5783 5784 sz = HalfSize; 5785 } 5786 5787 SplatBitSize = sz; 5788 return true; 5789} 5790 5791bool ShuffleVectorSDNode::isSplatMask(const int *Mask, MVT VT) { 5792 // Find the first non-undef value in the shuffle mask. 5793 unsigned i, e; 5794 for (i = 0, e = VT.getVectorNumElements(); i != e && Mask[i] < 0; ++i) 5795 /* search */; 5796 5797 assert(i != e && "VECTOR_SHUFFLE node with all undef indices!"); 5798 5799 // Make sure all remaining elements are either undef or the same as the first 5800 // non-undef value. 5801 for (int Idx = Mask[i]; i != e; ++i) 5802 if (Mask[i] >= 0 && Mask[i] != Idx) 5803 return false; 5804 return true; 5805} 5806