SelectionDAG.cpp revision 2f91f30b932ad56cd82398d872d4874facf84220
1//===-- SelectionDAG.cpp - Implement the SelectionDAG data structures -----===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAG class. 11// 12//===----------------------------------------------------------------------===// 13#include "llvm/CodeGen/SelectionDAG.h" 14#include "llvm/Constants.h" 15#include "llvm/Analysis/ValueTracking.h" 16#include "llvm/GlobalAlias.h" 17#include "llvm/GlobalVariable.h" 18#include "llvm/Intrinsics.h" 19#include "llvm/DerivedTypes.h" 20#include "llvm/Assembly/Writer.h" 21#include "llvm/CallingConv.h" 22#include "llvm/CodeGen/MachineBasicBlock.h" 23#include "llvm/CodeGen/MachineConstantPool.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/MachineModuleInfo.h" 26#include "llvm/CodeGen/PseudoSourceValue.h" 27#include "llvm/Target/TargetRegisterInfo.h" 28#include "llvm/Target/TargetData.h" 29#include "llvm/Target/TargetLowering.h" 30#include "llvm/Target/TargetOptions.h" 31#include "llvm/Target/TargetInstrInfo.h" 32#include "llvm/Target/TargetMachine.h" 33#include "llvm/Support/CommandLine.h" 34#include "llvm/Support/MathExtras.h" 35#include "llvm/Support/raw_ostream.h" 36#include "llvm/ADT/SetVector.h" 37#include "llvm/ADT/SmallPtrSet.h" 38#include "llvm/ADT/SmallSet.h" 39#include "llvm/ADT/SmallVector.h" 40#include "llvm/ADT/StringExtras.h" 41#include <algorithm> 42#include <cmath> 43using namespace llvm; 44 45/// makeVTList - Return an instance of the SDVTList struct initialized with the 46/// specified members. 47static SDVTList makeVTList(const MVT *VTs, unsigned NumVTs) { 48 SDVTList Res = {VTs, NumVTs}; 49 return Res; 50} 51 52static const fltSemantics *MVTToAPFloatSemantics(MVT VT) { 53 switch (VT.getSimpleVT()) { 54 default: assert(0 && "Unknown FP format"); 55 case MVT::f32: return &APFloat::IEEEsingle; 56 case MVT::f64: return &APFloat::IEEEdouble; 57 case MVT::f80: return &APFloat::x87DoubleExtended; 58 case MVT::f128: return &APFloat::IEEEquad; 59 case MVT::ppcf128: return &APFloat::PPCDoubleDouble; 60 } 61} 62 63SelectionDAG::DAGUpdateListener::~DAGUpdateListener() {} 64 65//===----------------------------------------------------------------------===// 66// ConstantFPSDNode Class 67//===----------------------------------------------------------------------===// 68 69/// isExactlyValue - We don't rely on operator== working on double values, as 70/// it returns true for things that are clearly not equal, like -0.0 and 0.0. 71/// As such, this method can be used to do an exact bit-for-bit comparison of 72/// two floating point values. 73bool ConstantFPSDNode::isExactlyValue(const APFloat& V) const { 74 return getValueAPF().bitwiseIsEqual(V); 75} 76 77bool ConstantFPSDNode::isValueValidForType(MVT VT, 78 const APFloat& Val) { 79 assert(VT.isFloatingPoint() && "Can only convert between FP types"); 80 81 // PPC long double cannot be converted to any other type. 82 if (VT == MVT::ppcf128 || 83 &Val.getSemantics() == &APFloat::PPCDoubleDouble) 84 return false; 85 86 // convert modifies in place, so make a copy. 87 APFloat Val2 = APFloat(Val); 88 bool losesInfo; 89 (void) Val2.convert(*MVTToAPFloatSemantics(VT), APFloat::rmNearestTiesToEven, 90 &losesInfo); 91 return !losesInfo; 92} 93 94//===----------------------------------------------------------------------===// 95// ISD Namespace 96//===----------------------------------------------------------------------===// 97 98/// isBuildVectorAllOnes - Return true if the specified node is a 99/// BUILD_VECTOR where all of the elements are ~0 or undef. 100bool ISD::isBuildVectorAllOnes(const SDNode *N) { 101 // Look through a bit convert. 102 if (N->getOpcode() == ISD::BIT_CONVERT) 103 N = N->getOperand(0).getNode(); 104 105 if (N->getOpcode() != ISD::BUILD_VECTOR) return false; 106 107 unsigned i = 0, e = N->getNumOperands(); 108 109 // Skip over all of the undef values. 110 while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF) 111 ++i; 112 113 // Do not accept an all-undef vector. 114 if (i == e) return false; 115 116 // Do not accept build_vectors that aren't all constants or which have non-~0 117 // elements. 118 SDValue NotZero = N->getOperand(i); 119 if (isa<ConstantSDNode>(NotZero)) { 120 if (!cast<ConstantSDNode>(NotZero)->isAllOnesValue()) 121 return false; 122 } else if (isa<ConstantFPSDNode>(NotZero)) { 123 if (!cast<ConstantFPSDNode>(NotZero)->getValueAPF(). 124 bitcastToAPInt().isAllOnesValue()) 125 return false; 126 } else 127 return false; 128 129 // Okay, we have at least one ~0 value, check to see if the rest match or are 130 // undefs. 131 for (++i; i != e; ++i) 132 if (N->getOperand(i) != NotZero && 133 N->getOperand(i).getOpcode() != ISD::UNDEF) 134 return false; 135 return true; 136} 137 138 139/// isBuildVectorAllZeros - Return true if the specified node is a 140/// BUILD_VECTOR where all of the elements are 0 or undef. 141bool ISD::isBuildVectorAllZeros(const SDNode *N) { 142 // Look through a bit convert. 143 if (N->getOpcode() == ISD::BIT_CONVERT) 144 N = N->getOperand(0).getNode(); 145 146 if (N->getOpcode() != ISD::BUILD_VECTOR) return false; 147 148 unsigned i = 0, e = N->getNumOperands(); 149 150 // Skip over all of the undef values. 151 while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF) 152 ++i; 153 154 // Do not accept an all-undef vector. 155 if (i == e) return false; 156 157 // Do not accept build_vectors that aren't all constants or which have non-~0 158 // elements. 159 SDValue Zero = N->getOperand(i); 160 if (isa<ConstantSDNode>(Zero)) { 161 if (!cast<ConstantSDNode>(Zero)->isNullValue()) 162 return false; 163 } else if (isa<ConstantFPSDNode>(Zero)) { 164 if (!cast<ConstantFPSDNode>(Zero)->getValueAPF().isPosZero()) 165 return false; 166 } else 167 return false; 168 169 // Okay, we have at least one ~0 value, check to see if the rest match or are 170 // undefs. 171 for (++i; i != e; ++i) 172 if (N->getOperand(i) != Zero && 173 N->getOperand(i).getOpcode() != ISD::UNDEF) 174 return false; 175 return true; 176} 177 178/// isScalarToVector - Return true if the specified node is a 179/// ISD::SCALAR_TO_VECTOR node or a BUILD_VECTOR node where only the low 180/// element is not an undef. 181bool ISD::isScalarToVector(const SDNode *N) { 182 if (N->getOpcode() == ISD::SCALAR_TO_VECTOR) 183 return true; 184 185 if (N->getOpcode() != ISD::BUILD_VECTOR) 186 return false; 187 if (N->getOperand(0).getOpcode() == ISD::UNDEF) 188 return false; 189 unsigned NumElems = N->getNumOperands(); 190 for (unsigned i = 1; i < NumElems; ++i) { 191 SDValue V = N->getOperand(i); 192 if (V.getOpcode() != ISD::UNDEF) 193 return false; 194 } 195 return true; 196} 197 198 199/// isDebugLabel - Return true if the specified node represents a debug 200/// label (i.e. ISD::DBG_LABEL or TargetInstrInfo::DBG_LABEL node). 201bool ISD::isDebugLabel(const SDNode *N) { 202 SDValue Zero; 203 if (N->getOpcode() == ISD::DBG_LABEL) 204 return true; 205 if (N->isMachineOpcode() && 206 N->getMachineOpcode() == TargetInstrInfo::DBG_LABEL) 207 return true; 208 return false; 209} 210 211/// getSetCCSwappedOperands - Return the operation corresponding to (Y op X) 212/// when given the operation for (X op Y). 213ISD::CondCode ISD::getSetCCSwappedOperands(ISD::CondCode Operation) { 214 // To perform this operation, we just need to swap the L and G bits of the 215 // operation. 216 unsigned OldL = (Operation >> 2) & 1; 217 unsigned OldG = (Operation >> 1) & 1; 218 return ISD::CondCode((Operation & ~6) | // Keep the N, U, E bits 219 (OldL << 1) | // New G bit 220 (OldG << 2)); // New L bit. 221} 222 223/// getSetCCInverse - Return the operation corresponding to !(X op Y), where 224/// 'op' is a valid SetCC operation. 225ISD::CondCode ISD::getSetCCInverse(ISD::CondCode Op, bool isInteger) { 226 unsigned Operation = Op; 227 if (isInteger) 228 Operation ^= 7; // Flip L, G, E bits, but not U. 229 else 230 Operation ^= 15; // Flip all of the condition bits. 231 232 if (Operation > ISD::SETTRUE2) 233 Operation &= ~8; // Don't let N and U bits get set. 234 235 return ISD::CondCode(Operation); 236} 237 238 239/// isSignedOp - For an integer comparison, return 1 if the comparison is a 240/// signed operation and 2 if the result is an unsigned comparison. Return zero 241/// if the operation does not depend on the sign of the input (setne and seteq). 242static int isSignedOp(ISD::CondCode Opcode) { 243 switch (Opcode) { 244 default: assert(0 && "Illegal integer setcc operation!"); 245 case ISD::SETEQ: 246 case ISD::SETNE: return 0; 247 case ISD::SETLT: 248 case ISD::SETLE: 249 case ISD::SETGT: 250 case ISD::SETGE: return 1; 251 case ISD::SETULT: 252 case ISD::SETULE: 253 case ISD::SETUGT: 254 case ISD::SETUGE: return 2; 255 } 256} 257 258/// getSetCCOrOperation - Return the result of a logical OR between different 259/// comparisons of identical values: ((X op1 Y) | (X op2 Y)). This function 260/// returns SETCC_INVALID if it is not possible to represent the resultant 261/// comparison. 262ISD::CondCode ISD::getSetCCOrOperation(ISD::CondCode Op1, ISD::CondCode Op2, 263 bool isInteger) { 264 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 265 // Cannot fold a signed integer setcc with an unsigned integer setcc. 266 return ISD::SETCC_INVALID; 267 268 unsigned Op = Op1 | Op2; // Combine all of the condition bits. 269 270 // If the N and U bits get set then the resultant comparison DOES suddenly 271 // care about orderedness, and is true when ordered. 272 if (Op > ISD::SETTRUE2) 273 Op &= ~16; // Clear the U bit if the N bit is set. 274 275 // Canonicalize illegal integer setcc's. 276 if (isInteger && Op == ISD::SETUNE) // e.g. SETUGT | SETULT 277 Op = ISD::SETNE; 278 279 return ISD::CondCode(Op); 280} 281 282/// getSetCCAndOperation - Return the result of a logical AND between different 283/// comparisons of identical values: ((X op1 Y) & (X op2 Y)). This 284/// function returns zero if it is not possible to represent the resultant 285/// comparison. 286ISD::CondCode ISD::getSetCCAndOperation(ISD::CondCode Op1, ISD::CondCode Op2, 287 bool isInteger) { 288 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 289 // Cannot fold a signed setcc with an unsigned setcc. 290 return ISD::SETCC_INVALID; 291 292 // Combine all of the condition bits. 293 ISD::CondCode Result = ISD::CondCode(Op1 & Op2); 294 295 // Canonicalize illegal integer setcc's. 296 if (isInteger) { 297 switch (Result) { 298 default: break; 299 case ISD::SETUO : Result = ISD::SETFALSE; break; // SETUGT & SETULT 300 case ISD::SETOEQ: // SETEQ & SETU[LG]E 301 case ISD::SETUEQ: Result = ISD::SETEQ ; break; // SETUGE & SETULE 302 case ISD::SETOLT: Result = ISD::SETULT ; break; // SETULT & SETNE 303 case ISD::SETOGT: Result = ISD::SETUGT ; break; // SETUGT & SETNE 304 } 305 } 306 307 return Result; 308} 309 310const TargetMachine &SelectionDAG::getTarget() const { 311 return MF->getTarget(); 312} 313 314//===----------------------------------------------------------------------===// 315// SDNode Profile Support 316//===----------------------------------------------------------------------===// 317 318/// AddNodeIDOpcode - Add the node opcode to the NodeID data. 319/// 320static void AddNodeIDOpcode(FoldingSetNodeID &ID, unsigned OpC) { 321 ID.AddInteger(OpC); 322} 323 324/// AddNodeIDValueTypes - Value type lists are intern'd so we can represent them 325/// solely with their pointer. 326static void AddNodeIDValueTypes(FoldingSetNodeID &ID, SDVTList VTList) { 327 ID.AddPointer(VTList.VTs); 328} 329 330/// AddNodeIDOperands - Various routines for adding operands to the NodeID data. 331/// 332static void AddNodeIDOperands(FoldingSetNodeID &ID, 333 const SDValue *Ops, unsigned NumOps) { 334 for (; NumOps; --NumOps, ++Ops) { 335 ID.AddPointer(Ops->getNode()); 336 ID.AddInteger(Ops->getResNo()); 337 } 338} 339 340/// AddNodeIDOperands - Various routines for adding operands to the NodeID data. 341/// 342static void AddNodeIDOperands(FoldingSetNodeID &ID, 343 const SDUse *Ops, unsigned NumOps) { 344 for (; NumOps; --NumOps, ++Ops) { 345 ID.AddPointer(Ops->getNode()); 346 ID.AddInteger(Ops->getResNo()); 347 } 348} 349 350static void AddNodeIDNode(FoldingSetNodeID &ID, 351 unsigned short OpC, SDVTList VTList, 352 const SDValue *OpList, unsigned N) { 353 AddNodeIDOpcode(ID, OpC); 354 AddNodeIDValueTypes(ID, VTList); 355 AddNodeIDOperands(ID, OpList, N); 356} 357 358/// AddNodeIDCustom - If this is an SDNode with special info, add this info to 359/// the NodeID data. 360static void AddNodeIDCustom(FoldingSetNodeID &ID, const SDNode *N) { 361 switch (N->getOpcode()) { 362 default: break; // Normal nodes don't need extra info. 363 case ISD::ARG_FLAGS: 364 ID.AddInteger(cast<ARG_FLAGSSDNode>(N)->getArgFlags().getRawBits()); 365 break; 366 case ISD::TargetConstant: 367 case ISD::Constant: 368 ID.AddPointer(cast<ConstantSDNode>(N)->getConstantIntValue()); 369 break; 370 case ISD::TargetConstantFP: 371 case ISD::ConstantFP: { 372 ID.AddPointer(cast<ConstantFPSDNode>(N)->getConstantFPValue()); 373 break; 374 } 375 case ISD::TargetGlobalAddress: 376 case ISD::GlobalAddress: 377 case ISD::TargetGlobalTLSAddress: 378 case ISD::GlobalTLSAddress: { 379 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(N); 380 ID.AddPointer(GA->getGlobal()); 381 ID.AddInteger(GA->getOffset()); 382 break; 383 } 384 case ISD::BasicBlock: 385 ID.AddPointer(cast<BasicBlockSDNode>(N)->getBasicBlock()); 386 break; 387 case ISD::Register: 388 ID.AddInteger(cast<RegisterSDNode>(N)->getReg()); 389 break; 390 case ISD::DBG_STOPPOINT: { 391 const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(N); 392 ID.AddInteger(DSP->getLine()); 393 ID.AddInteger(DSP->getColumn()); 394 ID.AddPointer(DSP->getCompileUnit()); 395 break; 396 } 397 case ISD::SRCVALUE: 398 ID.AddPointer(cast<SrcValueSDNode>(N)->getValue()); 399 break; 400 case ISD::MEMOPERAND: { 401 const MachineMemOperand &MO = cast<MemOperandSDNode>(N)->MO; 402 MO.Profile(ID); 403 break; 404 } 405 case ISD::FrameIndex: 406 case ISD::TargetFrameIndex: 407 ID.AddInteger(cast<FrameIndexSDNode>(N)->getIndex()); 408 break; 409 case ISD::JumpTable: 410 case ISD::TargetJumpTable: 411 ID.AddInteger(cast<JumpTableSDNode>(N)->getIndex()); 412 break; 413 case ISD::ConstantPool: 414 case ISD::TargetConstantPool: { 415 const ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(N); 416 ID.AddInteger(CP->getAlignment()); 417 ID.AddInteger(CP->getOffset()); 418 if (CP->isMachineConstantPoolEntry()) 419 CP->getMachineCPVal()->AddSelectionDAGCSEId(ID); 420 else 421 ID.AddPointer(CP->getConstVal()); 422 break; 423 } 424 case ISD::CALL: { 425 const CallSDNode *Call = cast<CallSDNode>(N); 426 ID.AddInteger(Call->getCallingConv()); 427 ID.AddInteger(Call->isVarArg()); 428 break; 429 } 430 case ISD::LOAD: { 431 const LoadSDNode *LD = cast<LoadSDNode>(N); 432 ID.AddInteger(LD->getMemoryVT().getRawBits()); 433 ID.AddInteger(LD->getRawSubclassData()); 434 break; 435 } 436 case ISD::STORE: { 437 const StoreSDNode *ST = cast<StoreSDNode>(N); 438 ID.AddInteger(ST->getMemoryVT().getRawBits()); 439 ID.AddInteger(ST->getRawSubclassData()); 440 break; 441 } 442 case ISD::ATOMIC_CMP_SWAP: 443 case ISD::ATOMIC_SWAP: 444 case ISD::ATOMIC_LOAD_ADD: 445 case ISD::ATOMIC_LOAD_SUB: 446 case ISD::ATOMIC_LOAD_AND: 447 case ISD::ATOMIC_LOAD_OR: 448 case ISD::ATOMIC_LOAD_XOR: 449 case ISD::ATOMIC_LOAD_NAND: 450 case ISD::ATOMIC_LOAD_MIN: 451 case ISD::ATOMIC_LOAD_MAX: 452 case ISD::ATOMIC_LOAD_UMIN: 453 case ISD::ATOMIC_LOAD_UMAX: { 454 const AtomicSDNode *AT = cast<AtomicSDNode>(N); 455 ID.AddInteger(AT->getMemoryVT().getRawBits()); 456 ID.AddInteger(AT->getRawSubclassData()); 457 break; 458 } 459 } // end switch (N->getOpcode()) 460} 461 462/// AddNodeIDNode - Generic routine for adding a nodes info to the NodeID 463/// data. 464static void AddNodeIDNode(FoldingSetNodeID &ID, const SDNode *N) { 465 AddNodeIDOpcode(ID, N->getOpcode()); 466 // Add the return value info. 467 AddNodeIDValueTypes(ID, N->getVTList()); 468 // Add the operand info. 469 AddNodeIDOperands(ID, N->op_begin(), N->getNumOperands()); 470 471 // Handle SDNode leafs with special info. 472 AddNodeIDCustom(ID, N); 473} 474 475/// encodeMemSDNodeFlags - Generic routine for computing a value for use in 476/// the CSE map that carries alignment, volatility, indexing mode, and 477/// extension/truncation information. 478/// 479static inline unsigned 480encodeMemSDNodeFlags(int ConvType, ISD::MemIndexedMode AM, 481 bool isVolatile, unsigned Alignment) { 482 assert((ConvType & 3) == ConvType && 483 "ConvType may not require more than 2 bits!"); 484 assert((AM & 7) == AM && 485 "AM may not require more than 3 bits!"); 486 return ConvType | 487 (AM << 2) | 488 (isVolatile << 5) | 489 ((Log2_32(Alignment) + 1) << 6); 490} 491 492//===----------------------------------------------------------------------===// 493// SelectionDAG Class 494//===----------------------------------------------------------------------===// 495 496/// doNotCSE - Return true if CSE should not be performed for this node. 497static bool doNotCSE(SDNode *N) { 498 if (N->getValueType(0) == MVT::Flag) 499 return true; // Never CSE anything that produces a flag. 500 501 switch (N->getOpcode()) { 502 default: break; 503 case ISD::HANDLENODE: 504 case ISD::DBG_LABEL: 505 case ISD::DBG_STOPPOINT: 506 case ISD::EH_LABEL: 507 case ISD::DECLARE: 508 return true; // Never CSE these nodes. 509 } 510 511 // Check that remaining values produced are not flags. 512 for (unsigned i = 1, e = N->getNumValues(); i != e; ++i) 513 if (N->getValueType(i) == MVT::Flag) 514 return true; // Never CSE anything that produces a flag. 515 516 return false; 517} 518 519/// RemoveDeadNodes - This method deletes all unreachable nodes in the 520/// SelectionDAG. 521void SelectionDAG::RemoveDeadNodes() { 522 // Create a dummy node (which is not added to allnodes), that adds a reference 523 // to the root node, preventing it from being deleted. 524 HandleSDNode Dummy(getRoot()); 525 526 SmallVector<SDNode*, 128> DeadNodes; 527 528 // Add all obviously-dead nodes to the DeadNodes worklist. 529 for (allnodes_iterator I = allnodes_begin(), E = allnodes_end(); I != E; ++I) 530 if (I->use_empty()) 531 DeadNodes.push_back(I); 532 533 RemoveDeadNodes(DeadNodes); 534 535 // If the root changed (e.g. it was a dead load, update the root). 536 setRoot(Dummy.getValue()); 537} 538 539/// RemoveDeadNodes - This method deletes the unreachable nodes in the 540/// given list, and any nodes that become unreachable as a result. 541void SelectionDAG::RemoveDeadNodes(SmallVectorImpl<SDNode *> &DeadNodes, 542 DAGUpdateListener *UpdateListener) { 543 544 // Process the worklist, deleting the nodes and adding their uses to the 545 // worklist. 546 while (!DeadNodes.empty()) { 547 SDNode *N = DeadNodes.pop_back_val(); 548 549 if (UpdateListener) 550 UpdateListener->NodeDeleted(N, 0); 551 552 // Take the node out of the appropriate CSE map. 553 RemoveNodeFromCSEMaps(N); 554 555 // Next, brutally remove the operand list. This is safe to do, as there are 556 // no cycles in the graph. 557 for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ) { 558 SDUse &Use = *I++; 559 SDNode *Operand = Use.getNode(); 560 Use.set(SDValue()); 561 562 // Now that we removed this operand, see if there are no uses of it left. 563 if (Operand->use_empty()) 564 DeadNodes.push_back(Operand); 565 } 566 567 DeallocateNode(N); 568 } 569} 570 571void SelectionDAG::RemoveDeadNode(SDNode *N, DAGUpdateListener *UpdateListener){ 572 SmallVector<SDNode*, 16> DeadNodes(1, N); 573 RemoveDeadNodes(DeadNodes, UpdateListener); 574} 575 576void SelectionDAG::DeleteNode(SDNode *N) { 577 // First take this out of the appropriate CSE map. 578 RemoveNodeFromCSEMaps(N); 579 580 // Finally, remove uses due to operands of this node, remove from the 581 // AllNodes list, and delete the node. 582 DeleteNodeNotInCSEMaps(N); 583} 584 585void SelectionDAG::DeleteNodeNotInCSEMaps(SDNode *N) { 586 assert(N != AllNodes.begin() && "Cannot delete the entry node!"); 587 assert(N->use_empty() && "Cannot delete a node that is not dead!"); 588 589 // Drop all of the operands and decrement used node's use counts. 590 N->DropOperands(); 591 592 DeallocateNode(N); 593} 594 595void SelectionDAG::DeallocateNode(SDNode *N) { 596 if (N->OperandsNeedDelete) 597 delete[] N->OperandList; 598 599 // Set the opcode to DELETED_NODE to help catch bugs when node 600 // memory is reallocated. 601 N->NodeType = ISD::DELETED_NODE; 602 603 NodeAllocator.Deallocate(AllNodes.remove(N)); 604} 605 606/// RemoveNodeFromCSEMaps - Take the specified node out of the CSE map that 607/// correspond to it. This is useful when we're about to delete or repurpose 608/// the node. We don't want future request for structurally identical nodes 609/// to return N anymore. 610bool SelectionDAG::RemoveNodeFromCSEMaps(SDNode *N) { 611 bool Erased = false; 612 switch (N->getOpcode()) { 613 case ISD::EntryToken: 614 assert(0 && "EntryToken should not be in CSEMaps!"); 615 return false; 616 case ISD::HANDLENODE: return false; // noop. 617 case ISD::CONDCODE: 618 assert(CondCodeNodes[cast<CondCodeSDNode>(N)->get()] && 619 "Cond code doesn't exist!"); 620 Erased = CondCodeNodes[cast<CondCodeSDNode>(N)->get()] != 0; 621 CondCodeNodes[cast<CondCodeSDNode>(N)->get()] = 0; 622 break; 623 case ISD::ExternalSymbol: 624 Erased = ExternalSymbols.erase(cast<ExternalSymbolSDNode>(N)->getSymbol()); 625 break; 626 case ISD::TargetExternalSymbol: 627 Erased = 628 TargetExternalSymbols.erase(cast<ExternalSymbolSDNode>(N)->getSymbol()); 629 break; 630 case ISD::VALUETYPE: { 631 MVT VT = cast<VTSDNode>(N)->getVT(); 632 if (VT.isExtended()) { 633 Erased = ExtendedValueTypeNodes.erase(VT); 634 } else { 635 Erased = ValueTypeNodes[VT.getSimpleVT()] != 0; 636 ValueTypeNodes[VT.getSimpleVT()] = 0; 637 } 638 break; 639 } 640 default: 641 // Remove it from the CSE Map. 642 Erased = CSEMap.RemoveNode(N); 643 break; 644 } 645#ifndef NDEBUG 646 // Verify that the node was actually in one of the CSE maps, unless it has a 647 // flag result (which cannot be CSE'd) or is one of the special cases that are 648 // not subject to CSE. 649 if (!Erased && N->getValueType(N->getNumValues()-1) != MVT::Flag && 650 !N->isMachineOpcode() && !doNotCSE(N)) { 651 N->dump(this); 652 cerr << "\n"; 653 assert(0 && "Node is not in map!"); 654 } 655#endif 656 return Erased; 657} 658 659/// AddModifiedNodeToCSEMaps - The specified node has been removed from the CSE 660/// maps and modified in place. Add it back to the CSE maps, unless an identical 661/// node already exists, in which case transfer all its users to the existing 662/// node. This transfer can potentially trigger recursive merging. 663/// 664void 665SelectionDAG::AddModifiedNodeToCSEMaps(SDNode *N, 666 DAGUpdateListener *UpdateListener) { 667 // For node types that aren't CSE'd, just act as if no identical node 668 // already exists. 669 if (!doNotCSE(N)) { 670 SDNode *Existing = CSEMap.GetOrInsertNode(N); 671 if (Existing != N) { 672 // If there was already an existing matching node, use ReplaceAllUsesWith 673 // to replace the dead one with the existing one. This can cause 674 // recursive merging of other unrelated nodes down the line. 675 ReplaceAllUsesWith(N, Existing, UpdateListener); 676 677 // N is now dead. Inform the listener if it exists and delete it. 678 if (UpdateListener) 679 UpdateListener->NodeDeleted(N, Existing); 680 DeleteNodeNotInCSEMaps(N); 681 return; 682 } 683 } 684 685 // If the node doesn't already exist, we updated it. Inform a listener if 686 // it exists. 687 if (UpdateListener) 688 UpdateListener->NodeUpdated(N); 689} 690 691/// FindModifiedNodeSlot - Find a slot for the specified node if its operands 692/// were replaced with those specified. If this node is never memoized, 693/// return null, otherwise return a pointer to the slot it would take. If a 694/// node already exists with these operands, the slot will be non-null. 695SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, SDValue Op, 696 void *&InsertPos) { 697 if (doNotCSE(N)) 698 return 0; 699 700 SDValue Ops[] = { Op }; 701 FoldingSetNodeID ID; 702 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, 1); 703 AddNodeIDCustom(ID, N); 704 return CSEMap.FindNodeOrInsertPos(ID, InsertPos); 705} 706 707/// FindModifiedNodeSlot - Find a slot for the specified node if its operands 708/// were replaced with those specified. If this node is never memoized, 709/// return null, otherwise return a pointer to the slot it would take. If a 710/// node already exists with these operands, the slot will be non-null. 711SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, 712 SDValue Op1, SDValue Op2, 713 void *&InsertPos) { 714 if (doNotCSE(N)) 715 return 0; 716 717 SDValue Ops[] = { Op1, Op2 }; 718 FoldingSetNodeID ID; 719 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, 2); 720 AddNodeIDCustom(ID, N); 721 return CSEMap.FindNodeOrInsertPos(ID, InsertPos); 722} 723 724 725/// FindModifiedNodeSlot - Find a slot for the specified node if its operands 726/// were replaced with those specified. If this node is never memoized, 727/// return null, otherwise return a pointer to the slot it would take. If a 728/// node already exists with these operands, the slot will be non-null. 729SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, 730 const SDValue *Ops,unsigned NumOps, 731 void *&InsertPos) { 732 if (doNotCSE(N)) 733 return 0; 734 735 FoldingSetNodeID ID; 736 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, NumOps); 737 AddNodeIDCustom(ID, N); 738 return CSEMap.FindNodeOrInsertPos(ID, InsertPos); 739} 740 741/// VerifyNode - Sanity check the given node. Aborts if it is invalid. 742void SelectionDAG::VerifyNode(SDNode *N) { 743 switch (N->getOpcode()) { 744 default: 745 break; 746 case ISD::BUILD_PAIR: { 747 MVT VT = N->getValueType(0); 748 assert(N->getNumValues() == 1 && "Too many results!"); 749 assert(!VT.isVector() && (VT.isInteger() || VT.isFloatingPoint()) && 750 "Wrong return type!"); 751 assert(N->getNumOperands() == 2 && "Wrong number of operands!"); 752 assert(N->getOperand(0).getValueType() == N->getOperand(1).getValueType() && 753 "Mismatched operand types!"); 754 assert(N->getOperand(0).getValueType().isInteger() == VT.isInteger() && 755 "Wrong operand type!"); 756 assert(VT.getSizeInBits() == 2 * N->getOperand(0).getValueSizeInBits() && 757 "Wrong return type size"); 758 break; 759 } 760 case ISD::BUILD_VECTOR: { 761 assert(N->getNumValues() == 1 && "Too many results!"); 762 assert(N->getValueType(0).isVector() && "Wrong return type!"); 763 assert(N->getNumOperands() == N->getValueType(0).getVectorNumElements() && 764 "Wrong number of operands!"); 765 MVT EltVT = N->getValueType(0).getVectorElementType(); 766 for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ++I) 767 assert((I->getValueType() == EltVT || 768 (EltVT.isInteger() && I->getValueType().isInteger() && 769 EltVT.bitsLE(I->getValueType()))) && 770 "Wrong operand type!"); 771 break; 772 } 773 } 774} 775 776/// getMVTAlignment - Compute the default alignment value for the 777/// given type. 778/// 779unsigned SelectionDAG::getMVTAlignment(MVT VT) const { 780 const Type *Ty = VT == MVT::iPTR ? 781 PointerType::get(Type::Int8Ty, 0) : 782 VT.getTypeForMVT(); 783 784 return TLI.getTargetData()->getABITypeAlignment(Ty); 785} 786 787// EntryNode could meaningfully have debug info if we can find it... 788SelectionDAG::SelectionDAG(TargetLowering &tli, FunctionLoweringInfo &fli) 789 : TLI(tli), FLI(fli), DW(0), 790 EntryNode(ISD::EntryToken, DebugLoc::getUnknownLoc(), 791 getVTList(MVT::Other)), Root(getEntryNode()) { 792 AllNodes.push_back(&EntryNode); 793} 794 795void SelectionDAG::init(MachineFunction &mf, MachineModuleInfo *mmi, 796 DwarfWriter *dw) { 797 MF = &mf; 798 MMI = mmi; 799 DW = dw; 800} 801 802SelectionDAG::~SelectionDAG() { 803 allnodes_clear(); 804} 805 806void SelectionDAG::allnodes_clear() { 807 assert(&*AllNodes.begin() == &EntryNode); 808 AllNodes.remove(AllNodes.begin()); 809 while (!AllNodes.empty()) 810 DeallocateNode(AllNodes.begin()); 811} 812 813void SelectionDAG::clear() { 814 allnodes_clear(); 815 OperandAllocator.Reset(); 816 CSEMap.clear(); 817 818 ExtendedValueTypeNodes.clear(); 819 ExternalSymbols.clear(); 820 TargetExternalSymbols.clear(); 821 std::fill(CondCodeNodes.begin(), CondCodeNodes.end(), 822 static_cast<CondCodeSDNode*>(0)); 823 std::fill(ValueTypeNodes.begin(), ValueTypeNodes.end(), 824 static_cast<SDNode*>(0)); 825 826 EntryNode.UseList = 0; 827 AllNodes.push_back(&EntryNode); 828 Root = getEntryNode(); 829} 830 831SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, DebugLoc DL, MVT VT) { 832 if (Op.getValueType() == VT) return Op; 833 APInt Imm = APInt::getLowBitsSet(Op.getValueSizeInBits(), 834 VT.getSizeInBits()); 835 return getNode(ISD::AND, DL, Op.getValueType(), Op, 836 getConstant(Imm, Op.getValueType())); 837} 838 839/// getNOT - Create a bitwise NOT operation as (XOR Val, -1). 840/// 841SDValue SelectionDAG::getNOT(DebugLoc DL, SDValue Val, MVT VT) { 842 MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 843 SDValue NegOne = 844 getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT); 845 return getNode(ISD::XOR, DL, VT, Val, NegOne); 846} 847 848SDValue SelectionDAG::getConstant(uint64_t Val, MVT VT, bool isT) { 849 MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 850 assert((EltVT.getSizeInBits() >= 64 || 851 (uint64_t)((int64_t)Val >> EltVT.getSizeInBits()) + 1 < 2) && 852 "getConstant with a uint64_t value that doesn't fit in the type!"); 853 return getConstant(APInt(EltVT.getSizeInBits(), Val), VT, isT); 854} 855 856SDValue SelectionDAG::getConstant(const APInt &Val, MVT VT, bool isT) { 857 return getConstant(*ConstantInt::get(Val), VT, isT); 858} 859 860SDValue SelectionDAG::getConstant(const ConstantInt &Val, MVT VT, bool isT) { 861 assert(VT.isInteger() && "Cannot create FP integer constant!"); 862 863 MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 864 assert(Val.getBitWidth() == EltVT.getSizeInBits() && 865 "APInt size does not match type size!"); 866 867 unsigned Opc = isT ? ISD::TargetConstant : ISD::Constant; 868 FoldingSetNodeID ID; 869 AddNodeIDNode(ID, Opc, getVTList(EltVT), 0, 0); 870 ID.AddPointer(&Val); 871 void *IP = 0; 872 SDNode *N = NULL; 873 if ((N = CSEMap.FindNodeOrInsertPos(ID, IP))) 874 if (!VT.isVector()) 875 return SDValue(N, 0); 876 if (!N) { 877 N = NodeAllocator.Allocate<ConstantSDNode>(); 878 new (N) ConstantSDNode(isT, &Val, EltVT); 879 CSEMap.InsertNode(N, IP); 880 AllNodes.push_back(N); 881 } 882 883 SDValue Result(N, 0); 884 if (VT.isVector()) { 885 SmallVector<SDValue, 8> Ops; 886 Ops.assign(VT.getVectorNumElements(), Result); 887 Result = getNode(ISD::BUILD_VECTOR, DebugLoc::getUnknownLoc(), 888 VT, &Ops[0], Ops.size()); 889 } 890 return Result; 891} 892 893SDValue SelectionDAG::getIntPtrConstant(uint64_t Val, bool isTarget) { 894 return getConstant(Val, TLI.getPointerTy(), isTarget); 895} 896 897 898SDValue SelectionDAG::getConstantFP(const APFloat& V, MVT VT, bool isTarget) { 899 return getConstantFP(*ConstantFP::get(V), VT, isTarget); 900} 901 902SDValue SelectionDAG::getConstantFP(const ConstantFP& V, MVT VT, bool isTarget){ 903 assert(VT.isFloatingPoint() && "Cannot create integer FP constant!"); 904 905 MVT EltVT = 906 VT.isVector() ? VT.getVectorElementType() : VT; 907 908 // Do the map lookup using the actual bit pattern for the floating point 909 // value, so that we don't have problems with 0.0 comparing equal to -0.0, and 910 // we don't have issues with SNANs. 911 unsigned Opc = isTarget ? ISD::TargetConstantFP : ISD::ConstantFP; 912 FoldingSetNodeID ID; 913 AddNodeIDNode(ID, Opc, getVTList(EltVT), 0, 0); 914 ID.AddPointer(&V); 915 void *IP = 0; 916 SDNode *N = NULL; 917 if ((N = CSEMap.FindNodeOrInsertPos(ID, IP))) 918 if (!VT.isVector()) 919 return SDValue(N, 0); 920 if (!N) { 921 N = NodeAllocator.Allocate<ConstantFPSDNode>(); 922 new (N) ConstantFPSDNode(isTarget, &V, EltVT); 923 CSEMap.InsertNode(N, IP); 924 AllNodes.push_back(N); 925 } 926 927 SDValue Result(N, 0); 928 if (VT.isVector()) { 929 SmallVector<SDValue, 8> Ops; 930 Ops.assign(VT.getVectorNumElements(), Result); 931 // FIXME DebugLoc info might be appropriate here 932 Result = getNode(ISD::BUILD_VECTOR, DebugLoc::getUnknownLoc(), 933 VT, &Ops[0], Ops.size()); 934 } 935 return Result; 936} 937 938SDValue SelectionDAG::getConstantFP(double Val, MVT VT, bool isTarget) { 939 MVT EltVT = 940 VT.isVector() ? VT.getVectorElementType() : VT; 941 if (EltVT==MVT::f32) 942 return getConstantFP(APFloat((float)Val), VT, isTarget); 943 else 944 return getConstantFP(APFloat(Val), VT, isTarget); 945} 946 947SDValue SelectionDAG::getGlobalAddress(const GlobalValue *GV, 948 MVT VT, int64_t Offset, 949 bool isTargetGA) { 950 unsigned Opc; 951 952 // Truncate (with sign-extension) the offset value to the pointer size. 953 unsigned BitWidth = TLI.getPointerTy().getSizeInBits(); 954 if (BitWidth < 64) 955 Offset = (Offset << (64 - BitWidth) >> (64 - BitWidth)); 956 957 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV); 958 if (!GVar) { 959 // If GV is an alias then use the aliasee for determining thread-localness. 960 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) 961 GVar = dyn_cast_or_null<GlobalVariable>(GA->resolveAliasedGlobal(false)); 962 } 963 964 if (GVar && GVar->isThreadLocal()) 965 Opc = isTargetGA ? ISD::TargetGlobalTLSAddress : ISD::GlobalTLSAddress; 966 else 967 Opc = isTargetGA ? ISD::TargetGlobalAddress : ISD::GlobalAddress; 968 969 FoldingSetNodeID ID; 970 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 971 ID.AddPointer(GV); 972 ID.AddInteger(Offset); 973 void *IP = 0; 974 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 975 return SDValue(E, 0); 976 SDNode *N = NodeAllocator.Allocate<GlobalAddressSDNode>(); 977 new (N) GlobalAddressSDNode(isTargetGA, GV, VT, Offset); 978 CSEMap.InsertNode(N, IP); 979 AllNodes.push_back(N); 980 return SDValue(N, 0); 981} 982 983SDValue SelectionDAG::getFrameIndex(int FI, MVT VT, bool isTarget) { 984 unsigned Opc = isTarget ? ISD::TargetFrameIndex : ISD::FrameIndex; 985 FoldingSetNodeID ID; 986 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 987 ID.AddInteger(FI); 988 void *IP = 0; 989 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 990 return SDValue(E, 0); 991 SDNode *N = NodeAllocator.Allocate<FrameIndexSDNode>(); 992 new (N) FrameIndexSDNode(FI, VT, isTarget); 993 CSEMap.InsertNode(N, IP); 994 AllNodes.push_back(N); 995 return SDValue(N, 0); 996} 997 998SDValue SelectionDAG::getJumpTable(int JTI, MVT VT, bool isTarget){ 999 unsigned Opc = isTarget ? ISD::TargetJumpTable : ISD::JumpTable; 1000 FoldingSetNodeID ID; 1001 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 1002 ID.AddInteger(JTI); 1003 void *IP = 0; 1004 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1005 return SDValue(E, 0); 1006 SDNode *N = NodeAllocator.Allocate<JumpTableSDNode>(); 1007 new (N) JumpTableSDNode(JTI, VT, isTarget); 1008 CSEMap.InsertNode(N, IP); 1009 AllNodes.push_back(N); 1010 return SDValue(N, 0); 1011} 1012 1013SDValue SelectionDAG::getConstantPool(Constant *C, MVT VT, 1014 unsigned Alignment, int Offset, 1015 bool isTarget) { 1016 if (Alignment == 0) 1017 Alignment = TLI.getTargetData()->getPrefTypeAlignment(C->getType()); 1018 unsigned Opc = isTarget ? ISD::TargetConstantPool : ISD::ConstantPool; 1019 FoldingSetNodeID ID; 1020 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 1021 ID.AddInteger(Alignment); 1022 ID.AddInteger(Offset); 1023 ID.AddPointer(C); 1024 void *IP = 0; 1025 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1026 return SDValue(E, 0); 1027 SDNode *N = NodeAllocator.Allocate<ConstantPoolSDNode>(); 1028 new (N) ConstantPoolSDNode(isTarget, C, VT, Offset, Alignment); 1029 CSEMap.InsertNode(N, IP); 1030 AllNodes.push_back(N); 1031 return SDValue(N, 0); 1032} 1033 1034 1035SDValue SelectionDAG::getConstantPool(MachineConstantPoolValue *C, MVT VT, 1036 unsigned Alignment, int Offset, 1037 bool isTarget) { 1038 if (Alignment == 0) 1039 Alignment = TLI.getTargetData()->getPrefTypeAlignment(C->getType()); 1040 unsigned Opc = isTarget ? ISD::TargetConstantPool : ISD::ConstantPool; 1041 FoldingSetNodeID ID; 1042 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 1043 ID.AddInteger(Alignment); 1044 ID.AddInteger(Offset); 1045 C->AddSelectionDAGCSEId(ID); 1046 void *IP = 0; 1047 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1048 return SDValue(E, 0); 1049 SDNode *N = NodeAllocator.Allocate<ConstantPoolSDNode>(); 1050 new (N) ConstantPoolSDNode(isTarget, C, VT, Offset, Alignment); 1051 CSEMap.InsertNode(N, IP); 1052 AllNodes.push_back(N); 1053 return SDValue(N, 0); 1054} 1055 1056SDValue SelectionDAG::getBasicBlock(MachineBasicBlock *MBB) { 1057 FoldingSetNodeID ID; 1058 AddNodeIDNode(ID, ISD::BasicBlock, getVTList(MVT::Other), 0, 0); 1059 ID.AddPointer(MBB); 1060 void *IP = 0; 1061 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1062 return SDValue(E, 0); 1063 SDNode *N = NodeAllocator.Allocate<BasicBlockSDNode>(); 1064 new (N) BasicBlockSDNode(MBB); 1065 CSEMap.InsertNode(N, IP); 1066 AllNodes.push_back(N); 1067 return SDValue(N, 0); 1068} 1069 1070SDValue SelectionDAG::getArgFlags(ISD::ArgFlagsTy Flags) { 1071 FoldingSetNodeID ID; 1072 AddNodeIDNode(ID, ISD::ARG_FLAGS, getVTList(MVT::Other), 0, 0); 1073 ID.AddInteger(Flags.getRawBits()); 1074 void *IP = 0; 1075 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1076 return SDValue(E, 0); 1077 SDNode *N = NodeAllocator.Allocate<ARG_FLAGSSDNode>(); 1078 new (N) ARG_FLAGSSDNode(Flags); 1079 CSEMap.InsertNode(N, IP); 1080 AllNodes.push_back(N); 1081 return SDValue(N, 0); 1082} 1083 1084SDValue SelectionDAG::getValueType(MVT VT) { 1085 if (VT.isSimple() && (unsigned)VT.getSimpleVT() >= ValueTypeNodes.size()) 1086 ValueTypeNodes.resize(VT.getSimpleVT()+1); 1087 1088 SDNode *&N = VT.isExtended() ? 1089 ExtendedValueTypeNodes[VT] : ValueTypeNodes[VT.getSimpleVT()]; 1090 1091 if (N) return SDValue(N, 0); 1092 N = NodeAllocator.Allocate<VTSDNode>(); 1093 new (N) VTSDNode(VT); 1094 AllNodes.push_back(N); 1095 return SDValue(N, 0); 1096} 1097 1098SDValue SelectionDAG::getExternalSymbol(const char *Sym, MVT VT) { 1099 SDNode *&N = ExternalSymbols[Sym]; 1100 if (N) return SDValue(N, 0); 1101 N = NodeAllocator.Allocate<ExternalSymbolSDNode>(); 1102 new (N) ExternalSymbolSDNode(false, Sym, VT); 1103 AllNodes.push_back(N); 1104 return SDValue(N, 0); 1105} 1106 1107SDValue SelectionDAG::getTargetExternalSymbol(const char *Sym, MVT VT) { 1108 SDNode *&N = TargetExternalSymbols[Sym]; 1109 if (N) return SDValue(N, 0); 1110 N = NodeAllocator.Allocate<ExternalSymbolSDNode>(); 1111 new (N) ExternalSymbolSDNode(true, Sym, VT); 1112 AllNodes.push_back(N); 1113 return SDValue(N, 0); 1114} 1115 1116SDValue SelectionDAG::getCondCode(ISD::CondCode Cond) { 1117 if ((unsigned)Cond >= CondCodeNodes.size()) 1118 CondCodeNodes.resize(Cond+1); 1119 1120 if (CondCodeNodes[Cond] == 0) { 1121 CondCodeSDNode *N = NodeAllocator.Allocate<CondCodeSDNode>(); 1122 new (N) CondCodeSDNode(Cond); 1123 CondCodeNodes[Cond] = N; 1124 AllNodes.push_back(N); 1125 } 1126 return SDValue(CondCodeNodes[Cond], 0); 1127} 1128 1129SDValue SelectionDAG::getConvertRndSat(MVT VT, DebugLoc dl, 1130 SDValue Val, SDValue DTy, 1131 SDValue STy, SDValue Rnd, SDValue Sat, 1132 ISD::CvtCode Code) { 1133 // If the src and dest types are the same and the conversion is between 1134 // integer types of the same sign or two floats, no conversion is necessary. 1135 if (DTy == STy && 1136 (Code == ISD::CVT_UU || Code == ISD::CVT_SS || Code == ISD::CVT_FF)) 1137 return Val; 1138 1139 FoldingSetNodeID ID; 1140 void* IP = 0; 1141 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1142 return SDValue(E, 0); 1143 CvtRndSatSDNode *N = NodeAllocator.Allocate<CvtRndSatSDNode>(); 1144 SDValue Ops[] = { Val, DTy, STy, Rnd, Sat }; 1145 new (N) CvtRndSatSDNode(VT, dl, Ops, 5, Code); 1146 CSEMap.InsertNode(N, IP); 1147 AllNodes.push_back(N); 1148 return SDValue(N, 0); 1149} 1150 1151SDValue SelectionDAG::getRegister(unsigned RegNo, MVT VT) { 1152 FoldingSetNodeID ID; 1153 AddNodeIDNode(ID, ISD::Register, getVTList(VT), 0, 0); 1154 ID.AddInteger(RegNo); 1155 void *IP = 0; 1156 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1157 return SDValue(E, 0); 1158 SDNode *N = NodeAllocator.Allocate<RegisterSDNode>(); 1159 new (N) RegisterSDNode(RegNo, VT); 1160 CSEMap.InsertNode(N, IP); 1161 AllNodes.push_back(N); 1162 return SDValue(N, 0); 1163} 1164 1165SDValue SelectionDAG::getDbgStopPoint(SDValue Root, 1166 unsigned Line, unsigned Col, 1167 Value *CU) { 1168 SDNode *N = NodeAllocator.Allocate<DbgStopPointSDNode>(); 1169 new (N) DbgStopPointSDNode(Root, Line, Col, CU); 1170 AllNodes.push_back(N); 1171 return SDValue(N, 0); 1172} 1173 1174SDValue SelectionDAG::getLabel(unsigned Opcode, DebugLoc dl, 1175 SDValue Root, 1176 unsigned LabelID) { 1177 FoldingSetNodeID ID; 1178 SDValue Ops[] = { Root }; 1179 AddNodeIDNode(ID, Opcode, getVTList(MVT::Other), &Ops[0], 1); 1180 ID.AddInteger(LabelID); 1181 void *IP = 0; 1182 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1183 return SDValue(E, 0); 1184 SDNode *N = NodeAllocator.Allocate<LabelSDNode>(); 1185 new (N) LabelSDNode(Opcode, dl, Root, LabelID); 1186 CSEMap.InsertNode(N, IP); 1187 AllNodes.push_back(N); 1188 return SDValue(N, 0); 1189} 1190 1191SDValue SelectionDAG::getSrcValue(const Value *V) { 1192 assert((!V || isa<PointerType>(V->getType())) && 1193 "SrcValue is not a pointer?"); 1194 1195 FoldingSetNodeID ID; 1196 AddNodeIDNode(ID, ISD::SRCVALUE, getVTList(MVT::Other), 0, 0); 1197 ID.AddPointer(V); 1198 1199 void *IP = 0; 1200 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1201 return SDValue(E, 0); 1202 1203 SDNode *N = NodeAllocator.Allocate<SrcValueSDNode>(); 1204 new (N) SrcValueSDNode(V); 1205 CSEMap.InsertNode(N, IP); 1206 AllNodes.push_back(N); 1207 return SDValue(N, 0); 1208} 1209 1210SDValue SelectionDAG::getMemOperand(const MachineMemOperand &MO) { 1211#ifndef NDEBUG 1212 const Value *v = MO.getValue(); 1213 assert((!v || isa<PointerType>(v->getType())) && 1214 "SrcValue is not a pointer?"); 1215#endif 1216 1217 FoldingSetNodeID ID; 1218 AddNodeIDNode(ID, ISD::MEMOPERAND, getVTList(MVT::Other), 0, 0); 1219 MO.Profile(ID); 1220 1221 void *IP = 0; 1222 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1223 return SDValue(E, 0); 1224 1225 SDNode *N = NodeAllocator.Allocate<MemOperandSDNode>(); 1226 new (N) MemOperandSDNode(MO); 1227 CSEMap.InsertNode(N, IP); 1228 AllNodes.push_back(N); 1229 return SDValue(N, 0); 1230} 1231 1232/// getShiftAmountOperand - Return the specified value casted to 1233/// the target's desired shift amount type. 1234SDValue SelectionDAG::getShiftAmountOperand(SDValue Op) { 1235 MVT OpTy = Op.getValueType(); 1236 MVT ShTy = TLI.getShiftAmountTy(); 1237 if (OpTy == ShTy || OpTy.isVector()) return Op; 1238 1239 ISD::NodeType Opcode = OpTy.bitsGT(ShTy) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; 1240 return getNode(Opcode, Op.getDebugLoc(), ShTy, Op); 1241} 1242 1243/// CreateStackTemporary - Create a stack temporary, suitable for holding the 1244/// specified value type. 1245SDValue SelectionDAG::CreateStackTemporary(MVT VT, unsigned minAlign) { 1246 MachineFrameInfo *FrameInfo = getMachineFunction().getFrameInfo(); 1247 unsigned ByteSize = VT.getStoreSizeInBits()/8; 1248 const Type *Ty = VT.getTypeForMVT(); 1249 unsigned StackAlign = 1250 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), minAlign); 1251 1252 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, StackAlign); 1253 return getFrameIndex(FrameIdx, TLI.getPointerTy()); 1254} 1255 1256/// CreateStackTemporary - Create a stack temporary suitable for holding 1257/// either of the specified value types. 1258SDValue SelectionDAG::CreateStackTemporary(MVT VT1, MVT VT2) { 1259 unsigned Bytes = std::max(VT1.getStoreSizeInBits(), 1260 VT2.getStoreSizeInBits())/8; 1261 const Type *Ty1 = VT1.getTypeForMVT(); 1262 const Type *Ty2 = VT2.getTypeForMVT(); 1263 const TargetData *TD = TLI.getTargetData(); 1264 unsigned Align = std::max(TD->getPrefTypeAlignment(Ty1), 1265 TD->getPrefTypeAlignment(Ty2)); 1266 1267 MachineFrameInfo *FrameInfo = getMachineFunction().getFrameInfo(); 1268 int FrameIdx = FrameInfo->CreateStackObject(Bytes, Align); 1269 return getFrameIndex(FrameIdx, TLI.getPointerTy()); 1270} 1271 1272SDValue SelectionDAG::FoldSetCC(MVT VT, SDValue N1, 1273 SDValue N2, ISD::CondCode Cond, DebugLoc dl) { 1274 // These setcc operations always fold. 1275 switch (Cond) { 1276 default: break; 1277 case ISD::SETFALSE: 1278 case ISD::SETFALSE2: return getConstant(0, VT); 1279 case ISD::SETTRUE: 1280 case ISD::SETTRUE2: return getConstant(1, VT); 1281 1282 case ISD::SETOEQ: 1283 case ISD::SETOGT: 1284 case ISD::SETOGE: 1285 case ISD::SETOLT: 1286 case ISD::SETOLE: 1287 case ISD::SETONE: 1288 case ISD::SETO: 1289 case ISD::SETUO: 1290 case ISD::SETUEQ: 1291 case ISD::SETUNE: 1292 assert(!N1.getValueType().isInteger() && "Illegal setcc for integer!"); 1293 break; 1294 } 1295 1296 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode())) { 1297 const APInt &C2 = N2C->getAPIntValue(); 1298 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) { 1299 const APInt &C1 = N1C->getAPIntValue(); 1300 1301 switch (Cond) { 1302 default: assert(0 && "Unknown integer setcc!"); 1303 case ISD::SETEQ: return getConstant(C1 == C2, VT); 1304 case ISD::SETNE: return getConstant(C1 != C2, VT); 1305 case ISD::SETULT: return getConstant(C1.ult(C2), VT); 1306 case ISD::SETUGT: return getConstant(C1.ugt(C2), VT); 1307 case ISD::SETULE: return getConstant(C1.ule(C2), VT); 1308 case ISD::SETUGE: return getConstant(C1.uge(C2), VT); 1309 case ISD::SETLT: return getConstant(C1.slt(C2), VT); 1310 case ISD::SETGT: return getConstant(C1.sgt(C2), VT); 1311 case ISD::SETLE: return getConstant(C1.sle(C2), VT); 1312 case ISD::SETGE: return getConstant(C1.sge(C2), VT); 1313 } 1314 } 1315 } 1316 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.getNode())) { 1317 if (ConstantFPSDNode *N2C = dyn_cast<ConstantFPSDNode>(N2.getNode())) { 1318 // No compile time operations on this type yet. 1319 if (N1C->getValueType(0) == MVT::ppcf128) 1320 return SDValue(); 1321 1322 APFloat::cmpResult R = N1C->getValueAPF().compare(N2C->getValueAPF()); 1323 switch (Cond) { 1324 default: break; 1325 case ISD::SETEQ: if (R==APFloat::cmpUnordered) 1326 return getUNDEF(VT); 1327 // fall through 1328 case ISD::SETOEQ: return getConstant(R==APFloat::cmpEqual, VT); 1329 case ISD::SETNE: if (R==APFloat::cmpUnordered) 1330 return getUNDEF(VT); 1331 // fall through 1332 case ISD::SETONE: return getConstant(R==APFloat::cmpGreaterThan || 1333 R==APFloat::cmpLessThan, VT); 1334 case ISD::SETLT: if (R==APFloat::cmpUnordered) 1335 return getUNDEF(VT); 1336 // fall through 1337 case ISD::SETOLT: return getConstant(R==APFloat::cmpLessThan, VT); 1338 case ISD::SETGT: if (R==APFloat::cmpUnordered) 1339 return getUNDEF(VT); 1340 // fall through 1341 case ISD::SETOGT: return getConstant(R==APFloat::cmpGreaterThan, VT); 1342 case ISD::SETLE: if (R==APFloat::cmpUnordered) 1343 return getUNDEF(VT); 1344 // fall through 1345 case ISD::SETOLE: return getConstant(R==APFloat::cmpLessThan || 1346 R==APFloat::cmpEqual, VT); 1347 case ISD::SETGE: if (R==APFloat::cmpUnordered) 1348 return getUNDEF(VT); 1349 // fall through 1350 case ISD::SETOGE: return getConstant(R==APFloat::cmpGreaterThan || 1351 R==APFloat::cmpEqual, VT); 1352 case ISD::SETO: return getConstant(R!=APFloat::cmpUnordered, VT); 1353 case ISD::SETUO: return getConstant(R==APFloat::cmpUnordered, VT); 1354 case ISD::SETUEQ: return getConstant(R==APFloat::cmpUnordered || 1355 R==APFloat::cmpEqual, VT); 1356 case ISD::SETUNE: return getConstant(R!=APFloat::cmpEqual, VT); 1357 case ISD::SETULT: return getConstant(R==APFloat::cmpUnordered || 1358 R==APFloat::cmpLessThan, VT); 1359 case ISD::SETUGT: return getConstant(R==APFloat::cmpGreaterThan || 1360 R==APFloat::cmpUnordered, VT); 1361 case ISD::SETULE: return getConstant(R!=APFloat::cmpGreaterThan, VT); 1362 case ISD::SETUGE: return getConstant(R!=APFloat::cmpLessThan, VT); 1363 } 1364 } else { 1365 // Ensure that the constant occurs on the RHS. 1366 return getSetCC(dl, VT, N2, N1, ISD::getSetCCSwappedOperands(Cond)); 1367 } 1368 } 1369 1370 // Could not fold it. 1371 return SDValue(); 1372} 1373 1374/// SignBitIsZero - Return true if the sign bit of Op is known to be zero. We 1375/// use this predicate to simplify operations downstream. 1376bool SelectionDAG::SignBitIsZero(SDValue Op, unsigned Depth) const { 1377 unsigned BitWidth = Op.getValueSizeInBits(); 1378 return MaskedValueIsZero(Op, APInt::getSignBit(BitWidth), Depth); 1379} 1380 1381/// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero. We use 1382/// this predicate to simplify operations downstream. Mask is known to be zero 1383/// for bits that V cannot have. 1384bool SelectionDAG::MaskedValueIsZero(SDValue Op, const APInt &Mask, 1385 unsigned Depth) const { 1386 APInt KnownZero, KnownOne; 1387 ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth); 1388 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1389 return (KnownZero & Mask) == Mask; 1390} 1391 1392/// ComputeMaskedBits - Determine which of the bits specified in Mask are 1393/// known to be either zero or one and return them in the KnownZero/KnownOne 1394/// bitsets. This code only analyzes bits in Mask, in order to short-circuit 1395/// processing. 1396void SelectionDAG::ComputeMaskedBits(SDValue Op, const APInt &Mask, 1397 APInt &KnownZero, APInt &KnownOne, 1398 unsigned Depth) const { 1399 unsigned BitWidth = Mask.getBitWidth(); 1400 assert(BitWidth == Op.getValueType().getSizeInBits() && 1401 "Mask size mismatches value type size!"); 1402 1403 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything. 1404 if (Depth == 6 || Mask == 0) 1405 return; // Limit search depth. 1406 1407 APInt KnownZero2, KnownOne2; 1408 1409 switch (Op.getOpcode()) { 1410 case ISD::Constant: 1411 // We know all of the bits for a constant! 1412 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & Mask; 1413 KnownZero = ~KnownOne & Mask; 1414 return; 1415 case ISD::AND: 1416 // If either the LHS or the RHS are Zero, the result is zero. 1417 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1418 ComputeMaskedBits(Op.getOperand(0), Mask & ~KnownZero, 1419 KnownZero2, KnownOne2, Depth+1); 1420 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1421 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1422 1423 // Output known-1 bits are only known if set in both the LHS & RHS. 1424 KnownOne &= KnownOne2; 1425 // Output known-0 are known to be clear if zero in either the LHS | RHS. 1426 KnownZero |= KnownZero2; 1427 return; 1428 case ISD::OR: 1429 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1430 ComputeMaskedBits(Op.getOperand(0), Mask & ~KnownOne, 1431 KnownZero2, KnownOne2, Depth+1); 1432 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1433 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1434 1435 // Output known-0 bits are only known if clear in both the LHS & RHS. 1436 KnownZero &= KnownZero2; 1437 // Output known-1 are known to be set if set in either the LHS | RHS. 1438 KnownOne |= KnownOne2; 1439 return; 1440 case ISD::XOR: { 1441 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1442 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1); 1443 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1444 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1445 1446 // Output known-0 bits are known if clear or set in both the LHS & RHS. 1447 APInt KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 1448 // Output known-1 are known to be set if set in only one of the LHS, RHS. 1449 KnownOne = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 1450 KnownZero = KnownZeroOut; 1451 return; 1452 } 1453 case ISD::MUL: { 1454 APInt Mask2 = APInt::getAllOnesValue(BitWidth); 1455 ComputeMaskedBits(Op.getOperand(1), Mask2, KnownZero, KnownOne, Depth+1); 1456 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero2, KnownOne2, Depth+1); 1457 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1458 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1459 1460 // If low bits are zero in either operand, output low known-0 bits. 1461 // Also compute a conserative estimate for high known-0 bits. 1462 // More trickiness is possible, but this is sufficient for the 1463 // interesting case of alignment computation. 1464 KnownOne.clear(); 1465 unsigned TrailZ = KnownZero.countTrailingOnes() + 1466 KnownZero2.countTrailingOnes(); 1467 unsigned LeadZ = std::max(KnownZero.countLeadingOnes() + 1468 KnownZero2.countLeadingOnes(), 1469 BitWidth) - BitWidth; 1470 1471 TrailZ = std::min(TrailZ, BitWidth); 1472 LeadZ = std::min(LeadZ, BitWidth); 1473 KnownZero = APInt::getLowBitsSet(BitWidth, TrailZ) | 1474 APInt::getHighBitsSet(BitWidth, LeadZ); 1475 KnownZero &= Mask; 1476 return; 1477 } 1478 case ISD::UDIV: { 1479 // For the purposes of computing leading zeros we can conservatively 1480 // treat a udiv as a logical right shift by the power of 2 known to 1481 // be less than the denominator. 1482 APInt AllOnes = APInt::getAllOnesValue(BitWidth); 1483 ComputeMaskedBits(Op.getOperand(0), 1484 AllOnes, KnownZero2, KnownOne2, Depth+1); 1485 unsigned LeadZ = KnownZero2.countLeadingOnes(); 1486 1487 KnownOne2.clear(); 1488 KnownZero2.clear(); 1489 ComputeMaskedBits(Op.getOperand(1), 1490 AllOnes, KnownZero2, KnownOne2, Depth+1); 1491 unsigned RHSUnknownLeadingOnes = KnownOne2.countLeadingZeros(); 1492 if (RHSUnknownLeadingOnes != BitWidth) 1493 LeadZ = std::min(BitWidth, 1494 LeadZ + BitWidth - RHSUnknownLeadingOnes - 1); 1495 1496 KnownZero = APInt::getHighBitsSet(BitWidth, LeadZ) & Mask; 1497 return; 1498 } 1499 case ISD::SELECT: 1500 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero, KnownOne, Depth+1); 1501 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero2, KnownOne2, Depth+1); 1502 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1503 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1504 1505 // Only known if known in both the LHS and RHS. 1506 KnownOne &= KnownOne2; 1507 KnownZero &= KnownZero2; 1508 return; 1509 case ISD::SELECT_CC: 1510 ComputeMaskedBits(Op.getOperand(3), Mask, KnownZero, KnownOne, Depth+1); 1511 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero2, KnownOne2, Depth+1); 1512 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1513 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1514 1515 // Only known if known in both the LHS and RHS. 1516 KnownOne &= KnownOne2; 1517 KnownZero &= KnownZero2; 1518 return; 1519 case ISD::SADDO: 1520 case ISD::UADDO: 1521 case ISD::SSUBO: 1522 case ISD::USUBO: 1523 case ISD::SMULO: 1524 case ISD::UMULO: 1525 if (Op.getResNo() != 1) 1526 return; 1527 // The boolean result conforms to getBooleanContents. Fall through. 1528 case ISD::SETCC: 1529 // If we know the result of a setcc has the top bits zero, use this info. 1530 if (TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent && 1531 BitWidth > 1) 1532 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1); 1533 return; 1534 case ISD::SHL: 1535 // (shl X, C1) & C2 == 0 iff (X & C2 >>u C1) == 0 1536 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1537 unsigned ShAmt = SA->getZExtValue(); 1538 1539 // If the shift count is an invalid immediate, don't do anything. 1540 if (ShAmt >= BitWidth) 1541 return; 1542 1543 ComputeMaskedBits(Op.getOperand(0), Mask.lshr(ShAmt), 1544 KnownZero, KnownOne, Depth+1); 1545 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1546 KnownZero <<= ShAmt; 1547 KnownOne <<= ShAmt; 1548 // low bits known zero. 1549 KnownZero |= APInt::getLowBitsSet(BitWidth, ShAmt); 1550 } 1551 return; 1552 case ISD::SRL: 1553 // (ushr X, C1) & C2 == 0 iff (-1 >> C1) & C2 == 0 1554 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1555 unsigned ShAmt = SA->getZExtValue(); 1556 1557 // If the shift count is an invalid immediate, don't do anything. 1558 if (ShAmt >= BitWidth) 1559 return; 1560 1561 ComputeMaskedBits(Op.getOperand(0), (Mask << ShAmt), 1562 KnownZero, KnownOne, Depth+1); 1563 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1564 KnownZero = KnownZero.lshr(ShAmt); 1565 KnownOne = KnownOne.lshr(ShAmt); 1566 1567 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt) & Mask; 1568 KnownZero |= HighBits; // High bits known zero. 1569 } 1570 return; 1571 case ISD::SRA: 1572 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1573 unsigned ShAmt = SA->getZExtValue(); 1574 1575 // If the shift count is an invalid immediate, don't do anything. 1576 if (ShAmt >= BitWidth) 1577 return; 1578 1579 APInt InDemandedMask = (Mask << ShAmt); 1580 // If any of the demanded bits are produced by the sign extension, we also 1581 // demand the input sign bit. 1582 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt) & Mask; 1583 if (HighBits.getBoolValue()) 1584 InDemandedMask |= APInt::getSignBit(BitWidth); 1585 1586 ComputeMaskedBits(Op.getOperand(0), InDemandedMask, KnownZero, KnownOne, 1587 Depth+1); 1588 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1589 KnownZero = KnownZero.lshr(ShAmt); 1590 KnownOne = KnownOne.lshr(ShAmt); 1591 1592 // Handle the sign bits. 1593 APInt SignBit = APInt::getSignBit(BitWidth); 1594 SignBit = SignBit.lshr(ShAmt); // Adjust to where it is now in the mask. 1595 1596 if (KnownZero.intersects(SignBit)) { 1597 KnownZero |= HighBits; // New bits are known zero. 1598 } else if (KnownOne.intersects(SignBit)) { 1599 KnownOne |= HighBits; // New bits are known one. 1600 } 1601 } 1602 return; 1603 case ISD::SIGN_EXTEND_INREG: { 1604 MVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1605 unsigned EBits = EVT.getSizeInBits(); 1606 1607 // Sign extension. Compute the demanded bits in the result that are not 1608 // present in the input. 1609 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - EBits) & Mask; 1610 1611 APInt InSignBit = APInt::getSignBit(EBits); 1612 APInt InputDemandedBits = Mask & APInt::getLowBitsSet(BitWidth, EBits); 1613 1614 // If the sign extended bits are demanded, we know that the sign 1615 // bit is demanded. 1616 InSignBit.zext(BitWidth); 1617 if (NewBits.getBoolValue()) 1618 InputDemandedBits |= InSignBit; 1619 1620 ComputeMaskedBits(Op.getOperand(0), InputDemandedBits, 1621 KnownZero, KnownOne, Depth+1); 1622 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1623 1624 // If the sign bit of the input is known set or clear, then we know the 1625 // top bits of the result. 1626 if (KnownZero.intersects(InSignBit)) { // Input sign bit known clear 1627 KnownZero |= NewBits; 1628 KnownOne &= ~NewBits; 1629 } else if (KnownOne.intersects(InSignBit)) { // Input sign bit known set 1630 KnownOne |= NewBits; 1631 KnownZero &= ~NewBits; 1632 } else { // Input sign bit unknown 1633 KnownZero &= ~NewBits; 1634 KnownOne &= ~NewBits; 1635 } 1636 return; 1637 } 1638 case ISD::CTTZ: 1639 case ISD::CTLZ: 1640 case ISD::CTPOP: { 1641 unsigned LowBits = Log2_32(BitWidth)+1; 1642 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - LowBits); 1643 KnownOne.clear(); 1644 return; 1645 } 1646 case ISD::LOAD: { 1647 if (ISD::isZEXTLoad(Op.getNode())) { 1648 LoadSDNode *LD = cast<LoadSDNode>(Op); 1649 MVT VT = LD->getMemoryVT(); 1650 unsigned MemBits = VT.getSizeInBits(); 1651 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits) & Mask; 1652 } 1653 return; 1654 } 1655 case ISD::ZERO_EXTEND: { 1656 MVT InVT = Op.getOperand(0).getValueType(); 1657 unsigned InBits = InVT.getSizeInBits(); 1658 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - InBits) & Mask; 1659 APInt InMask = Mask; 1660 InMask.trunc(InBits); 1661 KnownZero.trunc(InBits); 1662 KnownOne.trunc(InBits); 1663 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1664 KnownZero.zext(BitWidth); 1665 KnownOne.zext(BitWidth); 1666 KnownZero |= NewBits; 1667 return; 1668 } 1669 case ISD::SIGN_EXTEND: { 1670 MVT InVT = Op.getOperand(0).getValueType(); 1671 unsigned InBits = InVT.getSizeInBits(); 1672 APInt InSignBit = APInt::getSignBit(InBits); 1673 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - InBits) & Mask; 1674 APInt InMask = Mask; 1675 InMask.trunc(InBits); 1676 1677 // If any of the sign extended bits are demanded, we know that the sign 1678 // bit is demanded. Temporarily set this bit in the mask for our callee. 1679 if (NewBits.getBoolValue()) 1680 InMask |= InSignBit; 1681 1682 KnownZero.trunc(InBits); 1683 KnownOne.trunc(InBits); 1684 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1685 1686 // Note if the sign bit is known to be zero or one. 1687 bool SignBitKnownZero = KnownZero.isNegative(); 1688 bool SignBitKnownOne = KnownOne.isNegative(); 1689 assert(!(SignBitKnownZero && SignBitKnownOne) && 1690 "Sign bit can't be known to be both zero and one!"); 1691 1692 // If the sign bit wasn't actually demanded by our caller, we don't 1693 // want it set in the KnownZero and KnownOne result values. Reset the 1694 // mask and reapply it to the result values. 1695 InMask = Mask; 1696 InMask.trunc(InBits); 1697 KnownZero &= InMask; 1698 KnownOne &= InMask; 1699 1700 KnownZero.zext(BitWidth); 1701 KnownOne.zext(BitWidth); 1702 1703 // If the sign bit is known zero or one, the top bits match. 1704 if (SignBitKnownZero) 1705 KnownZero |= NewBits; 1706 else if (SignBitKnownOne) 1707 KnownOne |= NewBits; 1708 return; 1709 } 1710 case ISD::ANY_EXTEND: { 1711 MVT InVT = Op.getOperand(0).getValueType(); 1712 unsigned InBits = InVT.getSizeInBits(); 1713 APInt InMask = Mask; 1714 InMask.trunc(InBits); 1715 KnownZero.trunc(InBits); 1716 KnownOne.trunc(InBits); 1717 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1718 KnownZero.zext(BitWidth); 1719 KnownOne.zext(BitWidth); 1720 return; 1721 } 1722 case ISD::TRUNCATE: { 1723 MVT InVT = Op.getOperand(0).getValueType(); 1724 unsigned InBits = InVT.getSizeInBits(); 1725 APInt InMask = Mask; 1726 InMask.zext(InBits); 1727 KnownZero.zext(InBits); 1728 KnownOne.zext(InBits); 1729 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1730 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1731 KnownZero.trunc(BitWidth); 1732 KnownOne.trunc(BitWidth); 1733 break; 1734 } 1735 case ISD::AssertZext: { 1736 MVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1737 APInt InMask = APInt::getLowBitsSet(BitWidth, VT.getSizeInBits()); 1738 ComputeMaskedBits(Op.getOperand(0), Mask & InMask, KnownZero, 1739 KnownOne, Depth+1); 1740 KnownZero |= (~InMask) & Mask; 1741 return; 1742 } 1743 case ISD::FGETSIGN: 1744 // All bits are zero except the low bit. 1745 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - 1); 1746 return; 1747 1748 case ISD::SUB: { 1749 if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) { 1750 // We know that the top bits of C-X are clear if X contains less bits 1751 // than C (i.e. no wrap-around can happen). For example, 20-X is 1752 // positive if we can prove that X is >= 0 and < 16. 1753 if (CLHS->getAPIntValue().isNonNegative()) { 1754 unsigned NLZ = (CLHS->getAPIntValue()+1).countLeadingZeros(); 1755 // NLZ can't be BitWidth with no sign bit 1756 APInt MaskV = APInt::getHighBitsSet(BitWidth, NLZ+1); 1757 ComputeMaskedBits(Op.getOperand(1), MaskV, KnownZero2, KnownOne2, 1758 Depth+1); 1759 1760 // If all of the MaskV bits are known to be zero, then we know the 1761 // output top bits are zero, because we now know that the output is 1762 // from [0-C]. 1763 if ((KnownZero2 & MaskV) == MaskV) { 1764 unsigned NLZ2 = CLHS->getAPIntValue().countLeadingZeros(); 1765 // Top bits known zero. 1766 KnownZero = APInt::getHighBitsSet(BitWidth, NLZ2) & Mask; 1767 } 1768 } 1769 } 1770 } 1771 // fall through 1772 case ISD::ADD: { 1773 // Output known-0 bits are known if clear or set in both the low clear bits 1774 // common to both LHS & RHS. For example, 8+(X<<3) is known to have the 1775 // low 3 bits clear. 1776 APInt Mask2 = APInt::getLowBitsSet(BitWidth, Mask.countTrailingOnes()); 1777 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero2, KnownOne2, Depth+1); 1778 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1779 unsigned KnownZeroOut = KnownZero2.countTrailingOnes(); 1780 1781 ComputeMaskedBits(Op.getOperand(1), Mask2, KnownZero2, KnownOne2, Depth+1); 1782 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1783 KnownZeroOut = std::min(KnownZeroOut, 1784 KnownZero2.countTrailingOnes()); 1785 1786 KnownZero |= APInt::getLowBitsSet(BitWidth, KnownZeroOut); 1787 return; 1788 } 1789 case ISD::SREM: 1790 if (ConstantSDNode *Rem = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1791 const APInt &RA = Rem->getAPIntValue(); 1792 if (RA.isPowerOf2() || (-RA).isPowerOf2()) { 1793 APInt LowBits = RA.isStrictlyPositive() ? (RA - 1) : ~RA; 1794 APInt Mask2 = LowBits | APInt::getSignBit(BitWidth); 1795 ComputeMaskedBits(Op.getOperand(0), Mask2,KnownZero2,KnownOne2,Depth+1); 1796 1797 // If the sign bit of the first operand is zero, the sign bit of 1798 // the result is zero. If the first operand has no one bits below 1799 // the second operand's single 1 bit, its sign will be zero. 1800 if (KnownZero2[BitWidth-1] || ((KnownZero2 & LowBits) == LowBits)) 1801 KnownZero2 |= ~LowBits; 1802 1803 KnownZero |= KnownZero2 & Mask; 1804 1805 assert((KnownZero & KnownOne) == 0&&"Bits known to be one AND zero?"); 1806 } 1807 } 1808 return; 1809 case ISD::UREM: { 1810 if (ConstantSDNode *Rem = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1811 const APInt &RA = Rem->getAPIntValue(); 1812 if (RA.isPowerOf2()) { 1813 APInt LowBits = (RA - 1); 1814 APInt Mask2 = LowBits & Mask; 1815 KnownZero |= ~LowBits & Mask; 1816 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero, KnownOne,Depth+1); 1817 assert((KnownZero & KnownOne) == 0&&"Bits known to be one AND zero?"); 1818 break; 1819 } 1820 } 1821 1822 // Since the result is less than or equal to either operand, any leading 1823 // zero bits in either operand must also exist in the result. 1824 APInt AllOnes = APInt::getAllOnesValue(BitWidth); 1825 ComputeMaskedBits(Op.getOperand(0), AllOnes, KnownZero, KnownOne, 1826 Depth+1); 1827 ComputeMaskedBits(Op.getOperand(1), AllOnes, KnownZero2, KnownOne2, 1828 Depth+1); 1829 1830 uint32_t Leaders = std::max(KnownZero.countLeadingOnes(), 1831 KnownZero2.countLeadingOnes()); 1832 KnownOne.clear(); 1833 KnownZero = APInt::getHighBitsSet(BitWidth, Leaders) & Mask; 1834 return; 1835 } 1836 default: 1837 // Allow the target to implement this method for its nodes. 1838 if (Op.getOpcode() >= ISD::BUILTIN_OP_END) { 1839 case ISD::INTRINSIC_WO_CHAIN: 1840 case ISD::INTRINSIC_W_CHAIN: 1841 case ISD::INTRINSIC_VOID: 1842 TLI.computeMaskedBitsForTargetNode(Op, Mask, KnownZero, KnownOne, *this); 1843 } 1844 return; 1845 } 1846} 1847 1848/// ComputeNumSignBits - Return the number of times the sign bit of the 1849/// register is replicated into the other bits. We know that at least 1 bit 1850/// is always equal to the sign bit (itself), but other cases can give us 1851/// information. For example, immediately after an "SRA X, 2", we know that 1852/// the top 3 bits are all equal to each other, so we return 3. 1853unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, unsigned Depth) const{ 1854 MVT VT = Op.getValueType(); 1855 assert(VT.isInteger() && "Invalid VT!"); 1856 unsigned VTBits = VT.getSizeInBits(); 1857 unsigned Tmp, Tmp2; 1858 unsigned FirstAnswer = 1; 1859 1860 if (Depth == 6) 1861 return 1; // Limit search depth. 1862 1863 switch (Op.getOpcode()) { 1864 default: break; 1865 case ISD::AssertSext: 1866 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); 1867 return VTBits-Tmp+1; 1868 case ISD::AssertZext: 1869 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); 1870 return VTBits-Tmp; 1871 1872 case ISD::Constant: { 1873 const APInt &Val = cast<ConstantSDNode>(Op)->getAPIntValue(); 1874 // If negative, return # leading ones. 1875 if (Val.isNegative()) 1876 return Val.countLeadingOnes(); 1877 1878 // Return # leading zeros. 1879 return Val.countLeadingZeros(); 1880 } 1881 1882 case ISD::SIGN_EXTEND: 1883 Tmp = VTBits-Op.getOperand(0).getValueType().getSizeInBits(); 1884 return ComputeNumSignBits(Op.getOperand(0), Depth+1) + Tmp; 1885 1886 case ISD::SIGN_EXTEND_INREG: 1887 // Max of the input and what this extends. 1888 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); 1889 Tmp = VTBits-Tmp+1; 1890 1891 Tmp2 = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1892 return std::max(Tmp, Tmp2); 1893 1894 case ISD::SRA: 1895 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1896 // SRA X, C -> adds C sign bits. 1897 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1898 Tmp += C->getZExtValue(); 1899 if (Tmp > VTBits) Tmp = VTBits; 1900 } 1901 return Tmp; 1902 case ISD::SHL: 1903 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1904 // shl destroys sign bits. 1905 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1906 if (C->getZExtValue() >= VTBits || // Bad shift. 1907 C->getZExtValue() >= Tmp) break; // Shifted all sign bits out. 1908 return Tmp - C->getZExtValue(); 1909 } 1910 break; 1911 case ISD::AND: 1912 case ISD::OR: 1913 case ISD::XOR: // NOT is handled here. 1914 // Logical binary ops preserve the number of sign bits at the worst. 1915 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1916 if (Tmp != 1) { 1917 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 1918 FirstAnswer = std::min(Tmp, Tmp2); 1919 // We computed what we know about the sign bits as our first 1920 // answer. Now proceed to the generic code that uses 1921 // ComputeMaskedBits, and pick whichever answer is better. 1922 } 1923 break; 1924 1925 case ISD::SELECT: 1926 Tmp = ComputeNumSignBits(Op.getOperand(1), Depth+1); 1927 if (Tmp == 1) return 1; // Early out. 1928 Tmp2 = ComputeNumSignBits(Op.getOperand(2), Depth+1); 1929 return std::min(Tmp, Tmp2); 1930 1931 case ISD::SADDO: 1932 case ISD::UADDO: 1933 case ISD::SSUBO: 1934 case ISD::USUBO: 1935 case ISD::SMULO: 1936 case ISD::UMULO: 1937 if (Op.getResNo() != 1) 1938 break; 1939 // The boolean result conforms to getBooleanContents. Fall through. 1940 case ISD::SETCC: 1941 // If setcc returns 0/-1, all bits are sign bits. 1942 if (TLI.getBooleanContents() == 1943 TargetLowering::ZeroOrNegativeOneBooleanContent) 1944 return VTBits; 1945 break; 1946 case ISD::ROTL: 1947 case ISD::ROTR: 1948 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1949 unsigned RotAmt = C->getZExtValue() & (VTBits-1); 1950 1951 // Handle rotate right by N like a rotate left by 32-N. 1952 if (Op.getOpcode() == ISD::ROTR) 1953 RotAmt = (VTBits-RotAmt) & (VTBits-1); 1954 1955 // If we aren't rotating out all of the known-in sign bits, return the 1956 // number that are left. This handles rotl(sext(x), 1) for example. 1957 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1958 if (Tmp > RotAmt+1) return Tmp-RotAmt; 1959 } 1960 break; 1961 case ISD::ADD: 1962 // Add can have at most one carry bit. Thus we know that the output 1963 // is, at worst, one more bit than the inputs. 1964 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1965 if (Tmp == 1) return 1; // Early out. 1966 1967 // Special case decrementing a value (ADD X, -1): 1968 if (ConstantSDNode *CRHS = dyn_cast<ConstantSDNode>(Op.getOperand(1))) 1969 if (CRHS->isAllOnesValue()) { 1970 APInt KnownZero, KnownOne; 1971 APInt Mask = APInt::getAllOnesValue(VTBits); 1972 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1); 1973 1974 // If the input is known to be 0 or 1, the output is 0/-1, which is all 1975 // sign bits set. 1976 if ((KnownZero | APInt(VTBits, 1)) == Mask) 1977 return VTBits; 1978 1979 // If we are subtracting one from a positive number, there is no carry 1980 // out of the result. 1981 if (KnownZero.isNegative()) 1982 return Tmp; 1983 } 1984 1985 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 1986 if (Tmp2 == 1) return 1; 1987 return std::min(Tmp, Tmp2)-1; 1988 break; 1989 1990 case ISD::SUB: 1991 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 1992 if (Tmp2 == 1) return 1; 1993 1994 // Handle NEG. 1995 if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) 1996 if (CLHS->isNullValue()) { 1997 APInt KnownZero, KnownOne; 1998 APInt Mask = APInt::getAllOnesValue(VTBits); 1999 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 2000 // If the input is known to be 0 or 1, the output is 0/-1, which is all 2001 // sign bits set. 2002 if ((KnownZero | APInt(VTBits, 1)) == Mask) 2003 return VTBits; 2004 2005 // If the input is known to be positive (the sign bit is known clear), 2006 // the output of the NEG has the same number of sign bits as the input. 2007 if (KnownZero.isNegative()) 2008 return Tmp2; 2009 2010 // Otherwise, we treat this like a SUB. 2011 } 2012 2013 // Sub can have at most one carry bit. Thus we know that the output 2014 // is, at worst, one more bit than the inputs. 2015 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 2016 if (Tmp == 1) return 1; // Early out. 2017 return std::min(Tmp, Tmp2)-1; 2018 break; 2019 case ISD::TRUNCATE: 2020 // FIXME: it's tricky to do anything useful for this, but it is an important 2021 // case for targets like X86. 2022 break; 2023 } 2024 2025 // Handle LOADX separately here. EXTLOAD case will fallthrough. 2026 if (Op.getOpcode() == ISD::LOAD) { 2027 LoadSDNode *LD = cast<LoadSDNode>(Op); 2028 unsigned ExtType = LD->getExtensionType(); 2029 switch (ExtType) { 2030 default: break; 2031 case ISD::SEXTLOAD: // '17' bits known 2032 Tmp = LD->getMemoryVT().getSizeInBits(); 2033 return VTBits-Tmp+1; 2034 case ISD::ZEXTLOAD: // '16' bits known 2035 Tmp = LD->getMemoryVT().getSizeInBits(); 2036 return VTBits-Tmp; 2037 } 2038 } 2039 2040 // Allow the target to implement this method for its nodes. 2041 if (Op.getOpcode() >= ISD::BUILTIN_OP_END || 2042 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 2043 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 2044 Op.getOpcode() == ISD::INTRINSIC_VOID) { 2045 unsigned NumBits = TLI.ComputeNumSignBitsForTargetNode(Op, Depth); 2046 if (NumBits > 1) FirstAnswer = std::max(FirstAnswer, NumBits); 2047 } 2048 2049 // Finally, if we can prove that the top bits of the result are 0's or 1's, 2050 // use this information. 2051 APInt KnownZero, KnownOne; 2052 APInt Mask = APInt::getAllOnesValue(VTBits); 2053 ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth); 2054 2055 if (KnownZero.isNegative()) { // sign bit is 0 2056 Mask = KnownZero; 2057 } else if (KnownOne.isNegative()) { // sign bit is 1; 2058 Mask = KnownOne; 2059 } else { 2060 // Nothing known. 2061 return FirstAnswer; 2062 } 2063 2064 // Okay, we know that the sign bit in Mask is set. Use CLZ to determine 2065 // the number of identical bits in the top of the input value. 2066 Mask = ~Mask; 2067 Mask <<= Mask.getBitWidth()-VTBits; 2068 // Return # leading zeros. We use 'min' here in case Val was zero before 2069 // shifting. We don't want to return '64' as for an i32 "0". 2070 return std::max(FirstAnswer, std::min(VTBits, Mask.countLeadingZeros())); 2071} 2072 2073 2074bool SelectionDAG::isVerifiedDebugInfoDesc(SDValue Op) const { 2075 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op); 2076 if (!GA) return false; 2077 if (GA->getOffset() != 0) return false; 2078 GlobalVariable *GV = dyn_cast<GlobalVariable>(GA->getGlobal()); 2079 if (!GV) return false; 2080 MachineModuleInfo *MMI = getMachineModuleInfo(); 2081 return MMI && MMI->hasDebugInfo(); 2082} 2083 2084 2085/// getShuffleScalarElt - Returns the scalar element that will make up the ith 2086/// element of the result of the vector shuffle. 2087SDValue SelectionDAG::getShuffleScalarElt(const SDNode *N, unsigned i) { 2088 MVT VT = N->getValueType(0); 2089 DebugLoc dl = N->getDebugLoc(); 2090 SDValue PermMask = N->getOperand(2); 2091 SDValue Idx = PermMask.getOperand(i); 2092 if (Idx.getOpcode() == ISD::UNDEF) 2093 return getUNDEF(VT.getVectorElementType()); 2094 unsigned Index = cast<ConstantSDNode>(Idx)->getZExtValue(); 2095 unsigned NumElems = PermMask.getNumOperands(); 2096 SDValue V = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1); 2097 Index %= NumElems; 2098 2099 if (V.getOpcode() == ISD::BIT_CONVERT) { 2100 V = V.getOperand(0); 2101 MVT VVT = V.getValueType(); 2102 if (!VVT.isVector() || VVT.getVectorNumElements() != NumElems) 2103 return SDValue(); 2104 } 2105 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) 2106 return (Index == 0) ? V.getOperand(0) 2107 : getUNDEF(VT.getVectorElementType()); 2108 if (V.getOpcode() == ISD::BUILD_VECTOR) 2109 return V.getOperand(Index); 2110 if (V.getOpcode() == ISD::VECTOR_SHUFFLE) 2111 return getShuffleScalarElt(V.getNode(), Index); 2112 return SDValue(); 2113} 2114 2115 2116/// getNode - Gets or creates the specified node. 2117/// 2118SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT) { 2119 FoldingSetNodeID ID; 2120 AddNodeIDNode(ID, Opcode, getVTList(VT), 0, 0); 2121 void *IP = 0; 2122 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2123 return SDValue(E, 0); 2124 SDNode *N = NodeAllocator.Allocate<SDNode>(); 2125 new (N) SDNode(Opcode, DL, getVTList(VT)); 2126 CSEMap.InsertNode(N, IP); 2127 2128 AllNodes.push_back(N); 2129#ifndef NDEBUG 2130 VerifyNode(N); 2131#endif 2132 return SDValue(N, 0); 2133} 2134 2135SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, 2136 MVT VT, SDValue Operand) { 2137 // Constant fold unary operations with an integer constant operand. 2138 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Operand.getNode())) { 2139 const APInt &Val = C->getAPIntValue(); 2140 unsigned BitWidth = VT.getSizeInBits(); 2141 switch (Opcode) { 2142 default: break; 2143 case ISD::SIGN_EXTEND: 2144 return getConstant(APInt(Val).sextOrTrunc(BitWidth), VT); 2145 case ISD::ANY_EXTEND: 2146 case ISD::ZERO_EXTEND: 2147 case ISD::TRUNCATE: 2148 return getConstant(APInt(Val).zextOrTrunc(BitWidth), VT); 2149 case ISD::UINT_TO_FP: 2150 case ISD::SINT_TO_FP: { 2151 const uint64_t zero[] = {0, 0}; 2152 // No compile time operations on this type. 2153 if (VT==MVT::ppcf128) 2154 break; 2155 APFloat apf = APFloat(APInt(BitWidth, 2, zero)); 2156 (void)apf.convertFromAPInt(Val, 2157 Opcode==ISD::SINT_TO_FP, 2158 APFloat::rmNearestTiesToEven); 2159 return getConstantFP(apf, VT); 2160 } 2161 case ISD::BIT_CONVERT: 2162 if (VT == MVT::f32 && C->getValueType(0) == MVT::i32) 2163 return getConstantFP(Val.bitsToFloat(), VT); 2164 else if (VT == MVT::f64 && C->getValueType(0) == MVT::i64) 2165 return getConstantFP(Val.bitsToDouble(), VT); 2166 break; 2167 case ISD::BSWAP: 2168 return getConstant(Val.byteSwap(), VT); 2169 case ISD::CTPOP: 2170 return getConstant(Val.countPopulation(), VT); 2171 case ISD::CTLZ: 2172 return getConstant(Val.countLeadingZeros(), VT); 2173 case ISD::CTTZ: 2174 return getConstant(Val.countTrailingZeros(), VT); 2175 } 2176 } 2177 2178 // Constant fold unary operations with a floating point constant operand. 2179 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Operand.getNode())) { 2180 APFloat V = C->getValueAPF(); // make copy 2181 if (VT != MVT::ppcf128 && Operand.getValueType() != MVT::ppcf128) { 2182 switch (Opcode) { 2183 case ISD::FNEG: 2184 V.changeSign(); 2185 return getConstantFP(V, VT); 2186 case ISD::FABS: 2187 V.clearSign(); 2188 return getConstantFP(V, VT); 2189 case ISD::FP_ROUND: 2190 case ISD::FP_EXTEND: { 2191 bool ignored; 2192 // This can return overflow, underflow, or inexact; we don't care. 2193 // FIXME need to be more flexible about rounding mode. 2194 (void)V.convert(*MVTToAPFloatSemantics(VT), 2195 APFloat::rmNearestTiesToEven, &ignored); 2196 return getConstantFP(V, VT); 2197 } 2198 case ISD::FP_TO_SINT: 2199 case ISD::FP_TO_UINT: { 2200 integerPart x[2]; 2201 bool ignored; 2202 assert(integerPartWidth >= 64); 2203 // FIXME need to be more flexible about rounding mode. 2204 APFloat::opStatus s = V.convertToInteger(x, VT.getSizeInBits(), 2205 Opcode==ISD::FP_TO_SINT, 2206 APFloat::rmTowardZero, &ignored); 2207 if (s==APFloat::opInvalidOp) // inexact is OK, in fact usual 2208 break; 2209 APInt api(VT.getSizeInBits(), 2, x); 2210 return getConstant(api, VT); 2211 } 2212 case ISD::BIT_CONVERT: 2213 if (VT == MVT::i32 && C->getValueType(0) == MVT::f32) 2214 return getConstant((uint32_t)V.bitcastToAPInt().getZExtValue(), VT); 2215 else if (VT == MVT::i64 && C->getValueType(0) == MVT::f64) 2216 return getConstant(V.bitcastToAPInt().getZExtValue(), VT); 2217 break; 2218 } 2219 } 2220 } 2221 2222 unsigned OpOpcode = Operand.getNode()->getOpcode(); 2223 switch (Opcode) { 2224 case ISD::TokenFactor: 2225 case ISD::MERGE_VALUES: 2226 case ISD::CONCAT_VECTORS: 2227 return Operand; // Factor, merge or concat of one node? No need. 2228 case ISD::FP_ROUND: assert(0 && "Invalid method to make FP_ROUND node"); 2229 case ISD::FP_EXTEND: 2230 assert(VT.isFloatingPoint() && 2231 Operand.getValueType().isFloatingPoint() && "Invalid FP cast!"); 2232 if (Operand.getValueType() == VT) return Operand; // noop conversion. 2233 if (Operand.getOpcode() == ISD::UNDEF) 2234 return getUNDEF(VT); 2235 break; 2236 case ISD::SIGN_EXTEND: 2237 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2238 "Invalid SIGN_EXTEND!"); 2239 if (Operand.getValueType() == VT) return Operand; // noop extension 2240 assert(Operand.getValueType().bitsLT(VT) 2241 && "Invalid sext node, dst < src!"); 2242 if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND) 2243 return getNode(OpOpcode, DL, VT, Operand.getNode()->getOperand(0)); 2244 break; 2245 case ISD::ZERO_EXTEND: 2246 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2247 "Invalid ZERO_EXTEND!"); 2248 if (Operand.getValueType() == VT) return Operand; // noop extension 2249 assert(Operand.getValueType().bitsLT(VT) 2250 && "Invalid zext node, dst < src!"); 2251 if (OpOpcode == ISD::ZERO_EXTEND) // (zext (zext x)) -> (zext x) 2252 return getNode(ISD::ZERO_EXTEND, DL, VT, 2253 Operand.getNode()->getOperand(0)); 2254 break; 2255 case ISD::ANY_EXTEND: 2256 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2257 "Invalid ANY_EXTEND!"); 2258 if (Operand.getValueType() == VT) return Operand; // noop extension 2259 assert(Operand.getValueType().bitsLT(VT) 2260 && "Invalid anyext node, dst < src!"); 2261 if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND) 2262 // (ext (zext x)) -> (zext x) and (ext (sext x)) -> (sext x) 2263 return getNode(OpOpcode, DL, VT, Operand.getNode()->getOperand(0)); 2264 break; 2265 case ISD::TRUNCATE: 2266 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2267 "Invalid TRUNCATE!"); 2268 if (Operand.getValueType() == VT) return Operand; // noop truncate 2269 assert(Operand.getValueType().bitsGT(VT) 2270 && "Invalid truncate node, src < dst!"); 2271 if (OpOpcode == ISD::TRUNCATE) 2272 return getNode(ISD::TRUNCATE, DL, VT, Operand.getNode()->getOperand(0)); 2273 else if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND || 2274 OpOpcode == ISD::ANY_EXTEND) { 2275 // If the source is smaller than the dest, we still need an extend. 2276 if (Operand.getNode()->getOperand(0).getValueType().bitsLT(VT)) 2277 return getNode(OpOpcode, DL, VT, Operand.getNode()->getOperand(0)); 2278 else if (Operand.getNode()->getOperand(0).getValueType().bitsGT(VT)) 2279 return getNode(ISD::TRUNCATE, DL, VT, Operand.getNode()->getOperand(0)); 2280 else 2281 return Operand.getNode()->getOperand(0); 2282 } 2283 break; 2284 case ISD::BIT_CONVERT: 2285 // Basic sanity checking. 2286 assert(VT.getSizeInBits() == Operand.getValueType().getSizeInBits() 2287 && "Cannot BIT_CONVERT between types of different sizes!"); 2288 if (VT == Operand.getValueType()) return Operand; // noop conversion. 2289 if (OpOpcode == ISD::BIT_CONVERT) // bitconv(bitconv(x)) -> bitconv(x) 2290 return getNode(ISD::BIT_CONVERT, DL, VT, Operand.getOperand(0)); 2291 if (OpOpcode == ISD::UNDEF) 2292 return getUNDEF(VT); 2293 break; 2294 case ISD::SCALAR_TO_VECTOR: 2295 assert(VT.isVector() && !Operand.getValueType().isVector() && 2296 (VT.getVectorElementType() == Operand.getValueType() || 2297 (VT.getVectorElementType().isInteger() && 2298 Operand.getValueType().isInteger() && 2299 VT.getVectorElementType().bitsLE(Operand.getValueType()))) && 2300 "Illegal SCALAR_TO_VECTOR node!"); 2301 if (OpOpcode == ISD::UNDEF) 2302 return getUNDEF(VT); 2303 // scalar_to_vector(extract_vector_elt V, 0) -> V, top bits are undefined. 2304 if (OpOpcode == ISD::EXTRACT_VECTOR_ELT && 2305 isa<ConstantSDNode>(Operand.getOperand(1)) && 2306 Operand.getConstantOperandVal(1) == 0 && 2307 Operand.getOperand(0).getValueType() == VT) 2308 return Operand.getOperand(0); 2309 break; 2310 case ISD::FNEG: 2311 // -(X-Y) -> (Y-X) is unsafe because when X==Y, -0.0 != +0.0 2312 if (UnsafeFPMath && OpOpcode == ISD::FSUB) 2313 return getNode(ISD::FSUB, DL, VT, Operand.getNode()->getOperand(1), 2314 Operand.getNode()->getOperand(0)); 2315 if (OpOpcode == ISD::FNEG) // --X -> X 2316 return Operand.getNode()->getOperand(0); 2317 break; 2318 case ISD::FABS: 2319 if (OpOpcode == ISD::FNEG) // abs(-X) -> abs(X) 2320 return getNode(ISD::FABS, DL, VT, Operand.getNode()->getOperand(0)); 2321 break; 2322 } 2323 2324 SDNode *N; 2325 SDVTList VTs = getVTList(VT); 2326 if (VT != MVT::Flag) { // Don't CSE flag producing nodes 2327 FoldingSetNodeID ID; 2328 SDValue Ops[1] = { Operand }; 2329 AddNodeIDNode(ID, Opcode, VTs, Ops, 1); 2330 void *IP = 0; 2331 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2332 return SDValue(E, 0); 2333 N = NodeAllocator.Allocate<UnarySDNode>(); 2334 new (N) UnarySDNode(Opcode, DL, VTs, Operand); 2335 CSEMap.InsertNode(N, IP); 2336 } else { 2337 N = NodeAllocator.Allocate<UnarySDNode>(); 2338 new (N) UnarySDNode(Opcode, DL, VTs, Operand); 2339 } 2340 2341 AllNodes.push_back(N); 2342#ifndef NDEBUG 2343 VerifyNode(N); 2344#endif 2345 return SDValue(N, 0); 2346} 2347 2348SDValue SelectionDAG::FoldConstantArithmetic(unsigned Opcode, 2349 MVT VT, 2350 ConstantSDNode *Cst1, 2351 ConstantSDNode *Cst2) { 2352 const APInt &C1 = Cst1->getAPIntValue(), &C2 = Cst2->getAPIntValue(); 2353 2354 switch (Opcode) { 2355 case ISD::ADD: return getConstant(C1 + C2, VT); 2356 case ISD::SUB: return getConstant(C1 - C2, VT); 2357 case ISD::MUL: return getConstant(C1 * C2, VT); 2358 case ISD::UDIV: 2359 if (C2.getBoolValue()) return getConstant(C1.udiv(C2), VT); 2360 break; 2361 case ISD::UREM: 2362 if (C2.getBoolValue()) return getConstant(C1.urem(C2), VT); 2363 break; 2364 case ISD::SDIV: 2365 if (C2.getBoolValue()) return getConstant(C1.sdiv(C2), VT); 2366 break; 2367 case ISD::SREM: 2368 if (C2.getBoolValue()) return getConstant(C1.srem(C2), VT); 2369 break; 2370 case ISD::AND: return getConstant(C1 & C2, VT); 2371 case ISD::OR: return getConstant(C1 | C2, VT); 2372 case ISD::XOR: return getConstant(C1 ^ C2, VT); 2373 case ISD::SHL: return getConstant(C1 << C2, VT); 2374 case ISD::SRL: return getConstant(C1.lshr(C2), VT); 2375 case ISD::SRA: return getConstant(C1.ashr(C2), VT); 2376 case ISD::ROTL: return getConstant(C1.rotl(C2), VT); 2377 case ISD::ROTR: return getConstant(C1.rotr(C2), VT); 2378 default: break; 2379 } 2380 2381 return SDValue(); 2382} 2383 2384SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, 2385 SDValue N1, SDValue N2) { 2386 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 2387 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 2388 switch (Opcode) { 2389 default: break; 2390 case ISD::TokenFactor: 2391 assert(VT == MVT::Other && N1.getValueType() == MVT::Other && 2392 N2.getValueType() == MVT::Other && "Invalid token factor!"); 2393 // Fold trivial token factors. 2394 if (N1.getOpcode() == ISD::EntryToken) return N2; 2395 if (N2.getOpcode() == ISD::EntryToken) return N1; 2396 if (N1 == N2) return N1; 2397 break; 2398 case ISD::CONCAT_VECTORS: 2399 // A CONCAT_VECTOR with all operands BUILD_VECTOR can be simplified to 2400 // one big BUILD_VECTOR. 2401 if (N1.getOpcode() == ISD::BUILD_VECTOR && 2402 N2.getOpcode() == ISD::BUILD_VECTOR) { 2403 SmallVector<SDValue, 16> Elts(N1.getNode()->op_begin(), N1.getNode()->op_end()); 2404 Elts.insert(Elts.end(), N2.getNode()->op_begin(), N2.getNode()->op_end()); 2405 return getNode(ISD::BUILD_VECTOR, DL, VT, &Elts[0], Elts.size()); 2406 } 2407 break; 2408 case ISD::AND: 2409 assert(VT.isInteger() && N1.getValueType() == N2.getValueType() && 2410 N1.getValueType() == VT && "Binary operator types must match!"); 2411 // (X & 0) -> 0. This commonly occurs when legalizing i64 values, so it's 2412 // worth handling here. 2413 if (N2C && N2C->isNullValue()) 2414 return N2; 2415 if (N2C && N2C->isAllOnesValue()) // X & -1 -> X 2416 return N1; 2417 break; 2418 case ISD::OR: 2419 case ISD::XOR: 2420 case ISD::ADD: 2421 case ISD::SUB: 2422 assert(VT.isInteger() && N1.getValueType() == N2.getValueType() && 2423 N1.getValueType() == VT && "Binary operator types must match!"); 2424 // (X ^|+- 0) -> X. This commonly occurs when legalizing i64 values, so 2425 // it's worth handling here. 2426 if (N2C && N2C->isNullValue()) 2427 return N1; 2428 break; 2429 case ISD::UDIV: 2430 case ISD::UREM: 2431 case ISD::MULHU: 2432 case ISD::MULHS: 2433 case ISD::MUL: 2434 case ISD::SDIV: 2435 case ISD::SREM: 2436 assert(VT.isInteger() && "This operator does not apply to FP types!"); 2437 // fall through 2438 case ISD::FADD: 2439 case ISD::FSUB: 2440 case ISD::FMUL: 2441 case ISD::FDIV: 2442 case ISD::FREM: 2443 if (UnsafeFPMath) { 2444 if (Opcode == ISD::FADD) { 2445 // 0+x --> x 2446 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) 2447 if (CFP->getValueAPF().isZero()) 2448 return N2; 2449 // x+0 --> x 2450 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N2)) 2451 if (CFP->getValueAPF().isZero()) 2452 return N1; 2453 } else if (Opcode == ISD::FSUB) { 2454 // x-0 --> x 2455 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N2)) 2456 if (CFP->getValueAPF().isZero()) 2457 return N1; 2458 } 2459 } 2460 assert(N1.getValueType() == N2.getValueType() && 2461 N1.getValueType() == VT && "Binary operator types must match!"); 2462 break; 2463 case ISD::FCOPYSIGN: // N1 and result must match. N1/N2 need not match. 2464 assert(N1.getValueType() == VT && 2465 N1.getValueType().isFloatingPoint() && 2466 N2.getValueType().isFloatingPoint() && 2467 "Invalid FCOPYSIGN!"); 2468 break; 2469 case ISD::SHL: 2470 case ISD::SRA: 2471 case ISD::SRL: 2472 case ISD::ROTL: 2473 case ISD::ROTR: 2474 assert(VT == N1.getValueType() && 2475 "Shift operators return type must be the same as their first arg"); 2476 assert(VT.isInteger() && N2.getValueType().isInteger() && 2477 "Shifts only work on integers"); 2478 2479 // Always fold shifts of i1 values so the code generator doesn't need to 2480 // handle them. Since we know the size of the shift has to be less than the 2481 // size of the value, the shift/rotate count is guaranteed to be zero. 2482 if (VT == MVT::i1) 2483 return N1; 2484 break; 2485 case ISD::FP_ROUND_INREG: { 2486 MVT EVT = cast<VTSDNode>(N2)->getVT(); 2487 assert(VT == N1.getValueType() && "Not an inreg round!"); 2488 assert(VT.isFloatingPoint() && EVT.isFloatingPoint() && 2489 "Cannot FP_ROUND_INREG integer types"); 2490 assert(EVT.bitsLE(VT) && "Not rounding down!"); 2491 if (cast<VTSDNode>(N2)->getVT() == VT) return N1; // Not actually rounding. 2492 break; 2493 } 2494 case ISD::FP_ROUND: 2495 assert(VT.isFloatingPoint() && 2496 N1.getValueType().isFloatingPoint() && 2497 VT.bitsLE(N1.getValueType()) && 2498 isa<ConstantSDNode>(N2) && "Invalid FP_ROUND!"); 2499 if (N1.getValueType() == VT) return N1; // noop conversion. 2500 break; 2501 case ISD::AssertSext: 2502 case ISD::AssertZext: { 2503 MVT EVT = cast<VTSDNode>(N2)->getVT(); 2504 assert(VT == N1.getValueType() && "Not an inreg extend!"); 2505 assert(VT.isInteger() && EVT.isInteger() && 2506 "Cannot *_EXTEND_INREG FP types"); 2507 assert(EVT.bitsLE(VT) && "Not extending!"); 2508 if (VT == EVT) return N1; // noop assertion. 2509 break; 2510 } 2511 case ISD::SIGN_EXTEND_INREG: { 2512 MVT EVT = cast<VTSDNode>(N2)->getVT(); 2513 assert(VT == N1.getValueType() && "Not an inreg extend!"); 2514 assert(VT.isInteger() && EVT.isInteger() && 2515 "Cannot *_EXTEND_INREG FP types"); 2516 assert(EVT.bitsLE(VT) && "Not extending!"); 2517 if (EVT == VT) return N1; // Not actually extending 2518 2519 if (N1C) { 2520 APInt Val = N1C->getAPIntValue(); 2521 unsigned FromBits = cast<VTSDNode>(N2)->getVT().getSizeInBits(); 2522 Val <<= Val.getBitWidth()-FromBits; 2523 Val = Val.ashr(Val.getBitWidth()-FromBits); 2524 return getConstant(Val, VT); 2525 } 2526 break; 2527 } 2528 case ISD::EXTRACT_VECTOR_ELT: 2529 // EXTRACT_VECTOR_ELT of an UNDEF is an UNDEF. 2530 if (N1.getOpcode() == ISD::UNDEF) 2531 return getUNDEF(VT); 2532 2533 // EXTRACT_VECTOR_ELT of CONCAT_VECTORS is often formed while lowering is 2534 // expanding copies of large vectors from registers. 2535 if (N2C && 2536 N1.getOpcode() == ISD::CONCAT_VECTORS && 2537 N1.getNumOperands() > 0) { 2538 unsigned Factor = 2539 N1.getOperand(0).getValueType().getVectorNumElements(); 2540 return getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, 2541 N1.getOperand(N2C->getZExtValue() / Factor), 2542 getConstant(N2C->getZExtValue() % Factor, 2543 N2.getValueType())); 2544 } 2545 2546 // EXTRACT_VECTOR_ELT of BUILD_VECTOR is often formed while lowering is 2547 // expanding large vector constants. 2548 if (N2C && N1.getOpcode() == ISD::BUILD_VECTOR) { 2549 SDValue Elt = N1.getOperand(N2C->getZExtValue()); 2550 if (Elt.getValueType() != VT) { 2551 // If the vector element type is not legal, the BUILD_VECTOR operands 2552 // are promoted and implicitly truncated. Make that explicit here. 2553 assert(VT.isInteger() && Elt.getValueType().isInteger() && 2554 VT.bitsLE(Elt.getValueType()) && 2555 "Bad type for BUILD_VECTOR operand"); 2556 Elt = getNode(ISD::TRUNCATE, DL, VT, Elt); 2557 } 2558 return Elt; 2559 } 2560 2561 // EXTRACT_VECTOR_ELT of INSERT_VECTOR_ELT is often formed when vector 2562 // operations are lowered to scalars. 2563 if (N1.getOpcode() == ISD::INSERT_VECTOR_ELT) { 2564 // If the indices are the same, return the inserted element. 2565 if (N1.getOperand(2) == N2) 2566 return N1.getOperand(1); 2567 // If the indices are known different, extract the element from 2568 // the original vector. 2569 else if (isa<ConstantSDNode>(N1.getOperand(2)) && 2570 isa<ConstantSDNode>(N2)) 2571 return getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, N1.getOperand(0), N2); 2572 } 2573 break; 2574 case ISD::EXTRACT_ELEMENT: 2575 assert(N2C && (unsigned)N2C->getZExtValue() < 2 && "Bad EXTRACT_ELEMENT!"); 2576 assert(!N1.getValueType().isVector() && !VT.isVector() && 2577 (N1.getValueType().isInteger() == VT.isInteger()) && 2578 "Wrong types for EXTRACT_ELEMENT!"); 2579 2580 // EXTRACT_ELEMENT of BUILD_PAIR is often formed while legalize is expanding 2581 // 64-bit integers into 32-bit parts. Instead of building the extract of 2582 // the BUILD_PAIR, only to have legalize rip it apart, just do it now. 2583 if (N1.getOpcode() == ISD::BUILD_PAIR) 2584 return N1.getOperand(N2C->getZExtValue()); 2585 2586 // EXTRACT_ELEMENT of a constant int is also very common. 2587 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) { 2588 unsigned ElementSize = VT.getSizeInBits(); 2589 unsigned Shift = ElementSize * N2C->getZExtValue(); 2590 APInt ShiftedVal = C->getAPIntValue().lshr(Shift); 2591 return getConstant(ShiftedVal.trunc(ElementSize), VT); 2592 } 2593 break; 2594 case ISD::EXTRACT_SUBVECTOR: 2595 if (N1.getValueType() == VT) // Trivial extraction. 2596 return N1; 2597 break; 2598 } 2599 2600 if (N1C) { 2601 if (N2C) { 2602 SDValue SV = FoldConstantArithmetic(Opcode, VT, N1C, N2C); 2603 if (SV.getNode()) return SV; 2604 } else { // Cannonicalize constant to RHS if commutative 2605 if (isCommutativeBinOp(Opcode)) { 2606 std::swap(N1C, N2C); 2607 std::swap(N1, N2); 2608 } 2609 } 2610 } 2611 2612 // Constant fold FP operations. 2613 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1.getNode()); 2614 ConstantFPSDNode *N2CFP = dyn_cast<ConstantFPSDNode>(N2.getNode()); 2615 if (N1CFP) { 2616 if (!N2CFP && isCommutativeBinOp(Opcode)) { 2617 // Cannonicalize constant to RHS if commutative 2618 std::swap(N1CFP, N2CFP); 2619 std::swap(N1, N2); 2620 } else if (N2CFP && VT != MVT::ppcf128) { 2621 APFloat V1 = N1CFP->getValueAPF(), V2 = N2CFP->getValueAPF(); 2622 APFloat::opStatus s; 2623 switch (Opcode) { 2624 case ISD::FADD: 2625 s = V1.add(V2, APFloat::rmNearestTiesToEven); 2626 if (s != APFloat::opInvalidOp) 2627 return getConstantFP(V1, VT); 2628 break; 2629 case ISD::FSUB: 2630 s = V1.subtract(V2, APFloat::rmNearestTiesToEven); 2631 if (s!=APFloat::opInvalidOp) 2632 return getConstantFP(V1, VT); 2633 break; 2634 case ISD::FMUL: 2635 s = V1.multiply(V2, APFloat::rmNearestTiesToEven); 2636 if (s!=APFloat::opInvalidOp) 2637 return getConstantFP(V1, VT); 2638 break; 2639 case ISD::FDIV: 2640 s = V1.divide(V2, APFloat::rmNearestTiesToEven); 2641 if (s!=APFloat::opInvalidOp && s!=APFloat::opDivByZero) 2642 return getConstantFP(V1, VT); 2643 break; 2644 case ISD::FREM : 2645 s = V1.mod(V2, APFloat::rmNearestTiesToEven); 2646 if (s!=APFloat::opInvalidOp && s!=APFloat::opDivByZero) 2647 return getConstantFP(V1, VT); 2648 break; 2649 case ISD::FCOPYSIGN: 2650 V1.copySign(V2); 2651 return getConstantFP(V1, VT); 2652 default: break; 2653 } 2654 } 2655 } 2656 2657 // Canonicalize an UNDEF to the RHS, even over a constant. 2658 if (N1.getOpcode() == ISD::UNDEF) { 2659 if (isCommutativeBinOp(Opcode)) { 2660 std::swap(N1, N2); 2661 } else { 2662 switch (Opcode) { 2663 case ISD::FP_ROUND_INREG: 2664 case ISD::SIGN_EXTEND_INREG: 2665 case ISD::SUB: 2666 case ISD::FSUB: 2667 case ISD::FDIV: 2668 case ISD::FREM: 2669 case ISD::SRA: 2670 return N1; // fold op(undef, arg2) -> undef 2671 case ISD::UDIV: 2672 case ISD::SDIV: 2673 case ISD::UREM: 2674 case ISD::SREM: 2675 case ISD::SRL: 2676 case ISD::SHL: 2677 if (!VT.isVector()) 2678 return getConstant(0, VT); // fold op(undef, arg2) -> 0 2679 // For vectors, we can't easily build an all zero vector, just return 2680 // the LHS. 2681 return N2; 2682 } 2683 } 2684 } 2685 2686 // Fold a bunch of operators when the RHS is undef. 2687 if (N2.getOpcode() == ISD::UNDEF) { 2688 switch (Opcode) { 2689 case ISD::XOR: 2690 if (N1.getOpcode() == ISD::UNDEF) 2691 // Handle undef ^ undef -> 0 special case. This is a common 2692 // idiom (misuse). 2693 return getConstant(0, VT); 2694 // fallthrough 2695 case ISD::ADD: 2696 case ISD::ADDC: 2697 case ISD::ADDE: 2698 case ISD::SUB: 2699 case ISD::FADD: 2700 case ISD::FSUB: 2701 case ISD::FMUL: 2702 case ISD::FDIV: 2703 case ISD::FREM: 2704 case ISD::UDIV: 2705 case ISD::SDIV: 2706 case ISD::UREM: 2707 case ISD::SREM: 2708 return N2; // fold op(arg1, undef) -> undef 2709 case ISD::MUL: 2710 case ISD::AND: 2711 case ISD::SRL: 2712 case ISD::SHL: 2713 if (!VT.isVector()) 2714 return getConstant(0, VT); // fold op(arg1, undef) -> 0 2715 // For vectors, we can't easily build an all zero vector, just return 2716 // the LHS. 2717 return N1; 2718 case ISD::OR: 2719 if (!VT.isVector()) 2720 return getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT); 2721 // For vectors, we can't easily build an all one vector, just return 2722 // the LHS. 2723 return N1; 2724 case ISD::SRA: 2725 return N1; 2726 } 2727 } 2728 2729 // Memoize this node if possible. 2730 SDNode *N; 2731 SDVTList VTs = getVTList(VT); 2732 if (VT != MVT::Flag) { 2733 SDValue Ops[] = { N1, N2 }; 2734 FoldingSetNodeID ID; 2735 AddNodeIDNode(ID, Opcode, VTs, Ops, 2); 2736 void *IP = 0; 2737 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2738 return SDValue(E, 0); 2739 N = NodeAllocator.Allocate<BinarySDNode>(); 2740 new (N) BinarySDNode(Opcode, DL, VTs, N1, N2); 2741 CSEMap.InsertNode(N, IP); 2742 } else { 2743 N = NodeAllocator.Allocate<BinarySDNode>(); 2744 new (N) BinarySDNode(Opcode, DL, VTs, N1, N2); 2745 } 2746 2747 AllNodes.push_back(N); 2748#ifndef NDEBUG 2749 VerifyNode(N); 2750#endif 2751 return SDValue(N, 0); 2752} 2753 2754SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, 2755 SDValue N1, SDValue N2, SDValue N3) { 2756 // Perform various simplifications. 2757 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 2758 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 2759 switch (Opcode) { 2760 case ISD::CONCAT_VECTORS: 2761 // A CONCAT_VECTOR with all operands BUILD_VECTOR can be simplified to 2762 // one big BUILD_VECTOR. 2763 if (N1.getOpcode() == ISD::BUILD_VECTOR && 2764 N2.getOpcode() == ISD::BUILD_VECTOR && 2765 N3.getOpcode() == ISD::BUILD_VECTOR) { 2766 SmallVector<SDValue, 16> Elts(N1.getNode()->op_begin(), N1.getNode()->op_end()); 2767 Elts.insert(Elts.end(), N2.getNode()->op_begin(), N2.getNode()->op_end()); 2768 Elts.insert(Elts.end(), N3.getNode()->op_begin(), N3.getNode()->op_end()); 2769 return getNode(ISD::BUILD_VECTOR, DL, VT, &Elts[0], Elts.size()); 2770 } 2771 break; 2772 case ISD::SETCC: { 2773 // Use FoldSetCC to simplify SETCC's. 2774 SDValue Simp = FoldSetCC(VT, N1, N2, cast<CondCodeSDNode>(N3)->get(), DL); 2775 if (Simp.getNode()) return Simp; 2776 break; 2777 } 2778 case ISD::SELECT: 2779 if (N1C) { 2780 if (N1C->getZExtValue()) 2781 return N2; // select true, X, Y -> X 2782 else 2783 return N3; // select false, X, Y -> Y 2784 } 2785 2786 if (N2 == N3) return N2; // select C, X, X -> X 2787 break; 2788 case ISD::BRCOND: 2789 if (N2C) { 2790 if (N2C->getZExtValue()) // Unconditional branch 2791 return getNode(ISD::BR, DL, MVT::Other, N1, N3); 2792 else 2793 return N1; // Never-taken branch 2794 } 2795 break; 2796 case ISD::VECTOR_SHUFFLE: 2797 assert(N1.getValueType() == N2.getValueType() && 2798 N1.getValueType().isVector() && 2799 VT.isVector() && N3.getValueType().isVector() && 2800 N3.getOpcode() == ISD::BUILD_VECTOR && 2801 VT.getVectorNumElements() == N3.getNumOperands() && 2802 "Illegal VECTOR_SHUFFLE node!"); 2803 break; 2804 case ISD::BIT_CONVERT: 2805 // Fold bit_convert nodes from a type to themselves. 2806 if (N1.getValueType() == VT) 2807 return N1; 2808 break; 2809 } 2810 2811 // Memoize node if it doesn't produce a flag. 2812 SDNode *N; 2813 SDVTList VTs = getVTList(VT); 2814 if (VT != MVT::Flag) { 2815 SDValue Ops[] = { N1, N2, N3 }; 2816 FoldingSetNodeID ID; 2817 AddNodeIDNode(ID, Opcode, VTs, Ops, 3); 2818 void *IP = 0; 2819 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2820 return SDValue(E, 0); 2821 N = NodeAllocator.Allocate<TernarySDNode>(); 2822 new (N) TernarySDNode(Opcode, DL, VTs, N1, N2, N3); 2823 CSEMap.InsertNode(N, IP); 2824 } else { 2825 N = NodeAllocator.Allocate<TernarySDNode>(); 2826 new (N) TernarySDNode(Opcode, DL, VTs, N1, N2, N3); 2827 } 2828 AllNodes.push_back(N); 2829#ifndef NDEBUG 2830 VerifyNode(N); 2831#endif 2832 return SDValue(N, 0); 2833} 2834 2835SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, 2836 SDValue N1, SDValue N2, SDValue N3, 2837 SDValue N4) { 2838 SDValue Ops[] = { N1, N2, N3, N4 }; 2839 return getNode(Opcode, DL, VT, Ops, 4); 2840} 2841 2842SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, 2843 SDValue N1, SDValue N2, SDValue N3, 2844 SDValue N4, SDValue N5) { 2845 SDValue Ops[] = { N1, N2, N3, N4, N5 }; 2846 return getNode(Opcode, DL, VT, Ops, 5); 2847} 2848 2849/// getMemsetValue - Vectorized representation of the memset value 2850/// operand. 2851static SDValue getMemsetValue(SDValue Value, MVT VT, SelectionDAG &DAG, 2852 DebugLoc dl) { 2853 unsigned NumBits = VT.isVector() ? 2854 VT.getVectorElementType().getSizeInBits() : VT.getSizeInBits(); 2855 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) { 2856 APInt Val = APInt(NumBits, C->getZExtValue() & 255); 2857 unsigned Shift = 8; 2858 for (unsigned i = NumBits; i > 8; i >>= 1) { 2859 Val = (Val << Shift) | Val; 2860 Shift <<= 1; 2861 } 2862 if (VT.isInteger()) 2863 return DAG.getConstant(Val, VT); 2864 return DAG.getConstantFP(APFloat(Val), VT); 2865 } 2866 2867 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 2868 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Value); 2869 unsigned Shift = 8; 2870 for (unsigned i = NumBits; i > 8; i >>= 1) { 2871 Value = DAG.getNode(ISD::OR, dl, VT, 2872 DAG.getNode(ISD::SHL, dl, VT, Value, 2873 DAG.getConstant(Shift, 2874 TLI.getShiftAmountTy())), 2875 Value); 2876 Shift <<= 1; 2877 } 2878 2879 return Value; 2880} 2881 2882/// getMemsetStringVal - Similar to getMemsetValue. Except this is only 2883/// used when a memcpy is turned into a memset when the source is a constant 2884/// string ptr. 2885static SDValue getMemsetStringVal(MVT VT, DebugLoc dl, SelectionDAG &DAG, 2886 const TargetLowering &TLI, 2887 std::string &Str, unsigned Offset) { 2888 // Handle vector with all elements zero. 2889 if (Str.empty()) { 2890 if (VT.isInteger()) 2891 return DAG.getConstant(0, VT); 2892 unsigned NumElts = VT.getVectorNumElements(); 2893 MVT EltVT = (VT.getVectorElementType() == MVT::f32) ? MVT::i32 : MVT::i64; 2894 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 2895 DAG.getConstant(0, MVT::getVectorVT(EltVT, NumElts))); 2896 } 2897 2898 assert(!VT.isVector() && "Can't handle vector type here!"); 2899 unsigned NumBits = VT.getSizeInBits(); 2900 unsigned MSB = NumBits / 8; 2901 uint64_t Val = 0; 2902 if (TLI.isLittleEndian()) 2903 Offset = Offset + MSB - 1; 2904 for (unsigned i = 0; i != MSB; ++i) { 2905 Val = (Val << 8) | (unsigned char)Str[Offset]; 2906 Offset += TLI.isLittleEndian() ? -1 : 1; 2907 } 2908 return DAG.getConstant(Val, VT); 2909} 2910 2911/// getMemBasePlusOffset - Returns base and offset node for the 2912/// 2913static SDValue getMemBasePlusOffset(SDValue Base, unsigned Offset, 2914 SelectionDAG &DAG) { 2915 MVT VT = Base.getValueType(); 2916 return DAG.getNode(ISD::ADD, Base.getDebugLoc(), 2917 VT, Base, DAG.getConstant(Offset, VT)); 2918} 2919 2920/// isMemSrcFromString - Returns true if memcpy source is a string constant. 2921/// 2922static bool isMemSrcFromString(SDValue Src, std::string &Str) { 2923 unsigned SrcDelta = 0; 2924 GlobalAddressSDNode *G = NULL; 2925 if (Src.getOpcode() == ISD::GlobalAddress) 2926 G = cast<GlobalAddressSDNode>(Src); 2927 else if (Src.getOpcode() == ISD::ADD && 2928 Src.getOperand(0).getOpcode() == ISD::GlobalAddress && 2929 Src.getOperand(1).getOpcode() == ISD::Constant) { 2930 G = cast<GlobalAddressSDNode>(Src.getOperand(0)); 2931 SrcDelta = cast<ConstantSDNode>(Src.getOperand(1))->getZExtValue(); 2932 } 2933 if (!G) 2934 return false; 2935 2936 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal()); 2937 if (GV && GetConstantStringInfo(GV, Str, SrcDelta, false)) 2938 return true; 2939 2940 return false; 2941} 2942 2943/// MeetsMaxMemopRequirement - Determines if the number of memory ops required 2944/// to replace the memset / memcpy is below the threshold. It also returns the 2945/// types of the sequence of memory ops to perform memset / memcpy. 2946static 2947bool MeetsMaxMemopRequirement(std::vector<MVT> &MemOps, 2948 SDValue Dst, SDValue Src, 2949 unsigned Limit, uint64_t Size, unsigned &Align, 2950 std::string &Str, bool &isSrcStr, 2951 SelectionDAG &DAG, 2952 const TargetLowering &TLI) { 2953 isSrcStr = isMemSrcFromString(Src, Str); 2954 bool isSrcConst = isa<ConstantSDNode>(Src); 2955 bool AllowUnalign = TLI.allowsUnalignedMemoryAccesses(); 2956 MVT VT = TLI.getOptimalMemOpType(Size, Align, isSrcConst, isSrcStr); 2957 if (VT != MVT::iAny) { 2958 unsigned NewAlign = (unsigned) 2959 TLI.getTargetData()->getABITypeAlignment(VT.getTypeForMVT()); 2960 // If source is a string constant, this will require an unaligned load. 2961 if (NewAlign > Align && (isSrcConst || AllowUnalign)) { 2962 if (Dst.getOpcode() != ISD::FrameIndex) { 2963 // Can't change destination alignment. It requires a unaligned store. 2964 if (AllowUnalign) 2965 VT = MVT::iAny; 2966 } else { 2967 int FI = cast<FrameIndexSDNode>(Dst)->getIndex(); 2968 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 2969 if (MFI->isFixedObjectIndex(FI)) { 2970 // Can't change destination alignment. It requires a unaligned store. 2971 if (AllowUnalign) 2972 VT = MVT::iAny; 2973 } else { 2974 // Give the stack frame object a larger alignment if needed. 2975 if (MFI->getObjectAlignment(FI) < NewAlign) 2976 MFI->setObjectAlignment(FI, NewAlign); 2977 Align = NewAlign; 2978 } 2979 } 2980 } 2981 } 2982 2983 if (VT == MVT::iAny) { 2984 if (AllowUnalign) { 2985 VT = MVT::i64; 2986 } else { 2987 switch (Align & 7) { 2988 case 0: VT = MVT::i64; break; 2989 case 4: VT = MVT::i32; break; 2990 case 2: VT = MVT::i16; break; 2991 default: VT = MVT::i8; break; 2992 } 2993 } 2994 2995 MVT LVT = MVT::i64; 2996 while (!TLI.isTypeLegal(LVT)) 2997 LVT = (MVT::SimpleValueType)(LVT.getSimpleVT() - 1); 2998 assert(LVT.isInteger()); 2999 3000 if (VT.bitsGT(LVT)) 3001 VT = LVT; 3002 } 3003 3004 unsigned NumMemOps = 0; 3005 while (Size != 0) { 3006 unsigned VTSize = VT.getSizeInBits() / 8; 3007 while (VTSize > Size) { 3008 // For now, only use non-vector load / store's for the left-over pieces. 3009 if (VT.isVector()) { 3010 VT = MVT::i64; 3011 while (!TLI.isTypeLegal(VT)) 3012 VT = (MVT::SimpleValueType)(VT.getSimpleVT() - 1); 3013 VTSize = VT.getSizeInBits() / 8; 3014 } else { 3015 VT = (MVT::SimpleValueType)(VT.getSimpleVT() - 1); 3016 VTSize >>= 1; 3017 } 3018 } 3019 3020 if (++NumMemOps > Limit) 3021 return false; 3022 MemOps.push_back(VT); 3023 Size -= VTSize; 3024 } 3025 3026 return true; 3027} 3028 3029static SDValue getMemcpyLoadsAndStores(SelectionDAG &DAG, DebugLoc dl, 3030 SDValue Chain, SDValue Dst, 3031 SDValue Src, uint64_t Size, 3032 unsigned Align, bool AlwaysInline, 3033 const Value *DstSV, uint64_t DstSVOff, 3034 const Value *SrcSV, uint64_t SrcSVOff){ 3035 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 3036 3037 // Expand memcpy to a series of load and store ops if the size operand falls 3038 // below a certain threshold. 3039 std::vector<MVT> MemOps; 3040 uint64_t Limit = -1ULL; 3041 if (!AlwaysInline) 3042 Limit = TLI.getMaxStoresPerMemcpy(); 3043 unsigned DstAlign = Align; // Destination alignment can change. 3044 std::string Str; 3045 bool CopyFromStr; 3046 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, Limit, Size, DstAlign, 3047 Str, CopyFromStr, DAG, TLI)) 3048 return SDValue(); 3049 3050 3051 bool isZeroStr = CopyFromStr && Str.empty(); 3052 SmallVector<SDValue, 8> OutChains; 3053 unsigned NumMemOps = MemOps.size(); 3054 uint64_t SrcOff = 0, DstOff = 0; 3055 for (unsigned i = 0; i < NumMemOps; i++) { 3056 MVT VT = MemOps[i]; 3057 unsigned VTSize = VT.getSizeInBits() / 8; 3058 SDValue Value, Store; 3059 3060 if (CopyFromStr && (isZeroStr || !VT.isVector())) { 3061 // It's unlikely a store of a vector immediate can be done in a single 3062 // instruction. It would require a load from a constantpool first. 3063 // We also handle store a vector with all zero's. 3064 // FIXME: Handle other cases where store of vector immediate is done in 3065 // a single instruction. 3066 Value = getMemsetStringVal(VT, dl, DAG, TLI, Str, SrcOff); 3067 Store = DAG.getStore(Chain, dl, Value, 3068 getMemBasePlusOffset(Dst, DstOff, DAG), 3069 DstSV, DstSVOff + DstOff, false, DstAlign); 3070 } else { 3071 Value = DAG.getLoad(VT, dl, Chain, 3072 getMemBasePlusOffset(Src, SrcOff, DAG), 3073 SrcSV, SrcSVOff + SrcOff, false, Align); 3074 Store = DAG.getStore(Chain, dl, Value, 3075 getMemBasePlusOffset(Dst, DstOff, DAG), 3076 DstSV, DstSVOff + DstOff, false, DstAlign); 3077 } 3078 OutChains.push_back(Store); 3079 SrcOff += VTSize; 3080 DstOff += VTSize; 3081 } 3082 3083 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3084 &OutChains[0], OutChains.size()); 3085} 3086 3087static SDValue getMemmoveLoadsAndStores(SelectionDAG &DAG, DebugLoc dl, 3088 SDValue Chain, SDValue Dst, 3089 SDValue Src, uint64_t Size, 3090 unsigned Align, bool AlwaysInline, 3091 const Value *DstSV, uint64_t DstSVOff, 3092 const Value *SrcSV, uint64_t SrcSVOff){ 3093 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 3094 3095 // Expand memmove to a series of load and store ops if the size operand falls 3096 // below a certain threshold. 3097 std::vector<MVT> MemOps; 3098 uint64_t Limit = -1ULL; 3099 if (!AlwaysInline) 3100 Limit = TLI.getMaxStoresPerMemmove(); 3101 unsigned DstAlign = Align; // Destination alignment can change. 3102 std::string Str; 3103 bool CopyFromStr; 3104 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, Limit, Size, DstAlign, 3105 Str, CopyFromStr, DAG, TLI)) 3106 return SDValue(); 3107 3108 uint64_t SrcOff = 0, DstOff = 0; 3109 3110 SmallVector<SDValue, 8> LoadValues; 3111 SmallVector<SDValue, 8> LoadChains; 3112 SmallVector<SDValue, 8> OutChains; 3113 unsigned NumMemOps = MemOps.size(); 3114 for (unsigned i = 0; i < NumMemOps; i++) { 3115 MVT VT = MemOps[i]; 3116 unsigned VTSize = VT.getSizeInBits() / 8; 3117 SDValue Value, Store; 3118 3119 Value = DAG.getLoad(VT, dl, Chain, 3120 getMemBasePlusOffset(Src, SrcOff, DAG), 3121 SrcSV, SrcSVOff + SrcOff, false, Align); 3122 LoadValues.push_back(Value); 3123 LoadChains.push_back(Value.getValue(1)); 3124 SrcOff += VTSize; 3125 } 3126 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3127 &LoadChains[0], LoadChains.size()); 3128 OutChains.clear(); 3129 for (unsigned i = 0; i < NumMemOps; i++) { 3130 MVT VT = MemOps[i]; 3131 unsigned VTSize = VT.getSizeInBits() / 8; 3132 SDValue Value, Store; 3133 3134 Store = DAG.getStore(Chain, dl, LoadValues[i], 3135 getMemBasePlusOffset(Dst, DstOff, DAG), 3136 DstSV, DstSVOff + DstOff, false, DstAlign); 3137 OutChains.push_back(Store); 3138 DstOff += VTSize; 3139 } 3140 3141 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3142 &OutChains[0], OutChains.size()); 3143} 3144 3145static SDValue getMemsetStores(SelectionDAG &DAG, DebugLoc dl, 3146 SDValue Chain, SDValue Dst, 3147 SDValue Src, uint64_t Size, 3148 unsigned Align, 3149 const Value *DstSV, uint64_t DstSVOff) { 3150 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 3151 3152 // Expand memset to a series of load/store ops if the size operand 3153 // falls below a certain threshold. 3154 std::vector<MVT> MemOps; 3155 std::string Str; 3156 bool CopyFromStr; 3157 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, TLI.getMaxStoresPerMemset(), 3158 Size, Align, Str, CopyFromStr, DAG, TLI)) 3159 return SDValue(); 3160 3161 SmallVector<SDValue, 8> OutChains; 3162 uint64_t DstOff = 0; 3163 3164 unsigned NumMemOps = MemOps.size(); 3165 for (unsigned i = 0; i < NumMemOps; i++) { 3166 MVT VT = MemOps[i]; 3167 unsigned VTSize = VT.getSizeInBits() / 8; 3168 SDValue Value = getMemsetValue(Src, VT, DAG, dl); 3169 SDValue Store = DAG.getStore(Chain, dl, Value, 3170 getMemBasePlusOffset(Dst, DstOff, DAG), 3171 DstSV, DstSVOff + DstOff); 3172 OutChains.push_back(Store); 3173 DstOff += VTSize; 3174 } 3175 3176 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3177 &OutChains[0], OutChains.size()); 3178} 3179 3180SDValue SelectionDAG::getMemcpy(SDValue Chain, DebugLoc dl, SDValue Dst, 3181 SDValue Src, SDValue Size, 3182 unsigned Align, bool AlwaysInline, 3183 const Value *DstSV, uint64_t DstSVOff, 3184 const Value *SrcSV, uint64_t SrcSVOff) { 3185 3186 // Check to see if we should lower the memcpy to loads and stores first. 3187 // For cases within the target-specified limits, this is the best choice. 3188 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 3189 if (ConstantSize) { 3190 // Memcpy with size zero? Just return the original chain. 3191 if (ConstantSize->isNullValue()) 3192 return Chain; 3193 3194 SDValue Result = 3195 getMemcpyLoadsAndStores(*this, dl, Chain, Dst, Src, 3196 ConstantSize->getZExtValue(), 3197 Align, false, DstSV, DstSVOff, SrcSV, SrcSVOff); 3198 if (Result.getNode()) 3199 return Result; 3200 } 3201 3202 // Then check to see if we should lower the memcpy with target-specific 3203 // code. If the target chooses to do this, this is the next best. 3204 SDValue Result = 3205 TLI.EmitTargetCodeForMemcpy(*this, dl, Chain, Dst, Src, Size, Align, 3206 AlwaysInline, 3207 DstSV, DstSVOff, SrcSV, SrcSVOff); 3208 if (Result.getNode()) 3209 return Result; 3210 3211 // If we really need inline code and the target declined to provide it, 3212 // use a (potentially long) sequence of loads and stores. 3213 if (AlwaysInline) { 3214 assert(ConstantSize && "AlwaysInline requires a constant size!"); 3215 return getMemcpyLoadsAndStores(*this, dl, Chain, Dst, Src, 3216 ConstantSize->getZExtValue(), Align, true, 3217 DstSV, DstSVOff, SrcSV, SrcSVOff); 3218 } 3219 3220 // Emit a library call. 3221 TargetLowering::ArgListTy Args; 3222 TargetLowering::ArgListEntry Entry; 3223 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 3224 Entry.Node = Dst; Args.push_back(Entry); 3225 Entry.Node = Src; Args.push_back(Entry); 3226 Entry.Node = Size; Args.push_back(Entry); 3227 // FIXME: pass in DebugLoc 3228 std::pair<SDValue,SDValue> CallResult = 3229 TLI.LowerCallTo(Chain, Type::VoidTy, 3230 false, false, false, false, CallingConv::C, false, 3231 getExternalSymbol("memcpy", TLI.getPointerTy()), 3232 Args, *this, dl); 3233 return CallResult.second; 3234} 3235 3236SDValue SelectionDAG::getMemmove(SDValue Chain, DebugLoc dl, SDValue Dst, 3237 SDValue Src, SDValue Size, 3238 unsigned Align, 3239 const Value *DstSV, uint64_t DstSVOff, 3240 const Value *SrcSV, uint64_t SrcSVOff) { 3241 3242 // Check to see if we should lower the memmove to loads and stores first. 3243 // For cases within the target-specified limits, this is the best choice. 3244 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 3245 if (ConstantSize) { 3246 // Memmove with size zero? Just return the original chain. 3247 if (ConstantSize->isNullValue()) 3248 return Chain; 3249 3250 SDValue Result = 3251 getMemmoveLoadsAndStores(*this, dl, Chain, Dst, Src, 3252 ConstantSize->getZExtValue(), 3253 Align, false, DstSV, DstSVOff, SrcSV, SrcSVOff); 3254 if (Result.getNode()) 3255 return Result; 3256 } 3257 3258 // Then check to see if we should lower the memmove with target-specific 3259 // code. If the target chooses to do this, this is the next best. 3260 SDValue Result = 3261 TLI.EmitTargetCodeForMemmove(*this, dl, Chain, Dst, Src, Size, Align, 3262 DstSV, DstSVOff, SrcSV, SrcSVOff); 3263 if (Result.getNode()) 3264 return Result; 3265 3266 // Emit a library call. 3267 TargetLowering::ArgListTy Args; 3268 TargetLowering::ArgListEntry Entry; 3269 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 3270 Entry.Node = Dst; Args.push_back(Entry); 3271 Entry.Node = Src; Args.push_back(Entry); 3272 Entry.Node = Size; Args.push_back(Entry); 3273 // FIXME: pass in DebugLoc 3274 std::pair<SDValue,SDValue> CallResult = 3275 TLI.LowerCallTo(Chain, Type::VoidTy, 3276 false, false, false, false, CallingConv::C, false, 3277 getExternalSymbol("memmove", TLI.getPointerTy()), 3278 Args, *this, dl); 3279 return CallResult.second; 3280} 3281 3282SDValue SelectionDAG::getMemset(SDValue Chain, DebugLoc dl, SDValue Dst, 3283 SDValue Src, SDValue Size, 3284 unsigned Align, 3285 const Value *DstSV, uint64_t DstSVOff) { 3286 3287 // Check to see if we should lower the memset to stores first. 3288 // For cases within the target-specified limits, this is the best choice. 3289 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 3290 if (ConstantSize) { 3291 // Memset with size zero? Just return the original chain. 3292 if (ConstantSize->isNullValue()) 3293 return Chain; 3294 3295 SDValue Result = 3296 getMemsetStores(*this, dl, Chain, Dst, Src, ConstantSize->getZExtValue(), 3297 Align, DstSV, DstSVOff); 3298 if (Result.getNode()) 3299 return Result; 3300 } 3301 3302 // Then check to see if we should lower the memset with target-specific 3303 // code. If the target chooses to do this, this is the next best. 3304 SDValue Result = 3305 TLI.EmitTargetCodeForMemset(*this, dl, Chain, Dst, Src, Size, Align, 3306 DstSV, DstSVOff); 3307 if (Result.getNode()) 3308 return Result; 3309 3310 // Emit a library call. 3311 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType(); 3312 TargetLowering::ArgListTy Args; 3313 TargetLowering::ArgListEntry Entry; 3314 Entry.Node = Dst; Entry.Ty = IntPtrTy; 3315 Args.push_back(Entry); 3316 // Extend or truncate the argument to be an i32 value for the call. 3317 if (Src.getValueType().bitsGT(MVT::i32)) 3318 Src = getNode(ISD::TRUNCATE, dl, MVT::i32, Src); 3319 else 3320 Src = getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Src); 3321 Entry.Node = Src; Entry.Ty = Type::Int32Ty; Entry.isSExt = true; 3322 Args.push_back(Entry); 3323 Entry.Node = Size; Entry.Ty = IntPtrTy; Entry.isSExt = false; 3324 Args.push_back(Entry); 3325 // FIXME: pass in DebugLoc 3326 std::pair<SDValue,SDValue> CallResult = 3327 TLI.LowerCallTo(Chain, Type::VoidTy, 3328 false, false, false, false, CallingConv::C, false, 3329 getExternalSymbol("memset", TLI.getPointerTy()), 3330 Args, *this, dl); 3331 return CallResult.second; 3332} 3333 3334SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, MVT MemVT, 3335 SDValue Chain, 3336 SDValue Ptr, SDValue Cmp, 3337 SDValue Swp, const Value* PtrVal, 3338 unsigned Alignment) { 3339 assert(Opcode == ISD::ATOMIC_CMP_SWAP && "Invalid Atomic Op"); 3340 assert(Cmp.getValueType() == Swp.getValueType() && "Invalid Atomic Op Types"); 3341 3342 MVT VT = Cmp.getValueType(); 3343 3344 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3345 Alignment = getMVTAlignment(MemVT); 3346 3347 SDVTList VTs = getVTList(VT, MVT::Other); 3348 FoldingSetNodeID ID; 3349 ID.AddInteger(MemVT.getRawBits()); 3350 SDValue Ops[] = {Chain, Ptr, Cmp, Swp}; 3351 AddNodeIDNode(ID, Opcode, VTs, Ops, 4); 3352 void* IP = 0; 3353 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3354 return SDValue(E, 0); 3355 SDNode* N = NodeAllocator.Allocate<AtomicSDNode>(); 3356 new (N) AtomicSDNode(Opcode, dl, VTs, MemVT, 3357 Chain, Ptr, Cmp, Swp, PtrVal, Alignment); 3358 CSEMap.InsertNode(N, IP); 3359 AllNodes.push_back(N); 3360 return SDValue(N, 0); 3361} 3362 3363SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, MVT MemVT, 3364 SDValue Chain, 3365 SDValue Ptr, SDValue Val, 3366 const Value* PtrVal, 3367 unsigned Alignment) { 3368 assert((Opcode == ISD::ATOMIC_LOAD_ADD || 3369 Opcode == ISD::ATOMIC_LOAD_SUB || 3370 Opcode == ISD::ATOMIC_LOAD_AND || 3371 Opcode == ISD::ATOMIC_LOAD_OR || 3372 Opcode == ISD::ATOMIC_LOAD_XOR || 3373 Opcode == ISD::ATOMIC_LOAD_NAND || 3374 Opcode == ISD::ATOMIC_LOAD_MIN || 3375 Opcode == ISD::ATOMIC_LOAD_MAX || 3376 Opcode == ISD::ATOMIC_LOAD_UMIN || 3377 Opcode == ISD::ATOMIC_LOAD_UMAX || 3378 Opcode == ISD::ATOMIC_SWAP) && 3379 "Invalid Atomic Op"); 3380 3381 MVT VT = Val.getValueType(); 3382 3383 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3384 Alignment = getMVTAlignment(MemVT); 3385 3386 SDVTList VTs = getVTList(VT, MVT::Other); 3387 FoldingSetNodeID ID; 3388 ID.AddInteger(MemVT.getRawBits()); 3389 SDValue Ops[] = {Chain, Ptr, Val}; 3390 AddNodeIDNode(ID, Opcode, VTs, Ops, 3); 3391 void* IP = 0; 3392 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3393 return SDValue(E, 0); 3394 SDNode* N = NodeAllocator.Allocate<AtomicSDNode>(); 3395 new (N) AtomicSDNode(Opcode, dl, VTs, MemVT, 3396 Chain, Ptr, Val, PtrVal, Alignment); 3397 CSEMap.InsertNode(N, IP); 3398 AllNodes.push_back(N); 3399 return SDValue(N, 0); 3400} 3401 3402/// getMergeValues - Create a MERGE_VALUES node from the given operands. 3403/// Allowed to return something different (and simpler) if Simplify is true. 3404SDValue SelectionDAG::getMergeValues(const SDValue *Ops, unsigned NumOps, 3405 DebugLoc dl) { 3406 if (NumOps == 1) 3407 return Ops[0]; 3408 3409 SmallVector<MVT, 4> VTs; 3410 VTs.reserve(NumOps); 3411 for (unsigned i = 0; i < NumOps; ++i) 3412 VTs.push_back(Ops[i].getValueType()); 3413 return getNode(ISD::MERGE_VALUES, dl, getVTList(&VTs[0], NumOps), 3414 Ops, NumOps); 3415} 3416 3417SDValue 3418SelectionDAG::getMemIntrinsicNode(unsigned Opcode, DebugLoc dl, 3419 const MVT *VTs, unsigned NumVTs, 3420 const SDValue *Ops, unsigned NumOps, 3421 MVT MemVT, const Value *srcValue, int SVOff, 3422 unsigned Align, bool Vol, 3423 bool ReadMem, bool WriteMem) { 3424 return getMemIntrinsicNode(Opcode, dl, makeVTList(VTs, NumVTs), Ops, NumOps, 3425 MemVT, srcValue, SVOff, Align, Vol, 3426 ReadMem, WriteMem); 3427} 3428 3429SDValue 3430SelectionDAG::getMemIntrinsicNode(unsigned Opcode, DebugLoc dl, SDVTList VTList, 3431 const SDValue *Ops, unsigned NumOps, 3432 MVT MemVT, const Value *srcValue, int SVOff, 3433 unsigned Align, bool Vol, 3434 bool ReadMem, bool WriteMem) { 3435 // Memoize the node unless it returns a flag. 3436 MemIntrinsicSDNode *N; 3437 if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) { 3438 FoldingSetNodeID ID; 3439 AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps); 3440 void *IP = 0; 3441 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3442 return SDValue(E, 0); 3443 3444 N = NodeAllocator.Allocate<MemIntrinsicSDNode>(); 3445 new (N) MemIntrinsicSDNode(Opcode, dl, VTList, Ops, NumOps, MemVT, 3446 srcValue, SVOff, Align, Vol, ReadMem, WriteMem); 3447 CSEMap.InsertNode(N, IP); 3448 } else { 3449 N = NodeAllocator.Allocate<MemIntrinsicSDNode>(); 3450 new (N) MemIntrinsicSDNode(Opcode, dl, VTList, Ops, NumOps, MemVT, 3451 srcValue, SVOff, Align, Vol, ReadMem, WriteMem); 3452 } 3453 AllNodes.push_back(N); 3454 return SDValue(N, 0); 3455} 3456 3457SDValue 3458SelectionDAG::getCall(unsigned CallingConv, DebugLoc dl, bool IsVarArgs, 3459 bool IsTailCall, bool IsInreg, SDVTList VTs, 3460 const SDValue *Operands, unsigned NumOperands) { 3461 // Do not include isTailCall in the folding set profile. 3462 FoldingSetNodeID ID; 3463 AddNodeIDNode(ID, ISD::CALL, VTs, Operands, NumOperands); 3464 ID.AddInteger(CallingConv); 3465 ID.AddInteger(IsVarArgs); 3466 void *IP = 0; 3467 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) { 3468 // Instead of including isTailCall in the folding set, we just 3469 // set the flag of the existing node. 3470 if (!IsTailCall) 3471 cast<CallSDNode>(E)->setNotTailCall(); 3472 return SDValue(E, 0); 3473 } 3474 SDNode *N = NodeAllocator.Allocate<CallSDNode>(); 3475 new (N) CallSDNode(CallingConv, dl, IsVarArgs, IsTailCall, IsInreg, 3476 VTs, Operands, NumOperands); 3477 CSEMap.InsertNode(N, IP); 3478 AllNodes.push_back(N); 3479 return SDValue(N, 0); 3480} 3481 3482SDValue 3483SelectionDAG::getLoad(ISD::MemIndexedMode AM, DebugLoc dl, 3484 ISD::LoadExtType ExtType, MVT VT, SDValue Chain, 3485 SDValue Ptr, SDValue Offset, 3486 const Value *SV, int SVOffset, MVT EVT, 3487 bool isVolatile, unsigned Alignment) { 3488 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3489 Alignment = getMVTAlignment(VT); 3490 3491 if (VT == EVT) { 3492 ExtType = ISD::NON_EXTLOAD; 3493 } else if (ExtType == ISD::NON_EXTLOAD) { 3494 assert(VT == EVT && "Non-extending load from different memory type!"); 3495 } else { 3496 // Extending load. 3497 if (VT.isVector()) 3498 assert(EVT.getVectorNumElements() == VT.getVectorNumElements() && 3499 "Invalid vector extload!"); 3500 else 3501 assert(EVT.bitsLT(VT) && 3502 "Should only be an extending load, not truncating!"); 3503 assert((ExtType == ISD::EXTLOAD || VT.isInteger()) && 3504 "Cannot sign/zero extend a FP/Vector load!"); 3505 assert(VT.isInteger() == EVT.isInteger() && 3506 "Cannot convert from FP to Int or Int -> FP!"); 3507 } 3508 3509 bool Indexed = AM != ISD::UNINDEXED; 3510 assert((Indexed || Offset.getOpcode() == ISD::UNDEF) && 3511 "Unindexed load with an offset!"); 3512 3513 SDVTList VTs = Indexed ? 3514 getVTList(VT, Ptr.getValueType(), MVT::Other) : getVTList(VT, MVT::Other); 3515 SDValue Ops[] = { Chain, Ptr, Offset }; 3516 FoldingSetNodeID ID; 3517 AddNodeIDNode(ID, ISD::LOAD, VTs, Ops, 3); 3518 ID.AddInteger(EVT.getRawBits()); 3519 ID.AddInteger(encodeMemSDNodeFlags(ExtType, AM, isVolatile, Alignment)); 3520 void *IP = 0; 3521 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3522 return SDValue(E, 0); 3523 SDNode *N = NodeAllocator.Allocate<LoadSDNode>(); 3524 new (N) LoadSDNode(Ops, dl, VTs, AM, ExtType, EVT, SV, SVOffset, 3525 Alignment, isVolatile); 3526 CSEMap.InsertNode(N, IP); 3527 AllNodes.push_back(N); 3528 return SDValue(N, 0); 3529} 3530 3531SDValue SelectionDAG::getLoad(MVT VT, DebugLoc dl, 3532 SDValue Chain, SDValue Ptr, 3533 const Value *SV, int SVOffset, 3534 bool isVolatile, unsigned Alignment) { 3535 SDValue Undef = getUNDEF(Ptr.getValueType()); 3536 return getLoad(ISD::UNINDEXED, dl, ISD::NON_EXTLOAD, VT, Chain, Ptr, Undef, 3537 SV, SVOffset, VT, isVolatile, Alignment); 3538} 3539 3540SDValue SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, DebugLoc dl, MVT VT, 3541 SDValue Chain, SDValue Ptr, 3542 const Value *SV, 3543 int SVOffset, MVT EVT, 3544 bool isVolatile, unsigned Alignment) { 3545 SDValue Undef = getUNDEF(Ptr.getValueType()); 3546 return getLoad(ISD::UNINDEXED, dl, ExtType, VT, Chain, Ptr, Undef, 3547 SV, SVOffset, EVT, isVolatile, Alignment); 3548} 3549 3550SDValue 3551SelectionDAG::getIndexedLoad(SDValue OrigLoad, DebugLoc dl, SDValue Base, 3552 SDValue Offset, ISD::MemIndexedMode AM) { 3553 LoadSDNode *LD = cast<LoadSDNode>(OrigLoad); 3554 assert(LD->getOffset().getOpcode() == ISD::UNDEF && 3555 "Load is already a indexed load!"); 3556 return getLoad(AM, dl, LD->getExtensionType(), OrigLoad.getValueType(), 3557 LD->getChain(), Base, Offset, LD->getSrcValue(), 3558 LD->getSrcValueOffset(), LD->getMemoryVT(), 3559 LD->isVolatile(), LD->getAlignment()); 3560} 3561 3562SDValue SelectionDAG::getStore(SDValue Chain, DebugLoc dl, SDValue Val, 3563 SDValue Ptr, const Value *SV, int SVOffset, 3564 bool isVolatile, unsigned Alignment) { 3565 MVT VT = Val.getValueType(); 3566 3567 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3568 Alignment = getMVTAlignment(VT); 3569 3570 SDVTList VTs = getVTList(MVT::Other); 3571 SDValue Undef = getUNDEF(Ptr.getValueType()); 3572 SDValue Ops[] = { Chain, Val, Ptr, Undef }; 3573 FoldingSetNodeID ID; 3574 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); 3575 ID.AddInteger(VT.getRawBits()); 3576 ID.AddInteger(encodeMemSDNodeFlags(false, ISD::UNINDEXED, 3577 isVolatile, Alignment)); 3578 void *IP = 0; 3579 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3580 return SDValue(E, 0); 3581 SDNode *N = NodeAllocator.Allocate<StoreSDNode>(); 3582 new (N) StoreSDNode(Ops, dl, VTs, ISD::UNINDEXED, false, 3583 VT, SV, SVOffset, Alignment, isVolatile); 3584 CSEMap.InsertNode(N, IP); 3585 AllNodes.push_back(N); 3586 return SDValue(N, 0); 3587} 3588 3589SDValue SelectionDAG::getTruncStore(SDValue Chain, DebugLoc dl, SDValue Val, 3590 SDValue Ptr, const Value *SV, 3591 int SVOffset, MVT SVT, 3592 bool isVolatile, unsigned Alignment) { 3593 MVT VT = Val.getValueType(); 3594 3595 if (VT == SVT) 3596 return getStore(Chain, dl, Val, Ptr, SV, SVOffset, isVolatile, Alignment); 3597 3598 assert(VT.bitsGT(SVT) && "Not a truncation?"); 3599 assert(VT.isInteger() == SVT.isInteger() && 3600 "Can't do FP-INT conversion!"); 3601 3602 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3603 Alignment = getMVTAlignment(VT); 3604 3605 SDVTList VTs = getVTList(MVT::Other); 3606 SDValue Undef = getUNDEF(Ptr.getValueType()); 3607 SDValue Ops[] = { Chain, Val, Ptr, Undef }; 3608 FoldingSetNodeID ID; 3609 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); 3610 ID.AddInteger(SVT.getRawBits()); 3611 ID.AddInteger(encodeMemSDNodeFlags(true, ISD::UNINDEXED, 3612 isVolatile, Alignment)); 3613 void *IP = 0; 3614 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3615 return SDValue(E, 0); 3616 SDNode *N = NodeAllocator.Allocate<StoreSDNode>(); 3617 new (N) StoreSDNode(Ops, dl, VTs, ISD::UNINDEXED, true, 3618 SVT, SV, SVOffset, Alignment, isVolatile); 3619 CSEMap.InsertNode(N, IP); 3620 AllNodes.push_back(N); 3621 return SDValue(N, 0); 3622} 3623 3624SDValue 3625SelectionDAG::getIndexedStore(SDValue OrigStore, DebugLoc dl, SDValue Base, 3626 SDValue Offset, ISD::MemIndexedMode AM) { 3627 StoreSDNode *ST = cast<StoreSDNode>(OrigStore); 3628 assert(ST->getOffset().getOpcode() == ISD::UNDEF && 3629 "Store is already a indexed store!"); 3630 SDVTList VTs = getVTList(Base.getValueType(), MVT::Other); 3631 SDValue Ops[] = { ST->getChain(), ST->getValue(), Base, Offset }; 3632 FoldingSetNodeID ID; 3633 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); 3634 ID.AddInteger(ST->getMemoryVT().getRawBits()); 3635 ID.AddInteger(ST->getRawSubclassData()); 3636 void *IP = 0; 3637 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3638 return SDValue(E, 0); 3639 SDNode *N = NodeAllocator.Allocate<StoreSDNode>(); 3640 new (N) StoreSDNode(Ops, dl, VTs, AM, 3641 ST->isTruncatingStore(), ST->getMemoryVT(), 3642 ST->getSrcValue(), ST->getSrcValueOffset(), 3643 ST->getAlignment(), ST->isVolatile()); 3644 CSEMap.InsertNode(N, IP); 3645 AllNodes.push_back(N); 3646 return SDValue(N, 0); 3647} 3648 3649SDValue SelectionDAG::getVAArg(MVT VT, DebugLoc dl, 3650 SDValue Chain, SDValue Ptr, 3651 SDValue SV) { 3652 SDValue Ops[] = { Chain, Ptr, SV }; 3653 return getNode(ISD::VAARG, dl, getVTList(VT, MVT::Other), Ops, 3); 3654} 3655 3656SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, 3657 const SDUse *Ops, unsigned NumOps) { 3658 switch (NumOps) { 3659 case 0: return getNode(Opcode, DL, VT); 3660 case 1: return getNode(Opcode, DL, VT, Ops[0]); 3661 case 2: return getNode(Opcode, DL, VT, Ops[0], Ops[1]); 3662 case 3: return getNode(Opcode, DL, VT, Ops[0], Ops[1], Ops[2]); 3663 default: break; 3664 } 3665 3666 // Copy from an SDUse array into an SDValue array for use with 3667 // the regular getNode logic. 3668 SmallVector<SDValue, 8> NewOps(Ops, Ops + NumOps); 3669 return getNode(Opcode, DL, VT, &NewOps[0], NumOps); 3670} 3671 3672SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, 3673 const SDValue *Ops, unsigned NumOps) { 3674 switch (NumOps) { 3675 case 0: return getNode(Opcode, DL, VT); 3676 case 1: return getNode(Opcode, DL, VT, Ops[0]); 3677 case 2: return getNode(Opcode, DL, VT, Ops[0], Ops[1]); 3678 case 3: return getNode(Opcode, DL, VT, Ops[0], Ops[1], Ops[2]); 3679 default: break; 3680 } 3681 3682 switch (Opcode) { 3683 default: break; 3684 case ISD::SELECT_CC: { 3685 assert(NumOps == 5 && "SELECT_CC takes 5 operands!"); 3686 assert(Ops[0].getValueType() == Ops[1].getValueType() && 3687 "LHS and RHS of condition must have same type!"); 3688 assert(Ops[2].getValueType() == Ops[3].getValueType() && 3689 "True and False arms of SelectCC must have same type!"); 3690 assert(Ops[2].getValueType() == VT && 3691 "select_cc node must be of same type as true and false value!"); 3692 break; 3693 } 3694 case ISD::BR_CC: { 3695 assert(NumOps == 5 && "BR_CC takes 5 operands!"); 3696 assert(Ops[2].getValueType() == Ops[3].getValueType() && 3697 "LHS/RHS of comparison should match types!"); 3698 break; 3699 } 3700 } 3701 3702 // Memoize nodes. 3703 SDNode *N; 3704 SDVTList VTs = getVTList(VT); 3705 3706 if (VT != MVT::Flag) { 3707 FoldingSetNodeID ID; 3708 AddNodeIDNode(ID, Opcode, VTs, Ops, NumOps); 3709 void *IP = 0; 3710 3711 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3712 return SDValue(E, 0); 3713 3714 N = NodeAllocator.Allocate<SDNode>(); 3715 new (N) SDNode(Opcode, DL, VTs, Ops, NumOps); 3716 CSEMap.InsertNode(N, IP); 3717 } else { 3718 N = NodeAllocator.Allocate<SDNode>(); 3719 new (N) SDNode(Opcode, DL, VTs, Ops, NumOps); 3720 } 3721 3722 AllNodes.push_back(N); 3723#ifndef NDEBUG 3724 VerifyNode(N); 3725#endif 3726 return SDValue(N, 0); 3727} 3728 3729SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, 3730 const std::vector<MVT> &ResultTys, 3731 const SDValue *Ops, unsigned NumOps) { 3732 return getNode(Opcode, DL, getVTList(&ResultTys[0], ResultTys.size()), 3733 Ops, NumOps); 3734} 3735 3736SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, 3737 const MVT *VTs, unsigned NumVTs, 3738 const SDValue *Ops, unsigned NumOps) { 3739 if (NumVTs == 1) 3740 return getNode(Opcode, DL, VTs[0], Ops, NumOps); 3741 return getNode(Opcode, DL, makeVTList(VTs, NumVTs), Ops, NumOps); 3742} 3743 3744SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, 3745 const SDValue *Ops, unsigned NumOps) { 3746 if (VTList.NumVTs == 1) 3747 return getNode(Opcode, DL, VTList.VTs[0], Ops, NumOps); 3748 3749 switch (Opcode) { 3750 // FIXME: figure out how to safely handle things like 3751 // int foo(int x) { return 1 << (x & 255); } 3752 // int bar() { return foo(256); } 3753#if 0 3754 case ISD::SRA_PARTS: 3755 case ISD::SRL_PARTS: 3756 case ISD::SHL_PARTS: 3757 if (N3.getOpcode() == ISD::SIGN_EXTEND_INREG && 3758 cast<VTSDNode>(N3.getOperand(1))->getVT() != MVT::i1) 3759 return getNode(Opcode, DL, VT, N1, N2, N3.getOperand(0)); 3760 else if (N3.getOpcode() == ISD::AND) 3761 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(N3.getOperand(1))) { 3762 // If the and is only masking out bits that cannot effect the shift, 3763 // eliminate the and. 3764 unsigned NumBits = VT.getSizeInBits()*2; 3765 if ((AndRHS->getValue() & (NumBits-1)) == NumBits-1) 3766 return getNode(Opcode, DL, VT, N1, N2, N3.getOperand(0)); 3767 } 3768 break; 3769#endif 3770 } 3771 3772 // Memoize the node unless it returns a flag. 3773 SDNode *N; 3774 if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) { 3775 FoldingSetNodeID ID; 3776 AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps); 3777 void *IP = 0; 3778 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3779 return SDValue(E, 0); 3780 if (NumOps == 1) { 3781 N = NodeAllocator.Allocate<UnarySDNode>(); 3782 new (N) UnarySDNode(Opcode, DL, VTList, Ops[0]); 3783 } else if (NumOps == 2) { 3784 N = NodeAllocator.Allocate<BinarySDNode>(); 3785 new (N) BinarySDNode(Opcode, DL, VTList, Ops[0], Ops[1]); 3786 } else if (NumOps == 3) { 3787 N = NodeAllocator.Allocate<TernarySDNode>(); 3788 new (N) TernarySDNode(Opcode, DL, VTList, Ops[0], Ops[1], Ops[2]); 3789 } else { 3790 N = NodeAllocator.Allocate<SDNode>(); 3791 new (N) SDNode(Opcode, DL, VTList, Ops, NumOps); 3792 } 3793 CSEMap.InsertNode(N, IP); 3794 } else { 3795 if (NumOps == 1) { 3796 N = NodeAllocator.Allocate<UnarySDNode>(); 3797 new (N) UnarySDNode(Opcode, DL, VTList, Ops[0]); 3798 } else if (NumOps == 2) { 3799 N = NodeAllocator.Allocate<BinarySDNode>(); 3800 new (N) BinarySDNode(Opcode, DL, VTList, Ops[0], Ops[1]); 3801 } else if (NumOps == 3) { 3802 N = NodeAllocator.Allocate<TernarySDNode>(); 3803 new (N) TernarySDNode(Opcode, DL, VTList, Ops[0], Ops[1], Ops[2]); 3804 } else { 3805 N = NodeAllocator.Allocate<SDNode>(); 3806 new (N) SDNode(Opcode, DL, VTList, Ops, NumOps); 3807 } 3808 } 3809 AllNodes.push_back(N); 3810#ifndef NDEBUG 3811 VerifyNode(N); 3812#endif 3813 return SDValue(N, 0); 3814} 3815 3816SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList) { 3817 return getNode(Opcode, DL, VTList, 0, 0); 3818} 3819 3820SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, 3821 SDValue N1) { 3822 SDValue Ops[] = { N1 }; 3823 return getNode(Opcode, DL, VTList, Ops, 1); 3824} 3825 3826SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, 3827 SDValue N1, SDValue N2) { 3828 SDValue Ops[] = { N1, N2 }; 3829 return getNode(Opcode, DL, VTList, Ops, 2); 3830} 3831 3832SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, 3833 SDValue N1, SDValue N2, SDValue N3) { 3834 SDValue Ops[] = { N1, N2, N3 }; 3835 return getNode(Opcode, DL, VTList, Ops, 3); 3836} 3837 3838SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, 3839 SDValue N1, SDValue N2, SDValue N3, 3840 SDValue N4) { 3841 SDValue Ops[] = { N1, N2, N3, N4 }; 3842 return getNode(Opcode, DL, VTList, Ops, 4); 3843} 3844 3845SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, 3846 SDValue N1, SDValue N2, SDValue N3, 3847 SDValue N4, SDValue N5) { 3848 SDValue Ops[] = { N1, N2, N3, N4, N5 }; 3849 return getNode(Opcode, DL, VTList, Ops, 5); 3850} 3851 3852SDVTList SelectionDAG::getVTList(MVT VT) { 3853 return makeVTList(SDNode::getValueTypeList(VT), 1); 3854} 3855 3856SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2) { 3857 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 3858 E = VTList.rend(); I != E; ++I) 3859 if (I->NumVTs == 2 && I->VTs[0] == VT1 && I->VTs[1] == VT2) 3860 return *I; 3861 3862 MVT *Array = Allocator.Allocate<MVT>(2); 3863 Array[0] = VT1; 3864 Array[1] = VT2; 3865 SDVTList Result = makeVTList(Array, 2); 3866 VTList.push_back(Result); 3867 return Result; 3868} 3869 3870SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2, MVT VT3) { 3871 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 3872 E = VTList.rend(); I != E; ++I) 3873 if (I->NumVTs == 3 && I->VTs[0] == VT1 && I->VTs[1] == VT2 && 3874 I->VTs[2] == VT3) 3875 return *I; 3876 3877 MVT *Array = Allocator.Allocate<MVT>(3); 3878 Array[0] = VT1; 3879 Array[1] = VT2; 3880 Array[2] = VT3; 3881 SDVTList Result = makeVTList(Array, 3); 3882 VTList.push_back(Result); 3883 return Result; 3884} 3885 3886SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2, MVT VT3, MVT VT4) { 3887 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 3888 E = VTList.rend(); I != E; ++I) 3889 if (I->NumVTs == 4 && I->VTs[0] == VT1 && I->VTs[1] == VT2 && 3890 I->VTs[2] == VT3 && I->VTs[3] == VT4) 3891 return *I; 3892 3893 MVT *Array = Allocator.Allocate<MVT>(3); 3894 Array[0] = VT1; 3895 Array[1] = VT2; 3896 Array[2] = VT3; 3897 Array[3] = VT4; 3898 SDVTList Result = makeVTList(Array, 4); 3899 VTList.push_back(Result); 3900 return Result; 3901} 3902 3903SDVTList SelectionDAG::getVTList(const MVT *VTs, unsigned NumVTs) { 3904 switch (NumVTs) { 3905 case 0: assert(0 && "Cannot have nodes without results!"); 3906 case 1: return getVTList(VTs[0]); 3907 case 2: return getVTList(VTs[0], VTs[1]); 3908 case 3: return getVTList(VTs[0], VTs[1], VTs[2]); 3909 default: break; 3910 } 3911 3912 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 3913 E = VTList.rend(); I != E; ++I) { 3914 if (I->NumVTs != NumVTs || VTs[0] != I->VTs[0] || VTs[1] != I->VTs[1]) 3915 continue; 3916 3917 bool NoMatch = false; 3918 for (unsigned i = 2; i != NumVTs; ++i) 3919 if (VTs[i] != I->VTs[i]) { 3920 NoMatch = true; 3921 break; 3922 } 3923 if (!NoMatch) 3924 return *I; 3925 } 3926 3927 MVT *Array = Allocator.Allocate<MVT>(NumVTs); 3928 std::copy(VTs, VTs+NumVTs, Array); 3929 SDVTList Result = makeVTList(Array, NumVTs); 3930 VTList.push_back(Result); 3931 return Result; 3932} 3933 3934 3935/// UpdateNodeOperands - *Mutate* the specified node in-place to have the 3936/// specified operands. If the resultant node already exists in the DAG, 3937/// this does not modify the specified node, instead it returns the node that 3938/// already exists. If the resultant node does not exist in the DAG, the 3939/// input node is returned. As a degenerate case, if you specify the same 3940/// input operands as the node already has, the input node is returned. 3941SDValue SelectionDAG::UpdateNodeOperands(SDValue InN, SDValue Op) { 3942 SDNode *N = InN.getNode(); 3943 assert(N->getNumOperands() == 1 && "Update with wrong number of operands"); 3944 3945 // Check to see if there is no change. 3946 if (Op == N->getOperand(0)) return InN; 3947 3948 // See if the modified node already exists. 3949 void *InsertPos = 0; 3950 if (SDNode *Existing = FindModifiedNodeSlot(N, Op, InsertPos)) 3951 return SDValue(Existing, InN.getResNo()); 3952 3953 // Nope it doesn't. Remove the node from its current place in the maps. 3954 if (InsertPos) 3955 if (!RemoveNodeFromCSEMaps(N)) 3956 InsertPos = 0; 3957 3958 // Now we update the operands. 3959 N->OperandList[0].set(Op); 3960 3961 // If this gets put into a CSE map, add it. 3962 if (InsertPos) CSEMap.InsertNode(N, InsertPos); 3963 return InN; 3964} 3965 3966SDValue SelectionDAG:: 3967UpdateNodeOperands(SDValue InN, SDValue Op1, SDValue Op2) { 3968 SDNode *N = InN.getNode(); 3969 assert(N->getNumOperands() == 2 && "Update with wrong number of operands"); 3970 3971 // Check to see if there is no change. 3972 if (Op1 == N->getOperand(0) && Op2 == N->getOperand(1)) 3973 return InN; // No operands changed, just return the input node. 3974 3975 // See if the modified node already exists. 3976 void *InsertPos = 0; 3977 if (SDNode *Existing = FindModifiedNodeSlot(N, Op1, Op2, InsertPos)) 3978 return SDValue(Existing, InN.getResNo()); 3979 3980 // Nope it doesn't. Remove the node from its current place in the maps. 3981 if (InsertPos) 3982 if (!RemoveNodeFromCSEMaps(N)) 3983 InsertPos = 0; 3984 3985 // Now we update the operands. 3986 if (N->OperandList[0] != Op1) 3987 N->OperandList[0].set(Op1); 3988 if (N->OperandList[1] != Op2) 3989 N->OperandList[1].set(Op2); 3990 3991 // If this gets put into a CSE map, add it. 3992 if (InsertPos) CSEMap.InsertNode(N, InsertPos); 3993 return InN; 3994} 3995 3996SDValue SelectionDAG:: 3997UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, SDValue Op3) { 3998 SDValue Ops[] = { Op1, Op2, Op3 }; 3999 return UpdateNodeOperands(N, Ops, 3); 4000} 4001 4002SDValue SelectionDAG:: 4003UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, 4004 SDValue Op3, SDValue Op4) { 4005 SDValue Ops[] = { Op1, Op2, Op3, Op4 }; 4006 return UpdateNodeOperands(N, Ops, 4); 4007} 4008 4009SDValue SelectionDAG:: 4010UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, 4011 SDValue Op3, SDValue Op4, SDValue Op5) { 4012 SDValue Ops[] = { Op1, Op2, Op3, Op4, Op5 }; 4013 return UpdateNodeOperands(N, Ops, 5); 4014} 4015 4016SDValue SelectionDAG:: 4017UpdateNodeOperands(SDValue InN, const SDValue *Ops, unsigned NumOps) { 4018 SDNode *N = InN.getNode(); 4019 assert(N->getNumOperands() == NumOps && 4020 "Update with wrong number of operands"); 4021 4022 // Check to see if there is no change. 4023 bool AnyChange = false; 4024 for (unsigned i = 0; i != NumOps; ++i) { 4025 if (Ops[i] != N->getOperand(i)) { 4026 AnyChange = true; 4027 break; 4028 } 4029 } 4030 4031 // No operands changed, just return the input node. 4032 if (!AnyChange) return InN; 4033 4034 // See if the modified node already exists. 4035 void *InsertPos = 0; 4036 if (SDNode *Existing = FindModifiedNodeSlot(N, Ops, NumOps, InsertPos)) 4037 return SDValue(Existing, InN.getResNo()); 4038 4039 // Nope it doesn't. Remove the node from its current place in the maps. 4040 if (InsertPos) 4041 if (!RemoveNodeFromCSEMaps(N)) 4042 InsertPos = 0; 4043 4044 // Now we update the operands. 4045 for (unsigned i = 0; i != NumOps; ++i) 4046 if (N->OperandList[i] != Ops[i]) 4047 N->OperandList[i].set(Ops[i]); 4048 4049 // If this gets put into a CSE map, add it. 4050 if (InsertPos) CSEMap.InsertNode(N, InsertPos); 4051 return InN; 4052} 4053 4054/// DropOperands - Release the operands and set this node to have 4055/// zero operands. 4056void SDNode::DropOperands() { 4057 // Unlike the code in MorphNodeTo that does this, we don't need to 4058 // watch for dead nodes here. 4059 for (op_iterator I = op_begin(), E = op_end(); I != E; ) { 4060 SDUse &Use = *I++; 4061 Use.set(SDValue()); 4062 } 4063} 4064 4065/// SelectNodeTo - These are wrappers around MorphNodeTo that accept a 4066/// machine opcode. 4067/// 4068SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4069 MVT VT) { 4070 SDVTList VTs = getVTList(VT); 4071 return SelectNodeTo(N, MachineOpc, VTs, 0, 0); 4072} 4073 4074SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4075 MVT VT, SDValue Op1) { 4076 SDVTList VTs = getVTList(VT); 4077 SDValue Ops[] = { Op1 }; 4078 return SelectNodeTo(N, MachineOpc, VTs, Ops, 1); 4079} 4080 4081SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4082 MVT VT, SDValue Op1, 4083 SDValue Op2) { 4084 SDVTList VTs = getVTList(VT); 4085 SDValue Ops[] = { Op1, Op2 }; 4086 return SelectNodeTo(N, MachineOpc, VTs, Ops, 2); 4087} 4088 4089SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4090 MVT VT, SDValue Op1, 4091 SDValue Op2, SDValue Op3) { 4092 SDVTList VTs = getVTList(VT); 4093 SDValue Ops[] = { Op1, Op2, Op3 }; 4094 return SelectNodeTo(N, MachineOpc, VTs, Ops, 3); 4095} 4096 4097SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4098 MVT VT, const SDValue *Ops, 4099 unsigned NumOps) { 4100 SDVTList VTs = getVTList(VT); 4101 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 4102} 4103 4104SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4105 MVT VT1, MVT VT2, const SDValue *Ops, 4106 unsigned NumOps) { 4107 SDVTList VTs = getVTList(VT1, VT2); 4108 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 4109} 4110 4111SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4112 MVT VT1, MVT VT2) { 4113 SDVTList VTs = getVTList(VT1, VT2); 4114 return SelectNodeTo(N, MachineOpc, VTs, (SDValue *)0, 0); 4115} 4116 4117SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4118 MVT VT1, MVT VT2, MVT VT3, 4119 const SDValue *Ops, unsigned NumOps) { 4120 SDVTList VTs = getVTList(VT1, VT2, VT3); 4121 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 4122} 4123 4124SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4125 MVT VT1, MVT VT2, MVT VT3, MVT VT4, 4126 const SDValue *Ops, unsigned NumOps) { 4127 SDVTList VTs = getVTList(VT1, VT2, VT3, VT4); 4128 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 4129} 4130 4131SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4132 MVT VT1, MVT VT2, 4133 SDValue Op1) { 4134 SDVTList VTs = getVTList(VT1, VT2); 4135 SDValue Ops[] = { Op1 }; 4136 return SelectNodeTo(N, MachineOpc, VTs, Ops, 1); 4137} 4138 4139SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4140 MVT VT1, MVT VT2, 4141 SDValue Op1, SDValue Op2) { 4142 SDVTList VTs = getVTList(VT1, VT2); 4143 SDValue Ops[] = { Op1, Op2 }; 4144 return SelectNodeTo(N, MachineOpc, VTs, Ops, 2); 4145} 4146 4147SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4148 MVT VT1, MVT VT2, 4149 SDValue Op1, SDValue Op2, 4150 SDValue Op3) { 4151 SDVTList VTs = getVTList(VT1, VT2); 4152 SDValue Ops[] = { Op1, Op2, Op3 }; 4153 return SelectNodeTo(N, MachineOpc, VTs, Ops, 3); 4154} 4155 4156SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4157 MVT VT1, MVT VT2, MVT VT3, 4158 SDValue Op1, SDValue Op2, 4159 SDValue Op3) { 4160 SDVTList VTs = getVTList(VT1, VT2, VT3); 4161 SDValue Ops[] = { Op1, Op2, Op3 }; 4162 return SelectNodeTo(N, MachineOpc, VTs, Ops, 3); 4163} 4164 4165SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4166 SDVTList VTs, const SDValue *Ops, 4167 unsigned NumOps) { 4168 return MorphNodeTo(N, ~MachineOpc, VTs, Ops, NumOps); 4169} 4170 4171SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4172 MVT VT) { 4173 SDVTList VTs = getVTList(VT); 4174 return MorphNodeTo(N, Opc, VTs, 0, 0); 4175} 4176 4177SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4178 MVT VT, SDValue Op1) { 4179 SDVTList VTs = getVTList(VT); 4180 SDValue Ops[] = { Op1 }; 4181 return MorphNodeTo(N, Opc, VTs, Ops, 1); 4182} 4183 4184SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4185 MVT VT, SDValue Op1, 4186 SDValue Op2) { 4187 SDVTList VTs = getVTList(VT); 4188 SDValue Ops[] = { Op1, Op2 }; 4189 return MorphNodeTo(N, Opc, VTs, Ops, 2); 4190} 4191 4192SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4193 MVT VT, SDValue Op1, 4194 SDValue Op2, SDValue Op3) { 4195 SDVTList VTs = getVTList(VT); 4196 SDValue Ops[] = { Op1, Op2, Op3 }; 4197 return MorphNodeTo(N, Opc, VTs, Ops, 3); 4198} 4199 4200SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4201 MVT VT, const SDValue *Ops, 4202 unsigned NumOps) { 4203 SDVTList VTs = getVTList(VT); 4204 return MorphNodeTo(N, Opc, VTs, Ops, NumOps); 4205} 4206 4207SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4208 MVT VT1, MVT VT2, const SDValue *Ops, 4209 unsigned NumOps) { 4210 SDVTList VTs = getVTList(VT1, VT2); 4211 return MorphNodeTo(N, Opc, VTs, Ops, NumOps); 4212} 4213 4214SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4215 MVT VT1, MVT VT2) { 4216 SDVTList VTs = getVTList(VT1, VT2); 4217 return MorphNodeTo(N, Opc, VTs, (SDValue *)0, 0); 4218} 4219 4220SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4221 MVT VT1, MVT VT2, MVT VT3, 4222 const SDValue *Ops, unsigned NumOps) { 4223 SDVTList VTs = getVTList(VT1, VT2, VT3); 4224 return MorphNodeTo(N, Opc, VTs, Ops, NumOps); 4225} 4226 4227SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4228 MVT VT1, MVT VT2, 4229 SDValue Op1) { 4230 SDVTList VTs = getVTList(VT1, VT2); 4231 SDValue Ops[] = { Op1 }; 4232 return MorphNodeTo(N, Opc, VTs, Ops, 1); 4233} 4234 4235SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4236 MVT VT1, MVT VT2, 4237 SDValue Op1, SDValue Op2) { 4238 SDVTList VTs = getVTList(VT1, VT2); 4239 SDValue Ops[] = { Op1, Op2 }; 4240 return MorphNodeTo(N, Opc, VTs, Ops, 2); 4241} 4242 4243SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4244 MVT VT1, MVT VT2, 4245 SDValue Op1, SDValue Op2, 4246 SDValue Op3) { 4247 SDVTList VTs = getVTList(VT1, VT2); 4248 SDValue Ops[] = { Op1, Op2, Op3 }; 4249 return MorphNodeTo(N, Opc, VTs, Ops, 3); 4250} 4251 4252/// MorphNodeTo - These *mutate* the specified node to have the specified 4253/// return type, opcode, and operands. 4254/// 4255/// Note that MorphNodeTo returns the resultant node. If there is already a 4256/// node of the specified opcode and operands, it returns that node instead of 4257/// the current one. Note that the DebugLoc need not be the same. 4258/// 4259/// Using MorphNodeTo is faster than creating a new node and swapping it in 4260/// with ReplaceAllUsesWith both because it often avoids allocating a new 4261/// node, and because it doesn't require CSE recalculation for any of 4262/// the node's users. 4263/// 4264SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4265 SDVTList VTs, const SDValue *Ops, 4266 unsigned NumOps) { 4267 // If an identical node already exists, use it. 4268 void *IP = 0; 4269 if (VTs.VTs[VTs.NumVTs-1] != MVT::Flag) { 4270 FoldingSetNodeID ID; 4271 AddNodeIDNode(ID, Opc, VTs, Ops, NumOps); 4272 if (SDNode *ON = CSEMap.FindNodeOrInsertPos(ID, IP)) 4273 return ON; 4274 } 4275 4276 if (!RemoveNodeFromCSEMaps(N)) 4277 IP = 0; 4278 4279 // Start the morphing. 4280 N->NodeType = Opc; 4281 N->ValueList = VTs.VTs; 4282 N->NumValues = VTs.NumVTs; 4283 4284 // Clear the operands list, updating used nodes to remove this from their 4285 // use list. Keep track of any operands that become dead as a result. 4286 SmallPtrSet<SDNode*, 16> DeadNodeSet; 4287 for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ) { 4288 SDUse &Use = *I++; 4289 SDNode *Used = Use.getNode(); 4290 Use.set(SDValue()); 4291 if (Used->use_empty()) 4292 DeadNodeSet.insert(Used); 4293 } 4294 4295 // If NumOps is larger than the # of operands we currently have, reallocate 4296 // the operand list. 4297 if (NumOps > N->NumOperands) { 4298 if (N->OperandsNeedDelete) 4299 delete[] N->OperandList; 4300 4301 if (N->isMachineOpcode()) { 4302 // We're creating a final node that will live unmorphed for the 4303 // remainder of the current SelectionDAG iteration, so we can allocate 4304 // the operands directly out of a pool with no recycling metadata. 4305 N->OperandList = OperandAllocator.Allocate<SDUse>(NumOps); 4306 N->OperandsNeedDelete = false; 4307 } else { 4308 N->OperandList = new SDUse[NumOps]; 4309 N->OperandsNeedDelete = true; 4310 } 4311 } 4312 4313 // Assign the new operands. 4314 N->NumOperands = NumOps; 4315 for (unsigned i = 0, e = NumOps; i != e; ++i) { 4316 N->OperandList[i].setUser(N); 4317 N->OperandList[i].setInitial(Ops[i]); 4318 } 4319 4320 // Delete any nodes that are still dead after adding the uses for the 4321 // new operands. 4322 SmallVector<SDNode *, 16> DeadNodes; 4323 for (SmallPtrSet<SDNode *, 16>::iterator I = DeadNodeSet.begin(), 4324 E = DeadNodeSet.end(); I != E; ++I) 4325 if ((*I)->use_empty()) 4326 DeadNodes.push_back(*I); 4327 RemoveDeadNodes(DeadNodes); 4328 4329 if (IP) 4330 CSEMap.InsertNode(N, IP); // Memoize the new node. 4331 return N; 4332} 4333 4334 4335/// getTargetNode - These are used for target selectors to create a new node 4336/// with specified return type(s), target opcode, and operands. 4337/// 4338/// Note that getTargetNode returns the resultant node. If there is already a 4339/// node of the specified opcode and operands, it returns that node instead of 4340/// the current one. 4341SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT) { 4342 return getNode(~Opcode, dl, VT).getNode(); 4343} 4344 4345SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, 4346 SDValue Op1) { 4347 return getNode(~Opcode, dl, VT, Op1).getNode(); 4348} 4349 4350SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, 4351 SDValue Op1, SDValue Op2) { 4352 return getNode(~Opcode, dl, VT, Op1, Op2).getNode(); 4353} 4354 4355SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, 4356 SDValue Op1, SDValue Op2, 4357 SDValue Op3) { 4358 return getNode(~Opcode, dl, VT, Op1, Op2, Op3).getNode(); 4359} 4360 4361SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, 4362 const SDValue *Ops, unsigned NumOps) { 4363 return getNode(~Opcode, dl, VT, Ops, NumOps).getNode(); 4364} 4365 4366SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, 4367 MVT VT1, MVT VT2) { 4368 SDVTList VTs = getVTList(VT1, VT2); 4369 SDValue Op; 4370 return getNode(~Opcode, dl, VTs, &Op, 0).getNode(); 4371} 4372 4373SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, 4374 MVT VT2, SDValue Op1) { 4375 SDVTList VTs = getVTList(VT1, VT2); 4376 return getNode(~Opcode, dl, VTs, &Op1, 1).getNode(); 4377} 4378 4379SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, 4380 MVT VT2, SDValue Op1, 4381 SDValue Op2) { 4382 SDVTList VTs = getVTList(VT1, VT2); 4383 SDValue Ops[] = { Op1, Op2 }; 4384 return getNode(~Opcode, dl, VTs, Ops, 2).getNode(); 4385} 4386 4387SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, 4388 MVT VT2, SDValue Op1, 4389 SDValue Op2, SDValue Op3) { 4390 SDVTList VTs = getVTList(VT1, VT2); 4391 SDValue Ops[] = { Op1, Op2, Op3 }; 4392 return getNode(~Opcode, dl, VTs, Ops, 3).getNode(); 4393} 4394 4395SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, 4396 MVT VT1, MVT VT2, 4397 const SDValue *Ops, unsigned NumOps) { 4398 SDVTList VTs = getVTList(VT1, VT2); 4399 return getNode(~Opcode, dl, VTs, Ops, NumOps).getNode(); 4400} 4401 4402SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, 4403 MVT VT1, MVT VT2, MVT VT3, 4404 SDValue Op1, SDValue Op2) { 4405 SDVTList VTs = getVTList(VT1, VT2, VT3); 4406 SDValue Ops[] = { Op1, Op2 }; 4407 return getNode(~Opcode, dl, VTs, Ops, 2).getNode(); 4408} 4409 4410SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, 4411 MVT VT1, MVT VT2, MVT VT3, 4412 SDValue Op1, SDValue Op2, 4413 SDValue Op3) { 4414 SDVTList VTs = getVTList(VT1, VT2, VT3); 4415 SDValue Ops[] = { Op1, Op2, Op3 }; 4416 return getNode(~Opcode, dl, VTs, Ops, 3).getNode(); 4417} 4418 4419SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, 4420 MVT VT1, MVT VT2, MVT VT3, 4421 const SDValue *Ops, unsigned NumOps) { 4422 SDVTList VTs = getVTList(VT1, VT2, VT3); 4423 return getNode(~Opcode, dl, VTs, Ops, NumOps).getNode(); 4424} 4425 4426SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, 4427 MVT VT2, MVT VT3, MVT VT4, 4428 const SDValue *Ops, unsigned NumOps) { 4429 SDVTList VTs = getVTList(VT1, VT2, VT3, VT4); 4430 return getNode(~Opcode, dl, VTs, Ops, NumOps).getNode(); 4431} 4432 4433SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, 4434 const std::vector<MVT> &ResultTys, 4435 const SDValue *Ops, unsigned NumOps) { 4436 return getNode(~Opcode, dl, ResultTys, Ops, NumOps).getNode(); 4437} 4438 4439/// getNodeIfExists - Get the specified node if it's already available, or 4440/// else return NULL. 4441SDNode *SelectionDAG::getNodeIfExists(unsigned Opcode, SDVTList VTList, 4442 const SDValue *Ops, unsigned NumOps) { 4443 if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) { 4444 FoldingSetNodeID ID; 4445 AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps); 4446 void *IP = 0; 4447 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 4448 return E; 4449 } 4450 return NULL; 4451} 4452 4453/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. 4454/// This can cause recursive merging of nodes in the DAG. 4455/// 4456/// This version assumes From has a single result value. 4457/// 4458void SelectionDAG::ReplaceAllUsesWith(SDValue FromN, SDValue To, 4459 DAGUpdateListener *UpdateListener) { 4460 SDNode *From = FromN.getNode(); 4461 assert(From->getNumValues() == 1 && FromN.getResNo() == 0 && 4462 "Cannot replace with this method!"); 4463 assert(From != To.getNode() && "Cannot replace uses of with self"); 4464 4465 // Iterate over all the existing uses of From. New uses will be added 4466 // to the beginning of the use list, which we avoid visiting. 4467 // This specifically avoids visiting uses of From that arise while the 4468 // replacement is happening, because any such uses would be the result 4469 // of CSE: If an existing node looks like From after one of its operands 4470 // is replaced by To, we don't want to replace of all its users with To 4471 // too. See PR3018 for more info. 4472 SDNode::use_iterator UI = From->use_begin(), UE = From->use_end(); 4473 while (UI != UE) { 4474 SDNode *User = *UI; 4475 4476 // This node is about to morph, remove its old self from the CSE maps. 4477 RemoveNodeFromCSEMaps(User); 4478 4479 // A user can appear in a use list multiple times, and when this 4480 // happens the uses are usually next to each other in the list. 4481 // To help reduce the number of CSE recomputations, process all 4482 // the uses of this user that we can find this way. 4483 do { 4484 SDUse &Use = UI.getUse(); 4485 ++UI; 4486 Use.set(To); 4487 } while (UI != UE && *UI == User); 4488 4489 // Now that we have modified User, add it back to the CSE maps. If it 4490 // already exists there, recursively merge the results together. 4491 AddModifiedNodeToCSEMaps(User, UpdateListener); 4492 } 4493} 4494 4495/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. 4496/// This can cause recursive merging of nodes in the DAG. 4497/// 4498/// This version assumes that for each value of From, there is a 4499/// corresponding value in To in the same position with the same type. 4500/// 4501void SelectionDAG::ReplaceAllUsesWith(SDNode *From, SDNode *To, 4502 DAGUpdateListener *UpdateListener) { 4503#ifndef NDEBUG 4504 for (unsigned i = 0, e = From->getNumValues(); i != e; ++i) 4505 assert((!From->hasAnyUseOfValue(i) || 4506 From->getValueType(i) == To->getValueType(i)) && 4507 "Cannot use this version of ReplaceAllUsesWith!"); 4508#endif 4509 4510 // Handle the trivial case. 4511 if (From == To) 4512 return; 4513 4514 // Iterate over just the existing users of From. See the comments in 4515 // the ReplaceAllUsesWith above. 4516 SDNode::use_iterator UI = From->use_begin(), UE = From->use_end(); 4517 while (UI != UE) { 4518 SDNode *User = *UI; 4519 4520 // This node is about to morph, remove its old self from the CSE maps. 4521 RemoveNodeFromCSEMaps(User); 4522 4523 // A user can appear in a use list multiple times, and when this 4524 // happens the uses are usually next to each other in the list. 4525 // To help reduce the number of CSE recomputations, process all 4526 // the uses of this user that we can find this way. 4527 do { 4528 SDUse &Use = UI.getUse(); 4529 ++UI; 4530 Use.setNode(To); 4531 } while (UI != UE && *UI == User); 4532 4533 // Now that we have modified User, add it back to the CSE maps. If it 4534 // already exists there, recursively merge the results together. 4535 AddModifiedNodeToCSEMaps(User, UpdateListener); 4536 } 4537} 4538 4539/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. 4540/// This can cause recursive merging of nodes in the DAG. 4541/// 4542/// This version can replace From with any result values. To must match the 4543/// number and types of values returned by From. 4544void SelectionDAG::ReplaceAllUsesWith(SDNode *From, 4545 const SDValue *To, 4546 DAGUpdateListener *UpdateListener) { 4547 if (From->getNumValues() == 1) // Handle the simple case efficiently. 4548 return ReplaceAllUsesWith(SDValue(From, 0), To[0], UpdateListener); 4549 4550 // Iterate over just the existing users of From. See the comments in 4551 // the ReplaceAllUsesWith above. 4552 SDNode::use_iterator UI = From->use_begin(), UE = From->use_end(); 4553 while (UI != UE) { 4554 SDNode *User = *UI; 4555 4556 // This node is about to morph, remove its old self from the CSE maps. 4557 RemoveNodeFromCSEMaps(User); 4558 4559 // A user can appear in a use list multiple times, and when this 4560 // happens the uses are usually next to each other in the list. 4561 // To help reduce the number of CSE recomputations, process all 4562 // the uses of this user that we can find this way. 4563 do { 4564 SDUse &Use = UI.getUse(); 4565 const SDValue &ToOp = To[Use.getResNo()]; 4566 ++UI; 4567 Use.set(ToOp); 4568 } while (UI != UE && *UI == User); 4569 4570 // Now that we have modified User, add it back to the CSE maps. If it 4571 // already exists there, recursively merge the results together. 4572 AddModifiedNodeToCSEMaps(User, UpdateListener); 4573 } 4574} 4575 4576/// ReplaceAllUsesOfValueWith - Replace any uses of From with To, leaving 4577/// uses of other values produced by From.getNode() alone. The Deleted 4578/// vector is handled the same way as for ReplaceAllUsesWith. 4579void SelectionDAG::ReplaceAllUsesOfValueWith(SDValue From, SDValue To, 4580 DAGUpdateListener *UpdateListener){ 4581 // Handle the really simple, really trivial case efficiently. 4582 if (From == To) return; 4583 4584 // Handle the simple, trivial, case efficiently. 4585 if (From.getNode()->getNumValues() == 1) { 4586 ReplaceAllUsesWith(From, To, UpdateListener); 4587 return; 4588 } 4589 4590 // Iterate over just the existing users of From. See the comments in 4591 // the ReplaceAllUsesWith above. 4592 SDNode::use_iterator UI = From.getNode()->use_begin(), 4593 UE = From.getNode()->use_end(); 4594 while (UI != UE) { 4595 SDNode *User = *UI; 4596 bool UserRemovedFromCSEMaps = false; 4597 4598 // A user can appear in a use list multiple times, and when this 4599 // happens the uses are usually next to each other in the list. 4600 // To help reduce the number of CSE recomputations, process all 4601 // the uses of this user that we can find this way. 4602 do { 4603 SDUse &Use = UI.getUse(); 4604 4605 // Skip uses of different values from the same node. 4606 if (Use.getResNo() != From.getResNo()) { 4607 ++UI; 4608 continue; 4609 } 4610 4611 // If this node hasn't been modified yet, it's still in the CSE maps, 4612 // so remove its old self from the CSE maps. 4613 if (!UserRemovedFromCSEMaps) { 4614 RemoveNodeFromCSEMaps(User); 4615 UserRemovedFromCSEMaps = true; 4616 } 4617 4618 ++UI; 4619 Use.set(To); 4620 } while (UI != UE && *UI == User); 4621 4622 // We are iterating over all uses of the From node, so if a use 4623 // doesn't use the specific value, no changes are made. 4624 if (!UserRemovedFromCSEMaps) 4625 continue; 4626 4627 // Now that we have modified User, add it back to the CSE maps. If it 4628 // already exists there, recursively merge the results together. 4629 AddModifiedNodeToCSEMaps(User, UpdateListener); 4630 } 4631} 4632 4633namespace { 4634 /// UseMemo - This class is used by SelectionDAG::ReplaceAllUsesOfValuesWith 4635 /// to record information about a use. 4636 struct UseMemo { 4637 SDNode *User; 4638 unsigned Index; 4639 SDUse *Use; 4640 }; 4641 4642 /// operator< - Sort Memos by User. 4643 bool operator<(const UseMemo &L, const UseMemo &R) { 4644 return (intptr_t)L.User < (intptr_t)R.User; 4645 } 4646} 4647 4648/// ReplaceAllUsesOfValuesWith - Replace any uses of From with To, leaving 4649/// uses of other values produced by From.getNode() alone. The same value 4650/// may appear in both the From and To list. The Deleted vector is 4651/// handled the same way as for ReplaceAllUsesWith. 4652void SelectionDAG::ReplaceAllUsesOfValuesWith(const SDValue *From, 4653 const SDValue *To, 4654 unsigned Num, 4655 DAGUpdateListener *UpdateListener){ 4656 // Handle the simple, trivial case efficiently. 4657 if (Num == 1) 4658 return ReplaceAllUsesOfValueWith(*From, *To, UpdateListener); 4659 4660 // Read up all the uses and make records of them. This helps 4661 // processing new uses that are introduced during the 4662 // replacement process. 4663 SmallVector<UseMemo, 4> Uses; 4664 for (unsigned i = 0; i != Num; ++i) { 4665 unsigned FromResNo = From[i].getResNo(); 4666 SDNode *FromNode = From[i].getNode(); 4667 for (SDNode::use_iterator UI = FromNode->use_begin(), 4668 E = FromNode->use_end(); UI != E; ++UI) { 4669 SDUse &Use = UI.getUse(); 4670 if (Use.getResNo() == FromResNo) { 4671 UseMemo Memo = { *UI, i, &Use }; 4672 Uses.push_back(Memo); 4673 } 4674 } 4675 } 4676 4677 // Sort the uses, so that all the uses from a given User are together. 4678 std::sort(Uses.begin(), Uses.end()); 4679 4680 for (unsigned UseIndex = 0, UseIndexEnd = Uses.size(); 4681 UseIndex != UseIndexEnd; ) { 4682 // We know that this user uses some value of From. If it is the right 4683 // value, update it. 4684 SDNode *User = Uses[UseIndex].User; 4685 4686 // This node is about to morph, remove its old self from the CSE maps. 4687 RemoveNodeFromCSEMaps(User); 4688 4689 // The Uses array is sorted, so all the uses for a given User 4690 // are next to each other in the list. 4691 // To help reduce the number of CSE recomputations, process all 4692 // the uses of this user that we can find this way. 4693 do { 4694 unsigned i = Uses[UseIndex].Index; 4695 SDUse &Use = *Uses[UseIndex].Use; 4696 ++UseIndex; 4697 4698 Use.set(To[i]); 4699 } while (UseIndex != UseIndexEnd && Uses[UseIndex].User == User); 4700 4701 // Now that we have modified User, add it back to the CSE maps. If it 4702 // already exists there, recursively merge the results together. 4703 AddModifiedNodeToCSEMaps(User, UpdateListener); 4704 } 4705} 4706 4707/// AssignTopologicalOrder - Assign a unique node id for each node in the DAG 4708/// based on their topological order. It returns the maximum id and a vector 4709/// of the SDNodes* in assigned order by reference. 4710unsigned SelectionDAG::AssignTopologicalOrder() { 4711 4712 unsigned DAGSize = 0; 4713 4714 // SortedPos tracks the progress of the algorithm. Nodes before it are 4715 // sorted, nodes after it are unsorted. When the algorithm completes 4716 // it is at the end of the list. 4717 allnodes_iterator SortedPos = allnodes_begin(); 4718 4719 // Visit all the nodes. Move nodes with no operands to the front of 4720 // the list immediately. Annotate nodes that do have operands with their 4721 // operand count. Before we do this, the Node Id fields of the nodes 4722 // may contain arbitrary values. After, the Node Id fields for nodes 4723 // before SortedPos will contain the topological sort index, and the 4724 // Node Id fields for nodes At SortedPos and after will contain the 4725 // count of outstanding operands. 4726 for (allnodes_iterator I = allnodes_begin(),E = allnodes_end(); I != E; ) { 4727 SDNode *N = I++; 4728 unsigned Degree = N->getNumOperands(); 4729 if (Degree == 0) { 4730 // A node with no uses, add it to the result array immediately. 4731 N->setNodeId(DAGSize++); 4732 allnodes_iterator Q = N; 4733 if (Q != SortedPos) 4734 SortedPos = AllNodes.insert(SortedPos, AllNodes.remove(Q)); 4735 ++SortedPos; 4736 } else { 4737 // Temporarily use the Node Id as scratch space for the degree count. 4738 N->setNodeId(Degree); 4739 } 4740 } 4741 4742 // Visit all the nodes. As we iterate, moves nodes into sorted order, 4743 // such that by the time the end is reached all nodes will be sorted. 4744 for (allnodes_iterator I = allnodes_begin(),E = allnodes_end(); I != E; ++I) { 4745 SDNode *N = I; 4746 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 4747 UI != UE; ++UI) { 4748 SDNode *P = *UI; 4749 unsigned Degree = P->getNodeId(); 4750 --Degree; 4751 if (Degree == 0) { 4752 // All of P's operands are sorted, so P may sorted now. 4753 P->setNodeId(DAGSize++); 4754 if (P != SortedPos) 4755 SortedPos = AllNodes.insert(SortedPos, AllNodes.remove(P)); 4756 ++SortedPos; 4757 } else { 4758 // Update P's outstanding operand count. 4759 P->setNodeId(Degree); 4760 } 4761 } 4762 } 4763 4764 assert(SortedPos == AllNodes.end() && 4765 "Topological sort incomplete!"); 4766 assert(AllNodes.front().getOpcode() == ISD::EntryToken && 4767 "First node in topological sort is not the entry token!"); 4768 assert(AllNodes.front().getNodeId() == 0 && 4769 "First node in topological sort has non-zero id!"); 4770 assert(AllNodes.front().getNumOperands() == 0 && 4771 "First node in topological sort has operands!"); 4772 assert(AllNodes.back().getNodeId() == (int)DAGSize-1 && 4773 "Last node in topologic sort has unexpected id!"); 4774 assert(AllNodes.back().use_empty() && 4775 "Last node in topologic sort has users!"); 4776 assert(DAGSize == allnodes_size() && "Node count mismatch!"); 4777 return DAGSize; 4778} 4779 4780 4781 4782//===----------------------------------------------------------------------===// 4783// SDNode Class 4784//===----------------------------------------------------------------------===// 4785 4786HandleSDNode::~HandleSDNode() { 4787 DropOperands(); 4788} 4789 4790GlobalAddressSDNode::GlobalAddressSDNode(bool isTarget, const GlobalValue *GA, 4791 MVT VT, int64_t o) 4792 : SDNode(isa<GlobalVariable>(GA) && 4793 cast<GlobalVariable>(GA)->isThreadLocal() ? 4794 // Thread Local 4795 (isTarget ? ISD::TargetGlobalTLSAddress : ISD::GlobalTLSAddress) : 4796 // Non Thread Local 4797 (isTarget ? ISD::TargetGlobalAddress : ISD::GlobalAddress), 4798 DebugLoc::getUnknownLoc(), getSDVTList(VT)), Offset(o) { 4799 TheGlobal = const_cast<GlobalValue*>(GA); 4800} 4801 4802MemSDNode::MemSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, MVT memvt, 4803 const Value *srcValue, int SVO, 4804 unsigned alignment, bool vol) 4805 : SDNode(Opc, dl, VTs), MemoryVT(memvt), SrcValue(srcValue), SVOffset(SVO) { 4806 SubclassData = encodeMemSDNodeFlags(0, ISD::UNINDEXED, vol, alignment); 4807 assert(isPowerOf2_32(alignment) && "Alignment is not a power of 2!"); 4808 assert(getAlignment() == alignment && "Alignment representation error!"); 4809 assert(isVolatile() == vol && "Volatile representation error!"); 4810} 4811 4812MemSDNode::MemSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, 4813 const SDValue *Ops, 4814 unsigned NumOps, MVT memvt, const Value *srcValue, 4815 int SVO, unsigned alignment, bool vol) 4816 : SDNode(Opc, dl, VTs, Ops, NumOps), 4817 MemoryVT(memvt), SrcValue(srcValue), SVOffset(SVO) { 4818 SubclassData = encodeMemSDNodeFlags(0, ISD::UNINDEXED, vol, alignment); 4819 assert(isPowerOf2_32(alignment) && "Alignment is not a power of 2!"); 4820 assert(getAlignment() == alignment && "Alignment representation error!"); 4821 assert(isVolatile() == vol && "Volatile representation error!"); 4822} 4823 4824/// getMemOperand - Return a MachineMemOperand object describing the memory 4825/// reference performed by this memory reference. 4826MachineMemOperand MemSDNode::getMemOperand() const { 4827 int Flags = 0; 4828 if (isa<LoadSDNode>(this)) 4829 Flags = MachineMemOperand::MOLoad; 4830 else if (isa<StoreSDNode>(this)) 4831 Flags = MachineMemOperand::MOStore; 4832 else if (isa<AtomicSDNode>(this)) { 4833 Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore; 4834 } 4835 else { 4836 const MemIntrinsicSDNode* MemIntrinNode = dyn_cast<MemIntrinsicSDNode>(this); 4837 assert(MemIntrinNode && "Unknown MemSDNode opcode!"); 4838 if (MemIntrinNode->readMem()) Flags |= MachineMemOperand::MOLoad; 4839 if (MemIntrinNode->writeMem()) Flags |= MachineMemOperand::MOStore; 4840 } 4841 4842 int Size = (getMemoryVT().getSizeInBits() + 7) >> 3; 4843 if (isVolatile()) Flags |= MachineMemOperand::MOVolatile; 4844 4845 // Check if the memory reference references a frame index 4846 const FrameIndexSDNode *FI = 4847 dyn_cast<const FrameIndexSDNode>(getBasePtr().getNode()); 4848 if (!getSrcValue() && FI) 4849 return MachineMemOperand(PseudoSourceValue::getFixedStack(FI->getIndex()), 4850 Flags, 0, Size, getAlignment()); 4851 else 4852 return MachineMemOperand(getSrcValue(), Flags, getSrcValueOffset(), 4853 Size, getAlignment()); 4854} 4855 4856/// Profile - Gather unique data for the node. 4857/// 4858void SDNode::Profile(FoldingSetNodeID &ID) const { 4859 AddNodeIDNode(ID, this); 4860} 4861 4862/// getValueTypeList - Return a pointer to the specified value type. 4863/// 4864const MVT *SDNode::getValueTypeList(MVT VT) { 4865 if (VT.isExtended()) { 4866 static std::set<MVT, MVT::compareRawBits> EVTs; 4867 return &(*EVTs.insert(VT).first); 4868 } else { 4869 static MVT VTs[MVT::LAST_VALUETYPE]; 4870 VTs[VT.getSimpleVT()] = VT; 4871 return &VTs[VT.getSimpleVT()]; 4872 } 4873} 4874 4875/// hasNUsesOfValue - Return true if there are exactly NUSES uses of the 4876/// indicated value. This method ignores uses of other values defined by this 4877/// operation. 4878bool SDNode::hasNUsesOfValue(unsigned NUses, unsigned Value) const { 4879 assert(Value < getNumValues() && "Bad value!"); 4880 4881 // TODO: Only iterate over uses of a given value of the node 4882 for (SDNode::use_iterator UI = use_begin(), E = use_end(); UI != E; ++UI) { 4883 if (UI.getUse().getResNo() == Value) { 4884 if (NUses == 0) 4885 return false; 4886 --NUses; 4887 } 4888 } 4889 4890 // Found exactly the right number of uses? 4891 return NUses == 0; 4892} 4893 4894 4895/// hasAnyUseOfValue - Return true if there are any use of the indicated 4896/// value. This method ignores uses of other values defined by this operation. 4897bool SDNode::hasAnyUseOfValue(unsigned Value) const { 4898 assert(Value < getNumValues() && "Bad value!"); 4899 4900 for (SDNode::use_iterator UI = use_begin(), E = use_end(); UI != E; ++UI) 4901 if (UI.getUse().getResNo() == Value) 4902 return true; 4903 4904 return false; 4905} 4906 4907 4908/// isOnlyUserOf - Return true if this node is the only use of N. 4909/// 4910bool SDNode::isOnlyUserOf(SDNode *N) const { 4911 bool Seen = false; 4912 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 4913 SDNode *User = *I; 4914 if (User == this) 4915 Seen = true; 4916 else 4917 return false; 4918 } 4919 4920 return Seen; 4921} 4922 4923/// isOperand - Return true if this node is an operand of N. 4924/// 4925bool SDValue::isOperandOf(SDNode *N) const { 4926 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 4927 if (*this == N->getOperand(i)) 4928 return true; 4929 return false; 4930} 4931 4932bool SDNode::isOperandOf(SDNode *N) const { 4933 for (unsigned i = 0, e = N->NumOperands; i != e; ++i) 4934 if (this == N->OperandList[i].getNode()) 4935 return true; 4936 return false; 4937} 4938 4939/// reachesChainWithoutSideEffects - Return true if this operand (which must 4940/// be a chain) reaches the specified operand without crossing any 4941/// side-effecting instructions. In practice, this looks through token 4942/// factors and non-volatile loads. In order to remain efficient, this only 4943/// looks a couple of nodes in, it does not do an exhaustive search. 4944bool SDValue::reachesChainWithoutSideEffects(SDValue Dest, 4945 unsigned Depth) const { 4946 if (*this == Dest) return true; 4947 4948 // Don't search too deeply, we just want to be able to see through 4949 // TokenFactor's etc. 4950 if (Depth == 0) return false; 4951 4952 // If this is a token factor, all inputs to the TF happen in parallel. If any 4953 // of the operands of the TF reach dest, then we can do the xform. 4954 if (getOpcode() == ISD::TokenFactor) { 4955 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) 4956 if (getOperand(i).reachesChainWithoutSideEffects(Dest, Depth-1)) 4957 return true; 4958 return false; 4959 } 4960 4961 // Loads don't have side effects, look through them. 4962 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(*this)) { 4963 if (!Ld->isVolatile()) 4964 return Ld->getChain().reachesChainWithoutSideEffects(Dest, Depth-1); 4965 } 4966 return false; 4967} 4968 4969 4970static void findPredecessor(SDNode *N, const SDNode *P, bool &found, 4971 SmallPtrSet<SDNode *, 32> &Visited) { 4972 if (found || !Visited.insert(N)) 4973 return; 4974 4975 for (unsigned i = 0, e = N->getNumOperands(); !found && i != e; ++i) { 4976 SDNode *Op = N->getOperand(i).getNode(); 4977 if (Op == P) { 4978 found = true; 4979 return; 4980 } 4981 findPredecessor(Op, P, found, Visited); 4982 } 4983} 4984 4985/// isPredecessorOf - Return true if this node is a predecessor of N. This node 4986/// is either an operand of N or it can be reached by recursively traversing 4987/// up the operands. 4988/// NOTE: this is an expensive method. Use it carefully. 4989bool SDNode::isPredecessorOf(SDNode *N) const { 4990 SmallPtrSet<SDNode *, 32> Visited; 4991 bool found = false; 4992 findPredecessor(N, this, found, Visited); 4993 return found; 4994} 4995 4996uint64_t SDNode::getConstantOperandVal(unsigned Num) const { 4997 assert(Num < NumOperands && "Invalid child # of SDNode!"); 4998 return cast<ConstantSDNode>(OperandList[Num])->getZExtValue(); 4999} 5000 5001std::string SDNode::getOperationName(const SelectionDAG *G) const { 5002 switch (getOpcode()) { 5003 default: 5004 if (getOpcode() < ISD::BUILTIN_OP_END) 5005 return "<<Unknown DAG Node>>"; 5006 if (isMachineOpcode()) { 5007 if (G) 5008 if (const TargetInstrInfo *TII = G->getTarget().getInstrInfo()) 5009 if (getMachineOpcode() < TII->getNumOpcodes()) 5010 return TII->get(getMachineOpcode()).getName(); 5011 return "<<Unknown Machine Node>>"; 5012 } 5013 if (G) { 5014 const TargetLowering &TLI = G->getTargetLoweringInfo(); 5015 const char *Name = TLI.getTargetNodeName(getOpcode()); 5016 if (Name) return Name; 5017 return "<<Unknown Target Node>>"; 5018 } 5019 return "<<Unknown Node>>"; 5020 5021#ifndef NDEBUG 5022 case ISD::DELETED_NODE: 5023 return "<<Deleted Node!>>"; 5024#endif 5025 case ISD::PREFETCH: return "Prefetch"; 5026 case ISD::MEMBARRIER: return "MemBarrier"; 5027 case ISD::ATOMIC_CMP_SWAP: return "AtomicCmpSwap"; 5028 case ISD::ATOMIC_SWAP: return "AtomicSwap"; 5029 case ISD::ATOMIC_LOAD_ADD: return "AtomicLoadAdd"; 5030 case ISD::ATOMIC_LOAD_SUB: return "AtomicLoadSub"; 5031 case ISD::ATOMIC_LOAD_AND: return "AtomicLoadAnd"; 5032 case ISD::ATOMIC_LOAD_OR: return "AtomicLoadOr"; 5033 case ISD::ATOMIC_LOAD_XOR: return "AtomicLoadXor"; 5034 case ISD::ATOMIC_LOAD_NAND: return "AtomicLoadNand"; 5035 case ISD::ATOMIC_LOAD_MIN: return "AtomicLoadMin"; 5036 case ISD::ATOMIC_LOAD_MAX: return "AtomicLoadMax"; 5037 case ISD::ATOMIC_LOAD_UMIN: return "AtomicLoadUMin"; 5038 case ISD::ATOMIC_LOAD_UMAX: return "AtomicLoadUMax"; 5039 case ISD::PCMARKER: return "PCMarker"; 5040 case ISD::READCYCLECOUNTER: return "ReadCycleCounter"; 5041 case ISD::SRCVALUE: return "SrcValue"; 5042 case ISD::MEMOPERAND: return "MemOperand"; 5043 case ISD::EntryToken: return "EntryToken"; 5044 case ISD::TokenFactor: return "TokenFactor"; 5045 case ISD::AssertSext: return "AssertSext"; 5046 case ISD::AssertZext: return "AssertZext"; 5047 5048 case ISD::BasicBlock: return "BasicBlock"; 5049 case ISD::ARG_FLAGS: return "ArgFlags"; 5050 case ISD::VALUETYPE: return "ValueType"; 5051 case ISD::Register: return "Register"; 5052 5053 case ISD::Constant: return "Constant"; 5054 case ISD::ConstantFP: return "ConstantFP"; 5055 case ISD::GlobalAddress: return "GlobalAddress"; 5056 case ISD::GlobalTLSAddress: return "GlobalTLSAddress"; 5057 case ISD::FrameIndex: return "FrameIndex"; 5058 case ISD::JumpTable: return "JumpTable"; 5059 case ISD::GLOBAL_OFFSET_TABLE: return "GLOBAL_OFFSET_TABLE"; 5060 case ISD::RETURNADDR: return "RETURNADDR"; 5061 case ISD::FRAMEADDR: return "FRAMEADDR"; 5062 case ISD::FRAME_TO_ARGS_OFFSET: return "FRAME_TO_ARGS_OFFSET"; 5063 case ISD::EXCEPTIONADDR: return "EXCEPTIONADDR"; 5064 case ISD::EHSELECTION: return "EHSELECTION"; 5065 case ISD::EH_RETURN: return "EH_RETURN"; 5066 case ISD::ConstantPool: return "ConstantPool"; 5067 case ISD::ExternalSymbol: return "ExternalSymbol"; 5068 case ISD::INTRINSIC_WO_CHAIN: { 5069 unsigned IID = cast<ConstantSDNode>(getOperand(0))->getZExtValue(); 5070 return Intrinsic::getName((Intrinsic::ID)IID); 5071 } 5072 case ISD::INTRINSIC_VOID: 5073 case ISD::INTRINSIC_W_CHAIN: { 5074 unsigned IID = cast<ConstantSDNode>(getOperand(1))->getZExtValue(); 5075 return Intrinsic::getName((Intrinsic::ID)IID); 5076 } 5077 5078 case ISD::BUILD_VECTOR: return "BUILD_VECTOR"; 5079 case ISD::TargetConstant: return "TargetConstant"; 5080 case ISD::TargetConstantFP:return "TargetConstantFP"; 5081 case ISD::TargetGlobalAddress: return "TargetGlobalAddress"; 5082 case ISD::TargetGlobalTLSAddress: return "TargetGlobalTLSAddress"; 5083 case ISD::TargetFrameIndex: return "TargetFrameIndex"; 5084 case ISD::TargetJumpTable: return "TargetJumpTable"; 5085 case ISD::TargetConstantPool: return "TargetConstantPool"; 5086 case ISD::TargetExternalSymbol: return "TargetExternalSymbol"; 5087 5088 case ISD::CopyToReg: return "CopyToReg"; 5089 case ISD::CopyFromReg: return "CopyFromReg"; 5090 case ISD::UNDEF: return "undef"; 5091 case ISD::MERGE_VALUES: return "merge_values"; 5092 case ISD::INLINEASM: return "inlineasm"; 5093 case ISD::DBG_LABEL: return "dbg_label"; 5094 case ISD::EH_LABEL: return "eh_label"; 5095 case ISD::DECLARE: return "declare"; 5096 case ISD::HANDLENODE: return "handlenode"; 5097 case ISD::FORMAL_ARGUMENTS: return "formal_arguments"; 5098 case ISD::CALL: return "call"; 5099 5100 // Unary operators 5101 case ISD::FABS: return "fabs"; 5102 case ISD::FNEG: return "fneg"; 5103 case ISD::FSQRT: return "fsqrt"; 5104 case ISD::FSIN: return "fsin"; 5105 case ISD::FCOS: return "fcos"; 5106 case ISD::FPOWI: return "fpowi"; 5107 case ISD::FPOW: return "fpow"; 5108 case ISD::FTRUNC: return "ftrunc"; 5109 case ISD::FFLOOR: return "ffloor"; 5110 case ISD::FCEIL: return "fceil"; 5111 case ISD::FRINT: return "frint"; 5112 case ISD::FNEARBYINT: return "fnearbyint"; 5113 5114 // Binary operators 5115 case ISD::ADD: return "add"; 5116 case ISD::SUB: return "sub"; 5117 case ISD::MUL: return "mul"; 5118 case ISD::MULHU: return "mulhu"; 5119 case ISD::MULHS: return "mulhs"; 5120 case ISD::SDIV: return "sdiv"; 5121 case ISD::UDIV: return "udiv"; 5122 case ISD::SREM: return "srem"; 5123 case ISD::UREM: return "urem"; 5124 case ISD::SMUL_LOHI: return "smul_lohi"; 5125 case ISD::UMUL_LOHI: return "umul_lohi"; 5126 case ISD::SDIVREM: return "sdivrem"; 5127 case ISD::UDIVREM: return "udivrem"; 5128 case ISD::AND: return "and"; 5129 case ISD::OR: return "or"; 5130 case ISD::XOR: return "xor"; 5131 case ISD::SHL: return "shl"; 5132 case ISD::SRA: return "sra"; 5133 case ISD::SRL: return "srl"; 5134 case ISD::ROTL: return "rotl"; 5135 case ISD::ROTR: return "rotr"; 5136 case ISD::FADD: return "fadd"; 5137 case ISD::FSUB: return "fsub"; 5138 case ISD::FMUL: return "fmul"; 5139 case ISD::FDIV: return "fdiv"; 5140 case ISD::FREM: return "frem"; 5141 case ISD::FCOPYSIGN: return "fcopysign"; 5142 case ISD::FGETSIGN: return "fgetsign"; 5143 5144 case ISD::SETCC: return "setcc"; 5145 case ISD::VSETCC: return "vsetcc"; 5146 case ISD::SELECT: return "select"; 5147 case ISD::SELECT_CC: return "select_cc"; 5148 case ISD::INSERT_VECTOR_ELT: return "insert_vector_elt"; 5149 case ISD::EXTRACT_VECTOR_ELT: return "extract_vector_elt"; 5150 case ISD::CONCAT_VECTORS: return "concat_vectors"; 5151 case ISD::EXTRACT_SUBVECTOR: return "extract_subvector"; 5152 case ISD::SCALAR_TO_VECTOR: return "scalar_to_vector"; 5153 case ISD::VECTOR_SHUFFLE: return "vector_shuffle"; 5154 case ISD::CARRY_FALSE: return "carry_false"; 5155 case ISD::ADDC: return "addc"; 5156 case ISD::ADDE: return "adde"; 5157 case ISD::SADDO: return "saddo"; 5158 case ISD::UADDO: return "uaddo"; 5159 case ISD::SSUBO: return "ssubo"; 5160 case ISD::USUBO: return "usubo"; 5161 case ISD::SMULO: return "smulo"; 5162 case ISD::UMULO: return "umulo"; 5163 case ISD::SUBC: return "subc"; 5164 case ISD::SUBE: return "sube"; 5165 case ISD::SHL_PARTS: return "shl_parts"; 5166 case ISD::SRA_PARTS: return "sra_parts"; 5167 case ISD::SRL_PARTS: return "srl_parts"; 5168 5169 // Conversion operators. 5170 case ISD::SIGN_EXTEND: return "sign_extend"; 5171 case ISD::ZERO_EXTEND: return "zero_extend"; 5172 case ISD::ANY_EXTEND: return "any_extend"; 5173 case ISD::SIGN_EXTEND_INREG: return "sign_extend_inreg"; 5174 case ISD::TRUNCATE: return "truncate"; 5175 case ISD::FP_ROUND: return "fp_round"; 5176 case ISD::FLT_ROUNDS_: return "flt_rounds"; 5177 case ISD::FP_ROUND_INREG: return "fp_round_inreg"; 5178 case ISD::FP_EXTEND: return "fp_extend"; 5179 5180 case ISD::SINT_TO_FP: return "sint_to_fp"; 5181 case ISD::UINT_TO_FP: return "uint_to_fp"; 5182 case ISD::FP_TO_SINT: return "fp_to_sint"; 5183 case ISD::FP_TO_UINT: return "fp_to_uint"; 5184 case ISD::BIT_CONVERT: return "bit_convert"; 5185 5186 case ISD::CONVERT_RNDSAT: { 5187 switch (cast<CvtRndSatSDNode>(this)->getCvtCode()) { 5188 default: assert(0 && "Unknown cvt code!"); 5189 case ISD::CVT_FF: return "cvt_ff"; 5190 case ISD::CVT_FS: return "cvt_fs"; 5191 case ISD::CVT_FU: return "cvt_fu"; 5192 case ISD::CVT_SF: return "cvt_sf"; 5193 case ISD::CVT_UF: return "cvt_uf"; 5194 case ISD::CVT_SS: return "cvt_ss"; 5195 case ISD::CVT_SU: return "cvt_su"; 5196 case ISD::CVT_US: return "cvt_us"; 5197 case ISD::CVT_UU: return "cvt_uu"; 5198 } 5199 } 5200 5201 // Control flow instructions 5202 case ISD::BR: return "br"; 5203 case ISD::BRIND: return "brind"; 5204 case ISD::BR_JT: return "br_jt"; 5205 case ISD::BRCOND: return "brcond"; 5206 case ISD::BR_CC: return "br_cc"; 5207 case ISD::RET: return "ret"; 5208 case ISD::CALLSEQ_START: return "callseq_start"; 5209 case ISD::CALLSEQ_END: return "callseq_end"; 5210 5211 // Other operators 5212 case ISD::LOAD: return "load"; 5213 case ISD::STORE: return "store"; 5214 case ISD::VAARG: return "vaarg"; 5215 case ISD::VACOPY: return "vacopy"; 5216 case ISD::VAEND: return "vaend"; 5217 case ISD::VASTART: return "vastart"; 5218 case ISD::DYNAMIC_STACKALLOC: return "dynamic_stackalloc"; 5219 case ISD::EXTRACT_ELEMENT: return "extract_element"; 5220 case ISD::BUILD_PAIR: return "build_pair"; 5221 case ISD::STACKSAVE: return "stacksave"; 5222 case ISD::STACKRESTORE: return "stackrestore"; 5223 case ISD::TRAP: return "trap"; 5224 5225 // Bit manipulation 5226 case ISD::BSWAP: return "bswap"; 5227 case ISD::CTPOP: return "ctpop"; 5228 case ISD::CTTZ: return "cttz"; 5229 case ISD::CTLZ: return "ctlz"; 5230 5231 // Debug info 5232 case ISD::DBG_STOPPOINT: return "dbg_stoppoint"; 5233 case ISD::DEBUG_LOC: return "debug_loc"; 5234 5235 // Trampolines 5236 case ISD::TRAMPOLINE: return "trampoline"; 5237 5238 case ISD::CONDCODE: 5239 switch (cast<CondCodeSDNode>(this)->get()) { 5240 default: assert(0 && "Unknown setcc condition!"); 5241 case ISD::SETOEQ: return "setoeq"; 5242 case ISD::SETOGT: return "setogt"; 5243 case ISD::SETOGE: return "setoge"; 5244 case ISD::SETOLT: return "setolt"; 5245 case ISD::SETOLE: return "setole"; 5246 case ISD::SETONE: return "setone"; 5247 5248 case ISD::SETO: return "seto"; 5249 case ISD::SETUO: return "setuo"; 5250 case ISD::SETUEQ: return "setue"; 5251 case ISD::SETUGT: return "setugt"; 5252 case ISD::SETUGE: return "setuge"; 5253 case ISD::SETULT: return "setult"; 5254 case ISD::SETULE: return "setule"; 5255 case ISD::SETUNE: return "setune"; 5256 5257 case ISD::SETEQ: return "seteq"; 5258 case ISD::SETGT: return "setgt"; 5259 case ISD::SETGE: return "setge"; 5260 case ISD::SETLT: return "setlt"; 5261 case ISD::SETLE: return "setle"; 5262 case ISD::SETNE: return "setne"; 5263 } 5264 } 5265} 5266 5267const char *SDNode::getIndexedModeName(ISD::MemIndexedMode AM) { 5268 switch (AM) { 5269 default: 5270 return ""; 5271 case ISD::PRE_INC: 5272 return "<pre-inc>"; 5273 case ISD::PRE_DEC: 5274 return "<pre-dec>"; 5275 case ISD::POST_INC: 5276 return "<post-inc>"; 5277 case ISD::POST_DEC: 5278 return "<post-dec>"; 5279 } 5280} 5281 5282std::string ISD::ArgFlagsTy::getArgFlagsString() { 5283 std::string S = "< "; 5284 5285 if (isZExt()) 5286 S += "zext "; 5287 if (isSExt()) 5288 S += "sext "; 5289 if (isInReg()) 5290 S += "inreg "; 5291 if (isSRet()) 5292 S += "sret "; 5293 if (isByVal()) 5294 S += "byval "; 5295 if (isNest()) 5296 S += "nest "; 5297 if (getByValAlign()) 5298 S += "byval-align:" + utostr(getByValAlign()) + " "; 5299 if (getOrigAlign()) 5300 S += "orig-align:" + utostr(getOrigAlign()) + " "; 5301 if (getByValSize()) 5302 S += "byval-size:" + utostr(getByValSize()) + " "; 5303 return S + ">"; 5304} 5305 5306void SDNode::dump() const { dump(0); } 5307void SDNode::dump(const SelectionDAG *G) const { 5308 print(errs(), G); 5309} 5310 5311void SDNode::print_types(raw_ostream &OS, const SelectionDAG *G) const { 5312 OS << (void*)this << ": "; 5313 5314 for (unsigned i = 0, e = getNumValues(); i != e; ++i) { 5315 if (i) OS << ","; 5316 if (getValueType(i) == MVT::Other) 5317 OS << "ch"; 5318 else 5319 OS << getValueType(i).getMVTString(); 5320 } 5321 OS << " = " << getOperationName(G); 5322} 5323 5324void SDNode::print_details(raw_ostream &OS, const SelectionDAG *G) const { 5325 if (!isTargetOpcode() && getOpcode() == ISD::VECTOR_SHUFFLE) { 5326 SDNode *Mask = getOperand(2).getNode(); 5327 OS << "<"; 5328 for (unsigned i = 0, e = Mask->getNumOperands(); i != e; ++i) { 5329 if (i) OS << ","; 5330 if (Mask->getOperand(i).getOpcode() == ISD::UNDEF) 5331 OS << "u"; 5332 else 5333 OS << cast<ConstantSDNode>(Mask->getOperand(i))->getZExtValue(); 5334 } 5335 OS << ">"; 5336 } 5337 5338 if (const ConstantSDNode *CSDN = dyn_cast<ConstantSDNode>(this)) { 5339 OS << '<' << CSDN->getAPIntValue() << '>'; 5340 } else if (const ConstantFPSDNode *CSDN = dyn_cast<ConstantFPSDNode>(this)) { 5341 if (&CSDN->getValueAPF().getSemantics()==&APFloat::IEEEsingle) 5342 OS << '<' << CSDN->getValueAPF().convertToFloat() << '>'; 5343 else if (&CSDN->getValueAPF().getSemantics()==&APFloat::IEEEdouble) 5344 OS << '<' << CSDN->getValueAPF().convertToDouble() << '>'; 5345 else { 5346 OS << "<APFloat("; 5347 CSDN->getValueAPF().bitcastToAPInt().dump(); 5348 OS << ")>"; 5349 } 5350 } else if (const GlobalAddressSDNode *GADN = 5351 dyn_cast<GlobalAddressSDNode>(this)) { 5352 int64_t offset = GADN->getOffset(); 5353 OS << '<'; 5354 WriteAsOperand(OS, GADN->getGlobal()); 5355 OS << '>'; 5356 if (offset > 0) 5357 OS << " + " << offset; 5358 else 5359 OS << " " << offset; 5360 } else if (const FrameIndexSDNode *FIDN = dyn_cast<FrameIndexSDNode>(this)) { 5361 OS << "<" << FIDN->getIndex() << ">"; 5362 } else if (const JumpTableSDNode *JTDN = dyn_cast<JumpTableSDNode>(this)) { 5363 OS << "<" << JTDN->getIndex() << ">"; 5364 } else if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(this)){ 5365 int offset = CP->getOffset(); 5366 if (CP->isMachineConstantPoolEntry()) 5367 OS << "<" << *CP->getMachineCPVal() << ">"; 5368 else 5369 OS << "<" << *CP->getConstVal() << ">"; 5370 if (offset > 0) 5371 OS << " + " << offset; 5372 else 5373 OS << " " << offset; 5374 } else if (const BasicBlockSDNode *BBDN = dyn_cast<BasicBlockSDNode>(this)) { 5375 OS << "<"; 5376 const Value *LBB = (const Value*)BBDN->getBasicBlock()->getBasicBlock(); 5377 if (LBB) 5378 OS << LBB->getName() << " "; 5379 OS << (const void*)BBDN->getBasicBlock() << ">"; 5380 } else if (const RegisterSDNode *R = dyn_cast<RegisterSDNode>(this)) { 5381 if (G && R->getReg() && 5382 TargetRegisterInfo::isPhysicalRegister(R->getReg())) { 5383 OS << " " << G->getTarget().getRegisterInfo()->getName(R->getReg()); 5384 } else { 5385 OS << " #" << R->getReg(); 5386 } 5387 } else if (const ExternalSymbolSDNode *ES = 5388 dyn_cast<ExternalSymbolSDNode>(this)) { 5389 OS << "'" << ES->getSymbol() << "'"; 5390 } else if (const SrcValueSDNode *M = dyn_cast<SrcValueSDNode>(this)) { 5391 if (M->getValue()) 5392 OS << "<" << M->getValue() << ">"; 5393 else 5394 OS << "<null>"; 5395 } else if (const MemOperandSDNode *M = dyn_cast<MemOperandSDNode>(this)) { 5396 if (M->MO.getValue()) 5397 OS << "<" << M->MO.getValue() << ":" << M->MO.getOffset() << ">"; 5398 else 5399 OS << "<null:" << M->MO.getOffset() << ">"; 5400 } else if (const ARG_FLAGSSDNode *N = dyn_cast<ARG_FLAGSSDNode>(this)) { 5401 OS << N->getArgFlags().getArgFlagsString(); 5402 } else if (const VTSDNode *N = dyn_cast<VTSDNode>(this)) { 5403 OS << ":" << N->getVT().getMVTString(); 5404 } 5405 else if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(this)) { 5406 const Value *SrcValue = LD->getSrcValue(); 5407 int SrcOffset = LD->getSrcValueOffset(); 5408 OS << " <"; 5409 if (SrcValue) 5410 OS << SrcValue; 5411 else 5412 OS << "null"; 5413 OS << ":" << SrcOffset << ">"; 5414 5415 bool doExt = true; 5416 switch (LD->getExtensionType()) { 5417 default: doExt = false; break; 5418 case ISD::EXTLOAD: OS << " <anyext "; break; 5419 case ISD::SEXTLOAD: OS << " <sext "; break; 5420 case ISD::ZEXTLOAD: OS << " <zext "; break; 5421 } 5422 if (doExt) 5423 OS << LD->getMemoryVT().getMVTString() << ">"; 5424 5425 const char *AM = getIndexedModeName(LD->getAddressingMode()); 5426 if (*AM) 5427 OS << " " << AM; 5428 if (LD->isVolatile()) 5429 OS << " <volatile>"; 5430 OS << " alignment=" << LD->getAlignment(); 5431 } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(this)) { 5432 const Value *SrcValue = ST->getSrcValue(); 5433 int SrcOffset = ST->getSrcValueOffset(); 5434 OS << " <"; 5435 if (SrcValue) 5436 OS << SrcValue; 5437 else 5438 OS << "null"; 5439 OS << ":" << SrcOffset << ">"; 5440 5441 if (ST->isTruncatingStore()) 5442 OS << " <trunc " << ST->getMemoryVT().getMVTString() << ">"; 5443 5444 const char *AM = getIndexedModeName(ST->getAddressingMode()); 5445 if (*AM) 5446 OS << " " << AM; 5447 if (ST->isVolatile()) 5448 OS << " <volatile>"; 5449 OS << " alignment=" << ST->getAlignment(); 5450 } else if (const AtomicSDNode* AT = dyn_cast<AtomicSDNode>(this)) { 5451 const Value *SrcValue = AT->getSrcValue(); 5452 int SrcOffset = AT->getSrcValueOffset(); 5453 OS << " <"; 5454 if (SrcValue) 5455 OS << SrcValue; 5456 else 5457 OS << "null"; 5458 OS << ":" << SrcOffset << ">"; 5459 if (AT->isVolatile()) 5460 OS << " <volatile>"; 5461 OS << " alignment=" << AT->getAlignment(); 5462 } 5463} 5464 5465void SDNode::print(raw_ostream &OS, const SelectionDAG *G) const { 5466 print_types(OS, G); 5467 OS << " "; 5468 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 5469 if (i) OS << ", "; 5470 OS << (void*)getOperand(i).getNode(); 5471 if (unsigned RN = getOperand(i).getResNo()) 5472 OS << ":" << RN; 5473 } 5474 print_details(OS, G); 5475} 5476 5477static void DumpNodes(const SDNode *N, unsigned indent, const SelectionDAG *G) { 5478 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 5479 if (N->getOperand(i).getNode()->hasOneUse()) 5480 DumpNodes(N->getOperand(i).getNode(), indent+2, G); 5481 else 5482 cerr << "\n" << std::string(indent+2, ' ') 5483 << (void*)N->getOperand(i).getNode() << ": <multiple use>"; 5484 5485 5486 cerr << "\n" << std::string(indent, ' '); 5487 N->dump(G); 5488} 5489 5490void SelectionDAG::dump() const { 5491 cerr << "SelectionDAG has " << AllNodes.size() << " nodes:"; 5492 5493 for (allnodes_const_iterator I = allnodes_begin(), E = allnodes_end(); 5494 I != E; ++I) { 5495 const SDNode *N = I; 5496 if (!N->hasOneUse() && N != getRoot().getNode()) 5497 DumpNodes(N, 2, this); 5498 } 5499 5500 if (getRoot().getNode()) DumpNodes(getRoot().getNode(), 2, this); 5501 5502 cerr << "\n\n"; 5503} 5504 5505void SDNode::printr(raw_ostream &OS, const SelectionDAG *G) const { 5506 print_types(OS, G); 5507 print_details(OS, G); 5508} 5509 5510typedef SmallPtrSet<const SDNode *, 128> VisitedSDNodeSet; 5511static void DumpNodesr(raw_ostream &OS, const SDNode *N, unsigned indent, 5512 const SelectionDAG *G, VisitedSDNodeSet &once) { 5513 if (!once.insert(N)) // If we've been here before, return now. 5514 return; 5515 // Dump the current SDNode, but don't end the line yet. 5516 OS << std::string(indent, ' '); 5517 N->printr(OS, G); 5518 // Having printed this SDNode, walk the children: 5519 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 5520 const SDNode *child = N->getOperand(i).getNode(); 5521 if (i) OS << ","; 5522 OS << " "; 5523 if (child->getNumOperands() == 0) { 5524 // This child has no grandchildren; print it inline right here. 5525 child->printr(OS, G); 5526 once.insert(child); 5527 } else { // Just the address. FIXME: also print the child's opcode 5528 OS << (void*)child; 5529 if (unsigned RN = N->getOperand(i).getResNo()) 5530 OS << ":" << RN; 5531 } 5532 } 5533 OS << "\n"; 5534 // Dump children that have grandchildren on their own line(s). 5535 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 5536 const SDNode *child = N->getOperand(i).getNode(); 5537 DumpNodesr(OS, child, indent+2, G, once); 5538 } 5539} 5540 5541void SDNode::dumpr() const { 5542 VisitedSDNodeSet once; 5543 DumpNodesr(errs(), this, 0, 0, once); 5544} 5545 5546const Type *ConstantPoolSDNode::getType() const { 5547 if (isMachineConstantPoolEntry()) 5548 return Val.MachineCPVal->getType(); 5549 return Val.ConstVal->getType(); 5550} 5551 5552bool BuildVectorSDNode::isConstantSplat(APInt &SplatValue, 5553 APInt &SplatUndef, 5554 unsigned &SplatBitSize, 5555 bool &HasAnyUndefs, 5556 unsigned MinSplatBits) { 5557 MVT VT = getValueType(0); 5558 assert(VT.isVector() && "Expected a vector type"); 5559 unsigned sz = VT.getSizeInBits(); 5560 if (MinSplatBits > sz) 5561 return false; 5562 5563 SplatValue = APInt(sz, 0); 5564 SplatUndef = APInt(sz, 0); 5565 5566 // Get the bits. Bits with undefined values (when the corresponding element 5567 // of the vector is an ISD::UNDEF value) are set in SplatUndef and cleared 5568 // in SplatValue. If any of the values are not constant, give up and return 5569 // false. 5570 unsigned int nOps = getNumOperands(); 5571 assert(nOps > 0 && "isConstantSplat has 0-size build vector"); 5572 unsigned EltBitSize = VT.getVectorElementType().getSizeInBits(); 5573 for (unsigned i = 0; i < nOps; ++i) { 5574 SDValue OpVal = getOperand(i); 5575 unsigned BitPos = i * EltBitSize; 5576 5577 if (OpVal.getOpcode() == ISD::UNDEF) 5578 SplatUndef |= APInt::getBitsSet(sz, BitPos, BitPos +EltBitSize); 5579 else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) 5580 SplatValue |= (APInt(CN->getAPIntValue()).zextOrTrunc(EltBitSize). 5581 zextOrTrunc(sz) << BitPos); 5582 else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) 5583 SplatValue |= CN->getValueAPF().bitcastToAPInt().zextOrTrunc(sz) <<BitPos; 5584 else 5585 return false; 5586 } 5587 5588 // The build_vector is all constants or undefs. Find the smallest element 5589 // size that splats the vector. 5590 5591 HasAnyUndefs = (SplatUndef != 0); 5592 while (sz > 8) { 5593 5594 unsigned HalfSize = sz / 2; 5595 APInt HighValue = APInt(SplatValue).lshr(HalfSize).trunc(HalfSize); 5596 APInt LowValue = APInt(SplatValue).trunc(HalfSize); 5597 APInt HighUndef = APInt(SplatUndef).lshr(HalfSize).trunc(HalfSize); 5598 APInt LowUndef = APInt(SplatUndef).trunc(HalfSize); 5599 5600 // If the two halves do not match (ignoring undef bits), stop here. 5601 if ((HighValue & ~LowUndef) != (LowValue & ~HighUndef) || 5602 MinSplatBits > HalfSize) 5603 break; 5604 5605 SplatValue = HighValue | LowValue; 5606 SplatUndef = HighUndef & LowUndef; 5607 5608 sz = HalfSize; 5609 } 5610 5611 SplatBitSize = sz; 5612 return true; 5613} 5614