SelectionDAG.cpp revision 43247a157b613dbf3caedacdbb171a9d653e3ef5
1//===-- SelectionDAG.cpp - Implement the SelectionDAG data structures -----===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAG class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/Constants.h" 16#include "llvm/GlobalValue.h" 17#include "llvm/Assembly/Writer.h" 18#include "llvm/CodeGen/MachineBasicBlock.h" 19#include "llvm/Support/MathExtras.h" 20#include "llvm/Target/MRegisterInfo.h" 21#include "llvm/Target/TargetLowering.h" 22#include "llvm/Target/TargetInstrInfo.h" 23#include "llvm/Target/TargetMachine.h" 24#include <iostream> 25#include <set> 26#include <cmath> 27#include <algorithm> 28using namespace llvm; 29 30static bool isCommutativeBinOp(unsigned Opcode) { 31 switch (Opcode) { 32 case ISD::ADD: 33 case ISD::MUL: 34 case ISD::AND: 35 case ISD::OR: 36 case ISD::XOR: return true; 37 default: return false; // FIXME: Need commutative info for user ops! 38 } 39} 40 41static bool isAssociativeBinOp(unsigned Opcode) { 42 switch (Opcode) { 43 case ISD::ADD: 44 case ISD::MUL: 45 case ISD::AND: 46 case ISD::OR: 47 case ISD::XOR: return true; 48 default: return false; // FIXME: Need associative info for user ops! 49 } 50} 51 52// isInvertibleForFree - Return true if there is no cost to emitting the logical 53// inverse of this node. 54static bool isInvertibleForFree(SDOperand N) { 55 if (isa<ConstantSDNode>(N.Val)) return true; 56 if (N.Val->getOpcode() == ISD::SETCC && N.Val->hasOneUse()) 57 return true; 58 return false; 59} 60 61//===----------------------------------------------------------------------===// 62// ConstantFPSDNode Class 63//===----------------------------------------------------------------------===// 64 65/// isExactlyValue - We don't rely on operator== working on double values, as 66/// it returns true for things that are clearly not equal, like -0.0 and 0.0. 67/// As such, this method can be used to do an exact bit-for-bit comparison of 68/// two floating point values. 69bool ConstantFPSDNode::isExactlyValue(double V) const { 70 return DoubleToBits(V) == DoubleToBits(Value); 71} 72 73//===----------------------------------------------------------------------===// 74// ISD Class 75//===----------------------------------------------------------------------===// 76 77/// getSetCCSwappedOperands - Return the operation corresponding to (Y op X) 78/// when given the operation for (X op Y). 79ISD::CondCode ISD::getSetCCSwappedOperands(ISD::CondCode Operation) { 80 // To perform this operation, we just need to swap the L and G bits of the 81 // operation. 82 unsigned OldL = (Operation >> 2) & 1; 83 unsigned OldG = (Operation >> 1) & 1; 84 return ISD::CondCode((Operation & ~6) | // Keep the N, U, E bits 85 (OldL << 1) | // New G bit 86 (OldG << 2)); // New L bit. 87} 88 89/// getSetCCInverse - Return the operation corresponding to !(X op Y), where 90/// 'op' is a valid SetCC operation. 91ISD::CondCode ISD::getSetCCInverse(ISD::CondCode Op, bool isInteger) { 92 unsigned Operation = Op; 93 if (isInteger) 94 Operation ^= 7; // Flip L, G, E bits, but not U. 95 else 96 Operation ^= 15; // Flip all of the condition bits. 97 if (Operation > ISD::SETTRUE2) 98 Operation &= ~8; // Don't let N and U bits get set. 99 return ISD::CondCode(Operation); 100} 101 102 103/// isSignedOp - For an integer comparison, return 1 if the comparison is a 104/// signed operation and 2 if the result is an unsigned comparison. Return zero 105/// if the operation does not depend on the sign of the input (setne and seteq). 106static int isSignedOp(ISD::CondCode Opcode) { 107 switch (Opcode) { 108 default: assert(0 && "Illegal integer setcc operation!"); 109 case ISD::SETEQ: 110 case ISD::SETNE: return 0; 111 case ISD::SETLT: 112 case ISD::SETLE: 113 case ISD::SETGT: 114 case ISD::SETGE: return 1; 115 case ISD::SETULT: 116 case ISD::SETULE: 117 case ISD::SETUGT: 118 case ISD::SETUGE: return 2; 119 } 120} 121 122/// getSetCCOrOperation - Return the result of a logical OR between different 123/// comparisons of identical values: ((X op1 Y) | (X op2 Y)). This function 124/// returns SETCC_INVALID if it is not possible to represent the resultant 125/// comparison. 126ISD::CondCode ISD::getSetCCOrOperation(ISD::CondCode Op1, ISD::CondCode Op2, 127 bool isInteger) { 128 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 129 // Cannot fold a signed integer setcc with an unsigned integer setcc. 130 return ISD::SETCC_INVALID; 131 132 unsigned Op = Op1 | Op2; // Combine all of the condition bits. 133 134 // If the N and U bits get set then the resultant comparison DOES suddenly 135 // care about orderedness, and is true when ordered. 136 if (Op > ISD::SETTRUE2) 137 Op &= ~16; // Clear the N bit. 138 return ISD::CondCode(Op); 139} 140 141/// getSetCCAndOperation - Return the result of a logical AND between different 142/// comparisons of identical values: ((X op1 Y) & (X op2 Y)). This 143/// function returns zero if it is not possible to represent the resultant 144/// comparison. 145ISD::CondCode ISD::getSetCCAndOperation(ISD::CondCode Op1, ISD::CondCode Op2, 146 bool isInteger) { 147 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 148 // Cannot fold a signed setcc with an unsigned setcc. 149 return ISD::SETCC_INVALID; 150 151 // Combine all of the condition bits. 152 return ISD::CondCode(Op1 & Op2); 153} 154 155const TargetMachine &SelectionDAG::getTarget() const { 156 return TLI.getTargetMachine(); 157} 158 159//===----------------------------------------------------------------------===// 160// SelectionDAG Class 161//===----------------------------------------------------------------------===// 162 163/// RemoveDeadNodes - This method deletes all unreachable nodes in the 164/// SelectionDAG, including nodes (like loads) that have uses of their token 165/// chain but no other uses and no side effect. If a node is passed in as an 166/// argument, it is used as the seed for node deletion. 167void SelectionDAG::RemoveDeadNodes(SDNode *N) { 168 std::set<SDNode*> AllNodeSet(AllNodes.begin(), AllNodes.end()); 169 170 // Create a dummy node (which is not added to allnodes), that adds a reference 171 // to the root node, preventing it from being deleted. 172 SDNode *DummyNode = new SDNode(ISD::EntryToken, getRoot()); 173 174 // If we have a hint to start from, use it. 175 if (N) DeleteNodeIfDead(N, &AllNodeSet); 176 177 Restart: 178 unsigned NumNodes = AllNodeSet.size(); 179 for (std::set<SDNode*>::iterator I = AllNodeSet.begin(), E = AllNodeSet.end(); 180 I != E; ++I) { 181 // Try to delete this node. 182 DeleteNodeIfDead(*I, &AllNodeSet); 183 184 // If we actually deleted any nodes, do not use invalid iterators in 185 // AllNodeSet. 186 if (AllNodeSet.size() != NumNodes) 187 goto Restart; 188 } 189 190 // Restore AllNodes. 191 if (AllNodes.size() != NumNodes) 192 AllNodes.assign(AllNodeSet.begin(), AllNodeSet.end()); 193 194 // If the root changed (e.g. it was a dead load, update the root). 195 setRoot(DummyNode->getOperand(0)); 196 197 // Now that we are done with the dummy node, delete it. 198 DummyNode->getOperand(0).Val->removeUser(DummyNode); 199 delete DummyNode; 200} 201 202 203void SelectionDAG::DeleteNodeIfDead(SDNode *N, void *NodeSet) { 204 if (!N->use_empty()) 205 return; 206 207 // Okay, we really are going to delete this node. First take this out of the 208 // appropriate CSE map. 209 RemoveNodeFromCSEMaps(N); 210 211 // Next, brutally remove the operand list. This is safe to do, as there are 212 // no cycles in the graph. 213 while (!N->Operands.empty()) { 214 SDNode *O = N->Operands.back().Val; 215 N->Operands.pop_back(); 216 O->removeUser(N); 217 218 // Now that we removed this operand, see if there are no uses of it left. 219 DeleteNodeIfDead(O, NodeSet); 220 } 221 222 // Remove the node from the nodes set and delete it. 223 std::set<SDNode*> &AllNodeSet = *(std::set<SDNode*>*)NodeSet; 224 AllNodeSet.erase(N); 225 226 // Now that the node is gone, check to see if any of the operands of this node 227 // are dead now. 228 delete N; 229} 230 231/// RemoveNodeFromCSEMaps - Take the specified node out of the CSE map that 232/// correspond to it. This is useful when we're about to delete or repurpose 233/// the node. We don't want future request for structurally identical nodes 234/// to return N anymore. 235void SelectionDAG::RemoveNodeFromCSEMaps(SDNode *N) { 236 switch (N->getOpcode()) { 237 case ISD::Constant: 238 Constants.erase(std::make_pair(cast<ConstantSDNode>(N)->getValue(), 239 N->getValueType(0))); 240 break; 241 case ISD::TargetConstant: 242 TargetConstants.erase(std::make_pair(cast<ConstantSDNode>(N)->getValue(), 243 N->getValueType(0))); 244 break; 245 case ISD::ConstantFP: { 246 uint64_t V = DoubleToBits(cast<ConstantFPSDNode>(N)->getValue()); 247 ConstantFPs.erase(std::make_pair(V, N->getValueType(0))); 248 break; 249 } 250 case ISD::CONDCODE: 251 assert(CondCodeNodes[cast<CondCodeSDNode>(N)->get()] && 252 "Cond code doesn't exist!"); 253 CondCodeNodes[cast<CondCodeSDNode>(N)->get()] = 0; 254 break; 255 case ISD::GlobalAddress: 256 GlobalValues.erase(cast<GlobalAddressSDNode>(N)->getGlobal()); 257 break; 258 case ISD::TargetGlobalAddress: 259 TargetGlobalValues.erase(cast<GlobalAddressSDNode>(N)->getGlobal()); 260 break; 261 case ISD::FrameIndex: 262 FrameIndices.erase(cast<FrameIndexSDNode>(N)->getIndex()); 263 break; 264 case ISD::TargetFrameIndex: 265 TargetFrameIndices.erase(cast<FrameIndexSDNode>(N)->getIndex()); 266 break; 267 case ISD::ConstantPool: 268 ConstantPoolIndices.erase(cast<ConstantPoolSDNode>(N)->getIndex()); 269 break; 270 case ISD::TargetConstantPool: 271 TargetConstantPoolIndices.erase(cast<ConstantPoolSDNode>(N)->getIndex()); 272 break; 273 case ISD::BasicBlock: 274 BBNodes.erase(cast<BasicBlockSDNode>(N)->getBasicBlock()); 275 break; 276 case ISD::ExternalSymbol: 277 ExternalSymbols.erase(cast<ExternalSymbolSDNode>(N)->getSymbol()); 278 break; 279 case ISD::VALUETYPE: 280 ValueTypeNodes[cast<VTSDNode>(N)->getVT()] = 0; 281 break; 282 case ISD::Register: 283 RegNodes[cast<RegisterSDNode>(N)->getReg()] = 0; 284 break; 285 case ISD::SRCVALUE: { 286 SrcValueSDNode *SVN = cast<SrcValueSDNode>(N); 287 ValueNodes.erase(std::make_pair(SVN->getValue(), SVN->getOffset())); 288 break; 289 } 290 case ISD::LOAD: 291 Loads.erase(std::make_pair(N->getOperand(1), 292 std::make_pair(N->getOperand(0), 293 N->getValueType(0)))); 294 break; 295 default: 296 if (N->getNumOperands() == 1) 297 UnaryOps.erase(std::make_pair(N->getOpcode(), 298 std::make_pair(N->getOperand(0), 299 N->getValueType(0)))); 300 else if (N->getNumOperands() == 2) 301 BinaryOps.erase(std::make_pair(N->getOpcode(), 302 std::make_pair(N->getOperand(0), 303 N->getOperand(1)))); 304 else if (N->getNumValues() == 1) { 305 std::vector<SDOperand> Ops(N->op_begin(), N->op_end()); 306 OneResultNodes.erase(std::make_pair(N->getOpcode(), 307 std::make_pair(N->getValueType(0), 308 Ops))); 309 } else { 310 // Remove the node from the ArbitraryNodes map. 311 std::vector<MVT::ValueType> RV(N->value_begin(), N->value_end()); 312 std::vector<SDOperand> Ops(N->op_begin(), N->op_end()); 313 ArbitraryNodes.erase(std::make_pair(N->getOpcode(), 314 std::make_pair(RV, Ops))); 315 } 316 break; 317 } 318} 319 320/// AddNonLeafNodeToCSEMaps - Add the specified node back to the CSE maps. It 321/// has been taken out and modified in some way. If the specified node already 322/// exists in the CSE maps, do not modify the maps, but return the existing node 323/// instead. If it doesn't exist, add it and return null. 324/// 325SDNode *SelectionDAG::AddNonLeafNodeToCSEMaps(SDNode *N) { 326 assert(N->getNumOperands() && "This is a leaf node!"); 327 if (N->getOpcode() == ISD::LOAD) { 328 SDNode *&L = Loads[std::make_pair(N->getOperand(1), 329 std::make_pair(N->getOperand(0), 330 N->getValueType(0)))]; 331 if (L) return L; 332 L = N; 333 } else if (N->getNumOperands() == 1) { 334 SDNode *&U = UnaryOps[std::make_pair(N->getOpcode(), 335 std::make_pair(N->getOperand(0), 336 N->getValueType(0)))]; 337 if (U) return U; 338 U = N; 339 } else if (N->getNumOperands() == 2) { 340 SDNode *&B = BinaryOps[std::make_pair(N->getOpcode(), 341 std::make_pair(N->getOperand(0), 342 N->getOperand(1)))]; 343 if (B) return B; 344 B = N; 345 } else if (N->getNumValues() == 1) { 346 std::vector<SDOperand> Ops(N->op_begin(), N->op_end()); 347 SDNode *&ORN = OneResultNodes[std::make_pair(N->getOpcode(), 348 std::make_pair(N->getValueType(0), Ops))]; 349 if (ORN) return ORN; 350 ORN = N; 351 } else { 352 // Remove the node from the ArbitraryNodes map. 353 std::vector<MVT::ValueType> RV(N->value_begin(), N->value_end()); 354 std::vector<SDOperand> Ops(N->op_begin(), N->op_end()); 355 SDNode *&AN = ArbitraryNodes[std::make_pair(N->getOpcode(), 356 std::make_pair(RV, Ops))]; 357 if (AN) return AN; 358 AN = N; 359 } 360 return 0; 361 362} 363 364 365 366SelectionDAG::~SelectionDAG() { 367 for (unsigned i = 0, e = AllNodes.size(); i != e; ++i) 368 delete AllNodes[i]; 369} 370 371SDOperand SelectionDAG::getZeroExtendInReg(SDOperand Op, MVT::ValueType VT) { 372 if (Op.getValueType() == VT) return Op; 373 int64_t Imm = ~0ULL >> (64-MVT::getSizeInBits(VT)); 374 return getNode(ISD::AND, Op.getValueType(), Op, 375 getConstant(Imm, Op.getValueType())); 376} 377 378SDOperand SelectionDAG::getConstant(uint64_t Val, MVT::ValueType VT) { 379 assert(MVT::isInteger(VT) && "Cannot create FP integer constant!"); 380 // Mask out any bits that are not valid for this constant. 381 if (VT != MVT::i64) 382 Val &= ((uint64_t)1 << MVT::getSizeInBits(VT)) - 1; 383 384 SDNode *&N = Constants[std::make_pair(Val, VT)]; 385 if (N) return SDOperand(N, 0); 386 N = new ConstantSDNode(false, Val, VT); 387 AllNodes.push_back(N); 388 return SDOperand(N, 0); 389} 390 391SDOperand SelectionDAG::getTargetConstant(uint64_t Val, MVT::ValueType VT) { 392 assert(MVT::isInteger(VT) && "Cannot create FP integer constant!"); 393 // Mask out any bits that are not valid for this constant. 394 if (VT != MVT::i64) 395 Val &= ((uint64_t)1 << MVT::getSizeInBits(VT)) - 1; 396 397 SDNode *&N = TargetConstants[std::make_pair(Val, VT)]; 398 if (N) return SDOperand(N, 0); 399 N = new ConstantSDNode(true, Val, VT); 400 AllNodes.push_back(N); 401 return SDOperand(N, 0); 402} 403 404SDOperand SelectionDAG::getConstantFP(double Val, MVT::ValueType VT) { 405 assert(MVT::isFloatingPoint(VT) && "Cannot create integer FP constant!"); 406 if (VT == MVT::f32) 407 Val = (float)Val; // Mask out extra precision. 408 409 // Do the map lookup using the actual bit pattern for the floating point 410 // value, so that we don't have problems with 0.0 comparing equal to -0.0, and 411 // we don't have issues with SNANs. 412 SDNode *&N = ConstantFPs[std::make_pair(DoubleToBits(Val), VT)]; 413 if (N) return SDOperand(N, 0); 414 N = new ConstantFPSDNode(Val, VT); 415 AllNodes.push_back(N); 416 return SDOperand(N, 0); 417} 418 419 420 421SDOperand SelectionDAG::getGlobalAddress(const GlobalValue *GV, 422 MVT::ValueType VT) { 423 SDNode *&N = GlobalValues[GV]; 424 if (N) return SDOperand(N, 0); 425 N = new GlobalAddressSDNode(false, GV, VT); 426 AllNodes.push_back(N); 427 return SDOperand(N, 0); 428} 429 430SDOperand SelectionDAG::getTargetGlobalAddress(const GlobalValue *GV, 431 MVT::ValueType VT) { 432 SDNode *&N = TargetGlobalValues[GV]; 433 if (N) return SDOperand(N, 0); 434 N = new GlobalAddressSDNode(true, GV, VT); 435 AllNodes.push_back(N); 436 return SDOperand(N, 0); 437} 438 439SDOperand SelectionDAG::getFrameIndex(int FI, MVT::ValueType VT) { 440 SDNode *&N = FrameIndices[FI]; 441 if (N) return SDOperand(N, 0); 442 N = new FrameIndexSDNode(FI, VT, false); 443 AllNodes.push_back(N); 444 return SDOperand(N, 0); 445} 446 447SDOperand SelectionDAG::getTargetFrameIndex(int FI, MVT::ValueType VT) { 448 SDNode *&N = TargetFrameIndices[FI]; 449 if (N) return SDOperand(N, 0); 450 N = new FrameIndexSDNode(FI, VT, true); 451 AllNodes.push_back(N); 452 return SDOperand(N, 0); 453} 454 455SDOperand SelectionDAG::getConstantPool(unsigned CPIdx, MVT::ValueType VT) { 456 SDNode *N = ConstantPoolIndices[CPIdx]; 457 if (N) return SDOperand(N, 0); 458 N = new ConstantPoolSDNode(CPIdx, VT, false); 459 AllNodes.push_back(N); 460 return SDOperand(N, 0); 461} 462 463SDOperand SelectionDAG::getTargetConstantPool(unsigned CPIdx, 464 MVT::ValueType VT) { 465 SDNode *N = TargetConstantPoolIndices[CPIdx]; 466 if (N) return SDOperand(N, 0); 467 N = new ConstantPoolSDNode(CPIdx, VT, true); 468 AllNodes.push_back(N); 469 return SDOperand(N, 0); 470} 471 472SDOperand SelectionDAG::getBasicBlock(MachineBasicBlock *MBB) { 473 SDNode *&N = BBNodes[MBB]; 474 if (N) return SDOperand(N, 0); 475 N = new BasicBlockSDNode(MBB); 476 AllNodes.push_back(N); 477 return SDOperand(N, 0); 478} 479 480SDOperand SelectionDAG::getValueType(MVT::ValueType VT) { 481 if ((unsigned)VT >= ValueTypeNodes.size()) 482 ValueTypeNodes.resize(VT+1); 483 if (ValueTypeNodes[VT] == 0) { 484 ValueTypeNodes[VT] = new VTSDNode(VT); 485 AllNodes.push_back(ValueTypeNodes[VT]); 486 } 487 488 return SDOperand(ValueTypeNodes[VT], 0); 489} 490 491SDOperand SelectionDAG::getExternalSymbol(const char *Sym, MVT::ValueType VT) { 492 SDNode *&N = ExternalSymbols[Sym]; 493 if (N) return SDOperand(N, 0); 494 N = new ExternalSymbolSDNode(Sym, VT); 495 AllNodes.push_back(N); 496 return SDOperand(N, 0); 497} 498 499SDOperand SelectionDAG::getCondCode(ISD::CondCode Cond) { 500 if ((unsigned)Cond >= CondCodeNodes.size()) 501 CondCodeNodes.resize(Cond+1); 502 503 if (CondCodeNodes[Cond] == 0) { 504 CondCodeNodes[Cond] = new CondCodeSDNode(Cond); 505 AllNodes.push_back(CondCodeNodes[Cond]); 506 } 507 return SDOperand(CondCodeNodes[Cond], 0); 508} 509 510SDOperand SelectionDAG::getRegister(unsigned Reg, MVT::ValueType VT) { 511 if (Reg >= RegNodes.size()) 512 RegNodes.resize(Reg+1); 513 RegisterSDNode *&Result = RegNodes[Reg]; 514 if (Result) { 515 assert(Result->getValueType(0) == VT && 516 "Inconsistent value types for machine registers"); 517 } else { 518 Result = new RegisterSDNode(Reg, VT); 519 AllNodes.push_back(Result); 520 } 521 return SDOperand(Result, 0); 522} 523 524SDOperand SelectionDAG::SimplifySetCC(MVT::ValueType VT, SDOperand N1, 525 SDOperand N2, ISD::CondCode Cond) { 526 // These setcc operations always fold. 527 switch (Cond) { 528 default: break; 529 case ISD::SETFALSE: 530 case ISD::SETFALSE2: return getConstant(0, VT); 531 case ISD::SETTRUE: 532 case ISD::SETTRUE2: return getConstant(1, VT); 533 } 534 535 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val)) { 536 uint64_t C2 = N2C->getValue(); 537 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) { 538 uint64_t C1 = N1C->getValue(); 539 540 // Sign extend the operands if required 541 if (ISD::isSignedIntSetCC(Cond)) { 542 C1 = N1C->getSignExtended(); 543 C2 = N2C->getSignExtended(); 544 } 545 546 switch (Cond) { 547 default: assert(0 && "Unknown integer setcc!"); 548 case ISD::SETEQ: return getConstant(C1 == C2, VT); 549 case ISD::SETNE: return getConstant(C1 != C2, VT); 550 case ISD::SETULT: return getConstant(C1 < C2, VT); 551 case ISD::SETUGT: return getConstant(C1 > C2, VT); 552 case ISD::SETULE: return getConstant(C1 <= C2, VT); 553 case ISD::SETUGE: return getConstant(C1 >= C2, VT); 554 case ISD::SETLT: return getConstant((int64_t)C1 < (int64_t)C2, VT); 555 case ISD::SETGT: return getConstant((int64_t)C1 > (int64_t)C2, VT); 556 case ISD::SETLE: return getConstant((int64_t)C1 <= (int64_t)C2, VT); 557 case ISD::SETGE: return getConstant((int64_t)C1 >= (int64_t)C2, VT); 558 } 559 } else { 560 // If the LHS is a ZERO_EXTEND, perform the comparison on the input. 561 if (N1.getOpcode() == ISD::ZERO_EXTEND) { 562 unsigned InSize = MVT::getSizeInBits(N1.getOperand(0).getValueType()); 563 564 // If the comparison constant has bits in the upper part, the 565 // zero-extended value could never match. 566 if (C2 & (~0ULL << InSize)) { 567 unsigned VSize = MVT::getSizeInBits(N1.getValueType()); 568 switch (Cond) { 569 case ISD::SETUGT: 570 case ISD::SETUGE: 571 case ISD::SETEQ: return getConstant(0, VT); 572 case ISD::SETULT: 573 case ISD::SETULE: 574 case ISD::SETNE: return getConstant(1, VT); 575 case ISD::SETGT: 576 case ISD::SETGE: 577 // True if the sign bit of C2 is set. 578 return getConstant((C2 & (1ULL << VSize)) != 0, VT); 579 case ISD::SETLT: 580 case ISD::SETLE: 581 // True if the sign bit of C2 isn't set. 582 return getConstant((C2 & (1ULL << VSize)) == 0, VT); 583 default: 584 break; 585 } 586 } 587 588 // Otherwise, we can perform the comparison with the low bits. 589 switch (Cond) { 590 case ISD::SETEQ: 591 case ISD::SETNE: 592 case ISD::SETUGT: 593 case ISD::SETUGE: 594 case ISD::SETULT: 595 case ISD::SETULE: 596 return getSetCC(VT, N1.getOperand(0), 597 getConstant(C2, N1.getOperand(0).getValueType()), 598 Cond); 599 default: 600 break; // todo, be more careful with signed comparisons 601 } 602 } else if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG && 603 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 604 MVT::ValueType ExtSrcTy = cast<VTSDNode>(N1.getOperand(1))->getVT(); 605 unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy); 606 MVT::ValueType ExtDstTy = N1.getValueType(); 607 unsigned ExtDstTyBits = MVT::getSizeInBits(ExtDstTy); 608 609 // If the extended part has any inconsistent bits, it cannot ever 610 // compare equal. In other words, they have to be all ones or all 611 // zeros. 612 uint64_t ExtBits = 613 (~0ULL >> 64-ExtSrcTyBits) & (~0ULL << (ExtDstTyBits-1)); 614 if ((C2 & ExtBits) != 0 && (C2 & ExtBits) != ExtBits) 615 return getConstant(Cond == ISD::SETNE, VT); 616 617 // Otherwise, make this a use of a zext. 618 return getSetCC(VT, getZeroExtendInReg(N1.getOperand(0), ExtSrcTy), 619 getConstant(C2 & (~0ULL >> 64-ExtSrcTyBits), ExtDstTy), 620 Cond); 621 } 622 623 uint64_t MinVal, MaxVal; 624 unsigned OperandBitSize = MVT::getSizeInBits(N2C->getValueType(0)); 625 if (ISD::isSignedIntSetCC(Cond)) { 626 MinVal = 1ULL << (OperandBitSize-1); 627 if (OperandBitSize != 1) // Avoid X >> 64, which is undefined. 628 MaxVal = ~0ULL >> (65-OperandBitSize); 629 else 630 MaxVal = 0; 631 } else { 632 MinVal = 0; 633 MaxVal = ~0ULL >> (64-OperandBitSize); 634 } 635 636 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 637 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 638 if (C2 == MinVal) return getConstant(1, VT); // X >= MIN --> true 639 --C2; // X >= C1 --> X > (C1-1) 640 return getSetCC(VT, N1, getConstant(C2, N2.getValueType()), 641 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); 642 } 643 644 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 645 if (C2 == MaxVal) return getConstant(1, VT); // X <= MAX --> true 646 ++C2; // X <= C1 --> X < (C1+1) 647 return getSetCC(VT, N1, getConstant(C2, N2.getValueType()), 648 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); 649 } 650 651 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C2 == MinVal) 652 return getConstant(0, VT); // X < MIN --> false 653 654 // Canonicalize setgt X, Min --> setne X, Min 655 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C2 == MinVal) 656 return getSetCC(VT, N1, N2, ISD::SETNE); 657 658 // If we have setult X, 1, turn it into seteq X, 0 659 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C2 == MinVal+1) 660 return getSetCC(VT, N1, getConstant(MinVal, N1.getValueType()), 661 ISD::SETEQ); 662 // If we have setugt X, Max-1, turn it into seteq X, Max 663 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C2 == MaxVal-1) 664 return getSetCC(VT, N1, getConstant(MaxVal, N1.getValueType()), 665 ISD::SETEQ); 666 667 // If we have "setcc X, C1", check to see if we can shrink the immediate 668 // by changing cc. 669 670 // SETUGT X, SINTMAX -> SETLT X, 0 671 if (Cond == ISD::SETUGT && OperandBitSize != 1 && 672 C2 == (~0ULL >> (65-OperandBitSize))) 673 return getSetCC(VT, N1, getConstant(0, N2.getValueType()), ISD::SETLT); 674 675 // FIXME: Implement the rest of these. 676 677 678 // Fold bit comparisons when we can. 679 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 680 VT == N1.getValueType() && N1.getOpcode() == ISD::AND) 681 if (ConstantSDNode *AndRHS = 682 dyn_cast<ConstantSDNode>(N1.getOperand(1))) { 683 if (Cond == ISD::SETNE && C2 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 684 // Perform the xform if the AND RHS is a single bit. 685 if ((AndRHS->getValue() & (AndRHS->getValue()-1)) == 0) { 686 return getNode(ISD::SRL, VT, N1, 687 getConstant(Log2_64(AndRHS->getValue()), 688 TLI.getShiftAmountTy())); 689 } 690 } else if (Cond == ISD::SETEQ && C2 == AndRHS->getValue()) { 691 // (X & 8) == 8 --> (X & 8) >> 3 692 // Perform the xform if C2 is a single bit. 693 if ((C2 & (C2-1)) == 0) { 694 return getNode(ISD::SRL, VT, N1, 695 getConstant(Log2_64(C2),TLI.getShiftAmountTy())); 696 } 697 } 698 } 699 } 700 } else if (isa<ConstantSDNode>(N1.Val)) { 701 // Ensure that the constant occurs on the RHS. 702 return getSetCC(VT, N2, N1, ISD::getSetCCSwappedOperands(Cond)); 703 } 704 705 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.Val)) 706 if (ConstantFPSDNode *N2C = dyn_cast<ConstantFPSDNode>(N2.Val)) { 707 double C1 = N1C->getValue(), C2 = N2C->getValue(); 708 709 switch (Cond) { 710 default: break; // FIXME: Implement the rest of these! 711 case ISD::SETEQ: return getConstant(C1 == C2, VT); 712 case ISD::SETNE: return getConstant(C1 != C2, VT); 713 case ISD::SETLT: return getConstant(C1 < C2, VT); 714 case ISD::SETGT: return getConstant(C1 > C2, VT); 715 case ISD::SETLE: return getConstant(C1 <= C2, VT); 716 case ISD::SETGE: return getConstant(C1 >= C2, VT); 717 } 718 } else { 719 // Ensure that the constant occurs on the RHS. 720 return getSetCC(VT, N2, N1, ISD::getSetCCSwappedOperands(Cond)); 721 } 722 723 if (N1 == N2) { 724 // We can always fold X == Y for integer setcc's. 725 if (MVT::isInteger(N1.getValueType())) 726 return getConstant(ISD::isTrueWhenEqual(Cond), VT); 727 unsigned UOF = ISD::getUnorderedFlavor(Cond); 728 if (UOF == 2) // FP operators that are undefined on NaNs. 729 return getConstant(ISD::isTrueWhenEqual(Cond), VT); 730 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 731 return getConstant(UOF, VT); 732 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 733 // if it is not already. 734 ISD::CondCode NewCond = UOF == 0 ? ISD::SETUO : ISD::SETO; 735 if (NewCond != Cond) 736 return getSetCC(VT, N1, N2, NewCond); 737 } 738 739 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 740 MVT::isInteger(N1.getValueType())) { 741 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 742 N1.getOpcode() == ISD::XOR) { 743 // Simplify (X+Y) == (X+Z) --> Y == Z 744 if (N1.getOpcode() == N2.getOpcode()) { 745 if (N1.getOperand(0) == N2.getOperand(0)) 746 return getSetCC(VT, N1.getOperand(1), N2.getOperand(1), Cond); 747 if (N1.getOperand(1) == N2.getOperand(1)) 748 return getSetCC(VT, N1.getOperand(0), N2.getOperand(0), Cond); 749 if (isCommutativeBinOp(N1.getOpcode())) { 750 // If X op Y == Y op X, try other combinations. 751 if (N1.getOperand(0) == N2.getOperand(1)) 752 return getSetCC(VT, N1.getOperand(1), N2.getOperand(0), Cond); 753 if (N1.getOperand(1) == N2.getOperand(0)) 754 return getSetCC(VT, N1.getOperand(1), N2.getOperand(1), Cond); 755 } 756 } 757 758 // FIXME: move this stuff to the DAG Combiner when it exists! 759 760 // Simplify (X+Z) == X --> Z == 0 761 if (N1.getOperand(0) == N2) 762 return getSetCC(VT, N1.getOperand(1), 763 getConstant(0, N1.getValueType()), Cond); 764 if (N1.getOperand(1) == N2) { 765 if (isCommutativeBinOp(N1.getOpcode())) 766 return getSetCC(VT, N1.getOperand(0), 767 getConstant(0, N1.getValueType()), Cond); 768 else { 769 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 770 // (Z-X) == X --> Z == X<<1 771 return getSetCC(VT, N1.getOperand(0), 772 getNode(ISD::SHL, N2.getValueType(), 773 N2, getConstant(1, TLI.getShiftAmountTy())), 774 Cond); 775 } 776 } 777 } 778 779 if (N2.getOpcode() == ISD::ADD || N2.getOpcode() == ISD::SUB || 780 N2.getOpcode() == ISD::XOR) { 781 // Simplify X == (X+Z) --> Z == 0 782 if (N2.getOperand(0) == N1) { 783 return getSetCC(VT, N2.getOperand(1), 784 getConstant(0, N2.getValueType()), Cond); 785 } else if (N2.getOperand(1) == N1) { 786 if (isCommutativeBinOp(N2.getOpcode())) { 787 return getSetCC(VT, N2.getOperand(0), 788 getConstant(0, N2.getValueType()), Cond); 789 } else { 790 assert(N2.getOpcode() == ISD::SUB && "Unexpected operation!"); 791 // X == (Z-X) --> X<<1 == Z 792 return getSetCC(VT, getNode(ISD::SHL, N2.getValueType(), N1, 793 getConstant(1, TLI.getShiftAmountTy())), 794 N2.getOperand(0), Cond); 795 } 796 } 797 } 798 } 799 800 // Fold away ALL boolean setcc's. 801 if (N1.getValueType() == MVT::i1) { 802 switch (Cond) { 803 default: assert(0 && "Unknown integer setcc!"); 804 case ISD::SETEQ: // X == Y -> (X^Y)^1 805 N1 = getNode(ISD::XOR, MVT::i1, 806 getNode(ISD::XOR, MVT::i1, N1, N2), 807 getConstant(1, MVT::i1)); 808 break; 809 case ISD::SETNE: // X != Y --> (X^Y) 810 N1 = getNode(ISD::XOR, MVT::i1, N1, N2); 811 break; 812 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y 813 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y 814 N1 = getNode(ISD::AND, MVT::i1, N2, 815 getNode(ISD::XOR, MVT::i1, N1, getConstant(1, MVT::i1))); 816 break; 817 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X 818 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X 819 N1 = getNode(ISD::AND, MVT::i1, N1, 820 getNode(ISD::XOR, MVT::i1, N2, getConstant(1, MVT::i1))); 821 break; 822 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y 823 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y 824 N1 = getNode(ISD::OR, MVT::i1, N2, 825 getNode(ISD::XOR, MVT::i1, N1, getConstant(1, MVT::i1))); 826 break; 827 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X 828 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X 829 N1 = getNode(ISD::OR, MVT::i1, N1, 830 getNode(ISD::XOR, MVT::i1, N2, getConstant(1, MVT::i1))); 831 break; 832 } 833 if (VT != MVT::i1) 834 N1 = getNode(ISD::ZERO_EXTEND, VT, N1); 835 return N1; 836 } 837 838 // Could not fold it. 839 return SDOperand(); 840} 841 842SDOperand SelectionDAG::SimplifySelectCC(SDOperand N1, SDOperand N2, 843 SDOperand N3, SDOperand N4, 844 ISD::CondCode CC) { 845 MVT::ValueType VT = N3.getValueType(); 846 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 847 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val); 848 ConstantSDNode *N4C = dyn_cast<ConstantSDNode>(N4.Val); 849 850 // Check to see if we can simplify the select into an fabs node 851 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N2)) { 852 // Allow either -0.0 or 0.0 853 if (CFP->getValue() == 0.0) { 854 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 855 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 856 N1 == N3 && N4.getOpcode() == ISD::FNEG && 857 N1 == N4.getOperand(0)) 858 return getNode(ISD::FABS, VT, N1); 859 860 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 861 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 862 N1 == N4 && N3.getOpcode() == ISD::FNEG && 863 N3.getOperand(0) == N4) 864 return getNode(ISD::FABS, VT, N4); 865 } 866 } 867 868 // Check to see if we can perform the "gzip trick", transforming 869 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A 870 if (N2C && N2C->isNullValue() && N4C && N4C->isNullValue() && 871 MVT::isInteger(N1.getValueType()) && 872 MVT::isInteger(N3.getValueType()) && CC == ISD::SETLT) { 873 MVT::ValueType XType = N1.getValueType(); 874 MVT::ValueType AType = N3.getValueType(); 875 if (XType >= AType) { 876 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 877 // single-bit constant. FIXME: remove once the dag combiner 878 // exists. 879 if (N3C && ((N3C->getValue() & (N3C->getValue()-1)) == 0)) { 880 unsigned ShCtV = Log2_64(N3C->getValue()); 881 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1; 882 SDOperand ShCt = getConstant(ShCtV, TLI.getShiftAmountTy()); 883 SDOperand Shift = getNode(ISD::SRL, XType, N1, ShCt); 884 if (XType > AType) 885 Shift = getNode(ISD::TRUNCATE, AType, Shift); 886 return getNode(ISD::AND, AType, Shift, N3); 887 } 888 SDOperand Shift = getNode(ISD::SRA, XType, N1, 889 getConstant(MVT::getSizeInBits(XType)-1, 890 TLI.getShiftAmountTy())); 891 if (XType > AType) 892 Shift = getNode(ISD::TRUNCATE, AType, Shift); 893 return getNode(ISD::AND, AType, Shift, N3); 894 } 895 } 896 897 // Check to see if this is the equivalent of setcc X, 0 898 if (N4C && N4C->isNullValue() && N3C && (N3C->getValue() == 1ULL)) { 899 MVT::ValueType XType = N1.getValueType(); 900 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) 901 return getSetCC(TLI.getSetCCResultTy(), N1, N2, CC); 902 903 // seteq X, 0 -> srl (ctlz X, log2(size(X))) 904 if (N2C && N2C->isNullValue() && CC == ISD::SETEQ && 905 TLI.isOperationLegal(ISD::CTLZ, XType)) { 906 SDOperand Ctlz = getNode(ISD::CTLZ, XType, N1); 907 return getNode(ISD::SRL, XType, Ctlz, 908 getConstant(Log2_32(MVT::getSizeInBits(XType)), 909 TLI.getShiftAmountTy())); 910 } 911 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1) 912 if (N2C && N2C->isNullValue() && CC == ISD::SETGT) { 913 SDOperand NegN1 = getNode(ISD::SUB, XType, getConstant(0, XType), N1); 914 SDOperand NotN1 = getNode(ISD::XOR, XType, N1, getConstant(~0ULL, XType)); 915 return getNode(ISD::SRL, XType, getNode(ISD::AND, XType, NegN1, NotN1), 916 getConstant(MVT::getSizeInBits(XType)-1, 917 TLI.getShiftAmountTy())); 918 } 919 // setgt X, -1 -> xor (srl (X, size(X)-1), 1) 920 if (N2C && N2C->isAllOnesValue() && CC == ISD::SETGT) { 921 SDOperand Sign = getNode(ISD::SRL, XType, N1, 922 getConstant(MVT::getSizeInBits(XType)-1, 923 TLI.getShiftAmountTy())); 924 return getNode(ISD::XOR, XType, Sign, getConstant(1, XType)); 925 } 926 } 927 928 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 929 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 930 if (N2C && N2C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 931 N1 == N4 && N3.getOpcode() == ISD::SUB && N1 == N3.getOperand(1)) { 932 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) { 933 MVT::ValueType XType = N1.getValueType(); 934 if (SubC->isNullValue() && MVT::isInteger(XType)) { 935 SDOperand Shift = getNode(ISD::SRA, XType, N1, 936 getConstant(MVT::getSizeInBits(XType)-1, 937 TLI.getShiftAmountTy())); 938 return getNode(ISD::XOR, XType, getNode(ISD::ADD, XType, N1, Shift), 939 Shift); 940 } 941 } 942 } 943 944 // Could not fold it. 945 return SDOperand(); 946} 947 948/// getNode - Gets or creates the specified node. 949/// 950SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT) { 951 SDNode *N = new SDNode(Opcode, VT); 952 AllNodes.push_back(N); 953 return SDOperand(N, 0); 954} 955 956SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, 957 SDOperand Operand) { 958 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Operand.Val)) { 959 uint64_t Val = C->getValue(); 960 switch (Opcode) { 961 default: break; 962 case ISD::SIGN_EXTEND: return getConstant(C->getSignExtended(), VT); 963 case ISD::ZERO_EXTEND: return getConstant(Val, VT); 964 case ISD::TRUNCATE: return getConstant(Val, VT); 965 case ISD::SINT_TO_FP: return getConstantFP(C->getSignExtended(), VT); 966 case ISD::UINT_TO_FP: return getConstantFP(C->getValue(), VT); 967 } 968 } 969 970 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Operand.Val)) 971 switch (Opcode) { 972 case ISD::FNEG: 973 return getConstantFP(-C->getValue(), VT); 974 case ISD::FP_ROUND: 975 case ISD::FP_EXTEND: 976 return getConstantFP(C->getValue(), VT); 977 case ISD::FP_TO_SINT: 978 return getConstant((int64_t)C->getValue(), VT); 979 case ISD::FP_TO_UINT: 980 return getConstant((uint64_t)C->getValue(), VT); 981 } 982 983 unsigned OpOpcode = Operand.Val->getOpcode(); 984 switch (Opcode) { 985 case ISD::TokenFactor: 986 return Operand; // Factor of one node? No factor. 987 case ISD::SIGN_EXTEND: 988 if (Operand.getValueType() == VT) return Operand; // noop extension 989 if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND) 990 return getNode(OpOpcode, VT, Operand.Val->getOperand(0)); 991 break; 992 case ISD::ZERO_EXTEND: 993 if (Operand.getValueType() == VT) return Operand; // noop extension 994 if (OpOpcode == ISD::ZERO_EXTEND) // (zext (zext x)) -> (zext x) 995 return getNode(ISD::ZERO_EXTEND, VT, Operand.Val->getOperand(0)); 996 break; 997 case ISD::TRUNCATE: 998 if (Operand.getValueType() == VT) return Operand; // noop truncate 999 if (OpOpcode == ISD::TRUNCATE) 1000 return getNode(ISD::TRUNCATE, VT, Operand.Val->getOperand(0)); 1001 else if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND) { 1002 // If the source is smaller than the dest, we still need an extend. 1003 if (Operand.Val->getOperand(0).getValueType() < VT) 1004 return getNode(OpOpcode, VT, Operand.Val->getOperand(0)); 1005 else if (Operand.Val->getOperand(0).getValueType() > VT) 1006 return getNode(ISD::TRUNCATE, VT, Operand.Val->getOperand(0)); 1007 else 1008 return Operand.Val->getOperand(0); 1009 } 1010 break; 1011 case ISD::FNEG: 1012 if (OpOpcode == ISD::SUB) // -(X-Y) -> (Y-X) 1013 return getNode(ISD::SUB, VT, Operand.Val->getOperand(1), 1014 Operand.Val->getOperand(0)); 1015 if (OpOpcode == ISD::FNEG) // --X -> X 1016 return Operand.Val->getOperand(0); 1017 break; 1018 case ISD::FABS: 1019 if (OpOpcode == ISD::FNEG) // abs(-X) -> abs(X) 1020 return getNode(ISD::FABS, VT, Operand.Val->getOperand(0)); 1021 break; 1022 } 1023 1024 SDNode *N; 1025 if (VT != MVT::Flag) { // Don't CSE flag producing nodes 1026 SDNode *&E = UnaryOps[std::make_pair(Opcode, std::make_pair(Operand, VT))]; 1027 if (E) return SDOperand(N, 0); 1028 E = N = new SDNode(Opcode, Operand); 1029 } else { 1030 N = new SDNode(Opcode, Operand); 1031 } 1032 N->setValueTypes(VT); 1033 AllNodes.push_back(N); 1034 return SDOperand(N, 0); 1035} 1036 1037/// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero. We use 1038/// this predicate to simplify operations downstream. V and Mask are known to 1039/// be the same type. 1040static bool MaskedValueIsZero(const SDOperand &Op, uint64_t Mask, 1041 const TargetLowering &TLI) { 1042 unsigned SrcBits; 1043 if (Mask == 0) return true; 1044 1045 // If we know the result of a setcc has the top bits zero, use this info. 1046 switch (Op.getOpcode()) { 1047 case ISD::Constant: 1048 return (cast<ConstantSDNode>(Op)->getValue() & Mask) == 0; 1049 1050 case ISD::SETCC: 1051 return ((Mask & 1) == 0) && 1052 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult; 1053 1054 case ISD::ZEXTLOAD: 1055 SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(3))->getVT()); 1056 return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits. 1057 case ISD::ZERO_EXTEND: 1058 SrcBits = MVT::getSizeInBits(Op.getOperand(0).getValueType()); 1059 return MaskedValueIsZero(Op.getOperand(0),Mask & ((1ULL << SrcBits)-1),TLI); 1060 1061 case ISD::AND: 1062 // (X & C1) & C2 == 0 iff C1 & C2 == 0. 1063 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(Op.getOperand(1))) 1064 return MaskedValueIsZero(Op.getOperand(0),AndRHS->getValue() & Mask, TLI); 1065 1066 // FALL THROUGH 1067 case ISD::OR: 1068 case ISD::XOR: 1069 return MaskedValueIsZero(Op.getOperand(0), Mask, TLI) && 1070 MaskedValueIsZero(Op.getOperand(1), Mask, TLI); 1071 case ISD::SELECT: 1072 return MaskedValueIsZero(Op.getOperand(1), Mask, TLI) && 1073 MaskedValueIsZero(Op.getOperand(2), Mask, TLI); 1074 case ISD::SELECT_CC: 1075 return MaskedValueIsZero(Op.getOperand(2), Mask, TLI) && 1076 MaskedValueIsZero(Op.getOperand(3), Mask, TLI); 1077 case ISD::SRL: 1078 // (ushr X, C1) & C2 == 0 iff X & (C2 << C1) == 0 1079 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1080 uint64_t NewVal = Mask << ShAmt->getValue(); 1081 SrcBits = MVT::getSizeInBits(Op.getValueType()); 1082 if (SrcBits != 64) NewVal &= (1ULL << SrcBits)-1; 1083 return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI); 1084 } 1085 return false; 1086 case ISD::SHL: 1087 // (ushl X, C1) & C2 == 0 iff X & (C2 >> C1) == 0 1088 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1089 uint64_t NewVal = Mask >> ShAmt->getValue(); 1090 return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI); 1091 } 1092 return false; 1093 case ISD::CTTZ: 1094 case ISD::CTLZ: 1095 case ISD::CTPOP: 1096 // Bit counting instructions can not set the high bits of the result 1097 // register. The max number of bits sets depends on the input. 1098 return (Mask & (MVT::getSizeInBits(Op.getValueType())*2-1)) == 0; 1099 1100 // TODO we could handle some SRA cases here. 1101 default: break; 1102 } 1103 1104 return false; 1105} 1106 1107 1108 1109SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, 1110 SDOperand N1, SDOperand N2) { 1111#ifndef NDEBUG 1112 switch (Opcode) { 1113 case ISD::TokenFactor: 1114 assert(VT == MVT::Other && N1.getValueType() == MVT::Other && 1115 N2.getValueType() == MVT::Other && "Invalid token factor!"); 1116 break; 1117 case ISD::AND: 1118 case ISD::OR: 1119 case ISD::XOR: 1120 case ISD::UDIV: 1121 case ISD::UREM: 1122 case ISD::MULHU: 1123 case ISD::MULHS: 1124 assert(MVT::isInteger(VT) && "This operator does not apply to FP types!"); 1125 // fall through 1126 case ISD::ADD: 1127 case ISD::SUB: 1128 case ISD::MUL: 1129 case ISD::SDIV: 1130 case ISD::SREM: 1131 assert(N1.getValueType() == N2.getValueType() && 1132 N1.getValueType() == VT && "Binary operator types must match!"); 1133 break; 1134 1135 case ISD::SHL: 1136 case ISD::SRA: 1137 case ISD::SRL: 1138 assert(VT == N1.getValueType() && 1139 "Shift operators return type must be the same as their first arg"); 1140 assert(MVT::isInteger(VT) && MVT::isInteger(N2.getValueType()) && 1141 VT != MVT::i1 && "Shifts only work on integers"); 1142 break; 1143 case ISD::FP_ROUND_INREG: { 1144 MVT::ValueType EVT = cast<VTSDNode>(N2)->getVT(); 1145 assert(VT == N1.getValueType() && "Not an inreg round!"); 1146 assert(MVT::isFloatingPoint(VT) && MVT::isFloatingPoint(EVT) && 1147 "Cannot FP_ROUND_INREG integer types"); 1148 assert(EVT <= VT && "Not rounding down!"); 1149 break; 1150 } 1151 case ISD::SIGN_EXTEND_INREG: { 1152 MVT::ValueType EVT = cast<VTSDNode>(N2)->getVT(); 1153 assert(VT == N1.getValueType() && "Not an inreg extend!"); 1154 assert(MVT::isInteger(VT) && MVT::isInteger(EVT) && 1155 "Cannot *_EXTEND_INREG FP types"); 1156 assert(EVT <= VT && "Not extending!"); 1157 } 1158 1159 default: break; 1160 } 1161#endif 1162 1163 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1164 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 1165 if (N1C) { 1166 if (N2C) { 1167 uint64_t C1 = N1C->getValue(), C2 = N2C->getValue(); 1168 switch (Opcode) { 1169 case ISD::ADD: return getConstant(C1 + C2, VT); 1170 case ISD::SUB: return getConstant(C1 - C2, VT); 1171 case ISD::MUL: return getConstant(C1 * C2, VT); 1172 case ISD::UDIV: 1173 if (C2) return getConstant(C1 / C2, VT); 1174 break; 1175 case ISD::UREM : 1176 if (C2) return getConstant(C1 % C2, VT); 1177 break; 1178 case ISD::SDIV : 1179 if (C2) return getConstant(N1C->getSignExtended() / 1180 N2C->getSignExtended(), VT); 1181 break; 1182 case ISD::SREM : 1183 if (C2) return getConstant(N1C->getSignExtended() % 1184 N2C->getSignExtended(), VT); 1185 break; 1186 case ISD::AND : return getConstant(C1 & C2, VT); 1187 case ISD::OR : return getConstant(C1 | C2, VT); 1188 case ISD::XOR : return getConstant(C1 ^ C2, VT); 1189 case ISD::SHL : return getConstant(C1 << (int)C2, VT); 1190 case ISD::SRL : return getConstant(C1 >> (unsigned)C2, VT); 1191 case ISD::SRA : return getConstant(N1C->getSignExtended() >>(int)C2, VT); 1192 default: break; 1193 } 1194 1195 } else { // Cannonicalize constant to RHS if commutative 1196 if (isCommutativeBinOp(Opcode)) { 1197 std::swap(N1C, N2C); 1198 std::swap(N1, N2); 1199 } 1200 } 1201 1202 switch (Opcode) { 1203 default: break; 1204 case ISD::SHL: // shl 0, X -> 0 1205 if (N1C->isNullValue()) return N1; 1206 break; 1207 case ISD::SRL: // srl 0, X -> 0 1208 if (N1C->isNullValue()) return N1; 1209 break; 1210 case ISD::SRA: // sra -1, X -> -1 1211 if (N1C->isAllOnesValue()) return N1; 1212 break; 1213 case ISD::SIGN_EXTEND_INREG: // SIGN_EXTEND_INREG N1C, EVT 1214 // Extending a constant? Just return the extended constant. 1215 SDOperand Tmp = getNode(ISD::TRUNCATE, cast<VTSDNode>(N2)->getVT(), N1); 1216 return getNode(ISD::SIGN_EXTEND, VT, Tmp); 1217 } 1218 } 1219 1220 if (N2C) { 1221 uint64_t C2 = N2C->getValue(); 1222 1223 switch (Opcode) { 1224 case ISD::ADD: 1225 if (!C2) return N1; // add X, 0 -> X 1226 break; 1227 case ISD::SUB: 1228 if (!C2) return N1; // sub X, 0 -> X 1229 return getNode(ISD::ADD, VT, N1, getConstant(-C2, VT)); 1230 case ISD::MUL: 1231 if (!C2) return N2; // mul X, 0 -> 0 1232 if (N2C->isAllOnesValue()) // mul X, -1 -> 0-X 1233 return getNode(ISD::SUB, VT, getConstant(0, VT), N1); 1234 1235 // FIXME: Move this to the DAG combiner when it exists. 1236 if ((C2 & C2-1) == 0) { 1237 SDOperand ShAmt = getConstant(Log2_64(C2), TLI.getShiftAmountTy()); 1238 return getNode(ISD::SHL, VT, N1, ShAmt); 1239 } 1240 break; 1241 1242 case ISD::MULHU: 1243 case ISD::MULHS: 1244 if (!C2) return N2; // mul X, 0 -> 0 1245 1246 if (C2 == 1) // 0X*01 -> 0X hi(0X) == 0 1247 return getConstant(0, VT); 1248 1249 // Many others could be handled here, including -1, powers of 2, etc. 1250 break; 1251 1252 case ISD::UDIV: 1253 // FIXME: Move this to the DAG combiner when it exists. 1254 if ((C2 & C2-1) == 0 && C2) { 1255 SDOperand ShAmt = getConstant(Log2_64(C2), TLI.getShiftAmountTy()); 1256 return getNode(ISD::SRL, VT, N1, ShAmt); 1257 } 1258 break; 1259 1260 case ISD::SHL: 1261 case ISD::SRL: 1262 case ISD::SRA: 1263 // If the shift amount is bigger than the size of the data, then all the 1264 // bits are shifted out. Simplify to undef. 1265 if (C2 >= MVT::getSizeInBits(N1.getValueType())) { 1266 return getNode(ISD::UNDEF, N1.getValueType()); 1267 } 1268 if (C2 == 0) return N1; 1269 1270 if (Opcode == ISD::SRA) { 1271 // If the sign bit is known to be zero, switch this to a SRL. 1272 if (MaskedValueIsZero(N1, 1273 1ULL << (MVT::getSizeInBits(N1.getValueType())-1), 1274 TLI)) 1275 return getNode(ISD::SRL, N1.getValueType(), N1, N2); 1276 } else { 1277 // If the part left over is known to be zero, the whole thing is zero. 1278 uint64_t TypeMask = ~0ULL >> (64-MVT::getSizeInBits(N1.getValueType())); 1279 if (Opcode == ISD::SRL) { 1280 if (MaskedValueIsZero(N1, TypeMask << C2, TLI)) 1281 return getConstant(0, N1.getValueType()); 1282 } else if (Opcode == ISD::SHL) { 1283 if (MaskedValueIsZero(N1, TypeMask >> C2, TLI)) 1284 return getConstant(0, N1.getValueType()); 1285 } 1286 } 1287 1288 if (Opcode == ISD::SHL && N1.getNumOperands() == 2) 1289 if (ConstantSDNode *OpSA = dyn_cast<ConstantSDNode>(N1.getOperand(1))) { 1290 unsigned OpSAC = OpSA->getValue(); 1291 if (N1.getOpcode() == ISD::SHL) { 1292 if (C2+OpSAC >= MVT::getSizeInBits(N1.getValueType())) 1293 return getConstant(0, N1.getValueType()); 1294 return getNode(ISD::SHL, N1.getValueType(), N1.getOperand(0), 1295 getConstant(C2+OpSAC, N2.getValueType())); 1296 } else if (N1.getOpcode() == ISD::SRL) { 1297 // (X >> C1) << C2: if C2 > C1, ((X & ~0<<C1) << C2-C1) 1298 SDOperand Mask = getNode(ISD::AND, VT, N1.getOperand(0), 1299 getConstant(~0ULL << OpSAC, VT)); 1300 if (C2 > OpSAC) { 1301 return getNode(ISD::SHL, VT, Mask, 1302 getConstant(C2-OpSAC, N2.getValueType())); 1303 } else { 1304 // (X >> C1) << C2: if C2 <= C1, ((X & ~0<<C1) >> C1-C2) 1305 return getNode(ISD::SRL, VT, Mask, 1306 getConstant(OpSAC-C2, N2.getValueType())); 1307 } 1308 } else if (N1.getOpcode() == ISD::SRA) { 1309 // if C1 == C2, just mask out low bits. 1310 if (C2 == OpSAC) 1311 return getNode(ISD::AND, VT, N1.getOperand(0), 1312 getConstant(~0ULL << C2, VT)); 1313 } 1314 } 1315 break; 1316 1317 case ISD::AND: 1318 if (!C2) return N2; // X and 0 -> 0 1319 if (N2C->isAllOnesValue()) 1320 return N1; // X and -1 -> X 1321 1322 if (MaskedValueIsZero(N1, C2, TLI)) // X and 0 -> 0 1323 return getConstant(0, VT); 1324 1325 { 1326 uint64_t NotC2 = ~C2; 1327 if (VT != MVT::i64) 1328 NotC2 &= (1ULL << MVT::getSizeInBits(VT))-1; 1329 1330 if (MaskedValueIsZero(N1, NotC2, TLI)) 1331 return N1; // if (X & ~C2) -> 0, the and is redundant 1332 } 1333 1334 // FIXME: Should add a corresponding version of this for 1335 // ZERO_EXTEND/SIGN_EXTEND by converting them to an ANY_EXTEND node which 1336 // we don't have yet. 1337 1338 // and (sign_extend_inreg x:16:32), 1 -> and x, 1 1339 if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) { 1340 // If we are masking out the part of our input that was extended, just 1341 // mask the input to the extension directly. 1342 unsigned ExtendBits = 1343 MVT::getSizeInBits(cast<VTSDNode>(N1.getOperand(1))->getVT()); 1344 if ((C2 & (~0ULL << ExtendBits)) == 0) 1345 return getNode(ISD::AND, VT, N1.getOperand(0), N2); 1346 } else if (N1.getOpcode() == ISD::OR) { 1347 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N1.getOperand(1))) 1348 if ((ORI->getValue() & C2) == C2) { 1349 // If the 'or' is setting all of the bits that we are masking for, 1350 // we know the result of the AND will be the AND mask itself. 1351 return N2; 1352 } 1353 } 1354 break; 1355 case ISD::OR: 1356 if (!C2)return N1; // X or 0 -> X 1357 if (N2C->isAllOnesValue()) 1358 return N2; // X or -1 -> -1 1359 break; 1360 case ISD::XOR: 1361 if (!C2) return N1; // X xor 0 -> X 1362 if (N2C->isAllOnesValue()) { 1363 if (N1.Val->getOpcode() == ISD::SETCC){ 1364 SDNode *SetCC = N1.Val; 1365 // !(X op Y) -> (X !op Y) 1366 bool isInteger = MVT::isInteger(SetCC->getOperand(0).getValueType()); 1367 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC->getOperand(2))->get(); 1368 return getSetCC(SetCC->getValueType(0), 1369 SetCC->getOperand(0), SetCC->getOperand(1), 1370 ISD::getSetCCInverse(CC, isInteger)); 1371 } else if (N1.getOpcode() == ISD::AND || N1.getOpcode() == ISD::OR) { 1372 SDNode *Op = N1.Val; 1373 // !(X or Y) -> (!X and !Y) iff X or Y are freely invertible 1374 // !(X and Y) -> (!X or !Y) iff X or Y are freely invertible 1375 SDOperand LHS = Op->getOperand(0), RHS = Op->getOperand(1); 1376 if (isInvertibleForFree(RHS) || isInvertibleForFree(LHS)) { 1377 LHS = getNode(ISD::XOR, VT, LHS, N2); // RHS = ~LHS 1378 RHS = getNode(ISD::XOR, VT, RHS, N2); // RHS = ~RHS 1379 if (Op->getOpcode() == ISD::AND) 1380 return getNode(ISD::OR, VT, LHS, RHS); 1381 return getNode(ISD::AND, VT, LHS, RHS); 1382 } 1383 } 1384 // X xor -1 -> not(x) ? 1385 } 1386 break; 1387 } 1388 1389 // Reassociate ((X op C1) op C2) if possible. 1390 if (N1.getOpcode() == Opcode && isAssociativeBinOp(Opcode)) 1391 if (ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N1.Val->getOperand(1))) 1392 return getNode(Opcode, VT, N1.Val->getOperand(0), 1393 getNode(Opcode, VT, N2, N1.Val->getOperand(1))); 1394 } 1395 1396 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1.Val); 1397 ConstantFPSDNode *N2CFP = dyn_cast<ConstantFPSDNode>(N2.Val); 1398 if (N1CFP) { 1399 if (N2CFP) { 1400 double C1 = N1CFP->getValue(), C2 = N2CFP->getValue(); 1401 switch (Opcode) { 1402 case ISD::ADD: return getConstantFP(C1 + C2, VT); 1403 case ISD::SUB: return getConstantFP(C1 - C2, VT); 1404 case ISD::MUL: return getConstantFP(C1 * C2, VT); 1405 case ISD::SDIV: 1406 if (C2) return getConstantFP(C1 / C2, VT); 1407 break; 1408 case ISD::SREM : 1409 if (C2) return getConstantFP(fmod(C1, C2), VT); 1410 break; 1411 default: break; 1412 } 1413 1414 } else { // Cannonicalize constant to RHS if commutative 1415 if (isCommutativeBinOp(Opcode)) { 1416 std::swap(N1CFP, N2CFP); 1417 std::swap(N1, N2); 1418 } 1419 } 1420 1421 if (Opcode == ISD::FP_ROUND_INREG) 1422 return getNode(ISD::FP_EXTEND, VT, 1423 getNode(ISD::FP_ROUND, cast<VTSDNode>(N2)->getVT(), N1)); 1424 } 1425 1426 // Finally, fold operations that do not require constants. 1427 switch (Opcode) { 1428 case ISD::TokenFactor: 1429 if (N1.getOpcode() == ISD::EntryToken) 1430 return N2; 1431 if (N2.getOpcode() == ISD::EntryToken) 1432 return N1; 1433 break; 1434 1435 case ISD::AND: 1436 case ISD::OR: 1437 if (N1.Val->getOpcode() == ISD::SETCC && N2.Val->getOpcode() == ISD::SETCC){ 1438 SDNode *LHS = N1.Val, *RHS = N2.Val; 1439 SDOperand LL = LHS->getOperand(0), RL = RHS->getOperand(0); 1440 SDOperand LR = LHS->getOperand(1), RR = RHS->getOperand(1); 1441 ISD::CondCode Op1 = cast<CondCodeSDNode>(LHS->getOperand(2))->get(); 1442 ISD::CondCode Op2 = cast<CondCodeSDNode>(RHS->getOperand(2))->get(); 1443 1444 if (LR == RR && isa<ConstantSDNode>(LR) && 1445 Op2 == Op1 && MVT::isInteger(LL.getValueType())) { 1446 // (X != 0) | (Y != 0) -> (X|Y != 0) 1447 // (X == 0) & (Y == 0) -> (X|Y == 0) 1448 // (X < 0) | (Y < 0) -> (X|Y < 0) 1449 if (cast<ConstantSDNode>(LR)->getValue() == 0 && 1450 ((Op2 == ISD::SETEQ && Opcode == ISD::AND) || 1451 (Op2 == ISD::SETNE && Opcode == ISD::OR) || 1452 (Op2 == ISD::SETLT && Opcode == ISD::OR))) 1453 return getSetCC(VT, getNode(ISD::OR, LR.getValueType(), LL, RL), LR, 1454 Op2); 1455 1456 if (cast<ConstantSDNode>(LR)->isAllOnesValue()) { 1457 // (X == -1) & (Y == -1) -> (X&Y == -1) 1458 // (X != -1) | (Y != -1) -> (X&Y != -1) 1459 // (X > -1) | (Y > -1) -> (X&Y > -1) 1460 if ((Opcode == ISD::AND && Op2 == ISD::SETEQ) || 1461 (Opcode == ISD::OR && Op2 == ISD::SETNE) || 1462 (Opcode == ISD::OR && Op2 == ISD::SETGT)) 1463 return getSetCC(VT, getNode(ISD::AND, LR.getValueType(), LL, RL), 1464 LR, Op2); 1465 // (X > -1) & (Y > -1) -> (X|Y > -1) 1466 if (Opcode == ISD::AND && Op2 == ISD::SETGT) 1467 return getSetCC(VT, getNode(ISD::OR, LR.getValueType(), LL, RL), 1468 LR, Op2); 1469 } 1470 } 1471 1472 // (X op1 Y) | (Y op2 X) -> (X op1 Y) | (X swapop2 Y) 1473 if (LL == RR && LR == RL) { 1474 Op2 = ISD::getSetCCSwappedOperands(Op2); 1475 goto MatchedBackwards; 1476 } 1477 1478 if (LL == RL && LR == RR) { 1479 MatchedBackwards: 1480 ISD::CondCode Result; 1481 bool isInteger = MVT::isInteger(LL.getValueType()); 1482 if (Opcode == ISD::OR) 1483 Result = ISD::getSetCCOrOperation(Op1, Op2, isInteger); 1484 else 1485 Result = ISD::getSetCCAndOperation(Op1, Op2, isInteger); 1486 1487 if (Result != ISD::SETCC_INVALID) 1488 return getSetCC(LHS->getValueType(0), LL, LR, Result); 1489 } 1490 } 1491 1492 // and/or zext(a), zext(b) -> zext(and/or a, b) 1493 if (N1.getOpcode() == ISD::ZERO_EXTEND && 1494 N2.getOpcode() == ISD::ZERO_EXTEND && 1495 N1.getOperand(0).getValueType() == N2.getOperand(0).getValueType()) 1496 return getNode(ISD::ZERO_EXTEND, VT, 1497 getNode(Opcode, N1.getOperand(0).getValueType(), 1498 N1.getOperand(0), N2.getOperand(0))); 1499 break; 1500 case ISD::XOR: 1501 if (N1 == N2) return getConstant(0, VT); // xor X, Y -> 0 1502 break; 1503 case ISD::ADD: 1504 if (N2.getOpcode() == ISD::FNEG) // (A+ (-B) -> A-B 1505 return getNode(ISD::SUB, VT, N1, N2.getOperand(0)); 1506 if (N1.getOpcode() == ISD::FNEG) // ((-A)+B) -> B-A 1507 return getNode(ISD::SUB, VT, N2, N1.getOperand(0)); 1508 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 1509 cast<ConstantSDNode>(N1.getOperand(0))->getValue() == 0) 1510 return getNode(ISD::SUB, VT, N2, N1.getOperand(1)); // (0-A)+B -> B-A 1511 if (N2.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N2.getOperand(0)) && 1512 cast<ConstantSDNode>(N2.getOperand(0))->getValue() == 0) 1513 return getNode(ISD::SUB, VT, N1, N2.getOperand(1)); // A+(0-B) -> A-B 1514 if (N2.getOpcode() == ISD::SUB && N1 == N2.Val->getOperand(1) && 1515 !MVT::isFloatingPoint(N2.getValueType())) 1516 return N2.Val->getOperand(0); // A+(B-A) -> B 1517 break; 1518 case ISD::SUB: 1519 if (N1.getOpcode() == ISD::ADD) { 1520 if (N1.Val->getOperand(0) == N2 && 1521 !MVT::isFloatingPoint(N2.getValueType())) 1522 return N1.Val->getOperand(1); // (A+B)-A == B 1523 if (N1.Val->getOperand(1) == N2 && 1524 !MVT::isFloatingPoint(N2.getValueType())) 1525 return N1.Val->getOperand(0); // (A+B)-B == A 1526 } 1527 if (N2.getOpcode() == ISD::FNEG) // (A- (-B) -> A+B 1528 return getNode(ISD::ADD, VT, N1, N2.getOperand(0)); 1529 break; 1530 case ISD::FP_ROUND_INREG: 1531 if (cast<VTSDNode>(N2)->getVT() == VT) return N1; // Not actually rounding. 1532 break; 1533 case ISD::SIGN_EXTEND_INREG: { 1534 MVT::ValueType EVT = cast<VTSDNode>(N2)->getVT(); 1535 if (EVT == VT) return N1; // Not actually extending 1536 1537 // If we are sign extending an extension, use the original source. 1538 if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) 1539 if (cast<VTSDNode>(N1.getOperand(1))->getVT() <= EVT) 1540 return N1; 1541 1542 // If we are sign extending a sextload, return just the load. 1543 if (N1.getOpcode() == ISD::SEXTLOAD) 1544 if (cast<VTSDNode>(N1.getOperand(3))->getVT() <= EVT) 1545 return N1; 1546 1547 // If we are extending the result of a setcc, and we already know the 1548 // contents of the top bits, eliminate the extension. 1549 if (N1.getOpcode() == ISD::SETCC && 1550 TLI.getSetCCResultContents() == 1551 TargetLowering::ZeroOrNegativeOneSetCCResult) 1552 return N1; 1553 1554 // If we are sign extending the result of an (and X, C) operation, and we 1555 // know the extended bits are zeros already, don't do the extend. 1556 if (N1.getOpcode() == ISD::AND) 1557 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getOperand(1))) { 1558 uint64_t Mask = N1C->getValue(); 1559 unsigned NumBits = MVT::getSizeInBits(EVT); 1560 if ((Mask & (~0ULL << (NumBits-1))) == 0) 1561 return N1; 1562 } 1563 break; 1564 } 1565 1566 // FIXME: figure out how to safely handle things like 1567 // int foo(int x) { return 1 << (x & 255); } 1568 // int bar() { return foo(256); } 1569#if 0 1570 case ISD::SHL: 1571 case ISD::SRL: 1572 case ISD::SRA: 1573 if (N2.getOpcode() == ISD::SIGN_EXTEND_INREG && 1574 cast<VTSDNode>(N2.getOperand(1))->getVT() != MVT::i1) 1575 return getNode(Opcode, VT, N1, N2.getOperand(0)); 1576 else if (N2.getOpcode() == ISD::AND) 1577 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(N2.getOperand(1))) { 1578 // If the and is only masking out bits that cannot effect the shift, 1579 // eliminate the and. 1580 unsigned NumBits = MVT::getSizeInBits(VT); 1581 if ((AndRHS->getValue() & (NumBits-1)) == NumBits-1) 1582 return getNode(Opcode, VT, N1, N2.getOperand(0)); 1583 } 1584 break; 1585#endif 1586 } 1587 1588 // Memoize this node if possible. 1589 SDNode *N; 1590 if (Opcode != ISD::CALLSEQ_START && Opcode != ISD::CALLSEQ_END && 1591 VT != MVT::Flag) { 1592 SDNode *&BON = BinaryOps[std::make_pair(Opcode, std::make_pair(N1, N2))]; 1593 if (BON) return SDOperand(BON, 0); 1594 1595 BON = N = new SDNode(Opcode, N1, N2); 1596 } else { 1597 N = new SDNode(Opcode, N1, N2); 1598 } 1599 1600 N->setValueTypes(VT); 1601 AllNodes.push_back(N); 1602 return SDOperand(N, 0); 1603} 1604 1605// setAdjCallChain - This method changes the token chain of an 1606// CALLSEQ_START/END node to be the specified operand. 1607void SDNode::setAdjCallChain(SDOperand N) { 1608 assert(N.getValueType() == MVT::Other); 1609 assert((getOpcode() == ISD::CALLSEQ_START || 1610 getOpcode() == ISD::CALLSEQ_END) && "Cannot adjust this node!"); 1611 1612 Operands[0].Val->removeUser(this); 1613 Operands[0] = N; 1614 N.Val->Uses.push_back(this); 1615} 1616 1617 1618 1619SDOperand SelectionDAG::getLoad(MVT::ValueType VT, 1620 SDOperand Chain, SDOperand Ptr, 1621 SDOperand SV) { 1622 SDNode *&N = Loads[std::make_pair(Ptr, std::make_pair(Chain, VT))]; 1623 if (N) return SDOperand(N, 0); 1624 N = new SDNode(ISD::LOAD, Chain, Ptr, SV); 1625 1626 // Loads have a token chain. 1627 N->setValueTypes(VT, MVT::Other); 1628 AllNodes.push_back(N); 1629 return SDOperand(N, 0); 1630} 1631 1632 1633SDOperand SelectionDAG::getExtLoad(unsigned Opcode, MVT::ValueType VT, 1634 SDOperand Chain, SDOperand Ptr, SDOperand SV, 1635 MVT::ValueType EVT) { 1636 std::vector<SDOperand> Ops; 1637 Ops.reserve(4); 1638 Ops.push_back(Chain); 1639 Ops.push_back(Ptr); 1640 Ops.push_back(SV); 1641 Ops.push_back(getValueType(EVT)); 1642 std::vector<MVT::ValueType> VTs; 1643 VTs.reserve(2); 1644 VTs.push_back(VT); VTs.push_back(MVT::Other); // Add token chain. 1645 return getNode(Opcode, VTs, Ops); 1646} 1647 1648SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, 1649 SDOperand N1, SDOperand N2, SDOperand N3) { 1650 // Perform various simplifications. 1651 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1652 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 1653 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val); 1654 switch (Opcode) { 1655 case ISD::SETCC: { 1656 // Use SimplifySetCC to simplify SETCC's. 1657 SDOperand Simp = SimplifySetCC(VT, N1, N2, cast<CondCodeSDNode>(N3)->get()); 1658 if (Simp.Val) return Simp; 1659 break; 1660 } 1661 case ISD::SELECT: 1662 if (N1C) 1663 if (N1C->getValue()) 1664 return N2; // select true, X, Y -> X 1665 else 1666 return N3; // select false, X, Y -> Y 1667 1668 if (N2 == N3) return N2; // select C, X, X -> X 1669 1670 if (VT == MVT::i1) { // Boolean SELECT 1671 if (N2C) { 1672 if (N2C->getValue()) // select C, 1, X -> C | X 1673 return getNode(ISD::OR, VT, N1, N3); 1674 else // select C, 0, X -> ~C & X 1675 return getNode(ISD::AND, VT, 1676 getNode(ISD::XOR, N1.getValueType(), N1, 1677 getConstant(1, N1.getValueType())), N3); 1678 } else if (N3C) { 1679 if (N3C->getValue()) // select C, X, 1 -> ~C | X 1680 return getNode(ISD::OR, VT, 1681 getNode(ISD::XOR, N1.getValueType(), N1, 1682 getConstant(1, N1.getValueType())), N2); 1683 else // select C, X, 0 -> C & X 1684 return getNode(ISD::AND, VT, N1, N2); 1685 } 1686 1687 if (N1 == N2) // X ? X : Y --> X ? 1 : Y --> X | Y 1688 return getNode(ISD::OR, VT, N1, N3); 1689 if (N1 == N3) // X ? Y : X --> X ? Y : 0 --> X & Y 1690 return getNode(ISD::AND, VT, N1, N2); 1691 } 1692 if (N1.getOpcode() == ISD::SETCC) { 1693 SDOperand Simp = SimplifySelectCC(N1.getOperand(0), N1.getOperand(1), N2, 1694 N3, cast<CondCodeSDNode>(N1.getOperand(2))->get()); 1695 if (Simp.Val) return Simp; 1696 } 1697 break; 1698 case ISD::BRCOND: 1699 if (N2C) 1700 if (N2C->getValue()) // Unconditional branch 1701 return getNode(ISD::BR, MVT::Other, N1, N3); 1702 else 1703 return N1; // Never-taken branch 1704 break; 1705 } 1706 1707 std::vector<SDOperand> Ops; 1708 Ops.reserve(3); 1709 Ops.push_back(N1); 1710 Ops.push_back(N2); 1711 Ops.push_back(N3); 1712 1713 // Memoize node if it doesn't produce a flag. 1714 SDNode *N; 1715 if (VT != MVT::Flag) { 1716 SDNode *&E = OneResultNodes[std::make_pair(Opcode,std::make_pair(VT, Ops))]; 1717 if (E) return SDOperand(E, 0); 1718 E = N = new SDNode(Opcode, N1, N2, N3); 1719 } else { 1720 N = new SDNode(Opcode, N1, N2, N3); 1721 } 1722 N->setValueTypes(VT); 1723 AllNodes.push_back(N); 1724 return SDOperand(N, 0); 1725} 1726 1727SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, 1728 SDOperand N1, SDOperand N2, SDOperand N3, 1729 SDOperand N4) { 1730 std::vector<SDOperand> Ops; 1731 Ops.reserve(4); 1732 Ops.push_back(N1); 1733 Ops.push_back(N2); 1734 Ops.push_back(N3); 1735 Ops.push_back(N4); 1736 return getNode(Opcode, VT, Ops); 1737} 1738 1739SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, 1740 SDOperand N1, SDOperand N2, SDOperand N3, 1741 SDOperand N4, SDOperand N5) { 1742 std::vector<SDOperand> Ops; 1743 Ops.reserve(5); 1744 Ops.push_back(N1); 1745 Ops.push_back(N2); 1746 Ops.push_back(N3); 1747 Ops.push_back(N4); 1748 Ops.push_back(N5); 1749 return getNode(Opcode, VT, Ops); 1750} 1751 1752 1753SDOperand SelectionDAG::getSrcValue(const Value *V, int Offset) { 1754 assert((!V || isa<PointerType>(V->getType())) && 1755 "SrcValue is not a pointer?"); 1756 SDNode *&N = ValueNodes[std::make_pair(V, Offset)]; 1757 if (N) return SDOperand(N, 0); 1758 1759 N = new SrcValueSDNode(V, Offset); 1760 AllNodes.push_back(N); 1761 return SDOperand(N, 0); 1762} 1763 1764SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, 1765 std::vector<SDOperand> &Ops) { 1766 switch (Ops.size()) { 1767 case 0: return getNode(Opcode, VT); 1768 case 1: return getNode(Opcode, VT, Ops[0]); 1769 case 2: return getNode(Opcode, VT, Ops[0], Ops[1]); 1770 case 3: return getNode(Opcode, VT, Ops[0], Ops[1], Ops[2]); 1771 default: break; 1772 } 1773 1774 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Ops[1].Val); 1775 switch (Opcode) { 1776 default: break; 1777 case ISD::BRCONDTWOWAY: 1778 if (N1C) 1779 if (N1C->getValue()) // Unconditional branch to true dest. 1780 return getNode(ISD::BR, MVT::Other, Ops[0], Ops[2]); 1781 else // Unconditional branch to false dest. 1782 return getNode(ISD::BR, MVT::Other, Ops[0], Ops[3]); 1783 break; 1784 case ISD::BRTWOWAY_CC: 1785 assert(Ops.size() == 6 && "BRTWOWAY_CC takes 6 operands!"); 1786 assert(Ops[2].getValueType() == Ops[3].getValueType() && 1787 "LHS and RHS of comparison must have same type!"); 1788 break; 1789 case ISD::TRUNCSTORE: { 1790 assert(Ops.size() == 5 && "TRUNCSTORE takes 5 operands!"); 1791 MVT::ValueType EVT = cast<VTSDNode>(Ops[4])->getVT(); 1792#if 0 // FIXME: If the target supports EVT natively, convert to a truncate/store 1793 // If this is a truncating store of a constant, convert to the desired type 1794 // and store it instead. 1795 if (isa<Constant>(Ops[0])) { 1796 SDOperand Op = getNode(ISD::TRUNCATE, EVT, N1); 1797 if (isa<Constant>(Op)) 1798 N1 = Op; 1799 } 1800 // Also for ConstantFP? 1801#endif 1802 if (Ops[0].getValueType() == EVT) // Normal store? 1803 return getNode(ISD::STORE, VT, Ops[0], Ops[1], Ops[2], Ops[3]); 1804 assert(Ops[1].getValueType() > EVT && "Not a truncation?"); 1805 assert(MVT::isInteger(Ops[1].getValueType()) == MVT::isInteger(EVT) && 1806 "Can't do FP-INT conversion!"); 1807 break; 1808 } 1809 case ISD::SELECT_CC: { 1810 assert(Ops.size() == 5 && "TRUNCSTORE takes 5 operands!"); 1811 assert(Ops[0].getValueType() == Ops[1].getValueType() && 1812 "LHS and RHS of condition must have same type!"); 1813 assert(Ops[2].getValueType() == Ops[3].getValueType() && 1814 "True and False arms of SelectCC must have same type!"); 1815 assert(Ops[2].getValueType() == VT && 1816 "select_cc node must be of same type as true and false value!"); 1817 SDOperand Simp = SimplifySelectCC(Ops[0], Ops[1], Ops[2], Ops[3], 1818 cast<CondCodeSDNode>(Ops[4])->get()); 1819 if (Simp.Val) return Simp; 1820 break; 1821 } 1822 case ISD::BR_CC: { 1823 assert(Ops.size() == 5 && "TRUNCSTORE takes 5 operands!"); 1824 assert(Ops[2].getValueType() == Ops[3].getValueType() && 1825 "LHS/RHS of comparison should match types!"); 1826 // Use SimplifySetCC to simplify SETCC's. 1827 SDOperand Simp = SimplifySetCC(MVT::i1, Ops[2], Ops[3], 1828 cast<CondCodeSDNode>(Ops[1])->get()); 1829 if (Simp.Val) { 1830 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Simp)) { 1831 if (C->getValue() & 1) // Unconditional branch 1832 return getNode(ISD::BR, MVT::Other, Ops[0], Ops[4]); 1833 else 1834 return Ops[0]; // Unconditional Fall through 1835 } else if (Simp.Val->getOpcode() == ISD::SETCC) { 1836 Ops[2] = Simp.getOperand(0); 1837 Ops[3] = Simp.getOperand(1); 1838 Ops[1] = Simp.getOperand(2); 1839 } 1840 } 1841 break; 1842 } 1843 } 1844 1845 // Memoize nodes. 1846 SDNode *N; 1847 if (VT != MVT::Flag) { 1848 SDNode *&E = 1849 OneResultNodes[std::make_pair(Opcode, std::make_pair(VT, Ops))]; 1850 if (E) return SDOperand(E, 0); 1851 E = N = new SDNode(Opcode, Ops); 1852 } else { 1853 N = new SDNode(Opcode, Ops); 1854 } 1855 N->setValueTypes(VT); 1856 AllNodes.push_back(N); 1857 return SDOperand(N, 0); 1858} 1859 1860SDOperand SelectionDAG::getNode(unsigned Opcode, 1861 std::vector<MVT::ValueType> &ResultTys, 1862 std::vector<SDOperand> &Ops) { 1863 if (ResultTys.size() == 1) 1864 return getNode(Opcode, ResultTys[0], Ops); 1865 1866 switch (Opcode) { 1867 case ISD::EXTLOAD: 1868 case ISD::SEXTLOAD: 1869 case ISD::ZEXTLOAD: { 1870 MVT::ValueType EVT = cast<VTSDNode>(Ops[3])->getVT(); 1871 assert(Ops.size() == 4 && ResultTys.size() == 2 && "Bad *EXTLOAD!"); 1872 // If they are asking for an extending load from/to the same thing, return a 1873 // normal load. 1874 if (ResultTys[0] == EVT) 1875 return getLoad(ResultTys[0], Ops[0], Ops[1], Ops[2]); 1876 assert(EVT < ResultTys[0] && 1877 "Should only be an extending load, not truncating!"); 1878 assert((Opcode == ISD::EXTLOAD || MVT::isInteger(ResultTys[0])) && 1879 "Cannot sign/zero extend a FP load!"); 1880 assert(MVT::isInteger(ResultTys[0]) == MVT::isInteger(EVT) && 1881 "Cannot convert from FP to Int or Int -> FP!"); 1882 break; 1883 } 1884 1885 // FIXME: figure out how to safely handle things like 1886 // int foo(int x) { return 1 << (x & 255); } 1887 // int bar() { return foo(256); } 1888#if 0 1889 case ISD::SRA_PARTS: 1890 case ISD::SRL_PARTS: 1891 case ISD::SHL_PARTS: 1892 if (N3.getOpcode() == ISD::SIGN_EXTEND_INREG && 1893 cast<VTSDNode>(N3.getOperand(1))->getVT() != MVT::i1) 1894 return getNode(Opcode, VT, N1, N2, N3.getOperand(0)); 1895 else if (N3.getOpcode() == ISD::AND) 1896 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(N3.getOperand(1))) { 1897 // If the and is only masking out bits that cannot effect the shift, 1898 // eliminate the and. 1899 unsigned NumBits = MVT::getSizeInBits(VT)*2; 1900 if ((AndRHS->getValue() & (NumBits-1)) == NumBits-1) 1901 return getNode(Opcode, VT, N1, N2, N3.getOperand(0)); 1902 } 1903 break; 1904#endif 1905 } 1906 1907 // Memoize the node unless it returns a flag. 1908 SDNode *N; 1909 if (ResultTys.back() != MVT::Flag) { 1910 SDNode *&E = 1911 ArbitraryNodes[std::make_pair(Opcode, std::make_pair(ResultTys, Ops))]; 1912 if (E) return SDOperand(E, 0); 1913 E = N = new SDNode(Opcode, Ops); 1914 } else { 1915 N = new SDNode(Opcode, Ops); 1916 } 1917 N->setValueTypes(ResultTys); 1918 AllNodes.push_back(N); 1919 return SDOperand(N, 0); 1920} 1921 1922 1923/// SelectNodeTo - These are used for target selectors to *mutate* the 1924/// specified node to have the specified return type, Target opcode, and 1925/// operands. Note that target opcodes are stored as 1926/// ISD::BUILTIN_OP_END+TargetOpcode in the node opcode field. 1927void SelectionDAG::SelectNodeTo(SDNode *N, MVT::ValueType VT, 1928 unsigned TargetOpc) { 1929 RemoveNodeFromCSEMaps(N); 1930 N->MorphNodeTo(ISD::BUILTIN_OP_END+TargetOpc); 1931 N->setValueTypes(VT); 1932} 1933void SelectionDAG::SelectNodeTo(SDNode *N, MVT::ValueType VT, 1934 unsigned TargetOpc, SDOperand Op1) { 1935 RemoveNodeFromCSEMaps(N); 1936 N->MorphNodeTo(ISD::BUILTIN_OP_END+TargetOpc); 1937 N->setValueTypes(VT); 1938 N->setOperands(Op1); 1939} 1940void SelectionDAG::SelectNodeTo(SDNode *N, MVT::ValueType VT, 1941 unsigned TargetOpc, SDOperand Op1, 1942 SDOperand Op2) { 1943 RemoveNodeFromCSEMaps(N); 1944 N->MorphNodeTo(ISD::BUILTIN_OP_END+TargetOpc); 1945 N->setValueTypes(VT); 1946 N->setOperands(Op1, Op2); 1947} 1948void SelectionDAG::SelectNodeTo(SDNode *N, 1949 MVT::ValueType VT1, MVT::ValueType VT2, 1950 unsigned TargetOpc, SDOperand Op1, 1951 SDOperand Op2) { 1952 RemoveNodeFromCSEMaps(N); 1953 N->MorphNodeTo(ISD::BUILTIN_OP_END+TargetOpc); 1954 N->setValueTypes(VT1, VT2); 1955 N->setOperands(Op1, Op2); 1956} 1957void SelectionDAG::SelectNodeTo(SDNode *N, MVT::ValueType VT, 1958 unsigned TargetOpc, SDOperand Op1, 1959 SDOperand Op2, SDOperand Op3) { 1960 RemoveNodeFromCSEMaps(N); 1961 N->MorphNodeTo(ISD::BUILTIN_OP_END+TargetOpc); 1962 N->setValueTypes(VT); 1963 N->setOperands(Op1, Op2, Op3); 1964} 1965void SelectionDAG::SelectNodeTo(SDNode *N, MVT::ValueType VT1, 1966 MVT::ValueType VT2, 1967 unsigned TargetOpc, SDOperand Op1, 1968 SDOperand Op2, SDOperand Op3) { 1969 RemoveNodeFromCSEMaps(N); 1970 N->MorphNodeTo(ISD::BUILTIN_OP_END+TargetOpc); 1971 N->setValueTypes(VT1, VT2); 1972 N->setOperands(Op1, Op2, Op3); 1973} 1974 1975void SelectionDAG::SelectNodeTo(SDNode *N, MVT::ValueType VT, 1976 unsigned TargetOpc, SDOperand Op1, 1977 SDOperand Op2, SDOperand Op3, SDOperand Op4) { 1978 RemoveNodeFromCSEMaps(N); 1979 N->MorphNodeTo(ISD::BUILTIN_OP_END+TargetOpc); 1980 N->setValueTypes(VT); 1981 N->setOperands(Op1, Op2, Op3, Op4); 1982} 1983void SelectionDAG::SelectNodeTo(SDNode *N, MVT::ValueType VT, 1984 unsigned TargetOpc, SDOperand Op1, 1985 SDOperand Op2, SDOperand Op3, SDOperand Op4, 1986 SDOperand Op5) { 1987 RemoveNodeFromCSEMaps(N); 1988 N->MorphNodeTo(ISD::BUILTIN_OP_END+TargetOpc); 1989 N->setValueTypes(VT); 1990 N->setOperands(Op1, Op2, Op3, Op4, Op5); 1991} 1992 1993/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. 1994/// This can cause recursive merging of nodes in the DAG. 1995/// 1996void SelectionDAG::ReplaceAllUsesWith(SDNode *From, SDNode *To) { 1997 assert(From != To && "Cannot replace uses of with self"); 1998 while (!From->use_empty()) { 1999 // Process users until they are all gone. 2000 SDNode *U = *From->use_begin(); 2001 2002 // This node is about to morph, remove its old self from the CSE maps. 2003 RemoveNodeFromCSEMaps(U); 2004 2005 for (unsigned i = 0, e = U->getNumOperands(); i != e; ++i) 2006 if (U->getOperand(i).Val == From) { 2007 assert(U->getOperand(i).getValueType() == 2008 To->getValueType(U->getOperand(i).ResNo)); 2009 From->removeUser(U); 2010 U->Operands[i].Val = To; 2011 To->addUser(U); 2012 } 2013 2014 // Now that we have modified U, add it back to the CSE maps. If it already 2015 // exists there, recursively merge the results together. 2016 if (SDNode *Existing = AddNonLeafNodeToCSEMaps(U)) 2017 ReplaceAllUsesWith(U, Existing); 2018 // U is now dead. 2019 } 2020} 2021 2022void SelectionDAG::ReplaceAllUsesWith(SDNode *From, 2023 const std::vector<SDOperand> &To) { 2024 assert(From->getNumValues() == To.size() && 2025 "Incorrect number of values to replace with!"); 2026 if (To.size() == 1 && To[0].ResNo == 0) { 2027 // Degenerate case handled above. 2028 ReplaceAllUsesWith(From, To[0].Val); 2029 return; 2030 } 2031 2032 while (!From->use_empty()) { 2033 // Process users until they are all gone. 2034 SDNode *U = *From->use_begin(); 2035 2036 // This node is about to morph, remove its old self from the CSE maps. 2037 RemoveNodeFromCSEMaps(U); 2038 2039 for (unsigned i = 0, e = U->getNumOperands(); i != e; ++i) 2040 if (U->getOperand(i).Val == From) { 2041 const SDOperand &ToOp = To[U->getOperand(i).ResNo]; 2042 assert(U->getOperand(i).getValueType() == ToOp.getValueType()); 2043 From->removeUser(U); 2044 U->Operands[i] = ToOp; 2045 ToOp.Val->addUser(U); 2046 } 2047 2048 // Now that we have modified U, add it back to the CSE maps. If it already 2049 // exists there, recursively merge the results together. 2050 if (SDNode *Existing = AddNonLeafNodeToCSEMaps(U)) 2051 ReplaceAllUsesWith(U, Existing); 2052 // U is now dead. 2053 } 2054} 2055 2056 2057//===----------------------------------------------------------------------===// 2058// SDNode Class 2059//===----------------------------------------------------------------------===// 2060 2061/// hasNUsesOfValue - Return true if there are exactly NUSES uses of the 2062/// indicated value. This method ignores uses of other values defined by this 2063/// operation. 2064bool SDNode::hasNUsesOfValue(unsigned NUses, unsigned Value) { 2065 assert(Value < getNumValues() && "Bad value!"); 2066 2067 // If there is only one value, this is easy. 2068 if (getNumValues() == 1) 2069 return use_size() == NUses; 2070 if (Uses.size() < NUses) return false; 2071 2072 SDOperand TheValue(this, Value); 2073 2074 std::set<SDNode*> UsersHandled; 2075 2076 for (std::vector<SDNode*>::iterator UI = Uses.begin(), E = Uses.end(); 2077 UI != E; ++UI) { 2078 SDNode *User = *UI; 2079 if (User->getNumOperands() == 1 || 2080 UsersHandled.insert(User).second) // First time we've seen this? 2081 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 2082 if (User->getOperand(i) == TheValue) { 2083 if (NUses == 0) 2084 return false; // too many uses 2085 --NUses; 2086 } 2087 } 2088 2089 // Found exactly the right number of uses? 2090 return NUses == 0; 2091} 2092 2093 2094const char *SDNode::getOperationName(const SelectionDAG *G) const { 2095 switch (getOpcode()) { 2096 default: 2097 if (getOpcode() < ISD::BUILTIN_OP_END) 2098 return "<<Unknown DAG Node>>"; 2099 else { 2100 if (G) 2101 if (const TargetInstrInfo *TII = G->getTarget().getInstrInfo()) 2102 return TII->getName(getOpcode()-ISD::BUILTIN_OP_END); 2103 return "<<Unknown Target Node>>"; 2104 } 2105 2106 case ISD::PCMARKER: return "PCMarker"; 2107 case ISD::SRCVALUE: return "SrcValue"; 2108 case ISD::VALUETYPE: return "ValueType"; 2109 case ISD::EntryToken: return "EntryToken"; 2110 case ISD::TokenFactor: return "TokenFactor"; 2111 case ISD::Constant: return "Constant"; 2112 case ISD::TargetConstant: return "TargetConstant"; 2113 case ISD::ConstantFP: return "ConstantFP"; 2114 case ISD::GlobalAddress: return "GlobalAddress"; 2115 case ISD::TargetGlobalAddress: return "TargetGlobalAddress"; 2116 case ISD::FrameIndex: return "FrameIndex"; 2117 case ISD::TargetFrameIndex: return "TargetFrameIndex"; 2118 case ISD::BasicBlock: return "BasicBlock"; 2119 case ISD::Register: return "Register"; 2120 case ISD::ExternalSymbol: return "ExternalSymbol"; 2121 case ISD::ConstantPool: return "ConstantPoolIndex"; 2122 case ISD::TargetConstantPool: return "TargetConstantPoolIndex"; 2123 case ISD::CopyToReg: return "CopyToReg"; 2124 case ISD::CopyFromReg: return "CopyFromReg"; 2125 case ISD::ImplicitDef: return "ImplicitDef"; 2126 case ISD::UNDEF: return "undef"; 2127 2128 // Unary operators 2129 case ISD::FABS: return "fabs"; 2130 case ISD::FNEG: return "fneg"; 2131 case ISD::FSQRT: return "fsqrt"; 2132 case ISD::FSIN: return "fsin"; 2133 case ISD::FCOS: return "fcos"; 2134 2135 // Binary operators 2136 case ISD::ADD: return "add"; 2137 case ISD::SUB: return "sub"; 2138 case ISD::MUL: return "mul"; 2139 case ISD::MULHU: return "mulhu"; 2140 case ISD::MULHS: return "mulhs"; 2141 case ISD::SDIV: return "sdiv"; 2142 case ISD::UDIV: return "udiv"; 2143 case ISD::SREM: return "srem"; 2144 case ISD::UREM: return "urem"; 2145 case ISD::AND: return "and"; 2146 case ISD::OR: return "or"; 2147 case ISD::XOR: return "xor"; 2148 case ISD::SHL: return "shl"; 2149 case ISD::SRA: return "sra"; 2150 case ISD::SRL: return "srl"; 2151 2152 case ISD::SETCC: return "setcc"; 2153 case ISD::SELECT: return "select"; 2154 case ISD::SELECT_CC: return "select_cc"; 2155 case ISD::ADD_PARTS: return "add_parts"; 2156 case ISD::SUB_PARTS: return "sub_parts"; 2157 case ISD::SHL_PARTS: return "shl_parts"; 2158 case ISD::SRA_PARTS: return "sra_parts"; 2159 case ISD::SRL_PARTS: return "srl_parts"; 2160 2161 // Conversion operators. 2162 case ISD::SIGN_EXTEND: return "sign_extend"; 2163 case ISD::ZERO_EXTEND: return "zero_extend"; 2164 case ISD::SIGN_EXTEND_INREG: return "sign_extend_inreg"; 2165 case ISD::TRUNCATE: return "truncate"; 2166 case ISD::FP_ROUND: return "fp_round"; 2167 case ISD::FP_ROUND_INREG: return "fp_round_inreg"; 2168 case ISD::FP_EXTEND: return "fp_extend"; 2169 2170 case ISD::SINT_TO_FP: return "sint_to_fp"; 2171 case ISD::UINT_TO_FP: return "uint_to_fp"; 2172 case ISD::FP_TO_SINT: return "fp_to_sint"; 2173 case ISD::FP_TO_UINT: return "fp_to_uint"; 2174 2175 // Control flow instructions 2176 case ISD::BR: return "br"; 2177 case ISD::BRCOND: return "brcond"; 2178 case ISD::BRCONDTWOWAY: return "brcondtwoway"; 2179 case ISD::BR_CC: return "br_cc"; 2180 case ISD::BRTWOWAY_CC: return "brtwoway_cc"; 2181 case ISD::RET: return "ret"; 2182 case ISD::CALL: return "call"; 2183 case ISD::TAILCALL:return "tailcall"; 2184 case ISD::CALLSEQ_START: return "callseq_start"; 2185 case ISD::CALLSEQ_END: return "callseq_end"; 2186 2187 // Other operators 2188 case ISD::LOAD: return "load"; 2189 case ISD::STORE: return "store"; 2190 case ISD::EXTLOAD: return "extload"; 2191 case ISD::SEXTLOAD: return "sextload"; 2192 case ISD::ZEXTLOAD: return "zextload"; 2193 case ISD::TRUNCSTORE: return "truncstore"; 2194 2195 case ISD::DYNAMIC_STACKALLOC: return "dynamic_stackalloc"; 2196 case ISD::EXTRACT_ELEMENT: return "extract_element"; 2197 case ISD::BUILD_PAIR: return "build_pair"; 2198 case ISD::MEMSET: return "memset"; 2199 case ISD::MEMCPY: return "memcpy"; 2200 case ISD::MEMMOVE: return "memmove"; 2201 2202 // Bit counting 2203 case ISD::CTPOP: return "ctpop"; 2204 case ISD::CTTZ: return "cttz"; 2205 case ISD::CTLZ: return "ctlz"; 2206 2207 // IO Intrinsics 2208 case ISD::READPORT: return "readport"; 2209 case ISD::WRITEPORT: return "writeport"; 2210 case ISD::READIO: return "readio"; 2211 case ISD::WRITEIO: return "writeio"; 2212 2213 case ISD::CONDCODE: 2214 switch (cast<CondCodeSDNode>(this)->get()) { 2215 default: assert(0 && "Unknown setcc condition!"); 2216 case ISD::SETOEQ: return "setoeq"; 2217 case ISD::SETOGT: return "setogt"; 2218 case ISD::SETOGE: return "setoge"; 2219 case ISD::SETOLT: return "setolt"; 2220 case ISD::SETOLE: return "setole"; 2221 case ISD::SETONE: return "setone"; 2222 2223 case ISD::SETO: return "seto"; 2224 case ISD::SETUO: return "setuo"; 2225 case ISD::SETUEQ: return "setue"; 2226 case ISD::SETUGT: return "setugt"; 2227 case ISD::SETUGE: return "setuge"; 2228 case ISD::SETULT: return "setult"; 2229 case ISD::SETULE: return "setule"; 2230 case ISD::SETUNE: return "setune"; 2231 2232 case ISD::SETEQ: return "seteq"; 2233 case ISD::SETGT: return "setgt"; 2234 case ISD::SETGE: return "setge"; 2235 case ISD::SETLT: return "setlt"; 2236 case ISD::SETLE: return "setle"; 2237 case ISD::SETNE: return "setne"; 2238 } 2239 } 2240} 2241 2242void SDNode::dump() const { dump(0); } 2243void SDNode::dump(const SelectionDAG *G) const { 2244 std::cerr << (void*)this << ": "; 2245 2246 for (unsigned i = 0, e = getNumValues(); i != e; ++i) { 2247 if (i) std::cerr << ","; 2248 if (getValueType(i) == MVT::Other) 2249 std::cerr << "ch"; 2250 else 2251 std::cerr << MVT::getValueTypeString(getValueType(i)); 2252 } 2253 std::cerr << " = " << getOperationName(G); 2254 2255 std::cerr << " "; 2256 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 2257 if (i) std::cerr << ", "; 2258 std::cerr << (void*)getOperand(i).Val; 2259 if (unsigned RN = getOperand(i).ResNo) 2260 std::cerr << ":" << RN; 2261 } 2262 2263 if (const ConstantSDNode *CSDN = dyn_cast<ConstantSDNode>(this)) { 2264 std::cerr << "<" << CSDN->getValue() << ">"; 2265 } else if (const ConstantFPSDNode *CSDN = dyn_cast<ConstantFPSDNode>(this)) { 2266 std::cerr << "<" << CSDN->getValue() << ">"; 2267 } else if (const GlobalAddressSDNode *GADN = 2268 dyn_cast<GlobalAddressSDNode>(this)) { 2269 std::cerr << "<"; 2270 WriteAsOperand(std::cerr, GADN->getGlobal()) << ">"; 2271 } else if (const FrameIndexSDNode *FIDN = dyn_cast<FrameIndexSDNode>(this)) { 2272 std::cerr << "<" << FIDN->getIndex() << ">"; 2273 } else if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(this)){ 2274 std::cerr << "<" << CP->getIndex() << ">"; 2275 } else if (const BasicBlockSDNode *BBDN = dyn_cast<BasicBlockSDNode>(this)) { 2276 std::cerr << "<"; 2277 const Value *LBB = (const Value*)BBDN->getBasicBlock()->getBasicBlock(); 2278 if (LBB) 2279 std::cerr << LBB->getName() << " "; 2280 std::cerr << (const void*)BBDN->getBasicBlock() << ">"; 2281 } else if (const RegisterSDNode *R = dyn_cast<RegisterSDNode>(this)) { 2282 if (G && MRegisterInfo::isPhysicalRegister(R->getReg())) { 2283 std::cerr << " " <<G->getTarget().getRegisterInfo()->getName(R->getReg()); 2284 } else { 2285 std::cerr << " #" << R->getReg(); 2286 } 2287 } else if (const ExternalSymbolSDNode *ES = 2288 dyn_cast<ExternalSymbolSDNode>(this)) { 2289 std::cerr << "'" << ES->getSymbol() << "'"; 2290 } else if (const SrcValueSDNode *M = dyn_cast<SrcValueSDNode>(this)) { 2291 if (M->getValue()) 2292 std::cerr << "<" << M->getValue() << ":" << M->getOffset() << ">"; 2293 else 2294 std::cerr << "<null:" << M->getOffset() << ">"; 2295 } else if (const VTSDNode *N = dyn_cast<VTSDNode>(this)) { 2296 std::cerr << ":" << getValueTypeString(N->getVT()); 2297 } 2298} 2299 2300static void DumpNodes(SDNode *N, unsigned indent, const SelectionDAG *G) { 2301 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 2302 if (N->getOperand(i).Val->hasOneUse()) 2303 DumpNodes(N->getOperand(i).Val, indent+2, G); 2304 else 2305 std::cerr << "\n" << std::string(indent+2, ' ') 2306 << (void*)N->getOperand(i).Val << ": <multiple use>"; 2307 2308 2309 std::cerr << "\n" << std::string(indent, ' '); 2310 N->dump(G); 2311} 2312 2313void SelectionDAG::dump() const { 2314 std::cerr << "SelectionDAG has " << AllNodes.size() << " nodes:"; 2315 std::vector<SDNode*> Nodes(AllNodes); 2316 std::sort(Nodes.begin(), Nodes.end()); 2317 2318 for (unsigned i = 0, e = Nodes.size(); i != e; ++i) { 2319 if (!Nodes[i]->hasOneUse() && Nodes[i] != getRoot().Val) 2320 DumpNodes(Nodes[i], 2, this); 2321 } 2322 2323 DumpNodes(getRoot().Val, 2, this); 2324 2325 std::cerr << "\n\n"; 2326} 2327 2328