SelectionDAG.cpp revision 6158d8492cc021bb47caee6d4755135ef1d855a4
1//===-- SelectionDAG.cpp - Implement the SelectionDAG data structures -----===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAG class. 11// 12//===----------------------------------------------------------------------===// 13#include "llvm/CodeGen/SelectionDAG.h" 14#include "llvm/Constants.h" 15#include "llvm/Analysis/ValueTracking.h" 16#include "llvm/GlobalAlias.h" 17#include "llvm/GlobalVariable.h" 18#include "llvm/Intrinsics.h" 19#include "llvm/DerivedTypes.h" 20#include "llvm/Assembly/Writer.h" 21#include "llvm/CallingConv.h" 22#include "llvm/CodeGen/MachineBasicBlock.h" 23#include "llvm/CodeGen/MachineConstantPool.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/MachineModuleInfo.h" 26#include "llvm/CodeGen/PseudoSourceValue.h" 27#include "llvm/Target/TargetRegisterInfo.h" 28#include "llvm/Target/TargetData.h" 29#include "llvm/Target/TargetLowering.h" 30#include "llvm/Target/TargetInstrInfo.h" 31#include "llvm/Target/TargetMachine.h" 32#include "llvm/Support/CommandLine.h" 33#include "llvm/Support/MathExtras.h" 34#include "llvm/Support/raw_ostream.h" 35#include "llvm/ADT/SetVector.h" 36#include "llvm/ADT/SmallPtrSet.h" 37#include "llvm/ADT/SmallSet.h" 38#include "llvm/ADT/SmallVector.h" 39#include "llvm/ADT/StringExtras.h" 40#include <algorithm> 41#include <cmath> 42using namespace llvm; 43 44/// makeVTList - Return an instance of the SDVTList struct initialized with the 45/// specified members. 46static SDVTList makeVTList(const MVT *VTs, unsigned NumVTs) { 47 SDVTList Res = {VTs, NumVTs}; 48 return Res; 49} 50 51static const fltSemantics *MVTToAPFloatSemantics(MVT VT) { 52 switch (VT.getSimpleVT()) { 53 default: assert(0 && "Unknown FP format"); 54 case MVT::f32: return &APFloat::IEEEsingle; 55 case MVT::f64: return &APFloat::IEEEdouble; 56 case MVT::f80: return &APFloat::x87DoubleExtended; 57 case MVT::f128: return &APFloat::IEEEquad; 58 case MVT::ppcf128: return &APFloat::PPCDoubleDouble; 59 } 60} 61 62SelectionDAG::DAGUpdateListener::~DAGUpdateListener() {} 63 64//===----------------------------------------------------------------------===// 65// ConstantFPSDNode Class 66//===----------------------------------------------------------------------===// 67 68/// isExactlyValue - We don't rely on operator== working on double values, as 69/// it returns true for things that are clearly not equal, like -0.0 and 0.0. 70/// As such, this method can be used to do an exact bit-for-bit comparison of 71/// two floating point values. 72bool ConstantFPSDNode::isExactlyValue(const APFloat& V) const { 73 return getValueAPF().bitwiseIsEqual(V); 74} 75 76bool ConstantFPSDNode::isValueValidForType(MVT VT, 77 const APFloat& Val) { 78 assert(VT.isFloatingPoint() && "Can only convert between FP types"); 79 80 // PPC long double cannot be converted to any other type. 81 if (VT == MVT::ppcf128 || 82 &Val.getSemantics() == &APFloat::PPCDoubleDouble) 83 return false; 84 85 // convert modifies in place, so make a copy. 86 APFloat Val2 = APFloat(Val); 87 return Val2.convert(*MVTToAPFloatSemantics(VT), 88 APFloat::rmNearestTiesToEven) == APFloat::opOK; 89} 90 91//===----------------------------------------------------------------------===// 92// ISD Namespace 93//===----------------------------------------------------------------------===// 94 95/// isBuildVectorAllOnes - Return true if the specified node is a 96/// BUILD_VECTOR where all of the elements are ~0 or undef. 97bool ISD::isBuildVectorAllOnes(const SDNode *N) { 98 // Look through a bit convert. 99 if (N->getOpcode() == ISD::BIT_CONVERT) 100 N = N->getOperand(0).getNode(); 101 102 if (N->getOpcode() != ISD::BUILD_VECTOR) return false; 103 104 unsigned i = 0, e = N->getNumOperands(); 105 106 // Skip over all of the undef values. 107 while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF) 108 ++i; 109 110 // Do not accept an all-undef vector. 111 if (i == e) return false; 112 113 // Do not accept build_vectors that aren't all constants or which have non-~0 114 // elements. 115 SDValue NotZero = N->getOperand(i); 116 if (isa<ConstantSDNode>(NotZero)) { 117 if (!cast<ConstantSDNode>(NotZero)->isAllOnesValue()) 118 return false; 119 } else if (isa<ConstantFPSDNode>(NotZero)) { 120 if (!cast<ConstantFPSDNode>(NotZero)->getValueAPF(). 121 convertToAPInt().isAllOnesValue()) 122 return false; 123 } else 124 return false; 125 126 // Okay, we have at least one ~0 value, check to see if the rest match or are 127 // undefs. 128 for (++i; i != e; ++i) 129 if (N->getOperand(i) != NotZero && 130 N->getOperand(i).getOpcode() != ISD::UNDEF) 131 return false; 132 return true; 133} 134 135 136/// isBuildVectorAllZeros - Return true if the specified node is a 137/// BUILD_VECTOR where all of the elements are 0 or undef. 138bool ISD::isBuildVectorAllZeros(const SDNode *N) { 139 // Look through a bit convert. 140 if (N->getOpcode() == ISD::BIT_CONVERT) 141 N = N->getOperand(0).getNode(); 142 143 if (N->getOpcode() != ISD::BUILD_VECTOR) return false; 144 145 unsigned i = 0, e = N->getNumOperands(); 146 147 // Skip over all of the undef values. 148 while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF) 149 ++i; 150 151 // Do not accept an all-undef vector. 152 if (i == e) return false; 153 154 // Do not accept build_vectors that aren't all constants or which have non-~0 155 // elements. 156 SDValue Zero = N->getOperand(i); 157 if (isa<ConstantSDNode>(Zero)) { 158 if (!cast<ConstantSDNode>(Zero)->isNullValue()) 159 return false; 160 } else if (isa<ConstantFPSDNode>(Zero)) { 161 if (!cast<ConstantFPSDNode>(Zero)->getValueAPF().isPosZero()) 162 return false; 163 } else 164 return false; 165 166 // Okay, we have at least one ~0 value, check to see if the rest match or are 167 // undefs. 168 for (++i; i != e; ++i) 169 if (N->getOperand(i) != Zero && 170 N->getOperand(i).getOpcode() != ISD::UNDEF) 171 return false; 172 return true; 173} 174 175/// isScalarToVector - Return true if the specified node is a 176/// ISD::SCALAR_TO_VECTOR node or a BUILD_VECTOR node where only the low 177/// element is not an undef. 178bool ISD::isScalarToVector(const SDNode *N) { 179 if (N->getOpcode() == ISD::SCALAR_TO_VECTOR) 180 return true; 181 182 if (N->getOpcode() != ISD::BUILD_VECTOR) 183 return false; 184 if (N->getOperand(0).getOpcode() == ISD::UNDEF) 185 return false; 186 unsigned NumElems = N->getNumOperands(); 187 for (unsigned i = 1; i < NumElems; ++i) { 188 SDValue V = N->getOperand(i); 189 if (V.getOpcode() != ISD::UNDEF) 190 return false; 191 } 192 return true; 193} 194 195 196/// isDebugLabel - Return true if the specified node represents a debug 197/// label (i.e. ISD::DBG_LABEL or TargetInstrInfo::DBG_LABEL node). 198bool ISD::isDebugLabel(const SDNode *N) { 199 SDValue Zero; 200 if (N->getOpcode() == ISD::DBG_LABEL) 201 return true; 202 if (N->isMachineOpcode() && 203 N->getMachineOpcode() == TargetInstrInfo::DBG_LABEL) 204 return true; 205 return false; 206} 207 208/// getSetCCSwappedOperands - Return the operation corresponding to (Y op X) 209/// when given the operation for (X op Y). 210ISD::CondCode ISD::getSetCCSwappedOperands(ISD::CondCode Operation) { 211 // To perform this operation, we just need to swap the L and G bits of the 212 // operation. 213 unsigned OldL = (Operation >> 2) & 1; 214 unsigned OldG = (Operation >> 1) & 1; 215 return ISD::CondCode((Operation & ~6) | // Keep the N, U, E bits 216 (OldL << 1) | // New G bit 217 (OldG << 2)); // New L bit. 218} 219 220/// getSetCCInverse - Return the operation corresponding to !(X op Y), where 221/// 'op' is a valid SetCC operation. 222ISD::CondCode ISD::getSetCCInverse(ISD::CondCode Op, bool isInteger) { 223 unsigned Operation = Op; 224 if (isInteger) 225 Operation ^= 7; // Flip L, G, E bits, but not U. 226 else 227 Operation ^= 15; // Flip all of the condition bits. 228 if (Operation > ISD::SETTRUE2) 229 Operation &= ~8; // Don't let N and U bits get set. 230 return ISD::CondCode(Operation); 231} 232 233 234/// isSignedOp - For an integer comparison, return 1 if the comparison is a 235/// signed operation and 2 if the result is an unsigned comparison. Return zero 236/// if the operation does not depend on the sign of the input (setne and seteq). 237static int isSignedOp(ISD::CondCode Opcode) { 238 switch (Opcode) { 239 default: assert(0 && "Illegal integer setcc operation!"); 240 case ISD::SETEQ: 241 case ISD::SETNE: return 0; 242 case ISD::SETLT: 243 case ISD::SETLE: 244 case ISD::SETGT: 245 case ISD::SETGE: return 1; 246 case ISD::SETULT: 247 case ISD::SETULE: 248 case ISD::SETUGT: 249 case ISD::SETUGE: return 2; 250 } 251} 252 253/// getSetCCOrOperation - Return the result of a logical OR between different 254/// comparisons of identical values: ((X op1 Y) | (X op2 Y)). This function 255/// returns SETCC_INVALID if it is not possible to represent the resultant 256/// comparison. 257ISD::CondCode ISD::getSetCCOrOperation(ISD::CondCode Op1, ISD::CondCode Op2, 258 bool isInteger) { 259 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 260 // Cannot fold a signed integer setcc with an unsigned integer setcc. 261 return ISD::SETCC_INVALID; 262 263 unsigned Op = Op1 | Op2; // Combine all of the condition bits. 264 265 // If the N and U bits get set then the resultant comparison DOES suddenly 266 // care about orderedness, and is true when ordered. 267 if (Op > ISD::SETTRUE2) 268 Op &= ~16; // Clear the U bit if the N bit is set. 269 270 // Canonicalize illegal integer setcc's. 271 if (isInteger && Op == ISD::SETUNE) // e.g. SETUGT | SETULT 272 Op = ISD::SETNE; 273 274 return ISD::CondCode(Op); 275} 276 277/// getSetCCAndOperation - Return the result of a logical AND between different 278/// comparisons of identical values: ((X op1 Y) & (X op2 Y)). This 279/// function returns zero if it is not possible to represent the resultant 280/// comparison. 281ISD::CondCode ISD::getSetCCAndOperation(ISD::CondCode Op1, ISD::CondCode Op2, 282 bool isInteger) { 283 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 284 // Cannot fold a signed setcc with an unsigned setcc. 285 return ISD::SETCC_INVALID; 286 287 // Combine all of the condition bits. 288 ISD::CondCode Result = ISD::CondCode(Op1 & Op2); 289 290 // Canonicalize illegal integer setcc's. 291 if (isInteger) { 292 switch (Result) { 293 default: break; 294 case ISD::SETUO : Result = ISD::SETFALSE; break; // SETUGT & SETULT 295 case ISD::SETOEQ: // SETEQ & SETU[LG]E 296 case ISD::SETUEQ: Result = ISD::SETEQ ; break; // SETUGE & SETULE 297 case ISD::SETOLT: Result = ISD::SETULT ; break; // SETULT & SETNE 298 case ISD::SETOGT: Result = ISD::SETUGT ; break; // SETUGT & SETNE 299 } 300 } 301 302 return Result; 303} 304 305const TargetMachine &SelectionDAG::getTarget() const { 306 return MF->getTarget(); 307} 308 309//===----------------------------------------------------------------------===// 310// SDNode Profile Support 311//===----------------------------------------------------------------------===// 312 313/// AddNodeIDOpcode - Add the node opcode to the NodeID data. 314/// 315static void AddNodeIDOpcode(FoldingSetNodeID &ID, unsigned OpC) { 316 ID.AddInteger(OpC); 317} 318 319/// AddNodeIDValueTypes - Value type lists are intern'd so we can represent them 320/// solely with their pointer. 321static void AddNodeIDValueTypes(FoldingSetNodeID &ID, SDVTList VTList) { 322 ID.AddPointer(VTList.VTs); 323} 324 325/// AddNodeIDOperands - Various routines for adding operands to the NodeID data. 326/// 327static void AddNodeIDOperands(FoldingSetNodeID &ID, 328 const SDValue *Ops, unsigned NumOps) { 329 for (; NumOps; --NumOps, ++Ops) { 330 ID.AddPointer(Ops->getNode()); 331 ID.AddInteger(Ops->getResNo()); 332 } 333} 334 335/// AddNodeIDOperands - Various routines for adding operands to the NodeID data. 336/// 337static void AddNodeIDOperands(FoldingSetNodeID &ID, 338 const SDUse *Ops, unsigned NumOps) { 339 for (; NumOps; --NumOps, ++Ops) { 340 ID.AddPointer(Ops->getVal()); 341 ID.AddInteger(Ops->getSDValue().getResNo()); 342 } 343} 344 345static void AddNodeIDNode(FoldingSetNodeID &ID, 346 unsigned short OpC, SDVTList VTList, 347 const SDValue *OpList, unsigned N) { 348 AddNodeIDOpcode(ID, OpC); 349 AddNodeIDValueTypes(ID, VTList); 350 AddNodeIDOperands(ID, OpList, N); 351} 352 353 354/// AddNodeIDNode - Generic routine for adding a nodes info to the NodeID 355/// data. 356static void AddNodeIDNode(FoldingSetNodeID &ID, const SDNode *N) { 357 AddNodeIDOpcode(ID, N->getOpcode()); 358 // Add the return value info. 359 AddNodeIDValueTypes(ID, N->getVTList()); 360 // Add the operand info. 361 AddNodeIDOperands(ID, N->op_begin(), N->getNumOperands()); 362 363 // Handle SDNode leafs with special info. 364 switch (N->getOpcode()) { 365 default: break; // Normal nodes don't need extra info. 366 case ISD::ARG_FLAGS: 367 ID.AddInteger(cast<ARG_FLAGSSDNode>(N)->getArgFlags().getRawBits()); 368 break; 369 case ISD::TargetConstant: 370 case ISD::Constant: 371 ID.AddPointer(cast<ConstantSDNode>(N)->getConstantIntValue()); 372 break; 373 case ISD::TargetConstantFP: 374 case ISD::ConstantFP: { 375 ID.AddPointer(cast<ConstantFPSDNode>(N)->getConstantFPValue()); 376 break; 377 } 378 case ISD::TargetGlobalAddress: 379 case ISD::GlobalAddress: 380 case ISD::TargetGlobalTLSAddress: 381 case ISD::GlobalTLSAddress: { 382 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(N); 383 ID.AddPointer(GA->getGlobal()); 384 ID.AddInteger(GA->getOffset()); 385 break; 386 } 387 case ISD::BasicBlock: 388 ID.AddPointer(cast<BasicBlockSDNode>(N)->getBasicBlock()); 389 break; 390 case ISD::Register: 391 ID.AddInteger(cast<RegisterSDNode>(N)->getReg()); 392 break; 393 case ISD::DBG_STOPPOINT: { 394 const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(N); 395 ID.AddInteger(DSP->getLine()); 396 ID.AddInteger(DSP->getColumn()); 397 ID.AddPointer(DSP->getCompileUnit()); 398 break; 399 } 400 case ISD::SRCVALUE: 401 ID.AddPointer(cast<SrcValueSDNode>(N)->getValue()); 402 break; 403 case ISD::MEMOPERAND: { 404 const MachineMemOperand &MO = cast<MemOperandSDNode>(N)->MO; 405 MO.Profile(ID); 406 break; 407 } 408 case ISD::FrameIndex: 409 case ISD::TargetFrameIndex: 410 ID.AddInteger(cast<FrameIndexSDNode>(N)->getIndex()); 411 break; 412 case ISD::JumpTable: 413 case ISD::TargetJumpTable: 414 ID.AddInteger(cast<JumpTableSDNode>(N)->getIndex()); 415 break; 416 case ISD::ConstantPool: 417 case ISD::TargetConstantPool: { 418 const ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(N); 419 ID.AddInteger(CP->getAlignment()); 420 ID.AddInteger(CP->getOffset()); 421 if (CP->isMachineConstantPoolEntry()) 422 CP->getMachineCPVal()->AddSelectionDAGCSEId(ID); 423 else 424 ID.AddPointer(CP->getConstVal()); 425 break; 426 } 427 case ISD::CALL: { 428 const CallSDNode *Call = cast<CallSDNode>(N); 429 ID.AddInteger(Call->getCallingConv()); 430 ID.AddInteger(Call->isVarArg()); 431 break; 432 } 433 case ISD::LOAD: { 434 const LoadSDNode *LD = cast<LoadSDNode>(N); 435 ID.AddInteger(LD->getAddressingMode()); 436 ID.AddInteger(LD->getExtensionType()); 437 ID.AddInteger(LD->getMemoryVT().getRawBits()); 438 ID.AddInteger(LD->getRawFlags()); 439 break; 440 } 441 case ISD::STORE: { 442 const StoreSDNode *ST = cast<StoreSDNode>(N); 443 ID.AddInteger(ST->getAddressingMode()); 444 ID.AddInteger(ST->isTruncatingStore()); 445 ID.AddInteger(ST->getMemoryVT().getRawBits()); 446 ID.AddInteger(ST->getRawFlags()); 447 break; 448 } 449 case ISD::ATOMIC_CMP_SWAP_8: 450 case ISD::ATOMIC_SWAP_8: 451 case ISD::ATOMIC_LOAD_ADD_8: 452 case ISD::ATOMIC_LOAD_SUB_8: 453 case ISD::ATOMIC_LOAD_AND_8: 454 case ISD::ATOMIC_LOAD_OR_8: 455 case ISD::ATOMIC_LOAD_XOR_8: 456 case ISD::ATOMIC_LOAD_NAND_8: 457 case ISD::ATOMIC_LOAD_MIN_8: 458 case ISD::ATOMIC_LOAD_MAX_8: 459 case ISD::ATOMIC_LOAD_UMIN_8: 460 case ISD::ATOMIC_LOAD_UMAX_8: 461 case ISD::ATOMIC_CMP_SWAP_16: 462 case ISD::ATOMIC_SWAP_16: 463 case ISD::ATOMIC_LOAD_ADD_16: 464 case ISD::ATOMIC_LOAD_SUB_16: 465 case ISD::ATOMIC_LOAD_AND_16: 466 case ISD::ATOMIC_LOAD_OR_16: 467 case ISD::ATOMIC_LOAD_XOR_16: 468 case ISD::ATOMIC_LOAD_NAND_16: 469 case ISD::ATOMIC_LOAD_MIN_16: 470 case ISD::ATOMIC_LOAD_MAX_16: 471 case ISD::ATOMIC_LOAD_UMIN_16: 472 case ISD::ATOMIC_LOAD_UMAX_16: 473 case ISD::ATOMIC_CMP_SWAP_32: 474 case ISD::ATOMIC_SWAP_32: 475 case ISD::ATOMIC_LOAD_ADD_32: 476 case ISD::ATOMIC_LOAD_SUB_32: 477 case ISD::ATOMIC_LOAD_AND_32: 478 case ISD::ATOMIC_LOAD_OR_32: 479 case ISD::ATOMIC_LOAD_XOR_32: 480 case ISD::ATOMIC_LOAD_NAND_32: 481 case ISD::ATOMIC_LOAD_MIN_32: 482 case ISD::ATOMIC_LOAD_MAX_32: 483 case ISD::ATOMIC_LOAD_UMIN_32: 484 case ISD::ATOMIC_LOAD_UMAX_32: 485 case ISD::ATOMIC_CMP_SWAP_64: 486 case ISD::ATOMIC_SWAP_64: 487 case ISD::ATOMIC_LOAD_ADD_64: 488 case ISD::ATOMIC_LOAD_SUB_64: 489 case ISD::ATOMIC_LOAD_AND_64: 490 case ISD::ATOMIC_LOAD_OR_64: 491 case ISD::ATOMIC_LOAD_XOR_64: 492 case ISD::ATOMIC_LOAD_NAND_64: 493 case ISD::ATOMIC_LOAD_MIN_64: 494 case ISD::ATOMIC_LOAD_MAX_64: 495 case ISD::ATOMIC_LOAD_UMIN_64: 496 case ISD::ATOMIC_LOAD_UMAX_64: { 497 const AtomicSDNode *AT = cast<AtomicSDNode>(N); 498 ID.AddInteger(AT->getRawFlags()); 499 break; 500 } 501 } // end switch (N->getOpcode()) 502} 503 504/// encodeMemSDNodeFlags - Generic routine for computing a value for use in 505/// the CSE map that carries both alignment and volatility information. 506/// 507static unsigned encodeMemSDNodeFlags(bool isVolatile, unsigned Alignment) { 508 return isVolatile | ((Log2_32(Alignment) + 1) << 1); 509} 510 511//===----------------------------------------------------------------------===// 512// SelectionDAG Class 513//===----------------------------------------------------------------------===// 514 515/// RemoveDeadNodes - This method deletes all unreachable nodes in the 516/// SelectionDAG. 517void SelectionDAG::RemoveDeadNodes() { 518 // Create a dummy node (which is not added to allnodes), that adds a reference 519 // to the root node, preventing it from being deleted. 520 HandleSDNode Dummy(getRoot()); 521 522 SmallVector<SDNode*, 128> DeadNodes; 523 524 // Add all obviously-dead nodes to the DeadNodes worklist. 525 for (allnodes_iterator I = allnodes_begin(), E = allnodes_end(); I != E; ++I) 526 if (I->use_empty()) 527 DeadNodes.push_back(I); 528 529 RemoveDeadNodes(DeadNodes); 530 531 // If the root changed (e.g. it was a dead load, update the root). 532 setRoot(Dummy.getValue()); 533} 534 535/// RemoveDeadNodes - This method deletes the unreachable nodes in the 536/// given list, and any nodes that become unreachable as a result. 537void SelectionDAG::RemoveDeadNodes(SmallVectorImpl<SDNode *> &DeadNodes, 538 DAGUpdateListener *UpdateListener) { 539 540 // Process the worklist, deleting the nodes and adding their uses to the 541 // worklist. 542 while (!DeadNodes.empty()) { 543 SDNode *N = DeadNodes.back(); 544 DeadNodes.pop_back(); 545 546 if (UpdateListener) 547 UpdateListener->NodeDeleted(N, 0); 548 549 // Take the node out of the appropriate CSE map. 550 RemoveNodeFromCSEMaps(N); 551 552 // Next, brutally remove the operand list. This is safe to do, as there are 553 // no cycles in the graph. 554 for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ++I) { 555 SDNode *Operand = I->getVal(); 556 Operand->removeUser(std::distance(N->op_begin(), I), N); 557 558 // Now that we removed this operand, see if there are no uses of it left. 559 if (Operand->use_empty()) 560 DeadNodes.push_back(Operand); 561 } 562 if (N->OperandsNeedDelete) { 563 delete[] N->OperandList; 564 } 565 N->OperandList = 0; 566 N->NumOperands = 0; 567 568 // Finally, remove N itself. 569 NodeAllocator.Deallocate(AllNodes.remove(N)); 570 } 571} 572 573void SelectionDAG::RemoveDeadNode(SDNode *N, DAGUpdateListener *UpdateListener){ 574 SmallVector<SDNode*, 16> DeadNodes(1, N); 575 RemoveDeadNodes(DeadNodes, UpdateListener); 576} 577 578void SelectionDAG::DeleteNode(SDNode *N) { 579 assert(N->use_empty() && "Cannot delete a node that is not dead!"); 580 581 // First take this out of the appropriate CSE map. 582 RemoveNodeFromCSEMaps(N); 583 584 // Finally, remove uses due to operands of this node, remove from the 585 // AllNodes list, and delete the node. 586 DeleteNodeNotInCSEMaps(N); 587} 588 589void SelectionDAG::DeleteNodeNotInCSEMaps(SDNode *N) { 590 591 // Drop all of the operands and decrement used node's use counts. 592 for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ++I) 593 I->getVal()->removeUser(std::distance(N->op_begin(), I), N); 594 if (N->OperandsNeedDelete) 595 delete[] N->OperandList; 596 597 assert(N != AllNodes.begin()); 598 NodeAllocator.Deallocate(AllNodes.remove(N)); 599} 600 601/// RemoveNodeFromCSEMaps - Take the specified node out of the CSE map that 602/// correspond to it. This is useful when we're about to delete or repurpose 603/// the node. We don't want future request for structurally identical nodes 604/// to return N anymore. 605bool SelectionDAG::RemoveNodeFromCSEMaps(SDNode *N) { 606 bool Erased = false; 607 switch (N->getOpcode()) { 608 case ISD::EntryToken: 609 assert(0 && "EntryToken should not be in CSEMaps!"); 610 return false; 611 case ISD::HANDLENODE: return false; // noop. 612 case ISD::CONDCODE: 613 assert(CondCodeNodes[cast<CondCodeSDNode>(N)->get()] && 614 "Cond code doesn't exist!"); 615 Erased = CondCodeNodes[cast<CondCodeSDNode>(N)->get()] != 0; 616 CondCodeNodes[cast<CondCodeSDNode>(N)->get()] = 0; 617 break; 618 case ISD::ExternalSymbol: 619 Erased = ExternalSymbols.erase(cast<ExternalSymbolSDNode>(N)->getSymbol()); 620 break; 621 case ISD::TargetExternalSymbol: 622 Erased = 623 TargetExternalSymbols.erase(cast<ExternalSymbolSDNode>(N)->getSymbol()); 624 break; 625 case ISD::VALUETYPE: { 626 MVT VT = cast<VTSDNode>(N)->getVT(); 627 if (VT.isExtended()) { 628 Erased = ExtendedValueTypeNodes.erase(VT); 629 } else { 630 Erased = ValueTypeNodes[VT.getSimpleVT()] != 0; 631 ValueTypeNodes[VT.getSimpleVT()] = 0; 632 } 633 break; 634 } 635 default: 636 // Remove it from the CSE Map. 637 Erased = CSEMap.RemoveNode(N); 638 break; 639 } 640#ifndef NDEBUG 641 // Verify that the node was actually in one of the CSE maps, unless it has a 642 // flag result (which cannot be CSE'd) or is one of the special cases that are 643 // not subject to CSE. 644 if (!Erased && N->getValueType(N->getNumValues()-1) != MVT::Flag && 645 !N->isMachineOpcode() && 646 N->getOpcode() != ISD::DBG_LABEL && 647 N->getOpcode() != ISD::DBG_STOPPOINT && 648 N->getOpcode() != ISD::EH_LABEL && 649 N->getOpcode() != ISD::DECLARE) { 650 N->dump(this); 651 cerr << "\n"; 652 assert(0 && "Node is not in map!"); 653 } 654#endif 655 return Erased; 656} 657 658/// AddNonLeafNodeToCSEMaps - Add the specified node back to the CSE maps. It 659/// has been taken out and modified in some way. If the specified node already 660/// exists in the CSE maps, do not modify the maps, but return the existing node 661/// instead. If it doesn't exist, add it and return null. 662/// 663SDNode *SelectionDAG::AddNonLeafNodeToCSEMaps(SDNode *N) { 664 assert(N->getNumOperands() && "This is a leaf node!"); 665 666 if (N->getValueType(0) == MVT::Flag) 667 return 0; // Never CSE anything that produces a flag. 668 669 switch (N->getOpcode()) { 670 default: break; 671 case ISD::HANDLENODE: 672 case ISD::DBG_LABEL: 673 case ISD::DBG_STOPPOINT: 674 case ISD::EH_LABEL: 675 case ISD::DECLARE: 676 return 0; // Never add these nodes. 677 } 678 679 // Check that remaining values produced are not flags. 680 for (unsigned i = 1, e = N->getNumValues(); i != e; ++i) 681 if (N->getValueType(i) == MVT::Flag) 682 return 0; // Never CSE anything that produces a flag. 683 684 SDNode *New = CSEMap.GetOrInsertNode(N); 685 if (New != N) return New; // Node already existed. 686 return 0; 687} 688 689/// FindModifiedNodeSlot - Find a slot for the specified node if its operands 690/// were replaced with those specified. If this node is never memoized, 691/// return null, otherwise return a pointer to the slot it would take. If a 692/// node already exists with these operands, the slot will be non-null. 693SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, SDValue Op, 694 void *&InsertPos) { 695 if (N->getValueType(0) == MVT::Flag) 696 return 0; // Never CSE anything that produces a flag. 697 698 switch (N->getOpcode()) { 699 default: break; 700 case ISD::HANDLENODE: 701 case ISD::DBG_LABEL: 702 case ISD::DBG_STOPPOINT: 703 case ISD::EH_LABEL: 704 return 0; // Never add these nodes. 705 } 706 707 // Check that remaining values produced are not flags. 708 for (unsigned i = 1, e = N->getNumValues(); i != e; ++i) 709 if (N->getValueType(i) == MVT::Flag) 710 return 0; // Never CSE anything that produces a flag. 711 712 SDValue Ops[] = { Op }; 713 FoldingSetNodeID ID; 714 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, 1); 715 return CSEMap.FindNodeOrInsertPos(ID, InsertPos); 716} 717 718/// FindModifiedNodeSlot - Find a slot for the specified node if its operands 719/// were replaced with those specified. If this node is never memoized, 720/// return null, otherwise return a pointer to the slot it would take. If a 721/// node already exists with these operands, the slot will be non-null. 722SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, 723 SDValue Op1, SDValue Op2, 724 void *&InsertPos) { 725 if (N->getOpcode() == ISD::HANDLENODE || N->getValueType(0) == MVT::Flag) 726 727 // Check that remaining values produced are not flags. 728 for (unsigned i = 1, e = N->getNumValues(); i != e; ++i) 729 if (N->getValueType(i) == MVT::Flag) 730 return 0; // Never CSE anything that produces a flag. 731 732 SDValue Ops[] = { Op1, Op2 }; 733 FoldingSetNodeID ID; 734 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, 2); 735 return CSEMap.FindNodeOrInsertPos(ID, InsertPos); 736} 737 738 739/// FindModifiedNodeSlot - Find a slot for the specified node if its operands 740/// were replaced with those specified. If this node is never memoized, 741/// return null, otherwise return a pointer to the slot it would take. If a 742/// node already exists with these operands, the slot will be non-null. 743SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, 744 const SDValue *Ops,unsigned NumOps, 745 void *&InsertPos) { 746 if (N->getValueType(0) == MVT::Flag) 747 return 0; // Never CSE anything that produces a flag. 748 749 switch (N->getOpcode()) { 750 default: break; 751 case ISD::HANDLENODE: 752 case ISD::DBG_LABEL: 753 case ISD::DBG_STOPPOINT: 754 case ISD::EH_LABEL: 755 case ISD::DECLARE: 756 return 0; // Never add these nodes. 757 } 758 759 // Check that remaining values produced are not flags. 760 for (unsigned i = 1, e = N->getNumValues(); i != e; ++i) 761 if (N->getValueType(i) == MVT::Flag) 762 return 0; // Never CSE anything that produces a flag. 763 764 FoldingSetNodeID ID; 765 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, NumOps); 766 767 if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 768 ID.AddInteger(LD->getAddressingMode()); 769 ID.AddInteger(LD->getExtensionType()); 770 ID.AddInteger(LD->getMemoryVT().getRawBits()); 771 ID.AddInteger(LD->getRawFlags()); 772 } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 773 ID.AddInteger(ST->getAddressingMode()); 774 ID.AddInteger(ST->isTruncatingStore()); 775 ID.AddInteger(ST->getMemoryVT().getRawBits()); 776 ID.AddInteger(ST->getRawFlags()); 777 } 778 779 return CSEMap.FindNodeOrInsertPos(ID, InsertPos); 780} 781 782/// VerifyNode - Sanity check the given node. Aborts if it is invalid. 783void SelectionDAG::VerifyNode(SDNode *N) { 784 switch (N->getOpcode()) { 785 default: 786 break; 787 case ISD::BUILD_VECTOR: { 788 assert(N->getNumValues() == 1 && "Too many results for BUILD_VECTOR!"); 789 assert(N->getValueType(0).isVector() && "Wrong BUILD_VECTOR return type!"); 790 assert(N->getNumOperands() == N->getValueType(0).getVectorNumElements() && 791 "Wrong number of BUILD_VECTOR operands!"); 792 MVT EltVT = N->getValueType(0).getVectorElementType(); 793 for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ++I) 794 assert(I->getSDValue().getValueType() == EltVT && 795 "Wrong BUILD_VECTOR operand type!"); 796 break; 797 } 798 } 799} 800 801/// getMVTAlignment - Compute the default alignment value for the 802/// given type. 803/// 804unsigned SelectionDAG::getMVTAlignment(MVT VT) const { 805 const Type *Ty = VT == MVT::iPTR ? 806 PointerType::get(Type::Int8Ty, 0) : 807 VT.getTypeForMVT(); 808 809 return TLI.getTargetData()->getABITypeAlignment(Ty); 810} 811 812SelectionDAG::SelectionDAG(TargetLowering &tli, FunctionLoweringInfo &fli) 813 : TLI(tli), FLI(fli), 814 EntryNode(ISD::EntryToken, getVTList(MVT::Other)), 815 Root(getEntryNode()) { 816 AllNodes.push_back(&EntryNode); 817} 818 819void SelectionDAG::init(MachineFunction &mf, MachineModuleInfo *mmi) { 820 MF = &mf; 821 MMI = mmi; 822} 823 824SelectionDAG::~SelectionDAG() { 825 allnodes_clear(); 826} 827 828void SelectionDAG::allnodes_clear() { 829 assert(&*AllNodes.begin() == &EntryNode); 830 AllNodes.remove(AllNodes.begin()); 831 while (!AllNodes.empty()) { 832 SDNode *N = AllNodes.remove(AllNodes.begin()); 833 N->SetNextInBucket(0); 834 if (N->OperandsNeedDelete) 835 delete [] N->OperandList; 836 NodeAllocator.Deallocate(N); 837 } 838} 839 840void SelectionDAG::clear() { 841 allnodes_clear(); 842 OperandAllocator.Reset(); 843 CSEMap.clear(); 844 845 ExtendedValueTypeNodes.clear(); 846 ExternalSymbols.clear(); 847 TargetExternalSymbols.clear(); 848 std::fill(CondCodeNodes.begin(), CondCodeNodes.end(), 849 static_cast<CondCodeSDNode*>(0)); 850 std::fill(ValueTypeNodes.begin(), ValueTypeNodes.end(), 851 static_cast<SDNode*>(0)); 852 853 EntryNode.Uses = 0; 854 AllNodes.push_back(&EntryNode); 855 Root = getEntryNode(); 856} 857 858SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, MVT VT) { 859 if (Op.getValueType() == VT) return Op; 860 APInt Imm = APInt::getLowBitsSet(Op.getValueSizeInBits(), 861 VT.getSizeInBits()); 862 return getNode(ISD::AND, Op.getValueType(), Op, 863 getConstant(Imm, Op.getValueType())); 864} 865 866SDValue SelectionDAG::getConstant(uint64_t Val, MVT VT, bool isT) { 867 MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 868 return getConstant(APInt(EltVT.getSizeInBits(), Val), VT, isT); 869} 870 871SDValue SelectionDAG::getConstant(const APInt &Val, MVT VT, bool isT) { 872 return getConstant(*ConstantInt::get(Val), VT, isT); 873} 874 875SDValue SelectionDAG::getConstant(const ConstantInt &Val, MVT VT, bool isT) { 876 assert(VT.isInteger() && "Cannot create FP integer constant!"); 877 878 MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 879 assert(Val.getBitWidth() == EltVT.getSizeInBits() && 880 "APInt size does not match type size!"); 881 882 unsigned Opc = isT ? ISD::TargetConstant : ISD::Constant; 883 FoldingSetNodeID ID; 884 AddNodeIDNode(ID, Opc, getVTList(EltVT), 0, 0); 885 ID.AddPointer(&Val); 886 void *IP = 0; 887 SDNode *N = NULL; 888 if ((N = CSEMap.FindNodeOrInsertPos(ID, IP))) 889 if (!VT.isVector()) 890 return SDValue(N, 0); 891 if (!N) { 892 N = NodeAllocator.Allocate<ConstantSDNode>(); 893 new (N) ConstantSDNode(isT, &Val, EltVT); 894 CSEMap.InsertNode(N, IP); 895 AllNodes.push_back(N); 896 } 897 898 SDValue Result(N, 0); 899 if (VT.isVector()) { 900 SmallVector<SDValue, 8> Ops; 901 Ops.assign(VT.getVectorNumElements(), Result); 902 Result = getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 903 } 904 return Result; 905} 906 907SDValue SelectionDAG::getIntPtrConstant(uint64_t Val, bool isTarget) { 908 return getConstant(Val, TLI.getPointerTy(), isTarget); 909} 910 911 912SDValue SelectionDAG::getConstantFP(const APFloat& V, MVT VT, bool isTarget) { 913 return getConstantFP(*ConstantFP::get(V), VT, isTarget); 914} 915 916SDValue SelectionDAG::getConstantFP(const ConstantFP& V, MVT VT, bool isTarget){ 917 assert(VT.isFloatingPoint() && "Cannot create integer FP constant!"); 918 919 MVT EltVT = 920 VT.isVector() ? VT.getVectorElementType() : VT; 921 922 // Do the map lookup using the actual bit pattern for the floating point 923 // value, so that we don't have problems with 0.0 comparing equal to -0.0, and 924 // we don't have issues with SNANs. 925 unsigned Opc = isTarget ? ISD::TargetConstantFP : ISD::ConstantFP; 926 FoldingSetNodeID ID; 927 AddNodeIDNode(ID, Opc, getVTList(EltVT), 0, 0); 928 ID.AddPointer(&V); 929 void *IP = 0; 930 SDNode *N = NULL; 931 if ((N = CSEMap.FindNodeOrInsertPos(ID, IP))) 932 if (!VT.isVector()) 933 return SDValue(N, 0); 934 if (!N) { 935 N = NodeAllocator.Allocate<ConstantFPSDNode>(); 936 new (N) ConstantFPSDNode(isTarget, &V, EltVT); 937 CSEMap.InsertNode(N, IP); 938 AllNodes.push_back(N); 939 } 940 941 SDValue Result(N, 0); 942 if (VT.isVector()) { 943 SmallVector<SDValue, 8> Ops; 944 Ops.assign(VT.getVectorNumElements(), Result); 945 Result = getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 946 } 947 return Result; 948} 949 950SDValue SelectionDAG::getConstantFP(double Val, MVT VT, bool isTarget) { 951 MVT EltVT = 952 VT.isVector() ? VT.getVectorElementType() : VT; 953 if (EltVT==MVT::f32) 954 return getConstantFP(APFloat((float)Val), VT, isTarget); 955 else 956 return getConstantFP(APFloat(Val), VT, isTarget); 957} 958 959SDValue SelectionDAG::getGlobalAddress(const GlobalValue *GV, 960 MVT VT, int Offset, 961 bool isTargetGA) { 962 unsigned Opc; 963 964 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV); 965 if (!GVar) { 966 // If GV is an alias then use the aliasee for determining thread-localness. 967 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) 968 GVar = dyn_cast_or_null<GlobalVariable>(GA->resolveAliasedGlobal(false)); 969 } 970 971 if (GVar && GVar->isThreadLocal()) 972 Opc = isTargetGA ? ISD::TargetGlobalTLSAddress : ISD::GlobalTLSAddress; 973 else 974 Opc = isTargetGA ? ISD::TargetGlobalAddress : ISD::GlobalAddress; 975 976 FoldingSetNodeID ID; 977 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 978 ID.AddPointer(GV); 979 ID.AddInteger(Offset); 980 void *IP = 0; 981 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 982 return SDValue(E, 0); 983 SDNode *N = NodeAllocator.Allocate<GlobalAddressSDNode>(); 984 new (N) GlobalAddressSDNode(isTargetGA, GV, VT, Offset); 985 CSEMap.InsertNode(N, IP); 986 AllNodes.push_back(N); 987 return SDValue(N, 0); 988} 989 990SDValue SelectionDAG::getFrameIndex(int FI, MVT VT, bool isTarget) { 991 unsigned Opc = isTarget ? ISD::TargetFrameIndex : ISD::FrameIndex; 992 FoldingSetNodeID ID; 993 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 994 ID.AddInteger(FI); 995 void *IP = 0; 996 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 997 return SDValue(E, 0); 998 SDNode *N = NodeAllocator.Allocate<FrameIndexSDNode>(); 999 new (N) FrameIndexSDNode(FI, VT, isTarget); 1000 CSEMap.InsertNode(N, IP); 1001 AllNodes.push_back(N); 1002 return SDValue(N, 0); 1003} 1004 1005SDValue SelectionDAG::getJumpTable(int JTI, MVT VT, bool isTarget){ 1006 unsigned Opc = isTarget ? ISD::TargetJumpTable : ISD::JumpTable; 1007 FoldingSetNodeID ID; 1008 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 1009 ID.AddInteger(JTI); 1010 void *IP = 0; 1011 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1012 return SDValue(E, 0); 1013 SDNode *N = NodeAllocator.Allocate<JumpTableSDNode>(); 1014 new (N) JumpTableSDNode(JTI, VT, isTarget); 1015 CSEMap.InsertNode(N, IP); 1016 AllNodes.push_back(N); 1017 return SDValue(N, 0); 1018} 1019 1020SDValue SelectionDAG::getConstantPool(Constant *C, MVT VT, 1021 unsigned Alignment, int Offset, 1022 bool isTarget) { 1023 if (Alignment == 0) 1024 Alignment = 1025 TLI.getTargetData()->getPreferredTypeAlignmentShift(C->getType()); 1026 unsigned Opc = isTarget ? ISD::TargetConstantPool : ISD::ConstantPool; 1027 FoldingSetNodeID ID; 1028 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 1029 ID.AddInteger(Alignment); 1030 ID.AddInteger(Offset); 1031 ID.AddPointer(C); 1032 void *IP = 0; 1033 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1034 return SDValue(E, 0); 1035 SDNode *N = NodeAllocator.Allocate<ConstantPoolSDNode>(); 1036 new (N) ConstantPoolSDNode(isTarget, C, VT, Offset, Alignment); 1037 CSEMap.InsertNode(N, IP); 1038 AllNodes.push_back(N); 1039 return SDValue(N, 0); 1040} 1041 1042 1043SDValue SelectionDAG::getConstantPool(MachineConstantPoolValue *C, MVT VT, 1044 unsigned Alignment, int Offset, 1045 bool isTarget) { 1046 if (Alignment == 0) 1047 Alignment = 1048 TLI.getTargetData()->getPreferredTypeAlignmentShift(C->getType()); 1049 unsigned Opc = isTarget ? ISD::TargetConstantPool : ISD::ConstantPool; 1050 FoldingSetNodeID ID; 1051 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 1052 ID.AddInteger(Alignment); 1053 ID.AddInteger(Offset); 1054 C->AddSelectionDAGCSEId(ID); 1055 void *IP = 0; 1056 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1057 return SDValue(E, 0); 1058 SDNode *N = NodeAllocator.Allocate<ConstantPoolSDNode>(); 1059 new (N) ConstantPoolSDNode(isTarget, C, VT, Offset, Alignment); 1060 CSEMap.InsertNode(N, IP); 1061 AllNodes.push_back(N); 1062 return SDValue(N, 0); 1063} 1064 1065 1066SDValue SelectionDAG::getBasicBlock(MachineBasicBlock *MBB) { 1067 FoldingSetNodeID ID; 1068 AddNodeIDNode(ID, ISD::BasicBlock, getVTList(MVT::Other), 0, 0); 1069 ID.AddPointer(MBB); 1070 void *IP = 0; 1071 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1072 return SDValue(E, 0); 1073 SDNode *N = NodeAllocator.Allocate<BasicBlockSDNode>(); 1074 new (N) BasicBlockSDNode(MBB); 1075 CSEMap.InsertNode(N, IP); 1076 AllNodes.push_back(N); 1077 return SDValue(N, 0); 1078} 1079 1080SDValue SelectionDAG::getArgFlags(ISD::ArgFlagsTy Flags) { 1081 FoldingSetNodeID ID; 1082 AddNodeIDNode(ID, ISD::ARG_FLAGS, getVTList(MVT::Other), 0, 0); 1083 ID.AddInteger(Flags.getRawBits()); 1084 void *IP = 0; 1085 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1086 return SDValue(E, 0); 1087 SDNode *N = NodeAllocator.Allocate<ARG_FLAGSSDNode>(); 1088 new (N) ARG_FLAGSSDNode(Flags); 1089 CSEMap.InsertNode(N, IP); 1090 AllNodes.push_back(N); 1091 return SDValue(N, 0); 1092} 1093 1094SDValue SelectionDAG::getValueType(MVT VT) { 1095 if (VT.isSimple() && (unsigned)VT.getSimpleVT() >= ValueTypeNodes.size()) 1096 ValueTypeNodes.resize(VT.getSimpleVT()+1); 1097 1098 SDNode *&N = VT.isExtended() ? 1099 ExtendedValueTypeNodes[VT] : ValueTypeNodes[VT.getSimpleVT()]; 1100 1101 if (N) return SDValue(N, 0); 1102 N = NodeAllocator.Allocate<VTSDNode>(); 1103 new (N) VTSDNode(VT); 1104 AllNodes.push_back(N); 1105 return SDValue(N, 0); 1106} 1107 1108SDValue SelectionDAG::getExternalSymbol(const char *Sym, MVT VT) { 1109 SDNode *&N = ExternalSymbols[Sym]; 1110 if (N) return SDValue(N, 0); 1111 N = NodeAllocator.Allocate<ExternalSymbolSDNode>(); 1112 new (N) ExternalSymbolSDNode(false, Sym, VT); 1113 AllNodes.push_back(N); 1114 return SDValue(N, 0); 1115} 1116 1117SDValue SelectionDAG::getTargetExternalSymbol(const char *Sym, MVT VT) { 1118 SDNode *&N = TargetExternalSymbols[Sym]; 1119 if (N) return SDValue(N, 0); 1120 N = NodeAllocator.Allocate<ExternalSymbolSDNode>(); 1121 new (N) ExternalSymbolSDNode(true, Sym, VT); 1122 AllNodes.push_back(N); 1123 return SDValue(N, 0); 1124} 1125 1126SDValue SelectionDAG::getCondCode(ISD::CondCode Cond) { 1127 if ((unsigned)Cond >= CondCodeNodes.size()) 1128 CondCodeNodes.resize(Cond+1); 1129 1130 if (CondCodeNodes[Cond] == 0) { 1131 CondCodeSDNode *N = NodeAllocator.Allocate<CondCodeSDNode>(); 1132 new (N) CondCodeSDNode(Cond); 1133 CondCodeNodes[Cond] = N; 1134 AllNodes.push_back(N); 1135 } 1136 return SDValue(CondCodeNodes[Cond], 0); 1137} 1138 1139SDValue SelectionDAG::getRegister(unsigned RegNo, MVT VT) { 1140 FoldingSetNodeID ID; 1141 AddNodeIDNode(ID, ISD::Register, getVTList(VT), 0, 0); 1142 ID.AddInteger(RegNo); 1143 void *IP = 0; 1144 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1145 return SDValue(E, 0); 1146 SDNode *N = NodeAllocator.Allocate<RegisterSDNode>(); 1147 new (N) RegisterSDNode(RegNo, VT); 1148 CSEMap.InsertNode(N, IP); 1149 AllNodes.push_back(N); 1150 return SDValue(N, 0); 1151} 1152 1153SDValue SelectionDAG::getDbgStopPoint(SDValue Root, 1154 unsigned Line, unsigned Col, 1155 const CompileUnitDesc *CU) { 1156 SDNode *N = NodeAllocator.Allocate<DbgStopPointSDNode>(); 1157 new (N) DbgStopPointSDNode(Root, Line, Col, CU); 1158 AllNodes.push_back(N); 1159 return SDValue(N, 0); 1160} 1161 1162SDValue SelectionDAG::getLabel(unsigned Opcode, 1163 SDValue Root, 1164 unsigned LabelID) { 1165 FoldingSetNodeID ID; 1166 SDValue Ops[] = { Root }; 1167 AddNodeIDNode(ID, Opcode, getVTList(MVT::Other), &Ops[0], 1); 1168 ID.AddInteger(LabelID); 1169 void *IP = 0; 1170 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1171 return SDValue(E, 0); 1172 SDNode *N = NodeAllocator.Allocate<LabelSDNode>(); 1173 new (N) LabelSDNode(Opcode, Root, LabelID); 1174 CSEMap.InsertNode(N, IP); 1175 AllNodes.push_back(N); 1176 return SDValue(N, 0); 1177} 1178 1179SDValue SelectionDAG::getSrcValue(const Value *V) { 1180 assert((!V || isa<PointerType>(V->getType())) && 1181 "SrcValue is not a pointer?"); 1182 1183 FoldingSetNodeID ID; 1184 AddNodeIDNode(ID, ISD::SRCVALUE, getVTList(MVT::Other), 0, 0); 1185 ID.AddPointer(V); 1186 1187 void *IP = 0; 1188 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1189 return SDValue(E, 0); 1190 1191 SDNode *N = NodeAllocator.Allocate<SrcValueSDNode>(); 1192 new (N) SrcValueSDNode(V); 1193 CSEMap.InsertNode(N, IP); 1194 AllNodes.push_back(N); 1195 return SDValue(N, 0); 1196} 1197 1198SDValue SelectionDAG::getMemOperand(const MachineMemOperand &MO) { 1199 const Value *v = MO.getValue(); 1200 assert((!v || isa<PointerType>(v->getType())) && 1201 "SrcValue is not a pointer?"); 1202 1203 FoldingSetNodeID ID; 1204 AddNodeIDNode(ID, ISD::MEMOPERAND, getVTList(MVT::Other), 0, 0); 1205 MO.Profile(ID); 1206 1207 void *IP = 0; 1208 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1209 return SDValue(E, 0); 1210 1211 SDNode *N = NodeAllocator.Allocate<MemOperandSDNode>(); 1212 new (N) MemOperandSDNode(MO); 1213 CSEMap.InsertNode(N, IP); 1214 AllNodes.push_back(N); 1215 return SDValue(N, 0); 1216} 1217 1218/// CreateStackTemporary - Create a stack temporary, suitable for holding the 1219/// specified value type. 1220SDValue SelectionDAG::CreateStackTemporary(MVT VT, unsigned minAlign) { 1221 MachineFrameInfo *FrameInfo = getMachineFunction().getFrameInfo(); 1222 unsigned ByteSize = VT.getSizeInBits()/8; 1223 const Type *Ty = VT.getTypeForMVT(); 1224 unsigned StackAlign = 1225 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), minAlign); 1226 1227 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, StackAlign); 1228 return getFrameIndex(FrameIdx, TLI.getPointerTy()); 1229} 1230 1231SDValue SelectionDAG::FoldSetCC(MVT VT, SDValue N1, 1232 SDValue N2, ISD::CondCode Cond) { 1233 // These setcc operations always fold. 1234 switch (Cond) { 1235 default: break; 1236 case ISD::SETFALSE: 1237 case ISD::SETFALSE2: return getConstant(0, VT); 1238 case ISD::SETTRUE: 1239 case ISD::SETTRUE2: return getConstant(1, VT); 1240 1241 case ISD::SETOEQ: 1242 case ISD::SETOGT: 1243 case ISD::SETOGE: 1244 case ISD::SETOLT: 1245 case ISD::SETOLE: 1246 case ISD::SETONE: 1247 case ISD::SETO: 1248 case ISD::SETUO: 1249 case ISD::SETUEQ: 1250 case ISD::SETUNE: 1251 assert(!N1.getValueType().isInteger() && "Illegal setcc for integer!"); 1252 break; 1253 } 1254 1255 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode())) { 1256 const APInt &C2 = N2C->getAPIntValue(); 1257 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) { 1258 const APInt &C1 = N1C->getAPIntValue(); 1259 1260 switch (Cond) { 1261 default: assert(0 && "Unknown integer setcc!"); 1262 case ISD::SETEQ: return getConstant(C1 == C2, VT); 1263 case ISD::SETNE: return getConstant(C1 != C2, VT); 1264 case ISD::SETULT: return getConstant(C1.ult(C2), VT); 1265 case ISD::SETUGT: return getConstant(C1.ugt(C2), VT); 1266 case ISD::SETULE: return getConstant(C1.ule(C2), VT); 1267 case ISD::SETUGE: return getConstant(C1.uge(C2), VT); 1268 case ISD::SETLT: return getConstant(C1.slt(C2), VT); 1269 case ISD::SETGT: return getConstant(C1.sgt(C2), VT); 1270 case ISD::SETLE: return getConstant(C1.sle(C2), VT); 1271 case ISD::SETGE: return getConstant(C1.sge(C2), VT); 1272 } 1273 } 1274 } 1275 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.getNode())) { 1276 if (ConstantFPSDNode *N2C = dyn_cast<ConstantFPSDNode>(N2.getNode())) { 1277 // No compile time operations on this type yet. 1278 if (N1C->getValueType(0) == MVT::ppcf128) 1279 return SDValue(); 1280 1281 APFloat::cmpResult R = N1C->getValueAPF().compare(N2C->getValueAPF()); 1282 switch (Cond) { 1283 default: break; 1284 case ISD::SETEQ: if (R==APFloat::cmpUnordered) 1285 return getNode(ISD::UNDEF, VT); 1286 // fall through 1287 case ISD::SETOEQ: return getConstant(R==APFloat::cmpEqual, VT); 1288 case ISD::SETNE: if (R==APFloat::cmpUnordered) 1289 return getNode(ISD::UNDEF, VT); 1290 // fall through 1291 case ISD::SETONE: return getConstant(R==APFloat::cmpGreaterThan || 1292 R==APFloat::cmpLessThan, VT); 1293 case ISD::SETLT: if (R==APFloat::cmpUnordered) 1294 return getNode(ISD::UNDEF, VT); 1295 // fall through 1296 case ISD::SETOLT: return getConstant(R==APFloat::cmpLessThan, VT); 1297 case ISD::SETGT: if (R==APFloat::cmpUnordered) 1298 return getNode(ISD::UNDEF, VT); 1299 // fall through 1300 case ISD::SETOGT: return getConstant(R==APFloat::cmpGreaterThan, VT); 1301 case ISD::SETLE: if (R==APFloat::cmpUnordered) 1302 return getNode(ISD::UNDEF, VT); 1303 // fall through 1304 case ISD::SETOLE: return getConstant(R==APFloat::cmpLessThan || 1305 R==APFloat::cmpEqual, VT); 1306 case ISD::SETGE: if (R==APFloat::cmpUnordered) 1307 return getNode(ISD::UNDEF, VT); 1308 // fall through 1309 case ISD::SETOGE: return getConstant(R==APFloat::cmpGreaterThan || 1310 R==APFloat::cmpEqual, VT); 1311 case ISD::SETO: return getConstant(R!=APFloat::cmpUnordered, VT); 1312 case ISD::SETUO: return getConstant(R==APFloat::cmpUnordered, VT); 1313 case ISD::SETUEQ: return getConstant(R==APFloat::cmpUnordered || 1314 R==APFloat::cmpEqual, VT); 1315 case ISD::SETUNE: return getConstant(R!=APFloat::cmpEqual, VT); 1316 case ISD::SETULT: return getConstant(R==APFloat::cmpUnordered || 1317 R==APFloat::cmpLessThan, VT); 1318 case ISD::SETUGT: return getConstant(R==APFloat::cmpGreaterThan || 1319 R==APFloat::cmpUnordered, VT); 1320 case ISD::SETULE: return getConstant(R!=APFloat::cmpGreaterThan, VT); 1321 case ISD::SETUGE: return getConstant(R!=APFloat::cmpLessThan, VT); 1322 } 1323 } else { 1324 // Ensure that the constant occurs on the RHS. 1325 return getSetCC(VT, N2, N1, ISD::getSetCCSwappedOperands(Cond)); 1326 } 1327 } 1328 1329 // Could not fold it. 1330 return SDValue(); 1331} 1332 1333/// SignBitIsZero - Return true if the sign bit of Op is known to be zero. We 1334/// use this predicate to simplify operations downstream. 1335bool SelectionDAG::SignBitIsZero(SDValue Op, unsigned Depth) const { 1336 unsigned BitWidth = Op.getValueSizeInBits(); 1337 return MaskedValueIsZero(Op, APInt::getSignBit(BitWidth), Depth); 1338} 1339 1340/// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero. We use 1341/// this predicate to simplify operations downstream. Mask is known to be zero 1342/// for bits that V cannot have. 1343bool SelectionDAG::MaskedValueIsZero(SDValue Op, const APInt &Mask, 1344 unsigned Depth) const { 1345 APInt KnownZero, KnownOne; 1346 ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth); 1347 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1348 return (KnownZero & Mask) == Mask; 1349} 1350 1351/// ComputeMaskedBits - Determine which of the bits specified in Mask are 1352/// known to be either zero or one and return them in the KnownZero/KnownOne 1353/// bitsets. This code only analyzes bits in Mask, in order to short-circuit 1354/// processing. 1355void SelectionDAG::ComputeMaskedBits(SDValue Op, const APInt &Mask, 1356 APInt &KnownZero, APInt &KnownOne, 1357 unsigned Depth) const { 1358 unsigned BitWidth = Mask.getBitWidth(); 1359 assert(BitWidth == Op.getValueType().getSizeInBits() && 1360 "Mask size mismatches value type size!"); 1361 1362 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything. 1363 if (Depth == 6 || Mask == 0) 1364 return; // Limit search depth. 1365 1366 APInt KnownZero2, KnownOne2; 1367 1368 switch (Op.getOpcode()) { 1369 case ISD::Constant: 1370 // We know all of the bits for a constant! 1371 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & Mask; 1372 KnownZero = ~KnownOne & Mask; 1373 return; 1374 case ISD::AND: 1375 // If either the LHS or the RHS are Zero, the result is zero. 1376 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1377 ComputeMaskedBits(Op.getOperand(0), Mask & ~KnownZero, 1378 KnownZero2, KnownOne2, Depth+1); 1379 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1380 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1381 1382 // Output known-1 bits are only known if set in both the LHS & RHS. 1383 KnownOne &= KnownOne2; 1384 // Output known-0 are known to be clear if zero in either the LHS | RHS. 1385 KnownZero |= KnownZero2; 1386 return; 1387 case ISD::OR: 1388 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1389 ComputeMaskedBits(Op.getOperand(0), Mask & ~KnownOne, 1390 KnownZero2, KnownOne2, Depth+1); 1391 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1392 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1393 1394 // Output known-0 bits are only known if clear in both the LHS & RHS. 1395 KnownZero &= KnownZero2; 1396 // Output known-1 are known to be set if set in either the LHS | RHS. 1397 KnownOne |= KnownOne2; 1398 return; 1399 case ISD::XOR: { 1400 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1401 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1); 1402 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1403 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1404 1405 // Output known-0 bits are known if clear or set in both the LHS & RHS. 1406 APInt KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 1407 // Output known-1 are known to be set if set in only one of the LHS, RHS. 1408 KnownOne = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 1409 KnownZero = KnownZeroOut; 1410 return; 1411 } 1412 case ISD::MUL: { 1413 APInt Mask2 = APInt::getAllOnesValue(BitWidth); 1414 ComputeMaskedBits(Op.getOperand(1), Mask2, KnownZero, KnownOne, Depth+1); 1415 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero2, KnownOne2, Depth+1); 1416 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1417 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1418 1419 // If low bits are zero in either operand, output low known-0 bits. 1420 // Also compute a conserative estimate for high known-0 bits. 1421 // More trickiness is possible, but this is sufficient for the 1422 // interesting case of alignment computation. 1423 KnownOne.clear(); 1424 unsigned TrailZ = KnownZero.countTrailingOnes() + 1425 KnownZero2.countTrailingOnes(); 1426 unsigned LeadZ = std::max(KnownZero.countLeadingOnes() + 1427 KnownZero2.countLeadingOnes(), 1428 BitWidth) - BitWidth; 1429 1430 TrailZ = std::min(TrailZ, BitWidth); 1431 LeadZ = std::min(LeadZ, BitWidth); 1432 KnownZero = APInt::getLowBitsSet(BitWidth, TrailZ) | 1433 APInt::getHighBitsSet(BitWidth, LeadZ); 1434 KnownZero &= Mask; 1435 return; 1436 } 1437 case ISD::UDIV: { 1438 // For the purposes of computing leading zeros we can conservatively 1439 // treat a udiv as a logical right shift by the power of 2 known to 1440 // be less than the denominator. 1441 APInt AllOnes = APInt::getAllOnesValue(BitWidth); 1442 ComputeMaskedBits(Op.getOperand(0), 1443 AllOnes, KnownZero2, KnownOne2, Depth+1); 1444 unsigned LeadZ = KnownZero2.countLeadingOnes(); 1445 1446 KnownOne2.clear(); 1447 KnownZero2.clear(); 1448 ComputeMaskedBits(Op.getOperand(1), 1449 AllOnes, KnownZero2, KnownOne2, Depth+1); 1450 unsigned RHSUnknownLeadingOnes = KnownOne2.countLeadingZeros(); 1451 if (RHSUnknownLeadingOnes != BitWidth) 1452 LeadZ = std::min(BitWidth, 1453 LeadZ + BitWidth - RHSUnknownLeadingOnes - 1); 1454 1455 KnownZero = APInt::getHighBitsSet(BitWidth, LeadZ) & Mask; 1456 return; 1457 } 1458 case ISD::SELECT: 1459 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero, KnownOne, Depth+1); 1460 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero2, KnownOne2, Depth+1); 1461 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1462 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1463 1464 // Only known if known in both the LHS and RHS. 1465 KnownOne &= KnownOne2; 1466 KnownZero &= KnownZero2; 1467 return; 1468 case ISD::SELECT_CC: 1469 ComputeMaskedBits(Op.getOperand(3), Mask, KnownZero, KnownOne, Depth+1); 1470 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero2, KnownOne2, Depth+1); 1471 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1472 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1473 1474 // Only known if known in both the LHS and RHS. 1475 KnownOne &= KnownOne2; 1476 KnownZero &= KnownZero2; 1477 return; 1478 case ISD::SETCC: 1479 // If we know the result of a setcc has the top bits zero, use this info. 1480 if (TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult && 1481 BitWidth > 1) 1482 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1); 1483 return; 1484 case ISD::SHL: 1485 // (shl X, C1) & C2 == 0 iff (X & C2 >>u C1) == 0 1486 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1487 unsigned ShAmt = SA->getZExtValue(); 1488 1489 // If the shift count is an invalid immediate, don't do anything. 1490 if (ShAmt >= BitWidth) 1491 return; 1492 1493 ComputeMaskedBits(Op.getOperand(0), Mask.lshr(ShAmt), 1494 KnownZero, KnownOne, Depth+1); 1495 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1496 KnownZero <<= ShAmt; 1497 KnownOne <<= ShAmt; 1498 // low bits known zero. 1499 KnownZero |= APInt::getLowBitsSet(BitWidth, ShAmt); 1500 } 1501 return; 1502 case ISD::SRL: 1503 // (ushr X, C1) & C2 == 0 iff (-1 >> C1) & C2 == 0 1504 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1505 unsigned ShAmt = SA->getZExtValue(); 1506 1507 // If the shift count is an invalid immediate, don't do anything. 1508 if (ShAmt >= BitWidth) 1509 return; 1510 1511 ComputeMaskedBits(Op.getOperand(0), (Mask << ShAmt), 1512 KnownZero, KnownOne, Depth+1); 1513 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1514 KnownZero = KnownZero.lshr(ShAmt); 1515 KnownOne = KnownOne.lshr(ShAmt); 1516 1517 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt) & Mask; 1518 KnownZero |= HighBits; // High bits known zero. 1519 } 1520 return; 1521 case ISD::SRA: 1522 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1523 unsigned ShAmt = SA->getZExtValue(); 1524 1525 // If the shift count is an invalid immediate, don't do anything. 1526 if (ShAmt >= BitWidth) 1527 return; 1528 1529 APInt InDemandedMask = (Mask << ShAmt); 1530 // If any of the demanded bits are produced by the sign extension, we also 1531 // demand the input sign bit. 1532 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt) & Mask; 1533 if (HighBits.getBoolValue()) 1534 InDemandedMask |= APInt::getSignBit(BitWidth); 1535 1536 ComputeMaskedBits(Op.getOperand(0), InDemandedMask, KnownZero, KnownOne, 1537 Depth+1); 1538 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1539 KnownZero = KnownZero.lshr(ShAmt); 1540 KnownOne = KnownOne.lshr(ShAmt); 1541 1542 // Handle the sign bits. 1543 APInt SignBit = APInt::getSignBit(BitWidth); 1544 SignBit = SignBit.lshr(ShAmt); // Adjust to where it is now in the mask. 1545 1546 if (KnownZero.intersects(SignBit)) { 1547 KnownZero |= HighBits; // New bits are known zero. 1548 } else if (KnownOne.intersects(SignBit)) { 1549 KnownOne |= HighBits; // New bits are known one. 1550 } 1551 } 1552 return; 1553 case ISD::SIGN_EXTEND_INREG: { 1554 MVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1555 unsigned EBits = EVT.getSizeInBits(); 1556 1557 // Sign extension. Compute the demanded bits in the result that are not 1558 // present in the input. 1559 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - EBits) & Mask; 1560 1561 APInt InSignBit = APInt::getSignBit(EBits); 1562 APInt InputDemandedBits = Mask & APInt::getLowBitsSet(BitWidth, EBits); 1563 1564 // If the sign extended bits are demanded, we know that the sign 1565 // bit is demanded. 1566 InSignBit.zext(BitWidth); 1567 if (NewBits.getBoolValue()) 1568 InputDemandedBits |= InSignBit; 1569 1570 ComputeMaskedBits(Op.getOperand(0), InputDemandedBits, 1571 KnownZero, KnownOne, Depth+1); 1572 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1573 1574 // If the sign bit of the input is known set or clear, then we know the 1575 // top bits of the result. 1576 if (KnownZero.intersects(InSignBit)) { // Input sign bit known clear 1577 KnownZero |= NewBits; 1578 KnownOne &= ~NewBits; 1579 } else if (KnownOne.intersects(InSignBit)) { // Input sign bit known set 1580 KnownOne |= NewBits; 1581 KnownZero &= ~NewBits; 1582 } else { // Input sign bit unknown 1583 KnownZero &= ~NewBits; 1584 KnownOne &= ~NewBits; 1585 } 1586 return; 1587 } 1588 case ISD::CTTZ: 1589 case ISD::CTLZ: 1590 case ISD::CTPOP: { 1591 unsigned LowBits = Log2_32(BitWidth)+1; 1592 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - LowBits); 1593 KnownOne.clear(); 1594 return; 1595 } 1596 case ISD::LOAD: { 1597 if (ISD::isZEXTLoad(Op.getNode())) { 1598 LoadSDNode *LD = cast<LoadSDNode>(Op); 1599 MVT VT = LD->getMemoryVT(); 1600 unsigned MemBits = VT.getSizeInBits(); 1601 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits) & Mask; 1602 } 1603 return; 1604 } 1605 case ISD::ZERO_EXTEND: { 1606 MVT InVT = Op.getOperand(0).getValueType(); 1607 unsigned InBits = InVT.getSizeInBits(); 1608 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - InBits) & Mask; 1609 APInt InMask = Mask; 1610 InMask.trunc(InBits); 1611 KnownZero.trunc(InBits); 1612 KnownOne.trunc(InBits); 1613 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1614 KnownZero.zext(BitWidth); 1615 KnownOne.zext(BitWidth); 1616 KnownZero |= NewBits; 1617 return; 1618 } 1619 case ISD::SIGN_EXTEND: { 1620 MVT InVT = Op.getOperand(0).getValueType(); 1621 unsigned InBits = InVT.getSizeInBits(); 1622 APInt InSignBit = APInt::getSignBit(InBits); 1623 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - InBits) & Mask; 1624 APInt InMask = Mask; 1625 InMask.trunc(InBits); 1626 1627 // If any of the sign extended bits are demanded, we know that the sign 1628 // bit is demanded. Temporarily set this bit in the mask for our callee. 1629 if (NewBits.getBoolValue()) 1630 InMask |= InSignBit; 1631 1632 KnownZero.trunc(InBits); 1633 KnownOne.trunc(InBits); 1634 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1635 1636 // Note if the sign bit is known to be zero or one. 1637 bool SignBitKnownZero = KnownZero.isNegative(); 1638 bool SignBitKnownOne = KnownOne.isNegative(); 1639 assert(!(SignBitKnownZero && SignBitKnownOne) && 1640 "Sign bit can't be known to be both zero and one!"); 1641 1642 // If the sign bit wasn't actually demanded by our caller, we don't 1643 // want it set in the KnownZero and KnownOne result values. Reset the 1644 // mask and reapply it to the result values. 1645 InMask = Mask; 1646 InMask.trunc(InBits); 1647 KnownZero &= InMask; 1648 KnownOne &= InMask; 1649 1650 KnownZero.zext(BitWidth); 1651 KnownOne.zext(BitWidth); 1652 1653 // If the sign bit is known zero or one, the top bits match. 1654 if (SignBitKnownZero) 1655 KnownZero |= NewBits; 1656 else if (SignBitKnownOne) 1657 KnownOne |= NewBits; 1658 return; 1659 } 1660 case ISD::ANY_EXTEND: { 1661 MVT InVT = Op.getOperand(0).getValueType(); 1662 unsigned InBits = InVT.getSizeInBits(); 1663 APInt InMask = Mask; 1664 InMask.trunc(InBits); 1665 KnownZero.trunc(InBits); 1666 KnownOne.trunc(InBits); 1667 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1668 KnownZero.zext(BitWidth); 1669 KnownOne.zext(BitWidth); 1670 return; 1671 } 1672 case ISD::TRUNCATE: { 1673 MVT InVT = Op.getOperand(0).getValueType(); 1674 unsigned InBits = InVT.getSizeInBits(); 1675 APInt InMask = Mask; 1676 InMask.zext(InBits); 1677 KnownZero.zext(InBits); 1678 KnownOne.zext(InBits); 1679 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1680 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1681 KnownZero.trunc(BitWidth); 1682 KnownOne.trunc(BitWidth); 1683 break; 1684 } 1685 case ISD::AssertZext: { 1686 MVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1687 APInt InMask = APInt::getLowBitsSet(BitWidth, VT.getSizeInBits()); 1688 ComputeMaskedBits(Op.getOperand(0), Mask & InMask, KnownZero, 1689 KnownOne, Depth+1); 1690 KnownZero |= (~InMask) & Mask; 1691 return; 1692 } 1693 case ISD::FGETSIGN: 1694 // All bits are zero except the low bit. 1695 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - 1); 1696 return; 1697 1698 case ISD::SUB: { 1699 if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) { 1700 // We know that the top bits of C-X are clear if X contains less bits 1701 // than C (i.e. no wrap-around can happen). For example, 20-X is 1702 // positive if we can prove that X is >= 0 and < 16. 1703 if (CLHS->getAPIntValue().isNonNegative()) { 1704 unsigned NLZ = (CLHS->getAPIntValue()+1).countLeadingZeros(); 1705 // NLZ can't be BitWidth with no sign bit 1706 APInt MaskV = APInt::getHighBitsSet(BitWidth, NLZ+1); 1707 ComputeMaskedBits(Op.getOperand(1), MaskV, KnownZero2, KnownOne2, 1708 Depth+1); 1709 1710 // If all of the MaskV bits are known to be zero, then we know the 1711 // output top bits are zero, because we now know that the output is 1712 // from [0-C]. 1713 if ((KnownZero2 & MaskV) == MaskV) { 1714 unsigned NLZ2 = CLHS->getAPIntValue().countLeadingZeros(); 1715 // Top bits known zero. 1716 KnownZero = APInt::getHighBitsSet(BitWidth, NLZ2) & Mask; 1717 } 1718 } 1719 } 1720 } 1721 // fall through 1722 case ISD::ADD: { 1723 // Output known-0 bits are known if clear or set in both the low clear bits 1724 // common to both LHS & RHS. For example, 8+(X<<3) is known to have the 1725 // low 3 bits clear. 1726 APInt Mask2 = APInt::getLowBitsSet(BitWidth, Mask.countTrailingOnes()); 1727 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero2, KnownOne2, Depth+1); 1728 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1729 unsigned KnownZeroOut = KnownZero2.countTrailingOnes(); 1730 1731 ComputeMaskedBits(Op.getOperand(1), Mask2, KnownZero2, KnownOne2, Depth+1); 1732 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1733 KnownZeroOut = std::min(KnownZeroOut, 1734 KnownZero2.countTrailingOnes()); 1735 1736 KnownZero |= APInt::getLowBitsSet(BitWidth, KnownZeroOut); 1737 return; 1738 } 1739 case ISD::SREM: 1740 if (ConstantSDNode *Rem = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1741 const APInt &RA = Rem->getAPIntValue(); 1742 if (RA.isPowerOf2() || (-RA).isPowerOf2()) { 1743 APInt LowBits = RA.isStrictlyPositive() ? (RA - 1) : ~RA; 1744 APInt Mask2 = LowBits | APInt::getSignBit(BitWidth); 1745 ComputeMaskedBits(Op.getOperand(0), Mask2,KnownZero2,KnownOne2,Depth+1); 1746 1747 // If the sign bit of the first operand is zero, the sign bit of 1748 // the result is zero. If the first operand has no one bits below 1749 // the second operand's single 1 bit, its sign will be zero. 1750 if (KnownZero2[BitWidth-1] || ((KnownZero2 & LowBits) == LowBits)) 1751 KnownZero2 |= ~LowBits; 1752 1753 KnownZero |= KnownZero2 & Mask; 1754 1755 assert((KnownZero & KnownOne) == 0&&"Bits known to be one AND zero?"); 1756 } 1757 } 1758 return; 1759 case ISD::UREM: { 1760 if (ConstantSDNode *Rem = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1761 const APInt &RA = Rem->getAPIntValue(); 1762 if (RA.isPowerOf2()) { 1763 APInt LowBits = (RA - 1); 1764 APInt Mask2 = LowBits & Mask; 1765 KnownZero |= ~LowBits & Mask; 1766 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero, KnownOne,Depth+1); 1767 assert((KnownZero & KnownOne) == 0&&"Bits known to be one AND zero?"); 1768 break; 1769 } 1770 } 1771 1772 // Since the result is less than or equal to either operand, any leading 1773 // zero bits in either operand must also exist in the result. 1774 APInt AllOnes = APInt::getAllOnesValue(BitWidth); 1775 ComputeMaskedBits(Op.getOperand(0), AllOnes, KnownZero, KnownOne, 1776 Depth+1); 1777 ComputeMaskedBits(Op.getOperand(1), AllOnes, KnownZero2, KnownOne2, 1778 Depth+1); 1779 1780 uint32_t Leaders = std::max(KnownZero.countLeadingOnes(), 1781 KnownZero2.countLeadingOnes()); 1782 KnownOne.clear(); 1783 KnownZero = APInt::getHighBitsSet(BitWidth, Leaders) & Mask; 1784 return; 1785 } 1786 default: 1787 // Allow the target to implement this method for its nodes. 1788 if (Op.getOpcode() >= ISD::BUILTIN_OP_END) { 1789 case ISD::INTRINSIC_WO_CHAIN: 1790 case ISD::INTRINSIC_W_CHAIN: 1791 case ISD::INTRINSIC_VOID: 1792 TLI.computeMaskedBitsForTargetNode(Op, Mask, KnownZero, KnownOne, *this); 1793 } 1794 return; 1795 } 1796} 1797 1798/// ComputeNumSignBits - Return the number of times the sign bit of the 1799/// register is replicated into the other bits. We know that at least 1 bit 1800/// is always equal to the sign bit (itself), but other cases can give us 1801/// information. For example, immediately after an "SRA X, 2", we know that 1802/// the top 3 bits are all equal to each other, so we return 3. 1803unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, unsigned Depth) const{ 1804 MVT VT = Op.getValueType(); 1805 assert(VT.isInteger() && "Invalid VT!"); 1806 unsigned VTBits = VT.getSizeInBits(); 1807 unsigned Tmp, Tmp2; 1808 unsigned FirstAnswer = 1; 1809 1810 if (Depth == 6) 1811 return 1; // Limit search depth. 1812 1813 switch (Op.getOpcode()) { 1814 default: break; 1815 case ISD::AssertSext: 1816 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); 1817 return VTBits-Tmp+1; 1818 case ISD::AssertZext: 1819 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); 1820 return VTBits-Tmp; 1821 1822 case ISD::Constant: { 1823 const APInt &Val = cast<ConstantSDNode>(Op)->getAPIntValue(); 1824 // If negative, return # leading ones. 1825 if (Val.isNegative()) 1826 return Val.countLeadingOnes(); 1827 1828 // Return # leading zeros. 1829 return Val.countLeadingZeros(); 1830 } 1831 1832 case ISD::SIGN_EXTEND: 1833 Tmp = VTBits-Op.getOperand(0).getValueType().getSizeInBits(); 1834 return ComputeNumSignBits(Op.getOperand(0), Depth+1) + Tmp; 1835 1836 case ISD::SIGN_EXTEND_INREG: 1837 // Max of the input and what this extends. 1838 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); 1839 Tmp = VTBits-Tmp+1; 1840 1841 Tmp2 = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1842 return std::max(Tmp, Tmp2); 1843 1844 case ISD::SRA: 1845 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1846 // SRA X, C -> adds C sign bits. 1847 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1848 Tmp += C->getZExtValue(); 1849 if (Tmp > VTBits) Tmp = VTBits; 1850 } 1851 return Tmp; 1852 case ISD::SHL: 1853 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1854 // shl destroys sign bits. 1855 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1856 if (C->getZExtValue() >= VTBits || // Bad shift. 1857 C->getZExtValue() >= Tmp) break; // Shifted all sign bits out. 1858 return Tmp - C->getZExtValue(); 1859 } 1860 break; 1861 case ISD::AND: 1862 case ISD::OR: 1863 case ISD::XOR: // NOT is handled here. 1864 // Logical binary ops preserve the number of sign bits at the worst. 1865 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1866 if (Tmp != 1) { 1867 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 1868 FirstAnswer = std::min(Tmp, Tmp2); 1869 // We computed what we know about the sign bits as our first 1870 // answer. Now proceed to the generic code that uses 1871 // ComputeMaskedBits, and pick whichever answer is better. 1872 } 1873 break; 1874 1875 case ISD::SELECT: 1876 Tmp = ComputeNumSignBits(Op.getOperand(1), Depth+1); 1877 if (Tmp == 1) return 1; // Early out. 1878 Tmp2 = ComputeNumSignBits(Op.getOperand(2), Depth+1); 1879 return std::min(Tmp, Tmp2); 1880 1881 case ISD::SETCC: 1882 // If setcc returns 0/-1, all bits are sign bits. 1883 if (TLI.getSetCCResultContents() == 1884 TargetLowering::ZeroOrNegativeOneSetCCResult) 1885 return VTBits; 1886 break; 1887 case ISD::ROTL: 1888 case ISD::ROTR: 1889 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1890 unsigned RotAmt = C->getZExtValue() & (VTBits-1); 1891 1892 // Handle rotate right by N like a rotate left by 32-N. 1893 if (Op.getOpcode() == ISD::ROTR) 1894 RotAmt = (VTBits-RotAmt) & (VTBits-1); 1895 1896 // If we aren't rotating out all of the known-in sign bits, return the 1897 // number that are left. This handles rotl(sext(x), 1) for example. 1898 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1899 if (Tmp > RotAmt+1) return Tmp-RotAmt; 1900 } 1901 break; 1902 case ISD::ADD: 1903 // Add can have at most one carry bit. Thus we know that the output 1904 // is, at worst, one more bit than the inputs. 1905 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1906 if (Tmp == 1) return 1; // Early out. 1907 1908 // Special case decrementing a value (ADD X, -1): 1909 if (ConstantSDNode *CRHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) 1910 if (CRHS->isAllOnesValue()) { 1911 APInt KnownZero, KnownOne; 1912 APInt Mask = APInt::getAllOnesValue(VTBits); 1913 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1); 1914 1915 // If the input is known to be 0 or 1, the output is 0/-1, which is all 1916 // sign bits set. 1917 if ((KnownZero | APInt(VTBits, 1)) == Mask) 1918 return VTBits; 1919 1920 // If we are subtracting one from a positive number, there is no carry 1921 // out of the result. 1922 if (KnownZero.isNegative()) 1923 return Tmp; 1924 } 1925 1926 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 1927 if (Tmp2 == 1) return 1; 1928 return std::min(Tmp, Tmp2)-1; 1929 break; 1930 1931 case ISD::SUB: 1932 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 1933 if (Tmp2 == 1) return 1; 1934 1935 // Handle NEG. 1936 if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) 1937 if (CLHS->isNullValue()) { 1938 APInt KnownZero, KnownOne; 1939 APInt Mask = APInt::getAllOnesValue(VTBits); 1940 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1941 // If the input is known to be 0 or 1, the output is 0/-1, which is all 1942 // sign bits set. 1943 if ((KnownZero | APInt(VTBits, 1)) == Mask) 1944 return VTBits; 1945 1946 // If the input is known to be positive (the sign bit is known clear), 1947 // the output of the NEG has the same number of sign bits as the input. 1948 if (KnownZero.isNegative()) 1949 return Tmp2; 1950 1951 // Otherwise, we treat this like a SUB. 1952 } 1953 1954 // Sub can have at most one carry bit. Thus we know that the output 1955 // is, at worst, one more bit than the inputs. 1956 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1957 if (Tmp == 1) return 1; // Early out. 1958 return std::min(Tmp, Tmp2)-1; 1959 break; 1960 case ISD::TRUNCATE: 1961 // FIXME: it's tricky to do anything useful for this, but it is an important 1962 // case for targets like X86. 1963 break; 1964 } 1965 1966 // Handle LOADX separately here. EXTLOAD case will fallthrough. 1967 if (Op.getOpcode() == ISD::LOAD) { 1968 LoadSDNode *LD = cast<LoadSDNode>(Op); 1969 unsigned ExtType = LD->getExtensionType(); 1970 switch (ExtType) { 1971 default: break; 1972 case ISD::SEXTLOAD: // '17' bits known 1973 Tmp = LD->getMemoryVT().getSizeInBits(); 1974 return VTBits-Tmp+1; 1975 case ISD::ZEXTLOAD: // '16' bits known 1976 Tmp = LD->getMemoryVT().getSizeInBits(); 1977 return VTBits-Tmp; 1978 } 1979 } 1980 1981 // Allow the target to implement this method for its nodes. 1982 if (Op.getOpcode() >= ISD::BUILTIN_OP_END || 1983 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1984 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1985 Op.getOpcode() == ISD::INTRINSIC_VOID) { 1986 unsigned NumBits = TLI.ComputeNumSignBitsForTargetNode(Op, Depth); 1987 if (NumBits > 1) FirstAnswer = std::max(FirstAnswer, NumBits); 1988 } 1989 1990 // Finally, if we can prove that the top bits of the result are 0's or 1's, 1991 // use this information. 1992 APInt KnownZero, KnownOne; 1993 APInt Mask = APInt::getAllOnesValue(VTBits); 1994 ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth); 1995 1996 if (KnownZero.isNegative()) { // sign bit is 0 1997 Mask = KnownZero; 1998 } else if (KnownOne.isNegative()) { // sign bit is 1; 1999 Mask = KnownOne; 2000 } else { 2001 // Nothing known. 2002 return FirstAnswer; 2003 } 2004 2005 // Okay, we know that the sign bit in Mask is set. Use CLZ to determine 2006 // the number of identical bits in the top of the input value. 2007 Mask = ~Mask; 2008 Mask <<= Mask.getBitWidth()-VTBits; 2009 // Return # leading zeros. We use 'min' here in case Val was zero before 2010 // shifting. We don't want to return '64' as for an i32 "0". 2011 return std::max(FirstAnswer, std::min(VTBits, Mask.countLeadingZeros())); 2012} 2013 2014 2015bool SelectionDAG::isVerifiedDebugInfoDesc(SDValue Op) const { 2016 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op); 2017 if (!GA) return false; 2018 GlobalVariable *GV = dyn_cast<GlobalVariable>(GA->getGlobal()); 2019 if (!GV) return false; 2020 MachineModuleInfo *MMI = getMachineModuleInfo(); 2021 return MMI && MMI->hasDebugInfo() && MMI->isVerified(GV); 2022} 2023 2024 2025/// getShuffleScalarElt - Returns the scalar element that will make up the ith 2026/// element of the result of the vector shuffle. 2027SDValue SelectionDAG::getShuffleScalarElt(const SDNode *N, unsigned i) { 2028 MVT VT = N->getValueType(0); 2029 SDValue PermMask = N->getOperand(2); 2030 SDValue Idx = PermMask.getOperand(i); 2031 if (Idx.getOpcode() == ISD::UNDEF) 2032 return getNode(ISD::UNDEF, VT.getVectorElementType()); 2033 unsigned Index = cast<ConstantSDNode>(Idx)->getZExtValue(); 2034 unsigned NumElems = PermMask.getNumOperands(); 2035 SDValue V = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1); 2036 Index %= NumElems; 2037 2038 if (V.getOpcode() == ISD::BIT_CONVERT) { 2039 V = V.getOperand(0); 2040 if (V.getValueType().getVectorNumElements() != NumElems) 2041 return SDValue(); 2042 } 2043 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) 2044 return (Index == 0) ? V.getOperand(0) 2045 : getNode(ISD::UNDEF, VT.getVectorElementType()); 2046 if (V.getOpcode() == ISD::BUILD_VECTOR) 2047 return V.getOperand(Index); 2048 if (V.getOpcode() == ISD::VECTOR_SHUFFLE) 2049 return getShuffleScalarElt(V.getNode(), Index); 2050 return SDValue(); 2051} 2052 2053 2054/// getNode - Gets or creates the specified node. 2055/// 2056SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT) { 2057 FoldingSetNodeID ID; 2058 AddNodeIDNode(ID, Opcode, getVTList(VT), 0, 0); 2059 void *IP = 0; 2060 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2061 return SDValue(E, 0); 2062 SDNode *N = NodeAllocator.Allocate<SDNode>(); 2063 new (N) SDNode(Opcode, SDNode::getSDVTList(VT)); 2064 CSEMap.InsertNode(N, IP); 2065 2066 AllNodes.push_back(N); 2067#ifndef NDEBUG 2068 VerifyNode(N); 2069#endif 2070 return SDValue(N, 0); 2071} 2072 2073SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, SDValue Operand) { 2074 // Constant fold unary operations with an integer constant operand. 2075 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Operand.getNode())) { 2076 const APInt &Val = C->getAPIntValue(); 2077 unsigned BitWidth = VT.getSizeInBits(); 2078 switch (Opcode) { 2079 default: break; 2080 case ISD::SIGN_EXTEND: 2081 return getConstant(APInt(Val).sextOrTrunc(BitWidth), VT); 2082 case ISD::ANY_EXTEND: 2083 case ISD::ZERO_EXTEND: 2084 case ISD::TRUNCATE: 2085 return getConstant(APInt(Val).zextOrTrunc(BitWidth), VT); 2086 case ISD::UINT_TO_FP: 2087 case ISD::SINT_TO_FP: { 2088 const uint64_t zero[] = {0, 0}; 2089 // No compile time operations on this type. 2090 if (VT==MVT::ppcf128) 2091 break; 2092 APFloat apf = APFloat(APInt(BitWidth, 2, zero)); 2093 (void)apf.convertFromAPInt(Val, 2094 Opcode==ISD::SINT_TO_FP, 2095 APFloat::rmNearestTiesToEven); 2096 return getConstantFP(apf, VT); 2097 } 2098 case ISD::BIT_CONVERT: 2099 if (VT == MVT::f32 && C->getValueType(0) == MVT::i32) 2100 return getConstantFP(Val.bitsToFloat(), VT); 2101 else if (VT == MVT::f64 && C->getValueType(0) == MVT::i64) 2102 return getConstantFP(Val.bitsToDouble(), VT); 2103 break; 2104 case ISD::BSWAP: 2105 return getConstant(Val.byteSwap(), VT); 2106 case ISD::CTPOP: 2107 return getConstant(Val.countPopulation(), VT); 2108 case ISD::CTLZ: 2109 return getConstant(Val.countLeadingZeros(), VT); 2110 case ISD::CTTZ: 2111 return getConstant(Val.countTrailingZeros(), VT); 2112 } 2113 } 2114 2115 // Constant fold unary operations with a floating point constant operand. 2116 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Operand.getNode())) { 2117 APFloat V = C->getValueAPF(); // make copy 2118 if (VT != MVT::ppcf128 && Operand.getValueType() != MVT::ppcf128) { 2119 switch (Opcode) { 2120 case ISD::FNEG: 2121 V.changeSign(); 2122 return getConstantFP(V, VT); 2123 case ISD::FABS: 2124 V.clearSign(); 2125 return getConstantFP(V, VT); 2126 case ISD::FP_ROUND: 2127 case ISD::FP_EXTEND: 2128 // This can return overflow, underflow, or inexact; we don't care. 2129 // FIXME need to be more flexible about rounding mode. 2130 (void)V.convert(*MVTToAPFloatSemantics(VT), 2131 APFloat::rmNearestTiesToEven); 2132 return getConstantFP(V, VT); 2133 case ISD::FP_TO_SINT: 2134 case ISD::FP_TO_UINT: { 2135 integerPart x; 2136 assert(integerPartWidth >= 64); 2137 // FIXME need to be more flexible about rounding mode. 2138 APFloat::opStatus s = V.convertToInteger(&x, 64U, 2139 Opcode==ISD::FP_TO_SINT, 2140 APFloat::rmTowardZero); 2141 if (s==APFloat::opInvalidOp) // inexact is OK, in fact usual 2142 break; 2143 return getConstant(x, VT); 2144 } 2145 case ISD::BIT_CONVERT: 2146 if (VT == MVT::i32 && C->getValueType(0) == MVT::f32) 2147 return getConstant((uint32_t)V.convertToAPInt().getZExtValue(), VT); 2148 else if (VT == MVT::i64 && C->getValueType(0) == MVT::f64) 2149 return getConstant(V.convertToAPInt().getZExtValue(), VT); 2150 break; 2151 } 2152 } 2153 } 2154 2155 unsigned OpOpcode = Operand.getNode()->getOpcode(); 2156 switch (Opcode) { 2157 case ISD::TokenFactor: 2158 case ISD::CONCAT_VECTORS: 2159 return Operand; // Factor or concat of one node? No need. 2160 case ISD::FP_ROUND: assert(0 && "Invalid method to make FP_ROUND node"); 2161 case ISD::FP_EXTEND: 2162 assert(VT.isFloatingPoint() && 2163 Operand.getValueType().isFloatingPoint() && "Invalid FP cast!"); 2164 if (Operand.getValueType() == VT) return Operand; // noop conversion. 2165 if (Operand.getOpcode() == ISD::UNDEF) 2166 return getNode(ISD::UNDEF, VT); 2167 break; 2168 case ISD::SIGN_EXTEND: 2169 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2170 "Invalid SIGN_EXTEND!"); 2171 if (Operand.getValueType() == VT) return Operand; // noop extension 2172 assert(Operand.getValueType().bitsLT(VT) 2173 && "Invalid sext node, dst < src!"); 2174 if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND) 2175 return getNode(OpOpcode, VT, Operand.getNode()->getOperand(0)); 2176 break; 2177 case ISD::ZERO_EXTEND: 2178 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2179 "Invalid ZERO_EXTEND!"); 2180 if (Operand.getValueType() == VT) return Operand; // noop extension 2181 assert(Operand.getValueType().bitsLT(VT) 2182 && "Invalid zext node, dst < src!"); 2183 if (OpOpcode == ISD::ZERO_EXTEND) // (zext (zext x)) -> (zext x) 2184 return getNode(ISD::ZERO_EXTEND, VT, Operand.getNode()->getOperand(0)); 2185 break; 2186 case ISD::ANY_EXTEND: 2187 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2188 "Invalid ANY_EXTEND!"); 2189 if (Operand.getValueType() == VT) return Operand; // noop extension 2190 assert(Operand.getValueType().bitsLT(VT) 2191 && "Invalid anyext node, dst < src!"); 2192 if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND) 2193 // (ext (zext x)) -> (zext x) and (ext (sext x)) -> (sext x) 2194 return getNode(OpOpcode, VT, Operand.getNode()->getOperand(0)); 2195 break; 2196 case ISD::TRUNCATE: 2197 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2198 "Invalid TRUNCATE!"); 2199 if (Operand.getValueType() == VT) return Operand; // noop truncate 2200 assert(Operand.getValueType().bitsGT(VT) 2201 && "Invalid truncate node, src < dst!"); 2202 if (OpOpcode == ISD::TRUNCATE) 2203 return getNode(ISD::TRUNCATE, VT, Operand.getNode()->getOperand(0)); 2204 else if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND || 2205 OpOpcode == ISD::ANY_EXTEND) { 2206 // If the source is smaller than the dest, we still need an extend. 2207 if (Operand.getNode()->getOperand(0).getValueType().bitsLT(VT)) 2208 return getNode(OpOpcode, VT, Operand.getNode()->getOperand(0)); 2209 else if (Operand.getNode()->getOperand(0).getValueType().bitsGT(VT)) 2210 return getNode(ISD::TRUNCATE, VT, Operand.getNode()->getOperand(0)); 2211 else 2212 return Operand.getNode()->getOperand(0); 2213 } 2214 break; 2215 case ISD::BIT_CONVERT: 2216 // Basic sanity checking. 2217 assert(VT.getSizeInBits() == Operand.getValueType().getSizeInBits() 2218 && "Cannot BIT_CONVERT between types of different sizes!"); 2219 if (VT == Operand.getValueType()) return Operand; // noop conversion. 2220 if (OpOpcode == ISD::BIT_CONVERT) // bitconv(bitconv(x)) -> bitconv(x) 2221 return getNode(ISD::BIT_CONVERT, VT, Operand.getOperand(0)); 2222 if (OpOpcode == ISD::UNDEF) 2223 return getNode(ISD::UNDEF, VT); 2224 break; 2225 case ISD::SCALAR_TO_VECTOR: 2226 assert(VT.isVector() && !Operand.getValueType().isVector() && 2227 VT.getVectorElementType() == Operand.getValueType() && 2228 "Illegal SCALAR_TO_VECTOR node!"); 2229 if (OpOpcode == ISD::UNDEF) 2230 return getNode(ISD::UNDEF, VT); 2231 // scalar_to_vector(extract_vector_elt V, 0) -> V, top bits are undefined. 2232 if (OpOpcode == ISD::EXTRACT_VECTOR_ELT && 2233 isa<ConstantSDNode>(Operand.getOperand(1)) && 2234 Operand.getConstantOperandVal(1) == 0 && 2235 Operand.getOperand(0).getValueType() == VT) 2236 return Operand.getOperand(0); 2237 break; 2238 case ISD::FNEG: 2239 if (OpOpcode == ISD::FSUB) // -(X-Y) -> (Y-X) 2240 return getNode(ISD::FSUB, VT, Operand.getNode()->getOperand(1), 2241 Operand.getNode()->getOperand(0)); 2242 if (OpOpcode == ISD::FNEG) // --X -> X 2243 return Operand.getNode()->getOperand(0); 2244 break; 2245 case ISD::FABS: 2246 if (OpOpcode == ISD::FNEG) // abs(-X) -> abs(X) 2247 return getNode(ISD::FABS, VT, Operand.getNode()->getOperand(0)); 2248 break; 2249 } 2250 2251 SDNode *N; 2252 SDVTList VTs = getVTList(VT); 2253 if (VT != MVT::Flag) { // Don't CSE flag producing nodes 2254 FoldingSetNodeID ID; 2255 SDValue Ops[1] = { Operand }; 2256 AddNodeIDNode(ID, Opcode, VTs, Ops, 1); 2257 void *IP = 0; 2258 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2259 return SDValue(E, 0); 2260 N = NodeAllocator.Allocate<UnarySDNode>(); 2261 new (N) UnarySDNode(Opcode, VTs, Operand); 2262 CSEMap.InsertNode(N, IP); 2263 } else { 2264 N = NodeAllocator.Allocate<UnarySDNode>(); 2265 new (N) UnarySDNode(Opcode, VTs, Operand); 2266 } 2267 2268 AllNodes.push_back(N); 2269#ifndef NDEBUG 2270 VerifyNode(N); 2271#endif 2272 return SDValue(N, 0); 2273} 2274 2275SDValue SelectionDAG::FoldConstantArithmetic(unsigned Opcode, 2276 MVT VT, 2277 ConstantSDNode *Cst1, 2278 ConstantSDNode *Cst2) { 2279 const APInt &C1 = Cst1->getAPIntValue(), &C2 = Cst2->getAPIntValue(); 2280 2281 switch (Opcode) { 2282 case ISD::ADD: return getConstant(C1 + C2, VT); 2283 case ISD::SUB: return getConstant(C1 - C2, VT); 2284 case ISD::MUL: return getConstant(C1 * C2, VT); 2285 case ISD::UDIV: 2286 if (C2.getBoolValue()) return getConstant(C1.udiv(C2), VT); 2287 break; 2288 case ISD::UREM: 2289 if (C2.getBoolValue()) return getConstant(C1.urem(C2), VT); 2290 break; 2291 case ISD::SDIV: 2292 if (C2.getBoolValue()) return getConstant(C1.sdiv(C2), VT); 2293 break; 2294 case ISD::SREM: 2295 if (C2.getBoolValue()) return getConstant(C1.srem(C2), VT); 2296 break; 2297 case ISD::AND: return getConstant(C1 & C2, VT); 2298 case ISD::OR: return getConstant(C1 | C2, VT); 2299 case ISD::XOR: return getConstant(C1 ^ C2, VT); 2300 case ISD::SHL: return getConstant(C1 << C2, VT); 2301 case ISD::SRL: return getConstant(C1.lshr(C2), VT); 2302 case ISD::SRA: return getConstant(C1.ashr(C2), VT); 2303 case ISD::ROTL: return getConstant(C1.rotl(C2), VT); 2304 case ISD::ROTR: return getConstant(C1.rotr(C2), VT); 2305 default: break; 2306 } 2307 2308 return SDValue(); 2309} 2310 2311SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, 2312 SDValue N1, SDValue N2) { 2313 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 2314 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 2315 switch (Opcode) { 2316 default: break; 2317 case ISD::TokenFactor: 2318 assert(VT == MVT::Other && N1.getValueType() == MVT::Other && 2319 N2.getValueType() == MVT::Other && "Invalid token factor!"); 2320 // Fold trivial token factors. 2321 if (N1.getOpcode() == ISD::EntryToken) return N2; 2322 if (N2.getOpcode() == ISD::EntryToken) return N1; 2323 break; 2324 case ISD::CONCAT_VECTORS: 2325 // A CONCAT_VECTOR with all operands BUILD_VECTOR can be simplified to 2326 // one big BUILD_VECTOR. 2327 if (N1.getOpcode() == ISD::BUILD_VECTOR && 2328 N2.getOpcode() == ISD::BUILD_VECTOR) { 2329 SmallVector<SDValue, 16> Elts(N1.getNode()->op_begin(), N1.getNode()->op_end()); 2330 Elts.insert(Elts.end(), N2.getNode()->op_begin(), N2.getNode()->op_end()); 2331 return getNode(ISD::BUILD_VECTOR, VT, &Elts[0], Elts.size()); 2332 } 2333 break; 2334 case ISD::AND: 2335 assert(VT.isInteger() && N1.getValueType() == N2.getValueType() && 2336 N1.getValueType() == VT && "Binary operator types must match!"); 2337 // (X & 0) -> 0. This commonly occurs when legalizing i64 values, so it's 2338 // worth handling here. 2339 if (N2C && N2C->isNullValue()) 2340 return N2; 2341 if (N2C && N2C->isAllOnesValue()) // X & -1 -> X 2342 return N1; 2343 break; 2344 case ISD::OR: 2345 case ISD::XOR: 2346 case ISD::ADD: 2347 case ISD::SUB: 2348 assert(VT.isInteger() && N1.getValueType() == N2.getValueType() && 2349 N1.getValueType() == VT && "Binary operator types must match!"); 2350 // (X ^|+- 0) -> X. This commonly occurs when legalizing i64 values, so 2351 // it's worth handling here. 2352 if (N2C && N2C->isNullValue()) 2353 return N1; 2354 break; 2355 case ISD::UDIV: 2356 case ISD::UREM: 2357 case ISD::MULHU: 2358 case ISD::MULHS: 2359 assert(VT.isInteger() && "This operator does not apply to FP types!"); 2360 // fall through 2361 case ISD::MUL: 2362 case ISD::SDIV: 2363 case ISD::SREM: 2364 case ISD::FADD: 2365 case ISD::FSUB: 2366 case ISD::FMUL: 2367 case ISD::FDIV: 2368 case ISD::FREM: 2369 assert(N1.getValueType() == N2.getValueType() && 2370 N1.getValueType() == VT && "Binary operator types must match!"); 2371 break; 2372 case ISD::FCOPYSIGN: // N1 and result must match. N1/N2 need not match. 2373 assert(N1.getValueType() == VT && 2374 N1.getValueType().isFloatingPoint() && 2375 N2.getValueType().isFloatingPoint() && 2376 "Invalid FCOPYSIGN!"); 2377 break; 2378 case ISD::SHL: 2379 case ISD::SRA: 2380 case ISD::SRL: 2381 case ISD::ROTL: 2382 case ISD::ROTR: 2383 assert(VT == N1.getValueType() && 2384 "Shift operators return type must be the same as their first arg"); 2385 assert(VT.isInteger() && N2.getValueType().isInteger() && 2386 "Shifts only work on integers"); 2387 2388 // Always fold shifts of i1 values so the code generator doesn't need to 2389 // handle them. Since we know the size of the shift has to be less than the 2390 // size of the value, the shift/rotate count is guaranteed to be zero. 2391 if (VT == MVT::i1) 2392 return N1; 2393 break; 2394 case ISD::FP_ROUND_INREG: { 2395 MVT EVT = cast<VTSDNode>(N2)->getVT(); 2396 assert(VT == N1.getValueType() && "Not an inreg round!"); 2397 assert(VT.isFloatingPoint() && EVT.isFloatingPoint() && 2398 "Cannot FP_ROUND_INREG integer types"); 2399 assert(EVT.bitsLE(VT) && "Not rounding down!"); 2400 if (cast<VTSDNode>(N2)->getVT() == VT) return N1; // Not actually rounding. 2401 break; 2402 } 2403 case ISD::FP_ROUND: 2404 assert(VT.isFloatingPoint() && 2405 N1.getValueType().isFloatingPoint() && 2406 VT.bitsLE(N1.getValueType()) && 2407 isa<ConstantSDNode>(N2) && "Invalid FP_ROUND!"); 2408 if (N1.getValueType() == VT) return N1; // noop conversion. 2409 break; 2410 case ISD::AssertSext: 2411 case ISD::AssertZext: { 2412 MVT EVT = cast<VTSDNode>(N2)->getVT(); 2413 assert(VT == N1.getValueType() && "Not an inreg extend!"); 2414 assert(VT.isInteger() && EVT.isInteger() && 2415 "Cannot *_EXTEND_INREG FP types"); 2416 assert(EVT.bitsLE(VT) && "Not extending!"); 2417 if (VT == EVT) return N1; // noop assertion. 2418 break; 2419 } 2420 case ISD::SIGN_EXTEND_INREG: { 2421 MVT EVT = cast<VTSDNode>(N2)->getVT(); 2422 assert(VT == N1.getValueType() && "Not an inreg extend!"); 2423 assert(VT.isInteger() && EVT.isInteger() && 2424 "Cannot *_EXTEND_INREG FP types"); 2425 assert(EVT.bitsLE(VT) && "Not extending!"); 2426 if (EVT == VT) return N1; // Not actually extending 2427 2428 if (N1C) { 2429 APInt Val = N1C->getAPIntValue(); 2430 unsigned FromBits = cast<VTSDNode>(N2)->getVT().getSizeInBits(); 2431 Val <<= Val.getBitWidth()-FromBits; 2432 Val = Val.ashr(Val.getBitWidth()-FromBits); 2433 return getConstant(Val, VT); 2434 } 2435 break; 2436 } 2437 case ISD::EXTRACT_VECTOR_ELT: 2438 // EXTRACT_VECTOR_ELT of an UNDEF is an UNDEF. 2439 if (N1.getOpcode() == ISD::UNDEF) 2440 return getNode(ISD::UNDEF, VT); 2441 2442 // EXTRACT_VECTOR_ELT of CONCAT_VECTORS is often formed while lowering is 2443 // expanding copies of large vectors from registers. 2444 if (N2C && 2445 N1.getOpcode() == ISD::CONCAT_VECTORS && 2446 N1.getNumOperands() > 0) { 2447 unsigned Factor = 2448 N1.getOperand(0).getValueType().getVectorNumElements(); 2449 return getNode(ISD::EXTRACT_VECTOR_ELT, VT, 2450 N1.getOperand(N2C->getZExtValue() / Factor), 2451 getConstant(N2C->getZExtValue() % Factor, 2452 N2.getValueType())); 2453 } 2454 2455 // EXTRACT_VECTOR_ELT of BUILD_VECTOR is often formed while lowering is 2456 // expanding large vector constants. 2457 if (N2C && N1.getOpcode() == ISD::BUILD_VECTOR) 2458 return N1.getOperand(N2C->getZExtValue()); 2459 2460 // EXTRACT_VECTOR_ELT of INSERT_VECTOR_ELT is often formed when vector 2461 // operations are lowered to scalars. 2462 if (N1.getOpcode() == ISD::INSERT_VECTOR_ELT) { 2463 if (N1.getOperand(2) == N2) 2464 return N1.getOperand(1); 2465 else 2466 return getNode(ISD::EXTRACT_VECTOR_ELT, VT, N1.getOperand(0), N2); 2467 } 2468 break; 2469 case ISD::EXTRACT_ELEMENT: 2470 assert(N2C && (unsigned)N2C->getZExtValue() < 2 && "Bad EXTRACT_ELEMENT!"); 2471 assert(!N1.getValueType().isVector() && !VT.isVector() && 2472 (N1.getValueType().isInteger() == VT.isInteger()) && 2473 "Wrong types for EXTRACT_ELEMENT!"); 2474 2475 // EXTRACT_ELEMENT of BUILD_PAIR is often formed while legalize is expanding 2476 // 64-bit integers into 32-bit parts. Instead of building the extract of 2477 // the BUILD_PAIR, only to have legalize rip it apart, just do it now. 2478 if (N1.getOpcode() == ISD::BUILD_PAIR) 2479 return N1.getOperand(N2C->getZExtValue()); 2480 2481 // EXTRACT_ELEMENT of a constant int is also very common. 2482 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) { 2483 unsigned ElementSize = VT.getSizeInBits(); 2484 unsigned Shift = ElementSize * N2C->getZExtValue(); 2485 APInt ShiftedVal = C->getAPIntValue().lshr(Shift); 2486 return getConstant(ShiftedVal.trunc(ElementSize), VT); 2487 } 2488 break; 2489 case ISD::EXTRACT_SUBVECTOR: 2490 if (N1.getValueType() == VT) // Trivial extraction. 2491 return N1; 2492 break; 2493 } 2494 2495 if (N1C) { 2496 if (N2C) { 2497 SDValue SV = FoldConstantArithmetic(Opcode, VT, N1C, N2C); 2498 if (SV.getNode()) return SV; 2499 } else { // Cannonicalize constant to RHS if commutative 2500 if (isCommutativeBinOp(Opcode)) { 2501 std::swap(N1C, N2C); 2502 std::swap(N1, N2); 2503 } 2504 } 2505 } 2506 2507 // Constant fold FP operations. 2508 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1.getNode()); 2509 ConstantFPSDNode *N2CFP = dyn_cast<ConstantFPSDNode>(N2.getNode()); 2510 if (N1CFP) { 2511 if (!N2CFP && isCommutativeBinOp(Opcode)) { 2512 // Cannonicalize constant to RHS if commutative 2513 std::swap(N1CFP, N2CFP); 2514 std::swap(N1, N2); 2515 } else if (N2CFP && VT != MVT::ppcf128) { 2516 APFloat V1 = N1CFP->getValueAPF(), V2 = N2CFP->getValueAPF(); 2517 APFloat::opStatus s; 2518 switch (Opcode) { 2519 case ISD::FADD: 2520 s = V1.add(V2, APFloat::rmNearestTiesToEven); 2521 if (s != APFloat::opInvalidOp) 2522 return getConstantFP(V1, VT); 2523 break; 2524 case ISD::FSUB: 2525 s = V1.subtract(V2, APFloat::rmNearestTiesToEven); 2526 if (s!=APFloat::opInvalidOp) 2527 return getConstantFP(V1, VT); 2528 break; 2529 case ISD::FMUL: 2530 s = V1.multiply(V2, APFloat::rmNearestTiesToEven); 2531 if (s!=APFloat::opInvalidOp) 2532 return getConstantFP(V1, VT); 2533 break; 2534 case ISD::FDIV: 2535 s = V1.divide(V2, APFloat::rmNearestTiesToEven); 2536 if (s!=APFloat::opInvalidOp && s!=APFloat::opDivByZero) 2537 return getConstantFP(V1, VT); 2538 break; 2539 case ISD::FREM : 2540 s = V1.mod(V2, APFloat::rmNearestTiesToEven); 2541 if (s!=APFloat::opInvalidOp && s!=APFloat::opDivByZero) 2542 return getConstantFP(V1, VT); 2543 break; 2544 case ISD::FCOPYSIGN: 2545 V1.copySign(V2); 2546 return getConstantFP(V1, VT); 2547 default: break; 2548 } 2549 } 2550 } 2551 2552 // Canonicalize an UNDEF to the RHS, even over a constant. 2553 if (N1.getOpcode() == ISD::UNDEF) { 2554 if (isCommutativeBinOp(Opcode)) { 2555 std::swap(N1, N2); 2556 } else { 2557 switch (Opcode) { 2558 case ISD::FP_ROUND_INREG: 2559 case ISD::SIGN_EXTEND_INREG: 2560 case ISD::SUB: 2561 case ISD::FSUB: 2562 case ISD::FDIV: 2563 case ISD::FREM: 2564 case ISD::SRA: 2565 return N1; // fold op(undef, arg2) -> undef 2566 case ISD::UDIV: 2567 case ISD::SDIV: 2568 case ISD::UREM: 2569 case ISD::SREM: 2570 case ISD::SRL: 2571 case ISD::SHL: 2572 if (!VT.isVector()) 2573 return getConstant(0, VT); // fold op(undef, arg2) -> 0 2574 // For vectors, we can't easily build an all zero vector, just return 2575 // the LHS. 2576 return N2; 2577 } 2578 } 2579 } 2580 2581 // Fold a bunch of operators when the RHS is undef. 2582 if (N2.getOpcode() == ISD::UNDEF) { 2583 switch (Opcode) { 2584 case ISD::XOR: 2585 if (N1.getOpcode() == ISD::UNDEF) 2586 // Handle undef ^ undef -> 0 special case. This is a common 2587 // idiom (misuse). 2588 return getConstant(0, VT); 2589 // fallthrough 2590 case ISD::ADD: 2591 case ISD::ADDC: 2592 case ISD::ADDE: 2593 case ISD::SUB: 2594 case ISD::FADD: 2595 case ISD::FSUB: 2596 case ISD::FMUL: 2597 case ISD::FDIV: 2598 case ISD::FREM: 2599 case ISD::UDIV: 2600 case ISD::SDIV: 2601 case ISD::UREM: 2602 case ISD::SREM: 2603 return N2; // fold op(arg1, undef) -> undef 2604 case ISD::MUL: 2605 case ISD::AND: 2606 case ISD::SRL: 2607 case ISD::SHL: 2608 if (!VT.isVector()) 2609 return getConstant(0, VT); // fold op(arg1, undef) -> 0 2610 // For vectors, we can't easily build an all zero vector, just return 2611 // the LHS. 2612 return N1; 2613 case ISD::OR: 2614 if (!VT.isVector()) 2615 return getConstant(VT.getIntegerVTBitMask(), VT); 2616 // For vectors, we can't easily build an all one vector, just return 2617 // the LHS. 2618 return N1; 2619 case ISD::SRA: 2620 return N1; 2621 } 2622 } 2623 2624 // Memoize this node if possible. 2625 SDNode *N; 2626 SDVTList VTs = getVTList(VT); 2627 if (VT != MVT::Flag) { 2628 SDValue Ops[] = { N1, N2 }; 2629 FoldingSetNodeID ID; 2630 AddNodeIDNode(ID, Opcode, VTs, Ops, 2); 2631 void *IP = 0; 2632 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2633 return SDValue(E, 0); 2634 N = NodeAllocator.Allocate<BinarySDNode>(); 2635 new (N) BinarySDNode(Opcode, VTs, N1, N2); 2636 CSEMap.InsertNode(N, IP); 2637 } else { 2638 N = NodeAllocator.Allocate<BinarySDNode>(); 2639 new (N) BinarySDNode(Opcode, VTs, N1, N2); 2640 } 2641 2642 AllNodes.push_back(N); 2643#ifndef NDEBUG 2644 VerifyNode(N); 2645#endif 2646 return SDValue(N, 0); 2647} 2648 2649SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, 2650 SDValue N1, SDValue N2, SDValue N3) { 2651 // Perform various simplifications. 2652 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 2653 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 2654 switch (Opcode) { 2655 case ISD::CONCAT_VECTORS: 2656 // A CONCAT_VECTOR with all operands BUILD_VECTOR can be simplified to 2657 // one big BUILD_VECTOR. 2658 if (N1.getOpcode() == ISD::BUILD_VECTOR && 2659 N2.getOpcode() == ISD::BUILD_VECTOR && 2660 N3.getOpcode() == ISD::BUILD_VECTOR) { 2661 SmallVector<SDValue, 16> Elts(N1.getNode()->op_begin(), N1.getNode()->op_end()); 2662 Elts.insert(Elts.end(), N2.getNode()->op_begin(), N2.getNode()->op_end()); 2663 Elts.insert(Elts.end(), N3.getNode()->op_begin(), N3.getNode()->op_end()); 2664 return getNode(ISD::BUILD_VECTOR, VT, &Elts[0], Elts.size()); 2665 } 2666 break; 2667 case ISD::SETCC: { 2668 // Use FoldSetCC to simplify SETCC's. 2669 SDValue Simp = FoldSetCC(VT, N1, N2, cast<CondCodeSDNode>(N3)->get()); 2670 if (Simp.getNode()) return Simp; 2671 break; 2672 } 2673 case ISD::SELECT: 2674 if (N1C) { 2675 if (N1C->getZExtValue()) 2676 return N2; // select true, X, Y -> X 2677 else 2678 return N3; // select false, X, Y -> Y 2679 } 2680 2681 if (N2 == N3) return N2; // select C, X, X -> X 2682 break; 2683 case ISD::BRCOND: 2684 if (N2C) { 2685 if (N2C->getZExtValue()) // Unconditional branch 2686 return getNode(ISD::BR, MVT::Other, N1, N3); 2687 else 2688 return N1; // Never-taken branch 2689 } 2690 break; 2691 case ISD::VECTOR_SHUFFLE: 2692 assert(VT == N1.getValueType() && VT == N2.getValueType() && 2693 VT.isVector() && N3.getValueType().isVector() && 2694 N3.getOpcode() == ISD::BUILD_VECTOR && 2695 VT.getVectorNumElements() == N3.getNumOperands() && 2696 "Illegal VECTOR_SHUFFLE node!"); 2697 break; 2698 case ISD::BIT_CONVERT: 2699 // Fold bit_convert nodes from a type to themselves. 2700 if (N1.getValueType() == VT) 2701 return N1; 2702 break; 2703 } 2704 2705 // Memoize node if it doesn't produce a flag. 2706 SDNode *N; 2707 SDVTList VTs = getVTList(VT); 2708 if (VT != MVT::Flag) { 2709 SDValue Ops[] = { N1, N2, N3 }; 2710 FoldingSetNodeID ID; 2711 AddNodeIDNode(ID, Opcode, VTs, Ops, 3); 2712 void *IP = 0; 2713 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2714 return SDValue(E, 0); 2715 N = NodeAllocator.Allocate<TernarySDNode>(); 2716 new (N) TernarySDNode(Opcode, VTs, N1, N2, N3); 2717 CSEMap.InsertNode(N, IP); 2718 } else { 2719 N = NodeAllocator.Allocate<TernarySDNode>(); 2720 new (N) TernarySDNode(Opcode, VTs, N1, N2, N3); 2721 } 2722 AllNodes.push_back(N); 2723#ifndef NDEBUG 2724 VerifyNode(N); 2725#endif 2726 return SDValue(N, 0); 2727} 2728 2729SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, 2730 SDValue N1, SDValue N2, SDValue N3, 2731 SDValue N4) { 2732 SDValue Ops[] = { N1, N2, N3, N4 }; 2733 return getNode(Opcode, VT, Ops, 4); 2734} 2735 2736SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, 2737 SDValue N1, SDValue N2, SDValue N3, 2738 SDValue N4, SDValue N5) { 2739 SDValue Ops[] = { N1, N2, N3, N4, N5 }; 2740 return getNode(Opcode, VT, Ops, 5); 2741} 2742 2743/// getMemsetValue - Vectorized representation of the memset value 2744/// operand. 2745static SDValue getMemsetValue(SDValue Value, MVT VT, SelectionDAG &DAG) { 2746 unsigned NumBits = VT.isVector() ? 2747 VT.getVectorElementType().getSizeInBits() : VT.getSizeInBits(); 2748 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) { 2749 APInt Val = APInt(NumBits, C->getZExtValue() & 255); 2750 unsigned Shift = 8; 2751 for (unsigned i = NumBits; i > 8; i >>= 1) { 2752 Val = (Val << Shift) | Val; 2753 Shift <<= 1; 2754 } 2755 if (VT.isInteger()) 2756 return DAG.getConstant(Val, VT); 2757 return DAG.getConstantFP(APFloat(Val), VT); 2758 } 2759 2760 Value = DAG.getNode(ISD::ZERO_EXTEND, VT, Value); 2761 unsigned Shift = 8; 2762 for (unsigned i = NumBits; i > 8; i >>= 1) { 2763 Value = DAG.getNode(ISD::OR, VT, 2764 DAG.getNode(ISD::SHL, VT, Value, 2765 DAG.getConstant(Shift, MVT::i8)), Value); 2766 Shift <<= 1; 2767 } 2768 2769 return Value; 2770} 2771 2772/// getMemsetStringVal - Similar to getMemsetValue. Except this is only 2773/// used when a memcpy is turned into a memset when the source is a constant 2774/// string ptr. 2775static SDValue getMemsetStringVal(MVT VT, SelectionDAG &DAG, 2776 const TargetLowering &TLI, 2777 std::string &Str, unsigned Offset) { 2778 // Handle vector with all elements zero. 2779 if (Str.empty()) { 2780 if (VT.isInteger()) 2781 return DAG.getConstant(0, VT); 2782 unsigned NumElts = VT.getVectorNumElements(); 2783 MVT EltVT = (VT.getVectorElementType() == MVT::f32) ? MVT::i32 : MVT::i64; 2784 return DAG.getNode(ISD::BIT_CONVERT, VT, 2785 DAG.getConstant(0, MVT::getVectorVT(EltVT, NumElts))); 2786 } 2787 2788 assert(!VT.isVector() && "Can't handle vector type here!"); 2789 unsigned NumBits = VT.getSizeInBits(); 2790 unsigned MSB = NumBits / 8; 2791 uint64_t Val = 0; 2792 if (TLI.isLittleEndian()) 2793 Offset = Offset + MSB - 1; 2794 for (unsigned i = 0; i != MSB; ++i) { 2795 Val = (Val << 8) | (unsigned char)Str[Offset]; 2796 Offset += TLI.isLittleEndian() ? -1 : 1; 2797 } 2798 return DAG.getConstant(Val, VT); 2799} 2800 2801/// getMemBasePlusOffset - Returns base and offset node for the 2802/// 2803static SDValue getMemBasePlusOffset(SDValue Base, unsigned Offset, 2804 SelectionDAG &DAG) { 2805 MVT VT = Base.getValueType(); 2806 return DAG.getNode(ISD::ADD, VT, Base, DAG.getConstant(Offset, VT)); 2807} 2808 2809/// isMemSrcFromString - Returns true if memcpy source is a string constant. 2810/// 2811static bool isMemSrcFromString(SDValue Src, std::string &Str) { 2812 unsigned SrcDelta = 0; 2813 GlobalAddressSDNode *G = NULL; 2814 if (Src.getOpcode() == ISD::GlobalAddress) 2815 G = cast<GlobalAddressSDNode>(Src); 2816 else if (Src.getOpcode() == ISD::ADD && 2817 Src.getOperand(0).getOpcode() == ISD::GlobalAddress && 2818 Src.getOperand(1).getOpcode() == ISD::Constant) { 2819 G = cast<GlobalAddressSDNode>(Src.getOperand(0)); 2820 SrcDelta = cast<ConstantSDNode>(Src.getOperand(1))->getZExtValue(); 2821 } 2822 if (!G) 2823 return false; 2824 2825 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal()); 2826 if (GV && GetConstantStringInfo(GV, Str, SrcDelta, false)) 2827 return true; 2828 2829 return false; 2830} 2831 2832/// MeetsMaxMemopRequirement - Determines if the number of memory ops required 2833/// to replace the memset / memcpy is below the threshold. It also returns the 2834/// types of the sequence of memory ops to perform memset / memcpy. 2835static 2836bool MeetsMaxMemopRequirement(std::vector<MVT> &MemOps, 2837 SDValue Dst, SDValue Src, 2838 unsigned Limit, uint64_t Size, unsigned &Align, 2839 std::string &Str, bool &isSrcStr, 2840 SelectionDAG &DAG, 2841 const TargetLowering &TLI) { 2842 isSrcStr = isMemSrcFromString(Src, Str); 2843 bool isSrcConst = isa<ConstantSDNode>(Src); 2844 bool AllowUnalign = TLI.allowsUnalignedMemoryAccesses(); 2845 MVT VT= TLI.getOptimalMemOpType(Size, Align, isSrcConst, isSrcStr); 2846 if (VT != MVT::iAny) { 2847 unsigned NewAlign = (unsigned) 2848 TLI.getTargetData()->getABITypeAlignment(VT.getTypeForMVT()); 2849 // If source is a string constant, this will require an unaligned load. 2850 if (NewAlign > Align && (isSrcConst || AllowUnalign)) { 2851 if (Dst.getOpcode() != ISD::FrameIndex) { 2852 // Can't change destination alignment. It requires a unaligned store. 2853 if (AllowUnalign) 2854 VT = MVT::iAny; 2855 } else { 2856 int FI = cast<FrameIndexSDNode>(Dst)->getIndex(); 2857 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 2858 if (MFI->isFixedObjectIndex(FI)) { 2859 // Can't change destination alignment. It requires a unaligned store. 2860 if (AllowUnalign) 2861 VT = MVT::iAny; 2862 } else { 2863 // Give the stack frame object a larger alignment if needed. 2864 if (MFI->getObjectAlignment(FI) < NewAlign) 2865 MFI->setObjectAlignment(FI, NewAlign); 2866 Align = NewAlign; 2867 } 2868 } 2869 } 2870 } 2871 2872 if (VT == MVT::iAny) { 2873 if (AllowUnalign) { 2874 VT = MVT::i64; 2875 } else { 2876 switch (Align & 7) { 2877 case 0: VT = MVT::i64; break; 2878 case 4: VT = MVT::i32; break; 2879 case 2: VT = MVT::i16; break; 2880 default: VT = MVT::i8; break; 2881 } 2882 } 2883 2884 MVT LVT = MVT::i64; 2885 while (!TLI.isTypeLegal(LVT)) 2886 LVT = (MVT::SimpleValueType)(LVT.getSimpleVT() - 1); 2887 assert(LVT.isInteger()); 2888 2889 if (VT.bitsGT(LVT)) 2890 VT = LVT; 2891 } 2892 2893 unsigned NumMemOps = 0; 2894 while (Size != 0) { 2895 unsigned VTSize = VT.getSizeInBits() / 8; 2896 while (VTSize > Size) { 2897 // For now, only use non-vector load / store's for the left-over pieces. 2898 if (VT.isVector()) { 2899 VT = MVT::i64; 2900 while (!TLI.isTypeLegal(VT)) 2901 VT = (MVT::SimpleValueType)(VT.getSimpleVT() - 1); 2902 VTSize = VT.getSizeInBits() / 8; 2903 } else { 2904 VT = (MVT::SimpleValueType)(VT.getSimpleVT() - 1); 2905 VTSize >>= 1; 2906 } 2907 } 2908 2909 if (++NumMemOps > Limit) 2910 return false; 2911 MemOps.push_back(VT); 2912 Size -= VTSize; 2913 } 2914 2915 return true; 2916} 2917 2918static SDValue getMemcpyLoadsAndStores(SelectionDAG &DAG, 2919 SDValue Chain, SDValue Dst, 2920 SDValue Src, uint64_t Size, 2921 unsigned Align, bool AlwaysInline, 2922 const Value *DstSV, uint64_t DstSVOff, 2923 const Value *SrcSV, uint64_t SrcSVOff){ 2924 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 2925 2926 // Expand memcpy to a series of load and store ops if the size operand falls 2927 // below a certain threshold. 2928 std::vector<MVT> MemOps; 2929 uint64_t Limit = -1; 2930 if (!AlwaysInline) 2931 Limit = TLI.getMaxStoresPerMemcpy(); 2932 unsigned DstAlign = Align; // Destination alignment can change. 2933 std::string Str; 2934 bool CopyFromStr; 2935 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, Limit, Size, DstAlign, 2936 Str, CopyFromStr, DAG, TLI)) 2937 return SDValue(); 2938 2939 2940 bool isZeroStr = CopyFromStr && Str.empty(); 2941 SmallVector<SDValue, 8> OutChains; 2942 unsigned NumMemOps = MemOps.size(); 2943 uint64_t SrcOff = 0, DstOff = 0; 2944 for (unsigned i = 0; i < NumMemOps; i++) { 2945 MVT VT = MemOps[i]; 2946 unsigned VTSize = VT.getSizeInBits() / 8; 2947 SDValue Value, Store; 2948 2949 if (CopyFromStr && (isZeroStr || !VT.isVector())) { 2950 // It's unlikely a store of a vector immediate can be done in a single 2951 // instruction. It would require a load from a constantpool first. 2952 // We also handle store a vector with all zero's. 2953 // FIXME: Handle other cases where store of vector immediate is done in 2954 // a single instruction. 2955 Value = getMemsetStringVal(VT, DAG, TLI, Str, SrcOff); 2956 Store = DAG.getStore(Chain, Value, 2957 getMemBasePlusOffset(Dst, DstOff, DAG), 2958 DstSV, DstSVOff + DstOff, false, DstAlign); 2959 } else { 2960 Value = DAG.getLoad(VT, Chain, 2961 getMemBasePlusOffset(Src, SrcOff, DAG), 2962 SrcSV, SrcSVOff + SrcOff, false, Align); 2963 Store = DAG.getStore(Chain, Value, 2964 getMemBasePlusOffset(Dst, DstOff, DAG), 2965 DstSV, DstSVOff + DstOff, false, DstAlign); 2966 } 2967 OutChains.push_back(Store); 2968 SrcOff += VTSize; 2969 DstOff += VTSize; 2970 } 2971 2972 return DAG.getNode(ISD::TokenFactor, MVT::Other, 2973 &OutChains[0], OutChains.size()); 2974} 2975 2976static SDValue getMemmoveLoadsAndStores(SelectionDAG &DAG, 2977 SDValue Chain, SDValue Dst, 2978 SDValue Src, uint64_t Size, 2979 unsigned Align, bool AlwaysInline, 2980 const Value *DstSV, uint64_t DstSVOff, 2981 const Value *SrcSV, uint64_t SrcSVOff){ 2982 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 2983 2984 // Expand memmove to a series of load and store ops if the size operand falls 2985 // below a certain threshold. 2986 std::vector<MVT> MemOps; 2987 uint64_t Limit = -1; 2988 if (!AlwaysInline) 2989 Limit = TLI.getMaxStoresPerMemmove(); 2990 unsigned DstAlign = Align; // Destination alignment can change. 2991 std::string Str; 2992 bool CopyFromStr; 2993 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, Limit, Size, DstAlign, 2994 Str, CopyFromStr, DAG, TLI)) 2995 return SDValue(); 2996 2997 uint64_t SrcOff = 0, DstOff = 0; 2998 2999 SmallVector<SDValue, 8> LoadValues; 3000 SmallVector<SDValue, 8> LoadChains; 3001 SmallVector<SDValue, 8> OutChains; 3002 unsigned NumMemOps = MemOps.size(); 3003 for (unsigned i = 0; i < NumMemOps; i++) { 3004 MVT VT = MemOps[i]; 3005 unsigned VTSize = VT.getSizeInBits() / 8; 3006 SDValue Value, Store; 3007 3008 Value = DAG.getLoad(VT, Chain, 3009 getMemBasePlusOffset(Src, SrcOff, DAG), 3010 SrcSV, SrcSVOff + SrcOff, false, Align); 3011 LoadValues.push_back(Value); 3012 LoadChains.push_back(Value.getValue(1)); 3013 SrcOff += VTSize; 3014 } 3015 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 3016 &LoadChains[0], LoadChains.size()); 3017 OutChains.clear(); 3018 for (unsigned i = 0; i < NumMemOps; i++) { 3019 MVT VT = MemOps[i]; 3020 unsigned VTSize = VT.getSizeInBits() / 8; 3021 SDValue Value, Store; 3022 3023 Store = DAG.getStore(Chain, LoadValues[i], 3024 getMemBasePlusOffset(Dst, DstOff, DAG), 3025 DstSV, DstSVOff + DstOff, false, DstAlign); 3026 OutChains.push_back(Store); 3027 DstOff += VTSize; 3028 } 3029 3030 return DAG.getNode(ISD::TokenFactor, MVT::Other, 3031 &OutChains[0], OutChains.size()); 3032} 3033 3034static SDValue getMemsetStores(SelectionDAG &DAG, 3035 SDValue Chain, SDValue Dst, 3036 SDValue Src, uint64_t Size, 3037 unsigned Align, 3038 const Value *DstSV, uint64_t DstSVOff) { 3039 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 3040 3041 // Expand memset to a series of load/store ops if the size operand 3042 // falls below a certain threshold. 3043 std::vector<MVT> MemOps; 3044 std::string Str; 3045 bool CopyFromStr; 3046 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, TLI.getMaxStoresPerMemset(), 3047 Size, Align, Str, CopyFromStr, DAG, TLI)) 3048 return SDValue(); 3049 3050 SmallVector<SDValue, 8> OutChains; 3051 uint64_t DstOff = 0; 3052 3053 unsigned NumMemOps = MemOps.size(); 3054 for (unsigned i = 0; i < NumMemOps; i++) { 3055 MVT VT = MemOps[i]; 3056 unsigned VTSize = VT.getSizeInBits() / 8; 3057 SDValue Value = getMemsetValue(Src, VT, DAG); 3058 SDValue Store = DAG.getStore(Chain, Value, 3059 getMemBasePlusOffset(Dst, DstOff, DAG), 3060 DstSV, DstSVOff + DstOff); 3061 OutChains.push_back(Store); 3062 DstOff += VTSize; 3063 } 3064 3065 return DAG.getNode(ISD::TokenFactor, MVT::Other, 3066 &OutChains[0], OutChains.size()); 3067} 3068 3069SDValue SelectionDAG::getMemcpy(SDValue Chain, SDValue Dst, 3070 SDValue Src, SDValue Size, 3071 unsigned Align, bool AlwaysInline, 3072 const Value *DstSV, uint64_t DstSVOff, 3073 const Value *SrcSV, uint64_t SrcSVOff) { 3074 3075 // Check to see if we should lower the memcpy to loads and stores first. 3076 // For cases within the target-specified limits, this is the best choice. 3077 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 3078 if (ConstantSize) { 3079 // Memcpy with size zero? Just return the original chain. 3080 if (ConstantSize->isNullValue()) 3081 return Chain; 3082 3083 SDValue Result = 3084 getMemcpyLoadsAndStores(*this, Chain, Dst, Src, 3085 ConstantSize->getZExtValue(), 3086 Align, false, DstSV, DstSVOff, SrcSV, SrcSVOff); 3087 if (Result.getNode()) 3088 return Result; 3089 } 3090 3091 // Then check to see if we should lower the memcpy with target-specific 3092 // code. If the target chooses to do this, this is the next best. 3093 SDValue Result = 3094 TLI.EmitTargetCodeForMemcpy(*this, Chain, Dst, Src, Size, Align, 3095 AlwaysInline, 3096 DstSV, DstSVOff, SrcSV, SrcSVOff); 3097 if (Result.getNode()) 3098 return Result; 3099 3100 // If we really need inline code and the target declined to provide it, 3101 // use a (potentially long) sequence of loads and stores. 3102 if (AlwaysInline) { 3103 assert(ConstantSize && "AlwaysInline requires a constant size!"); 3104 return getMemcpyLoadsAndStores(*this, Chain, Dst, Src, 3105 ConstantSize->getZExtValue(), Align, true, 3106 DstSV, DstSVOff, SrcSV, SrcSVOff); 3107 } 3108 3109 // Emit a library call. 3110 TargetLowering::ArgListTy Args; 3111 TargetLowering::ArgListEntry Entry; 3112 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 3113 Entry.Node = Dst; Args.push_back(Entry); 3114 Entry.Node = Src; Args.push_back(Entry); 3115 Entry.Node = Size; Args.push_back(Entry); 3116 std::pair<SDValue,SDValue> CallResult = 3117 TLI.LowerCallTo(Chain, Type::VoidTy, 3118 false, false, false, false, CallingConv::C, false, 3119 getExternalSymbol("memcpy", TLI.getPointerTy()), 3120 Args, *this); 3121 return CallResult.second; 3122} 3123 3124SDValue SelectionDAG::getMemmove(SDValue Chain, SDValue Dst, 3125 SDValue Src, SDValue Size, 3126 unsigned Align, 3127 const Value *DstSV, uint64_t DstSVOff, 3128 const Value *SrcSV, uint64_t SrcSVOff) { 3129 3130 // Check to see if we should lower the memmove to loads and stores first. 3131 // For cases within the target-specified limits, this is the best choice. 3132 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 3133 if (ConstantSize) { 3134 // Memmove with size zero? Just return the original chain. 3135 if (ConstantSize->isNullValue()) 3136 return Chain; 3137 3138 SDValue Result = 3139 getMemmoveLoadsAndStores(*this, Chain, Dst, Src, 3140 ConstantSize->getZExtValue(), 3141 Align, false, DstSV, DstSVOff, SrcSV, SrcSVOff); 3142 if (Result.getNode()) 3143 return Result; 3144 } 3145 3146 // Then check to see if we should lower the memmove with target-specific 3147 // code. If the target chooses to do this, this is the next best. 3148 SDValue Result = 3149 TLI.EmitTargetCodeForMemmove(*this, Chain, Dst, Src, Size, Align, 3150 DstSV, DstSVOff, SrcSV, SrcSVOff); 3151 if (Result.getNode()) 3152 return Result; 3153 3154 // Emit a library call. 3155 TargetLowering::ArgListTy Args; 3156 TargetLowering::ArgListEntry Entry; 3157 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 3158 Entry.Node = Dst; Args.push_back(Entry); 3159 Entry.Node = Src; Args.push_back(Entry); 3160 Entry.Node = Size; Args.push_back(Entry); 3161 std::pair<SDValue,SDValue> CallResult = 3162 TLI.LowerCallTo(Chain, Type::VoidTy, 3163 false, false, false, false, CallingConv::C, false, 3164 getExternalSymbol("memmove", TLI.getPointerTy()), 3165 Args, *this); 3166 return CallResult.second; 3167} 3168 3169SDValue SelectionDAG::getMemset(SDValue Chain, SDValue Dst, 3170 SDValue Src, SDValue Size, 3171 unsigned Align, 3172 const Value *DstSV, uint64_t DstSVOff) { 3173 3174 // Check to see if we should lower the memset to stores first. 3175 // For cases within the target-specified limits, this is the best choice. 3176 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 3177 if (ConstantSize) { 3178 // Memset with size zero? Just return the original chain. 3179 if (ConstantSize->isNullValue()) 3180 return Chain; 3181 3182 SDValue Result = 3183 getMemsetStores(*this, Chain, Dst, Src, ConstantSize->getZExtValue(), 3184 Align, DstSV, DstSVOff); 3185 if (Result.getNode()) 3186 return Result; 3187 } 3188 3189 // Then check to see if we should lower the memset with target-specific 3190 // code. If the target chooses to do this, this is the next best. 3191 SDValue Result = 3192 TLI.EmitTargetCodeForMemset(*this, Chain, Dst, Src, Size, Align, 3193 DstSV, DstSVOff); 3194 if (Result.getNode()) 3195 return Result; 3196 3197 // Emit a library call. 3198 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType(); 3199 TargetLowering::ArgListTy Args; 3200 TargetLowering::ArgListEntry Entry; 3201 Entry.Node = Dst; Entry.Ty = IntPtrTy; 3202 Args.push_back(Entry); 3203 // Extend or truncate the argument to be an i32 value for the call. 3204 if (Src.getValueType().bitsGT(MVT::i32)) 3205 Src = getNode(ISD::TRUNCATE, MVT::i32, Src); 3206 else 3207 Src = getNode(ISD::ZERO_EXTEND, MVT::i32, Src); 3208 Entry.Node = Src; Entry.Ty = Type::Int32Ty; Entry.isSExt = true; 3209 Args.push_back(Entry); 3210 Entry.Node = Size; Entry.Ty = IntPtrTy; Entry.isSExt = false; 3211 Args.push_back(Entry); 3212 std::pair<SDValue,SDValue> CallResult = 3213 TLI.LowerCallTo(Chain, Type::VoidTy, 3214 false, false, false, false, CallingConv::C, false, 3215 getExternalSymbol("memset", TLI.getPointerTy()), 3216 Args, *this); 3217 return CallResult.second; 3218} 3219 3220SDValue SelectionDAG::getAtomic(unsigned Opcode, SDValue Chain, 3221 SDValue Ptr, SDValue Cmp, 3222 SDValue Swp, const Value* PtrVal, 3223 unsigned Alignment) { 3224 assert((Opcode == ISD::ATOMIC_CMP_SWAP_8 || 3225 Opcode == ISD::ATOMIC_CMP_SWAP_16 || 3226 Opcode == ISD::ATOMIC_CMP_SWAP_32 || 3227 Opcode == ISD::ATOMIC_CMP_SWAP_64) && "Invalid Atomic Op"); 3228 assert(Cmp.getValueType() == Swp.getValueType() && "Invalid Atomic Op Types"); 3229 3230 MVT VT = Cmp.getValueType(); 3231 3232 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3233 Alignment = getMVTAlignment(VT); 3234 3235 SDVTList VTs = getVTList(VT, MVT::Other); 3236 FoldingSetNodeID ID; 3237 SDValue Ops[] = {Chain, Ptr, Cmp, Swp}; 3238 AddNodeIDNode(ID, Opcode, VTs, Ops, 4); 3239 void* IP = 0; 3240 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3241 return SDValue(E, 0); 3242 SDNode* N = NodeAllocator.Allocate<AtomicSDNode>(); 3243 new (N) AtomicSDNode(Opcode, VTs, Chain, Ptr, Cmp, Swp, PtrVal, Alignment); 3244 CSEMap.InsertNode(N, IP); 3245 AllNodes.push_back(N); 3246 return SDValue(N, 0); 3247} 3248 3249SDValue SelectionDAG::getAtomic(unsigned Opcode, SDValue Chain, 3250 SDValue Ptr, SDValue Val, 3251 const Value* PtrVal, 3252 unsigned Alignment) { 3253 assert((Opcode == ISD::ATOMIC_LOAD_ADD_8 || 3254 Opcode == ISD::ATOMIC_LOAD_SUB_8 || 3255 Opcode == ISD::ATOMIC_LOAD_AND_8 || 3256 Opcode == ISD::ATOMIC_LOAD_OR_8 || 3257 Opcode == ISD::ATOMIC_LOAD_XOR_8 || 3258 Opcode == ISD::ATOMIC_LOAD_NAND_8 || 3259 Opcode == ISD::ATOMIC_LOAD_MIN_8 || 3260 Opcode == ISD::ATOMIC_LOAD_MAX_8 || 3261 Opcode == ISD::ATOMIC_LOAD_UMIN_8 || 3262 Opcode == ISD::ATOMIC_LOAD_UMAX_8 || 3263 Opcode == ISD::ATOMIC_SWAP_8 || 3264 Opcode == ISD::ATOMIC_LOAD_ADD_16 || 3265 Opcode == ISD::ATOMIC_LOAD_SUB_16 || 3266 Opcode == ISD::ATOMIC_LOAD_AND_16 || 3267 Opcode == ISD::ATOMIC_LOAD_OR_16 || 3268 Opcode == ISD::ATOMIC_LOAD_XOR_16 || 3269 Opcode == ISD::ATOMIC_LOAD_NAND_16 || 3270 Opcode == ISD::ATOMIC_LOAD_MIN_16 || 3271 Opcode == ISD::ATOMIC_LOAD_MAX_16 || 3272 Opcode == ISD::ATOMIC_LOAD_UMIN_16 || 3273 Opcode == ISD::ATOMIC_LOAD_UMAX_16 || 3274 Opcode == ISD::ATOMIC_SWAP_16 || 3275 Opcode == ISD::ATOMIC_LOAD_ADD_32 || 3276 Opcode == ISD::ATOMIC_LOAD_SUB_32 || 3277 Opcode == ISD::ATOMIC_LOAD_AND_32 || 3278 Opcode == ISD::ATOMIC_LOAD_OR_32 || 3279 Opcode == ISD::ATOMIC_LOAD_XOR_32 || 3280 Opcode == ISD::ATOMIC_LOAD_NAND_32 || 3281 Opcode == ISD::ATOMIC_LOAD_MIN_32 || 3282 Opcode == ISD::ATOMIC_LOAD_MAX_32 || 3283 Opcode == ISD::ATOMIC_LOAD_UMIN_32 || 3284 Opcode == ISD::ATOMIC_LOAD_UMAX_32 || 3285 Opcode == ISD::ATOMIC_SWAP_32 || 3286 Opcode == ISD::ATOMIC_LOAD_ADD_64 || 3287 Opcode == ISD::ATOMIC_LOAD_SUB_64 || 3288 Opcode == ISD::ATOMIC_LOAD_AND_64 || 3289 Opcode == ISD::ATOMIC_LOAD_OR_64 || 3290 Opcode == ISD::ATOMIC_LOAD_XOR_64 || 3291 Opcode == ISD::ATOMIC_LOAD_NAND_64 || 3292 Opcode == ISD::ATOMIC_LOAD_MIN_64 || 3293 Opcode == ISD::ATOMIC_LOAD_MAX_64 || 3294 Opcode == ISD::ATOMIC_LOAD_UMIN_64 || 3295 Opcode == ISD::ATOMIC_LOAD_UMAX_64 || 3296 Opcode == ISD::ATOMIC_SWAP_64) && "Invalid Atomic Op"); 3297 3298 MVT VT = Val.getValueType(); 3299 3300 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3301 Alignment = getMVTAlignment(VT); 3302 3303 SDVTList VTs = getVTList(VT, MVT::Other); 3304 FoldingSetNodeID ID; 3305 SDValue Ops[] = {Chain, Ptr, Val}; 3306 AddNodeIDNode(ID, Opcode, VTs, Ops, 3); 3307 void* IP = 0; 3308 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3309 return SDValue(E, 0); 3310 SDNode* N = NodeAllocator.Allocate<AtomicSDNode>(); 3311 new (N) AtomicSDNode(Opcode, VTs, Chain, Ptr, Val, PtrVal, Alignment); 3312 CSEMap.InsertNode(N, IP); 3313 AllNodes.push_back(N); 3314 return SDValue(N, 0); 3315} 3316 3317/// getMergeValues - Create a MERGE_VALUES node from the given operands. 3318/// Allowed to return something different (and simpler) if Simplify is true. 3319SDValue SelectionDAG::getMergeValues(const SDValue *Ops, unsigned NumOps, 3320 bool Simplify) { 3321 if (Simplify && NumOps == 1) 3322 return Ops[0]; 3323 3324 SmallVector<MVT, 4> VTs; 3325 VTs.reserve(NumOps); 3326 for (unsigned i = 0; i < NumOps; ++i) 3327 VTs.push_back(Ops[i].getValueType()); 3328 return getNode(ISD::MERGE_VALUES, getVTList(&VTs[0], NumOps), Ops, NumOps); 3329} 3330 3331SDValue 3332SelectionDAG::getCall(unsigned CallingConv, bool IsVarArgs, bool IsTailCall, 3333 bool IsInreg, SDVTList VTs, 3334 const SDValue *Operands, unsigned NumOperands) { 3335 // Do not include isTailCall in the folding set profile. 3336 FoldingSetNodeID ID; 3337 AddNodeIDNode(ID, ISD::CALL, VTs, Operands, NumOperands); 3338 ID.AddInteger(CallingConv); 3339 ID.AddInteger(IsVarArgs); 3340 void *IP = 0; 3341 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) { 3342 // Instead of including isTailCall in the folding set, we just 3343 // set the flag of the existing node. 3344 if (!IsTailCall) 3345 cast<CallSDNode>(E)->setNotTailCall(); 3346 return SDValue(E, 0); 3347 } 3348 SDNode *N = NodeAllocator.Allocate<CallSDNode>(); 3349 new (N) CallSDNode(CallingConv, IsVarArgs, IsTailCall, IsInreg, 3350 VTs, Operands, NumOperands); 3351 CSEMap.InsertNode(N, IP); 3352 AllNodes.push_back(N); 3353 return SDValue(N, 0); 3354} 3355 3356SDValue 3357SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, 3358 MVT VT, SDValue Chain, 3359 SDValue Ptr, SDValue Offset, 3360 const Value *SV, int SVOffset, MVT EVT, 3361 bool isVolatile, unsigned Alignment) { 3362 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3363 Alignment = getMVTAlignment(VT); 3364 3365 if (VT == EVT) { 3366 ExtType = ISD::NON_EXTLOAD; 3367 } else if (ExtType == ISD::NON_EXTLOAD) { 3368 assert(VT == EVT && "Non-extending load from different memory type!"); 3369 } else { 3370 // Extending load. 3371 if (VT.isVector()) 3372 assert(EVT.getVectorNumElements() == VT.getVectorNumElements() && 3373 "Invalid vector extload!"); 3374 else 3375 assert(EVT.bitsLT(VT) && 3376 "Should only be an extending load, not truncating!"); 3377 assert((ExtType == ISD::EXTLOAD || VT.isInteger()) && 3378 "Cannot sign/zero extend a FP/Vector load!"); 3379 assert(VT.isInteger() == EVT.isInteger() && 3380 "Cannot convert from FP to Int or Int -> FP!"); 3381 } 3382 3383 bool Indexed = AM != ISD::UNINDEXED; 3384 assert((Indexed || Offset.getOpcode() == ISD::UNDEF) && 3385 "Unindexed load with an offset!"); 3386 3387 SDVTList VTs = Indexed ? 3388 getVTList(VT, Ptr.getValueType(), MVT::Other) : getVTList(VT, MVT::Other); 3389 SDValue Ops[] = { Chain, Ptr, Offset }; 3390 FoldingSetNodeID ID; 3391 AddNodeIDNode(ID, ISD::LOAD, VTs, Ops, 3); 3392 ID.AddInteger(AM); 3393 ID.AddInteger(ExtType); 3394 ID.AddInteger(EVT.getRawBits()); 3395 ID.AddInteger(encodeMemSDNodeFlags(isVolatile, Alignment)); 3396 void *IP = 0; 3397 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3398 return SDValue(E, 0); 3399 SDNode *N = NodeAllocator.Allocate<LoadSDNode>(); 3400 new (N) LoadSDNode(Ops, VTs, AM, ExtType, EVT, SV, SVOffset, 3401 Alignment, isVolatile); 3402 CSEMap.InsertNode(N, IP); 3403 AllNodes.push_back(N); 3404 return SDValue(N, 0); 3405} 3406 3407SDValue SelectionDAG::getLoad(MVT VT, 3408 SDValue Chain, SDValue Ptr, 3409 const Value *SV, int SVOffset, 3410 bool isVolatile, unsigned Alignment) { 3411 SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType()); 3412 return getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD, VT, Chain, Ptr, Undef, 3413 SV, SVOffset, VT, isVolatile, Alignment); 3414} 3415 3416SDValue SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, MVT VT, 3417 SDValue Chain, SDValue Ptr, 3418 const Value *SV, 3419 int SVOffset, MVT EVT, 3420 bool isVolatile, unsigned Alignment) { 3421 SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType()); 3422 return getLoad(ISD::UNINDEXED, ExtType, VT, Chain, Ptr, Undef, 3423 SV, SVOffset, EVT, isVolatile, Alignment); 3424} 3425 3426SDValue 3427SelectionDAG::getIndexedLoad(SDValue OrigLoad, SDValue Base, 3428 SDValue Offset, ISD::MemIndexedMode AM) { 3429 LoadSDNode *LD = cast<LoadSDNode>(OrigLoad); 3430 assert(LD->getOffset().getOpcode() == ISD::UNDEF && 3431 "Load is already a indexed load!"); 3432 return getLoad(AM, LD->getExtensionType(), OrigLoad.getValueType(), 3433 LD->getChain(), Base, Offset, LD->getSrcValue(), 3434 LD->getSrcValueOffset(), LD->getMemoryVT(), 3435 LD->isVolatile(), LD->getAlignment()); 3436} 3437 3438SDValue SelectionDAG::getStore(SDValue Chain, SDValue Val, 3439 SDValue Ptr, const Value *SV, int SVOffset, 3440 bool isVolatile, unsigned Alignment) { 3441 MVT VT = Val.getValueType(); 3442 3443 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3444 Alignment = getMVTAlignment(VT); 3445 3446 SDVTList VTs = getVTList(MVT::Other); 3447 SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType()); 3448 SDValue Ops[] = { Chain, Val, Ptr, Undef }; 3449 FoldingSetNodeID ID; 3450 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); 3451 ID.AddInteger(ISD::UNINDEXED); 3452 ID.AddInteger(false); 3453 ID.AddInteger(VT.getRawBits()); 3454 ID.AddInteger(encodeMemSDNodeFlags(isVolatile, Alignment)); 3455 void *IP = 0; 3456 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3457 return SDValue(E, 0); 3458 SDNode *N = NodeAllocator.Allocate<StoreSDNode>(); 3459 new (N) StoreSDNode(Ops, VTs, ISD::UNINDEXED, false, 3460 VT, SV, SVOffset, Alignment, isVolatile); 3461 CSEMap.InsertNode(N, IP); 3462 AllNodes.push_back(N); 3463 return SDValue(N, 0); 3464} 3465 3466SDValue SelectionDAG::getTruncStore(SDValue Chain, SDValue Val, 3467 SDValue Ptr, const Value *SV, 3468 int SVOffset, MVT SVT, 3469 bool isVolatile, unsigned Alignment) { 3470 MVT VT = Val.getValueType(); 3471 3472 if (VT == SVT) 3473 return getStore(Chain, Val, Ptr, SV, SVOffset, isVolatile, Alignment); 3474 3475 assert(VT.bitsGT(SVT) && "Not a truncation?"); 3476 assert(VT.isInteger() == SVT.isInteger() && 3477 "Can't do FP-INT conversion!"); 3478 3479 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3480 Alignment = getMVTAlignment(VT); 3481 3482 SDVTList VTs = getVTList(MVT::Other); 3483 SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType()); 3484 SDValue Ops[] = { Chain, Val, Ptr, Undef }; 3485 FoldingSetNodeID ID; 3486 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); 3487 ID.AddInteger(ISD::UNINDEXED); 3488 ID.AddInteger(1); 3489 ID.AddInteger(SVT.getRawBits()); 3490 ID.AddInteger(encodeMemSDNodeFlags(isVolatile, Alignment)); 3491 void *IP = 0; 3492 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3493 return SDValue(E, 0); 3494 SDNode *N = NodeAllocator.Allocate<StoreSDNode>(); 3495 new (N) StoreSDNode(Ops, VTs, ISD::UNINDEXED, true, 3496 SVT, SV, SVOffset, Alignment, isVolatile); 3497 CSEMap.InsertNode(N, IP); 3498 AllNodes.push_back(N); 3499 return SDValue(N, 0); 3500} 3501 3502SDValue 3503SelectionDAG::getIndexedStore(SDValue OrigStore, SDValue Base, 3504 SDValue Offset, ISD::MemIndexedMode AM) { 3505 StoreSDNode *ST = cast<StoreSDNode>(OrigStore); 3506 assert(ST->getOffset().getOpcode() == ISD::UNDEF && 3507 "Store is already a indexed store!"); 3508 SDVTList VTs = getVTList(Base.getValueType(), MVT::Other); 3509 SDValue Ops[] = { ST->getChain(), ST->getValue(), Base, Offset }; 3510 FoldingSetNodeID ID; 3511 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); 3512 ID.AddInteger(AM); 3513 ID.AddInteger(ST->isTruncatingStore()); 3514 ID.AddInteger(ST->getMemoryVT().getRawBits()); 3515 ID.AddInteger(ST->getRawFlags()); 3516 void *IP = 0; 3517 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3518 return SDValue(E, 0); 3519 SDNode *N = NodeAllocator.Allocate<StoreSDNode>(); 3520 new (N) StoreSDNode(Ops, VTs, AM, 3521 ST->isTruncatingStore(), ST->getMemoryVT(), 3522 ST->getSrcValue(), ST->getSrcValueOffset(), 3523 ST->getAlignment(), ST->isVolatile()); 3524 CSEMap.InsertNode(N, IP); 3525 AllNodes.push_back(N); 3526 return SDValue(N, 0); 3527} 3528 3529SDValue SelectionDAG::getVAArg(MVT VT, 3530 SDValue Chain, SDValue Ptr, 3531 SDValue SV) { 3532 SDValue Ops[] = { Chain, Ptr, SV }; 3533 return getNode(ISD::VAARG, getVTList(VT, MVT::Other), Ops, 3); 3534} 3535 3536SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, 3537 const SDUse *Ops, unsigned NumOps) { 3538 switch (NumOps) { 3539 case 0: return getNode(Opcode, VT); 3540 case 1: return getNode(Opcode, VT, Ops[0]); 3541 case 2: return getNode(Opcode, VT, Ops[0], Ops[1]); 3542 case 3: return getNode(Opcode, VT, Ops[0], Ops[1], Ops[2]); 3543 default: break; 3544 } 3545 3546 // Copy from an SDUse array into an SDValue array for use with 3547 // the regular getNode logic. 3548 SmallVector<SDValue, 8> NewOps(Ops, Ops + NumOps); 3549 return getNode(Opcode, VT, &NewOps[0], NumOps); 3550} 3551 3552SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, 3553 const SDValue *Ops, unsigned NumOps) { 3554 switch (NumOps) { 3555 case 0: return getNode(Opcode, VT); 3556 case 1: return getNode(Opcode, VT, Ops[0]); 3557 case 2: return getNode(Opcode, VT, Ops[0], Ops[1]); 3558 case 3: return getNode(Opcode, VT, Ops[0], Ops[1], Ops[2]); 3559 default: break; 3560 } 3561 3562 switch (Opcode) { 3563 default: break; 3564 case ISD::SELECT_CC: { 3565 assert(NumOps == 5 && "SELECT_CC takes 5 operands!"); 3566 assert(Ops[0].getValueType() == Ops[1].getValueType() && 3567 "LHS and RHS of condition must have same type!"); 3568 assert(Ops[2].getValueType() == Ops[3].getValueType() && 3569 "True and False arms of SelectCC must have same type!"); 3570 assert(Ops[2].getValueType() == VT && 3571 "select_cc node must be of same type as true and false value!"); 3572 break; 3573 } 3574 case ISD::BR_CC: { 3575 assert(NumOps == 5 && "BR_CC takes 5 operands!"); 3576 assert(Ops[2].getValueType() == Ops[3].getValueType() && 3577 "LHS/RHS of comparison should match types!"); 3578 break; 3579 } 3580 } 3581 3582 // Memoize nodes. 3583 SDNode *N; 3584 SDVTList VTs = getVTList(VT); 3585 if (VT != MVT::Flag) { 3586 FoldingSetNodeID ID; 3587 AddNodeIDNode(ID, Opcode, VTs, Ops, NumOps); 3588 void *IP = 0; 3589 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3590 return SDValue(E, 0); 3591 N = NodeAllocator.Allocate<SDNode>(); 3592 new (N) SDNode(Opcode, VTs, Ops, NumOps); 3593 CSEMap.InsertNode(N, IP); 3594 } else { 3595 N = NodeAllocator.Allocate<SDNode>(); 3596 new (N) SDNode(Opcode, VTs, Ops, NumOps); 3597 } 3598 AllNodes.push_back(N); 3599#ifndef NDEBUG 3600 VerifyNode(N); 3601#endif 3602 return SDValue(N, 0); 3603} 3604 3605SDValue SelectionDAG::getNode(unsigned Opcode, 3606 const std::vector<MVT> &ResultTys, 3607 const SDValue *Ops, unsigned NumOps) { 3608 return getNode(Opcode, getNodeValueTypes(ResultTys), ResultTys.size(), 3609 Ops, NumOps); 3610} 3611 3612SDValue SelectionDAG::getNode(unsigned Opcode, 3613 const MVT *VTs, unsigned NumVTs, 3614 const SDValue *Ops, unsigned NumOps) { 3615 if (NumVTs == 1) 3616 return getNode(Opcode, VTs[0], Ops, NumOps); 3617 return getNode(Opcode, makeVTList(VTs, NumVTs), Ops, NumOps); 3618} 3619 3620SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, 3621 const SDValue *Ops, unsigned NumOps) { 3622 if (VTList.NumVTs == 1) 3623 return getNode(Opcode, VTList.VTs[0], Ops, NumOps); 3624 3625 switch (Opcode) { 3626 // FIXME: figure out how to safely handle things like 3627 // int foo(int x) { return 1 << (x & 255); } 3628 // int bar() { return foo(256); } 3629#if 0 3630 case ISD::SRA_PARTS: 3631 case ISD::SRL_PARTS: 3632 case ISD::SHL_PARTS: 3633 if (N3.getOpcode() == ISD::SIGN_EXTEND_INREG && 3634 cast<VTSDNode>(N3.getOperand(1))->getVT() != MVT::i1) 3635 return getNode(Opcode, VT, N1, N2, N3.getOperand(0)); 3636 else if (N3.getOpcode() == ISD::AND) 3637 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(N3.getOperand(1))) { 3638 // If the and is only masking out bits that cannot effect the shift, 3639 // eliminate the and. 3640 unsigned NumBits = VT.getSizeInBits()*2; 3641 if ((AndRHS->getValue() & (NumBits-1)) == NumBits-1) 3642 return getNode(Opcode, VT, N1, N2, N3.getOperand(0)); 3643 } 3644 break; 3645#endif 3646 } 3647 3648 // Memoize the node unless it returns a flag. 3649 SDNode *N; 3650 if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) { 3651 FoldingSetNodeID ID; 3652 AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps); 3653 void *IP = 0; 3654 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3655 return SDValue(E, 0); 3656 if (NumOps == 1) { 3657 N = NodeAllocator.Allocate<UnarySDNode>(); 3658 new (N) UnarySDNode(Opcode, VTList, Ops[0]); 3659 } else if (NumOps == 2) { 3660 N = NodeAllocator.Allocate<BinarySDNode>(); 3661 new (N) BinarySDNode(Opcode, VTList, Ops[0], Ops[1]); 3662 } else if (NumOps == 3) { 3663 N = NodeAllocator.Allocate<TernarySDNode>(); 3664 new (N) TernarySDNode(Opcode, VTList, Ops[0], Ops[1], Ops[2]); 3665 } else { 3666 N = NodeAllocator.Allocate<SDNode>(); 3667 new (N) SDNode(Opcode, VTList, Ops, NumOps); 3668 } 3669 CSEMap.InsertNode(N, IP); 3670 } else { 3671 if (NumOps == 1) { 3672 N = NodeAllocator.Allocate<UnarySDNode>(); 3673 new (N) UnarySDNode(Opcode, VTList, Ops[0]); 3674 } else if (NumOps == 2) { 3675 N = NodeAllocator.Allocate<BinarySDNode>(); 3676 new (N) BinarySDNode(Opcode, VTList, Ops[0], Ops[1]); 3677 } else if (NumOps == 3) { 3678 N = NodeAllocator.Allocate<TernarySDNode>(); 3679 new (N) TernarySDNode(Opcode, VTList, Ops[0], Ops[1], Ops[2]); 3680 } else { 3681 N = NodeAllocator.Allocate<SDNode>(); 3682 new (N) SDNode(Opcode, VTList, Ops, NumOps); 3683 } 3684 } 3685 AllNodes.push_back(N); 3686#ifndef NDEBUG 3687 VerifyNode(N); 3688#endif 3689 return SDValue(N, 0); 3690} 3691 3692SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList) { 3693 return getNode(Opcode, VTList, 0, 0); 3694} 3695 3696SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, 3697 SDValue N1) { 3698 SDValue Ops[] = { N1 }; 3699 return getNode(Opcode, VTList, Ops, 1); 3700} 3701 3702SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, 3703 SDValue N1, SDValue N2) { 3704 SDValue Ops[] = { N1, N2 }; 3705 return getNode(Opcode, VTList, Ops, 2); 3706} 3707 3708SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, 3709 SDValue N1, SDValue N2, SDValue N3) { 3710 SDValue Ops[] = { N1, N2, N3 }; 3711 return getNode(Opcode, VTList, Ops, 3); 3712} 3713 3714SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, 3715 SDValue N1, SDValue N2, SDValue N3, 3716 SDValue N4) { 3717 SDValue Ops[] = { N1, N2, N3, N4 }; 3718 return getNode(Opcode, VTList, Ops, 4); 3719} 3720 3721SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, 3722 SDValue N1, SDValue N2, SDValue N3, 3723 SDValue N4, SDValue N5) { 3724 SDValue Ops[] = { N1, N2, N3, N4, N5 }; 3725 return getNode(Opcode, VTList, Ops, 5); 3726} 3727 3728SDVTList SelectionDAG::getVTList(MVT VT) { 3729 return makeVTList(SDNode::getValueTypeList(VT), 1); 3730} 3731 3732SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2) { 3733 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 3734 E = VTList.rend(); I != E; ++I) 3735 if (I->NumVTs == 2 && I->VTs[0] == VT1 && I->VTs[1] == VT2) 3736 return *I; 3737 3738 MVT *Array = Allocator.Allocate<MVT>(2); 3739 Array[0] = VT1; 3740 Array[1] = VT2; 3741 SDVTList Result = makeVTList(Array, 2); 3742 VTList.push_back(Result); 3743 return Result; 3744} 3745 3746SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2, MVT VT3) { 3747 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 3748 E = VTList.rend(); I != E; ++I) 3749 if (I->NumVTs == 3 && I->VTs[0] == VT1 && I->VTs[1] == VT2 && 3750 I->VTs[2] == VT3) 3751 return *I; 3752 3753 MVT *Array = Allocator.Allocate<MVT>(3); 3754 Array[0] = VT1; 3755 Array[1] = VT2; 3756 Array[2] = VT3; 3757 SDVTList Result = makeVTList(Array, 3); 3758 VTList.push_back(Result); 3759 return Result; 3760} 3761 3762SDVTList SelectionDAG::getVTList(const MVT *VTs, unsigned NumVTs) { 3763 switch (NumVTs) { 3764 case 0: assert(0 && "Cannot have nodes without results!"); 3765 case 1: return getVTList(VTs[0]); 3766 case 2: return getVTList(VTs[0], VTs[1]); 3767 case 3: return getVTList(VTs[0], VTs[1], VTs[2]); 3768 default: break; 3769 } 3770 3771 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 3772 E = VTList.rend(); I != E; ++I) { 3773 if (I->NumVTs != NumVTs || VTs[0] != I->VTs[0] || VTs[1] != I->VTs[1]) 3774 continue; 3775 3776 bool NoMatch = false; 3777 for (unsigned i = 2; i != NumVTs; ++i) 3778 if (VTs[i] != I->VTs[i]) { 3779 NoMatch = true; 3780 break; 3781 } 3782 if (!NoMatch) 3783 return *I; 3784 } 3785 3786 MVT *Array = Allocator.Allocate<MVT>(NumVTs); 3787 std::copy(VTs, VTs+NumVTs, Array); 3788 SDVTList Result = makeVTList(Array, NumVTs); 3789 VTList.push_back(Result); 3790 return Result; 3791} 3792 3793 3794/// UpdateNodeOperands - *Mutate* the specified node in-place to have the 3795/// specified operands. If the resultant node already exists in the DAG, 3796/// this does not modify the specified node, instead it returns the node that 3797/// already exists. If the resultant node does not exist in the DAG, the 3798/// input node is returned. As a degenerate case, if you specify the same 3799/// input operands as the node already has, the input node is returned. 3800SDValue SelectionDAG::UpdateNodeOperands(SDValue InN, SDValue Op) { 3801 SDNode *N = InN.getNode(); 3802 assert(N->getNumOperands() == 1 && "Update with wrong number of operands"); 3803 3804 // Check to see if there is no change. 3805 if (Op == N->getOperand(0)) return InN; 3806 3807 // See if the modified node already exists. 3808 void *InsertPos = 0; 3809 if (SDNode *Existing = FindModifiedNodeSlot(N, Op, InsertPos)) 3810 return SDValue(Existing, InN.getResNo()); 3811 3812 // Nope it doesn't. Remove the node from its current place in the maps. 3813 if (InsertPos) 3814 if (!RemoveNodeFromCSEMaps(N)) 3815 InsertPos = 0; 3816 3817 // Now we update the operands. 3818 N->OperandList[0].getVal()->removeUser(0, N); 3819 N->OperandList[0] = Op; 3820 N->OperandList[0].setUser(N); 3821 Op.getNode()->addUser(0, N); 3822 3823 // If this gets put into a CSE map, add it. 3824 if (InsertPos) CSEMap.InsertNode(N, InsertPos); 3825 return InN; 3826} 3827 3828SDValue SelectionDAG:: 3829UpdateNodeOperands(SDValue InN, SDValue Op1, SDValue Op2) { 3830 SDNode *N = InN.getNode(); 3831 assert(N->getNumOperands() == 2 && "Update with wrong number of operands"); 3832 3833 // Check to see if there is no change. 3834 if (Op1 == N->getOperand(0) && Op2 == N->getOperand(1)) 3835 return InN; // No operands changed, just return the input node. 3836 3837 // See if the modified node already exists. 3838 void *InsertPos = 0; 3839 if (SDNode *Existing = FindModifiedNodeSlot(N, Op1, Op2, InsertPos)) 3840 return SDValue(Existing, InN.getResNo()); 3841 3842 // Nope it doesn't. Remove the node from its current place in the maps. 3843 if (InsertPos) 3844 if (!RemoveNodeFromCSEMaps(N)) 3845 InsertPos = 0; 3846 3847 // Now we update the operands. 3848 if (N->OperandList[0] != Op1) { 3849 N->OperandList[0].getVal()->removeUser(0, N); 3850 N->OperandList[0] = Op1; 3851 N->OperandList[0].setUser(N); 3852 Op1.getNode()->addUser(0, N); 3853 } 3854 if (N->OperandList[1] != Op2) { 3855 N->OperandList[1].getVal()->removeUser(1, N); 3856 N->OperandList[1] = Op2; 3857 N->OperandList[1].setUser(N); 3858 Op2.getNode()->addUser(1, N); 3859 } 3860 3861 // If this gets put into a CSE map, add it. 3862 if (InsertPos) CSEMap.InsertNode(N, InsertPos); 3863 return InN; 3864} 3865 3866SDValue SelectionDAG:: 3867UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, SDValue Op3) { 3868 SDValue Ops[] = { Op1, Op2, Op3 }; 3869 return UpdateNodeOperands(N, Ops, 3); 3870} 3871 3872SDValue SelectionDAG:: 3873UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, 3874 SDValue Op3, SDValue Op4) { 3875 SDValue Ops[] = { Op1, Op2, Op3, Op4 }; 3876 return UpdateNodeOperands(N, Ops, 4); 3877} 3878 3879SDValue SelectionDAG:: 3880UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, 3881 SDValue Op3, SDValue Op4, SDValue Op5) { 3882 SDValue Ops[] = { Op1, Op2, Op3, Op4, Op5 }; 3883 return UpdateNodeOperands(N, Ops, 5); 3884} 3885 3886SDValue SelectionDAG:: 3887UpdateNodeOperands(SDValue InN, const SDValue *Ops, unsigned NumOps) { 3888 SDNode *N = InN.getNode(); 3889 assert(N->getNumOperands() == NumOps && 3890 "Update with wrong number of operands"); 3891 3892 // Check to see if there is no change. 3893 bool AnyChange = false; 3894 for (unsigned i = 0; i != NumOps; ++i) { 3895 if (Ops[i] != N->getOperand(i)) { 3896 AnyChange = true; 3897 break; 3898 } 3899 } 3900 3901 // No operands changed, just return the input node. 3902 if (!AnyChange) return InN; 3903 3904 // See if the modified node already exists. 3905 void *InsertPos = 0; 3906 if (SDNode *Existing = FindModifiedNodeSlot(N, Ops, NumOps, InsertPos)) 3907 return SDValue(Existing, InN.getResNo()); 3908 3909 // Nope it doesn't. Remove the node from its current place in the maps. 3910 if (InsertPos) 3911 if (!RemoveNodeFromCSEMaps(N)) 3912 InsertPos = 0; 3913 3914 // Now we update the operands. 3915 for (unsigned i = 0; i != NumOps; ++i) { 3916 if (N->OperandList[i] != Ops[i]) { 3917 N->OperandList[i].getVal()->removeUser(i, N); 3918 N->OperandList[i] = Ops[i]; 3919 N->OperandList[i].setUser(N); 3920 Ops[i].getNode()->addUser(i, N); 3921 } 3922 } 3923 3924 // If this gets put into a CSE map, add it. 3925 if (InsertPos) CSEMap.InsertNode(N, InsertPos); 3926 return InN; 3927} 3928 3929/// DropOperands - Release the operands and set this node to have 3930/// zero operands. 3931void SDNode::DropOperands() { 3932 // Unlike the code in MorphNodeTo that does this, we don't need to 3933 // watch for dead nodes here. 3934 for (op_iterator I = op_begin(), E = op_end(); I != E; ++I) 3935 I->getVal()->removeUser(std::distance(op_begin(), I), this); 3936 3937 NumOperands = 0; 3938} 3939 3940/// SelectNodeTo - These are wrappers around MorphNodeTo that accept a 3941/// machine opcode. 3942/// 3943SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 3944 MVT VT) { 3945 SDVTList VTs = getVTList(VT); 3946 return SelectNodeTo(N, MachineOpc, VTs, 0, 0); 3947} 3948 3949SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 3950 MVT VT, SDValue Op1) { 3951 SDVTList VTs = getVTList(VT); 3952 SDValue Ops[] = { Op1 }; 3953 return SelectNodeTo(N, MachineOpc, VTs, Ops, 1); 3954} 3955 3956SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 3957 MVT VT, SDValue Op1, 3958 SDValue Op2) { 3959 SDVTList VTs = getVTList(VT); 3960 SDValue Ops[] = { Op1, Op2 }; 3961 return SelectNodeTo(N, MachineOpc, VTs, Ops, 2); 3962} 3963 3964SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 3965 MVT VT, SDValue Op1, 3966 SDValue Op2, SDValue Op3) { 3967 SDVTList VTs = getVTList(VT); 3968 SDValue Ops[] = { Op1, Op2, Op3 }; 3969 return SelectNodeTo(N, MachineOpc, VTs, Ops, 3); 3970} 3971 3972SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 3973 MVT VT, const SDValue *Ops, 3974 unsigned NumOps) { 3975 SDVTList VTs = getVTList(VT); 3976 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 3977} 3978 3979SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 3980 MVT VT1, MVT VT2, const SDValue *Ops, 3981 unsigned NumOps) { 3982 SDVTList VTs = getVTList(VT1, VT2); 3983 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 3984} 3985 3986SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 3987 MVT VT1, MVT VT2) { 3988 SDVTList VTs = getVTList(VT1, VT2); 3989 return SelectNodeTo(N, MachineOpc, VTs, (SDValue *)0, 0); 3990} 3991 3992SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 3993 MVT VT1, MVT VT2, MVT VT3, 3994 const SDValue *Ops, unsigned NumOps) { 3995 SDVTList VTs = getVTList(VT1, VT2, VT3); 3996 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 3997} 3998 3999SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4000 MVT VT1, MVT VT2, 4001 SDValue Op1) { 4002 SDVTList VTs = getVTList(VT1, VT2); 4003 SDValue Ops[] = { Op1 }; 4004 return SelectNodeTo(N, MachineOpc, VTs, Ops, 1); 4005} 4006 4007SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4008 MVT VT1, MVT VT2, 4009 SDValue Op1, SDValue Op2) { 4010 SDVTList VTs = getVTList(VT1, VT2); 4011 SDValue Ops[] = { Op1, Op2 }; 4012 return SelectNodeTo(N, MachineOpc, VTs, Ops, 2); 4013} 4014 4015SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4016 MVT VT1, MVT VT2, 4017 SDValue Op1, SDValue Op2, 4018 SDValue Op3) { 4019 SDVTList VTs = getVTList(VT1, VT2); 4020 SDValue Ops[] = { Op1, Op2, Op3 }; 4021 return SelectNodeTo(N, MachineOpc, VTs, Ops, 3); 4022} 4023 4024SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4025 SDVTList VTs, const SDValue *Ops, 4026 unsigned NumOps) { 4027 return MorphNodeTo(N, ~MachineOpc, VTs, Ops, NumOps); 4028} 4029 4030SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4031 MVT VT) { 4032 SDVTList VTs = getVTList(VT); 4033 return MorphNodeTo(N, Opc, VTs, 0, 0); 4034} 4035 4036SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4037 MVT VT, SDValue Op1) { 4038 SDVTList VTs = getVTList(VT); 4039 SDValue Ops[] = { Op1 }; 4040 return MorphNodeTo(N, Opc, VTs, Ops, 1); 4041} 4042 4043SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4044 MVT VT, SDValue Op1, 4045 SDValue Op2) { 4046 SDVTList VTs = getVTList(VT); 4047 SDValue Ops[] = { Op1, Op2 }; 4048 return MorphNodeTo(N, Opc, VTs, Ops, 2); 4049} 4050 4051SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4052 MVT VT, SDValue Op1, 4053 SDValue Op2, SDValue Op3) { 4054 SDVTList VTs = getVTList(VT); 4055 SDValue Ops[] = { Op1, Op2, Op3 }; 4056 return MorphNodeTo(N, Opc, VTs, Ops, 3); 4057} 4058 4059SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4060 MVT VT, const SDValue *Ops, 4061 unsigned NumOps) { 4062 SDVTList VTs = getVTList(VT); 4063 return MorphNodeTo(N, Opc, VTs, Ops, NumOps); 4064} 4065 4066SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4067 MVT VT1, MVT VT2, const SDValue *Ops, 4068 unsigned NumOps) { 4069 SDVTList VTs = getVTList(VT1, VT2); 4070 return MorphNodeTo(N, Opc, VTs, Ops, NumOps); 4071} 4072 4073SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4074 MVT VT1, MVT VT2) { 4075 SDVTList VTs = getVTList(VT1, VT2); 4076 return MorphNodeTo(N, Opc, VTs, (SDValue *)0, 0); 4077} 4078 4079SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4080 MVT VT1, MVT VT2, MVT VT3, 4081 const SDValue *Ops, unsigned NumOps) { 4082 SDVTList VTs = getVTList(VT1, VT2, VT3); 4083 return MorphNodeTo(N, Opc, VTs, Ops, NumOps); 4084} 4085 4086SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4087 MVT VT1, MVT VT2, 4088 SDValue Op1) { 4089 SDVTList VTs = getVTList(VT1, VT2); 4090 SDValue Ops[] = { Op1 }; 4091 return MorphNodeTo(N, Opc, VTs, Ops, 1); 4092} 4093 4094SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4095 MVT VT1, MVT VT2, 4096 SDValue Op1, SDValue Op2) { 4097 SDVTList VTs = getVTList(VT1, VT2); 4098 SDValue Ops[] = { Op1, Op2 }; 4099 return MorphNodeTo(N, Opc, VTs, Ops, 2); 4100} 4101 4102SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4103 MVT VT1, MVT VT2, 4104 SDValue Op1, SDValue Op2, 4105 SDValue Op3) { 4106 SDVTList VTs = getVTList(VT1, VT2); 4107 SDValue Ops[] = { Op1, Op2, Op3 }; 4108 return MorphNodeTo(N, Opc, VTs, Ops, 3); 4109} 4110 4111/// MorphNodeTo - These *mutate* the specified node to have the specified 4112/// return type, opcode, and operands. 4113/// 4114/// Note that MorphNodeTo returns the resultant node. If there is already a 4115/// node of the specified opcode and operands, it returns that node instead of 4116/// the current one. 4117/// 4118/// Using MorphNodeTo is faster than creating a new node and swapping it in 4119/// with ReplaceAllUsesWith both because it often avoids allocating a new 4120/// node, and because it doesn't require CSE recalculation for any of 4121/// the node's users. 4122/// 4123SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4124 SDVTList VTs, const SDValue *Ops, 4125 unsigned NumOps) { 4126 // If an identical node already exists, use it. 4127 void *IP = 0; 4128 if (VTs.VTs[VTs.NumVTs-1] != MVT::Flag) { 4129 FoldingSetNodeID ID; 4130 AddNodeIDNode(ID, Opc, VTs, Ops, NumOps); 4131 if (SDNode *ON = CSEMap.FindNodeOrInsertPos(ID, IP)) 4132 return ON; 4133 } 4134 4135 if (!RemoveNodeFromCSEMaps(N)) 4136 IP = 0; 4137 4138 // Start the morphing. 4139 N->NodeType = Opc; 4140 N->ValueList = VTs.VTs; 4141 N->NumValues = VTs.NumVTs; 4142 4143 // Clear the operands list, updating used nodes to remove this from their 4144 // use list. Keep track of any operands that become dead as a result. 4145 SmallPtrSet<SDNode*, 16> DeadNodeSet; 4146 for (SDNode::op_iterator B = N->op_begin(), I = B, E = N->op_end(); 4147 I != E; ++I) { 4148 SDNode *Used = I->getVal(); 4149 Used->removeUser(std::distance(B, I), N); 4150 if (Used->use_empty()) 4151 DeadNodeSet.insert(Used); 4152 } 4153 4154 // If NumOps is larger than the # of operands we currently have, reallocate 4155 // the operand list. 4156 if (NumOps > N->NumOperands) { 4157 if (N->OperandsNeedDelete) 4158 delete[] N->OperandList; 4159 if (N->isMachineOpcode()) { 4160 // We're creating a final node that will live unmorphed for the 4161 // remainder of the current SelectionDAG iteration, so we can allocate 4162 // the operands directly out of a pool with no recycling metadata. 4163 N->OperandList = OperandAllocator.Allocate<SDUse>(NumOps); 4164 N->OperandsNeedDelete = false; 4165 } else { 4166 N->OperandList = new SDUse[NumOps]; 4167 N->OperandsNeedDelete = true; 4168 } 4169 } 4170 4171 // Assign the new operands. 4172 N->NumOperands = NumOps; 4173 for (unsigned i = 0, e = NumOps; i != e; ++i) { 4174 N->OperandList[i] = Ops[i]; 4175 N->OperandList[i].setUser(N); 4176 SDNode *ToUse = N->OperandList[i].getVal(); 4177 ToUse->addUser(i, N); 4178 } 4179 4180 // Delete any nodes that are still dead after adding the uses for the 4181 // new operands. 4182 SmallVector<SDNode *, 16> DeadNodes; 4183 for (SmallPtrSet<SDNode *, 16>::iterator I = DeadNodeSet.begin(), 4184 E = DeadNodeSet.end(); I != E; ++I) 4185 if ((*I)->use_empty()) 4186 DeadNodes.push_back(*I); 4187 RemoveDeadNodes(DeadNodes); 4188 4189 if (IP) 4190 CSEMap.InsertNode(N, IP); // Memoize the new node. 4191 return N; 4192} 4193 4194 4195/// getTargetNode - These are used for target selectors to create a new node 4196/// with specified return type(s), target opcode, and operands. 4197/// 4198/// Note that getTargetNode returns the resultant node. If there is already a 4199/// node of the specified opcode and operands, it returns that node instead of 4200/// the current one. 4201SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT) { 4202 return getNode(~Opcode, VT).getNode(); 4203} 4204SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT, SDValue Op1) { 4205 return getNode(~Opcode, VT, Op1).getNode(); 4206} 4207SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT, 4208 SDValue Op1, SDValue Op2) { 4209 return getNode(~Opcode, VT, Op1, Op2).getNode(); 4210} 4211SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT, 4212 SDValue Op1, SDValue Op2, 4213 SDValue Op3) { 4214 return getNode(~Opcode, VT, Op1, Op2, Op3).getNode(); 4215} 4216SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT, 4217 const SDValue *Ops, unsigned NumOps) { 4218 return getNode(~Opcode, VT, Ops, NumOps).getNode(); 4219} 4220SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2) { 4221 const MVT *VTs = getNodeValueTypes(VT1, VT2); 4222 SDValue Op; 4223 return getNode(~Opcode, VTs, 2, &Op, 0).getNode(); 4224} 4225SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, 4226 MVT VT2, SDValue Op1) { 4227 const MVT *VTs = getNodeValueTypes(VT1, VT2); 4228 return getNode(~Opcode, VTs, 2, &Op1, 1).getNode(); 4229} 4230SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, 4231 MVT VT2, SDValue Op1, 4232 SDValue Op2) { 4233 const MVT *VTs = getNodeValueTypes(VT1, VT2); 4234 SDValue Ops[] = { Op1, Op2 }; 4235 return getNode(~Opcode, VTs, 2, Ops, 2).getNode(); 4236} 4237SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, 4238 MVT VT2, SDValue Op1, 4239 SDValue Op2, SDValue Op3) { 4240 const MVT *VTs = getNodeValueTypes(VT1, VT2); 4241 SDValue Ops[] = { Op1, Op2, Op3 }; 4242 return getNode(~Opcode, VTs, 2, Ops, 3).getNode(); 4243} 4244SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, 4245 const SDValue *Ops, unsigned NumOps) { 4246 const MVT *VTs = getNodeValueTypes(VT1, VT2); 4247 return getNode(~Opcode, VTs, 2, Ops, NumOps).getNode(); 4248} 4249SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3, 4250 SDValue Op1, SDValue Op2) { 4251 const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3); 4252 SDValue Ops[] = { Op1, Op2 }; 4253 return getNode(~Opcode, VTs, 3, Ops, 2).getNode(); 4254} 4255SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3, 4256 SDValue Op1, SDValue Op2, 4257 SDValue Op3) { 4258 const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3); 4259 SDValue Ops[] = { Op1, Op2, Op3 }; 4260 return getNode(~Opcode, VTs, 3, Ops, 3).getNode(); 4261} 4262SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3, 4263 const SDValue *Ops, unsigned NumOps) { 4264 const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3); 4265 return getNode(~Opcode, VTs, 3, Ops, NumOps).getNode(); 4266} 4267SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, 4268 MVT VT2, MVT VT3, MVT VT4, 4269 const SDValue *Ops, unsigned NumOps) { 4270 std::vector<MVT> VTList; 4271 VTList.push_back(VT1); 4272 VTList.push_back(VT2); 4273 VTList.push_back(VT3); 4274 VTList.push_back(VT4); 4275 const MVT *VTs = getNodeValueTypes(VTList); 4276 return getNode(~Opcode, VTs, 4, Ops, NumOps).getNode(); 4277} 4278SDNode *SelectionDAG::getTargetNode(unsigned Opcode, 4279 const std::vector<MVT> &ResultTys, 4280 const SDValue *Ops, unsigned NumOps) { 4281 const MVT *VTs = getNodeValueTypes(ResultTys); 4282 return getNode(~Opcode, VTs, ResultTys.size(), 4283 Ops, NumOps).getNode(); 4284} 4285 4286/// getNodeIfExists - Get the specified node if it's already available, or 4287/// else return NULL. 4288SDNode *SelectionDAG::getNodeIfExists(unsigned Opcode, SDVTList VTList, 4289 const SDValue *Ops, unsigned NumOps) { 4290 if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) { 4291 FoldingSetNodeID ID; 4292 AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps); 4293 void *IP = 0; 4294 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 4295 return E; 4296 } 4297 return NULL; 4298} 4299 4300 4301/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. 4302/// This can cause recursive merging of nodes in the DAG. 4303/// 4304/// This version assumes From has a single result value. 4305/// 4306void SelectionDAG::ReplaceAllUsesWith(SDValue FromN, SDValue To, 4307 DAGUpdateListener *UpdateListener) { 4308 SDNode *From = FromN.getNode(); 4309 assert(From->getNumValues() == 1 && FromN.getResNo() == 0 && 4310 "Cannot replace with this method!"); 4311 assert(From != To.getNode() && "Cannot replace uses of with self"); 4312 4313 while (!From->use_empty()) { 4314 SDNode::use_iterator UI = From->use_begin(); 4315 SDNode *U = *UI; 4316 4317 // This node is about to morph, remove its old self from the CSE maps. 4318 RemoveNodeFromCSEMaps(U); 4319 int operandNum = 0; 4320 for (SDNode::op_iterator I = U->op_begin(), E = U->op_end(); 4321 I != E; ++I, ++operandNum) 4322 if (I->getVal() == From) { 4323 From->removeUser(operandNum, U); 4324 *I = To; 4325 I->setUser(U); 4326 To.getNode()->addUser(operandNum, U); 4327 } 4328 4329 // Now that we have modified U, add it back to the CSE maps. If it already 4330 // exists there, recursively merge the results together. 4331 if (SDNode *Existing = AddNonLeafNodeToCSEMaps(U)) { 4332 ReplaceAllUsesWith(U, Existing, UpdateListener); 4333 // U is now dead. Inform the listener if it exists and delete it. 4334 if (UpdateListener) 4335 UpdateListener->NodeDeleted(U, Existing); 4336 DeleteNodeNotInCSEMaps(U); 4337 } else { 4338 // If the node doesn't already exist, we updated it. Inform a listener if 4339 // it exists. 4340 if (UpdateListener) 4341 UpdateListener->NodeUpdated(U); 4342 } 4343 } 4344} 4345 4346/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. 4347/// This can cause recursive merging of nodes in the DAG. 4348/// 4349/// This version assumes From/To have matching types and numbers of result 4350/// values. 4351/// 4352void SelectionDAG::ReplaceAllUsesWith(SDNode *From, SDNode *To, 4353 DAGUpdateListener *UpdateListener) { 4354 assert(From->getVTList().VTs == To->getVTList().VTs && 4355 From->getNumValues() == To->getNumValues() && 4356 "Cannot use this version of ReplaceAllUsesWith!"); 4357 4358 // Handle the trivial case. 4359 if (From == To) 4360 return; 4361 4362 while (!From->use_empty()) { 4363 SDNode::use_iterator UI = From->use_begin(); 4364 SDNode *U = *UI; 4365 4366 // This node is about to morph, remove its old self from the CSE maps. 4367 RemoveNodeFromCSEMaps(U); 4368 int operandNum = 0; 4369 for (SDNode::op_iterator I = U->op_begin(), E = U->op_end(); 4370 I != E; ++I, ++operandNum) 4371 if (I->getVal() == From) { 4372 From->removeUser(operandNum, U); 4373 I->getSDValue().setNode(To); 4374 To->addUser(operandNum, U); 4375 } 4376 4377 // Now that we have modified U, add it back to the CSE maps. If it already 4378 // exists there, recursively merge the results together. 4379 if (SDNode *Existing = AddNonLeafNodeToCSEMaps(U)) { 4380 ReplaceAllUsesWith(U, Existing, UpdateListener); 4381 // U is now dead. Inform the listener if it exists and delete it. 4382 if (UpdateListener) 4383 UpdateListener->NodeDeleted(U, Existing); 4384 DeleteNodeNotInCSEMaps(U); 4385 } else { 4386 // If the node doesn't already exist, we updated it. Inform a listener if 4387 // it exists. 4388 if (UpdateListener) 4389 UpdateListener->NodeUpdated(U); 4390 } 4391 } 4392} 4393 4394/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. 4395/// This can cause recursive merging of nodes in the DAG. 4396/// 4397/// This version can replace From with any result values. To must match the 4398/// number and types of values returned by From. 4399void SelectionDAG::ReplaceAllUsesWith(SDNode *From, 4400 const SDValue *To, 4401 DAGUpdateListener *UpdateListener) { 4402 if (From->getNumValues() == 1) // Handle the simple case efficiently. 4403 return ReplaceAllUsesWith(SDValue(From, 0), To[0], UpdateListener); 4404 4405 while (!From->use_empty()) { 4406 SDNode::use_iterator UI = From->use_begin(); 4407 SDNode *U = *UI; 4408 4409 // This node is about to morph, remove its old self from the CSE maps. 4410 RemoveNodeFromCSEMaps(U); 4411 int operandNum = 0; 4412 for (SDNode::op_iterator I = U->op_begin(), E = U->op_end(); 4413 I != E; ++I, ++operandNum) 4414 if (I->getVal() == From) { 4415 const SDValue &ToOp = To[I->getSDValue().getResNo()]; 4416 From->removeUser(operandNum, U); 4417 *I = ToOp; 4418 I->setUser(U); 4419 ToOp.getNode()->addUser(operandNum, U); 4420 } 4421 4422 // Now that we have modified U, add it back to the CSE maps. If it already 4423 // exists there, recursively merge the results together. 4424 if (SDNode *Existing = AddNonLeafNodeToCSEMaps(U)) { 4425 ReplaceAllUsesWith(U, Existing, UpdateListener); 4426 // U is now dead. Inform the listener if it exists and delete it. 4427 if (UpdateListener) 4428 UpdateListener->NodeDeleted(U, Existing); 4429 DeleteNodeNotInCSEMaps(U); 4430 } else { 4431 // If the node doesn't already exist, we updated it. Inform a listener if 4432 // it exists. 4433 if (UpdateListener) 4434 UpdateListener->NodeUpdated(U); 4435 } 4436 } 4437} 4438 4439/// ReplaceAllUsesOfValueWith - Replace any uses of From with To, leaving 4440/// uses of other values produced by From.getVal() alone. The Deleted vector is 4441/// handled the same way as for ReplaceAllUsesWith. 4442void SelectionDAG::ReplaceAllUsesOfValueWith(SDValue From, SDValue To, 4443 DAGUpdateListener *UpdateListener){ 4444 // Handle the really simple, really trivial case efficiently. 4445 if (From == To) return; 4446 4447 // Handle the simple, trivial, case efficiently. 4448 if (From.getNode()->getNumValues() == 1) { 4449 ReplaceAllUsesWith(From, To, UpdateListener); 4450 return; 4451 } 4452 4453 // Get all of the users of From.getNode(). We want these in a nice, 4454 // deterministically ordered and uniqued set, so we use a SmallSetVector. 4455 SmallSetVector<SDNode*, 16> Users(From.getNode()->use_begin(), From.getNode()->use_end()); 4456 4457 while (!Users.empty()) { 4458 // We know that this user uses some value of From. If it is the right 4459 // value, update it. 4460 SDNode *User = Users.back(); 4461 Users.pop_back(); 4462 4463 // Scan for an operand that matches From. 4464 SDNode::op_iterator Op = User->op_begin(), E = User->op_end(); 4465 for (; Op != E; ++Op) 4466 if (*Op == From) break; 4467 4468 // If there are no matches, the user must use some other result of From. 4469 if (Op == E) continue; 4470 4471 // Okay, we know this user needs to be updated. Remove its old self 4472 // from the CSE maps. 4473 RemoveNodeFromCSEMaps(User); 4474 4475 // Update all operands that match "From" in case there are multiple uses. 4476 for (; Op != E; ++Op) { 4477 if (*Op == From) { 4478 From.getNode()->removeUser(Op-User->op_begin(), User); 4479 *Op = To; 4480 Op->setUser(User); 4481 To.getNode()->addUser(Op-User->op_begin(), User); 4482 } 4483 } 4484 4485 // Now that we have modified User, add it back to the CSE maps. If it 4486 // already exists there, recursively merge the results together. 4487 SDNode *Existing = AddNonLeafNodeToCSEMaps(User); 4488 if (!Existing) { 4489 if (UpdateListener) UpdateListener->NodeUpdated(User); 4490 continue; // Continue on to next user. 4491 } 4492 4493 // If there was already an existing matching node, use ReplaceAllUsesWith 4494 // to replace the dead one with the existing one. This can cause 4495 // recursive merging of other unrelated nodes down the line. 4496 ReplaceAllUsesWith(User, Existing, UpdateListener); 4497 4498 // User is now dead. Notify a listener if present. 4499 if (UpdateListener) UpdateListener->NodeDeleted(User, Existing); 4500 DeleteNodeNotInCSEMaps(User); 4501 } 4502} 4503 4504/// ReplaceAllUsesOfValuesWith - Replace any uses of From with To, leaving 4505/// uses of other values produced by From.getVal() alone. The same value may 4506/// appear in both the From and To list. The Deleted vector is 4507/// handled the same way as for ReplaceAllUsesWith. 4508void SelectionDAG::ReplaceAllUsesOfValuesWith(const SDValue *From, 4509 const SDValue *To, 4510 unsigned Num, 4511 DAGUpdateListener *UpdateListener){ 4512 // Handle the simple, trivial case efficiently. 4513 if (Num == 1) 4514 return ReplaceAllUsesOfValueWith(*From, *To, UpdateListener); 4515 4516 SmallVector<std::pair<SDNode *, unsigned>, 16> Users; 4517 for (unsigned i = 0; i != Num; ++i) 4518 for (SDNode::use_iterator UI = From[i].getNode()->use_begin(), 4519 E = From[i].getNode()->use_end(); UI != E; ++UI) 4520 Users.push_back(std::make_pair(*UI, i)); 4521 4522 while (!Users.empty()) { 4523 // We know that this user uses some value of From. If it is the right 4524 // value, update it. 4525 SDNode *User = Users.back().first; 4526 unsigned i = Users.back().second; 4527 Users.pop_back(); 4528 4529 // Scan for an operand that matches From. 4530 SDNode::op_iterator Op = User->op_begin(), E = User->op_end(); 4531 for (; Op != E; ++Op) 4532 if (*Op == From[i]) break; 4533 4534 // If there are no matches, the user must use some other result of From. 4535 if (Op == E) continue; 4536 4537 // Okay, we know this user needs to be updated. Remove its old self 4538 // from the CSE maps. 4539 RemoveNodeFromCSEMaps(User); 4540 4541 // Update all operands that match "From" in case there are multiple uses. 4542 for (; Op != E; ++Op) { 4543 if (*Op == From[i]) { 4544 From[i].getNode()->removeUser(Op-User->op_begin(), User); 4545 *Op = To[i]; 4546 Op->setUser(User); 4547 To[i].getNode()->addUser(Op-User->op_begin(), User); 4548 } 4549 } 4550 4551 // Now that we have modified User, add it back to the CSE maps. If it 4552 // already exists there, recursively merge the results together. 4553 SDNode *Existing = AddNonLeafNodeToCSEMaps(User); 4554 if (!Existing) { 4555 if (UpdateListener) UpdateListener->NodeUpdated(User); 4556 continue; // Continue on to next user. 4557 } 4558 4559 // If there was already an existing matching node, use ReplaceAllUsesWith 4560 // to replace the dead one with the existing one. This can cause 4561 // recursive merging of other unrelated nodes down the line. 4562 ReplaceAllUsesWith(User, Existing, UpdateListener); 4563 4564 // User is now dead. Notify a listener if present. 4565 if (UpdateListener) UpdateListener->NodeDeleted(User, Existing); 4566 DeleteNodeNotInCSEMaps(User); 4567 } 4568} 4569 4570/// AssignTopologicalOrder - Assign a unique node id for each node in the DAG 4571/// based on their topological order. It returns the maximum id and a vector 4572/// of the SDNodes* in assigned order by reference. 4573unsigned SelectionDAG::AssignTopologicalOrder() { 4574 4575 unsigned DAGSize = 0; 4576 4577 // SortedPos tracks the progress of the algorithm. Nodes before it are 4578 // sorted, nodes after it are unsorted. When the algorithm completes 4579 // it is at the end of the list. 4580 allnodes_iterator SortedPos = allnodes_begin(); 4581 4582 // Visit all the nodes. Add nodes with no operands to the TopOrder result 4583 // array immediately. Annotate nodes that do have operands with their 4584 // operand count. Before we do this, the Node Id fields of the nodes 4585 // may contain arbitrary values. After, the Node Id fields for nodes 4586 // before SortedPos will contain the topological sort index, and the 4587 // Node Id fields for nodes At SortedPos and after will contain the 4588 // count of outstanding operands. 4589 for (allnodes_iterator I = allnodes_begin(),E = allnodes_end(); I != E; ) { 4590 SDNode *N = I++; 4591 unsigned Degree = N->getNumOperands(); 4592 if (Degree == 0) { 4593 // A node with no uses, add it to the result array immediately. 4594 N->setNodeId(DAGSize++); 4595 allnodes_iterator Q = N; 4596 if (Q != SortedPos) 4597 SortedPos = AllNodes.insert(SortedPos, AllNodes.remove(Q)); 4598 ++SortedPos; 4599 } else { 4600 // Temporarily use the Node Id as scratch space for the degree count. 4601 N->setNodeId(Degree); 4602 } 4603 } 4604 4605 // Visit all the nodes. As we iterate, moves nodes into sorted order, 4606 // such that by the time the end is reached all nodes will be sorted. 4607 for (allnodes_iterator I = allnodes_begin(),E = allnodes_end(); I != E; ++I) { 4608 SDNode *N = I; 4609 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 4610 UI != UE; ++UI) { 4611 SDNode *P = *UI; 4612 unsigned Degree = P->getNodeId(); 4613 --Degree; 4614 if (Degree == 0) { 4615 // All of P's operands are sorted, so P may sorted now. 4616 P->setNodeId(DAGSize++); 4617 if (P != SortedPos) 4618 SortedPos = AllNodes.insert(SortedPos, AllNodes.remove(P)); 4619 ++SortedPos; 4620 } else { 4621 // Update P's outstanding operand count. 4622 P->setNodeId(Degree); 4623 } 4624 } 4625 } 4626 4627 assert(SortedPos == AllNodes.end() && 4628 "Topological sort incomplete!"); 4629 assert(AllNodes.front().getOpcode() == ISD::EntryToken && 4630 "First node in topological sort is not the entry token!"); 4631 assert(AllNodes.front().getNodeId() == 0 && 4632 "First node in topological sort has non-zero id!"); 4633 assert(AllNodes.front().getNumOperands() == 0 && 4634 "First node in topological sort has operands!"); 4635 assert(AllNodes.back().getNodeId() == (int)DAGSize-1 && 4636 "Last node in topologic sort has unexpected id!"); 4637 assert(AllNodes.back().use_empty() && 4638 "Last node in topologic sort has users!"); 4639 assert(DAGSize == allnodes_size() && "TopOrder result count mismatch!"); 4640 return DAGSize; 4641} 4642 4643 4644 4645//===----------------------------------------------------------------------===// 4646// SDNode Class 4647//===----------------------------------------------------------------------===// 4648 4649// Out-of-line virtual method to give class a home. 4650void SDNode::ANCHOR() {} 4651void UnarySDNode::ANCHOR() {} 4652void BinarySDNode::ANCHOR() {} 4653void TernarySDNode::ANCHOR() {} 4654void HandleSDNode::ANCHOR() {} 4655void ConstantSDNode::ANCHOR() {} 4656void ConstantFPSDNode::ANCHOR() {} 4657void GlobalAddressSDNode::ANCHOR() {} 4658void FrameIndexSDNode::ANCHOR() {} 4659void JumpTableSDNode::ANCHOR() {} 4660void ConstantPoolSDNode::ANCHOR() {} 4661void BasicBlockSDNode::ANCHOR() {} 4662void SrcValueSDNode::ANCHOR() {} 4663void MemOperandSDNode::ANCHOR() {} 4664void RegisterSDNode::ANCHOR() {} 4665void DbgStopPointSDNode::ANCHOR() {} 4666void LabelSDNode::ANCHOR() {} 4667void ExternalSymbolSDNode::ANCHOR() {} 4668void CondCodeSDNode::ANCHOR() {} 4669void ARG_FLAGSSDNode::ANCHOR() {} 4670void VTSDNode::ANCHOR() {} 4671void MemSDNode::ANCHOR() {} 4672void LoadSDNode::ANCHOR() {} 4673void StoreSDNode::ANCHOR() {} 4674void AtomicSDNode::ANCHOR() {} 4675void CallSDNode::ANCHOR() {} 4676 4677HandleSDNode::~HandleSDNode() { 4678 DropOperands(); 4679} 4680 4681GlobalAddressSDNode::GlobalAddressSDNode(bool isTarget, const GlobalValue *GA, 4682 MVT VT, int o) 4683 : SDNode(isa<GlobalVariable>(GA) && 4684 cast<GlobalVariable>(GA)->isThreadLocal() ? 4685 // Thread Local 4686 (isTarget ? ISD::TargetGlobalTLSAddress : ISD::GlobalTLSAddress) : 4687 // Non Thread Local 4688 (isTarget ? ISD::TargetGlobalAddress : ISD::GlobalAddress), 4689 getSDVTList(VT)), Offset(o) { 4690 TheGlobal = const_cast<GlobalValue*>(GA); 4691} 4692 4693MemSDNode::MemSDNode(unsigned Opc, SDVTList VTs, MVT memvt, 4694 const Value *srcValue, int SVO, 4695 unsigned alignment, bool vol) 4696 : SDNode(Opc, VTs), MemoryVT(memvt), SrcValue(srcValue), SVOffset(SVO), 4697 Flags(encodeMemSDNodeFlags(vol, alignment)) { 4698 4699 assert(isPowerOf2_32(alignment) && "Alignment is not a power of 2!"); 4700 assert(getAlignment() == alignment && "Alignment representation error!"); 4701 assert(isVolatile() == vol && "Volatile representation error!"); 4702} 4703 4704/// getMemOperand - Return a MachineMemOperand object describing the memory 4705/// reference performed by this memory reference. 4706MachineMemOperand MemSDNode::getMemOperand() const { 4707 int Flags; 4708 if (isa<LoadSDNode>(this)) 4709 Flags = MachineMemOperand::MOLoad; 4710 else if (isa<StoreSDNode>(this)) 4711 Flags = MachineMemOperand::MOStore; 4712 else { 4713 assert(isa<AtomicSDNode>(this) && "Unknown MemSDNode opcode!"); 4714 Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore; 4715 } 4716 4717 int Size = (getMemoryVT().getSizeInBits() + 7) >> 3; 4718 if (isVolatile()) Flags |= MachineMemOperand::MOVolatile; 4719 4720 // Check if the memory reference references a frame index 4721 const FrameIndexSDNode *FI = 4722 dyn_cast<const FrameIndexSDNode>(getBasePtr().getNode()); 4723 if (!getSrcValue() && FI) 4724 return MachineMemOperand(PseudoSourceValue::getFixedStack(FI->getIndex()), 4725 Flags, 0, Size, getAlignment()); 4726 else 4727 return MachineMemOperand(getSrcValue(), Flags, getSrcValueOffset(), 4728 Size, getAlignment()); 4729} 4730 4731/// Profile - Gather unique data for the node. 4732/// 4733void SDNode::Profile(FoldingSetNodeID &ID) const { 4734 AddNodeIDNode(ID, this); 4735} 4736 4737/// getValueTypeList - Return a pointer to the specified value type. 4738/// 4739const MVT *SDNode::getValueTypeList(MVT VT) { 4740 if (VT.isExtended()) { 4741 static std::set<MVT, MVT::compareRawBits> EVTs; 4742 return &(*EVTs.insert(VT).first); 4743 } else { 4744 static MVT VTs[MVT::LAST_VALUETYPE]; 4745 VTs[VT.getSimpleVT()] = VT; 4746 return &VTs[VT.getSimpleVT()]; 4747 } 4748} 4749 4750/// hasNUsesOfValue - Return true if there are exactly NUSES uses of the 4751/// indicated value. This method ignores uses of other values defined by this 4752/// operation. 4753bool SDNode::hasNUsesOfValue(unsigned NUses, unsigned Value) const { 4754 assert(Value < getNumValues() && "Bad value!"); 4755 4756 // TODO: Only iterate over uses of a given value of the node 4757 for (SDNode::use_iterator UI = use_begin(), E = use_end(); UI != E; ++UI) { 4758 if (UI.getUse().getSDValue().getResNo() == Value) { 4759 if (NUses == 0) 4760 return false; 4761 --NUses; 4762 } 4763 } 4764 4765 // Found exactly the right number of uses? 4766 return NUses == 0; 4767} 4768 4769 4770/// hasAnyUseOfValue - Return true if there are any use of the indicated 4771/// value. This method ignores uses of other values defined by this operation. 4772bool SDNode::hasAnyUseOfValue(unsigned Value) const { 4773 assert(Value < getNumValues() && "Bad value!"); 4774 4775 for (SDNode::use_iterator UI = use_begin(), E = use_end(); UI != E; ++UI) 4776 if (UI.getUse().getSDValue().getResNo() == Value) 4777 return true; 4778 4779 return false; 4780} 4781 4782 4783/// isOnlyUserOf - Return true if this node is the only use of N. 4784/// 4785bool SDNode::isOnlyUserOf(SDNode *N) const { 4786 bool Seen = false; 4787 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 4788 SDNode *User = *I; 4789 if (User == this) 4790 Seen = true; 4791 else 4792 return false; 4793 } 4794 4795 return Seen; 4796} 4797 4798/// isOperand - Return true if this node is an operand of N. 4799/// 4800bool SDValue::isOperandOf(SDNode *N) const { 4801 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 4802 if (*this == N->getOperand(i)) 4803 return true; 4804 return false; 4805} 4806 4807bool SDNode::isOperandOf(SDNode *N) const { 4808 for (unsigned i = 0, e = N->NumOperands; i != e; ++i) 4809 if (this == N->OperandList[i].getVal()) 4810 return true; 4811 return false; 4812} 4813 4814/// reachesChainWithoutSideEffects - Return true if this operand (which must 4815/// be a chain) reaches the specified operand without crossing any 4816/// side-effecting instructions. In practice, this looks through token 4817/// factors and non-volatile loads. In order to remain efficient, this only 4818/// looks a couple of nodes in, it does not do an exhaustive search. 4819bool SDValue::reachesChainWithoutSideEffects(SDValue Dest, 4820 unsigned Depth) const { 4821 if (*this == Dest) return true; 4822 4823 // Don't search too deeply, we just want to be able to see through 4824 // TokenFactor's etc. 4825 if (Depth == 0) return false; 4826 4827 // If this is a token factor, all inputs to the TF happen in parallel. If any 4828 // of the operands of the TF reach dest, then we can do the xform. 4829 if (getOpcode() == ISD::TokenFactor) { 4830 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) 4831 if (getOperand(i).reachesChainWithoutSideEffects(Dest, Depth-1)) 4832 return true; 4833 return false; 4834 } 4835 4836 // Loads don't have side effects, look through them. 4837 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(*this)) { 4838 if (!Ld->isVolatile()) 4839 return Ld->getChain().reachesChainWithoutSideEffects(Dest, Depth-1); 4840 } 4841 return false; 4842} 4843 4844 4845static void findPredecessor(SDNode *N, const SDNode *P, bool &found, 4846 SmallPtrSet<SDNode *, 32> &Visited) { 4847 if (found || !Visited.insert(N)) 4848 return; 4849 4850 for (unsigned i = 0, e = N->getNumOperands(); !found && i != e; ++i) { 4851 SDNode *Op = N->getOperand(i).getNode(); 4852 if (Op == P) { 4853 found = true; 4854 return; 4855 } 4856 findPredecessor(Op, P, found, Visited); 4857 } 4858} 4859 4860/// isPredecessorOf - Return true if this node is a predecessor of N. This node 4861/// is either an operand of N or it can be reached by recursively traversing 4862/// up the operands. 4863/// NOTE: this is an expensive method. Use it carefully. 4864bool SDNode::isPredecessorOf(SDNode *N) const { 4865 SmallPtrSet<SDNode *, 32> Visited; 4866 bool found = false; 4867 findPredecessor(N, this, found, Visited); 4868 return found; 4869} 4870 4871uint64_t SDNode::getConstantOperandVal(unsigned Num) const { 4872 assert(Num < NumOperands && "Invalid child # of SDNode!"); 4873 return cast<ConstantSDNode>(OperandList[Num])->getZExtValue(); 4874} 4875 4876std::string SDNode::getOperationName(const SelectionDAG *G) const { 4877 switch (getOpcode()) { 4878 default: 4879 if (getOpcode() < ISD::BUILTIN_OP_END) 4880 return "<<Unknown DAG Node>>"; 4881 if (isMachineOpcode()) { 4882 if (G) 4883 if (const TargetInstrInfo *TII = G->getTarget().getInstrInfo()) 4884 if (getMachineOpcode() < TII->getNumOpcodes()) 4885 return TII->get(getMachineOpcode()).getName(); 4886 return "<<Unknown Machine Node>>"; 4887 } 4888 if (G) { 4889 TargetLowering &TLI = G->getTargetLoweringInfo(); 4890 const char *Name = TLI.getTargetNodeName(getOpcode()); 4891 if (Name) return Name; 4892 return "<<Unknown Target Node>>"; 4893 } 4894 return "<<Unknown Node>>"; 4895 4896#ifndef NDEBUG 4897 case ISD::DELETED_NODE: 4898 return "<<Deleted Node!>>"; 4899#endif 4900 case ISD::PREFETCH: return "Prefetch"; 4901 case ISD::MEMBARRIER: return "MemBarrier"; 4902 case ISD::ATOMIC_CMP_SWAP_8: return "AtomicCmpSwap8"; 4903 case ISD::ATOMIC_SWAP_8: return "AtomicSwap8"; 4904 case ISD::ATOMIC_LOAD_ADD_8: return "AtomicLoadAdd8"; 4905 case ISD::ATOMIC_LOAD_SUB_8: return "AtomicLoadSub8"; 4906 case ISD::ATOMIC_LOAD_AND_8: return "AtomicLoadAnd8"; 4907 case ISD::ATOMIC_LOAD_OR_8: return "AtomicLoadOr8"; 4908 case ISD::ATOMIC_LOAD_XOR_8: return "AtomicLoadXor8"; 4909 case ISD::ATOMIC_LOAD_NAND_8: return "AtomicLoadNand8"; 4910 case ISD::ATOMIC_LOAD_MIN_8: return "AtomicLoadMin8"; 4911 case ISD::ATOMIC_LOAD_MAX_8: return "AtomicLoadMax8"; 4912 case ISD::ATOMIC_LOAD_UMIN_8: return "AtomicLoadUMin8"; 4913 case ISD::ATOMIC_LOAD_UMAX_8: return "AtomicLoadUMax8"; 4914 case ISD::ATOMIC_CMP_SWAP_16: return "AtomicCmpSwap16"; 4915 case ISD::ATOMIC_SWAP_16: return "AtomicSwap16"; 4916 case ISD::ATOMIC_LOAD_ADD_16: return "AtomicLoadAdd16"; 4917 case ISD::ATOMIC_LOAD_SUB_16: return "AtomicLoadSub16"; 4918 case ISD::ATOMIC_LOAD_AND_16: return "AtomicLoadAnd16"; 4919 case ISD::ATOMIC_LOAD_OR_16: return "AtomicLoadOr16"; 4920 case ISD::ATOMIC_LOAD_XOR_16: return "AtomicLoadXor16"; 4921 case ISD::ATOMIC_LOAD_NAND_16: return "AtomicLoadNand16"; 4922 case ISD::ATOMIC_LOAD_MIN_16: return "AtomicLoadMin16"; 4923 case ISD::ATOMIC_LOAD_MAX_16: return "AtomicLoadMax16"; 4924 case ISD::ATOMIC_LOAD_UMIN_16: return "AtomicLoadUMin16"; 4925 case ISD::ATOMIC_LOAD_UMAX_16: return "AtomicLoadUMax16"; 4926 case ISD::ATOMIC_CMP_SWAP_32: return "AtomicCmpSwap32"; 4927 case ISD::ATOMIC_SWAP_32: return "AtomicSwap32"; 4928 case ISD::ATOMIC_LOAD_ADD_32: return "AtomicLoadAdd32"; 4929 case ISD::ATOMIC_LOAD_SUB_32: return "AtomicLoadSub32"; 4930 case ISD::ATOMIC_LOAD_AND_32: return "AtomicLoadAnd32"; 4931 case ISD::ATOMIC_LOAD_OR_32: return "AtomicLoadOr32"; 4932 case ISD::ATOMIC_LOAD_XOR_32: return "AtomicLoadXor32"; 4933 case ISD::ATOMIC_LOAD_NAND_32: return "AtomicLoadNand32"; 4934 case ISD::ATOMIC_LOAD_MIN_32: return "AtomicLoadMin32"; 4935 case ISD::ATOMIC_LOAD_MAX_32: return "AtomicLoadMax32"; 4936 case ISD::ATOMIC_LOAD_UMIN_32: return "AtomicLoadUMin32"; 4937 case ISD::ATOMIC_LOAD_UMAX_32: return "AtomicLoadUMax32"; 4938 case ISD::ATOMIC_CMP_SWAP_64: return "AtomicCmpSwap64"; 4939 case ISD::ATOMIC_SWAP_64: return "AtomicSwap64"; 4940 case ISD::ATOMIC_LOAD_ADD_64: return "AtomicLoadAdd64"; 4941 case ISD::ATOMIC_LOAD_SUB_64: return "AtomicLoadSub64"; 4942 case ISD::ATOMIC_LOAD_AND_64: return "AtomicLoadAnd64"; 4943 case ISD::ATOMIC_LOAD_OR_64: return "AtomicLoadOr64"; 4944 case ISD::ATOMIC_LOAD_XOR_64: return "AtomicLoadXor64"; 4945 case ISD::ATOMIC_LOAD_NAND_64: return "AtomicLoadNand64"; 4946 case ISD::ATOMIC_LOAD_MIN_64: return "AtomicLoadMin64"; 4947 case ISD::ATOMIC_LOAD_MAX_64: return "AtomicLoadMax64"; 4948 case ISD::ATOMIC_LOAD_UMIN_64: return "AtomicLoadUMin64"; 4949 case ISD::ATOMIC_LOAD_UMAX_64: return "AtomicLoadUMax64"; 4950 case ISD::PCMARKER: return "PCMarker"; 4951 case ISD::READCYCLECOUNTER: return "ReadCycleCounter"; 4952 case ISD::SRCVALUE: return "SrcValue"; 4953 case ISD::MEMOPERAND: return "MemOperand"; 4954 case ISD::EntryToken: return "EntryToken"; 4955 case ISD::TokenFactor: return "TokenFactor"; 4956 case ISD::AssertSext: return "AssertSext"; 4957 case ISD::AssertZext: return "AssertZext"; 4958 4959 case ISD::BasicBlock: return "BasicBlock"; 4960 case ISD::ARG_FLAGS: return "ArgFlags"; 4961 case ISD::VALUETYPE: return "ValueType"; 4962 case ISD::Register: return "Register"; 4963 4964 case ISD::Constant: return "Constant"; 4965 case ISD::ConstantFP: return "ConstantFP"; 4966 case ISD::GlobalAddress: return "GlobalAddress"; 4967 case ISD::GlobalTLSAddress: return "GlobalTLSAddress"; 4968 case ISD::FrameIndex: return "FrameIndex"; 4969 case ISD::JumpTable: return "JumpTable"; 4970 case ISD::GLOBAL_OFFSET_TABLE: return "GLOBAL_OFFSET_TABLE"; 4971 case ISD::RETURNADDR: return "RETURNADDR"; 4972 case ISD::FRAMEADDR: return "FRAMEADDR"; 4973 case ISD::FRAME_TO_ARGS_OFFSET: return "FRAME_TO_ARGS_OFFSET"; 4974 case ISD::EXCEPTIONADDR: return "EXCEPTIONADDR"; 4975 case ISD::EHSELECTION: return "EHSELECTION"; 4976 case ISD::EH_RETURN: return "EH_RETURN"; 4977 case ISD::ConstantPool: return "ConstantPool"; 4978 case ISD::ExternalSymbol: return "ExternalSymbol"; 4979 case ISD::INTRINSIC_WO_CHAIN: { 4980 unsigned IID = cast<ConstantSDNode>(getOperand(0))->getZExtValue(); 4981 return Intrinsic::getName((Intrinsic::ID)IID); 4982 } 4983 case ISD::INTRINSIC_VOID: 4984 case ISD::INTRINSIC_W_CHAIN: { 4985 unsigned IID = cast<ConstantSDNode>(getOperand(1))->getZExtValue(); 4986 return Intrinsic::getName((Intrinsic::ID)IID); 4987 } 4988 4989 case ISD::BUILD_VECTOR: return "BUILD_VECTOR"; 4990 case ISD::TargetConstant: return "TargetConstant"; 4991 case ISD::TargetConstantFP:return "TargetConstantFP"; 4992 case ISD::TargetGlobalAddress: return "TargetGlobalAddress"; 4993 case ISD::TargetGlobalTLSAddress: return "TargetGlobalTLSAddress"; 4994 case ISD::TargetFrameIndex: return "TargetFrameIndex"; 4995 case ISD::TargetJumpTable: return "TargetJumpTable"; 4996 case ISD::TargetConstantPool: return "TargetConstantPool"; 4997 case ISD::TargetExternalSymbol: return "TargetExternalSymbol"; 4998 4999 case ISD::CopyToReg: return "CopyToReg"; 5000 case ISD::CopyFromReg: return "CopyFromReg"; 5001 case ISD::UNDEF: return "undef"; 5002 case ISD::MERGE_VALUES: return "merge_values"; 5003 case ISD::INLINEASM: return "inlineasm"; 5004 case ISD::DBG_LABEL: return "dbg_label"; 5005 case ISD::EH_LABEL: return "eh_label"; 5006 case ISD::DECLARE: return "declare"; 5007 case ISD::HANDLENODE: return "handlenode"; 5008 case ISD::FORMAL_ARGUMENTS: return "formal_arguments"; 5009 case ISD::CALL: return "call"; 5010 5011 // Unary operators 5012 case ISD::FABS: return "fabs"; 5013 case ISD::FNEG: return "fneg"; 5014 case ISD::FSQRT: return "fsqrt"; 5015 case ISD::FSIN: return "fsin"; 5016 case ISD::FCOS: return "fcos"; 5017 case ISD::FPOWI: return "fpowi"; 5018 case ISD::FPOW: return "fpow"; 5019 case ISD::FTRUNC: return "ftrunc"; 5020 case ISD::FFLOOR: return "ffloor"; 5021 case ISD::FCEIL: return "fceil"; 5022 case ISD::FRINT: return "frint"; 5023 case ISD::FNEARBYINT: return "fnearbyint"; 5024 5025 // Binary operators 5026 case ISD::ADD: return "add"; 5027 case ISD::SUB: return "sub"; 5028 case ISD::MUL: return "mul"; 5029 case ISD::MULHU: return "mulhu"; 5030 case ISD::MULHS: return "mulhs"; 5031 case ISD::SDIV: return "sdiv"; 5032 case ISD::UDIV: return "udiv"; 5033 case ISD::SREM: return "srem"; 5034 case ISD::UREM: return "urem"; 5035 case ISD::SMUL_LOHI: return "smul_lohi"; 5036 case ISD::UMUL_LOHI: return "umul_lohi"; 5037 case ISD::SDIVREM: return "sdivrem"; 5038 case ISD::UDIVREM: return "udivrem"; 5039 case ISD::AND: return "and"; 5040 case ISD::OR: return "or"; 5041 case ISD::XOR: return "xor"; 5042 case ISD::SHL: return "shl"; 5043 case ISD::SRA: return "sra"; 5044 case ISD::SRL: return "srl"; 5045 case ISD::ROTL: return "rotl"; 5046 case ISD::ROTR: return "rotr"; 5047 case ISD::FADD: return "fadd"; 5048 case ISD::FSUB: return "fsub"; 5049 case ISD::FMUL: return "fmul"; 5050 case ISD::FDIV: return "fdiv"; 5051 case ISD::FREM: return "frem"; 5052 case ISD::FCOPYSIGN: return "fcopysign"; 5053 case ISD::FGETSIGN: return "fgetsign"; 5054 5055 case ISD::SETCC: return "setcc"; 5056 case ISD::VSETCC: return "vsetcc"; 5057 case ISD::SELECT: return "select"; 5058 case ISD::SELECT_CC: return "select_cc"; 5059 case ISD::INSERT_VECTOR_ELT: return "insert_vector_elt"; 5060 case ISD::EXTRACT_VECTOR_ELT: return "extract_vector_elt"; 5061 case ISD::CONCAT_VECTORS: return "concat_vectors"; 5062 case ISD::EXTRACT_SUBVECTOR: return "extract_subvector"; 5063 case ISD::SCALAR_TO_VECTOR: return "scalar_to_vector"; 5064 case ISD::VECTOR_SHUFFLE: return "vector_shuffle"; 5065 case ISD::CARRY_FALSE: return "carry_false"; 5066 case ISD::ADDC: return "addc"; 5067 case ISD::ADDE: return "adde"; 5068 case ISD::SUBC: return "subc"; 5069 case ISD::SUBE: return "sube"; 5070 case ISD::SHL_PARTS: return "shl_parts"; 5071 case ISD::SRA_PARTS: return "sra_parts"; 5072 case ISD::SRL_PARTS: return "srl_parts"; 5073 5074 case ISD::EXTRACT_SUBREG: return "extract_subreg"; 5075 case ISD::INSERT_SUBREG: return "insert_subreg"; 5076 5077 // Conversion operators. 5078 case ISD::SIGN_EXTEND: return "sign_extend"; 5079 case ISD::ZERO_EXTEND: return "zero_extend"; 5080 case ISD::ANY_EXTEND: return "any_extend"; 5081 case ISD::SIGN_EXTEND_INREG: return "sign_extend_inreg"; 5082 case ISD::TRUNCATE: return "truncate"; 5083 case ISD::FP_ROUND: return "fp_round"; 5084 case ISD::FLT_ROUNDS_: return "flt_rounds"; 5085 case ISD::FP_ROUND_INREG: return "fp_round_inreg"; 5086 case ISD::FP_EXTEND: return "fp_extend"; 5087 5088 case ISD::SINT_TO_FP: return "sint_to_fp"; 5089 case ISD::UINT_TO_FP: return "uint_to_fp"; 5090 case ISD::FP_TO_SINT: return "fp_to_sint"; 5091 case ISD::FP_TO_UINT: return "fp_to_uint"; 5092 case ISD::BIT_CONVERT: return "bit_convert"; 5093 5094 // Control flow instructions 5095 case ISD::BR: return "br"; 5096 case ISD::BRIND: return "brind"; 5097 case ISD::BR_JT: return "br_jt"; 5098 case ISD::BRCOND: return "brcond"; 5099 case ISD::BR_CC: return "br_cc"; 5100 case ISD::RET: return "ret"; 5101 case ISD::CALLSEQ_START: return "callseq_start"; 5102 case ISD::CALLSEQ_END: return "callseq_end"; 5103 5104 // Other operators 5105 case ISD::LOAD: return "load"; 5106 case ISD::STORE: return "store"; 5107 case ISD::VAARG: return "vaarg"; 5108 case ISD::VACOPY: return "vacopy"; 5109 case ISD::VAEND: return "vaend"; 5110 case ISD::VASTART: return "vastart"; 5111 case ISD::DYNAMIC_STACKALLOC: return "dynamic_stackalloc"; 5112 case ISD::EXTRACT_ELEMENT: return "extract_element"; 5113 case ISD::BUILD_PAIR: return "build_pair"; 5114 case ISD::STACKSAVE: return "stacksave"; 5115 case ISD::STACKRESTORE: return "stackrestore"; 5116 case ISD::TRAP: return "trap"; 5117 5118 // Bit manipulation 5119 case ISD::BSWAP: return "bswap"; 5120 case ISD::CTPOP: return "ctpop"; 5121 case ISD::CTTZ: return "cttz"; 5122 case ISD::CTLZ: return "ctlz"; 5123 5124 // Debug info 5125 case ISD::DBG_STOPPOINT: return "dbg_stoppoint"; 5126 case ISD::DEBUG_LOC: return "debug_loc"; 5127 5128 // Trampolines 5129 case ISD::TRAMPOLINE: return "trampoline"; 5130 5131 case ISD::CONDCODE: 5132 switch (cast<CondCodeSDNode>(this)->get()) { 5133 default: assert(0 && "Unknown setcc condition!"); 5134 case ISD::SETOEQ: return "setoeq"; 5135 case ISD::SETOGT: return "setogt"; 5136 case ISD::SETOGE: return "setoge"; 5137 case ISD::SETOLT: return "setolt"; 5138 case ISD::SETOLE: return "setole"; 5139 case ISD::SETONE: return "setone"; 5140 5141 case ISD::SETO: return "seto"; 5142 case ISD::SETUO: return "setuo"; 5143 case ISD::SETUEQ: return "setue"; 5144 case ISD::SETUGT: return "setugt"; 5145 case ISD::SETUGE: return "setuge"; 5146 case ISD::SETULT: return "setult"; 5147 case ISD::SETULE: return "setule"; 5148 case ISD::SETUNE: return "setune"; 5149 5150 case ISD::SETEQ: return "seteq"; 5151 case ISD::SETGT: return "setgt"; 5152 case ISD::SETGE: return "setge"; 5153 case ISD::SETLT: return "setlt"; 5154 case ISD::SETLE: return "setle"; 5155 case ISD::SETNE: return "setne"; 5156 } 5157 } 5158} 5159 5160const char *SDNode::getIndexedModeName(ISD::MemIndexedMode AM) { 5161 switch (AM) { 5162 default: 5163 return ""; 5164 case ISD::PRE_INC: 5165 return "<pre-inc>"; 5166 case ISD::PRE_DEC: 5167 return "<pre-dec>"; 5168 case ISD::POST_INC: 5169 return "<post-inc>"; 5170 case ISD::POST_DEC: 5171 return "<post-dec>"; 5172 } 5173} 5174 5175std::string ISD::ArgFlagsTy::getArgFlagsString() { 5176 std::string S = "< "; 5177 5178 if (isZExt()) 5179 S += "zext "; 5180 if (isSExt()) 5181 S += "sext "; 5182 if (isInReg()) 5183 S += "inreg "; 5184 if (isSRet()) 5185 S += "sret "; 5186 if (isByVal()) 5187 S += "byval "; 5188 if (isNest()) 5189 S += "nest "; 5190 if (getByValAlign()) 5191 S += "byval-align:" + utostr(getByValAlign()) + " "; 5192 if (getOrigAlign()) 5193 S += "orig-align:" + utostr(getOrigAlign()) + " "; 5194 if (getByValSize()) 5195 S += "byval-size:" + utostr(getByValSize()) + " "; 5196 return S + ">"; 5197} 5198 5199void SDNode::dump() const { dump(0); } 5200void SDNode::dump(const SelectionDAG *G) const { 5201 print(errs(), G); 5202 errs().flush(); 5203} 5204 5205void SDNode::print(raw_ostream &OS, const SelectionDAG *G) const { 5206 OS << (void*)this << ": "; 5207 5208 for (unsigned i = 0, e = getNumValues(); i != e; ++i) { 5209 if (i) OS << ","; 5210 if (getValueType(i) == MVT::Other) 5211 OS << "ch"; 5212 else 5213 OS << getValueType(i).getMVTString(); 5214 } 5215 OS << " = " << getOperationName(G); 5216 5217 OS << " "; 5218 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 5219 if (i) OS << ", "; 5220 OS << (void*)getOperand(i).getNode(); 5221 if (unsigned RN = getOperand(i).getResNo()) 5222 OS << ":" << RN; 5223 } 5224 5225 if (!isTargetOpcode() && getOpcode() == ISD::VECTOR_SHUFFLE) { 5226 SDNode *Mask = getOperand(2).getNode(); 5227 OS << "<"; 5228 for (unsigned i = 0, e = Mask->getNumOperands(); i != e; ++i) { 5229 if (i) OS << ","; 5230 if (Mask->getOperand(i).getOpcode() == ISD::UNDEF) 5231 OS << "u"; 5232 else 5233 OS << cast<ConstantSDNode>(Mask->getOperand(i))->getZExtValue(); 5234 } 5235 OS << ">"; 5236 } 5237 5238 if (const ConstantSDNode *CSDN = dyn_cast<ConstantSDNode>(this)) { 5239 OS << '<' << CSDN->getAPIntValue() << '>'; 5240 } else if (const ConstantFPSDNode *CSDN = dyn_cast<ConstantFPSDNode>(this)) { 5241 if (&CSDN->getValueAPF().getSemantics()==&APFloat::IEEEsingle) 5242 OS << '<' << CSDN->getValueAPF().convertToFloat() << '>'; 5243 else if (&CSDN->getValueAPF().getSemantics()==&APFloat::IEEEdouble) 5244 OS << '<' << CSDN->getValueAPF().convertToDouble() << '>'; 5245 else { 5246 OS << "<APFloat("; 5247 CSDN->getValueAPF().convertToAPInt().dump(); 5248 OS << ")>"; 5249 } 5250 } else if (const GlobalAddressSDNode *GADN = 5251 dyn_cast<GlobalAddressSDNode>(this)) { 5252 int offset = GADN->getOffset(); 5253 OS << '<'; 5254 WriteAsOperand(OS, GADN->getGlobal()); 5255 OS << '>'; 5256 if (offset > 0) 5257 OS << " + " << offset; 5258 else 5259 OS << " " << offset; 5260 } else if (const FrameIndexSDNode *FIDN = dyn_cast<FrameIndexSDNode>(this)) { 5261 OS << "<" << FIDN->getIndex() << ">"; 5262 } else if (const JumpTableSDNode *JTDN = dyn_cast<JumpTableSDNode>(this)) { 5263 OS << "<" << JTDN->getIndex() << ">"; 5264 } else if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(this)){ 5265 int offset = CP->getOffset(); 5266 if (CP->isMachineConstantPoolEntry()) 5267 OS << "<" << *CP->getMachineCPVal() << ">"; 5268 else 5269 OS << "<" << *CP->getConstVal() << ">"; 5270 if (offset > 0) 5271 OS << " + " << offset; 5272 else 5273 OS << " " << offset; 5274 } else if (const BasicBlockSDNode *BBDN = dyn_cast<BasicBlockSDNode>(this)) { 5275 OS << "<"; 5276 const Value *LBB = (const Value*)BBDN->getBasicBlock()->getBasicBlock(); 5277 if (LBB) 5278 OS << LBB->getName() << " "; 5279 OS << (const void*)BBDN->getBasicBlock() << ">"; 5280 } else if (const RegisterSDNode *R = dyn_cast<RegisterSDNode>(this)) { 5281 if (G && R->getReg() && 5282 TargetRegisterInfo::isPhysicalRegister(R->getReg())) { 5283 OS << " " << G->getTarget().getRegisterInfo()->getName(R->getReg()); 5284 } else { 5285 OS << " #" << R->getReg(); 5286 } 5287 } else if (const ExternalSymbolSDNode *ES = 5288 dyn_cast<ExternalSymbolSDNode>(this)) { 5289 OS << "'" << ES->getSymbol() << "'"; 5290 } else if (const SrcValueSDNode *M = dyn_cast<SrcValueSDNode>(this)) { 5291 if (M->getValue()) 5292 OS << "<" << M->getValue() << ">"; 5293 else 5294 OS << "<null>"; 5295 } else if (const MemOperandSDNode *M = dyn_cast<MemOperandSDNode>(this)) { 5296 if (M->MO.getValue()) 5297 OS << "<" << M->MO.getValue() << ":" << M->MO.getOffset() << ">"; 5298 else 5299 OS << "<null:" << M->MO.getOffset() << ">"; 5300 } else if (const ARG_FLAGSSDNode *N = dyn_cast<ARG_FLAGSSDNode>(this)) { 5301 OS << N->getArgFlags().getArgFlagsString(); 5302 } else if (const VTSDNode *N = dyn_cast<VTSDNode>(this)) { 5303 OS << ":" << N->getVT().getMVTString(); 5304 } 5305 else if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(this)) { 5306 const Value *SrcValue = LD->getSrcValue(); 5307 int SrcOffset = LD->getSrcValueOffset(); 5308 OS << " <"; 5309 if (SrcValue) 5310 OS << SrcValue; 5311 else 5312 OS << "null"; 5313 OS << ":" << SrcOffset << ">"; 5314 5315 bool doExt = true; 5316 switch (LD->getExtensionType()) { 5317 default: doExt = false; break; 5318 case ISD::EXTLOAD: OS << " <anyext "; break; 5319 case ISD::SEXTLOAD: OS << " <sext "; break; 5320 case ISD::ZEXTLOAD: OS << " <zext "; break; 5321 } 5322 if (doExt) 5323 OS << LD->getMemoryVT().getMVTString() << ">"; 5324 5325 const char *AM = getIndexedModeName(LD->getAddressingMode()); 5326 if (*AM) 5327 OS << " " << AM; 5328 if (LD->isVolatile()) 5329 OS << " <volatile>"; 5330 OS << " alignment=" << LD->getAlignment(); 5331 } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(this)) { 5332 const Value *SrcValue = ST->getSrcValue(); 5333 int SrcOffset = ST->getSrcValueOffset(); 5334 OS << " <"; 5335 if (SrcValue) 5336 OS << SrcValue; 5337 else 5338 OS << "null"; 5339 OS << ":" << SrcOffset << ">"; 5340 5341 if (ST->isTruncatingStore()) 5342 OS << " <trunc " << ST->getMemoryVT().getMVTString() << ">"; 5343 5344 const char *AM = getIndexedModeName(ST->getAddressingMode()); 5345 if (*AM) 5346 OS << " " << AM; 5347 if (ST->isVolatile()) 5348 OS << " <volatile>"; 5349 OS << " alignment=" << ST->getAlignment(); 5350 } else if (const AtomicSDNode* AT = dyn_cast<AtomicSDNode>(this)) { 5351 const Value *SrcValue = AT->getSrcValue(); 5352 int SrcOffset = AT->getSrcValueOffset(); 5353 OS << " <"; 5354 if (SrcValue) 5355 OS << SrcValue; 5356 else 5357 OS << "null"; 5358 OS << ":" << SrcOffset << ">"; 5359 if (AT->isVolatile()) 5360 OS << " <volatile>"; 5361 OS << " alignment=" << AT->getAlignment(); 5362 } 5363} 5364 5365static void DumpNodes(const SDNode *N, unsigned indent, const SelectionDAG *G) { 5366 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 5367 if (N->getOperand(i).getNode()->hasOneUse()) 5368 DumpNodes(N->getOperand(i).getNode(), indent+2, G); 5369 else 5370 cerr << "\n" << std::string(indent+2, ' ') 5371 << (void*)N->getOperand(i).getNode() << ": <multiple use>"; 5372 5373 5374 cerr << "\n" << std::string(indent, ' '); 5375 N->dump(G); 5376} 5377 5378void SelectionDAG::dump() const { 5379 cerr << "SelectionDAG has " << AllNodes.size() << " nodes:"; 5380 5381 for (allnodes_const_iterator I = allnodes_begin(), E = allnodes_end(); 5382 I != E; ++I) { 5383 const SDNode *N = I; 5384 if (!N->hasOneUse() && N != getRoot().getNode()) 5385 DumpNodes(N, 2, this); 5386 } 5387 5388 if (getRoot().getNode()) DumpNodes(getRoot().getNode(), 2, this); 5389 5390 cerr << "\n\n"; 5391} 5392 5393const Type *ConstantPoolSDNode::getType() const { 5394 if (isMachineConstantPoolEntry()) 5395 return Val.MachineCPVal->getType(); 5396 return Val.ConstVal->getType(); 5397} 5398