SelectionDAG.cpp revision 6520e20e4fb31f2e65e25c38b372b19d33a83df4
1//===-- SelectionDAG.cpp - Implement the SelectionDAG data structures -----===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAG class. 11// 12//===----------------------------------------------------------------------===// 13#include "llvm/CodeGen/SelectionDAG.h" 14#include "llvm/Constants.h" 15#include "llvm/Analysis/ValueTracking.h" 16#include "llvm/GlobalAlias.h" 17#include "llvm/GlobalVariable.h" 18#include "llvm/Intrinsics.h" 19#include "llvm/DerivedTypes.h" 20#include "llvm/Assembly/Writer.h" 21#include "llvm/CallingConv.h" 22#include "llvm/CodeGen/MachineBasicBlock.h" 23#include "llvm/CodeGen/MachineConstantPool.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/MachineModuleInfo.h" 26#include "llvm/CodeGen/PseudoSourceValue.h" 27#include "llvm/Target/TargetRegisterInfo.h" 28#include "llvm/Target/TargetData.h" 29#include "llvm/Target/TargetLowering.h" 30#include "llvm/Target/TargetInstrInfo.h" 31#include "llvm/Target/TargetMachine.h" 32#include "llvm/Support/CommandLine.h" 33#include "llvm/Support/MathExtras.h" 34#include "llvm/Support/raw_ostream.h" 35#include "llvm/ADT/SetVector.h" 36#include "llvm/ADT/SmallPtrSet.h" 37#include "llvm/ADT/SmallSet.h" 38#include "llvm/ADT/SmallVector.h" 39#include "llvm/ADT/StringExtras.h" 40#include <algorithm> 41#include <cmath> 42using namespace llvm; 43 44/// makeVTList - Return an instance of the SDVTList struct initialized with the 45/// specified members. 46static SDVTList makeVTList(const MVT *VTs, unsigned NumVTs) { 47 SDVTList Res = {VTs, NumVTs}; 48 return Res; 49} 50 51static const fltSemantics *MVTToAPFloatSemantics(MVT VT) { 52 switch (VT.getSimpleVT()) { 53 default: assert(0 && "Unknown FP format"); 54 case MVT::f32: return &APFloat::IEEEsingle; 55 case MVT::f64: return &APFloat::IEEEdouble; 56 case MVT::f80: return &APFloat::x87DoubleExtended; 57 case MVT::f128: return &APFloat::IEEEquad; 58 case MVT::ppcf128: return &APFloat::PPCDoubleDouble; 59 } 60} 61 62SelectionDAG::DAGUpdateListener::~DAGUpdateListener() {} 63 64//===----------------------------------------------------------------------===// 65// ConstantFPSDNode Class 66//===----------------------------------------------------------------------===// 67 68/// isExactlyValue - We don't rely on operator== working on double values, as 69/// it returns true for things that are clearly not equal, like -0.0 and 0.0. 70/// As such, this method can be used to do an exact bit-for-bit comparison of 71/// two floating point values. 72bool ConstantFPSDNode::isExactlyValue(const APFloat& V) const { 73 return getValueAPF().bitwiseIsEqual(V); 74} 75 76bool ConstantFPSDNode::isValueValidForType(MVT VT, 77 const APFloat& Val) { 78 assert(VT.isFloatingPoint() && "Can only convert between FP types"); 79 80 // PPC long double cannot be converted to any other type. 81 if (VT == MVT::ppcf128 || 82 &Val.getSemantics() == &APFloat::PPCDoubleDouble) 83 return false; 84 85 // convert modifies in place, so make a copy. 86 APFloat Val2 = APFloat(Val); 87 bool losesInfo; 88 (void) Val2.convert(*MVTToAPFloatSemantics(VT), APFloat::rmNearestTiesToEven, 89 &losesInfo); 90 return !losesInfo; 91} 92 93//===----------------------------------------------------------------------===// 94// ISD Namespace 95//===----------------------------------------------------------------------===// 96 97/// isBuildVectorAllOnes - Return true if the specified node is a 98/// BUILD_VECTOR where all of the elements are ~0 or undef. 99bool ISD::isBuildVectorAllOnes(const SDNode *N) { 100 // Look through a bit convert. 101 if (N->getOpcode() == ISD::BIT_CONVERT) 102 N = N->getOperand(0).getNode(); 103 104 if (N->getOpcode() != ISD::BUILD_VECTOR) return false; 105 106 unsigned i = 0, e = N->getNumOperands(); 107 108 // Skip over all of the undef values. 109 while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF) 110 ++i; 111 112 // Do not accept an all-undef vector. 113 if (i == e) return false; 114 115 // Do not accept build_vectors that aren't all constants or which have non-~0 116 // elements. 117 SDValue NotZero = N->getOperand(i); 118 if (isa<ConstantSDNode>(NotZero)) { 119 if (!cast<ConstantSDNode>(NotZero)->isAllOnesValue()) 120 return false; 121 } else if (isa<ConstantFPSDNode>(NotZero)) { 122 if (!cast<ConstantFPSDNode>(NotZero)->getValueAPF(). 123 bitcastToAPInt().isAllOnesValue()) 124 return false; 125 } else 126 return false; 127 128 // Okay, we have at least one ~0 value, check to see if the rest match or are 129 // undefs. 130 for (++i; i != e; ++i) 131 if (N->getOperand(i) != NotZero && 132 N->getOperand(i).getOpcode() != ISD::UNDEF) 133 return false; 134 return true; 135} 136 137 138/// isBuildVectorAllZeros - Return true if the specified node is a 139/// BUILD_VECTOR where all of the elements are 0 or undef. 140bool ISD::isBuildVectorAllZeros(const SDNode *N) { 141 // Look through a bit convert. 142 if (N->getOpcode() == ISD::BIT_CONVERT) 143 N = N->getOperand(0).getNode(); 144 145 if (N->getOpcode() != ISD::BUILD_VECTOR) return false; 146 147 unsigned i = 0, e = N->getNumOperands(); 148 149 // Skip over all of the undef values. 150 while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF) 151 ++i; 152 153 // Do not accept an all-undef vector. 154 if (i == e) return false; 155 156 // Do not accept build_vectors that aren't all constants or which have non-~0 157 // elements. 158 SDValue Zero = N->getOperand(i); 159 if (isa<ConstantSDNode>(Zero)) { 160 if (!cast<ConstantSDNode>(Zero)->isNullValue()) 161 return false; 162 } else if (isa<ConstantFPSDNode>(Zero)) { 163 if (!cast<ConstantFPSDNode>(Zero)->getValueAPF().isPosZero()) 164 return false; 165 } else 166 return false; 167 168 // Okay, we have at least one ~0 value, check to see if the rest match or are 169 // undefs. 170 for (++i; i != e; ++i) 171 if (N->getOperand(i) != Zero && 172 N->getOperand(i).getOpcode() != ISD::UNDEF) 173 return false; 174 return true; 175} 176 177/// isScalarToVector - Return true if the specified node is a 178/// ISD::SCALAR_TO_VECTOR node or a BUILD_VECTOR node where only the low 179/// element is not an undef. 180bool ISD::isScalarToVector(const SDNode *N) { 181 if (N->getOpcode() == ISD::SCALAR_TO_VECTOR) 182 return true; 183 184 if (N->getOpcode() != ISD::BUILD_VECTOR) 185 return false; 186 if (N->getOperand(0).getOpcode() == ISD::UNDEF) 187 return false; 188 unsigned NumElems = N->getNumOperands(); 189 for (unsigned i = 1; i < NumElems; ++i) { 190 SDValue V = N->getOperand(i); 191 if (V.getOpcode() != ISD::UNDEF) 192 return false; 193 } 194 return true; 195} 196 197 198/// isDebugLabel - Return true if the specified node represents a debug 199/// label (i.e. ISD::DBG_LABEL or TargetInstrInfo::DBG_LABEL node). 200bool ISD::isDebugLabel(const SDNode *N) { 201 SDValue Zero; 202 if (N->getOpcode() == ISD::DBG_LABEL) 203 return true; 204 if (N->isMachineOpcode() && 205 N->getMachineOpcode() == TargetInstrInfo::DBG_LABEL) 206 return true; 207 return false; 208} 209 210/// getSetCCSwappedOperands - Return the operation corresponding to (Y op X) 211/// when given the operation for (X op Y). 212ISD::CondCode ISD::getSetCCSwappedOperands(ISD::CondCode Operation) { 213 // To perform this operation, we just need to swap the L and G bits of the 214 // operation. 215 unsigned OldL = (Operation >> 2) & 1; 216 unsigned OldG = (Operation >> 1) & 1; 217 return ISD::CondCode((Operation & ~6) | // Keep the N, U, E bits 218 (OldL << 1) | // New G bit 219 (OldG << 2)); // New L bit. 220} 221 222/// getSetCCInverse - Return the operation corresponding to !(X op Y), where 223/// 'op' is a valid SetCC operation. 224ISD::CondCode ISD::getSetCCInverse(ISD::CondCode Op, bool isInteger) { 225 unsigned Operation = Op; 226 if (isInteger) 227 Operation ^= 7; // Flip L, G, E bits, but not U. 228 else 229 Operation ^= 15; // Flip all of the condition bits. 230 if (Operation > ISD::SETTRUE2) 231 Operation &= ~8; // Don't let N and U bits get set. 232 return ISD::CondCode(Operation); 233} 234 235 236/// isSignedOp - For an integer comparison, return 1 if the comparison is a 237/// signed operation and 2 if the result is an unsigned comparison. Return zero 238/// if the operation does not depend on the sign of the input (setne and seteq). 239static int isSignedOp(ISD::CondCode Opcode) { 240 switch (Opcode) { 241 default: assert(0 && "Illegal integer setcc operation!"); 242 case ISD::SETEQ: 243 case ISD::SETNE: return 0; 244 case ISD::SETLT: 245 case ISD::SETLE: 246 case ISD::SETGT: 247 case ISD::SETGE: return 1; 248 case ISD::SETULT: 249 case ISD::SETULE: 250 case ISD::SETUGT: 251 case ISD::SETUGE: return 2; 252 } 253} 254 255/// getSetCCOrOperation - Return the result of a logical OR between different 256/// comparisons of identical values: ((X op1 Y) | (X op2 Y)). This function 257/// returns SETCC_INVALID if it is not possible to represent the resultant 258/// comparison. 259ISD::CondCode ISD::getSetCCOrOperation(ISD::CondCode Op1, ISD::CondCode Op2, 260 bool isInteger) { 261 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 262 // Cannot fold a signed integer setcc with an unsigned integer setcc. 263 return ISD::SETCC_INVALID; 264 265 unsigned Op = Op1 | Op2; // Combine all of the condition bits. 266 267 // If the N and U bits get set then the resultant comparison DOES suddenly 268 // care about orderedness, and is true when ordered. 269 if (Op > ISD::SETTRUE2) 270 Op &= ~16; // Clear the U bit if the N bit is set. 271 272 // Canonicalize illegal integer setcc's. 273 if (isInteger && Op == ISD::SETUNE) // e.g. SETUGT | SETULT 274 Op = ISD::SETNE; 275 276 return ISD::CondCode(Op); 277} 278 279/// getSetCCAndOperation - Return the result of a logical AND between different 280/// comparisons of identical values: ((X op1 Y) & (X op2 Y)). This 281/// function returns zero if it is not possible to represent the resultant 282/// comparison. 283ISD::CondCode ISD::getSetCCAndOperation(ISD::CondCode Op1, ISD::CondCode Op2, 284 bool isInteger) { 285 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 286 // Cannot fold a signed setcc with an unsigned setcc. 287 return ISD::SETCC_INVALID; 288 289 // Combine all of the condition bits. 290 ISD::CondCode Result = ISD::CondCode(Op1 & Op2); 291 292 // Canonicalize illegal integer setcc's. 293 if (isInteger) { 294 switch (Result) { 295 default: break; 296 case ISD::SETUO : Result = ISD::SETFALSE; break; // SETUGT & SETULT 297 case ISD::SETOEQ: // SETEQ & SETU[LG]E 298 case ISD::SETUEQ: Result = ISD::SETEQ ; break; // SETUGE & SETULE 299 case ISD::SETOLT: Result = ISD::SETULT ; break; // SETULT & SETNE 300 case ISD::SETOGT: Result = ISD::SETUGT ; break; // SETUGT & SETNE 301 } 302 } 303 304 return Result; 305} 306 307const TargetMachine &SelectionDAG::getTarget() const { 308 return MF->getTarget(); 309} 310 311//===----------------------------------------------------------------------===// 312// SDNode Profile Support 313//===----------------------------------------------------------------------===// 314 315/// AddNodeIDOpcode - Add the node opcode to the NodeID data. 316/// 317static void AddNodeIDOpcode(FoldingSetNodeID &ID, unsigned OpC) { 318 ID.AddInteger(OpC); 319} 320 321/// AddNodeIDValueTypes - Value type lists are intern'd so we can represent them 322/// solely with their pointer. 323static void AddNodeIDValueTypes(FoldingSetNodeID &ID, SDVTList VTList) { 324 ID.AddPointer(VTList.VTs); 325} 326 327/// AddNodeIDOperands - Various routines for adding operands to the NodeID data. 328/// 329static void AddNodeIDOperands(FoldingSetNodeID &ID, 330 const SDValue *Ops, unsigned NumOps) { 331 for (; NumOps; --NumOps, ++Ops) { 332 ID.AddPointer(Ops->getNode()); 333 ID.AddInteger(Ops->getResNo()); 334 } 335} 336 337/// AddNodeIDOperands - Various routines for adding operands to the NodeID data. 338/// 339static void AddNodeIDOperands(FoldingSetNodeID &ID, 340 const SDUse *Ops, unsigned NumOps) { 341 for (; NumOps; --NumOps, ++Ops) { 342 ID.AddPointer(Ops->getVal()); 343 ID.AddInteger(Ops->getSDValue().getResNo()); 344 } 345} 346 347static void AddNodeIDNode(FoldingSetNodeID &ID, 348 unsigned short OpC, SDVTList VTList, 349 const SDValue *OpList, unsigned N) { 350 AddNodeIDOpcode(ID, OpC); 351 AddNodeIDValueTypes(ID, VTList); 352 AddNodeIDOperands(ID, OpList, N); 353} 354 355 356/// AddNodeIDNode - Generic routine for adding a nodes info to the NodeID 357/// data. 358static void AddNodeIDNode(FoldingSetNodeID &ID, const SDNode *N) { 359 AddNodeIDOpcode(ID, N->getOpcode()); 360 // Add the return value info. 361 AddNodeIDValueTypes(ID, N->getVTList()); 362 // Add the operand info. 363 AddNodeIDOperands(ID, N->op_begin(), N->getNumOperands()); 364 365 // Handle SDNode leafs with special info. 366 switch (N->getOpcode()) { 367 default: break; // Normal nodes don't need extra info. 368 case ISD::ARG_FLAGS: 369 ID.AddInteger(cast<ARG_FLAGSSDNode>(N)->getArgFlags().getRawBits()); 370 break; 371 case ISD::TargetConstant: 372 case ISD::Constant: 373 ID.AddPointer(cast<ConstantSDNode>(N)->getConstantIntValue()); 374 break; 375 case ISD::TargetConstantFP: 376 case ISD::ConstantFP: { 377 ID.AddPointer(cast<ConstantFPSDNode>(N)->getConstantFPValue()); 378 break; 379 } 380 case ISD::TargetGlobalAddress: 381 case ISD::GlobalAddress: 382 case ISD::TargetGlobalTLSAddress: 383 case ISD::GlobalTLSAddress: { 384 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(N); 385 ID.AddPointer(GA->getGlobal()); 386 ID.AddInteger(GA->getOffset()); 387 break; 388 } 389 case ISD::BasicBlock: 390 ID.AddPointer(cast<BasicBlockSDNode>(N)->getBasicBlock()); 391 break; 392 case ISD::Register: 393 ID.AddInteger(cast<RegisterSDNode>(N)->getReg()); 394 break; 395 case ISD::DBG_STOPPOINT: { 396 const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(N); 397 ID.AddInteger(DSP->getLine()); 398 ID.AddInteger(DSP->getColumn()); 399 ID.AddPointer(DSP->getCompileUnit()); 400 break; 401 } 402 case ISD::SRCVALUE: 403 ID.AddPointer(cast<SrcValueSDNode>(N)->getValue()); 404 break; 405 case ISD::MEMOPERAND: { 406 const MachineMemOperand &MO = cast<MemOperandSDNode>(N)->MO; 407 MO.Profile(ID); 408 break; 409 } 410 case ISD::FrameIndex: 411 case ISD::TargetFrameIndex: 412 ID.AddInteger(cast<FrameIndexSDNode>(N)->getIndex()); 413 break; 414 case ISD::JumpTable: 415 case ISD::TargetJumpTable: 416 ID.AddInteger(cast<JumpTableSDNode>(N)->getIndex()); 417 break; 418 case ISD::ConstantPool: 419 case ISD::TargetConstantPool: { 420 const ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(N); 421 ID.AddInteger(CP->getAlignment()); 422 ID.AddInteger(CP->getOffset()); 423 if (CP->isMachineConstantPoolEntry()) 424 CP->getMachineCPVal()->AddSelectionDAGCSEId(ID); 425 else 426 ID.AddPointer(CP->getConstVal()); 427 break; 428 } 429 case ISD::CALL: { 430 const CallSDNode *Call = cast<CallSDNode>(N); 431 ID.AddInteger(Call->getCallingConv()); 432 ID.AddInteger(Call->isVarArg()); 433 break; 434 } 435 case ISD::LOAD: { 436 const LoadSDNode *LD = cast<LoadSDNode>(N); 437 ID.AddInteger(LD->getAddressingMode()); 438 ID.AddInteger(LD->getExtensionType()); 439 ID.AddInteger(LD->getMemoryVT().getRawBits()); 440 ID.AddInteger(LD->getRawFlags()); 441 break; 442 } 443 case ISD::STORE: { 444 const StoreSDNode *ST = cast<StoreSDNode>(N); 445 ID.AddInteger(ST->getAddressingMode()); 446 ID.AddInteger(ST->isTruncatingStore()); 447 ID.AddInteger(ST->getMemoryVT().getRawBits()); 448 ID.AddInteger(ST->getRawFlags()); 449 break; 450 } 451 case ISD::ATOMIC_CMP_SWAP_8: 452 case ISD::ATOMIC_SWAP_8: 453 case ISD::ATOMIC_LOAD_ADD_8: 454 case ISD::ATOMIC_LOAD_SUB_8: 455 case ISD::ATOMIC_LOAD_AND_8: 456 case ISD::ATOMIC_LOAD_OR_8: 457 case ISD::ATOMIC_LOAD_XOR_8: 458 case ISD::ATOMIC_LOAD_NAND_8: 459 case ISD::ATOMIC_LOAD_MIN_8: 460 case ISD::ATOMIC_LOAD_MAX_8: 461 case ISD::ATOMIC_LOAD_UMIN_8: 462 case ISD::ATOMIC_LOAD_UMAX_8: 463 case ISD::ATOMIC_CMP_SWAP_16: 464 case ISD::ATOMIC_SWAP_16: 465 case ISD::ATOMIC_LOAD_ADD_16: 466 case ISD::ATOMIC_LOAD_SUB_16: 467 case ISD::ATOMIC_LOAD_AND_16: 468 case ISD::ATOMIC_LOAD_OR_16: 469 case ISD::ATOMIC_LOAD_XOR_16: 470 case ISD::ATOMIC_LOAD_NAND_16: 471 case ISD::ATOMIC_LOAD_MIN_16: 472 case ISD::ATOMIC_LOAD_MAX_16: 473 case ISD::ATOMIC_LOAD_UMIN_16: 474 case ISD::ATOMIC_LOAD_UMAX_16: 475 case ISD::ATOMIC_CMP_SWAP_32: 476 case ISD::ATOMIC_SWAP_32: 477 case ISD::ATOMIC_LOAD_ADD_32: 478 case ISD::ATOMIC_LOAD_SUB_32: 479 case ISD::ATOMIC_LOAD_AND_32: 480 case ISD::ATOMIC_LOAD_OR_32: 481 case ISD::ATOMIC_LOAD_XOR_32: 482 case ISD::ATOMIC_LOAD_NAND_32: 483 case ISD::ATOMIC_LOAD_MIN_32: 484 case ISD::ATOMIC_LOAD_MAX_32: 485 case ISD::ATOMIC_LOAD_UMIN_32: 486 case ISD::ATOMIC_LOAD_UMAX_32: 487 case ISD::ATOMIC_CMP_SWAP_64: 488 case ISD::ATOMIC_SWAP_64: 489 case ISD::ATOMIC_LOAD_ADD_64: 490 case ISD::ATOMIC_LOAD_SUB_64: 491 case ISD::ATOMIC_LOAD_AND_64: 492 case ISD::ATOMIC_LOAD_OR_64: 493 case ISD::ATOMIC_LOAD_XOR_64: 494 case ISD::ATOMIC_LOAD_NAND_64: 495 case ISD::ATOMIC_LOAD_MIN_64: 496 case ISD::ATOMIC_LOAD_MAX_64: 497 case ISD::ATOMIC_LOAD_UMIN_64: 498 case ISD::ATOMIC_LOAD_UMAX_64: { 499 const AtomicSDNode *AT = cast<AtomicSDNode>(N); 500 ID.AddInteger(AT->getRawFlags()); 501 break; 502 } 503 } // end switch (N->getOpcode()) 504} 505 506/// encodeMemSDNodeFlags - Generic routine for computing a value for use in 507/// the CSE map that carries both alignment and volatility information. 508/// 509static unsigned encodeMemSDNodeFlags(bool isVolatile, unsigned Alignment) { 510 return isVolatile | ((Log2_32(Alignment) + 1) << 1); 511} 512 513//===----------------------------------------------------------------------===// 514// SelectionDAG Class 515//===----------------------------------------------------------------------===// 516 517/// RemoveDeadNodes - This method deletes all unreachable nodes in the 518/// SelectionDAG. 519void SelectionDAG::RemoveDeadNodes() { 520 // Create a dummy node (which is not added to allnodes), that adds a reference 521 // to the root node, preventing it from being deleted. 522 HandleSDNode Dummy(getRoot()); 523 524 SmallVector<SDNode*, 128> DeadNodes; 525 526 // Add all obviously-dead nodes to the DeadNodes worklist. 527 for (allnodes_iterator I = allnodes_begin(), E = allnodes_end(); I != E; ++I) 528 if (I->use_empty()) 529 DeadNodes.push_back(I); 530 531 RemoveDeadNodes(DeadNodes); 532 533 // If the root changed (e.g. it was a dead load, update the root). 534 setRoot(Dummy.getValue()); 535} 536 537/// RemoveDeadNodes - This method deletes the unreachable nodes in the 538/// given list, and any nodes that become unreachable as a result. 539void SelectionDAG::RemoveDeadNodes(SmallVectorImpl<SDNode *> &DeadNodes, 540 DAGUpdateListener *UpdateListener) { 541 542 // Process the worklist, deleting the nodes and adding their uses to the 543 // worklist. 544 while (!DeadNodes.empty()) { 545 SDNode *N = DeadNodes.back(); 546 DeadNodes.pop_back(); 547 548 if (UpdateListener) 549 UpdateListener->NodeDeleted(N, 0); 550 551 // Take the node out of the appropriate CSE map. 552 RemoveNodeFromCSEMaps(N); 553 554 // Next, brutally remove the operand list. This is safe to do, as there are 555 // no cycles in the graph. 556 for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ++I) { 557 SDNode *Operand = I->getVal(); 558 Operand->removeUser(std::distance(N->op_begin(), I), N); 559 560 // Now that we removed this operand, see if there are no uses of it left. 561 if (Operand->use_empty()) 562 DeadNodes.push_back(Operand); 563 } 564 if (N->OperandsNeedDelete) { 565 delete[] N->OperandList; 566 } 567 N->OperandList = 0; 568 N->NumOperands = 0; 569 570 // Finally, remove N itself. 571 NodeAllocator.Deallocate(AllNodes.remove(N)); 572 } 573} 574 575void SelectionDAG::RemoveDeadNode(SDNode *N, DAGUpdateListener *UpdateListener){ 576 SmallVector<SDNode*, 16> DeadNodes(1, N); 577 RemoveDeadNodes(DeadNodes, UpdateListener); 578} 579 580void SelectionDAG::DeleteNode(SDNode *N) { 581 assert(N->use_empty() && "Cannot delete a node that is not dead!"); 582 583 // First take this out of the appropriate CSE map. 584 RemoveNodeFromCSEMaps(N); 585 586 // Finally, remove uses due to operands of this node, remove from the 587 // AllNodes list, and delete the node. 588 DeleteNodeNotInCSEMaps(N); 589} 590 591void SelectionDAG::DeleteNodeNotInCSEMaps(SDNode *N) { 592 593 // Drop all of the operands and decrement used node's use counts. 594 for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ++I) 595 I->getVal()->removeUser(std::distance(N->op_begin(), I), N); 596 if (N->OperandsNeedDelete) 597 delete[] N->OperandList; 598 599 assert(N != AllNodes.begin()); 600 NodeAllocator.Deallocate(AllNodes.remove(N)); 601} 602 603/// RemoveNodeFromCSEMaps - Take the specified node out of the CSE map that 604/// correspond to it. This is useful when we're about to delete or repurpose 605/// the node. We don't want future request for structurally identical nodes 606/// to return N anymore. 607bool SelectionDAG::RemoveNodeFromCSEMaps(SDNode *N) { 608 bool Erased = false; 609 switch (N->getOpcode()) { 610 case ISD::EntryToken: 611 assert(0 && "EntryToken should not be in CSEMaps!"); 612 return false; 613 case ISD::HANDLENODE: return false; // noop. 614 case ISD::CONDCODE: 615 assert(CondCodeNodes[cast<CondCodeSDNode>(N)->get()] && 616 "Cond code doesn't exist!"); 617 Erased = CondCodeNodes[cast<CondCodeSDNode>(N)->get()] != 0; 618 CondCodeNodes[cast<CondCodeSDNode>(N)->get()] = 0; 619 break; 620 case ISD::ExternalSymbol: 621 Erased = ExternalSymbols.erase(cast<ExternalSymbolSDNode>(N)->getSymbol()); 622 break; 623 case ISD::TargetExternalSymbol: 624 Erased = 625 TargetExternalSymbols.erase(cast<ExternalSymbolSDNode>(N)->getSymbol()); 626 break; 627 case ISD::VALUETYPE: { 628 MVT VT = cast<VTSDNode>(N)->getVT(); 629 if (VT.isExtended()) { 630 Erased = ExtendedValueTypeNodes.erase(VT); 631 } else { 632 Erased = ValueTypeNodes[VT.getSimpleVT()] != 0; 633 ValueTypeNodes[VT.getSimpleVT()] = 0; 634 } 635 break; 636 } 637 default: 638 // Remove it from the CSE Map. 639 Erased = CSEMap.RemoveNode(N); 640 break; 641 } 642#ifndef NDEBUG 643 // Verify that the node was actually in one of the CSE maps, unless it has a 644 // flag result (which cannot be CSE'd) or is one of the special cases that are 645 // not subject to CSE. 646 if (!Erased && N->getValueType(N->getNumValues()-1) != MVT::Flag && 647 !N->isMachineOpcode() && 648 N->getOpcode() != ISD::DBG_LABEL && 649 N->getOpcode() != ISD::DBG_STOPPOINT && 650 N->getOpcode() != ISD::EH_LABEL && 651 N->getOpcode() != ISD::DECLARE) { 652 N->dump(this); 653 cerr << "\n"; 654 assert(0 && "Node is not in map!"); 655 } 656#endif 657 return Erased; 658} 659 660/// AddNonLeafNodeToCSEMaps - Add the specified node back to the CSE maps. It 661/// has been taken out and modified in some way. If the specified node already 662/// exists in the CSE maps, do not modify the maps, but return the existing node 663/// instead. If it doesn't exist, add it and return null. 664/// 665SDNode *SelectionDAG::AddNonLeafNodeToCSEMaps(SDNode *N) { 666 assert(N->getNumOperands() && "This is a leaf node!"); 667 668 if (N->getValueType(0) == MVT::Flag) 669 return 0; // Never CSE anything that produces a flag. 670 671 switch (N->getOpcode()) { 672 default: break; 673 case ISD::HANDLENODE: 674 case ISD::DBG_LABEL: 675 case ISD::DBG_STOPPOINT: 676 case ISD::EH_LABEL: 677 case ISD::DECLARE: 678 return 0; // Never add these nodes. 679 } 680 681 // Check that remaining values produced are not flags. 682 for (unsigned i = 1, e = N->getNumValues(); i != e; ++i) 683 if (N->getValueType(i) == MVT::Flag) 684 return 0; // Never CSE anything that produces a flag. 685 686 SDNode *New = CSEMap.GetOrInsertNode(N); 687 if (New != N) return New; // Node already existed. 688 return 0; 689} 690 691/// FindModifiedNodeSlot - Find a slot for the specified node if its operands 692/// were replaced with those specified. If this node is never memoized, 693/// return null, otherwise return a pointer to the slot it would take. If a 694/// node already exists with these operands, the slot will be non-null. 695SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, SDValue Op, 696 void *&InsertPos) { 697 if (N->getValueType(0) == MVT::Flag) 698 return 0; // Never CSE anything that produces a flag. 699 700 switch (N->getOpcode()) { 701 default: break; 702 case ISD::HANDLENODE: 703 case ISD::DBG_LABEL: 704 case ISD::DBG_STOPPOINT: 705 case ISD::EH_LABEL: 706 return 0; // Never add these nodes. 707 } 708 709 // Check that remaining values produced are not flags. 710 for (unsigned i = 1, e = N->getNumValues(); i != e; ++i) 711 if (N->getValueType(i) == MVT::Flag) 712 return 0; // Never CSE anything that produces a flag. 713 714 SDValue Ops[] = { Op }; 715 FoldingSetNodeID ID; 716 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, 1); 717 return CSEMap.FindNodeOrInsertPos(ID, InsertPos); 718} 719 720/// FindModifiedNodeSlot - Find a slot for the specified node if its operands 721/// were replaced with those specified. If this node is never memoized, 722/// return null, otherwise return a pointer to the slot it would take. If a 723/// node already exists with these operands, the slot will be non-null. 724SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, 725 SDValue Op1, SDValue Op2, 726 void *&InsertPos) { 727 if (N->getOpcode() == ISD::HANDLENODE || N->getValueType(0) == MVT::Flag) 728 729 // Check that remaining values produced are not flags. 730 for (unsigned i = 1, e = N->getNumValues(); i != e; ++i) 731 if (N->getValueType(i) == MVT::Flag) 732 return 0; // Never CSE anything that produces a flag. 733 734 SDValue Ops[] = { Op1, Op2 }; 735 FoldingSetNodeID ID; 736 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, 2); 737 return CSEMap.FindNodeOrInsertPos(ID, InsertPos); 738} 739 740 741/// FindModifiedNodeSlot - Find a slot for the specified node if its operands 742/// were replaced with those specified. If this node is never memoized, 743/// return null, otherwise return a pointer to the slot it would take. If a 744/// node already exists with these operands, the slot will be non-null. 745SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, 746 const SDValue *Ops,unsigned NumOps, 747 void *&InsertPos) { 748 if (N->getValueType(0) == MVT::Flag) 749 return 0; // Never CSE anything that produces a flag. 750 751 switch (N->getOpcode()) { 752 default: break; 753 case ISD::HANDLENODE: 754 case ISD::DBG_LABEL: 755 case ISD::DBG_STOPPOINT: 756 case ISD::EH_LABEL: 757 case ISD::DECLARE: 758 return 0; // Never add these nodes. 759 } 760 761 // Check that remaining values produced are not flags. 762 for (unsigned i = 1, e = N->getNumValues(); i != e; ++i) 763 if (N->getValueType(i) == MVT::Flag) 764 return 0; // Never CSE anything that produces a flag. 765 766 FoldingSetNodeID ID; 767 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, NumOps); 768 769 if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 770 ID.AddInteger(LD->getAddressingMode()); 771 ID.AddInteger(LD->getExtensionType()); 772 ID.AddInteger(LD->getMemoryVT().getRawBits()); 773 ID.AddInteger(LD->getRawFlags()); 774 } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 775 ID.AddInteger(ST->getAddressingMode()); 776 ID.AddInteger(ST->isTruncatingStore()); 777 ID.AddInteger(ST->getMemoryVT().getRawBits()); 778 ID.AddInteger(ST->getRawFlags()); 779 } 780 781 return CSEMap.FindNodeOrInsertPos(ID, InsertPos); 782} 783 784/// VerifyNode - Sanity check the given node. Aborts if it is invalid. 785void SelectionDAG::VerifyNode(SDNode *N) { 786 switch (N->getOpcode()) { 787 default: 788 break; 789 case ISD::BUILD_VECTOR: { 790 assert(N->getNumValues() == 1 && "Too many results for BUILD_VECTOR!"); 791 assert(N->getValueType(0).isVector() && "Wrong BUILD_VECTOR return type!"); 792 assert(N->getNumOperands() == N->getValueType(0).getVectorNumElements() && 793 "Wrong number of BUILD_VECTOR operands!"); 794 MVT EltVT = N->getValueType(0).getVectorElementType(); 795 for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ++I) 796 assert(I->getSDValue().getValueType() == EltVT && 797 "Wrong BUILD_VECTOR operand type!"); 798 break; 799 } 800 } 801} 802 803/// getMVTAlignment - Compute the default alignment value for the 804/// given type. 805/// 806unsigned SelectionDAG::getMVTAlignment(MVT VT) const { 807 const Type *Ty = VT == MVT::iPTR ? 808 PointerType::get(Type::Int8Ty, 0) : 809 VT.getTypeForMVT(); 810 811 return TLI.getTargetData()->getABITypeAlignment(Ty); 812} 813 814SelectionDAG::SelectionDAG(TargetLowering &tli, FunctionLoweringInfo &fli) 815 : TLI(tli), FLI(fli), 816 EntryNode(ISD::EntryToken, getVTList(MVT::Other)), 817 Root(getEntryNode()) { 818 AllNodes.push_back(&EntryNode); 819} 820 821void SelectionDAG::init(MachineFunction &mf, MachineModuleInfo *mmi) { 822 MF = &mf; 823 MMI = mmi; 824} 825 826SelectionDAG::~SelectionDAG() { 827 allnodes_clear(); 828} 829 830void SelectionDAG::allnodes_clear() { 831 assert(&*AllNodes.begin() == &EntryNode); 832 AllNodes.remove(AllNodes.begin()); 833 while (!AllNodes.empty()) { 834 SDNode *N = AllNodes.remove(AllNodes.begin()); 835 N->SetNextInBucket(0); 836 if (N->OperandsNeedDelete) 837 delete [] N->OperandList; 838 NodeAllocator.Deallocate(N); 839 } 840} 841 842void SelectionDAG::clear() { 843 allnodes_clear(); 844 OperandAllocator.Reset(); 845 CSEMap.clear(); 846 847 ExtendedValueTypeNodes.clear(); 848 ExternalSymbols.clear(); 849 TargetExternalSymbols.clear(); 850 std::fill(CondCodeNodes.begin(), CondCodeNodes.end(), 851 static_cast<CondCodeSDNode*>(0)); 852 std::fill(ValueTypeNodes.begin(), ValueTypeNodes.end(), 853 static_cast<SDNode*>(0)); 854 855 EntryNode.Uses = 0; 856 AllNodes.push_back(&EntryNode); 857 Root = getEntryNode(); 858} 859 860SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, MVT VT) { 861 if (Op.getValueType() == VT) return Op; 862 APInt Imm = APInt::getLowBitsSet(Op.getValueSizeInBits(), 863 VT.getSizeInBits()); 864 return getNode(ISD::AND, Op.getValueType(), Op, 865 getConstant(Imm, Op.getValueType())); 866} 867 868SDValue SelectionDAG::getConstant(uint64_t Val, MVT VT, bool isT) { 869 MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 870 return getConstant(APInt(EltVT.getSizeInBits(), Val), VT, isT); 871} 872 873SDValue SelectionDAG::getConstant(const APInt &Val, MVT VT, bool isT) { 874 return getConstant(*ConstantInt::get(Val), VT, isT); 875} 876 877SDValue SelectionDAG::getConstant(const ConstantInt &Val, MVT VT, bool isT) { 878 assert(VT.isInteger() && "Cannot create FP integer constant!"); 879 880 MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 881 assert(Val.getBitWidth() == EltVT.getSizeInBits() && 882 "APInt size does not match type size!"); 883 884 unsigned Opc = isT ? ISD::TargetConstant : ISD::Constant; 885 FoldingSetNodeID ID; 886 AddNodeIDNode(ID, Opc, getVTList(EltVT), 0, 0); 887 ID.AddPointer(&Val); 888 void *IP = 0; 889 SDNode *N = NULL; 890 if ((N = CSEMap.FindNodeOrInsertPos(ID, IP))) 891 if (!VT.isVector()) 892 return SDValue(N, 0); 893 if (!N) { 894 N = NodeAllocator.Allocate<ConstantSDNode>(); 895 new (N) ConstantSDNode(isT, &Val, EltVT); 896 CSEMap.InsertNode(N, IP); 897 AllNodes.push_back(N); 898 } 899 900 SDValue Result(N, 0); 901 if (VT.isVector()) { 902 SmallVector<SDValue, 8> Ops; 903 Ops.assign(VT.getVectorNumElements(), Result); 904 Result = getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 905 } 906 return Result; 907} 908 909SDValue SelectionDAG::getIntPtrConstant(uint64_t Val, bool isTarget) { 910 return getConstant(Val, TLI.getPointerTy(), isTarget); 911} 912 913 914SDValue SelectionDAG::getConstantFP(const APFloat& V, MVT VT, bool isTarget) { 915 return getConstantFP(*ConstantFP::get(V), VT, isTarget); 916} 917 918SDValue SelectionDAG::getConstantFP(const ConstantFP& V, MVT VT, bool isTarget){ 919 assert(VT.isFloatingPoint() && "Cannot create integer FP constant!"); 920 921 MVT EltVT = 922 VT.isVector() ? VT.getVectorElementType() : VT; 923 924 // Do the map lookup using the actual bit pattern for the floating point 925 // value, so that we don't have problems with 0.0 comparing equal to -0.0, and 926 // we don't have issues with SNANs. 927 unsigned Opc = isTarget ? ISD::TargetConstantFP : ISD::ConstantFP; 928 FoldingSetNodeID ID; 929 AddNodeIDNode(ID, Opc, getVTList(EltVT), 0, 0); 930 ID.AddPointer(&V); 931 void *IP = 0; 932 SDNode *N = NULL; 933 if ((N = CSEMap.FindNodeOrInsertPos(ID, IP))) 934 if (!VT.isVector()) 935 return SDValue(N, 0); 936 if (!N) { 937 N = NodeAllocator.Allocate<ConstantFPSDNode>(); 938 new (N) ConstantFPSDNode(isTarget, &V, EltVT); 939 CSEMap.InsertNode(N, IP); 940 AllNodes.push_back(N); 941 } 942 943 SDValue Result(N, 0); 944 if (VT.isVector()) { 945 SmallVector<SDValue, 8> Ops; 946 Ops.assign(VT.getVectorNumElements(), Result); 947 Result = getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 948 } 949 return Result; 950} 951 952SDValue SelectionDAG::getConstantFP(double Val, MVT VT, bool isTarget) { 953 MVT EltVT = 954 VT.isVector() ? VT.getVectorElementType() : VT; 955 if (EltVT==MVT::f32) 956 return getConstantFP(APFloat((float)Val), VT, isTarget); 957 else 958 return getConstantFP(APFloat(Val), VT, isTarget); 959} 960 961SDValue SelectionDAG::getGlobalAddress(const GlobalValue *GV, 962 MVT VT, int64_t Offset, 963 bool isTargetGA) { 964 unsigned Opc; 965 966 // Truncate (with sign-extension) the offset value to the pointer size. 967 unsigned BitWidth = VT.getSizeInBits(); 968 if (BitWidth < 64) 969 Offset = (Offset << (64 - BitWidth) >> (64 - BitWidth)); 970 971 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV); 972 if (!GVar) { 973 // If GV is an alias then use the aliasee for determining thread-localness. 974 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) 975 GVar = dyn_cast_or_null<GlobalVariable>(GA->resolveAliasedGlobal(false)); 976 } 977 978 if (GVar && GVar->isThreadLocal()) 979 Opc = isTargetGA ? ISD::TargetGlobalTLSAddress : ISD::GlobalTLSAddress; 980 else 981 Opc = isTargetGA ? ISD::TargetGlobalAddress : ISD::GlobalAddress; 982 983 FoldingSetNodeID ID; 984 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 985 ID.AddPointer(GV); 986 ID.AddInteger(Offset); 987 void *IP = 0; 988 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 989 return SDValue(E, 0); 990 SDNode *N = NodeAllocator.Allocate<GlobalAddressSDNode>(); 991 new (N) GlobalAddressSDNode(isTargetGA, GV, VT, Offset); 992 CSEMap.InsertNode(N, IP); 993 AllNodes.push_back(N); 994 return SDValue(N, 0); 995} 996 997SDValue SelectionDAG::getFrameIndex(int FI, MVT VT, bool isTarget) { 998 unsigned Opc = isTarget ? ISD::TargetFrameIndex : ISD::FrameIndex; 999 FoldingSetNodeID ID; 1000 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 1001 ID.AddInteger(FI); 1002 void *IP = 0; 1003 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1004 return SDValue(E, 0); 1005 SDNode *N = NodeAllocator.Allocate<FrameIndexSDNode>(); 1006 new (N) FrameIndexSDNode(FI, VT, isTarget); 1007 CSEMap.InsertNode(N, IP); 1008 AllNodes.push_back(N); 1009 return SDValue(N, 0); 1010} 1011 1012SDValue SelectionDAG::getJumpTable(int JTI, MVT VT, bool isTarget){ 1013 unsigned Opc = isTarget ? ISD::TargetJumpTable : ISD::JumpTable; 1014 FoldingSetNodeID ID; 1015 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 1016 ID.AddInteger(JTI); 1017 void *IP = 0; 1018 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1019 return SDValue(E, 0); 1020 SDNode *N = NodeAllocator.Allocate<JumpTableSDNode>(); 1021 new (N) JumpTableSDNode(JTI, VT, isTarget); 1022 CSEMap.InsertNode(N, IP); 1023 AllNodes.push_back(N); 1024 return SDValue(N, 0); 1025} 1026 1027SDValue SelectionDAG::getConstantPool(Constant *C, MVT VT, 1028 unsigned Alignment, int Offset, 1029 bool isTarget) { 1030 if (Alignment == 0) 1031 Alignment = 1032 TLI.getTargetData()->getPreferredTypeAlignmentShift(C->getType()); 1033 unsigned Opc = isTarget ? ISD::TargetConstantPool : ISD::ConstantPool; 1034 FoldingSetNodeID ID; 1035 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 1036 ID.AddInteger(Alignment); 1037 ID.AddInteger(Offset); 1038 ID.AddPointer(C); 1039 void *IP = 0; 1040 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1041 return SDValue(E, 0); 1042 SDNode *N = NodeAllocator.Allocate<ConstantPoolSDNode>(); 1043 new (N) ConstantPoolSDNode(isTarget, C, VT, Offset, Alignment); 1044 CSEMap.InsertNode(N, IP); 1045 AllNodes.push_back(N); 1046 return SDValue(N, 0); 1047} 1048 1049 1050SDValue SelectionDAG::getConstantPool(MachineConstantPoolValue *C, MVT VT, 1051 unsigned Alignment, int Offset, 1052 bool isTarget) { 1053 if (Alignment == 0) 1054 Alignment = 1055 TLI.getTargetData()->getPreferredTypeAlignmentShift(C->getType()); 1056 unsigned Opc = isTarget ? ISD::TargetConstantPool : ISD::ConstantPool; 1057 FoldingSetNodeID ID; 1058 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 1059 ID.AddInteger(Alignment); 1060 ID.AddInteger(Offset); 1061 C->AddSelectionDAGCSEId(ID); 1062 void *IP = 0; 1063 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1064 return SDValue(E, 0); 1065 SDNode *N = NodeAllocator.Allocate<ConstantPoolSDNode>(); 1066 new (N) ConstantPoolSDNode(isTarget, C, VT, Offset, Alignment); 1067 CSEMap.InsertNode(N, IP); 1068 AllNodes.push_back(N); 1069 return SDValue(N, 0); 1070} 1071 1072 1073SDValue SelectionDAG::getBasicBlock(MachineBasicBlock *MBB) { 1074 FoldingSetNodeID ID; 1075 AddNodeIDNode(ID, ISD::BasicBlock, getVTList(MVT::Other), 0, 0); 1076 ID.AddPointer(MBB); 1077 void *IP = 0; 1078 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1079 return SDValue(E, 0); 1080 SDNode *N = NodeAllocator.Allocate<BasicBlockSDNode>(); 1081 new (N) BasicBlockSDNode(MBB); 1082 CSEMap.InsertNode(N, IP); 1083 AllNodes.push_back(N); 1084 return SDValue(N, 0); 1085} 1086 1087SDValue SelectionDAG::getArgFlags(ISD::ArgFlagsTy Flags) { 1088 FoldingSetNodeID ID; 1089 AddNodeIDNode(ID, ISD::ARG_FLAGS, getVTList(MVT::Other), 0, 0); 1090 ID.AddInteger(Flags.getRawBits()); 1091 void *IP = 0; 1092 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1093 return SDValue(E, 0); 1094 SDNode *N = NodeAllocator.Allocate<ARG_FLAGSSDNode>(); 1095 new (N) ARG_FLAGSSDNode(Flags); 1096 CSEMap.InsertNode(N, IP); 1097 AllNodes.push_back(N); 1098 return SDValue(N, 0); 1099} 1100 1101SDValue SelectionDAG::getValueType(MVT VT) { 1102 if (VT.isSimple() && (unsigned)VT.getSimpleVT() >= ValueTypeNodes.size()) 1103 ValueTypeNodes.resize(VT.getSimpleVT()+1); 1104 1105 SDNode *&N = VT.isExtended() ? 1106 ExtendedValueTypeNodes[VT] : ValueTypeNodes[VT.getSimpleVT()]; 1107 1108 if (N) return SDValue(N, 0); 1109 N = NodeAllocator.Allocate<VTSDNode>(); 1110 new (N) VTSDNode(VT); 1111 AllNodes.push_back(N); 1112 return SDValue(N, 0); 1113} 1114 1115SDValue SelectionDAG::getExternalSymbol(const char *Sym, MVT VT) { 1116 SDNode *&N = ExternalSymbols[Sym]; 1117 if (N) return SDValue(N, 0); 1118 N = NodeAllocator.Allocate<ExternalSymbolSDNode>(); 1119 new (N) ExternalSymbolSDNode(false, Sym, VT); 1120 AllNodes.push_back(N); 1121 return SDValue(N, 0); 1122} 1123 1124SDValue SelectionDAG::getTargetExternalSymbol(const char *Sym, MVT VT) { 1125 SDNode *&N = TargetExternalSymbols[Sym]; 1126 if (N) return SDValue(N, 0); 1127 N = NodeAllocator.Allocate<ExternalSymbolSDNode>(); 1128 new (N) ExternalSymbolSDNode(true, Sym, VT); 1129 AllNodes.push_back(N); 1130 return SDValue(N, 0); 1131} 1132 1133SDValue SelectionDAG::getCondCode(ISD::CondCode Cond) { 1134 if ((unsigned)Cond >= CondCodeNodes.size()) 1135 CondCodeNodes.resize(Cond+1); 1136 1137 if (CondCodeNodes[Cond] == 0) { 1138 CondCodeSDNode *N = NodeAllocator.Allocate<CondCodeSDNode>(); 1139 new (N) CondCodeSDNode(Cond); 1140 CondCodeNodes[Cond] = N; 1141 AllNodes.push_back(N); 1142 } 1143 return SDValue(CondCodeNodes[Cond], 0); 1144} 1145 1146SDValue SelectionDAG::getRegister(unsigned RegNo, MVT VT) { 1147 FoldingSetNodeID ID; 1148 AddNodeIDNode(ID, ISD::Register, getVTList(VT), 0, 0); 1149 ID.AddInteger(RegNo); 1150 void *IP = 0; 1151 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1152 return SDValue(E, 0); 1153 SDNode *N = NodeAllocator.Allocate<RegisterSDNode>(); 1154 new (N) RegisterSDNode(RegNo, VT); 1155 CSEMap.InsertNode(N, IP); 1156 AllNodes.push_back(N); 1157 return SDValue(N, 0); 1158} 1159 1160SDValue SelectionDAG::getDbgStopPoint(SDValue Root, 1161 unsigned Line, unsigned Col, 1162 const CompileUnitDesc *CU) { 1163 SDNode *N = NodeAllocator.Allocate<DbgStopPointSDNode>(); 1164 new (N) DbgStopPointSDNode(Root, Line, Col, CU); 1165 AllNodes.push_back(N); 1166 return SDValue(N, 0); 1167} 1168 1169SDValue SelectionDAG::getLabel(unsigned Opcode, 1170 SDValue Root, 1171 unsigned LabelID) { 1172 FoldingSetNodeID ID; 1173 SDValue Ops[] = { Root }; 1174 AddNodeIDNode(ID, Opcode, getVTList(MVT::Other), &Ops[0], 1); 1175 ID.AddInteger(LabelID); 1176 void *IP = 0; 1177 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1178 return SDValue(E, 0); 1179 SDNode *N = NodeAllocator.Allocate<LabelSDNode>(); 1180 new (N) LabelSDNode(Opcode, Root, LabelID); 1181 CSEMap.InsertNode(N, IP); 1182 AllNodes.push_back(N); 1183 return SDValue(N, 0); 1184} 1185 1186SDValue SelectionDAG::getSrcValue(const Value *V) { 1187 assert((!V || isa<PointerType>(V->getType())) && 1188 "SrcValue is not a pointer?"); 1189 1190 FoldingSetNodeID ID; 1191 AddNodeIDNode(ID, ISD::SRCVALUE, getVTList(MVT::Other), 0, 0); 1192 ID.AddPointer(V); 1193 1194 void *IP = 0; 1195 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1196 return SDValue(E, 0); 1197 1198 SDNode *N = NodeAllocator.Allocate<SrcValueSDNode>(); 1199 new (N) SrcValueSDNode(V); 1200 CSEMap.InsertNode(N, IP); 1201 AllNodes.push_back(N); 1202 return SDValue(N, 0); 1203} 1204 1205SDValue SelectionDAG::getMemOperand(const MachineMemOperand &MO) { 1206 const Value *v = MO.getValue(); 1207 assert((!v || isa<PointerType>(v->getType())) && 1208 "SrcValue is not a pointer?"); 1209 1210 FoldingSetNodeID ID; 1211 AddNodeIDNode(ID, ISD::MEMOPERAND, getVTList(MVT::Other), 0, 0); 1212 MO.Profile(ID); 1213 1214 void *IP = 0; 1215 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1216 return SDValue(E, 0); 1217 1218 SDNode *N = NodeAllocator.Allocate<MemOperandSDNode>(); 1219 new (N) MemOperandSDNode(MO); 1220 CSEMap.InsertNode(N, IP); 1221 AllNodes.push_back(N); 1222 return SDValue(N, 0); 1223} 1224 1225/// CreateStackTemporary - Create a stack temporary, suitable for holding the 1226/// specified value type. 1227SDValue SelectionDAG::CreateStackTemporary(MVT VT, unsigned minAlign) { 1228 MachineFrameInfo *FrameInfo = getMachineFunction().getFrameInfo(); 1229 unsigned ByteSize = VT.getSizeInBits()/8; 1230 const Type *Ty = VT.getTypeForMVT(); 1231 unsigned StackAlign = 1232 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), minAlign); 1233 1234 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, StackAlign); 1235 return getFrameIndex(FrameIdx, TLI.getPointerTy()); 1236} 1237 1238SDValue SelectionDAG::FoldSetCC(MVT VT, SDValue N1, 1239 SDValue N2, ISD::CondCode Cond) { 1240 // These setcc operations always fold. 1241 switch (Cond) { 1242 default: break; 1243 case ISD::SETFALSE: 1244 case ISD::SETFALSE2: return getConstant(0, VT); 1245 case ISD::SETTRUE: 1246 case ISD::SETTRUE2: return getConstant(1, VT); 1247 1248 case ISD::SETOEQ: 1249 case ISD::SETOGT: 1250 case ISD::SETOGE: 1251 case ISD::SETOLT: 1252 case ISD::SETOLE: 1253 case ISD::SETONE: 1254 case ISD::SETO: 1255 case ISD::SETUO: 1256 case ISD::SETUEQ: 1257 case ISD::SETUNE: 1258 assert(!N1.getValueType().isInteger() && "Illegal setcc for integer!"); 1259 break; 1260 } 1261 1262 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode())) { 1263 const APInt &C2 = N2C->getAPIntValue(); 1264 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) { 1265 const APInt &C1 = N1C->getAPIntValue(); 1266 1267 switch (Cond) { 1268 default: assert(0 && "Unknown integer setcc!"); 1269 case ISD::SETEQ: return getConstant(C1 == C2, VT); 1270 case ISD::SETNE: return getConstant(C1 != C2, VT); 1271 case ISD::SETULT: return getConstant(C1.ult(C2), VT); 1272 case ISD::SETUGT: return getConstant(C1.ugt(C2), VT); 1273 case ISD::SETULE: return getConstant(C1.ule(C2), VT); 1274 case ISD::SETUGE: return getConstant(C1.uge(C2), VT); 1275 case ISD::SETLT: return getConstant(C1.slt(C2), VT); 1276 case ISD::SETGT: return getConstant(C1.sgt(C2), VT); 1277 case ISD::SETLE: return getConstant(C1.sle(C2), VT); 1278 case ISD::SETGE: return getConstant(C1.sge(C2), VT); 1279 } 1280 } 1281 } 1282 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.getNode())) { 1283 if (ConstantFPSDNode *N2C = dyn_cast<ConstantFPSDNode>(N2.getNode())) { 1284 // No compile time operations on this type yet. 1285 if (N1C->getValueType(0) == MVT::ppcf128) 1286 return SDValue(); 1287 1288 APFloat::cmpResult R = N1C->getValueAPF().compare(N2C->getValueAPF()); 1289 switch (Cond) { 1290 default: break; 1291 case ISD::SETEQ: if (R==APFloat::cmpUnordered) 1292 return getNode(ISD::UNDEF, VT); 1293 // fall through 1294 case ISD::SETOEQ: return getConstant(R==APFloat::cmpEqual, VT); 1295 case ISD::SETNE: if (R==APFloat::cmpUnordered) 1296 return getNode(ISD::UNDEF, VT); 1297 // fall through 1298 case ISD::SETONE: return getConstant(R==APFloat::cmpGreaterThan || 1299 R==APFloat::cmpLessThan, VT); 1300 case ISD::SETLT: if (R==APFloat::cmpUnordered) 1301 return getNode(ISD::UNDEF, VT); 1302 // fall through 1303 case ISD::SETOLT: return getConstant(R==APFloat::cmpLessThan, VT); 1304 case ISD::SETGT: if (R==APFloat::cmpUnordered) 1305 return getNode(ISD::UNDEF, VT); 1306 // fall through 1307 case ISD::SETOGT: return getConstant(R==APFloat::cmpGreaterThan, VT); 1308 case ISD::SETLE: if (R==APFloat::cmpUnordered) 1309 return getNode(ISD::UNDEF, VT); 1310 // fall through 1311 case ISD::SETOLE: return getConstant(R==APFloat::cmpLessThan || 1312 R==APFloat::cmpEqual, VT); 1313 case ISD::SETGE: if (R==APFloat::cmpUnordered) 1314 return getNode(ISD::UNDEF, VT); 1315 // fall through 1316 case ISD::SETOGE: return getConstant(R==APFloat::cmpGreaterThan || 1317 R==APFloat::cmpEqual, VT); 1318 case ISD::SETO: return getConstant(R!=APFloat::cmpUnordered, VT); 1319 case ISD::SETUO: return getConstant(R==APFloat::cmpUnordered, VT); 1320 case ISD::SETUEQ: return getConstant(R==APFloat::cmpUnordered || 1321 R==APFloat::cmpEqual, VT); 1322 case ISD::SETUNE: return getConstant(R!=APFloat::cmpEqual, VT); 1323 case ISD::SETULT: return getConstant(R==APFloat::cmpUnordered || 1324 R==APFloat::cmpLessThan, VT); 1325 case ISD::SETUGT: return getConstant(R==APFloat::cmpGreaterThan || 1326 R==APFloat::cmpUnordered, VT); 1327 case ISD::SETULE: return getConstant(R!=APFloat::cmpGreaterThan, VT); 1328 case ISD::SETUGE: return getConstant(R!=APFloat::cmpLessThan, VT); 1329 } 1330 } else { 1331 // Ensure that the constant occurs on the RHS. 1332 return getSetCC(VT, N2, N1, ISD::getSetCCSwappedOperands(Cond)); 1333 } 1334 } 1335 1336 // Could not fold it. 1337 return SDValue(); 1338} 1339 1340/// SignBitIsZero - Return true if the sign bit of Op is known to be zero. We 1341/// use this predicate to simplify operations downstream. 1342bool SelectionDAG::SignBitIsZero(SDValue Op, unsigned Depth) const { 1343 unsigned BitWidth = Op.getValueSizeInBits(); 1344 return MaskedValueIsZero(Op, APInt::getSignBit(BitWidth), Depth); 1345} 1346 1347/// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero. We use 1348/// this predicate to simplify operations downstream. Mask is known to be zero 1349/// for bits that V cannot have. 1350bool SelectionDAG::MaskedValueIsZero(SDValue Op, const APInt &Mask, 1351 unsigned Depth) const { 1352 APInt KnownZero, KnownOne; 1353 ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth); 1354 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1355 return (KnownZero & Mask) == Mask; 1356} 1357 1358/// ComputeMaskedBits - Determine which of the bits specified in Mask are 1359/// known to be either zero or one and return them in the KnownZero/KnownOne 1360/// bitsets. This code only analyzes bits in Mask, in order to short-circuit 1361/// processing. 1362void SelectionDAG::ComputeMaskedBits(SDValue Op, const APInt &Mask, 1363 APInt &KnownZero, APInt &KnownOne, 1364 unsigned Depth) const { 1365 unsigned BitWidth = Mask.getBitWidth(); 1366 assert(BitWidth == Op.getValueType().getSizeInBits() && 1367 "Mask size mismatches value type size!"); 1368 1369 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything. 1370 if (Depth == 6 || Mask == 0) 1371 return; // Limit search depth. 1372 1373 APInt KnownZero2, KnownOne2; 1374 1375 switch (Op.getOpcode()) { 1376 case ISD::Constant: 1377 // We know all of the bits for a constant! 1378 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & Mask; 1379 KnownZero = ~KnownOne & Mask; 1380 return; 1381 case ISD::AND: 1382 // If either the LHS or the RHS are Zero, the result is zero. 1383 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1384 ComputeMaskedBits(Op.getOperand(0), Mask & ~KnownZero, 1385 KnownZero2, KnownOne2, Depth+1); 1386 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1387 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1388 1389 // Output known-1 bits are only known if set in both the LHS & RHS. 1390 KnownOne &= KnownOne2; 1391 // Output known-0 are known to be clear if zero in either the LHS | RHS. 1392 KnownZero |= KnownZero2; 1393 return; 1394 case ISD::OR: 1395 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1396 ComputeMaskedBits(Op.getOperand(0), Mask & ~KnownOne, 1397 KnownZero2, KnownOne2, Depth+1); 1398 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1399 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1400 1401 // Output known-0 bits are only known if clear in both the LHS & RHS. 1402 KnownZero &= KnownZero2; 1403 // Output known-1 are known to be set if set in either the LHS | RHS. 1404 KnownOne |= KnownOne2; 1405 return; 1406 case ISD::XOR: { 1407 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1408 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1); 1409 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1410 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1411 1412 // Output known-0 bits are known if clear or set in both the LHS & RHS. 1413 APInt KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 1414 // Output known-1 are known to be set if set in only one of the LHS, RHS. 1415 KnownOne = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 1416 KnownZero = KnownZeroOut; 1417 return; 1418 } 1419 case ISD::MUL: { 1420 APInt Mask2 = APInt::getAllOnesValue(BitWidth); 1421 ComputeMaskedBits(Op.getOperand(1), Mask2, KnownZero, KnownOne, Depth+1); 1422 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero2, KnownOne2, Depth+1); 1423 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1424 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1425 1426 // If low bits are zero in either operand, output low known-0 bits. 1427 // Also compute a conserative estimate for high known-0 bits. 1428 // More trickiness is possible, but this is sufficient for the 1429 // interesting case of alignment computation. 1430 KnownOne.clear(); 1431 unsigned TrailZ = KnownZero.countTrailingOnes() + 1432 KnownZero2.countTrailingOnes(); 1433 unsigned LeadZ = std::max(KnownZero.countLeadingOnes() + 1434 KnownZero2.countLeadingOnes(), 1435 BitWidth) - BitWidth; 1436 1437 TrailZ = std::min(TrailZ, BitWidth); 1438 LeadZ = std::min(LeadZ, BitWidth); 1439 KnownZero = APInt::getLowBitsSet(BitWidth, TrailZ) | 1440 APInt::getHighBitsSet(BitWidth, LeadZ); 1441 KnownZero &= Mask; 1442 return; 1443 } 1444 case ISD::UDIV: { 1445 // For the purposes of computing leading zeros we can conservatively 1446 // treat a udiv as a logical right shift by the power of 2 known to 1447 // be less than the denominator. 1448 APInt AllOnes = APInt::getAllOnesValue(BitWidth); 1449 ComputeMaskedBits(Op.getOperand(0), 1450 AllOnes, KnownZero2, KnownOne2, Depth+1); 1451 unsigned LeadZ = KnownZero2.countLeadingOnes(); 1452 1453 KnownOne2.clear(); 1454 KnownZero2.clear(); 1455 ComputeMaskedBits(Op.getOperand(1), 1456 AllOnes, KnownZero2, KnownOne2, Depth+1); 1457 unsigned RHSUnknownLeadingOnes = KnownOne2.countLeadingZeros(); 1458 if (RHSUnknownLeadingOnes != BitWidth) 1459 LeadZ = std::min(BitWidth, 1460 LeadZ + BitWidth - RHSUnknownLeadingOnes - 1); 1461 1462 KnownZero = APInt::getHighBitsSet(BitWidth, LeadZ) & Mask; 1463 return; 1464 } 1465 case ISD::SELECT: 1466 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero, KnownOne, Depth+1); 1467 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero2, KnownOne2, Depth+1); 1468 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1469 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1470 1471 // Only known if known in both the LHS and RHS. 1472 KnownOne &= KnownOne2; 1473 KnownZero &= KnownZero2; 1474 return; 1475 case ISD::SELECT_CC: 1476 ComputeMaskedBits(Op.getOperand(3), Mask, KnownZero, KnownOne, Depth+1); 1477 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero2, KnownOne2, Depth+1); 1478 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1479 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1480 1481 // Only known if known in both the LHS and RHS. 1482 KnownOne &= KnownOne2; 1483 KnownZero &= KnownZero2; 1484 return; 1485 case ISD::SETCC: 1486 // If we know the result of a setcc has the top bits zero, use this info. 1487 if (TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult && 1488 BitWidth > 1) 1489 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1); 1490 return; 1491 case ISD::SHL: 1492 // (shl X, C1) & C2 == 0 iff (X & C2 >>u C1) == 0 1493 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1494 unsigned ShAmt = SA->getZExtValue(); 1495 1496 // If the shift count is an invalid immediate, don't do anything. 1497 if (ShAmt >= BitWidth) 1498 return; 1499 1500 ComputeMaskedBits(Op.getOperand(0), Mask.lshr(ShAmt), 1501 KnownZero, KnownOne, Depth+1); 1502 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1503 KnownZero <<= ShAmt; 1504 KnownOne <<= ShAmt; 1505 // low bits known zero. 1506 KnownZero |= APInt::getLowBitsSet(BitWidth, ShAmt); 1507 } 1508 return; 1509 case ISD::SRL: 1510 // (ushr X, C1) & C2 == 0 iff (-1 >> C1) & C2 == 0 1511 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1512 unsigned ShAmt = SA->getZExtValue(); 1513 1514 // If the shift count is an invalid immediate, don't do anything. 1515 if (ShAmt >= BitWidth) 1516 return; 1517 1518 ComputeMaskedBits(Op.getOperand(0), (Mask << ShAmt), 1519 KnownZero, KnownOne, Depth+1); 1520 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1521 KnownZero = KnownZero.lshr(ShAmt); 1522 KnownOne = KnownOne.lshr(ShAmt); 1523 1524 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt) & Mask; 1525 KnownZero |= HighBits; // High bits known zero. 1526 } 1527 return; 1528 case ISD::SRA: 1529 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1530 unsigned ShAmt = SA->getZExtValue(); 1531 1532 // If the shift count is an invalid immediate, don't do anything. 1533 if (ShAmt >= BitWidth) 1534 return; 1535 1536 APInt InDemandedMask = (Mask << ShAmt); 1537 // If any of the demanded bits are produced by the sign extension, we also 1538 // demand the input sign bit. 1539 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt) & Mask; 1540 if (HighBits.getBoolValue()) 1541 InDemandedMask |= APInt::getSignBit(BitWidth); 1542 1543 ComputeMaskedBits(Op.getOperand(0), InDemandedMask, KnownZero, KnownOne, 1544 Depth+1); 1545 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1546 KnownZero = KnownZero.lshr(ShAmt); 1547 KnownOne = KnownOne.lshr(ShAmt); 1548 1549 // Handle the sign bits. 1550 APInt SignBit = APInt::getSignBit(BitWidth); 1551 SignBit = SignBit.lshr(ShAmt); // Adjust to where it is now in the mask. 1552 1553 if (KnownZero.intersects(SignBit)) { 1554 KnownZero |= HighBits; // New bits are known zero. 1555 } else if (KnownOne.intersects(SignBit)) { 1556 KnownOne |= HighBits; // New bits are known one. 1557 } 1558 } 1559 return; 1560 case ISD::SIGN_EXTEND_INREG: { 1561 MVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1562 unsigned EBits = EVT.getSizeInBits(); 1563 1564 // Sign extension. Compute the demanded bits in the result that are not 1565 // present in the input. 1566 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - EBits) & Mask; 1567 1568 APInt InSignBit = APInt::getSignBit(EBits); 1569 APInt InputDemandedBits = Mask & APInt::getLowBitsSet(BitWidth, EBits); 1570 1571 // If the sign extended bits are demanded, we know that the sign 1572 // bit is demanded. 1573 InSignBit.zext(BitWidth); 1574 if (NewBits.getBoolValue()) 1575 InputDemandedBits |= InSignBit; 1576 1577 ComputeMaskedBits(Op.getOperand(0), InputDemandedBits, 1578 KnownZero, KnownOne, Depth+1); 1579 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1580 1581 // If the sign bit of the input is known set or clear, then we know the 1582 // top bits of the result. 1583 if (KnownZero.intersects(InSignBit)) { // Input sign bit known clear 1584 KnownZero |= NewBits; 1585 KnownOne &= ~NewBits; 1586 } else if (KnownOne.intersects(InSignBit)) { // Input sign bit known set 1587 KnownOne |= NewBits; 1588 KnownZero &= ~NewBits; 1589 } else { // Input sign bit unknown 1590 KnownZero &= ~NewBits; 1591 KnownOne &= ~NewBits; 1592 } 1593 return; 1594 } 1595 case ISD::CTTZ: 1596 case ISD::CTLZ: 1597 case ISD::CTPOP: { 1598 unsigned LowBits = Log2_32(BitWidth)+1; 1599 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - LowBits); 1600 KnownOne.clear(); 1601 return; 1602 } 1603 case ISD::LOAD: { 1604 if (ISD::isZEXTLoad(Op.getNode())) { 1605 LoadSDNode *LD = cast<LoadSDNode>(Op); 1606 MVT VT = LD->getMemoryVT(); 1607 unsigned MemBits = VT.getSizeInBits(); 1608 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits) & Mask; 1609 } 1610 return; 1611 } 1612 case ISD::ZERO_EXTEND: { 1613 MVT InVT = Op.getOperand(0).getValueType(); 1614 unsigned InBits = InVT.getSizeInBits(); 1615 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - InBits) & Mask; 1616 APInt InMask = Mask; 1617 InMask.trunc(InBits); 1618 KnownZero.trunc(InBits); 1619 KnownOne.trunc(InBits); 1620 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1621 KnownZero.zext(BitWidth); 1622 KnownOne.zext(BitWidth); 1623 KnownZero |= NewBits; 1624 return; 1625 } 1626 case ISD::SIGN_EXTEND: { 1627 MVT InVT = Op.getOperand(0).getValueType(); 1628 unsigned InBits = InVT.getSizeInBits(); 1629 APInt InSignBit = APInt::getSignBit(InBits); 1630 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - InBits) & Mask; 1631 APInt InMask = Mask; 1632 InMask.trunc(InBits); 1633 1634 // If any of the sign extended bits are demanded, we know that the sign 1635 // bit is demanded. Temporarily set this bit in the mask for our callee. 1636 if (NewBits.getBoolValue()) 1637 InMask |= InSignBit; 1638 1639 KnownZero.trunc(InBits); 1640 KnownOne.trunc(InBits); 1641 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1642 1643 // Note if the sign bit is known to be zero or one. 1644 bool SignBitKnownZero = KnownZero.isNegative(); 1645 bool SignBitKnownOne = KnownOne.isNegative(); 1646 assert(!(SignBitKnownZero && SignBitKnownOne) && 1647 "Sign bit can't be known to be both zero and one!"); 1648 1649 // If the sign bit wasn't actually demanded by our caller, we don't 1650 // want it set in the KnownZero and KnownOne result values. Reset the 1651 // mask and reapply it to the result values. 1652 InMask = Mask; 1653 InMask.trunc(InBits); 1654 KnownZero &= InMask; 1655 KnownOne &= InMask; 1656 1657 KnownZero.zext(BitWidth); 1658 KnownOne.zext(BitWidth); 1659 1660 // If the sign bit is known zero or one, the top bits match. 1661 if (SignBitKnownZero) 1662 KnownZero |= NewBits; 1663 else if (SignBitKnownOne) 1664 KnownOne |= NewBits; 1665 return; 1666 } 1667 case ISD::ANY_EXTEND: { 1668 MVT InVT = Op.getOperand(0).getValueType(); 1669 unsigned InBits = InVT.getSizeInBits(); 1670 APInt InMask = Mask; 1671 InMask.trunc(InBits); 1672 KnownZero.trunc(InBits); 1673 KnownOne.trunc(InBits); 1674 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1675 KnownZero.zext(BitWidth); 1676 KnownOne.zext(BitWidth); 1677 return; 1678 } 1679 case ISD::TRUNCATE: { 1680 MVT InVT = Op.getOperand(0).getValueType(); 1681 unsigned InBits = InVT.getSizeInBits(); 1682 APInt InMask = Mask; 1683 InMask.zext(InBits); 1684 KnownZero.zext(InBits); 1685 KnownOne.zext(InBits); 1686 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1687 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1688 KnownZero.trunc(BitWidth); 1689 KnownOne.trunc(BitWidth); 1690 break; 1691 } 1692 case ISD::AssertZext: { 1693 MVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1694 APInt InMask = APInt::getLowBitsSet(BitWidth, VT.getSizeInBits()); 1695 ComputeMaskedBits(Op.getOperand(0), Mask & InMask, KnownZero, 1696 KnownOne, Depth+1); 1697 KnownZero |= (~InMask) & Mask; 1698 return; 1699 } 1700 case ISD::FGETSIGN: 1701 // All bits are zero except the low bit. 1702 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - 1); 1703 return; 1704 1705 case ISD::SUB: { 1706 if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) { 1707 // We know that the top bits of C-X are clear if X contains less bits 1708 // than C (i.e. no wrap-around can happen). For example, 20-X is 1709 // positive if we can prove that X is >= 0 and < 16. 1710 if (CLHS->getAPIntValue().isNonNegative()) { 1711 unsigned NLZ = (CLHS->getAPIntValue()+1).countLeadingZeros(); 1712 // NLZ can't be BitWidth with no sign bit 1713 APInt MaskV = APInt::getHighBitsSet(BitWidth, NLZ+1); 1714 ComputeMaskedBits(Op.getOperand(1), MaskV, KnownZero2, KnownOne2, 1715 Depth+1); 1716 1717 // If all of the MaskV bits are known to be zero, then we know the 1718 // output top bits are zero, because we now know that the output is 1719 // from [0-C]. 1720 if ((KnownZero2 & MaskV) == MaskV) { 1721 unsigned NLZ2 = CLHS->getAPIntValue().countLeadingZeros(); 1722 // Top bits known zero. 1723 KnownZero = APInt::getHighBitsSet(BitWidth, NLZ2) & Mask; 1724 } 1725 } 1726 } 1727 } 1728 // fall through 1729 case ISD::ADD: { 1730 // Output known-0 bits are known if clear or set in both the low clear bits 1731 // common to both LHS & RHS. For example, 8+(X<<3) is known to have the 1732 // low 3 bits clear. 1733 APInt Mask2 = APInt::getLowBitsSet(BitWidth, Mask.countTrailingOnes()); 1734 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero2, KnownOne2, Depth+1); 1735 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1736 unsigned KnownZeroOut = KnownZero2.countTrailingOnes(); 1737 1738 ComputeMaskedBits(Op.getOperand(1), Mask2, KnownZero2, KnownOne2, Depth+1); 1739 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1740 KnownZeroOut = std::min(KnownZeroOut, 1741 KnownZero2.countTrailingOnes()); 1742 1743 KnownZero |= APInt::getLowBitsSet(BitWidth, KnownZeroOut); 1744 return; 1745 } 1746 case ISD::SREM: 1747 if (ConstantSDNode *Rem = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1748 const APInt &RA = Rem->getAPIntValue(); 1749 if (RA.isPowerOf2() || (-RA).isPowerOf2()) { 1750 APInt LowBits = RA.isStrictlyPositive() ? (RA - 1) : ~RA; 1751 APInt Mask2 = LowBits | APInt::getSignBit(BitWidth); 1752 ComputeMaskedBits(Op.getOperand(0), Mask2,KnownZero2,KnownOne2,Depth+1); 1753 1754 // If the sign bit of the first operand is zero, the sign bit of 1755 // the result is zero. If the first operand has no one bits below 1756 // the second operand's single 1 bit, its sign will be zero. 1757 if (KnownZero2[BitWidth-1] || ((KnownZero2 & LowBits) == LowBits)) 1758 KnownZero2 |= ~LowBits; 1759 1760 KnownZero |= KnownZero2 & Mask; 1761 1762 assert((KnownZero & KnownOne) == 0&&"Bits known to be one AND zero?"); 1763 } 1764 } 1765 return; 1766 case ISD::UREM: { 1767 if (ConstantSDNode *Rem = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1768 const APInt &RA = Rem->getAPIntValue(); 1769 if (RA.isPowerOf2()) { 1770 APInt LowBits = (RA - 1); 1771 APInt Mask2 = LowBits & Mask; 1772 KnownZero |= ~LowBits & Mask; 1773 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero, KnownOne,Depth+1); 1774 assert((KnownZero & KnownOne) == 0&&"Bits known to be one AND zero?"); 1775 break; 1776 } 1777 } 1778 1779 // Since the result is less than or equal to either operand, any leading 1780 // zero bits in either operand must also exist in the result. 1781 APInt AllOnes = APInt::getAllOnesValue(BitWidth); 1782 ComputeMaskedBits(Op.getOperand(0), AllOnes, KnownZero, KnownOne, 1783 Depth+1); 1784 ComputeMaskedBits(Op.getOperand(1), AllOnes, KnownZero2, KnownOne2, 1785 Depth+1); 1786 1787 uint32_t Leaders = std::max(KnownZero.countLeadingOnes(), 1788 KnownZero2.countLeadingOnes()); 1789 KnownOne.clear(); 1790 KnownZero = APInt::getHighBitsSet(BitWidth, Leaders) & Mask; 1791 return; 1792 } 1793 default: 1794 // Allow the target to implement this method for its nodes. 1795 if (Op.getOpcode() >= ISD::BUILTIN_OP_END) { 1796 case ISD::INTRINSIC_WO_CHAIN: 1797 case ISD::INTRINSIC_W_CHAIN: 1798 case ISD::INTRINSIC_VOID: 1799 TLI.computeMaskedBitsForTargetNode(Op, Mask, KnownZero, KnownOne, *this); 1800 } 1801 return; 1802 } 1803} 1804 1805/// ComputeNumSignBits - Return the number of times the sign bit of the 1806/// register is replicated into the other bits. We know that at least 1 bit 1807/// is always equal to the sign bit (itself), but other cases can give us 1808/// information. For example, immediately after an "SRA X, 2", we know that 1809/// the top 3 bits are all equal to each other, so we return 3. 1810unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, unsigned Depth) const{ 1811 MVT VT = Op.getValueType(); 1812 assert(VT.isInteger() && "Invalid VT!"); 1813 unsigned VTBits = VT.getSizeInBits(); 1814 unsigned Tmp, Tmp2; 1815 unsigned FirstAnswer = 1; 1816 1817 if (Depth == 6) 1818 return 1; // Limit search depth. 1819 1820 switch (Op.getOpcode()) { 1821 default: break; 1822 case ISD::AssertSext: 1823 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); 1824 return VTBits-Tmp+1; 1825 case ISD::AssertZext: 1826 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); 1827 return VTBits-Tmp; 1828 1829 case ISD::Constant: { 1830 const APInt &Val = cast<ConstantSDNode>(Op)->getAPIntValue(); 1831 // If negative, return # leading ones. 1832 if (Val.isNegative()) 1833 return Val.countLeadingOnes(); 1834 1835 // Return # leading zeros. 1836 return Val.countLeadingZeros(); 1837 } 1838 1839 case ISD::SIGN_EXTEND: 1840 Tmp = VTBits-Op.getOperand(0).getValueType().getSizeInBits(); 1841 return ComputeNumSignBits(Op.getOperand(0), Depth+1) + Tmp; 1842 1843 case ISD::SIGN_EXTEND_INREG: 1844 // Max of the input and what this extends. 1845 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); 1846 Tmp = VTBits-Tmp+1; 1847 1848 Tmp2 = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1849 return std::max(Tmp, Tmp2); 1850 1851 case ISD::SRA: 1852 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1853 // SRA X, C -> adds C sign bits. 1854 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1855 Tmp += C->getZExtValue(); 1856 if (Tmp > VTBits) Tmp = VTBits; 1857 } 1858 return Tmp; 1859 case ISD::SHL: 1860 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1861 // shl destroys sign bits. 1862 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1863 if (C->getZExtValue() >= VTBits || // Bad shift. 1864 C->getZExtValue() >= Tmp) break; // Shifted all sign bits out. 1865 return Tmp - C->getZExtValue(); 1866 } 1867 break; 1868 case ISD::AND: 1869 case ISD::OR: 1870 case ISD::XOR: // NOT is handled here. 1871 // Logical binary ops preserve the number of sign bits at the worst. 1872 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1873 if (Tmp != 1) { 1874 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 1875 FirstAnswer = std::min(Tmp, Tmp2); 1876 // We computed what we know about the sign bits as our first 1877 // answer. Now proceed to the generic code that uses 1878 // ComputeMaskedBits, and pick whichever answer is better. 1879 } 1880 break; 1881 1882 case ISD::SELECT: 1883 Tmp = ComputeNumSignBits(Op.getOperand(1), Depth+1); 1884 if (Tmp == 1) return 1; // Early out. 1885 Tmp2 = ComputeNumSignBits(Op.getOperand(2), Depth+1); 1886 return std::min(Tmp, Tmp2); 1887 1888 case ISD::SETCC: 1889 // If setcc returns 0/-1, all bits are sign bits. 1890 if (TLI.getSetCCResultContents() == 1891 TargetLowering::ZeroOrNegativeOneSetCCResult) 1892 return VTBits; 1893 break; 1894 case ISD::ROTL: 1895 case ISD::ROTR: 1896 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1897 unsigned RotAmt = C->getZExtValue() & (VTBits-1); 1898 1899 // Handle rotate right by N like a rotate left by 32-N. 1900 if (Op.getOpcode() == ISD::ROTR) 1901 RotAmt = (VTBits-RotAmt) & (VTBits-1); 1902 1903 // If we aren't rotating out all of the known-in sign bits, return the 1904 // number that are left. This handles rotl(sext(x), 1) for example. 1905 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1906 if (Tmp > RotAmt+1) return Tmp-RotAmt; 1907 } 1908 break; 1909 case ISD::ADD: 1910 // Add can have at most one carry bit. Thus we know that the output 1911 // is, at worst, one more bit than the inputs. 1912 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1913 if (Tmp == 1) return 1; // Early out. 1914 1915 // Special case decrementing a value (ADD X, -1): 1916 if (ConstantSDNode *CRHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) 1917 if (CRHS->isAllOnesValue()) { 1918 APInt KnownZero, KnownOne; 1919 APInt Mask = APInt::getAllOnesValue(VTBits); 1920 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1); 1921 1922 // If the input is known to be 0 or 1, the output is 0/-1, which is all 1923 // sign bits set. 1924 if ((KnownZero | APInt(VTBits, 1)) == Mask) 1925 return VTBits; 1926 1927 // If we are subtracting one from a positive number, there is no carry 1928 // out of the result. 1929 if (KnownZero.isNegative()) 1930 return Tmp; 1931 } 1932 1933 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 1934 if (Tmp2 == 1) return 1; 1935 return std::min(Tmp, Tmp2)-1; 1936 break; 1937 1938 case ISD::SUB: 1939 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 1940 if (Tmp2 == 1) return 1; 1941 1942 // Handle NEG. 1943 if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) 1944 if (CLHS->isNullValue()) { 1945 APInt KnownZero, KnownOne; 1946 APInt Mask = APInt::getAllOnesValue(VTBits); 1947 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1948 // If the input is known to be 0 or 1, the output is 0/-1, which is all 1949 // sign bits set. 1950 if ((KnownZero | APInt(VTBits, 1)) == Mask) 1951 return VTBits; 1952 1953 // If the input is known to be positive (the sign bit is known clear), 1954 // the output of the NEG has the same number of sign bits as the input. 1955 if (KnownZero.isNegative()) 1956 return Tmp2; 1957 1958 // Otherwise, we treat this like a SUB. 1959 } 1960 1961 // Sub can have at most one carry bit. Thus we know that the output 1962 // is, at worst, one more bit than the inputs. 1963 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1964 if (Tmp == 1) return 1; // Early out. 1965 return std::min(Tmp, Tmp2)-1; 1966 break; 1967 case ISD::TRUNCATE: 1968 // FIXME: it's tricky to do anything useful for this, but it is an important 1969 // case for targets like X86. 1970 break; 1971 } 1972 1973 // Handle LOADX separately here. EXTLOAD case will fallthrough. 1974 if (Op.getOpcode() == ISD::LOAD) { 1975 LoadSDNode *LD = cast<LoadSDNode>(Op); 1976 unsigned ExtType = LD->getExtensionType(); 1977 switch (ExtType) { 1978 default: break; 1979 case ISD::SEXTLOAD: // '17' bits known 1980 Tmp = LD->getMemoryVT().getSizeInBits(); 1981 return VTBits-Tmp+1; 1982 case ISD::ZEXTLOAD: // '16' bits known 1983 Tmp = LD->getMemoryVT().getSizeInBits(); 1984 return VTBits-Tmp; 1985 } 1986 } 1987 1988 // Allow the target to implement this method for its nodes. 1989 if (Op.getOpcode() >= ISD::BUILTIN_OP_END || 1990 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1991 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1992 Op.getOpcode() == ISD::INTRINSIC_VOID) { 1993 unsigned NumBits = TLI.ComputeNumSignBitsForTargetNode(Op, Depth); 1994 if (NumBits > 1) FirstAnswer = std::max(FirstAnswer, NumBits); 1995 } 1996 1997 // Finally, if we can prove that the top bits of the result are 0's or 1's, 1998 // use this information. 1999 APInt KnownZero, KnownOne; 2000 APInt Mask = APInt::getAllOnesValue(VTBits); 2001 ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth); 2002 2003 if (KnownZero.isNegative()) { // sign bit is 0 2004 Mask = KnownZero; 2005 } else if (KnownOne.isNegative()) { // sign bit is 1; 2006 Mask = KnownOne; 2007 } else { 2008 // Nothing known. 2009 return FirstAnswer; 2010 } 2011 2012 // Okay, we know that the sign bit in Mask is set. Use CLZ to determine 2013 // the number of identical bits in the top of the input value. 2014 Mask = ~Mask; 2015 Mask <<= Mask.getBitWidth()-VTBits; 2016 // Return # leading zeros. We use 'min' here in case Val was zero before 2017 // shifting. We don't want to return '64' as for an i32 "0". 2018 return std::max(FirstAnswer, std::min(VTBits, Mask.countLeadingZeros())); 2019} 2020 2021 2022bool SelectionDAG::isVerifiedDebugInfoDesc(SDValue Op) const { 2023 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op); 2024 if (!GA) return false; 2025 if (GA->getOffset() != 0) return false; 2026 GlobalVariable *GV = dyn_cast<GlobalVariable>(GA->getGlobal()); 2027 if (!GV) return false; 2028 MachineModuleInfo *MMI = getMachineModuleInfo(); 2029 return MMI && MMI->hasDebugInfo() && MMI->isVerified(GV); 2030} 2031 2032 2033/// getShuffleScalarElt - Returns the scalar element that will make up the ith 2034/// element of the result of the vector shuffle. 2035SDValue SelectionDAG::getShuffleScalarElt(const SDNode *N, unsigned i) { 2036 MVT VT = N->getValueType(0); 2037 SDValue PermMask = N->getOperand(2); 2038 SDValue Idx = PermMask.getOperand(i); 2039 if (Idx.getOpcode() == ISD::UNDEF) 2040 return getNode(ISD::UNDEF, VT.getVectorElementType()); 2041 unsigned Index = cast<ConstantSDNode>(Idx)->getZExtValue(); 2042 unsigned NumElems = PermMask.getNumOperands(); 2043 SDValue V = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1); 2044 Index %= NumElems; 2045 2046 if (V.getOpcode() == ISD::BIT_CONVERT) { 2047 V = V.getOperand(0); 2048 if (V.getValueType().getVectorNumElements() != NumElems) 2049 return SDValue(); 2050 } 2051 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) 2052 return (Index == 0) ? V.getOperand(0) 2053 : getNode(ISD::UNDEF, VT.getVectorElementType()); 2054 if (V.getOpcode() == ISD::BUILD_VECTOR) 2055 return V.getOperand(Index); 2056 if (V.getOpcode() == ISD::VECTOR_SHUFFLE) 2057 return getShuffleScalarElt(V.getNode(), Index); 2058 return SDValue(); 2059} 2060 2061 2062/// getNode - Gets or creates the specified node. 2063/// 2064SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT) { 2065 FoldingSetNodeID ID; 2066 AddNodeIDNode(ID, Opcode, getVTList(VT), 0, 0); 2067 void *IP = 0; 2068 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2069 return SDValue(E, 0); 2070 SDNode *N = NodeAllocator.Allocate<SDNode>(); 2071 new (N) SDNode(Opcode, SDNode::getSDVTList(VT)); 2072 CSEMap.InsertNode(N, IP); 2073 2074 AllNodes.push_back(N); 2075#ifndef NDEBUG 2076 VerifyNode(N); 2077#endif 2078 return SDValue(N, 0); 2079} 2080 2081SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, SDValue Operand) { 2082 // Constant fold unary operations with an integer constant operand. 2083 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Operand.getNode())) { 2084 const APInt &Val = C->getAPIntValue(); 2085 unsigned BitWidth = VT.getSizeInBits(); 2086 switch (Opcode) { 2087 default: break; 2088 case ISD::SIGN_EXTEND: 2089 return getConstant(APInt(Val).sextOrTrunc(BitWidth), VT); 2090 case ISD::ANY_EXTEND: 2091 case ISD::ZERO_EXTEND: 2092 case ISD::TRUNCATE: 2093 return getConstant(APInt(Val).zextOrTrunc(BitWidth), VT); 2094 case ISD::UINT_TO_FP: 2095 case ISD::SINT_TO_FP: { 2096 const uint64_t zero[] = {0, 0}; 2097 // No compile time operations on this type. 2098 if (VT==MVT::ppcf128) 2099 break; 2100 APFloat apf = APFloat(APInt(BitWidth, 2, zero)); 2101 (void)apf.convertFromAPInt(Val, 2102 Opcode==ISD::SINT_TO_FP, 2103 APFloat::rmNearestTiesToEven); 2104 return getConstantFP(apf, VT); 2105 } 2106 case ISD::BIT_CONVERT: 2107 if (VT == MVT::f32 && C->getValueType(0) == MVT::i32) 2108 return getConstantFP(Val.bitsToFloat(), VT); 2109 else if (VT == MVT::f64 && C->getValueType(0) == MVT::i64) 2110 return getConstantFP(Val.bitsToDouble(), VT); 2111 break; 2112 case ISD::BSWAP: 2113 return getConstant(Val.byteSwap(), VT); 2114 case ISD::CTPOP: 2115 return getConstant(Val.countPopulation(), VT); 2116 case ISD::CTLZ: 2117 return getConstant(Val.countLeadingZeros(), VT); 2118 case ISD::CTTZ: 2119 return getConstant(Val.countTrailingZeros(), VT); 2120 } 2121 } 2122 2123 // Constant fold unary operations with a floating point constant operand. 2124 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Operand.getNode())) { 2125 APFloat V = C->getValueAPF(); // make copy 2126 if (VT != MVT::ppcf128 && Operand.getValueType() != MVT::ppcf128) { 2127 switch (Opcode) { 2128 case ISD::FNEG: 2129 V.changeSign(); 2130 return getConstantFP(V, VT); 2131 case ISD::FABS: 2132 V.clearSign(); 2133 return getConstantFP(V, VT); 2134 case ISD::FP_ROUND: 2135 case ISD::FP_EXTEND: { 2136 bool ignored; 2137 // This can return overflow, underflow, or inexact; we don't care. 2138 // FIXME need to be more flexible about rounding mode. 2139 (void)V.convert(*MVTToAPFloatSemantics(VT), 2140 APFloat::rmNearestTiesToEven, &ignored); 2141 return getConstantFP(V, VT); 2142 } 2143 case ISD::FP_TO_SINT: 2144 case ISD::FP_TO_UINT: { 2145 integerPart x; 2146 bool ignored; 2147 assert(integerPartWidth >= 64); 2148 // FIXME need to be more flexible about rounding mode. 2149 APFloat::opStatus s = V.convertToInteger(&x, 64U, 2150 Opcode==ISD::FP_TO_SINT, 2151 APFloat::rmTowardZero, &ignored); 2152 if (s==APFloat::opInvalidOp) // inexact is OK, in fact usual 2153 break; 2154 return getConstant(x, VT); 2155 } 2156 case ISD::BIT_CONVERT: 2157 if (VT == MVT::i32 && C->getValueType(0) == MVT::f32) 2158 return getConstant((uint32_t)V.bitcastToAPInt().getZExtValue(), VT); 2159 else if (VT == MVT::i64 && C->getValueType(0) == MVT::f64) 2160 return getConstant(V.bitcastToAPInt().getZExtValue(), VT); 2161 break; 2162 } 2163 } 2164 } 2165 2166 unsigned OpOpcode = Operand.getNode()->getOpcode(); 2167 switch (Opcode) { 2168 case ISD::TokenFactor: 2169 case ISD::CONCAT_VECTORS: 2170 return Operand; // Factor or concat of one node? No need. 2171 case ISD::FP_ROUND: assert(0 && "Invalid method to make FP_ROUND node"); 2172 case ISD::FP_EXTEND: 2173 assert(VT.isFloatingPoint() && 2174 Operand.getValueType().isFloatingPoint() && "Invalid FP cast!"); 2175 if (Operand.getValueType() == VT) return Operand; // noop conversion. 2176 if (Operand.getOpcode() == ISD::UNDEF) 2177 return getNode(ISD::UNDEF, VT); 2178 break; 2179 case ISD::SIGN_EXTEND: 2180 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2181 "Invalid SIGN_EXTEND!"); 2182 if (Operand.getValueType() == VT) return Operand; // noop extension 2183 assert(Operand.getValueType().bitsLT(VT) 2184 && "Invalid sext node, dst < src!"); 2185 if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND) 2186 return getNode(OpOpcode, VT, Operand.getNode()->getOperand(0)); 2187 break; 2188 case ISD::ZERO_EXTEND: 2189 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2190 "Invalid ZERO_EXTEND!"); 2191 if (Operand.getValueType() == VT) return Operand; // noop extension 2192 assert(Operand.getValueType().bitsLT(VT) 2193 && "Invalid zext node, dst < src!"); 2194 if (OpOpcode == ISD::ZERO_EXTEND) // (zext (zext x)) -> (zext x) 2195 return getNode(ISD::ZERO_EXTEND, VT, Operand.getNode()->getOperand(0)); 2196 break; 2197 case ISD::ANY_EXTEND: 2198 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2199 "Invalid ANY_EXTEND!"); 2200 if (Operand.getValueType() == VT) return Operand; // noop extension 2201 assert(Operand.getValueType().bitsLT(VT) 2202 && "Invalid anyext node, dst < src!"); 2203 if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND) 2204 // (ext (zext x)) -> (zext x) and (ext (sext x)) -> (sext x) 2205 return getNode(OpOpcode, VT, Operand.getNode()->getOperand(0)); 2206 break; 2207 case ISD::TRUNCATE: 2208 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2209 "Invalid TRUNCATE!"); 2210 if (Operand.getValueType() == VT) return Operand; // noop truncate 2211 assert(Operand.getValueType().bitsGT(VT) 2212 && "Invalid truncate node, src < dst!"); 2213 if (OpOpcode == ISD::TRUNCATE) 2214 return getNode(ISD::TRUNCATE, VT, Operand.getNode()->getOperand(0)); 2215 else if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND || 2216 OpOpcode == ISD::ANY_EXTEND) { 2217 // If the source is smaller than the dest, we still need an extend. 2218 if (Operand.getNode()->getOperand(0).getValueType().bitsLT(VT)) 2219 return getNode(OpOpcode, VT, Operand.getNode()->getOperand(0)); 2220 else if (Operand.getNode()->getOperand(0).getValueType().bitsGT(VT)) 2221 return getNode(ISD::TRUNCATE, VT, Operand.getNode()->getOperand(0)); 2222 else 2223 return Operand.getNode()->getOperand(0); 2224 } 2225 break; 2226 case ISD::BIT_CONVERT: 2227 // Basic sanity checking. 2228 assert(VT.getSizeInBits() == Operand.getValueType().getSizeInBits() 2229 && "Cannot BIT_CONVERT between types of different sizes!"); 2230 if (VT == Operand.getValueType()) return Operand; // noop conversion. 2231 if (OpOpcode == ISD::BIT_CONVERT) // bitconv(bitconv(x)) -> bitconv(x) 2232 return getNode(ISD::BIT_CONVERT, VT, Operand.getOperand(0)); 2233 if (OpOpcode == ISD::UNDEF) 2234 return getNode(ISD::UNDEF, VT); 2235 break; 2236 case ISD::SCALAR_TO_VECTOR: 2237 assert(VT.isVector() && !Operand.getValueType().isVector() && 2238 VT.getVectorElementType() == Operand.getValueType() && 2239 "Illegal SCALAR_TO_VECTOR node!"); 2240 if (OpOpcode == ISD::UNDEF) 2241 return getNode(ISD::UNDEF, VT); 2242 // scalar_to_vector(extract_vector_elt V, 0) -> V, top bits are undefined. 2243 if (OpOpcode == ISD::EXTRACT_VECTOR_ELT && 2244 isa<ConstantSDNode>(Operand.getOperand(1)) && 2245 Operand.getConstantOperandVal(1) == 0 && 2246 Operand.getOperand(0).getValueType() == VT) 2247 return Operand.getOperand(0); 2248 break; 2249 case ISD::FNEG: 2250 if (OpOpcode == ISD::FSUB) // -(X-Y) -> (Y-X) 2251 return getNode(ISD::FSUB, VT, Operand.getNode()->getOperand(1), 2252 Operand.getNode()->getOperand(0)); 2253 if (OpOpcode == ISD::FNEG) // --X -> X 2254 return Operand.getNode()->getOperand(0); 2255 break; 2256 case ISD::FABS: 2257 if (OpOpcode == ISD::FNEG) // abs(-X) -> abs(X) 2258 return getNode(ISD::FABS, VT, Operand.getNode()->getOperand(0)); 2259 break; 2260 } 2261 2262 SDNode *N; 2263 SDVTList VTs = getVTList(VT); 2264 if (VT != MVT::Flag) { // Don't CSE flag producing nodes 2265 FoldingSetNodeID ID; 2266 SDValue Ops[1] = { Operand }; 2267 AddNodeIDNode(ID, Opcode, VTs, Ops, 1); 2268 void *IP = 0; 2269 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2270 return SDValue(E, 0); 2271 N = NodeAllocator.Allocate<UnarySDNode>(); 2272 new (N) UnarySDNode(Opcode, VTs, Operand); 2273 CSEMap.InsertNode(N, IP); 2274 } else { 2275 N = NodeAllocator.Allocate<UnarySDNode>(); 2276 new (N) UnarySDNode(Opcode, VTs, Operand); 2277 } 2278 2279 AllNodes.push_back(N); 2280#ifndef NDEBUG 2281 VerifyNode(N); 2282#endif 2283 return SDValue(N, 0); 2284} 2285 2286SDValue SelectionDAG::FoldConstantArithmetic(unsigned Opcode, 2287 MVT VT, 2288 ConstantSDNode *Cst1, 2289 ConstantSDNode *Cst2) { 2290 const APInt &C1 = Cst1->getAPIntValue(), &C2 = Cst2->getAPIntValue(); 2291 2292 switch (Opcode) { 2293 case ISD::ADD: return getConstant(C1 + C2, VT); 2294 case ISD::SUB: return getConstant(C1 - C2, VT); 2295 case ISD::MUL: return getConstant(C1 * C2, VT); 2296 case ISD::UDIV: 2297 if (C2.getBoolValue()) return getConstant(C1.udiv(C2), VT); 2298 break; 2299 case ISD::UREM: 2300 if (C2.getBoolValue()) return getConstant(C1.urem(C2), VT); 2301 break; 2302 case ISD::SDIV: 2303 if (C2.getBoolValue()) return getConstant(C1.sdiv(C2), VT); 2304 break; 2305 case ISD::SREM: 2306 if (C2.getBoolValue()) return getConstant(C1.srem(C2), VT); 2307 break; 2308 case ISD::AND: return getConstant(C1 & C2, VT); 2309 case ISD::OR: return getConstant(C1 | C2, VT); 2310 case ISD::XOR: return getConstant(C1 ^ C2, VT); 2311 case ISD::SHL: return getConstant(C1 << C2, VT); 2312 case ISD::SRL: return getConstant(C1.lshr(C2), VT); 2313 case ISD::SRA: return getConstant(C1.ashr(C2), VT); 2314 case ISD::ROTL: return getConstant(C1.rotl(C2), VT); 2315 case ISD::ROTR: return getConstant(C1.rotr(C2), VT); 2316 default: break; 2317 } 2318 2319 return SDValue(); 2320} 2321 2322SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, 2323 SDValue N1, SDValue N2) { 2324 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 2325 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 2326 switch (Opcode) { 2327 default: break; 2328 case ISD::TokenFactor: 2329 assert(VT == MVT::Other && N1.getValueType() == MVT::Other && 2330 N2.getValueType() == MVT::Other && "Invalid token factor!"); 2331 // Fold trivial token factors. 2332 if (N1.getOpcode() == ISD::EntryToken) return N2; 2333 if (N2.getOpcode() == ISD::EntryToken) return N1; 2334 if (N1 == N2) return N1; 2335 break; 2336 case ISD::CONCAT_VECTORS: 2337 // A CONCAT_VECTOR with all operands BUILD_VECTOR can be simplified to 2338 // one big BUILD_VECTOR. 2339 if (N1.getOpcode() == ISD::BUILD_VECTOR && 2340 N2.getOpcode() == ISD::BUILD_VECTOR) { 2341 SmallVector<SDValue, 16> Elts(N1.getNode()->op_begin(), N1.getNode()->op_end()); 2342 Elts.insert(Elts.end(), N2.getNode()->op_begin(), N2.getNode()->op_end()); 2343 return getNode(ISD::BUILD_VECTOR, VT, &Elts[0], Elts.size()); 2344 } 2345 break; 2346 case ISD::AND: 2347 assert(VT.isInteger() && N1.getValueType() == N2.getValueType() && 2348 N1.getValueType() == VT && "Binary operator types must match!"); 2349 // (X & 0) -> 0. This commonly occurs when legalizing i64 values, so it's 2350 // worth handling here. 2351 if (N2C && N2C->isNullValue()) 2352 return N2; 2353 if (N2C && N2C->isAllOnesValue()) // X & -1 -> X 2354 return N1; 2355 break; 2356 case ISD::OR: 2357 case ISD::XOR: 2358 case ISD::ADD: 2359 case ISD::SUB: 2360 assert(VT.isInteger() && N1.getValueType() == N2.getValueType() && 2361 N1.getValueType() == VT && "Binary operator types must match!"); 2362 // (X ^|+- 0) -> X. This commonly occurs when legalizing i64 values, so 2363 // it's worth handling here. 2364 if (N2C && N2C->isNullValue()) 2365 return N1; 2366 break; 2367 case ISD::UDIV: 2368 case ISD::UREM: 2369 case ISD::MULHU: 2370 case ISD::MULHS: 2371 assert(VT.isInteger() && "This operator does not apply to FP types!"); 2372 // fall through 2373 case ISD::MUL: 2374 case ISD::SDIV: 2375 case ISD::SREM: 2376 case ISD::FADD: 2377 case ISD::FSUB: 2378 case ISD::FMUL: 2379 case ISD::FDIV: 2380 case ISD::FREM: 2381 assert(N1.getValueType() == N2.getValueType() && 2382 N1.getValueType() == VT && "Binary operator types must match!"); 2383 break; 2384 case ISD::FCOPYSIGN: // N1 and result must match. N1/N2 need not match. 2385 assert(N1.getValueType() == VT && 2386 N1.getValueType().isFloatingPoint() && 2387 N2.getValueType().isFloatingPoint() && 2388 "Invalid FCOPYSIGN!"); 2389 break; 2390 case ISD::SHL: 2391 case ISD::SRA: 2392 case ISD::SRL: 2393 case ISD::ROTL: 2394 case ISD::ROTR: 2395 assert(VT == N1.getValueType() && 2396 "Shift operators return type must be the same as their first arg"); 2397 assert(VT.isInteger() && N2.getValueType().isInteger() && 2398 "Shifts only work on integers"); 2399 2400 // Always fold shifts of i1 values so the code generator doesn't need to 2401 // handle them. Since we know the size of the shift has to be less than the 2402 // size of the value, the shift/rotate count is guaranteed to be zero. 2403 if (VT == MVT::i1) 2404 return N1; 2405 break; 2406 case ISD::FP_ROUND_INREG: { 2407 MVT EVT = cast<VTSDNode>(N2)->getVT(); 2408 assert(VT == N1.getValueType() && "Not an inreg round!"); 2409 assert(VT.isFloatingPoint() && EVT.isFloatingPoint() && 2410 "Cannot FP_ROUND_INREG integer types"); 2411 assert(EVT.bitsLE(VT) && "Not rounding down!"); 2412 if (cast<VTSDNode>(N2)->getVT() == VT) return N1; // Not actually rounding. 2413 break; 2414 } 2415 case ISD::FP_ROUND: 2416 assert(VT.isFloatingPoint() && 2417 N1.getValueType().isFloatingPoint() && 2418 VT.bitsLE(N1.getValueType()) && 2419 isa<ConstantSDNode>(N2) && "Invalid FP_ROUND!"); 2420 if (N1.getValueType() == VT) return N1; // noop conversion. 2421 break; 2422 case ISD::AssertSext: 2423 case ISD::AssertZext: { 2424 MVT EVT = cast<VTSDNode>(N2)->getVT(); 2425 assert(VT == N1.getValueType() && "Not an inreg extend!"); 2426 assert(VT.isInteger() && EVT.isInteger() && 2427 "Cannot *_EXTEND_INREG FP types"); 2428 assert(EVT.bitsLE(VT) && "Not extending!"); 2429 if (VT == EVT) return N1; // noop assertion. 2430 break; 2431 } 2432 case ISD::SIGN_EXTEND_INREG: { 2433 MVT EVT = cast<VTSDNode>(N2)->getVT(); 2434 assert(VT == N1.getValueType() && "Not an inreg extend!"); 2435 assert(VT.isInteger() && EVT.isInteger() && 2436 "Cannot *_EXTEND_INREG FP types"); 2437 assert(EVT.bitsLE(VT) && "Not extending!"); 2438 if (EVT == VT) return N1; // Not actually extending 2439 2440 if (N1C) { 2441 APInt Val = N1C->getAPIntValue(); 2442 unsigned FromBits = cast<VTSDNode>(N2)->getVT().getSizeInBits(); 2443 Val <<= Val.getBitWidth()-FromBits; 2444 Val = Val.ashr(Val.getBitWidth()-FromBits); 2445 return getConstant(Val, VT); 2446 } 2447 break; 2448 } 2449 case ISD::EXTRACT_VECTOR_ELT: 2450 // EXTRACT_VECTOR_ELT of an UNDEF is an UNDEF. 2451 if (N1.getOpcode() == ISD::UNDEF) 2452 return getNode(ISD::UNDEF, VT); 2453 2454 // EXTRACT_VECTOR_ELT of CONCAT_VECTORS is often formed while lowering is 2455 // expanding copies of large vectors from registers. 2456 if (N2C && 2457 N1.getOpcode() == ISD::CONCAT_VECTORS && 2458 N1.getNumOperands() > 0) { 2459 unsigned Factor = 2460 N1.getOperand(0).getValueType().getVectorNumElements(); 2461 return getNode(ISD::EXTRACT_VECTOR_ELT, VT, 2462 N1.getOperand(N2C->getZExtValue() / Factor), 2463 getConstant(N2C->getZExtValue() % Factor, 2464 N2.getValueType())); 2465 } 2466 2467 // EXTRACT_VECTOR_ELT of BUILD_VECTOR is often formed while lowering is 2468 // expanding large vector constants. 2469 if (N2C && N1.getOpcode() == ISD::BUILD_VECTOR) 2470 return N1.getOperand(N2C->getZExtValue()); 2471 2472 // EXTRACT_VECTOR_ELT of INSERT_VECTOR_ELT is often formed when vector 2473 // operations are lowered to scalars. 2474 if (N1.getOpcode() == ISD::INSERT_VECTOR_ELT) { 2475 if (N1.getOperand(2) == N2) 2476 return N1.getOperand(1); 2477 else 2478 return getNode(ISD::EXTRACT_VECTOR_ELT, VT, N1.getOperand(0), N2); 2479 } 2480 break; 2481 case ISD::EXTRACT_ELEMENT: 2482 assert(N2C && (unsigned)N2C->getZExtValue() < 2 && "Bad EXTRACT_ELEMENT!"); 2483 assert(!N1.getValueType().isVector() && !VT.isVector() && 2484 (N1.getValueType().isInteger() == VT.isInteger()) && 2485 "Wrong types for EXTRACT_ELEMENT!"); 2486 2487 // EXTRACT_ELEMENT of BUILD_PAIR is often formed while legalize is expanding 2488 // 64-bit integers into 32-bit parts. Instead of building the extract of 2489 // the BUILD_PAIR, only to have legalize rip it apart, just do it now. 2490 if (N1.getOpcode() == ISD::BUILD_PAIR) 2491 return N1.getOperand(N2C->getZExtValue()); 2492 2493 // EXTRACT_ELEMENT of a constant int is also very common. 2494 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) { 2495 unsigned ElementSize = VT.getSizeInBits(); 2496 unsigned Shift = ElementSize * N2C->getZExtValue(); 2497 APInt ShiftedVal = C->getAPIntValue().lshr(Shift); 2498 return getConstant(ShiftedVal.trunc(ElementSize), VT); 2499 } 2500 break; 2501 case ISD::EXTRACT_SUBVECTOR: 2502 if (N1.getValueType() == VT) // Trivial extraction. 2503 return N1; 2504 break; 2505 } 2506 2507 if (N1C) { 2508 if (N2C) { 2509 SDValue SV = FoldConstantArithmetic(Opcode, VT, N1C, N2C); 2510 if (SV.getNode()) return SV; 2511 } else { // Cannonicalize constant to RHS if commutative 2512 if (isCommutativeBinOp(Opcode)) { 2513 std::swap(N1C, N2C); 2514 std::swap(N1, N2); 2515 } 2516 } 2517 } 2518 2519 // Constant fold FP operations. 2520 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1.getNode()); 2521 ConstantFPSDNode *N2CFP = dyn_cast<ConstantFPSDNode>(N2.getNode()); 2522 if (N1CFP) { 2523 if (!N2CFP && isCommutativeBinOp(Opcode)) { 2524 // Cannonicalize constant to RHS if commutative 2525 std::swap(N1CFP, N2CFP); 2526 std::swap(N1, N2); 2527 } else if (N2CFP && VT != MVT::ppcf128) { 2528 APFloat V1 = N1CFP->getValueAPF(), V2 = N2CFP->getValueAPF(); 2529 APFloat::opStatus s; 2530 switch (Opcode) { 2531 case ISD::FADD: 2532 s = V1.add(V2, APFloat::rmNearestTiesToEven); 2533 if (s != APFloat::opInvalidOp) 2534 return getConstantFP(V1, VT); 2535 break; 2536 case ISD::FSUB: 2537 s = V1.subtract(V2, APFloat::rmNearestTiesToEven); 2538 if (s!=APFloat::opInvalidOp) 2539 return getConstantFP(V1, VT); 2540 break; 2541 case ISD::FMUL: 2542 s = V1.multiply(V2, APFloat::rmNearestTiesToEven); 2543 if (s!=APFloat::opInvalidOp) 2544 return getConstantFP(V1, VT); 2545 break; 2546 case ISD::FDIV: 2547 s = V1.divide(V2, APFloat::rmNearestTiesToEven); 2548 if (s!=APFloat::opInvalidOp && s!=APFloat::opDivByZero) 2549 return getConstantFP(V1, VT); 2550 break; 2551 case ISD::FREM : 2552 s = V1.mod(V2, APFloat::rmNearestTiesToEven); 2553 if (s!=APFloat::opInvalidOp && s!=APFloat::opDivByZero) 2554 return getConstantFP(V1, VT); 2555 break; 2556 case ISD::FCOPYSIGN: 2557 V1.copySign(V2); 2558 return getConstantFP(V1, VT); 2559 default: break; 2560 } 2561 } 2562 } 2563 2564 // Canonicalize an UNDEF to the RHS, even over a constant. 2565 if (N1.getOpcode() == ISD::UNDEF) { 2566 if (isCommutativeBinOp(Opcode)) { 2567 std::swap(N1, N2); 2568 } else { 2569 switch (Opcode) { 2570 case ISD::FP_ROUND_INREG: 2571 case ISD::SIGN_EXTEND_INREG: 2572 case ISD::SUB: 2573 case ISD::FSUB: 2574 case ISD::FDIV: 2575 case ISD::FREM: 2576 case ISD::SRA: 2577 return N1; // fold op(undef, arg2) -> undef 2578 case ISD::UDIV: 2579 case ISD::SDIV: 2580 case ISD::UREM: 2581 case ISD::SREM: 2582 case ISD::SRL: 2583 case ISD::SHL: 2584 if (!VT.isVector()) 2585 return getConstant(0, VT); // fold op(undef, arg2) -> 0 2586 // For vectors, we can't easily build an all zero vector, just return 2587 // the LHS. 2588 return N2; 2589 } 2590 } 2591 } 2592 2593 // Fold a bunch of operators when the RHS is undef. 2594 if (N2.getOpcode() == ISD::UNDEF) { 2595 switch (Opcode) { 2596 case ISD::XOR: 2597 if (N1.getOpcode() == ISD::UNDEF) 2598 // Handle undef ^ undef -> 0 special case. This is a common 2599 // idiom (misuse). 2600 return getConstant(0, VT); 2601 // fallthrough 2602 case ISD::ADD: 2603 case ISD::ADDC: 2604 case ISD::ADDE: 2605 case ISD::SUB: 2606 case ISD::FADD: 2607 case ISD::FSUB: 2608 case ISD::FMUL: 2609 case ISD::FDIV: 2610 case ISD::FREM: 2611 case ISD::UDIV: 2612 case ISD::SDIV: 2613 case ISD::UREM: 2614 case ISD::SREM: 2615 return N2; // fold op(arg1, undef) -> undef 2616 case ISD::MUL: 2617 case ISD::AND: 2618 case ISD::SRL: 2619 case ISD::SHL: 2620 if (!VT.isVector()) 2621 return getConstant(0, VT); // fold op(arg1, undef) -> 0 2622 // For vectors, we can't easily build an all zero vector, just return 2623 // the LHS. 2624 return N1; 2625 case ISD::OR: 2626 if (!VT.isVector()) 2627 return getConstant(VT.getIntegerVTBitMask(), VT); 2628 // For vectors, we can't easily build an all one vector, just return 2629 // the LHS. 2630 return N1; 2631 case ISD::SRA: 2632 return N1; 2633 } 2634 } 2635 2636 // Memoize this node if possible. 2637 SDNode *N; 2638 SDVTList VTs = getVTList(VT); 2639 if (VT != MVT::Flag) { 2640 SDValue Ops[] = { N1, N2 }; 2641 FoldingSetNodeID ID; 2642 AddNodeIDNode(ID, Opcode, VTs, Ops, 2); 2643 void *IP = 0; 2644 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2645 return SDValue(E, 0); 2646 N = NodeAllocator.Allocate<BinarySDNode>(); 2647 new (N) BinarySDNode(Opcode, VTs, N1, N2); 2648 CSEMap.InsertNode(N, IP); 2649 } else { 2650 N = NodeAllocator.Allocate<BinarySDNode>(); 2651 new (N) BinarySDNode(Opcode, VTs, N1, N2); 2652 } 2653 2654 AllNodes.push_back(N); 2655#ifndef NDEBUG 2656 VerifyNode(N); 2657#endif 2658 return SDValue(N, 0); 2659} 2660 2661SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, 2662 SDValue N1, SDValue N2, SDValue N3) { 2663 // Perform various simplifications. 2664 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 2665 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 2666 switch (Opcode) { 2667 case ISD::CONCAT_VECTORS: 2668 // A CONCAT_VECTOR with all operands BUILD_VECTOR can be simplified to 2669 // one big BUILD_VECTOR. 2670 if (N1.getOpcode() == ISD::BUILD_VECTOR && 2671 N2.getOpcode() == ISD::BUILD_VECTOR && 2672 N3.getOpcode() == ISD::BUILD_VECTOR) { 2673 SmallVector<SDValue, 16> Elts(N1.getNode()->op_begin(), N1.getNode()->op_end()); 2674 Elts.insert(Elts.end(), N2.getNode()->op_begin(), N2.getNode()->op_end()); 2675 Elts.insert(Elts.end(), N3.getNode()->op_begin(), N3.getNode()->op_end()); 2676 return getNode(ISD::BUILD_VECTOR, VT, &Elts[0], Elts.size()); 2677 } 2678 break; 2679 case ISD::SETCC: { 2680 // Use FoldSetCC to simplify SETCC's. 2681 SDValue Simp = FoldSetCC(VT, N1, N2, cast<CondCodeSDNode>(N3)->get()); 2682 if (Simp.getNode()) return Simp; 2683 break; 2684 } 2685 case ISD::SELECT: 2686 if (N1C) { 2687 if (N1C->getZExtValue()) 2688 return N2; // select true, X, Y -> X 2689 else 2690 return N3; // select false, X, Y -> Y 2691 } 2692 2693 if (N2 == N3) return N2; // select C, X, X -> X 2694 break; 2695 case ISD::BRCOND: 2696 if (N2C) { 2697 if (N2C->getZExtValue()) // Unconditional branch 2698 return getNode(ISD::BR, MVT::Other, N1, N3); 2699 else 2700 return N1; // Never-taken branch 2701 } 2702 break; 2703 case ISD::VECTOR_SHUFFLE: 2704 assert(VT == N1.getValueType() && VT == N2.getValueType() && 2705 VT.isVector() && N3.getValueType().isVector() && 2706 N3.getOpcode() == ISD::BUILD_VECTOR && 2707 VT.getVectorNumElements() == N3.getNumOperands() && 2708 "Illegal VECTOR_SHUFFLE node!"); 2709 break; 2710 case ISD::BIT_CONVERT: 2711 // Fold bit_convert nodes from a type to themselves. 2712 if (N1.getValueType() == VT) 2713 return N1; 2714 break; 2715 } 2716 2717 // Memoize node if it doesn't produce a flag. 2718 SDNode *N; 2719 SDVTList VTs = getVTList(VT); 2720 if (VT != MVT::Flag) { 2721 SDValue Ops[] = { N1, N2, N3 }; 2722 FoldingSetNodeID ID; 2723 AddNodeIDNode(ID, Opcode, VTs, Ops, 3); 2724 void *IP = 0; 2725 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2726 return SDValue(E, 0); 2727 N = NodeAllocator.Allocate<TernarySDNode>(); 2728 new (N) TernarySDNode(Opcode, VTs, N1, N2, N3); 2729 CSEMap.InsertNode(N, IP); 2730 } else { 2731 N = NodeAllocator.Allocate<TernarySDNode>(); 2732 new (N) TernarySDNode(Opcode, VTs, N1, N2, N3); 2733 } 2734 AllNodes.push_back(N); 2735#ifndef NDEBUG 2736 VerifyNode(N); 2737#endif 2738 return SDValue(N, 0); 2739} 2740 2741SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, 2742 SDValue N1, SDValue N2, SDValue N3, 2743 SDValue N4) { 2744 SDValue Ops[] = { N1, N2, N3, N4 }; 2745 return getNode(Opcode, VT, Ops, 4); 2746} 2747 2748SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, 2749 SDValue N1, SDValue N2, SDValue N3, 2750 SDValue N4, SDValue N5) { 2751 SDValue Ops[] = { N1, N2, N3, N4, N5 }; 2752 return getNode(Opcode, VT, Ops, 5); 2753} 2754 2755/// getMemsetValue - Vectorized representation of the memset value 2756/// operand. 2757static SDValue getMemsetValue(SDValue Value, MVT VT, SelectionDAG &DAG) { 2758 unsigned NumBits = VT.isVector() ? 2759 VT.getVectorElementType().getSizeInBits() : VT.getSizeInBits(); 2760 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) { 2761 APInt Val = APInt(NumBits, C->getZExtValue() & 255); 2762 unsigned Shift = 8; 2763 for (unsigned i = NumBits; i > 8; i >>= 1) { 2764 Val = (Val << Shift) | Val; 2765 Shift <<= 1; 2766 } 2767 if (VT.isInteger()) 2768 return DAG.getConstant(Val, VT); 2769 return DAG.getConstantFP(APFloat(Val), VT); 2770 } 2771 2772 Value = DAG.getNode(ISD::ZERO_EXTEND, VT, Value); 2773 unsigned Shift = 8; 2774 for (unsigned i = NumBits; i > 8; i >>= 1) { 2775 Value = DAG.getNode(ISD::OR, VT, 2776 DAG.getNode(ISD::SHL, VT, Value, 2777 DAG.getConstant(Shift, MVT::i8)), Value); 2778 Shift <<= 1; 2779 } 2780 2781 return Value; 2782} 2783 2784/// getMemsetStringVal - Similar to getMemsetValue. Except this is only 2785/// used when a memcpy is turned into a memset when the source is a constant 2786/// string ptr. 2787static SDValue getMemsetStringVal(MVT VT, SelectionDAG &DAG, 2788 const TargetLowering &TLI, 2789 std::string &Str, unsigned Offset) { 2790 // Handle vector with all elements zero. 2791 if (Str.empty()) { 2792 if (VT.isInteger()) 2793 return DAG.getConstant(0, VT); 2794 unsigned NumElts = VT.getVectorNumElements(); 2795 MVT EltVT = (VT.getVectorElementType() == MVT::f32) ? MVT::i32 : MVT::i64; 2796 return DAG.getNode(ISD::BIT_CONVERT, VT, 2797 DAG.getConstant(0, MVT::getVectorVT(EltVT, NumElts))); 2798 } 2799 2800 assert(!VT.isVector() && "Can't handle vector type here!"); 2801 unsigned NumBits = VT.getSizeInBits(); 2802 unsigned MSB = NumBits / 8; 2803 uint64_t Val = 0; 2804 if (TLI.isLittleEndian()) 2805 Offset = Offset + MSB - 1; 2806 for (unsigned i = 0; i != MSB; ++i) { 2807 Val = (Val << 8) | (unsigned char)Str[Offset]; 2808 Offset += TLI.isLittleEndian() ? -1 : 1; 2809 } 2810 return DAG.getConstant(Val, VT); 2811} 2812 2813/// getMemBasePlusOffset - Returns base and offset node for the 2814/// 2815static SDValue getMemBasePlusOffset(SDValue Base, unsigned Offset, 2816 SelectionDAG &DAG) { 2817 MVT VT = Base.getValueType(); 2818 return DAG.getNode(ISD::ADD, VT, Base, DAG.getConstant(Offset, VT)); 2819} 2820 2821/// isMemSrcFromString - Returns true if memcpy source is a string constant. 2822/// 2823static bool isMemSrcFromString(SDValue Src, std::string &Str) { 2824 unsigned SrcDelta = 0; 2825 GlobalAddressSDNode *G = NULL; 2826 if (Src.getOpcode() == ISD::GlobalAddress) 2827 G = cast<GlobalAddressSDNode>(Src); 2828 else if (Src.getOpcode() == ISD::ADD && 2829 Src.getOperand(0).getOpcode() == ISD::GlobalAddress && 2830 Src.getOperand(1).getOpcode() == ISD::Constant) { 2831 G = cast<GlobalAddressSDNode>(Src.getOperand(0)); 2832 SrcDelta = cast<ConstantSDNode>(Src.getOperand(1))->getZExtValue(); 2833 } 2834 if (!G) 2835 return false; 2836 2837 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal()); 2838 if (GV && GetConstantStringInfo(GV, Str, SrcDelta, false)) 2839 return true; 2840 2841 return false; 2842} 2843 2844/// MeetsMaxMemopRequirement - Determines if the number of memory ops required 2845/// to replace the memset / memcpy is below the threshold. It also returns the 2846/// types of the sequence of memory ops to perform memset / memcpy. 2847static 2848bool MeetsMaxMemopRequirement(std::vector<MVT> &MemOps, 2849 SDValue Dst, SDValue Src, 2850 unsigned Limit, uint64_t Size, unsigned &Align, 2851 std::string &Str, bool &isSrcStr, 2852 SelectionDAG &DAG, 2853 const TargetLowering &TLI) { 2854 isSrcStr = isMemSrcFromString(Src, Str); 2855 bool isSrcConst = isa<ConstantSDNode>(Src); 2856 bool AllowUnalign = TLI.allowsUnalignedMemoryAccesses(); 2857 MVT VT= TLI.getOptimalMemOpType(Size, Align, isSrcConst, isSrcStr); 2858 if (VT != MVT::iAny) { 2859 unsigned NewAlign = (unsigned) 2860 TLI.getTargetData()->getABITypeAlignment(VT.getTypeForMVT()); 2861 // If source is a string constant, this will require an unaligned load. 2862 if (NewAlign > Align && (isSrcConst || AllowUnalign)) { 2863 if (Dst.getOpcode() != ISD::FrameIndex) { 2864 // Can't change destination alignment. It requires a unaligned store. 2865 if (AllowUnalign) 2866 VT = MVT::iAny; 2867 } else { 2868 int FI = cast<FrameIndexSDNode>(Dst)->getIndex(); 2869 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 2870 if (MFI->isFixedObjectIndex(FI)) { 2871 // Can't change destination alignment. It requires a unaligned store. 2872 if (AllowUnalign) 2873 VT = MVT::iAny; 2874 } else { 2875 // Give the stack frame object a larger alignment if needed. 2876 if (MFI->getObjectAlignment(FI) < NewAlign) 2877 MFI->setObjectAlignment(FI, NewAlign); 2878 Align = NewAlign; 2879 } 2880 } 2881 } 2882 } 2883 2884 if (VT == MVT::iAny) { 2885 if (AllowUnalign) { 2886 VT = MVT::i64; 2887 } else { 2888 switch (Align & 7) { 2889 case 0: VT = MVT::i64; break; 2890 case 4: VT = MVT::i32; break; 2891 case 2: VT = MVT::i16; break; 2892 default: VT = MVT::i8; break; 2893 } 2894 } 2895 2896 MVT LVT = MVT::i64; 2897 while (!TLI.isTypeLegal(LVT)) 2898 LVT = (MVT::SimpleValueType)(LVT.getSimpleVT() - 1); 2899 assert(LVT.isInteger()); 2900 2901 if (VT.bitsGT(LVT)) 2902 VT = LVT; 2903 } 2904 2905 unsigned NumMemOps = 0; 2906 while (Size != 0) { 2907 unsigned VTSize = VT.getSizeInBits() / 8; 2908 while (VTSize > Size) { 2909 // For now, only use non-vector load / store's for the left-over pieces. 2910 if (VT.isVector()) { 2911 VT = MVT::i64; 2912 while (!TLI.isTypeLegal(VT)) 2913 VT = (MVT::SimpleValueType)(VT.getSimpleVT() - 1); 2914 VTSize = VT.getSizeInBits() / 8; 2915 } else { 2916 VT = (MVT::SimpleValueType)(VT.getSimpleVT() - 1); 2917 VTSize >>= 1; 2918 } 2919 } 2920 2921 if (++NumMemOps > Limit) 2922 return false; 2923 MemOps.push_back(VT); 2924 Size -= VTSize; 2925 } 2926 2927 return true; 2928} 2929 2930static SDValue getMemcpyLoadsAndStores(SelectionDAG &DAG, 2931 SDValue Chain, SDValue Dst, 2932 SDValue Src, uint64_t Size, 2933 unsigned Align, bool AlwaysInline, 2934 const Value *DstSV, uint64_t DstSVOff, 2935 const Value *SrcSV, uint64_t SrcSVOff){ 2936 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 2937 2938 // Expand memcpy to a series of load and store ops if the size operand falls 2939 // below a certain threshold. 2940 std::vector<MVT> MemOps; 2941 uint64_t Limit = -1ULL; 2942 if (!AlwaysInline) 2943 Limit = TLI.getMaxStoresPerMemcpy(); 2944 unsigned DstAlign = Align; // Destination alignment can change. 2945 std::string Str; 2946 bool CopyFromStr; 2947 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, Limit, Size, DstAlign, 2948 Str, CopyFromStr, DAG, TLI)) 2949 return SDValue(); 2950 2951 2952 bool isZeroStr = CopyFromStr && Str.empty(); 2953 SmallVector<SDValue, 8> OutChains; 2954 unsigned NumMemOps = MemOps.size(); 2955 uint64_t SrcOff = 0, DstOff = 0; 2956 for (unsigned i = 0; i < NumMemOps; i++) { 2957 MVT VT = MemOps[i]; 2958 unsigned VTSize = VT.getSizeInBits() / 8; 2959 SDValue Value, Store; 2960 2961 if (CopyFromStr && (isZeroStr || !VT.isVector())) { 2962 // It's unlikely a store of a vector immediate can be done in a single 2963 // instruction. It would require a load from a constantpool first. 2964 // We also handle store a vector with all zero's. 2965 // FIXME: Handle other cases where store of vector immediate is done in 2966 // a single instruction. 2967 Value = getMemsetStringVal(VT, DAG, TLI, Str, SrcOff); 2968 Store = DAG.getStore(Chain, Value, 2969 getMemBasePlusOffset(Dst, DstOff, DAG), 2970 DstSV, DstSVOff + DstOff, false, DstAlign); 2971 } else { 2972 Value = DAG.getLoad(VT, Chain, 2973 getMemBasePlusOffset(Src, SrcOff, DAG), 2974 SrcSV, SrcSVOff + SrcOff, false, Align); 2975 Store = DAG.getStore(Chain, Value, 2976 getMemBasePlusOffset(Dst, DstOff, DAG), 2977 DstSV, DstSVOff + DstOff, false, DstAlign); 2978 } 2979 OutChains.push_back(Store); 2980 SrcOff += VTSize; 2981 DstOff += VTSize; 2982 } 2983 2984 return DAG.getNode(ISD::TokenFactor, MVT::Other, 2985 &OutChains[0], OutChains.size()); 2986} 2987 2988static SDValue getMemmoveLoadsAndStores(SelectionDAG &DAG, 2989 SDValue Chain, SDValue Dst, 2990 SDValue Src, uint64_t Size, 2991 unsigned Align, bool AlwaysInline, 2992 const Value *DstSV, uint64_t DstSVOff, 2993 const Value *SrcSV, uint64_t SrcSVOff){ 2994 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 2995 2996 // Expand memmove to a series of load and store ops if the size operand falls 2997 // below a certain threshold. 2998 std::vector<MVT> MemOps; 2999 uint64_t Limit = -1ULL; 3000 if (!AlwaysInline) 3001 Limit = TLI.getMaxStoresPerMemmove(); 3002 unsigned DstAlign = Align; // Destination alignment can change. 3003 std::string Str; 3004 bool CopyFromStr; 3005 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, Limit, Size, DstAlign, 3006 Str, CopyFromStr, DAG, TLI)) 3007 return SDValue(); 3008 3009 uint64_t SrcOff = 0, DstOff = 0; 3010 3011 SmallVector<SDValue, 8> LoadValues; 3012 SmallVector<SDValue, 8> LoadChains; 3013 SmallVector<SDValue, 8> OutChains; 3014 unsigned NumMemOps = MemOps.size(); 3015 for (unsigned i = 0; i < NumMemOps; i++) { 3016 MVT VT = MemOps[i]; 3017 unsigned VTSize = VT.getSizeInBits() / 8; 3018 SDValue Value, Store; 3019 3020 Value = DAG.getLoad(VT, Chain, 3021 getMemBasePlusOffset(Src, SrcOff, DAG), 3022 SrcSV, SrcSVOff + SrcOff, false, Align); 3023 LoadValues.push_back(Value); 3024 LoadChains.push_back(Value.getValue(1)); 3025 SrcOff += VTSize; 3026 } 3027 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 3028 &LoadChains[0], LoadChains.size()); 3029 OutChains.clear(); 3030 for (unsigned i = 0; i < NumMemOps; i++) { 3031 MVT VT = MemOps[i]; 3032 unsigned VTSize = VT.getSizeInBits() / 8; 3033 SDValue Value, Store; 3034 3035 Store = DAG.getStore(Chain, LoadValues[i], 3036 getMemBasePlusOffset(Dst, DstOff, DAG), 3037 DstSV, DstSVOff + DstOff, false, DstAlign); 3038 OutChains.push_back(Store); 3039 DstOff += VTSize; 3040 } 3041 3042 return DAG.getNode(ISD::TokenFactor, MVT::Other, 3043 &OutChains[0], OutChains.size()); 3044} 3045 3046static SDValue getMemsetStores(SelectionDAG &DAG, 3047 SDValue Chain, SDValue Dst, 3048 SDValue Src, uint64_t Size, 3049 unsigned Align, 3050 const Value *DstSV, uint64_t DstSVOff) { 3051 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 3052 3053 // Expand memset to a series of load/store ops if the size operand 3054 // falls below a certain threshold. 3055 std::vector<MVT> MemOps; 3056 std::string Str; 3057 bool CopyFromStr; 3058 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, TLI.getMaxStoresPerMemset(), 3059 Size, Align, Str, CopyFromStr, DAG, TLI)) 3060 return SDValue(); 3061 3062 SmallVector<SDValue, 8> OutChains; 3063 uint64_t DstOff = 0; 3064 3065 unsigned NumMemOps = MemOps.size(); 3066 for (unsigned i = 0; i < NumMemOps; i++) { 3067 MVT VT = MemOps[i]; 3068 unsigned VTSize = VT.getSizeInBits() / 8; 3069 SDValue Value = getMemsetValue(Src, VT, DAG); 3070 SDValue Store = DAG.getStore(Chain, Value, 3071 getMemBasePlusOffset(Dst, DstOff, DAG), 3072 DstSV, DstSVOff + DstOff); 3073 OutChains.push_back(Store); 3074 DstOff += VTSize; 3075 } 3076 3077 return DAG.getNode(ISD::TokenFactor, MVT::Other, 3078 &OutChains[0], OutChains.size()); 3079} 3080 3081SDValue SelectionDAG::getMemcpy(SDValue Chain, SDValue Dst, 3082 SDValue Src, SDValue Size, 3083 unsigned Align, bool AlwaysInline, 3084 const Value *DstSV, uint64_t DstSVOff, 3085 const Value *SrcSV, uint64_t SrcSVOff) { 3086 3087 // Check to see if we should lower the memcpy to loads and stores first. 3088 // For cases within the target-specified limits, this is the best choice. 3089 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 3090 if (ConstantSize) { 3091 // Memcpy with size zero? Just return the original chain. 3092 if (ConstantSize->isNullValue()) 3093 return Chain; 3094 3095 SDValue Result = 3096 getMemcpyLoadsAndStores(*this, Chain, Dst, Src, 3097 ConstantSize->getZExtValue(), 3098 Align, false, DstSV, DstSVOff, SrcSV, SrcSVOff); 3099 if (Result.getNode()) 3100 return Result; 3101 } 3102 3103 // Then check to see if we should lower the memcpy with target-specific 3104 // code. If the target chooses to do this, this is the next best. 3105 SDValue Result = 3106 TLI.EmitTargetCodeForMemcpy(*this, Chain, Dst, Src, Size, Align, 3107 AlwaysInline, 3108 DstSV, DstSVOff, SrcSV, SrcSVOff); 3109 if (Result.getNode()) 3110 return Result; 3111 3112 // If we really need inline code and the target declined to provide it, 3113 // use a (potentially long) sequence of loads and stores. 3114 if (AlwaysInline) { 3115 assert(ConstantSize && "AlwaysInline requires a constant size!"); 3116 return getMemcpyLoadsAndStores(*this, Chain, Dst, Src, 3117 ConstantSize->getZExtValue(), Align, true, 3118 DstSV, DstSVOff, SrcSV, SrcSVOff); 3119 } 3120 3121 // Emit a library call. 3122 TargetLowering::ArgListTy Args; 3123 TargetLowering::ArgListEntry Entry; 3124 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 3125 Entry.Node = Dst; Args.push_back(Entry); 3126 Entry.Node = Src; Args.push_back(Entry); 3127 Entry.Node = Size; Args.push_back(Entry); 3128 std::pair<SDValue,SDValue> CallResult = 3129 TLI.LowerCallTo(Chain, Type::VoidTy, 3130 false, false, false, false, CallingConv::C, false, 3131 getExternalSymbol("memcpy", TLI.getPointerTy()), 3132 Args, *this); 3133 return CallResult.second; 3134} 3135 3136SDValue SelectionDAG::getMemmove(SDValue Chain, SDValue Dst, 3137 SDValue Src, SDValue Size, 3138 unsigned Align, 3139 const Value *DstSV, uint64_t DstSVOff, 3140 const Value *SrcSV, uint64_t SrcSVOff) { 3141 3142 // Check to see if we should lower the memmove to loads and stores first. 3143 // For cases within the target-specified limits, this is the best choice. 3144 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 3145 if (ConstantSize) { 3146 // Memmove with size zero? Just return the original chain. 3147 if (ConstantSize->isNullValue()) 3148 return Chain; 3149 3150 SDValue Result = 3151 getMemmoveLoadsAndStores(*this, Chain, Dst, Src, 3152 ConstantSize->getZExtValue(), 3153 Align, false, DstSV, DstSVOff, SrcSV, SrcSVOff); 3154 if (Result.getNode()) 3155 return Result; 3156 } 3157 3158 // Then check to see if we should lower the memmove with target-specific 3159 // code. If the target chooses to do this, this is the next best. 3160 SDValue Result = 3161 TLI.EmitTargetCodeForMemmove(*this, Chain, Dst, Src, Size, Align, 3162 DstSV, DstSVOff, SrcSV, SrcSVOff); 3163 if (Result.getNode()) 3164 return Result; 3165 3166 // Emit a library call. 3167 TargetLowering::ArgListTy Args; 3168 TargetLowering::ArgListEntry Entry; 3169 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 3170 Entry.Node = Dst; Args.push_back(Entry); 3171 Entry.Node = Src; Args.push_back(Entry); 3172 Entry.Node = Size; Args.push_back(Entry); 3173 std::pair<SDValue,SDValue> CallResult = 3174 TLI.LowerCallTo(Chain, Type::VoidTy, 3175 false, false, false, false, CallingConv::C, false, 3176 getExternalSymbol("memmove", TLI.getPointerTy()), 3177 Args, *this); 3178 return CallResult.second; 3179} 3180 3181SDValue SelectionDAG::getMemset(SDValue Chain, SDValue Dst, 3182 SDValue Src, SDValue Size, 3183 unsigned Align, 3184 const Value *DstSV, uint64_t DstSVOff) { 3185 3186 // Check to see if we should lower the memset to stores first. 3187 // For cases within the target-specified limits, this is the best choice. 3188 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 3189 if (ConstantSize) { 3190 // Memset with size zero? Just return the original chain. 3191 if (ConstantSize->isNullValue()) 3192 return Chain; 3193 3194 SDValue Result = 3195 getMemsetStores(*this, Chain, Dst, Src, ConstantSize->getZExtValue(), 3196 Align, DstSV, DstSVOff); 3197 if (Result.getNode()) 3198 return Result; 3199 } 3200 3201 // Then check to see if we should lower the memset with target-specific 3202 // code. If the target chooses to do this, this is the next best. 3203 SDValue Result = 3204 TLI.EmitTargetCodeForMemset(*this, Chain, Dst, Src, Size, Align, 3205 DstSV, DstSVOff); 3206 if (Result.getNode()) 3207 return Result; 3208 3209 // Emit a library call. 3210 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType(); 3211 TargetLowering::ArgListTy Args; 3212 TargetLowering::ArgListEntry Entry; 3213 Entry.Node = Dst; Entry.Ty = IntPtrTy; 3214 Args.push_back(Entry); 3215 // Extend or truncate the argument to be an i32 value for the call. 3216 if (Src.getValueType().bitsGT(MVT::i32)) 3217 Src = getNode(ISD::TRUNCATE, MVT::i32, Src); 3218 else 3219 Src = getNode(ISD::ZERO_EXTEND, MVT::i32, Src); 3220 Entry.Node = Src; Entry.Ty = Type::Int32Ty; Entry.isSExt = true; 3221 Args.push_back(Entry); 3222 Entry.Node = Size; Entry.Ty = IntPtrTy; Entry.isSExt = false; 3223 Args.push_back(Entry); 3224 std::pair<SDValue,SDValue> CallResult = 3225 TLI.LowerCallTo(Chain, Type::VoidTy, 3226 false, false, false, false, CallingConv::C, false, 3227 getExternalSymbol("memset", TLI.getPointerTy()), 3228 Args, *this); 3229 return CallResult.second; 3230} 3231 3232SDValue SelectionDAG::getAtomic(unsigned Opcode, SDValue Chain, 3233 SDValue Ptr, SDValue Cmp, 3234 SDValue Swp, const Value* PtrVal, 3235 unsigned Alignment) { 3236 assert((Opcode == ISD::ATOMIC_CMP_SWAP_8 || 3237 Opcode == ISD::ATOMIC_CMP_SWAP_16 || 3238 Opcode == ISD::ATOMIC_CMP_SWAP_32 || 3239 Opcode == ISD::ATOMIC_CMP_SWAP_64) && "Invalid Atomic Op"); 3240 assert(Cmp.getValueType() == Swp.getValueType() && "Invalid Atomic Op Types"); 3241 3242 MVT VT = Cmp.getValueType(); 3243 3244 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3245 Alignment = getMVTAlignment(VT); 3246 3247 SDVTList VTs = getVTList(VT, MVT::Other); 3248 FoldingSetNodeID ID; 3249 SDValue Ops[] = {Chain, Ptr, Cmp, Swp}; 3250 AddNodeIDNode(ID, Opcode, VTs, Ops, 4); 3251 void* IP = 0; 3252 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3253 return SDValue(E, 0); 3254 SDNode* N = NodeAllocator.Allocate<AtomicSDNode>(); 3255 new (N) AtomicSDNode(Opcode, VTs, Chain, Ptr, Cmp, Swp, PtrVal, Alignment); 3256 CSEMap.InsertNode(N, IP); 3257 AllNodes.push_back(N); 3258 return SDValue(N, 0); 3259} 3260 3261SDValue SelectionDAG::getAtomic(unsigned Opcode, SDValue Chain, 3262 SDValue Ptr, SDValue Val, 3263 const Value* PtrVal, 3264 unsigned Alignment) { 3265 assert((Opcode == ISD::ATOMIC_LOAD_ADD_8 || 3266 Opcode == ISD::ATOMIC_LOAD_SUB_8 || 3267 Opcode == ISD::ATOMIC_LOAD_AND_8 || 3268 Opcode == ISD::ATOMIC_LOAD_OR_8 || 3269 Opcode == ISD::ATOMIC_LOAD_XOR_8 || 3270 Opcode == ISD::ATOMIC_LOAD_NAND_8 || 3271 Opcode == ISD::ATOMIC_LOAD_MIN_8 || 3272 Opcode == ISD::ATOMIC_LOAD_MAX_8 || 3273 Opcode == ISD::ATOMIC_LOAD_UMIN_8 || 3274 Opcode == ISD::ATOMIC_LOAD_UMAX_8 || 3275 Opcode == ISD::ATOMIC_SWAP_8 || 3276 Opcode == ISD::ATOMIC_LOAD_ADD_16 || 3277 Opcode == ISD::ATOMIC_LOAD_SUB_16 || 3278 Opcode == ISD::ATOMIC_LOAD_AND_16 || 3279 Opcode == ISD::ATOMIC_LOAD_OR_16 || 3280 Opcode == ISD::ATOMIC_LOAD_XOR_16 || 3281 Opcode == ISD::ATOMIC_LOAD_NAND_16 || 3282 Opcode == ISD::ATOMIC_LOAD_MIN_16 || 3283 Opcode == ISD::ATOMIC_LOAD_MAX_16 || 3284 Opcode == ISD::ATOMIC_LOAD_UMIN_16 || 3285 Opcode == ISD::ATOMIC_LOAD_UMAX_16 || 3286 Opcode == ISD::ATOMIC_SWAP_16 || 3287 Opcode == ISD::ATOMIC_LOAD_ADD_32 || 3288 Opcode == ISD::ATOMIC_LOAD_SUB_32 || 3289 Opcode == ISD::ATOMIC_LOAD_AND_32 || 3290 Opcode == ISD::ATOMIC_LOAD_OR_32 || 3291 Opcode == ISD::ATOMIC_LOAD_XOR_32 || 3292 Opcode == ISD::ATOMIC_LOAD_NAND_32 || 3293 Opcode == ISD::ATOMIC_LOAD_MIN_32 || 3294 Opcode == ISD::ATOMIC_LOAD_MAX_32 || 3295 Opcode == ISD::ATOMIC_LOAD_UMIN_32 || 3296 Opcode == ISD::ATOMIC_LOAD_UMAX_32 || 3297 Opcode == ISD::ATOMIC_SWAP_32 || 3298 Opcode == ISD::ATOMIC_LOAD_ADD_64 || 3299 Opcode == ISD::ATOMIC_LOAD_SUB_64 || 3300 Opcode == ISD::ATOMIC_LOAD_AND_64 || 3301 Opcode == ISD::ATOMIC_LOAD_OR_64 || 3302 Opcode == ISD::ATOMIC_LOAD_XOR_64 || 3303 Opcode == ISD::ATOMIC_LOAD_NAND_64 || 3304 Opcode == ISD::ATOMIC_LOAD_MIN_64 || 3305 Opcode == ISD::ATOMIC_LOAD_MAX_64 || 3306 Opcode == ISD::ATOMIC_LOAD_UMIN_64 || 3307 Opcode == ISD::ATOMIC_LOAD_UMAX_64 || 3308 Opcode == ISD::ATOMIC_SWAP_64) && "Invalid Atomic Op"); 3309 3310 MVT VT = Val.getValueType(); 3311 3312 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3313 Alignment = getMVTAlignment(VT); 3314 3315 SDVTList VTs = getVTList(VT, MVT::Other); 3316 FoldingSetNodeID ID; 3317 SDValue Ops[] = {Chain, Ptr, Val}; 3318 AddNodeIDNode(ID, Opcode, VTs, Ops, 3); 3319 void* IP = 0; 3320 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3321 return SDValue(E, 0); 3322 SDNode* N = NodeAllocator.Allocate<AtomicSDNode>(); 3323 new (N) AtomicSDNode(Opcode, VTs, Chain, Ptr, Val, PtrVal, Alignment); 3324 CSEMap.InsertNode(N, IP); 3325 AllNodes.push_back(N); 3326 return SDValue(N, 0); 3327} 3328 3329/// getMergeValues - Create a MERGE_VALUES node from the given operands. 3330/// Allowed to return something different (and simpler) if Simplify is true. 3331SDValue SelectionDAG::getMergeValues(const SDValue *Ops, unsigned NumOps, 3332 bool Simplify) { 3333 if (Simplify && NumOps == 1) 3334 return Ops[0]; 3335 3336 SmallVector<MVT, 4> VTs; 3337 VTs.reserve(NumOps); 3338 for (unsigned i = 0; i < NumOps; ++i) 3339 VTs.push_back(Ops[i].getValueType()); 3340 return getNode(ISD::MERGE_VALUES, getVTList(&VTs[0], NumOps), Ops, NumOps); 3341} 3342 3343SDValue 3344SelectionDAG::getMemIntrinsicNode(unsigned Opcode, 3345 const MVT *VTs, unsigned NumVTs, 3346 const SDValue *Ops, unsigned NumOps, 3347 MVT MemVT, const Value *srcValue, int SVOff, 3348 unsigned Align, bool Vol, 3349 bool ReadMem, bool WriteMem) { 3350 return getMemIntrinsicNode(Opcode, makeVTList(VTs, NumVTs), Ops, NumOps, 3351 MemVT, srcValue, SVOff, Align, Vol, 3352 ReadMem, WriteMem); 3353} 3354 3355SDValue 3356SelectionDAG::getMemIntrinsicNode(unsigned Opcode, SDVTList VTList, 3357 const SDValue *Ops, unsigned NumOps, 3358 MVT MemVT, const Value *srcValue, int SVOff, 3359 unsigned Align, bool Vol, 3360 bool ReadMem, bool WriteMem) { 3361 // Memoize the node unless it returns a flag. 3362 MemIntrinsicSDNode *N; 3363 if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) { 3364 FoldingSetNodeID ID; 3365 AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps); 3366 void *IP = 0; 3367 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3368 return SDValue(E, 0); 3369 3370 N = NodeAllocator.Allocate<MemIntrinsicSDNode>(); 3371 new (N) MemIntrinsicSDNode(Opcode, VTList, Ops, NumOps, MemVT, 3372 srcValue, SVOff, Align, Vol, ReadMem, WriteMem); 3373 CSEMap.InsertNode(N, IP); 3374 } else { 3375 N = NodeAllocator.Allocate<MemIntrinsicSDNode>(); 3376 new (N) MemIntrinsicSDNode(Opcode, VTList, Ops, NumOps, MemVT, 3377 srcValue, SVOff, Align, Vol, ReadMem, WriteMem); 3378 } 3379 AllNodes.push_back(N); 3380 return SDValue(N, 0); 3381} 3382 3383SDValue 3384SelectionDAG::getCall(unsigned CallingConv, bool IsVarArgs, bool IsTailCall, 3385 bool IsInreg, SDVTList VTs, 3386 const SDValue *Operands, unsigned NumOperands) { 3387 // Do not include isTailCall in the folding set profile. 3388 FoldingSetNodeID ID; 3389 AddNodeIDNode(ID, ISD::CALL, VTs, Operands, NumOperands); 3390 ID.AddInteger(CallingConv); 3391 ID.AddInteger(IsVarArgs); 3392 void *IP = 0; 3393 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) { 3394 // Instead of including isTailCall in the folding set, we just 3395 // set the flag of the existing node. 3396 if (!IsTailCall) 3397 cast<CallSDNode>(E)->setNotTailCall(); 3398 return SDValue(E, 0); 3399 } 3400 SDNode *N = NodeAllocator.Allocate<CallSDNode>(); 3401 new (N) CallSDNode(CallingConv, IsVarArgs, IsTailCall, IsInreg, 3402 VTs, Operands, NumOperands); 3403 CSEMap.InsertNode(N, IP); 3404 AllNodes.push_back(N); 3405 return SDValue(N, 0); 3406} 3407 3408SDValue 3409SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, 3410 MVT VT, SDValue Chain, 3411 SDValue Ptr, SDValue Offset, 3412 const Value *SV, int SVOffset, MVT EVT, 3413 bool isVolatile, unsigned Alignment) { 3414 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3415 Alignment = getMVTAlignment(VT); 3416 3417 if (VT == EVT) { 3418 ExtType = ISD::NON_EXTLOAD; 3419 } else if (ExtType == ISD::NON_EXTLOAD) { 3420 assert(VT == EVT && "Non-extending load from different memory type!"); 3421 } else { 3422 // Extending load. 3423 if (VT.isVector()) 3424 assert(EVT.getVectorNumElements() == VT.getVectorNumElements() && 3425 "Invalid vector extload!"); 3426 else 3427 assert(EVT.bitsLT(VT) && 3428 "Should only be an extending load, not truncating!"); 3429 assert((ExtType == ISD::EXTLOAD || VT.isInteger()) && 3430 "Cannot sign/zero extend a FP/Vector load!"); 3431 assert(VT.isInteger() == EVT.isInteger() && 3432 "Cannot convert from FP to Int or Int -> FP!"); 3433 } 3434 3435 bool Indexed = AM != ISD::UNINDEXED; 3436 assert((Indexed || Offset.getOpcode() == ISD::UNDEF) && 3437 "Unindexed load with an offset!"); 3438 3439 SDVTList VTs = Indexed ? 3440 getVTList(VT, Ptr.getValueType(), MVT::Other) : getVTList(VT, MVT::Other); 3441 SDValue Ops[] = { Chain, Ptr, Offset }; 3442 FoldingSetNodeID ID; 3443 AddNodeIDNode(ID, ISD::LOAD, VTs, Ops, 3); 3444 ID.AddInteger(AM); 3445 ID.AddInteger(ExtType); 3446 ID.AddInteger(EVT.getRawBits()); 3447 ID.AddInteger(encodeMemSDNodeFlags(isVolatile, Alignment)); 3448 void *IP = 0; 3449 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3450 return SDValue(E, 0); 3451 SDNode *N = NodeAllocator.Allocate<LoadSDNode>(); 3452 new (N) LoadSDNode(Ops, VTs, AM, ExtType, EVT, SV, SVOffset, 3453 Alignment, isVolatile); 3454 CSEMap.InsertNode(N, IP); 3455 AllNodes.push_back(N); 3456 return SDValue(N, 0); 3457} 3458 3459SDValue SelectionDAG::getLoad(MVT VT, 3460 SDValue Chain, SDValue Ptr, 3461 const Value *SV, int SVOffset, 3462 bool isVolatile, unsigned Alignment) { 3463 SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType()); 3464 return getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD, VT, Chain, Ptr, Undef, 3465 SV, SVOffset, VT, isVolatile, Alignment); 3466} 3467 3468SDValue SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, MVT VT, 3469 SDValue Chain, SDValue Ptr, 3470 const Value *SV, 3471 int SVOffset, MVT EVT, 3472 bool isVolatile, unsigned Alignment) { 3473 SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType()); 3474 return getLoad(ISD::UNINDEXED, ExtType, VT, Chain, Ptr, Undef, 3475 SV, SVOffset, EVT, isVolatile, Alignment); 3476} 3477 3478SDValue 3479SelectionDAG::getIndexedLoad(SDValue OrigLoad, SDValue Base, 3480 SDValue Offset, ISD::MemIndexedMode AM) { 3481 LoadSDNode *LD = cast<LoadSDNode>(OrigLoad); 3482 assert(LD->getOffset().getOpcode() == ISD::UNDEF && 3483 "Load is already a indexed load!"); 3484 return getLoad(AM, LD->getExtensionType(), OrigLoad.getValueType(), 3485 LD->getChain(), Base, Offset, LD->getSrcValue(), 3486 LD->getSrcValueOffset(), LD->getMemoryVT(), 3487 LD->isVolatile(), LD->getAlignment()); 3488} 3489 3490SDValue SelectionDAG::getStore(SDValue Chain, SDValue Val, 3491 SDValue Ptr, const Value *SV, int SVOffset, 3492 bool isVolatile, unsigned Alignment) { 3493 MVT VT = Val.getValueType(); 3494 3495 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3496 Alignment = getMVTAlignment(VT); 3497 3498 SDVTList VTs = getVTList(MVT::Other); 3499 SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType()); 3500 SDValue Ops[] = { Chain, Val, Ptr, Undef }; 3501 FoldingSetNodeID ID; 3502 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); 3503 ID.AddInteger(ISD::UNINDEXED); 3504 ID.AddInteger(false); 3505 ID.AddInteger(VT.getRawBits()); 3506 ID.AddInteger(encodeMemSDNodeFlags(isVolatile, Alignment)); 3507 void *IP = 0; 3508 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3509 return SDValue(E, 0); 3510 SDNode *N = NodeAllocator.Allocate<StoreSDNode>(); 3511 new (N) StoreSDNode(Ops, VTs, ISD::UNINDEXED, false, 3512 VT, SV, SVOffset, Alignment, isVolatile); 3513 CSEMap.InsertNode(N, IP); 3514 AllNodes.push_back(N); 3515 return SDValue(N, 0); 3516} 3517 3518SDValue SelectionDAG::getTruncStore(SDValue Chain, SDValue Val, 3519 SDValue Ptr, const Value *SV, 3520 int SVOffset, MVT SVT, 3521 bool isVolatile, unsigned Alignment) { 3522 MVT VT = Val.getValueType(); 3523 3524 if (VT == SVT) 3525 return getStore(Chain, Val, Ptr, SV, SVOffset, isVolatile, Alignment); 3526 3527 assert(VT.bitsGT(SVT) && "Not a truncation?"); 3528 assert(VT.isInteger() == SVT.isInteger() && 3529 "Can't do FP-INT conversion!"); 3530 3531 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3532 Alignment = getMVTAlignment(VT); 3533 3534 SDVTList VTs = getVTList(MVT::Other); 3535 SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType()); 3536 SDValue Ops[] = { Chain, Val, Ptr, Undef }; 3537 FoldingSetNodeID ID; 3538 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); 3539 ID.AddInteger(ISD::UNINDEXED); 3540 ID.AddInteger(1); 3541 ID.AddInteger(SVT.getRawBits()); 3542 ID.AddInteger(encodeMemSDNodeFlags(isVolatile, Alignment)); 3543 void *IP = 0; 3544 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3545 return SDValue(E, 0); 3546 SDNode *N = NodeAllocator.Allocate<StoreSDNode>(); 3547 new (N) StoreSDNode(Ops, VTs, ISD::UNINDEXED, true, 3548 SVT, SV, SVOffset, Alignment, isVolatile); 3549 CSEMap.InsertNode(N, IP); 3550 AllNodes.push_back(N); 3551 return SDValue(N, 0); 3552} 3553 3554SDValue 3555SelectionDAG::getIndexedStore(SDValue OrigStore, SDValue Base, 3556 SDValue Offset, ISD::MemIndexedMode AM) { 3557 StoreSDNode *ST = cast<StoreSDNode>(OrigStore); 3558 assert(ST->getOffset().getOpcode() == ISD::UNDEF && 3559 "Store is already a indexed store!"); 3560 SDVTList VTs = getVTList(Base.getValueType(), MVT::Other); 3561 SDValue Ops[] = { ST->getChain(), ST->getValue(), Base, Offset }; 3562 FoldingSetNodeID ID; 3563 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); 3564 ID.AddInteger(AM); 3565 ID.AddInteger(ST->isTruncatingStore()); 3566 ID.AddInteger(ST->getMemoryVT().getRawBits()); 3567 ID.AddInteger(ST->getRawFlags()); 3568 void *IP = 0; 3569 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3570 return SDValue(E, 0); 3571 SDNode *N = NodeAllocator.Allocate<StoreSDNode>(); 3572 new (N) StoreSDNode(Ops, VTs, AM, 3573 ST->isTruncatingStore(), ST->getMemoryVT(), 3574 ST->getSrcValue(), ST->getSrcValueOffset(), 3575 ST->getAlignment(), ST->isVolatile()); 3576 CSEMap.InsertNode(N, IP); 3577 AllNodes.push_back(N); 3578 return SDValue(N, 0); 3579} 3580 3581SDValue SelectionDAG::getVAArg(MVT VT, 3582 SDValue Chain, SDValue Ptr, 3583 SDValue SV) { 3584 SDValue Ops[] = { Chain, Ptr, SV }; 3585 return getNode(ISD::VAARG, getVTList(VT, MVT::Other), Ops, 3); 3586} 3587 3588SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, 3589 const SDUse *Ops, unsigned NumOps) { 3590 switch (NumOps) { 3591 case 0: return getNode(Opcode, VT); 3592 case 1: return getNode(Opcode, VT, Ops[0]); 3593 case 2: return getNode(Opcode, VT, Ops[0], Ops[1]); 3594 case 3: return getNode(Opcode, VT, Ops[0], Ops[1], Ops[2]); 3595 default: break; 3596 } 3597 3598 // Copy from an SDUse array into an SDValue array for use with 3599 // the regular getNode logic. 3600 SmallVector<SDValue, 8> NewOps(Ops, Ops + NumOps); 3601 return getNode(Opcode, VT, &NewOps[0], NumOps); 3602} 3603 3604SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, 3605 const SDValue *Ops, unsigned NumOps) { 3606 switch (NumOps) { 3607 case 0: return getNode(Opcode, VT); 3608 case 1: return getNode(Opcode, VT, Ops[0]); 3609 case 2: return getNode(Opcode, VT, Ops[0], Ops[1]); 3610 case 3: return getNode(Opcode, VT, Ops[0], Ops[1], Ops[2]); 3611 default: break; 3612 } 3613 3614 switch (Opcode) { 3615 default: break; 3616 case ISD::SELECT_CC: { 3617 assert(NumOps == 5 && "SELECT_CC takes 5 operands!"); 3618 assert(Ops[0].getValueType() == Ops[1].getValueType() && 3619 "LHS and RHS of condition must have same type!"); 3620 assert(Ops[2].getValueType() == Ops[3].getValueType() && 3621 "True and False arms of SelectCC must have same type!"); 3622 assert(Ops[2].getValueType() == VT && 3623 "select_cc node must be of same type as true and false value!"); 3624 break; 3625 } 3626 case ISD::BR_CC: { 3627 assert(NumOps == 5 && "BR_CC takes 5 operands!"); 3628 assert(Ops[2].getValueType() == Ops[3].getValueType() && 3629 "LHS/RHS of comparison should match types!"); 3630 break; 3631 } 3632 } 3633 3634 // Memoize nodes. 3635 SDNode *N; 3636 SDVTList VTs = getVTList(VT); 3637 if (VT != MVT::Flag) { 3638 FoldingSetNodeID ID; 3639 AddNodeIDNode(ID, Opcode, VTs, Ops, NumOps); 3640 void *IP = 0; 3641 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3642 return SDValue(E, 0); 3643 N = NodeAllocator.Allocate<SDNode>(); 3644 new (N) SDNode(Opcode, VTs, Ops, NumOps); 3645 CSEMap.InsertNode(N, IP); 3646 } else { 3647 N = NodeAllocator.Allocate<SDNode>(); 3648 new (N) SDNode(Opcode, VTs, Ops, NumOps); 3649 } 3650 AllNodes.push_back(N); 3651#ifndef NDEBUG 3652 VerifyNode(N); 3653#endif 3654 return SDValue(N, 0); 3655} 3656 3657SDValue SelectionDAG::getNode(unsigned Opcode, 3658 const std::vector<MVT> &ResultTys, 3659 const SDValue *Ops, unsigned NumOps) { 3660 return getNode(Opcode, getNodeValueTypes(ResultTys), ResultTys.size(), 3661 Ops, NumOps); 3662} 3663 3664SDValue SelectionDAG::getNode(unsigned Opcode, 3665 const MVT *VTs, unsigned NumVTs, 3666 const SDValue *Ops, unsigned NumOps) { 3667 if (NumVTs == 1) 3668 return getNode(Opcode, VTs[0], Ops, NumOps); 3669 return getNode(Opcode, makeVTList(VTs, NumVTs), Ops, NumOps); 3670} 3671 3672SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, 3673 const SDValue *Ops, unsigned NumOps) { 3674 if (VTList.NumVTs == 1) 3675 return getNode(Opcode, VTList.VTs[0], Ops, NumOps); 3676 3677 switch (Opcode) { 3678 // FIXME: figure out how to safely handle things like 3679 // int foo(int x) { return 1 << (x & 255); } 3680 // int bar() { return foo(256); } 3681#if 0 3682 case ISD::SRA_PARTS: 3683 case ISD::SRL_PARTS: 3684 case ISD::SHL_PARTS: 3685 if (N3.getOpcode() == ISD::SIGN_EXTEND_INREG && 3686 cast<VTSDNode>(N3.getOperand(1))->getVT() != MVT::i1) 3687 return getNode(Opcode, VT, N1, N2, N3.getOperand(0)); 3688 else if (N3.getOpcode() == ISD::AND) 3689 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(N3.getOperand(1))) { 3690 // If the and is only masking out bits that cannot effect the shift, 3691 // eliminate the and. 3692 unsigned NumBits = VT.getSizeInBits()*2; 3693 if ((AndRHS->getValue() & (NumBits-1)) == NumBits-1) 3694 return getNode(Opcode, VT, N1, N2, N3.getOperand(0)); 3695 } 3696 break; 3697#endif 3698 } 3699 3700 // Memoize the node unless it returns a flag. 3701 SDNode *N; 3702 if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) { 3703 FoldingSetNodeID ID; 3704 AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps); 3705 void *IP = 0; 3706 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3707 return SDValue(E, 0); 3708 if (NumOps == 1) { 3709 N = NodeAllocator.Allocate<UnarySDNode>(); 3710 new (N) UnarySDNode(Opcode, VTList, Ops[0]); 3711 } else if (NumOps == 2) { 3712 N = NodeAllocator.Allocate<BinarySDNode>(); 3713 new (N) BinarySDNode(Opcode, VTList, Ops[0], Ops[1]); 3714 } else if (NumOps == 3) { 3715 N = NodeAllocator.Allocate<TernarySDNode>(); 3716 new (N) TernarySDNode(Opcode, VTList, Ops[0], Ops[1], Ops[2]); 3717 } else { 3718 N = NodeAllocator.Allocate<SDNode>(); 3719 new (N) SDNode(Opcode, VTList, Ops, NumOps); 3720 } 3721 CSEMap.InsertNode(N, IP); 3722 } else { 3723 if (NumOps == 1) { 3724 N = NodeAllocator.Allocate<UnarySDNode>(); 3725 new (N) UnarySDNode(Opcode, VTList, Ops[0]); 3726 } else if (NumOps == 2) { 3727 N = NodeAllocator.Allocate<BinarySDNode>(); 3728 new (N) BinarySDNode(Opcode, VTList, Ops[0], Ops[1]); 3729 } else if (NumOps == 3) { 3730 N = NodeAllocator.Allocate<TernarySDNode>(); 3731 new (N) TernarySDNode(Opcode, VTList, Ops[0], Ops[1], Ops[2]); 3732 } else { 3733 N = NodeAllocator.Allocate<SDNode>(); 3734 new (N) SDNode(Opcode, VTList, Ops, NumOps); 3735 } 3736 } 3737 AllNodes.push_back(N); 3738#ifndef NDEBUG 3739 VerifyNode(N); 3740#endif 3741 return SDValue(N, 0); 3742} 3743 3744SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList) { 3745 return getNode(Opcode, VTList, 0, 0); 3746} 3747 3748SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, 3749 SDValue N1) { 3750 SDValue Ops[] = { N1 }; 3751 return getNode(Opcode, VTList, Ops, 1); 3752} 3753 3754SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, 3755 SDValue N1, SDValue N2) { 3756 SDValue Ops[] = { N1, N2 }; 3757 return getNode(Opcode, VTList, Ops, 2); 3758} 3759 3760SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, 3761 SDValue N1, SDValue N2, SDValue N3) { 3762 SDValue Ops[] = { N1, N2, N3 }; 3763 return getNode(Opcode, VTList, Ops, 3); 3764} 3765 3766SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, 3767 SDValue N1, SDValue N2, SDValue N3, 3768 SDValue N4) { 3769 SDValue Ops[] = { N1, N2, N3, N4 }; 3770 return getNode(Opcode, VTList, Ops, 4); 3771} 3772 3773SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, 3774 SDValue N1, SDValue N2, SDValue N3, 3775 SDValue N4, SDValue N5) { 3776 SDValue Ops[] = { N1, N2, N3, N4, N5 }; 3777 return getNode(Opcode, VTList, Ops, 5); 3778} 3779 3780SDVTList SelectionDAG::getVTList(MVT VT) { 3781 return makeVTList(SDNode::getValueTypeList(VT), 1); 3782} 3783 3784SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2) { 3785 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 3786 E = VTList.rend(); I != E; ++I) 3787 if (I->NumVTs == 2 && I->VTs[0] == VT1 && I->VTs[1] == VT2) 3788 return *I; 3789 3790 MVT *Array = Allocator.Allocate<MVT>(2); 3791 Array[0] = VT1; 3792 Array[1] = VT2; 3793 SDVTList Result = makeVTList(Array, 2); 3794 VTList.push_back(Result); 3795 return Result; 3796} 3797 3798SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2, MVT VT3) { 3799 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 3800 E = VTList.rend(); I != E; ++I) 3801 if (I->NumVTs == 3 && I->VTs[0] == VT1 && I->VTs[1] == VT2 && 3802 I->VTs[2] == VT3) 3803 return *I; 3804 3805 MVT *Array = Allocator.Allocate<MVT>(3); 3806 Array[0] = VT1; 3807 Array[1] = VT2; 3808 Array[2] = VT3; 3809 SDVTList Result = makeVTList(Array, 3); 3810 VTList.push_back(Result); 3811 return Result; 3812} 3813 3814SDVTList SelectionDAG::getVTList(const MVT *VTs, unsigned NumVTs) { 3815 switch (NumVTs) { 3816 case 0: assert(0 && "Cannot have nodes without results!"); 3817 case 1: return getVTList(VTs[0]); 3818 case 2: return getVTList(VTs[0], VTs[1]); 3819 case 3: return getVTList(VTs[0], VTs[1], VTs[2]); 3820 default: break; 3821 } 3822 3823 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 3824 E = VTList.rend(); I != E; ++I) { 3825 if (I->NumVTs != NumVTs || VTs[0] != I->VTs[0] || VTs[1] != I->VTs[1]) 3826 continue; 3827 3828 bool NoMatch = false; 3829 for (unsigned i = 2; i != NumVTs; ++i) 3830 if (VTs[i] != I->VTs[i]) { 3831 NoMatch = true; 3832 break; 3833 } 3834 if (!NoMatch) 3835 return *I; 3836 } 3837 3838 MVT *Array = Allocator.Allocate<MVT>(NumVTs); 3839 std::copy(VTs, VTs+NumVTs, Array); 3840 SDVTList Result = makeVTList(Array, NumVTs); 3841 VTList.push_back(Result); 3842 return Result; 3843} 3844 3845 3846/// UpdateNodeOperands - *Mutate* the specified node in-place to have the 3847/// specified operands. If the resultant node already exists in the DAG, 3848/// this does not modify the specified node, instead it returns the node that 3849/// already exists. If the resultant node does not exist in the DAG, the 3850/// input node is returned. As a degenerate case, if you specify the same 3851/// input operands as the node already has, the input node is returned. 3852SDValue SelectionDAG::UpdateNodeOperands(SDValue InN, SDValue Op) { 3853 SDNode *N = InN.getNode(); 3854 assert(N->getNumOperands() == 1 && "Update with wrong number of operands"); 3855 3856 // Check to see if there is no change. 3857 if (Op == N->getOperand(0)) return InN; 3858 3859 // See if the modified node already exists. 3860 void *InsertPos = 0; 3861 if (SDNode *Existing = FindModifiedNodeSlot(N, Op, InsertPos)) 3862 return SDValue(Existing, InN.getResNo()); 3863 3864 // Nope it doesn't. Remove the node from its current place in the maps. 3865 if (InsertPos) 3866 if (!RemoveNodeFromCSEMaps(N)) 3867 InsertPos = 0; 3868 3869 // Now we update the operands. 3870 N->OperandList[0].getVal()->removeUser(0, N); 3871 N->OperandList[0] = Op; 3872 N->OperandList[0].setUser(N); 3873 Op.getNode()->addUser(0, N); 3874 3875 // If this gets put into a CSE map, add it. 3876 if (InsertPos) CSEMap.InsertNode(N, InsertPos); 3877 return InN; 3878} 3879 3880SDValue SelectionDAG:: 3881UpdateNodeOperands(SDValue InN, SDValue Op1, SDValue Op2) { 3882 SDNode *N = InN.getNode(); 3883 assert(N->getNumOperands() == 2 && "Update with wrong number of operands"); 3884 3885 // Check to see if there is no change. 3886 if (Op1 == N->getOperand(0) && Op2 == N->getOperand(1)) 3887 return InN; // No operands changed, just return the input node. 3888 3889 // See if the modified node already exists. 3890 void *InsertPos = 0; 3891 if (SDNode *Existing = FindModifiedNodeSlot(N, Op1, Op2, InsertPos)) 3892 return SDValue(Existing, InN.getResNo()); 3893 3894 // Nope it doesn't. Remove the node from its current place in the maps. 3895 if (InsertPos) 3896 if (!RemoveNodeFromCSEMaps(N)) 3897 InsertPos = 0; 3898 3899 // Now we update the operands. 3900 if (N->OperandList[0] != Op1) { 3901 N->OperandList[0].getVal()->removeUser(0, N); 3902 N->OperandList[0] = Op1; 3903 N->OperandList[0].setUser(N); 3904 Op1.getNode()->addUser(0, N); 3905 } 3906 if (N->OperandList[1] != Op2) { 3907 N->OperandList[1].getVal()->removeUser(1, N); 3908 N->OperandList[1] = Op2; 3909 N->OperandList[1].setUser(N); 3910 Op2.getNode()->addUser(1, N); 3911 } 3912 3913 // If this gets put into a CSE map, add it. 3914 if (InsertPos) CSEMap.InsertNode(N, InsertPos); 3915 return InN; 3916} 3917 3918SDValue SelectionDAG:: 3919UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, SDValue Op3) { 3920 SDValue Ops[] = { Op1, Op2, Op3 }; 3921 return UpdateNodeOperands(N, Ops, 3); 3922} 3923 3924SDValue SelectionDAG:: 3925UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, 3926 SDValue Op3, SDValue Op4) { 3927 SDValue Ops[] = { Op1, Op2, Op3, Op4 }; 3928 return UpdateNodeOperands(N, Ops, 4); 3929} 3930 3931SDValue SelectionDAG:: 3932UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, 3933 SDValue Op3, SDValue Op4, SDValue Op5) { 3934 SDValue Ops[] = { Op1, Op2, Op3, Op4, Op5 }; 3935 return UpdateNodeOperands(N, Ops, 5); 3936} 3937 3938SDValue SelectionDAG:: 3939UpdateNodeOperands(SDValue InN, const SDValue *Ops, unsigned NumOps) { 3940 SDNode *N = InN.getNode(); 3941 assert(N->getNumOperands() == NumOps && 3942 "Update with wrong number of operands"); 3943 3944 // Check to see if there is no change. 3945 bool AnyChange = false; 3946 for (unsigned i = 0; i != NumOps; ++i) { 3947 if (Ops[i] != N->getOperand(i)) { 3948 AnyChange = true; 3949 break; 3950 } 3951 } 3952 3953 // No operands changed, just return the input node. 3954 if (!AnyChange) return InN; 3955 3956 // See if the modified node already exists. 3957 void *InsertPos = 0; 3958 if (SDNode *Existing = FindModifiedNodeSlot(N, Ops, NumOps, InsertPos)) 3959 return SDValue(Existing, InN.getResNo()); 3960 3961 // Nope it doesn't. Remove the node from its current place in the maps. 3962 if (InsertPos) 3963 if (!RemoveNodeFromCSEMaps(N)) 3964 InsertPos = 0; 3965 3966 // Now we update the operands. 3967 for (unsigned i = 0; i != NumOps; ++i) { 3968 if (N->OperandList[i] != Ops[i]) { 3969 N->OperandList[i].getVal()->removeUser(i, N); 3970 N->OperandList[i] = Ops[i]; 3971 N->OperandList[i].setUser(N); 3972 Ops[i].getNode()->addUser(i, N); 3973 } 3974 } 3975 3976 // If this gets put into a CSE map, add it. 3977 if (InsertPos) CSEMap.InsertNode(N, InsertPos); 3978 return InN; 3979} 3980 3981/// DropOperands - Release the operands and set this node to have 3982/// zero operands. 3983void SDNode::DropOperands() { 3984 // Unlike the code in MorphNodeTo that does this, we don't need to 3985 // watch for dead nodes here. 3986 for (op_iterator I = op_begin(), E = op_end(); I != E; ++I) 3987 I->getVal()->removeUser(std::distance(op_begin(), I), this); 3988 3989 NumOperands = 0; 3990} 3991 3992/// SelectNodeTo - These are wrappers around MorphNodeTo that accept a 3993/// machine opcode. 3994/// 3995SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 3996 MVT VT) { 3997 SDVTList VTs = getVTList(VT); 3998 return SelectNodeTo(N, MachineOpc, VTs, 0, 0); 3999} 4000 4001SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4002 MVT VT, SDValue Op1) { 4003 SDVTList VTs = getVTList(VT); 4004 SDValue Ops[] = { Op1 }; 4005 return SelectNodeTo(N, MachineOpc, VTs, Ops, 1); 4006} 4007 4008SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4009 MVT VT, SDValue Op1, 4010 SDValue Op2) { 4011 SDVTList VTs = getVTList(VT); 4012 SDValue Ops[] = { Op1, Op2 }; 4013 return SelectNodeTo(N, MachineOpc, VTs, Ops, 2); 4014} 4015 4016SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4017 MVT VT, SDValue Op1, 4018 SDValue Op2, SDValue Op3) { 4019 SDVTList VTs = getVTList(VT); 4020 SDValue Ops[] = { Op1, Op2, Op3 }; 4021 return SelectNodeTo(N, MachineOpc, VTs, Ops, 3); 4022} 4023 4024SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4025 MVT VT, const SDValue *Ops, 4026 unsigned NumOps) { 4027 SDVTList VTs = getVTList(VT); 4028 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 4029} 4030 4031SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4032 MVT VT1, MVT VT2, const SDValue *Ops, 4033 unsigned NumOps) { 4034 SDVTList VTs = getVTList(VT1, VT2); 4035 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 4036} 4037 4038SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4039 MVT VT1, MVT VT2) { 4040 SDVTList VTs = getVTList(VT1, VT2); 4041 return SelectNodeTo(N, MachineOpc, VTs, (SDValue *)0, 0); 4042} 4043 4044SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4045 MVT VT1, MVT VT2, MVT VT3, 4046 const SDValue *Ops, unsigned NumOps) { 4047 SDVTList VTs = getVTList(VT1, VT2, VT3); 4048 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 4049} 4050 4051SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4052 MVT VT1, MVT VT2, 4053 SDValue Op1) { 4054 SDVTList VTs = getVTList(VT1, VT2); 4055 SDValue Ops[] = { Op1 }; 4056 return SelectNodeTo(N, MachineOpc, VTs, Ops, 1); 4057} 4058 4059SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4060 MVT VT1, MVT VT2, 4061 SDValue Op1, SDValue Op2) { 4062 SDVTList VTs = getVTList(VT1, VT2); 4063 SDValue Ops[] = { Op1, Op2 }; 4064 return SelectNodeTo(N, MachineOpc, VTs, Ops, 2); 4065} 4066 4067SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4068 MVT VT1, MVT VT2, 4069 SDValue Op1, SDValue Op2, 4070 SDValue Op3) { 4071 SDVTList VTs = getVTList(VT1, VT2); 4072 SDValue Ops[] = { Op1, Op2, Op3 }; 4073 return SelectNodeTo(N, MachineOpc, VTs, Ops, 3); 4074} 4075 4076SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4077 SDVTList VTs, const SDValue *Ops, 4078 unsigned NumOps) { 4079 return MorphNodeTo(N, ~MachineOpc, VTs, Ops, NumOps); 4080} 4081 4082SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4083 MVT VT) { 4084 SDVTList VTs = getVTList(VT); 4085 return MorphNodeTo(N, Opc, VTs, 0, 0); 4086} 4087 4088SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4089 MVT VT, SDValue Op1) { 4090 SDVTList VTs = getVTList(VT); 4091 SDValue Ops[] = { Op1 }; 4092 return MorphNodeTo(N, Opc, VTs, Ops, 1); 4093} 4094 4095SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4096 MVT VT, SDValue Op1, 4097 SDValue Op2) { 4098 SDVTList VTs = getVTList(VT); 4099 SDValue Ops[] = { Op1, Op2 }; 4100 return MorphNodeTo(N, Opc, VTs, Ops, 2); 4101} 4102 4103SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4104 MVT VT, SDValue Op1, 4105 SDValue Op2, SDValue Op3) { 4106 SDVTList VTs = getVTList(VT); 4107 SDValue Ops[] = { Op1, Op2, Op3 }; 4108 return MorphNodeTo(N, Opc, VTs, Ops, 3); 4109} 4110 4111SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4112 MVT VT, const SDValue *Ops, 4113 unsigned NumOps) { 4114 SDVTList VTs = getVTList(VT); 4115 return MorphNodeTo(N, Opc, VTs, Ops, NumOps); 4116} 4117 4118SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4119 MVT VT1, MVT VT2, const SDValue *Ops, 4120 unsigned NumOps) { 4121 SDVTList VTs = getVTList(VT1, VT2); 4122 return MorphNodeTo(N, Opc, VTs, Ops, NumOps); 4123} 4124 4125SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4126 MVT VT1, MVT VT2) { 4127 SDVTList VTs = getVTList(VT1, VT2); 4128 return MorphNodeTo(N, Opc, VTs, (SDValue *)0, 0); 4129} 4130 4131SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4132 MVT VT1, MVT VT2, MVT VT3, 4133 const SDValue *Ops, unsigned NumOps) { 4134 SDVTList VTs = getVTList(VT1, VT2, VT3); 4135 return MorphNodeTo(N, Opc, VTs, Ops, NumOps); 4136} 4137 4138SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4139 MVT VT1, MVT VT2, 4140 SDValue Op1) { 4141 SDVTList VTs = getVTList(VT1, VT2); 4142 SDValue Ops[] = { Op1 }; 4143 return MorphNodeTo(N, Opc, VTs, Ops, 1); 4144} 4145 4146SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4147 MVT VT1, MVT VT2, 4148 SDValue Op1, SDValue Op2) { 4149 SDVTList VTs = getVTList(VT1, VT2); 4150 SDValue Ops[] = { Op1, Op2 }; 4151 return MorphNodeTo(N, Opc, VTs, Ops, 2); 4152} 4153 4154SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4155 MVT VT1, MVT VT2, 4156 SDValue Op1, SDValue Op2, 4157 SDValue Op3) { 4158 SDVTList VTs = getVTList(VT1, VT2); 4159 SDValue Ops[] = { Op1, Op2, Op3 }; 4160 return MorphNodeTo(N, Opc, VTs, Ops, 3); 4161} 4162 4163/// MorphNodeTo - These *mutate* the specified node to have the specified 4164/// return type, opcode, and operands. 4165/// 4166/// Note that MorphNodeTo returns the resultant node. If there is already a 4167/// node of the specified opcode and operands, it returns that node instead of 4168/// the current one. 4169/// 4170/// Using MorphNodeTo is faster than creating a new node and swapping it in 4171/// with ReplaceAllUsesWith both because it often avoids allocating a new 4172/// node, and because it doesn't require CSE recalculation for any of 4173/// the node's users. 4174/// 4175SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4176 SDVTList VTs, const SDValue *Ops, 4177 unsigned NumOps) { 4178 // If an identical node already exists, use it. 4179 void *IP = 0; 4180 if (VTs.VTs[VTs.NumVTs-1] != MVT::Flag) { 4181 FoldingSetNodeID ID; 4182 AddNodeIDNode(ID, Opc, VTs, Ops, NumOps); 4183 if (SDNode *ON = CSEMap.FindNodeOrInsertPos(ID, IP)) 4184 return ON; 4185 } 4186 4187 if (!RemoveNodeFromCSEMaps(N)) 4188 IP = 0; 4189 4190 // Start the morphing. 4191 N->NodeType = Opc; 4192 N->ValueList = VTs.VTs; 4193 N->NumValues = VTs.NumVTs; 4194 4195 // Clear the operands list, updating used nodes to remove this from their 4196 // use list. Keep track of any operands that become dead as a result. 4197 SmallPtrSet<SDNode*, 16> DeadNodeSet; 4198 for (SDNode::op_iterator B = N->op_begin(), I = B, E = N->op_end(); 4199 I != E; ++I) { 4200 SDNode *Used = I->getVal(); 4201 Used->removeUser(std::distance(B, I), N); 4202 if (Used->use_empty()) 4203 DeadNodeSet.insert(Used); 4204 } 4205 4206 // If NumOps is larger than the # of operands we currently have, reallocate 4207 // the operand list. 4208 if (NumOps > N->NumOperands) { 4209 if (N->OperandsNeedDelete) 4210 delete[] N->OperandList; 4211 if (N->isMachineOpcode()) { 4212 // We're creating a final node that will live unmorphed for the 4213 // remainder of the current SelectionDAG iteration, so we can allocate 4214 // the operands directly out of a pool with no recycling metadata. 4215 N->OperandList = OperandAllocator.Allocate<SDUse>(NumOps); 4216 N->OperandsNeedDelete = false; 4217 } else { 4218 N->OperandList = new SDUse[NumOps]; 4219 N->OperandsNeedDelete = true; 4220 } 4221 } 4222 4223 // Assign the new operands. 4224 N->NumOperands = NumOps; 4225 for (unsigned i = 0, e = NumOps; i != e; ++i) { 4226 N->OperandList[i] = Ops[i]; 4227 N->OperandList[i].setUser(N); 4228 SDNode *ToUse = N->OperandList[i].getVal(); 4229 ToUse->addUser(i, N); 4230 } 4231 4232 // Delete any nodes that are still dead after adding the uses for the 4233 // new operands. 4234 SmallVector<SDNode *, 16> DeadNodes; 4235 for (SmallPtrSet<SDNode *, 16>::iterator I = DeadNodeSet.begin(), 4236 E = DeadNodeSet.end(); I != E; ++I) 4237 if ((*I)->use_empty()) 4238 DeadNodes.push_back(*I); 4239 RemoveDeadNodes(DeadNodes); 4240 4241 if (IP) 4242 CSEMap.InsertNode(N, IP); // Memoize the new node. 4243 return N; 4244} 4245 4246 4247/// getTargetNode - These are used for target selectors to create a new node 4248/// with specified return type(s), target opcode, and operands. 4249/// 4250/// Note that getTargetNode returns the resultant node. If there is already a 4251/// node of the specified opcode and operands, it returns that node instead of 4252/// the current one. 4253SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT) { 4254 return getNode(~Opcode, VT).getNode(); 4255} 4256SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT, SDValue Op1) { 4257 return getNode(~Opcode, VT, Op1).getNode(); 4258} 4259SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT, 4260 SDValue Op1, SDValue Op2) { 4261 return getNode(~Opcode, VT, Op1, Op2).getNode(); 4262} 4263SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT, 4264 SDValue Op1, SDValue Op2, 4265 SDValue Op3) { 4266 return getNode(~Opcode, VT, Op1, Op2, Op3).getNode(); 4267} 4268SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT, 4269 const SDValue *Ops, unsigned NumOps) { 4270 return getNode(~Opcode, VT, Ops, NumOps).getNode(); 4271} 4272SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2) { 4273 const MVT *VTs = getNodeValueTypes(VT1, VT2); 4274 SDValue Op; 4275 return getNode(~Opcode, VTs, 2, &Op, 0).getNode(); 4276} 4277SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, 4278 MVT VT2, SDValue Op1) { 4279 const MVT *VTs = getNodeValueTypes(VT1, VT2); 4280 return getNode(~Opcode, VTs, 2, &Op1, 1).getNode(); 4281} 4282SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, 4283 MVT VT2, SDValue Op1, 4284 SDValue Op2) { 4285 const MVT *VTs = getNodeValueTypes(VT1, VT2); 4286 SDValue Ops[] = { Op1, Op2 }; 4287 return getNode(~Opcode, VTs, 2, Ops, 2).getNode(); 4288} 4289SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, 4290 MVT VT2, SDValue Op1, 4291 SDValue Op2, SDValue Op3) { 4292 const MVT *VTs = getNodeValueTypes(VT1, VT2); 4293 SDValue Ops[] = { Op1, Op2, Op3 }; 4294 return getNode(~Opcode, VTs, 2, Ops, 3).getNode(); 4295} 4296SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, 4297 const SDValue *Ops, unsigned NumOps) { 4298 const MVT *VTs = getNodeValueTypes(VT1, VT2); 4299 return getNode(~Opcode, VTs, 2, Ops, NumOps).getNode(); 4300} 4301SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3, 4302 SDValue Op1, SDValue Op2) { 4303 const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3); 4304 SDValue Ops[] = { Op1, Op2 }; 4305 return getNode(~Opcode, VTs, 3, Ops, 2).getNode(); 4306} 4307SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3, 4308 SDValue Op1, SDValue Op2, 4309 SDValue Op3) { 4310 const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3); 4311 SDValue Ops[] = { Op1, Op2, Op3 }; 4312 return getNode(~Opcode, VTs, 3, Ops, 3).getNode(); 4313} 4314SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3, 4315 const SDValue *Ops, unsigned NumOps) { 4316 const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3); 4317 return getNode(~Opcode, VTs, 3, Ops, NumOps).getNode(); 4318} 4319SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, 4320 MVT VT2, MVT VT3, MVT VT4, 4321 const SDValue *Ops, unsigned NumOps) { 4322 std::vector<MVT> VTList; 4323 VTList.push_back(VT1); 4324 VTList.push_back(VT2); 4325 VTList.push_back(VT3); 4326 VTList.push_back(VT4); 4327 const MVT *VTs = getNodeValueTypes(VTList); 4328 return getNode(~Opcode, VTs, 4, Ops, NumOps).getNode(); 4329} 4330SDNode *SelectionDAG::getTargetNode(unsigned Opcode, 4331 const std::vector<MVT> &ResultTys, 4332 const SDValue *Ops, unsigned NumOps) { 4333 const MVT *VTs = getNodeValueTypes(ResultTys); 4334 return getNode(~Opcode, VTs, ResultTys.size(), 4335 Ops, NumOps).getNode(); 4336} 4337 4338/// getNodeIfExists - Get the specified node if it's already available, or 4339/// else return NULL. 4340SDNode *SelectionDAG::getNodeIfExists(unsigned Opcode, SDVTList VTList, 4341 const SDValue *Ops, unsigned NumOps) { 4342 if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) { 4343 FoldingSetNodeID ID; 4344 AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps); 4345 void *IP = 0; 4346 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 4347 return E; 4348 } 4349 return NULL; 4350} 4351 4352 4353/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. 4354/// This can cause recursive merging of nodes in the DAG. 4355/// 4356/// This version assumes From has a single result value. 4357/// 4358void SelectionDAG::ReplaceAllUsesWith(SDValue FromN, SDValue To, 4359 DAGUpdateListener *UpdateListener) { 4360 SDNode *From = FromN.getNode(); 4361 assert(From->getNumValues() == 1 && FromN.getResNo() == 0 && 4362 "Cannot replace with this method!"); 4363 assert(From != To.getNode() && "Cannot replace uses of with self"); 4364 4365 while (!From->use_empty()) { 4366 SDNode::use_iterator UI = From->use_begin(); 4367 SDNode *U = *UI; 4368 4369 // This node is about to morph, remove its old self from the CSE maps. 4370 RemoveNodeFromCSEMaps(U); 4371 int operandNum = 0; 4372 for (SDNode::op_iterator I = U->op_begin(), E = U->op_end(); 4373 I != E; ++I, ++operandNum) 4374 if (I->getVal() == From) { 4375 From->removeUser(operandNum, U); 4376 *I = To; 4377 I->setUser(U); 4378 To.getNode()->addUser(operandNum, U); 4379 } 4380 4381 // Now that we have modified U, add it back to the CSE maps. If it already 4382 // exists there, recursively merge the results together. 4383 if (SDNode *Existing = AddNonLeafNodeToCSEMaps(U)) { 4384 ReplaceAllUsesWith(U, Existing, UpdateListener); 4385 // U is now dead. Inform the listener if it exists and delete it. 4386 if (UpdateListener) 4387 UpdateListener->NodeDeleted(U, Existing); 4388 DeleteNodeNotInCSEMaps(U); 4389 } else { 4390 // If the node doesn't already exist, we updated it. Inform a listener if 4391 // it exists. 4392 if (UpdateListener) 4393 UpdateListener->NodeUpdated(U); 4394 } 4395 } 4396} 4397 4398/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. 4399/// This can cause recursive merging of nodes in the DAG. 4400/// 4401/// This version assumes From/To have matching types and numbers of result 4402/// values. 4403/// 4404void SelectionDAG::ReplaceAllUsesWith(SDNode *From, SDNode *To, 4405 DAGUpdateListener *UpdateListener) { 4406 assert(From->getVTList().VTs == To->getVTList().VTs && 4407 From->getNumValues() == To->getNumValues() && 4408 "Cannot use this version of ReplaceAllUsesWith!"); 4409 4410 // Handle the trivial case. 4411 if (From == To) 4412 return; 4413 4414 while (!From->use_empty()) { 4415 SDNode::use_iterator UI = From->use_begin(); 4416 SDNode *U = *UI; 4417 4418 // This node is about to morph, remove its old self from the CSE maps. 4419 RemoveNodeFromCSEMaps(U); 4420 int operandNum = 0; 4421 for (SDNode::op_iterator I = U->op_begin(), E = U->op_end(); 4422 I != E; ++I, ++operandNum) 4423 if (I->getVal() == From) { 4424 From->removeUser(operandNum, U); 4425 I->getSDValue().setNode(To); 4426 To->addUser(operandNum, U); 4427 } 4428 4429 // Now that we have modified U, add it back to the CSE maps. If it already 4430 // exists there, recursively merge the results together. 4431 if (SDNode *Existing = AddNonLeafNodeToCSEMaps(U)) { 4432 ReplaceAllUsesWith(U, Existing, UpdateListener); 4433 // U is now dead. Inform the listener if it exists and delete it. 4434 if (UpdateListener) 4435 UpdateListener->NodeDeleted(U, Existing); 4436 DeleteNodeNotInCSEMaps(U); 4437 } else { 4438 // If the node doesn't already exist, we updated it. Inform a listener if 4439 // it exists. 4440 if (UpdateListener) 4441 UpdateListener->NodeUpdated(U); 4442 } 4443 } 4444} 4445 4446/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. 4447/// This can cause recursive merging of nodes in the DAG. 4448/// 4449/// This version can replace From with any result values. To must match the 4450/// number and types of values returned by From. 4451void SelectionDAG::ReplaceAllUsesWith(SDNode *From, 4452 const SDValue *To, 4453 DAGUpdateListener *UpdateListener) { 4454 if (From->getNumValues() == 1) // Handle the simple case efficiently. 4455 return ReplaceAllUsesWith(SDValue(From, 0), To[0], UpdateListener); 4456 4457 while (!From->use_empty()) { 4458 SDNode::use_iterator UI = From->use_begin(); 4459 SDNode *U = *UI; 4460 4461 // This node is about to morph, remove its old self from the CSE maps. 4462 RemoveNodeFromCSEMaps(U); 4463 int operandNum = 0; 4464 for (SDNode::op_iterator I = U->op_begin(), E = U->op_end(); 4465 I != E; ++I, ++operandNum) 4466 if (I->getVal() == From) { 4467 const SDValue &ToOp = To[I->getSDValue().getResNo()]; 4468 From->removeUser(operandNum, U); 4469 *I = ToOp; 4470 I->setUser(U); 4471 ToOp.getNode()->addUser(operandNum, U); 4472 } 4473 4474 // Now that we have modified U, add it back to the CSE maps. If it already 4475 // exists there, recursively merge the results together. 4476 if (SDNode *Existing = AddNonLeafNodeToCSEMaps(U)) { 4477 ReplaceAllUsesWith(U, Existing, UpdateListener); 4478 // U is now dead. Inform the listener if it exists and delete it. 4479 if (UpdateListener) 4480 UpdateListener->NodeDeleted(U, Existing); 4481 DeleteNodeNotInCSEMaps(U); 4482 } else { 4483 // If the node doesn't already exist, we updated it. Inform a listener if 4484 // it exists. 4485 if (UpdateListener) 4486 UpdateListener->NodeUpdated(U); 4487 } 4488 } 4489} 4490 4491/// ReplaceAllUsesOfValueWith - Replace any uses of From with To, leaving 4492/// uses of other values produced by From.getVal() alone. The Deleted vector is 4493/// handled the same way as for ReplaceAllUsesWith. 4494void SelectionDAG::ReplaceAllUsesOfValueWith(SDValue From, SDValue To, 4495 DAGUpdateListener *UpdateListener){ 4496 // Handle the really simple, really trivial case efficiently. 4497 if (From == To) return; 4498 4499 // Handle the simple, trivial, case efficiently. 4500 if (From.getNode()->getNumValues() == 1) { 4501 ReplaceAllUsesWith(From, To, UpdateListener); 4502 return; 4503 } 4504 4505 // Get all of the users of From.getNode(). We want these in a nice, 4506 // deterministically ordered and uniqued set, so we use a SmallSetVector. 4507 SmallSetVector<SDNode*, 16> Users(From.getNode()->use_begin(), From.getNode()->use_end()); 4508 4509 while (!Users.empty()) { 4510 // We know that this user uses some value of From. If it is the right 4511 // value, update it. 4512 SDNode *User = Users.back(); 4513 Users.pop_back(); 4514 4515 // Scan for an operand that matches From. 4516 SDNode::op_iterator Op = User->op_begin(), E = User->op_end(); 4517 for (; Op != E; ++Op) 4518 if (*Op == From) break; 4519 4520 // If there are no matches, the user must use some other result of From. 4521 if (Op == E) continue; 4522 4523 // Okay, we know this user needs to be updated. Remove its old self 4524 // from the CSE maps. 4525 RemoveNodeFromCSEMaps(User); 4526 4527 // Update all operands that match "From" in case there are multiple uses. 4528 for (; Op != E; ++Op) { 4529 if (*Op == From) { 4530 From.getNode()->removeUser(Op-User->op_begin(), User); 4531 *Op = To; 4532 Op->setUser(User); 4533 To.getNode()->addUser(Op-User->op_begin(), User); 4534 } 4535 } 4536 4537 // Now that we have modified User, add it back to the CSE maps. If it 4538 // already exists there, recursively merge the results together. 4539 SDNode *Existing = AddNonLeafNodeToCSEMaps(User); 4540 if (!Existing) { 4541 if (UpdateListener) UpdateListener->NodeUpdated(User); 4542 continue; // Continue on to next user. 4543 } 4544 4545 // If there was already an existing matching node, use ReplaceAllUsesWith 4546 // to replace the dead one with the existing one. This can cause 4547 // recursive merging of other unrelated nodes down the line. 4548 ReplaceAllUsesWith(User, Existing, UpdateListener); 4549 4550 // User is now dead. Notify a listener if present. 4551 if (UpdateListener) UpdateListener->NodeDeleted(User, Existing); 4552 DeleteNodeNotInCSEMaps(User); 4553 } 4554} 4555 4556/// ReplaceAllUsesOfValuesWith - Replace any uses of From with To, leaving 4557/// uses of other values produced by From.getVal() alone. The same value may 4558/// appear in both the From and To list. The Deleted vector is 4559/// handled the same way as for ReplaceAllUsesWith. 4560void SelectionDAG::ReplaceAllUsesOfValuesWith(const SDValue *From, 4561 const SDValue *To, 4562 unsigned Num, 4563 DAGUpdateListener *UpdateListener){ 4564 // Handle the simple, trivial case efficiently. 4565 if (Num == 1) 4566 return ReplaceAllUsesOfValueWith(*From, *To, UpdateListener); 4567 4568 SmallVector<std::pair<SDNode *, unsigned>, 16> Users; 4569 for (unsigned i = 0; i != Num; ++i) 4570 for (SDNode::use_iterator UI = From[i].getNode()->use_begin(), 4571 E = From[i].getNode()->use_end(); UI != E; ++UI) 4572 Users.push_back(std::make_pair(*UI, i)); 4573 4574 while (!Users.empty()) { 4575 // We know that this user uses some value of From. If it is the right 4576 // value, update it. 4577 SDNode *User = Users.back().first; 4578 unsigned i = Users.back().second; 4579 Users.pop_back(); 4580 4581 // Scan for an operand that matches From. 4582 SDNode::op_iterator Op = User->op_begin(), E = User->op_end(); 4583 for (; Op != E; ++Op) 4584 if (*Op == From[i]) break; 4585 4586 // If there are no matches, the user must use some other result of From. 4587 if (Op == E) continue; 4588 4589 // Okay, we know this user needs to be updated. Remove its old self 4590 // from the CSE maps. 4591 RemoveNodeFromCSEMaps(User); 4592 4593 // Update all operands that match "From" in case there are multiple uses. 4594 for (; Op != E; ++Op) { 4595 if (*Op == From[i]) { 4596 From[i].getNode()->removeUser(Op-User->op_begin(), User); 4597 *Op = To[i]; 4598 Op->setUser(User); 4599 To[i].getNode()->addUser(Op-User->op_begin(), User); 4600 } 4601 } 4602 4603 // Now that we have modified User, add it back to the CSE maps. If it 4604 // already exists there, recursively merge the results together. 4605 SDNode *Existing = AddNonLeafNodeToCSEMaps(User); 4606 if (!Existing) { 4607 if (UpdateListener) UpdateListener->NodeUpdated(User); 4608 continue; // Continue on to next user. 4609 } 4610 4611 // If there was already an existing matching node, use ReplaceAllUsesWith 4612 // to replace the dead one with the existing one. This can cause 4613 // recursive merging of other unrelated nodes down the line. 4614 ReplaceAllUsesWith(User, Existing, UpdateListener); 4615 4616 // User is now dead. Notify a listener if present. 4617 if (UpdateListener) UpdateListener->NodeDeleted(User, Existing); 4618 DeleteNodeNotInCSEMaps(User); 4619 } 4620} 4621 4622/// AssignTopologicalOrder - Assign a unique node id for each node in the DAG 4623/// based on their topological order. It returns the maximum id and a vector 4624/// of the SDNodes* in assigned order by reference. 4625unsigned SelectionDAG::AssignTopologicalOrder() { 4626 4627 unsigned DAGSize = 0; 4628 4629 // SortedPos tracks the progress of the algorithm. Nodes before it are 4630 // sorted, nodes after it are unsorted. When the algorithm completes 4631 // it is at the end of the list. 4632 allnodes_iterator SortedPos = allnodes_begin(); 4633 4634 // Visit all the nodes. Add nodes with no operands to the TopOrder result 4635 // array immediately. Annotate nodes that do have operands with their 4636 // operand count. Before we do this, the Node Id fields of the nodes 4637 // may contain arbitrary values. After, the Node Id fields for nodes 4638 // before SortedPos will contain the topological sort index, and the 4639 // Node Id fields for nodes At SortedPos and after will contain the 4640 // count of outstanding operands. 4641 for (allnodes_iterator I = allnodes_begin(),E = allnodes_end(); I != E; ) { 4642 SDNode *N = I++; 4643 unsigned Degree = N->getNumOperands(); 4644 if (Degree == 0) { 4645 // A node with no uses, add it to the result array immediately. 4646 N->setNodeId(DAGSize++); 4647 allnodes_iterator Q = N; 4648 if (Q != SortedPos) 4649 SortedPos = AllNodes.insert(SortedPos, AllNodes.remove(Q)); 4650 ++SortedPos; 4651 } else { 4652 // Temporarily use the Node Id as scratch space for the degree count. 4653 N->setNodeId(Degree); 4654 } 4655 } 4656 4657 // Visit all the nodes. As we iterate, moves nodes into sorted order, 4658 // such that by the time the end is reached all nodes will be sorted. 4659 for (allnodes_iterator I = allnodes_begin(),E = allnodes_end(); I != E; ++I) { 4660 SDNode *N = I; 4661 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 4662 UI != UE; ++UI) { 4663 SDNode *P = *UI; 4664 unsigned Degree = P->getNodeId(); 4665 --Degree; 4666 if (Degree == 0) { 4667 // All of P's operands are sorted, so P may sorted now. 4668 P->setNodeId(DAGSize++); 4669 if (P != SortedPos) 4670 SortedPos = AllNodes.insert(SortedPos, AllNodes.remove(P)); 4671 ++SortedPos; 4672 } else { 4673 // Update P's outstanding operand count. 4674 P->setNodeId(Degree); 4675 } 4676 } 4677 } 4678 4679 assert(SortedPos == AllNodes.end() && 4680 "Topological sort incomplete!"); 4681 assert(AllNodes.front().getOpcode() == ISD::EntryToken && 4682 "First node in topological sort is not the entry token!"); 4683 assert(AllNodes.front().getNodeId() == 0 && 4684 "First node in topological sort has non-zero id!"); 4685 assert(AllNodes.front().getNumOperands() == 0 && 4686 "First node in topological sort has operands!"); 4687 assert(AllNodes.back().getNodeId() == (int)DAGSize-1 && 4688 "Last node in topologic sort has unexpected id!"); 4689 assert(AllNodes.back().use_empty() && 4690 "Last node in topologic sort has users!"); 4691 assert(DAGSize == allnodes_size() && "TopOrder result count mismatch!"); 4692 return DAGSize; 4693} 4694 4695 4696 4697//===----------------------------------------------------------------------===// 4698// SDNode Class 4699//===----------------------------------------------------------------------===// 4700 4701// Out-of-line virtual method to give class a home. 4702void SDNode::ANCHOR() {} 4703void UnarySDNode::ANCHOR() {} 4704void BinarySDNode::ANCHOR() {} 4705void TernarySDNode::ANCHOR() {} 4706void HandleSDNode::ANCHOR() {} 4707void ConstantSDNode::ANCHOR() {} 4708void ConstantFPSDNode::ANCHOR() {} 4709void GlobalAddressSDNode::ANCHOR() {} 4710void FrameIndexSDNode::ANCHOR() {} 4711void JumpTableSDNode::ANCHOR() {} 4712void ConstantPoolSDNode::ANCHOR() {} 4713void BasicBlockSDNode::ANCHOR() {} 4714void SrcValueSDNode::ANCHOR() {} 4715void MemOperandSDNode::ANCHOR() {} 4716void RegisterSDNode::ANCHOR() {} 4717void DbgStopPointSDNode::ANCHOR() {} 4718void LabelSDNode::ANCHOR() {} 4719void ExternalSymbolSDNode::ANCHOR() {} 4720void CondCodeSDNode::ANCHOR() {} 4721void ARG_FLAGSSDNode::ANCHOR() {} 4722void VTSDNode::ANCHOR() {} 4723void MemSDNode::ANCHOR() {} 4724void LoadSDNode::ANCHOR() {} 4725void StoreSDNode::ANCHOR() {} 4726void AtomicSDNode::ANCHOR() {} 4727void MemIntrinsicSDNode::ANCHOR() {} 4728void CallSDNode::ANCHOR() {} 4729 4730HandleSDNode::~HandleSDNode() { 4731 DropOperands(); 4732} 4733 4734GlobalAddressSDNode::GlobalAddressSDNode(bool isTarget, const GlobalValue *GA, 4735 MVT VT, int64_t o) 4736 : SDNode(isa<GlobalVariable>(GA) && 4737 cast<GlobalVariable>(GA)->isThreadLocal() ? 4738 // Thread Local 4739 (isTarget ? ISD::TargetGlobalTLSAddress : ISD::GlobalTLSAddress) : 4740 // Non Thread Local 4741 (isTarget ? ISD::TargetGlobalAddress : ISD::GlobalAddress), 4742 getSDVTList(VT)), Offset(o) { 4743 TheGlobal = const_cast<GlobalValue*>(GA); 4744} 4745 4746MemSDNode::MemSDNode(unsigned Opc, SDVTList VTs, MVT memvt, 4747 const Value *srcValue, int SVO, 4748 unsigned alignment, bool vol) 4749 : SDNode(Opc, VTs), MemoryVT(memvt), SrcValue(srcValue), SVOffset(SVO), 4750 Flags(encodeMemSDNodeFlags(vol, alignment)) { 4751 4752 assert(isPowerOf2_32(alignment) && "Alignment is not a power of 2!"); 4753 assert(getAlignment() == alignment && "Alignment representation error!"); 4754 assert(isVolatile() == vol && "Volatile representation error!"); 4755} 4756 4757MemSDNode::MemSDNode(unsigned Opc, SDVTList VTs, const SDValue *Ops, 4758 unsigned NumOps, MVT memvt, const Value *srcValue, 4759 int SVO, unsigned alignment, bool vol) 4760 : SDNode(Opc, VTs, Ops, NumOps), 4761 MemoryVT(memvt), SrcValue(srcValue), SVOffset(SVO), 4762 Flags(vol | ((Log2_32(alignment) + 1) << 1)) { 4763 assert(isPowerOf2_32(alignment) && "Alignment is not a power of 2!"); 4764 assert(getAlignment() == alignment && "Alignment representation error!"); 4765 assert(isVolatile() == vol && "Volatile representation error!"); 4766} 4767 4768/// getMemOperand - Return a MachineMemOperand object describing the memory 4769/// reference performed by this memory reference. 4770MachineMemOperand MemSDNode::getMemOperand() const { 4771 int Flags; 4772 if (isa<LoadSDNode>(this)) 4773 Flags = MachineMemOperand::MOLoad; 4774 else if (isa<StoreSDNode>(this)) 4775 Flags = MachineMemOperand::MOStore; 4776 else if (isa<AtomicSDNode>(this)) { 4777 Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore; 4778 } 4779 else { 4780 const MemIntrinsicSDNode* MemIntrinNode = dyn_cast<MemIntrinsicSDNode>(this); 4781 assert(MemIntrinNode && "Unknown MemSDNode opcode!"); 4782 if (MemIntrinNode->readMem()) Flags |= MachineMemOperand::MOLoad; 4783 if (MemIntrinNode->writeMem()) Flags |= MachineMemOperand::MOStore; 4784 } 4785 4786 int Size = (getMemoryVT().getSizeInBits() + 7) >> 3; 4787 if (isVolatile()) Flags |= MachineMemOperand::MOVolatile; 4788 4789 // Check if the memory reference references a frame index 4790 const FrameIndexSDNode *FI = 4791 dyn_cast<const FrameIndexSDNode>(getBasePtr().getNode()); 4792 if (!getSrcValue() && FI) 4793 return MachineMemOperand(PseudoSourceValue::getFixedStack(FI->getIndex()), 4794 Flags, 0, Size, getAlignment()); 4795 else 4796 return MachineMemOperand(getSrcValue(), Flags, getSrcValueOffset(), 4797 Size, getAlignment()); 4798} 4799 4800/// Profile - Gather unique data for the node. 4801/// 4802void SDNode::Profile(FoldingSetNodeID &ID) const { 4803 AddNodeIDNode(ID, this); 4804} 4805 4806/// getValueTypeList - Return a pointer to the specified value type. 4807/// 4808const MVT *SDNode::getValueTypeList(MVT VT) { 4809 if (VT.isExtended()) { 4810 static std::set<MVT, MVT::compareRawBits> EVTs; 4811 return &(*EVTs.insert(VT).first); 4812 } else { 4813 static MVT VTs[MVT::LAST_VALUETYPE]; 4814 VTs[VT.getSimpleVT()] = VT; 4815 return &VTs[VT.getSimpleVT()]; 4816 } 4817} 4818 4819/// hasNUsesOfValue - Return true if there are exactly NUSES uses of the 4820/// indicated value. This method ignores uses of other values defined by this 4821/// operation. 4822bool SDNode::hasNUsesOfValue(unsigned NUses, unsigned Value) const { 4823 assert(Value < getNumValues() && "Bad value!"); 4824 4825 // TODO: Only iterate over uses of a given value of the node 4826 for (SDNode::use_iterator UI = use_begin(), E = use_end(); UI != E; ++UI) { 4827 if (UI.getUse().getSDValue().getResNo() == Value) { 4828 if (NUses == 0) 4829 return false; 4830 --NUses; 4831 } 4832 } 4833 4834 // Found exactly the right number of uses? 4835 return NUses == 0; 4836} 4837 4838 4839/// hasAnyUseOfValue - Return true if there are any use of the indicated 4840/// value. This method ignores uses of other values defined by this operation. 4841bool SDNode::hasAnyUseOfValue(unsigned Value) const { 4842 assert(Value < getNumValues() && "Bad value!"); 4843 4844 for (SDNode::use_iterator UI = use_begin(), E = use_end(); UI != E; ++UI) 4845 if (UI.getUse().getSDValue().getResNo() == Value) 4846 return true; 4847 4848 return false; 4849} 4850 4851 4852/// isOnlyUserOf - Return true if this node is the only use of N. 4853/// 4854bool SDNode::isOnlyUserOf(SDNode *N) const { 4855 bool Seen = false; 4856 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 4857 SDNode *User = *I; 4858 if (User == this) 4859 Seen = true; 4860 else 4861 return false; 4862 } 4863 4864 return Seen; 4865} 4866 4867/// isOperand - Return true if this node is an operand of N. 4868/// 4869bool SDValue::isOperandOf(SDNode *N) const { 4870 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 4871 if (*this == N->getOperand(i)) 4872 return true; 4873 return false; 4874} 4875 4876bool SDNode::isOperandOf(SDNode *N) const { 4877 for (unsigned i = 0, e = N->NumOperands; i != e; ++i) 4878 if (this == N->OperandList[i].getVal()) 4879 return true; 4880 return false; 4881} 4882 4883/// reachesChainWithoutSideEffects - Return true if this operand (which must 4884/// be a chain) reaches the specified operand without crossing any 4885/// side-effecting instructions. In practice, this looks through token 4886/// factors and non-volatile loads. In order to remain efficient, this only 4887/// looks a couple of nodes in, it does not do an exhaustive search. 4888bool SDValue::reachesChainWithoutSideEffects(SDValue Dest, 4889 unsigned Depth) const { 4890 if (*this == Dest) return true; 4891 4892 // Don't search too deeply, we just want to be able to see through 4893 // TokenFactor's etc. 4894 if (Depth == 0) return false; 4895 4896 // If this is a token factor, all inputs to the TF happen in parallel. If any 4897 // of the operands of the TF reach dest, then we can do the xform. 4898 if (getOpcode() == ISD::TokenFactor) { 4899 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) 4900 if (getOperand(i).reachesChainWithoutSideEffects(Dest, Depth-1)) 4901 return true; 4902 return false; 4903 } 4904 4905 // Loads don't have side effects, look through them. 4906 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(*this)) { 4907 if (!Ld->isVolatile()) 4908 return Ld->getChain().reachesChainWithoutSideEffects(Dest, Depth-1); 4909 } 4910 return false; 4911} 4912 4913 4914static void findPredecessor(SDNode *N, const SDNode *P, bool &found, 4915 SmallPtrSet<SDNode *, 32> &Visited) { 4916 if (found || !Visited.insert(N)) 4917 return; 4918 4919 for (unsigned i = 0, e = N->getNumOperands(); !found && i != e; ++i) { 4920 SDNode *Op = N->getOperand(i).getNode(); 4921 if (Op == P) { 4922 found = true; 4923 return; 4924 } 4925 findPredecessor(Op, P, found, Visited); 4926 } 4927} 4928 4929/// isPredecessorOf - Return true if this node is a predecessor of N. This node 4930/// is either an operand of N or it can be reached by recursively traversing 4931/// up the operands. 4932/// NOTE: this is an expensive method. Use it carefully. 4933bool SDNode::isPredecessorOf(SDNode *N) const { 4934 SmallPtrSet<SDNode *, 32> Visited; 4935 bool found = false; 4936 findPredecessor(N, this, found, Visited); 4937 return found; 4938} 4939 4940uint64_t SDNode::getConstantOperandVal(unsigned Num) const { 4941 assert(Num < NumOperands && "Invalid child # of SDNode!"); 4942 return cast<ConstantSDNode>(OperandList[Num])->getZExtValue(); 4943} 4944 4945std::string SDNode::getOperationName(const SelectionDAG *G) const { 4946 switch (getOpcode()) { 4947 default: 4948 if (getOpcode() < ISD::BUILTIN_OP_END) 4949 return "<<Unknown DAG Node>>"; 4950 if (isMachineOpcode()) { 4951 if (G) 4952 if (const TargetInstrInfo *TII = G->getTarget().getInstrInfo()) 4953 if (getMachineOpcode() < TII->getNumOpcodes()) 4954 return TII->get(getMachineOpcode()).getName(); 4955 return "<<Unknown Machine Node>>"; 4956 } 4957 if (G) { 4958 TargetLowering &TLI = G->getTargetLoweringInfo(); 4959 const char *Name = TLI.getTargetNodeName(getOpcode()); 4960 if (Name) return Name; 4961 return "<<Unknown Target Node>>"; 4962 } 4963 return "<<Unknown Node>>"; 4964 4965#ifndef NDEBUG 4966 case ISD::DELETED_NODE: 4967 return "<<Deleted Node!>>"; 4968#endif 4969 case ISD::PREFETCH: return "Prefetch"; 4970 case ISD::MEMBARRIER: return "MemBarrier"; 4971 case ISD::ATOMIC_CMP_SWAP_8: return "AtomicCmpSwap8"; 4972 case ISD::ATOMIC_SWAP_8: return "AtomicSwap8"; 4973 case ISD::ATOMIC_LOAD_ADD_8: return "AtomicLoadAdd8"; 4974 case ISD::ATOMIC_LOAD_SUB_8: return "AtomicLoadSub8"; 4975 case ISD::ATOMIC_LOAD_AND_8: return "AtomicLoadAnd8"; 4976 case ISD::ATOMIC_LOAD_OR_8: return "AtomicLoadOr8"; 4977 case ISD::ATOMIC_LOAD_XOR_8: return "AtomicLoadXor8"; 4978 case ISD::ATOMIC_LOAD_NAND_8: return "AtomicLoadNand8"; 4979 case ISD::ATOMIC_LOAD_MIN_8: return "AtomicLoadMin8"; 4980 case ISD::ATOMIC_LOAD_MAX_8: return "AtomicLoadMax8"; 4981 case ISD::ATOMIC_LOAD_UMIN_8: return "AtomicLoadUMin8"; 4982 case ISD::ATOMIC_LOAD_UMAX_8: return "AtomicLoadUMax8"; 4983 case ISD::ATOMIC_CMP_SWAP_16: return "AtomicCmpSwap16"; 4984 case ISD::ATOMIC_SWAP_16: return "AtomicSwap16"; 4985 case ISD::ATOMIC_LOAD_ADD_16: return "AtomicLoadAdd16"; 4986 case ISD::ATOMIC_LOAD_SUB_16: return "AtomicLoadSub16"; 4987 case ISD::ATOMIC_LOAD_AND_16: return "AtomicLoadAnd16"; 4988 case ISD::ATOMIC_LOAD_OR_16: return "AtomicLoadOr16"; 4989 case ISD::ATOMIC_LOAD_XOR_16: return "AtomicLoadXor16"; 4990 case ISD::ATOMIC_LOAD_NAND_16: return "AtomicLoadNand16"; 4991 case ISD::ATOMIC_LOAD_MIN_16: return "AtomicLoadMin16"; 4992 case ISD::ATOMIC_LOAD_MAX_16: return "AtomicLoadMax16"; 4993 case ISD::ATOMIC_LOAD_UMIN_16: return "AtomicLoadUMin16"; 4994 case ISD::ATOMIC_LOAD_UMAX_16: return "AtomicLoadUMax16"; 4995 case ISD::ATOMIC_CMP_SWAP_32: return "AtomicCmpSwap32"; 4996 case ISD::ATOMIC_SWAP_32: return "AtomicSwap32"; 4997 case ISD::ATOMIC_LOAD_ADD_32: return "AtomicLoadAdd32"; 4998 case ISD::ATOMIC_LOAD_SUB_32: return "AtomicLoadSub32"; 4999 case ISD::ATOMIC_LOAD_AND_32: return "AtomicLoadAnd32"; 5000 case ISD::ATOMIC_LOAD_OR_32: return "AtomicLoadOr32"; 5001 case ISD::ATOMIC_LOAD_XOR_32: return "AtomicLoadXor32"; 5002 case ISD::ATOMIC_LOAD_NAND_32: return "AtomicLoadNand32"; 5003 case ISD::ATOMIC_LOAD_MIN_32: return "AtomicLoadMin32"; 5004 case ISD::ATOMIC_LOAD_MAX_32: return "AtomicLoadMax32"; 5005 case ISD::ATOMIC_LOAD_UMIN_32: return "AtomicLoadUMin32"; 5006 case ISD::ATOMIC_LOAD_UMAX_32: return "AtomicLoadUMax32"; 5007 case ISD::ATOMIC_CMP_SWAP_64: return "AtomicCmpSwap64"; 5008 case ISD::ATOMIC_SWAP_64: return "AtomicSwap64"; 5009 case ISD::ATOMIC_LOAD_ADD_64: return "AtomicLoadAdd64"; 5010 case ISD::ATOMIC_LOAD_SUB_64: return "AtomicLoadSub64"; 5011 case ISD::ATOMIC_LOAD_AND_64: return "AtomicLoadAnd64"; 5012 case ISD::ATOMIC_LOAD_OR_64: return "AtomicLoadOr64"; 5013 case ISD::ATOMIC_LOAD_XOR_64: return "AtomicLoadXor64"; 5014 case ISD::ATOMIC_LOAD_NAND_64: return "AtomicLoadNand64"; 5015 case ISD::ATOMIC_LOAD_MIN_64: return "AtomicLoadMin64"; 5016 case ISD::ATOMIC_LOAD_MAX_64: return "AtomicLoadMax64"; 5017 case ISD::ATOMIC_LOAD_UMIN_64: return "AtomicLoadUMin64"; 5018 case ISD::ATOMIC_LOAD_UMAX_64: return "AtomicLoadUMax64"; 5019 case ISD::PCMARKER: return "PCMarker"; 5020 case ISD::READCYCLECOUNTER: return "ReadCycleCounter"; 5021 case ISD::SRCVALUE: return "SrcValue"; 5022 case ISD::MEMOPERAND: return "MemOperand"; 5023 case ISD::EntryToken: return "EntryToken"; 5024 case ISD::TokenFactor: return "TokenFactor"; 5025 case ISD::AssertSext: return "AssertSext"; 5026 case ISD::AssertZext: return "AssertZext"; 5027 5028 case ISD::BasicBlock: return "BasicBlock"; 5029 case ISD::ARG_FLAGS: return "ArgFlags"; 5030 case ISD::VALUETYPE: return "ValueType"; 5031 case ISD::Register: return "Register"; 5032 5033 case ISD::Constant: return "Constant"; 5034 case ISD::ConstantFP: return "ConstantFP"; 5035 case ISD::GlobalAddress: return "GlobalAddress"; 5036 case ISD::GlobalTLSAddress: return "GlobalTLSAddress"; 5037 case ISD::FrameIndex: return "FrameIndex"; 5038 case ISD::JumpTable: return "JumpTable"; 5039 case ISD::GLOBAL_OFFSET_TABLE: return "GLOBAL_OFFSET_TABLE"; 5040 case ISD::RETURNADDR: return "RETURNADDR"; 5041 case ISD::FRAMEADDR: return "FRAMEADDR"; 5042 case ISD::FRAME_TO_ARGS_OFFSET: return "FRAME_TO_ARGS_OFFSET"; 5043 case ISD::EXCEPTIONADDR: return "EXCEPTIONADDR"; 5044 case ISD::EHSELECTION: return "EHSELECTION"; 5045 case ISD::EH_RETURN: return "EH_RETURN"; 5046 case ISD::ConstantPool: return "ConstantPool"; 5047 case ISD::ExternalSymbol: return "ExternalSymbol"; 5048 case ISD::INTRINSIC_WO_CHAIN: { 5049 unsigned IID = cast<ConstantSDNode>(getOperand(0))->getZExtValue(); 5050 return Intrinsic::getName((Intrinsic::ID)IID); 5051 } 5052 case ISD::INTRINSIC_VOID: 5053 case ISD::INTRINSIC_W_CHAIN: { 5054 unsigned IID = cast<ConstantSDNode>(getOperand(1))->getZExtValue(); 5055 return Intrinsic::getName((Intrinsic::ID)IID); 5056 } 5057 5058 case ISD::BUILD_VECTOR: return "BUILD_VECTOR"; 5059 case ISD::TargetConstant: return "TargetConstant"; 5060 case ISD::TargetConstantFP:return "TargetConstantFP"; 5061 case ISD::TargetGlobalAddress: return "TargetGlobalAddress"; 5062 case ISD::TargetGlobalTLSAddress: return "TargetGlobalTLSAddress"; 5063 case ISD::TargetFrameIndex: return "TargetFrameIndex"; 5064 case ISD::TargetJumpTable: return "TargetJumpTable"; 5065 case ISD::TargetConstantPool: return "TargetConstantPool"; 5066 case ISD::TargetExternalSymbol: return "TargetExternalSymbol"; 5067 5068 case ISD::CopyToReg: return "CopyToReg"; 5069 case ISD::CopyFromReg: return "CopyFromReg"; 5070 case ISD::UNDEF: return "undef"; 5071 case ISD::MERGE_VALUES: return "merge_values"; 5072 case ISD::INLINEASM: return "inlineasm"; 5073 case ISD::DBG_LABEL: return "dbg_label"; 5074 case ISD::EH_LABEL: return "eh_label"; 5075 case ISD::DECLARE: return "declare"; 5076 case ISD::HANDLENODE: return "handlenode"; 5077 case ISD::FORMAL_ARGUMENTS: return "formal_arguments"; 5078 case ISD::CALL: return "call"; 5079 5080 // Unary operators 5081 case ISD::FABS: return "fabs"; 5082 case ISD::FNEG: return "fneg"; 5083 case ISD::FSQRT: return "fsqrt"; 5084 case ISD::FSIN: return "fsin"; 5085 case ISD::FCOS: return "fcos"; 5086 case ISD::FPOWI: return "fpowi"; 5087 case ISD::FPOW: return "fpow"; 5088 case ISD::FTRUNC: return "ftrunc"; 5089 case ISD::FFLOOR: return "ffloor"; 5090 case ISD::FCEIL: return "fceil"; 5091 case ISD::FRINT: return "frint"; 5092 case ISD::FNEARBYINT: return "fnearbyint"; 5093 5094 // Binary operators 5095 case ISD::ADD: return "add"; 5096 case ISD::SUB: return "sub"; 5097 case ISD::MUL: return "mul"; 5098 case ISD::MULHU: return "mulhu"; 5099 case ISD::MULHS: return "mulhs"; 5100 case ISD::SDIV: return "sdiv"; 5101 case ISD::UDIV: return "udiv"; 5102 case ISD::SREM: return "srem"; 5103 case ISD::UREM: return "urem"; 5104 case ISD::SMUL_LOHI: return "smul_lohi"; 5105 case ISD::UMUL_LOHI: return "umul_lohi"; 5106 case ISD::SDIVREM: return "sdivrem"; 5107 case ISD::UDIVREM: return "udivrem"; 5108 case ISD::AND: return "and"; 5109 case ISD::OR: return "or"; 5110 case ISD::XOR: return "xor"; 5111 case ISD::SHL: return "shl"; 5112 case ISD::SRA: return "sra"; 5113 case ISD::SRL: return "srl"; 5114 case ISD::ROTL: return "rotl"; 5115 case ISD::ROTR: return "rotr"; 5116 case ISD::FADD: return "fadd"; 5117 case ISD::FSUB: return "fsub"; 5118 case ISD::FMUL: return "fmul"; 5119 case ISD::FDIV: return "fdiv"; 5120 case ISD::FREM: return "frem"; 5121 case ISD::FCOPYSIGN: return "fcopysign"; 5122 case ISD::FGETSIGN: return "fgetsign"; 5123 5124 case ISD::SETCC: return "setcc"; 5125 case ISD::VSETCC: return "vsetcc"; 5126 case ISD::SELECT: return "select"; 5127 case ISD::SELECT_CC: return "select_cc"; 5128 case ISD::INSERT_VECTOR_ELT: return "insert_vector_elt"; 5129 case ISD::EXTRACT_VECTOR_ELT: return "extract_vector_elt"; 5130 case ISD::CONCAT_VECTORS: return "concat_vectors"; 5131 case ISD::EXTRACT_SUBVECTOR: return "extract_subvector"; 5132 case ISD::SCALAR_TO_VECTOR: return "scalar_to_vector"; 5133 case ISD::VECTOR_SHUFFLE: return "vector_shuffle"; 5134 case ISD::CARRY_FALSE: return "carry_false"; 5135 case ISD::ADDC: return "addc"; 5136 case ISD::ADDE: return "adde"; 5137 case ISD::SUBC: return "subc"; 5138 case ISD::SUBE: return "sube"; 5139 case ISD::SHL_PARTS: return "shl_parts"; 5140 case ISD::SRA_PARTS: return "sra_parts"; 5141 case ISD::SRL_PARTS: return "srl_parts"; 5142 5143 case ISD::EXTRACT_SUBREG: return "extract_subreg"; 5144 case ISD::INSERT_SUBREG: return "insert_subreg"; 5145 5146 // Conversion operators. 5147 case ISD::SIGN_EXTEND: return "sign_extend"; 5148 case ISD::ZERO_EXTEND: return "zero_extend"; 5149 case ISD::ANY_EXTEND: return "any_extend"; 5150 case ISD::SIGN_EXTEND_INREG: return "sign_extend_inreg"; 5151 case ISD::TRUNCATE: return "truncate"; 5152 case ISD::FP_ROUND: return "fp_round"; 5153 case ISD::FLT_ROUNDS_: return "flt_rounds"; 5154 case ISD::FP_ROUND_INREG: return "fp_round_inreg"; 5155 case ISD::FP_EXTEND: return "fp_extend"; 5156 5157 case ISD::SINT_TO_FP: return "sint_to_fp"; 5158 case ISD::UINT_TO_FP: return "uint_to_fp"; 5159 case ISD::FP_TO_SINT: return "fp_to_sint"; 5160 case ISD::FP_TO_UINT: return "fp_to_uint"; 5161 case ISD::BIT_CONVERT: return "bit_convert"; 5162 5163 // Control flow instructions 5164 case ISD::BR: return "br"; 5165 case ISD::BRIND: return "brind"; 5166 case ISD::BR_JT: return "br_jt"; 5167 case ISD::BRCOND: return "brcond"; 5168 case ISD::BR_CC: return "br_cc"; 5169 case ISD::RET: return "ret"; 5170 case ISD::CALLSEQ_START: return "callseq_start"; 5171 case ISD::CALLSEQ_END: return "callseq_end"; 5172 5173 // Other operators 5174 case ISD::LOAD: return "load"; 5175 case ISD::STORE: return "store"; 5176 case ISD::VAARG: return "vaarg"; 5177 case ISD::VACOPY: return "vacopy"; 5178 case ISD::VAEND: return "vaend"; 5179 case ISD::VASTART: return "vastart"; 5180 case ISD::DYNAMIC_STACKALLOC: return "dynamic_stackalloc"; 5181 case ISD::EXTRACT_ELEMENT: return "extract_element"; 5182 case ISD::BUILD_PAIR: return "build_pair"; 5183 case ISD::STACKSAVE: return "stacksave"; 5184 case ISD::STACKRESTORE: return "stackrestore"; 5185 case ISD::TRAP: return "trap"; 5186 5187 // Bit manipulation 5188 case ISD::BSWAP: return "bswap"; 5189 case ISD::CTPOP: return "ctpop"; 5190 case ISD::CTTZ: return "cttz"; 5191 case ISD::CTLZ: return "ctlz"; 5192 5193 // Debug info 5194 case ISD::DBG_STOPPOINT: return "dbg_stoppoint"; 5195 case ISD::DEBUG_LOC: return "debug_loc"; 5196 5197 // Trampolines 5198 case ISD::TRAMPOLINE: return "trampoline"; 5199 5200 case ISD::CONDCODE: 5201 switch (cast<CondCodeSDNode>(this)->get()) { 5202 default: assert(0 && "Unknown setcc condition!"); 5203 case ISD::SETOEQ: return "setoeq"; 5204 case ISD::SETOGT: return "setogt"; 5205 case ISD::SETOGE: return "setoge"; 5206 case ISD::SETOLT: return "setolt"; 5207 case ISD::SETOLE: return "setole"; 5208 case ISD::SETONE: return "setone"; 5209 5210 case ISD::SETO: return "seto"; 5211 case ISD::SETUO: return "setuo"; 5212 case ISD::SETUEQ: return "setue"; 5213 case ISD::SETUGT: return "setugt"; 5214 case ISD::SETUGE: return "setuge"; 5215 case ISD::SETULT: return "setult"; 5216 case ISD::SETULE: return "setule"; 5217 case ISD::SETUNE: return "setune"; 5218 5219 case ISD::SETEQ: return "seteq"; 5220 case ISD::SETGT: return "setgt"; 5221 case ISD::SETGE: return "setge"; 5222 case ISD::SETLT: return "setlt"; 5223 case ISD::SETLE: return "setle"; 5224 case ISD::SETNE: return "setne"; 5225 } 5226 } 5227} 5228 5229const char *SDNode::getIndexedModeName(ISD::MemIndexedMode AM) { 5230 switch (AM) { 5231 default: 5232 return ""; 5233 case ISD::PRE_INC: 5234 return "<pre-inc>"; 5235 case ISD::PRE_DEC: 5236 return "<pre-dec>"; 5237 case ISD::POST_INC: 5238 return "<post-inc>"; 5239 case ISD::POST_DEC: 5240 return "<post-dec>"; 5241 } 5242} 5243 5244std::string ISD::ArgFlagsTy::getArgFlagsString() { 5245 std::string S = "< "; 5246 5247 if (isZExt()) 5248 S += "zext "; 5249 if (isSExt()) 5250 S += "sext "; 5251 if (isInReg()) 5252 S += "inreg "; 5253 if (isSRet()) 5254 S += "sret "; 5255 if (isByVal()) 5256 S += "byval "; 5257 if (isNest()) 5258 S += "nest "; 5259 if (getByValAlign()) 5260 S += "byval-align:" + utostr(getByValAlign()) + " "; 5261 if (getOrigAlign()) 5262 S += "orig-align:" + utostr(getOrigAlign()) + " "; 5263 if (getByValSize()) 5264 S += "byval-size:" + utostr(getByValSize()) + " "; 5265 return S + ">"; 5266} 5267 5268void SDNode::dump() const { dump(0); } 5269void SDNode::dump(const SelectionDAG *G) const { 5270 print(errs(), G); 5271 errs().flush(); 5272} 5273 5274void SDNode::print(raw_ostream &OS, const SelectionDAG *G) const { 5275 OS << (void*)this << ": "; 5276 5277 for (unsigned i = 0, e = getNumValues(); i != e; ++i) { 5278 if (i) OS << ","; 5279 if (getValueType(i) == MVT::Other) 5280 OS << "ch"; 5281 else 5282 OS << getValueType(i).getMVTString(); 5283 } 5284 OS << " = " << getOperationName(G); 5285 5286 OS << " "; 5287 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 5288 if (i) OS << ", "; 5289 OS << (void*)getOperand(i).getNode(); 5290 if (unsigned RN = getOperand(i).getResNo()) 5291 OS << ":" << RN; 5292 } 5293 5294 if (!isTargetOpcode() && getOpcode() == ISD::VECTOR_SHUFFLE) { 5295 SDNode *Mask = getOperand(2).getNode(); 5296 OS << "<"; 5297 for (unsigned i = 0, e = Mask->getNumOperands(); i != e; ++i) { 5298 if (i) OS << ","; 5299 if (Mask->getOperand(i).getOpcode() == ISD::UNDEF) 5300 OS << "u"; 5301 else 5302 OS << cast<ConstantSDNode>(Mask->getOperand(i))->getZExtValue(); 5303 } 5304 OS << ">"; 5305 } 5306 5307 if (const ConstantSDNode *CSDN = dyn_cast<ConstantSDNode>(this)) { 5308 OS << '<' << CSDN->getAPIntValue() << '>'; 5309 } else if (const ConstantFPSDNode *CSDN = dyn_cast<ConstantFPSDNode>(this)) { 5310 if (&CSDN->getValueAPF().getSemantics()==&APFloat::IEEEsingle) 5311 OS << '<' << CSDN->getValueAPF().convertToFloat() << '>'; 5312 else if (&CSDN->getValueAPF().getSemantics()==&APFloat::IEEEdouble) 5313 OS << '<' << CSDN->getValueAPF().convertToDouble() << '>'; 5314 else { 5315 OS << "<APFloat("; 5316 CSDN->getValueAPF().bitcastToAPInt().dump(); 5317 OS << ")>"; 5318 } 5319 } else if (const GlobalAddressSDNode *GADN = 5320 dyn_cast<GlobalAddressSDNode>(this)) { 5321 int offset = GADN->getOffset(); 5322 OS << '<'; 5323 WriteAsOperand(OS, GADN->getGlobal()); 5324 OS << '>'; 5325 if (offset > 0) 5326 OS << " + " << offset; 5327 else 5328 OS << " " << offset; 5329 } else if (const FrameIndexSDNode *FIDN = dyn_cast<FrameIndexSDNode>(this)) { 5330 OS << "<" << FIDN->getIndex() << ">"; 5331 } else if (const JumpTableSDNode *JTDN = dyn_cast<JumpTableSDNode>(this)) { 5332 OS << "<" << JTDN->getIndex() << ">"; 5333 } else if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(this)){ 5334 int offset = CP->getOffset(); 5335 if (CP->isMachineConstantPoolEntry()) 5336 OS << "<" << *CP->getMachineCPVal() << ">"; 5337 else 5338 OS << "<" << *CP->getConstVal() << ">"; 5339 if (offset > 0) 5340 OS << " + " << offset; 5341 else 5342 OS << " " << offset; 5343 } else if (const BasicBlockSDNode *BBDN = dyn_cast<BasicBlockSDNode>(this)) { 5344 OS << "<"; 5345 const Value *LBB = (const Value*)BBDN->getBasicBlock()->getBasicBlock(); 5346 if (LBB) 5347 OS << LBB->getName() << " "; 5348 OS << (const void*)BBDN->getBasicBlock() << ">"; 5349 } else if (const RegisterSDNode *R = dyn_cast<RegisterSDNode>(this)) { 5350 if (G && R->getReg() && 5351 TargetRegisterInfo::isPhysicalRegister(R->getReg())) { 5352 OS << " " << G->getTarget().getRegisterInfo()->getName(R->getReg()); 5353 } else { 5354 OS << " #" << R->getReg(); 5355 } 5356 } else if (const ExternalSymbolSDNode *ES = 5357 dyn_cast<ExternalSymbolSDNode>(this)) { 5358 OS << "'" << ES->getSymbol() << "'"; 5359 } else if (const SrcValueSDNode *M = dyn_cast<SrcValueSDNode>(this)) { 5360 if (M->getValue()) 5361 OS << "<" << M->getValue() << ">"; 5362 else 5363 OS << "<null>"; 5364 } else if (const MemOperandSDNode *M = dyn_cast<MemOperandSDNode>(this)) { 5365 if (M->MO.getValue()) 5366 OS << "<" << M->MO.getValue() << ":" << M->MO.getOffset() << ">"; 5367 else 5368 OS << "<null:" << M->MO.getOffset() << ">"; 5369 } else if (const ARG_FLAGSSDNode *N = dyn_cast<ARG_FLAGSSDNode>(this)) { 5370 OS << N->getArgFlags().getArgFlagsString(); 5371 } else if (const VTSDNode *N = dyn_cast<VTSDNode>(this)) { 5372 OS << ":" << N->getVT().getMVTString(); 5373 } 5374 else if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(this)) { 5375 const Value *SrcValue = LD->getSrcValue(); 5376 int SrcOffset = LD->getSrcValueOffset(); 5377 OS << " <"; 5378 if (SrcValue) 5379 OS << SrcValue; 5380 else 5381 OS << "null"; 5382 OS << ":" << SrcOffset << ">"; 5383 5384 bool doExt = true; 5385 switch (LD->getExtensionType()) { 5386 default: doExt = false; break; 5387 case ISD::EXTLOAD: OS << " <anyext "; break; 5388 case ISD::SEXTLOAD: OS << " <sext "; break; 5389 case ISD::ZEXTLOAD: OS << " <zext "; break; 5390 } 5391 if (doExt) 5392 OS << LD->getMemoryVT().getMVTString() << ">"; 5393 5394 const char *AM = getIndexedModeName(LD->getAddressingMode()); 5395 if (*AM) 5396 OS << " " << AM; 5397 if (LD->isVolatile()) 5398 OS << " <volatile>"; 5399 OS << " alignment=" << LD->getAlignment(); 5400 } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(this)) { 5401 const Value *SrcValue = ST->getSrcValue(); 5402 int SrcOffset = ST->getSrcValueOffset(); 5403 OS << " <"; 5404 if (SrcValue) 5405 OS << SrcValue; 5406 else 5407 OS << "null"; 5408 OS << ":" << SrcOffset << ">"; 5409 5410 if (ST->isTruncatingStore()) 5411 OS << " <trunc " << ST->getMemoryVT().getMVTString() << ">"; 5412 5413 const char *AM = getIndexedModeName(ST->getAddressingMode()); 5414 if (*AM) 5415 OS << " " << AM; 5416 if (ST->isVolatile()) 5417 OS << " <volatile>"; 5418 OS << " alignment=" << ST->getAlignment(); 5419 } else if (const AtomicSDNode* AT = dyn_cast<AtomicSDNode>(this)) { 5420 const Value *SrcValue = AT->getSrcValue(); 5421 int SrcOffset = AT->getSrcValueOffset(); 5422 OS << " <"; 5423 if (SrcValue) 5424 OS << SrcValue; 5425 else 5426 OS << "null"; 5427 OS << ":" << SrcOffset << ">"; 5428 if (AT->isVolatile()) 5429 OS << " <volatile>"; 5430 OS << " alignment=" << AT->getAlignment(); 5431 } 5432} 5433 5434static void DumpNodes(const SDNode *N, unsigned indent, const SelectionDAG *G) { 5435 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 5436 if (N->getOperand(i).getNode()->hasOneUse()) 5437 DumpNodes(N->getOperand(i).getNode(), indent+2, G); 5438 else 5439 cerr << "\n" << std::string(indent+2, ' ') 5440 << (void*)N->getOperand(i).getNode() << ": <multiple use>"; 5441 5442 5443 cerr << "\n" << std::string(indent, ' '); 5444 N->dump(G); 5445} 5446 5447void SelectionDAG::dump() const { 5448 cerr << "SelectionDAG has " << AllNodes.size() << " nodes:"; 5449 5450 for (allnodes_const_iterator I = allnodes_begin(), E = allnodes_end(); 5451 I != E; ++I) { 5452 const SDNode *N = I; 5453 if (!N->hasOneUse() && N != getRoot().getNode()) 5454 DumpNodes(N, 2, this); 5455 } 5456 5457 if (getRoot().getNode()) DumpNodes(getRoot().getNode(), 2, this); 5458 5459 cerr << "\n\n"; 5460} 5461 5462const Type *ConstantPoolSDNode::getType() const { 5463 if (isMachineConstantPoolEntry()) 5464 return Val.MachineCPVal->getType(); 5465 return Val.ConstVal->getType(); 5466} 5467