SelectionDAG.cpp revision 7042f15bded917ba68e5e66be873ad4d06f9ca2d
1//===-- SelectionDAG.cpp - Implement the SelectionDAG data structures -----===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAG class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/Constants.h" 16#include "llvm/GlobalValue.h" 17#include "llvm/Assembly/Writer.h" 18#include "llvm/CodeGen/MachineBasicBlock.h" 19#include "llvm/Support/MathExtras.h" 20#include "llvm/Target/MRegisterInfo.h" 21#include "llvm/Target/TargetLowering.h" 22#include "llvm/Target/TargetInstrInfo.h" 23#include "llvm/Target/TargetMachine.h" 24#include <iostream> 25#include <set> 26#include <cmath> 27#include <algorithm> 28using namespace llvm; 29 30static bool isCommutativeBinOp(unsigned Opcode) { 31 switch (Opcode) { 32 case ISD::ADD: 33 case ISD::MUL: 34 case ISD::AND: 35 case ISD::OR: 36 case ISD::XOR: return true; 37 default: return false; // FIXME: Need commutative info for user ops! 38 } 39} 40 41static bool isAssociativeBinOp(unsigned Opcode) { 42 switch (Opcode) { 43 case ISD::ADD: 44 case ISD::MUL: 45 case ISD::AND: 46 case ISD::OR: 47 case ISD::XOR: return true; 48 default: return false; // FIXME: Need associative info for user ops! 49 } 50} 51 52// isInvertibleForFree - Return true if there is no cost to emitting the logical 53// inverse of this node. 54static bool isInvertibleForFree(SDOperand N) { 55 if (isa<ConstantSDNode>(N.Val)) return true; 56 if (N.Val->getOpcode() == ISD::SETCC && N.Val->hasOneUse()) 57 return true; 58 return false; 59} 60 61//===----------------------------------------------------------------------===// 62// ConstantFPSDNode Class 63//===----------------------------------------------------------------------===// 64 65/// isExactlyValue - We don't rely on operator== working on double values, as 66/// it returns true for things that are clearly not equal, like -0.0 and 0.0. 67/// As such, this method can be used to do an exact bit-for-bit comparison of 68/// two floating point values. 69bool ConstantFPSDNode::isExactlyValue(double V) const { 70 return DoubleToBits(V) == DoubleToBits(Value); 71} 72 73//===----------------------------------------------------------------------===// 74// ISD Class 75//===----------------------------------------------------------------------===// 76 77/// getSetCCSwappedOperands - Return the operation corresponding to (Y op X) 78/// when given the operation for (X op Y). 79ISD::CondCode ISD::getSetCCSwappedOperands(ISD::CondCode Operation) { 80 // To perform this operation, we just need to swap the L and G bits of the 81 // operation. 82 unsigned OldL = (Operation >> 2) & 1; 83 unsigned OldG = (Operation >> 1) & 1; 84 return ISD::CondCode((Operation & ~6) | // Keep the N, U, E bits 85 (OldL << 1) | // New G bit 86 (OldG << 2)); // New L bit. 87} 88 89/// getSetCCInverse - Return the operation corresponding to !(X op Y), where 90/// 'op' is a valid SetCC operation. 91ISD::CondCode ISD::getSetCCInverse(ISD::CondCode Op, bool isInteger) { 92 unsigned Operation = Op; 93 if (isInteger) 94 Operation ^= 7; // Flip L, G, E bits, but not U. 95 else 96 Operation ^= 15; // Flip all of the condition bits. 97 if (Operation > ISD::SETTRUE2) 98 Operation &= ~8; // Don't let N and U bits get set. 99 return ISD::CondCode(Operation); 100} 101 102 103/// isSignedOp - For an integer comparison, return 1 if the comparison is a 104/// signed operation and 2 if the result is an unsigned comparison. Return zero 105/// if the operation does not depend on the sign of the input (setne and seteq). 106static int isSignedOp(ISD::CondCode Opcode) { 107 switch (Opcode) { 108 default: assert(0 && "Illegal integer setcc operation!"); 109 case ISD::SETEQ: 110 case ISD::SETNE: return 0; 111 case ISD::SETLT: 112 case ISD::SETLE: 113 case ISD::SETGT: 114 case ISD::SETGE: return 1; 115 case ISD::SETULT: 116 case ISD::SETULE: 117 case ISD::SETUGT: 118 case ISD::SETUGE: return 2; 119 } 120} 121 122/// getSetCCOrOperation - Return the result of a logical OR between different 123/// comparisons of identical values: ((X op1 Y) | (X op2 Y)). This function 124/// returns SETCC_INVALID if it is not possible to represent the resultant 125/// comparison. 126ISD::CondCode ISD::getSetCCOrOperation(ISD::CondCode Op1, ISD::CondCode Op2, 127 bool isInteger) { 128 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 129 // Cannot fold a signed integer setcc with an unsigned integer setcc. 130 return ISD::SETCC_INVALID; 131 132 unsigned Op = Op1 | Op2; // Combine all of the condition bits. 133 134 // If the N and U bits get set then the resultant comparison DOES suddenly 135 // care about orderedness, and is true when ordered. 136 if (Op > ISD::SETTRUE2) 137 Op &= ~16; // Clear the N bit. 138 return ISD::CondCode(Op); 139} 140 141/// getSetCCAndOperation - Return the result of a logical AND between different 142/// comparisons of identical values: ((X op1 Y) & (X op2 Y)). This 143/// function returns zero if it is not possible to represent the resultant 144/// comparison. 145ISD::CondCode ISD::getSetCCAndOperation(ISD::CondCode Op1, ISD::CondCode Op2, 146 bool isInteger) { 147 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 148 // Cannot fold a signed setcc with an unsigned setcc. 149 return ISD::SETCC_INVALID; 150 151 // Combine all of the condition bits. 152 return ISD::CondCode(Op1 & Op2); 153} 154 155const TargetMachine &SelectionDAG::getTarget() const { 156 return TLI.getTargetMachine(); 157} 158 159//===----------------------------------------------------------------------===// 160// SelectionDAG Class 161//===----------------------------------------------------------------------===// 162 163/// RemoveDeadNodes - This method deletes all unreachable nodes in the 164/// SelectionDAG, including nodes (like loads) that have uses of their token 165/// chain but no other uses and no side effect. If a node is passed in as an 166/// argument, it is used as the seed for node deletion. 167void SelectionDAG::RemoveDeadNodes(SDNode *N) { 168 std::set<SDNode*> AllNodeSet(AllNodes.begin(), AllNodes.end()); 169 170 // Create a dummy node (which is not added to allnodes), that adds a reference 171 // to the root node, preventing it from being deleted. 172 SDNode *DummyNode = new SDNode(ISD::EntryToken, getRoot()); 173 174 // If we have a hint to start from, use it. 175 if (N) DeleteNodeIfDead(N, &AllNodeSet); 176 177 Restart: 178 unsigned NumNodes = AllNodeSet.size(); 179 for (std::set<SDNode*>::iterator I = AllNodeSet.begin(), E = AllNodeSet.end(); 180 I != E; ++I) { 181 // Try to delete this node. 182 DeleteNodeIfDead(*I, &AllNodeSet); 183 184 // If we actually deleted any nodes, do not use invalid iterators in 185 // AllNodeSet. 186 if (AllNodeSet.size() != NumNodes) 187 goto Restart; 188 } 189 190 // Restore AllNodes. 191 if (AllNodes.size() != NumNodes) 192 AllNodes.assign(AllNodeSet.begin(), AllNodeSet.end()); 193 194 // If the root changed (e.g. it was a dead load, update the root). 195 setRoot(DummyNode->getOperand(0)); 196 197 // Now that we are done with the dummy node, delete it. 198 DummyNode->getOperand(0).Val->removeUser(DummyNode); 199 delete DummyNode; 200} 201 202 203void SelectionDAG::DeleteNodeIfDead(SDNode *N, void *NodeSet) { 204 if (!N->use_empty()) 205 return; 206 207 // Okay, we really are going to delete this node. First take this out of the 208 // appropriate CSE map. 209 RemoveNodeFromCSEMaps(N); 210 211 // Next, brutally remove the operand list. This is safe to do, as there are 212 // no cycles in the graph. 213 while (!N->Operands.empty()) { 214 SDNode *O = N->Operands.back().Val; 215 N->Operands.pop_back(); 216 O->removeUser(N); 217 218 // Now that we removed this operand, see if there are no uses of it left. 219 DeleteNodeIfDead(O, NodeSet); 220 } 221 222 // Remove the node from the nodes set and delete it. 223 std::set<SDNode*> &AllNodeSet = *(std::set<SDNode*>*)NodeSet; 224 AllNodeSet.erase(N); 225 226 // Now that the node is gone, check to see if any of the operands of this node 227 // are dead now. 228 delete N; 229} 230 231/// RemoveNodeFromCSEMaps - Take the specified node out of the CSE map that 232/// correspond to it. This is useful when we're about to delete or repurpose 233/// the node. We don't want future request for structurally identical nodes 234/// to return N anymore. 235void SelectionDAG::RemoveNodeFromCSEMaps(SDNode *N) { 236 switch (N->getOpcode()) { 237 case ISD::Constant: 238 Constants.erase(std::make_pair(cast<ConstantSDNode>(N)->getValue(), 239 N->getValueType(0))); 240 break; 241 case ISD::TargetConstant: 242 TargetConstants.erase(std::make_pair(cast<ConstantSDNode>(N)->getValue(), 243 N->getValueType(0))); 244 break; 245 case ISD::ConstantFP: { 246 uint64_t V = DoubleToBits(cast<ConstantFPSDNode>(N)->getValue()); 247 ConstantFPs.erase(std::make_pair(V, N->getValueType(0))); 248 break; 249 } 250 case ISD::CONDCODE: 251 assert(CondCodeNodes[cast<CondCodeSDNode>(N)->get()] && 252 "Cond code doesn't exist!"); 253 CondCodeNodes[cast<CondCodeSDNode>(N)->get()] = 0; 254 break; 255 case ISD::GlobalAddress: 256 GlobalValues.erase(cast<GlobalAddressSDNode>(N)->getGlobal()); 257 break; 258 case ISD::TargetGlobalAddress: 259 TargetGlobalValues.erase(cast<GlobalAddressSDNode>(N)->getGlobal()); 260 break; 261 case ISD::FrameIndex: 262 FrameIndices.erase(cast<FrameIndexSDNode>(N)->getIndex()); 263 break; 264 case ISD::ConstantPool: 265 ConstantPoolIndices.erase(cast<ConstantPoolSDNode>(N)->getIndex()); 266 break; 267 case ISD::BasicBlock: 268 BBNodes.erase(cast<BasicBlockSDNode>(N)->getBasicBlock()); 269 break; 270 case ISD::ExternalSymbol: 271 ExternalSymbols.erase(cast<ExternalSymbolSDNode>(N)->getSymbol()); 272 break; 273 case ISD::VALUETYPE: 274 ValueTypeNodes[cast<VTSDNode>(N)->getVT()] = 0; 275 break; 276 case ISD::Register: 277 RegNodes[cast<RegisterSDNode>(N)->getReg()] = 0; 278 break; 279 case ISD::SRCVALUE: { 280 SrcValueSDNode *SVN = cast<SrcValueSDNode>(N); 281 ValueNodes.erase(std::make_pair(SVN->getValue(), SVN->getOffset())); 282 break; 283 } 284 case ISD::LOAD: 285 Loads.erase(std::make_pair(N->getOperand(1), 286 std::make_pair(N->getOperand(0), 287 N->getValueType(0)))); 288 break; 289 default: 290 if (N->getNumOperands() == 1) 291 UnaryOps.erase(std::make_pair(N->getOpcode(), 292 std::make_pair(N->getOperand(0), 293 N->getValueType(0)))); 294 else if (N->getNumOperands() == 2) 295 BinaryOps.erase(std::make_pair(N->getOpcode(), 296 std::make_pair(N->getOperand(0), 297 N->getOperand(1)))); 298 else if (N->getNumValues() == 1) { 299 std::vector<SDOperand> Ops(N->op_begin(), N->op_end()); 300 OneResultNodes.erase(std::make_pair(N->getOpcode(), 301 std::make_pair(N->getValueType(0), 302 Ops))); 303 } else { 304 // Remove the node from the ArbitraryNodes map. 305 std::vector<MVT::ValueType> RV(N->value_begin(), N->value_end()); 306 std::vector<SDOperand> Ops(N->op_begin(), N->op_end()); 307 ArbitraryNodes.erase(std::make_pair(N->getOpcode(), 308 std::make_pair(RV, Ops))); 309 } 310 break; 311 } 312} 313 314/// AddNonLeafNodeToCSEMaps - Add the specified node back to the CSE maps. It 315/// has been taken out and modified in some way. If the specified node already 316/// exists in the CSE maps, do not modify the maps, but return the existing node 317/// instead. If it doesn't exist, add it and return null. 318/// 319SDNode *SelectionDAG::AddNonLeafNodeToCSEMaps(SDNode *N) { 320 assert(N->getNumOperands() && "This is a leaf node!"); 321 if (N->getOpcode() == ISD::LOAD) { 322 SDNode *&L = Loads[std::make_pair(N->getOperand(1), 323 std::make_pair(N->getOperand(0), 324 N->getValueType(0)))]; 325 if (L) return L; 326 L = N; 327 } else if (N->getNumOperands() == 1) { 328 SDNode *&U = UnaryOps[std::make_pair(N->getOpcode(), 329 std::make_pair(N->getOperand(0), 330 N->getValueType(0)))]; 331 if (U) return U; 332 U = N; 333 } else if (N->getNumOperands() == 2) { 334 SDNode *&B = BinaryOps[std::make_pair(N->getOpcode(), 335 std::make_pair(N->getOperand(0), 336 N->getOperand(1)))]; 337 if (B) return B; 338 B = N; 339 } else if (N->getNumValues() == 1) { 340 std::vector<SDOperand> Ops(N->op_begin(), N->op_end()); 341 SDNode *&ORN = OneResultNodes[std::make_pair(N->getOpcode(), 342 std::make_pair(N->getValueType(0), Ops))]; 343 if (ORN) return ORN; 344 ORN = N; 345 } else { 346 // Remove the node from the ArbitraryNodes map. 347 std::vector<MVT::ValueType> RV(N->value_begin(), N->value_end()); 348 std::vector<SDOperand> Ops(N->op_begin(), N->op_end()); 349 SDNode *&AN = ArbitraryNodes[std::make_pair(N->getOpcode(), 350 std::make_pair(RV, Ops))]; 351 if (AN) return AN; 352 AN = N; 353 } 354 return 0; 355 356} 357 358 359 360SelectionDAG::~SelectionDAG() { 361 for (unsigned i = 0, e = AllNodes.size(); i != e; ++i) 362 delete AllNodes[i]; 363} 364 365SDOperand SelectionDAG::getZeroExtendInReg(SDOperand Op, MVT::ValueType VT) { 366 if (Op.getValueType() == VT) return Op; 367 int64_t Imm = ~0ULL >> (64-MVT::getSizeInBits(VT)); 368 return getNode(ISD::AND, Op.getValueType(), Op, 369 getConstant(Imm, Op.getValueType())); 370} 371 372SDOperand SelectionDAG::getConstant(uint64_t Val, MVT::ValueType VT) { 373 assert(MVT::isInteger(VT) && "Cannot create FP integer constant!"); 374 // Mask out any bits that are not valid for this constant. 375 if (VT != MVT::i64) 376 Val &= ((uint64_t)1 << MVT::getSizeInBits(VT)) - 1; 377 378 SDNode *&N = Constants[std::make_pair(Val, VT)]; 379 if (N) return SDOperand(N, 0); 380 N = new ConstantSDNode(false, Val, VT); 381 AllNodes.push_back(N); 382 return SDOperand(N, 0); 383} 384 385SDOperand SelectionDAG::getTargetConstant(uint64_t Val, MVT::ValueType VT) { 386 assert(MVT::isInteger(VT) && "Cannot create FP integer constant!"); 387 // Mask out any bits that are not valid for this constant. 388 if (VT != MVT::i64) 389 Val &= ((uint64_t)1 << MVT::getSizeInBits(VT)) - 1; 390 391 SDNode *&N = TargetConstants[std::make_pair(Val, VT)]; 392 if (N) return SDOperand(N, 0); 393 N = new ConstantSDNode(true, Val, VT); 394 AllNodes.push_back(N); 395 return SDOperand(N, 0); 396} 397 398SDOperand SelectionDAG::getConstantFP(double Val, MVT::ValueType VT) { 399 assert(MVT::isFloatingPoint(VT) && "Cannot create integer FP constant!"); 400 if (VT == MVT::f32) 401 Val = (float)Val; // Mask out extra precision. 402 403 // Do the map lookup using the actual bit pattern for the floating point 404 // value, so that we don't have problems with 0.0 comparing equal to -0.0, and 405 // we don't have issues with SNANs. 406 SDNode *&N = ConstantFPs[std::make_pair(DoubleToBits(Val), VT)]; 407 if (N) return SDOperand(N, 0); 408 N = new ConstantFPSDNode(Val, VT); 409 AllNodes.push_back(N); 410 return SDOperand(N, 0); 411} 412 413 414 415SDOperand SelectionDAG::getGlobalAddress(const GlobalValue *GV, 416 MVT::ValueType VT) { 417 SDNode *&N = GlobalValues[GV]; 418 if (N) return SDOperand(N, 0); 419 N = new GlobalAddressSDNode(false, GV, VT); 420 AllNodes.push_back(N); 421 return SDOperand(N, 0); 422} 423 424SDOperand SelectionDAG::getTargetGlobalAddress(const GlobalValue *GV, 425 MVT::ValueType VT) { 426 SDNode *&N = TargetGlobalValues[GV]; 427 if (N) return SDOperand(N, 0); 428 N = new GlobalAddressSDNode(true, GV, VT); 429 AllNodes.push_back(N); 430 return SDOperand(N, 0); 431} 432 433SDOperand SelectionDAG::getFrameIndex(int FI, MVT::ValueType VT) { 434 SDNode *&N = FrameIndices[FI]; 435 if (N) return SDOperand(N, 0); 436 N = new FrameIndexSDNode(FI, VT); 437 AllNodes.push_back(N); 438 return SDOperand(N, 0); 439} 440 441SDOperand SelectionDAG::getConstantPool(unsigned CPIdx, MVT::ValueType VT) { 442 SDNode *N = ConstantPoolIndices[CPIdx]; 443 if (N) return SDOperand(N, 0); 444 N = new ConstantPoolSDNode(CPIdx, VT); 445 AllNodes.push_back(N); 446 return SDOperand(N, 0); 447} 448 449SDOperand SelectionDAG::getBasicBlock(MachineBasicBlock *MBB) { 450 SDNode *&N = BBNodes[MBB]; 451 if (N) return SDOperand(N, 0); 452 N = new BasicBlockSDNode(MBB); 453 AllNodes.push_back(N); 454 return SDOperand(N, 0); 455} 456 457SDOperand SelectionDAG::getValueType(MVT::ValueType VT) { 458 if ((unsigned)VT >= ValueTypeNodes.size()) 459 ValueTypeNodes.resize(VT+1); 460 if (ValueTypeNodes[VT] == 0) { 461 ValueTypeNodes[VT] = new VTSDNode(VT); 462 AllNodes.push_back(ValueTypeNodes[VT]); 463 } 464 465 return SDOperand(ValueTypeNodes[VT], 0); 466} 467 468SDOperand SelectionDAG::getExternalSymbol(const char *Sym, MVT::ValueType VT) { 469 SDNode *&N = ExternalSymbols[Sym]; 470 if (N) return SDOperand(N, 0); 471 N = new ExternalSymbolSDNode(Sym, VT); 472 AllNodes.push_back(N); 473 return SDOperand(N, 0); 474} 475 476SDOperand SelectionDAG::getCondCode(ISD::CondCode Cond) { 477 if ((unsigned)Cond >= CondCodeNodes.size()) 478 CondCodeNodes.resize(Cond+1); 479 480 if (CondCodeNodes[Cond] == 0) { 481 CondCodeNodes[Cond] = new CondCodeSDNode(Cond); 482 AllNodes.push_back(CondCodeNodes[Cond]); 483 } 484 return SDOperand(CondCodeNodes[Cond], 0); 485} 486 487SDOperand SelectionDAG::getRegister(unsigned Reg, MVT::ValueType VT) { 488 if (Reg >= RegNodes.size()) 489 RegNodes.resize(Reg+1); 490 RegisterSDNode *&Result = RegNodes[Reg]; 491 if (Result) { 492 assert(Result->getValueType(0) == VT && 493 "Inconsistent value types for machine registers"); 494 } else { 495 Result = new RegisterSDNode(Reg, VT); 496 AllNodes.push_back(Result); 497 } 498 return SDOperand(Result, 0); 499} 500 501SDOperand SelectionDAG::SimplifySetCC(MVT::ValueType VT, SDOperand N1, 502 SDOperand N2, ISD::CondCode Cond) { 503 // These setcc operations always fold. 504 switch (Cond) { 505 default: break; 506 case ISD::SETFALSE: 507 case ISD::SETFALSE2: return getConstant(0, VT); 508 case ISD::SETTRUE: 509 case ISD::SETTRUE2: return getConstant(1, VT); 510 } 511 512 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val)) { 513 uint64_t C2 = N2C->getValue(); 514 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) { 515 uint64_t C1 = N1C->getValue(); 516 517 // Sign extend the operands if required 518 if (ISD::isSignedIntSetCC(Cond)) { 519 C1 = N1C->getSignExtended(); 520 C2 = N2C->getSignExtended(); 521 } 522 523 switch (Cond) { 524 default: assert(0 && "Unknown integer setcc!"); 525 case ISD::SETEQ: return getConstant(C1 == C2, VT); 526 case ISD::SETNE: return getConstant(C1 != C2, VT); 527 case ISD::SETULT: return getConstant(C1 < C2, VT); 528 case ISD::SETUGT: return getConstant(C1 > C2, VT); 529 case ISD::SETULE: return getConstant(C1 <= C2, VT); 530 case ISD::SETUGE: return getConstant(C1 >= C2, VT); 531 case ISD::SETLT: return getConstant((int64_t)C1 < (int64_t)C2, VT); 532 case ISD::SETGT: return getConstant((int64_t)C1 > (int64_t)C2, VT); 533 case ISD::SETLE: return getConstant((int64_t)C1 <= (int64_t)C2, VT); 534 case ISD::SETGE: return getConstant((int64_t)C1 >= (int64_t)C2, VT); 535 } 536 } else { 537 // If the LHS is a ZERO_EXTEND and if this is an ==/!= comparison, perform 538 // the comparison on the input. 539 if (N1.getOpcode() == ISD::ZERO_EXTEND) { 540 unsigned InSize = MVT::getSizeInBits(N1.getOperand(0).getValueType()); 541 542 // If the comparison constant has bits in the upper part, the 543 // zero-extended value could never match. 544 if (C2 & (~0ULL << InSize)) { 545 unsigned VSize = MVT::getSizeInBits(N1.getValueType()); 546 switch (Cond) { 547 case ISD::SETUGT: 548 case ISD::SETUGE: 549 case ISD::SETEQ: return getConstant(0, VT); 550 case ISD::SETULT: 551 case ISD::SETULE: 552 case ISD::SETNE: return getConstant(1, VT); 553 case ISD::SETGT: 554 case ISD::SETGE: 555 // True if the sign bit of C2 is set. 556 return getConstant((C2 & (1ULL << VSize)) != 0, VT); 557 case ISD::SETLT: 558 case ISD::SETLE: 559 // True if the sign bit of C2 isn't set. 560 return getConstant((C2 & (1ULL << VSize)) == 0, VT); 561 default: 562 break; 563 } 564 } 565 566 // Otherwise, we can perform the comparison with the low bits. 567 switch (Cond) { 568 case ISD::SETEQ: 569 case ISD::SETNE: 570 case ISD::SETUGT: 571 case ISD::SETUGE: 572 case ISD::SETULT: 573 case ISD::SETULE: 574 return getSetCC(VT, N1.getOperand(0), 575 getConstant(C2, N1.getOperand(0).getValueType()), 576 Cond); 577 default: 578 break; // todo, be more careful with signed comparisons 579 } 580 } 581 582 uint64_t MinVal, MaxVal; 583 unsigned OperandBitSize = MVT::getSizeInBits(N2C->getValueType(0)); 584 if (ISD::isSignedIntSetCC(Cond)) { 585 MinVal = 1ULL << (OperandBitSize-1); 586 if (OperandBitSize != 1) // Avoid X >> 64, which is undefined. 587 MaxVal = ~0ULL >> (65-OperandBitSize); 588 else 589 MaxVal = 0; 590 } else { 591 MinVal = 0; 592 MaxVal = ~0ULL >> (64-OperandBitSize); 593 } 594 595 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 596 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 597 if (C2 == MinVal) return getConstant(1, VT); // X >= MIN --> true 598 --C2; // X >= C1 --> X > (C1-1) 599 return getSetCC(VT, N1, getConstant(C2, N2.getValueType()), 600 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); 601 } 602 603 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 604 if (C2 == MaxVal) return getConstant(1, VT); // X <= MAX --> true 605 ++C2; // X <= C1 --> X < (C1+1) 606 return getSetCC(VT, N1, getConstant(C2, N2.getValueType()), 607 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); 608 } 609 610 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C2 == MinVal) 611 return getConstant(0, VT); // X < MIN --> false 612 613 // Canonicalize setgt X, Min --> setne X, Min 614 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C2 == MinVal) 615 return getSetCC(VT, N1, N2, ISD::SETNE); 616 617 // If we have setult X, 1, turn it into seteq X, 0 618 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C2 == MinVal+1) 619 return getSetCC(VT, N1, getConstant(MinVal, N1.getValueType()), 620 ISD::SETEQ); 621 // If we have setugt X, Max-1, turn it into seteq X, Max 622 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C2 == MaxVal-1) 623 return getSetCC(VT, N1, getConstant(MaxVal, N1.getValueType()), 624 ISD::SETEQ); 625 626 // If we have "setcc X, C1", check to see if we can shrink the immediate 627 // by changing cc. 628 629 // SETUGT X, SINTMAX -> SETLT X, 0 630 if (Cond == ISD::SETUGT && OperandBitSize != 1 && 631 C2 == (~0ULL >> (65-OperandBitSize))) 632 return getSetCC(VT, N1, getConstant(0, N2.getValueType()), ISD::SETLT); 633 634 // FIXME: Implement the rest of these. 635 636 637 // Fold bit comparisons when we can. 638 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 639 VT == N1.getValueType() && N1.getOpcode() == ISD::AND) 640 if (ConstantSDNode *AndRHS = 641 dyn_cast<ConstantSDNode>(N1.getOperand(1))) { 642 if (Cond == ISD::SETNE && C2 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 643 // Perform the xform if the AND RHS is a single bit. 644 if ((AndRHS->getValue() & (AndRHS->getValue()-1)) == 0) { 645 return getNode(ISD::SRL, VT, N1, 646 getConstant(Log2_64(AndRHS->getValue()), 647 TLI.getShiftAmountTy())); 648 } 649 } else if (Cond == ISD::SETEQ && C2 == AndRHS->getValue()) { 650 // (X & 8) == 8 --> (X & 8) >> 3 651 // Perform the xform if C2 is a single bit. 652 if ((C2 & (C2-1)) == 0) { 653 return getNode(ISD::SRL, VT, N1, 654 getConstant(Log2_64(C2),TLI.getShiftAmountTy())); 655 } 656 } 657 } 658 } 659 } else if (isa<ConstantSDNode>(N1.Val)) { 660 // Ensure that the constant occurs on the RHS. 661 return getSetCC(VT, N2, N1, ISD::getSetCCSwappedOperands(Cond)); 662 } 663 664 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.Val)) 665 if (ConstantFPSDNode *N2C = dyn_cast<ConstantFPSDNode>(N2.Val)) { 666 double C1 = N1C->getValue(), C2 = N2C->getValue(); 667 668 switch (Cond) { 669 default: break; // FIXME: Implement the rest of these! 670 case ISD::SETEQ: return getConstant(C1 == C2, VT); 671 case ISD::SETNE: return getConstant(C1 != C2, VT); 672 case ISD::SETLT: return getConstant(C1 < C2, VT); 673 case ISD::SETGT: return getConstant(C1 > C2, VT); 674 case ISD::SETLE: return getConstant(C1 <= C2, VT); 675 case ISD::SETGE: return getConstant(C1 >= C2, VT); 676 } 677 } else { 678 // Ensure that the constant occurs on the RHS. 679 return getSetCC(VT, N2, N1, ISD::getSetCCSwappedOperands(Cond)); 680 } 681 682 if (N1 == N2) { 683 // We can always fold X == Y for integer setcc's. 684 if (MVT::isInteger(N1.getValueType())) 685 return getConstant(ISD::isTrueWhenEqual(Cond), VT); 686 unsigned UOF = ISD::getUnorderedFlavor(Cond); 687 if (UOF == 2) // FP operators that are undefined on NaNs. 688 return getConstant(ISD::isTrueWhenEqual(Cond), VT); 689 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 690 return getConstant(UOF, VT); 691 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 692 // if it is not already. 693 ISD::CondCode NewCond = UOF == 0 ? ISD::SETUO : ISD::SETO; 694 if (NewCond != Cond) 695 return getSetCC(VT, N1, N2, NewCond); 696 } 697 698 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 699 MVT::isInteger(N1.getValueType())) { 700 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 701 N1.getOpcode() == ISD::XOR) { 702 // Simplify (X+Y) == (X+Z) --> Y == Z 703 if (N1.getOpcode() == N2.getOpcode()) { 704 if (N1.getOperand(0) == N2.getOperand(0)) 705 return getSetCC(VT, N1.getOperand(1), N2.getOperand(1), Cond); 706 if (N1.getOperand(1) == N2.getOperand(1)) 707 return getSetCC(VT, N1.getOperand(0), N2.getOperand(0), Cond); 708 if (isCommutativeBinOp(N1.getOpcode())) { 709 // If X op Y == Y op X, try other combinations. 710 if (N1.getOperand(0) == N2.getOperand(1)) 711 return getSetCC(VT, N1.getOperand(1), N2.getOperand(0), Cond); 712 if (N1.getOperand(1) == N2.getOperand(0)) 713 return getSetCC(VT, N1.getOperand(1), N2.getOperand(1), Cond); 714 } 715 } 716 717 // FIXME: move this stuff to the DAG Combiner when it exists! 718 719 // Simplify (X+Z) == X --> Z == 0 720 if (N1.getOperand(0) == N2) 721 return getSetCC(VT, N1.getOperand(1), 722 getConstant(0, N1.getValueType()), Cond); 723 if (N1.getOperand(1) == N2) { 724 if (isCommutativeBinOp(N1.getOpcode())) 725 return getSetCC(VT, N1.getOperand(0), 726 getConstant(0, N1.getValueType()), Cond); 727 else { 728 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 729 // (Z-X) == X --> Z == X<<1 730 return getSetCC(VT, N1.getOperand(0), 731 getNode(ISD::SHL, N2.getValueType(), 732 N2, getConstant(1, TLI.getShiftAmountTy())), 733 Cond); 734 } 735 } 736 } 737 738 if (N2.getOpcode() == ISD::ADD || N2.getOpcode() == ISD::SUB || 739 N2.getOpcode() == ISD::XOR) { 740 // Simplify X == (X+Z) --> Z == 0 741 if (N2.getOperand(0) == N1) { 742 return getSetCC(VT, N2.getOperand(1), 743 getConstant(0, N2.getValueType()), Cond); 744 } else if (N2.getOperand(1) == N1) { 745 if (isCommutativeBinOp(N2.getOpcode())) { 746 return getSetCC(VT, N2.getOperand(0), 747 getConstant(0, N2.getValueType()), Cond); 748 } else { 749 assert(N2.getOpcode() == ISD::SUB && "Unexpected operation!"); 750 // X == (Z-X) --> X<<1 == Z 751 return getSetCC(VT, getNode(ISD::SHL, N2.getValueType(), N1, 752 getConstant(1, TLI.getShiftAmountTy())), 753 N2.getOperand(0), Cond); 754 } 755 } 756 } 757 } 758 759 // Fold away ALL boolean setcc's. 760 if (N1.getValueType() == MVT::i1) { 761 switch (Cond) { 762 default: assert(0 && "Unknown integer setcc!"); 763 case ISD::SETEQ: // X == Y -> (X^Y)^1 764 N1 = getNode(ISD::XOR, MVT::i1, 765 getNode(ISD::XOR, MVT::i1, N1, N2), 766 getConstant(1, MVT::i1)); 767 break; 768 case ISD::SETNE: // X != Y --> (X^Y) 769 N1 = getNode(ISD::XOR, MVT::i1, N1, N2); 770 break; 771 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y 772 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y 773 N1 = getNode(ISD::AND, MVT::i1, N2, 774 getNode(ISD::XOR, MVT::i1, N1, getConstant(1, MVT::i1))); 775 break; 776 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X 777 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X 778 N1 = getNode(ISD::AND, MVT::i1, N1, 779 getNode(ISD::XOR, MVT::i1, N2, getConstant(1, MVT::i1))); 780 break; 781 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y 782 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y 783 N1 = getNode(ISD::OR, MVT::i1, N2, 784 getNode(ISD::XOR, MVT::i1, N1, getConstant(1, MVT::i1))); 785 break; 786 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X 787 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X 788 N1 = getNode(ISD::OR, MVT::i1, N1, 789 getNode(ISD::XOR, MVT::i1, N2, getConstant(1, MVT::i1))); 790 break; 791 } 792 if (VT != MVT::i1) 793 N1 = getNode(ISD::ZERO_EXTEND, VT, N1); 794 return N1; 795 } 796 797 // Could not fold it. 798 return SDOperand(); 799} 800 801SDOperand SelectionDAG::SimplifySelectCC(SDOperand N1, SDOperand N2, 802 SDOperand N3, SDOperand N4, 803 ISD::CondCode CC) { 804 MVT::ValueType VT = N3.getValueType(); 805 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 806 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val); 807 ConstantSDNode *N4C = dyn_cast<ConstantSDNode>(N4.Val); 808 809 // Check to see if we can simplify the select into an fabs node 810 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N2)) { 811 // Allow either -0.0 or 0.0 812 if (CFP->getValue() == 0.0) { 813 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 814 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 815 N1 == N3 && N4.getOpcode() == ISD::FNEG && 816 N1 == N4.getOperand(0)) 817 return getNode(ISD::FABS, VT, N1); 818 819 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 820 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 821 N1 == N4 && N3.getOpcode() == ISD::FNEG && 822 N3.getOperand(0) == N4) 823 return getNode(ISD::FABS, VT, N4); 824 } 825 } 826 827 // Check to see if we can perform the "gzip trick", transforming 828 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A 829 if (N2C && N2C->isNullValue() && N4C && N4C->isNullValue() && 830 MVT::isInteger(N1.getValueType()) && 831 MVT::isInteger(N3.getValueType()) && CC == ISD::SETLT) { 832 MVT::ValueType XType = N1.getValueType(); 833 MVT::ValueType AType = N3.getValueType(); 834 if (XType >= AType) { 835 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 836 // single-bit constant. FIXME: remove once the dag combiner 837 // exists. 838 if (N3C && ((N3C->getValue() & (N3C->getValue()-1)) == 0)) { 839 unsigned ShCtV = Log2_64(N3C->getValue()); 840 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1; 841 SDOperand ShCt = getConstant(ShCtV, TLI.getShiftAmountTy()); 842 SDOperand Shift = getNode(ISD::SRL, XType, N1, ShCt); 843 if (XType > AType) 844 Shift = getNode(ISD::TRUNCATE, AType, Shift); 845 return getNode(ISD::AND, AType, Shift, N3); 846 } 847 SDOperand Shift = getNode(ISD::SRA, XType, N1, 848 getConstant(MVT::getSizeInBits(XType)-1, 849 TLI.getShiftAmountTy())); 850 if (XType > AType) 851 Shift = getNode(ISD::TRUNCATE, AType, Shift); 852 return getNode(ISD::AND, AType, Shift, N3); 853 } 854 } 855 856 // Check to see if this is the equivalent of seteq X, 0. 857 // select_cc seteq X, 0, 1, 0 -> setcc X, 0, seteq -> srl (ctlz X), size(X)-1 858 if (N2C && N2C->isNullValue() && N4C && N4C->isNullValue() && 859 N3C && (N3C->getValue() == 1)) { 860 MVT::ValueType XType = N1.getValueType(); 861 if (TLI.getOperationAction(ISD::SETCC, TLI.getSetCCResultTy()) == 862 TargetLowering::Legal) { 863 return getSetCC(TLI.getSetCCResultTy(), N1, N2, ISD::SETEQ); 864 } 865 if (TLI.getOperationAction(ISD::CTLZ, XType) == TargetLowering::Legal) { 866 SDOperand Ctlz = getNode(ISD::CTLZ, XType, N1); 867 return getNode(ISD::SRL, XType, Ctlz, 868 getConstant(MVT::getSizeInBits(XType)-1, 869 TLI.getShiftAmountTy())); 870 } 871 } 872 873 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 874 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 875 if (N2C && N2C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 876 N1 == N4 && N3.getOpcode() == ISD::SUB && N1 == N3.getOperand(1)) { 877 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) { 878 MVT::ValueType XType = N1.getValueType(); 879 if (SubC->isNullValue() && MVT::isInteger(XType)) { 880 SDOperand Shift = getNode(ISD::SRA, XType, N1, 881 getConstant(MVT::getSizeInBits(XType)-1, 882 TLI.getShiftAmountTy())); 883 return getNode(ISD::XOR, XType, getNode(ISD::ADD, XType, N1, Shift), 884 Shift); 885 } 886 } 887 } 888 889 // Could not fold it. 890 return SDOperand(); 891} 892 893/// getNode - Gets or creates the specified node. 894/// 895SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT) { 896 SDNode *N = new SDNode(Opcode, VT); 897 AllNodes.push_back(N); 898 return SDOperand(N, 0); 899} 900 901SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, 902 SDOperand Operand) { 903 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Operand.Val)) { 904 uint64_t Val = C->getValue(); 905 switch (Opcode) { 906 default: break; 907 case ISD::SIGN_EXTEND: return getConstant(C->getSignExtended(), VT); 908 case ISD::ZERO_EXTEND: return getConstant(Val, VT); 909 case ISD::TRUNCATE: return getConstant(Val, VT); 910 case ISD::SINT_TO_FP: return getConstantFP(C->getSignExtended(), VT); 911 case ISD::UINT_TO_FP: return getConstantFP(C->getValue(), VT); 912 } 913 } 914 915 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Operand.Val)) 916 switch (Opcode) { 917 case ISD::FNEG: 918 return getConstantFP(-C->getValue(), VT); 919 case ISD::FP_ROUND: 920 case ISD::FP_EXTEND: 921 return getConstantFP(C->getValue(), VT); 922 case ISD::FP_TO_SINT: 923 return getConstant((int64_t)C->getValue(), VT); 924 case ISD::FP_TO_UINT: 925 return getConstant((uint64_t)C->getValue(), VT); 926 } 927 928 unsigned OpOpcode = Operand.Val->getOpcode(); 929 switch (Opcode) { 930 case ISD::TokenFactor: 931 return Operand; // Factor of one node? No factor. 932 case ISD::SIGN_EXTEND: 933 if (Operand.getValueType() == VT) return Operand; // noop extension 934 if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND) 935 return getNode(OpOpcode, VT, Operand.Val->getOperand(0)); 936 break; 937 case ISD::ZERO_EXTEND: 938 if (Operand.getValueType() == VT) return Operand; // noop extension 939 if (OpOpcode == ISD::ZERO_EXTEND) // (zext (zext x)) -> (zext x) 940 return getNode(ISD::ZERO_EXTEND, VT, Operand.Val->getOperand(0)); 941 break; 942 case ISD::TRUNCATE: 943 if (Operand.getValueType() == VT) return Operand; // noop truncate 944 if (OpOpcode == ISD::TRUNCATE) 945 return getNode(ISD::TRUNCATE, VT, Operand.Val->getOperand(0)); 946 else if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND) { 947 // If the source is smaller than the dest, we still need an extend. 948 if (Operand.Val->getOperand(0).getValueType() < VT) 949 return getNode(OpOpcode, VT, Operand.Val->getOperand(0)); 950 else if (Operand.Val->getOperand(0).getValueType() > VT) 951 return getNode(ISD::TRUNCATE, VT, Operand.Val->getOperand(0)); 952 else 953 return Operand.Val->getOperand(0); 954 } 955 break; 956 case ISD::FNEG: 957 if (OpOpcode == ISD::SUB) // -(X-Y) -> (Y-X) 958 return getNode(ISD::SUB, VT, Operand.Val->getOperand(1), 959 Operand.Val->getOperand(0)); 960 if (OpOpcode == ISD::FNEG) // --X -> X 961 return Operand.Val->getOperand(0); 962 break; 963 case ISD::FABS: 964 if (OpOpcode == ISD::FNEG) // abs(-X) -> abs(X) 965 return getNode(ISD::FABS, VT, Operand.Val->getOperand(0)); 966 break; 967 } 968 969 SDNode *&N = UnaryOps[std::make_pair(Opcode, std::make_pair(Operand, VT))]; 970 if (N) return SDOperand(N, 0); 971 N = new SDNode(Opcode, Operand); 972 N->setValueTypes(VT); 973 AllNodes.push_back(N); 974 return SDOperand(N, 0); 975} 976 977/// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero. We use 978/// this predicate to simplify operations downstream. V and Mask are known to 979/// be the same type. 980static bool MaskedValueIsZero(const SDOperand &Op, uint64_t Mask, 981 const TargetLowering &TLI) { 982 unsigned SrcBits; 983 if (Mask == 0) return true; 984 985 // If we know the result of a setcc has the top bits zero, use this info. 986 switch (Op.getOpcode()) { 987 case ISD::Constant: 988 return (cast<ConstantSDNode>(Op)->getValue() & Mask) == 0; 989 990 case ISD::SETCC: 991 return ((Mask & 1) == 0) && 992 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult; 993 994 case ISD::ZEXTLOAD: 995 SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(3))->getVT()); 996 return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits. 997 case ISD::ZERO_EXTEND: 998 SrcBits = MVT::getSizeInBits(Op.getOperand(0).getValueType()); 999 return MaskedValueIsZero(Op.getOperand(0),Mask & ((1ULL << SrcBits)-1),TLI); 1000 1001 case ISD::AND: 1002 // (X & C1) & C2 == 0 iff C1 & C2 == 0. 1003 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(Op.getOperand(1))) 1004 return MaskedValueIsZero(Op.getOperand(0),AndRHS->getValue() & Mask, TLI); 1005 1006 // FALL THROUGH 1007 case ISD::OR: 1008 case ISD::XOR: 1009 return MaskedValueIsZero(Op.getOperand(0), Mask, TLI) && 1010 MaskedValueIsZero(Op.getOperand(1), Mask, TLI); 1011 case ISD::SELECT: 1012 return MaskedValueIsZero(Op.getOperand(1), Mask, TLI) && 1013 MaskedValueIsZero(Op.getOperand(2), Mask, TLI); 1014 1015 case ISD::SRL: 1016 // (ushr X, C1) & C2 == 0 iff X & (C2 << C1) == 0 1017 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1018 uint64_t NewVal = Mask << ShAmt->getValue(); 1019 SrcBits = MVT::getSizeInBits(Op.getValueType()); 1020 if (SrcBits != 64) NewVal &= (1ULL << SrcBits)-1; 1021 return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI); 1022 } 1023 return false; 1024 case ISD::SHL: 1025 // (ushl X, C1) & C2 == 0 iff X & (C2 >> C1) == 0 1026 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1027 uint64_t NewVal = Mask >> ShAmt->getValue(); 1028 return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI); 1029 } 1030 return false; 1031 // TODO we could handle some SRA cases here. 1032 default: break; 1033 } 1034 1035 return false; 1036} 1037 1038 1039 1040SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, 1041 SDOperand N1, SDOperand N2) { 1042#ifndef NDEBUG 1043 switch (Opcode) { 1044 case ISD::TokenFactor: 1045 assert(VT == MVT::Other && N1.getValueType() == MVT::Other && 1046 N2.getValueType() == MVT::Other && "Invalid token factor!"); 1047 break; 1048 case ISD::AND: 1049 case ISD::OR: 1050 case ISD::XOR: 1051 case ISD::UDIV: 1052 case ISD::UREM: 1053 case ISD::MULHU: 1054 case ISD::MULHS: 1055 assert(MVT::isInteger(VT) && "This operator does not apply to FP types!"); 1056 // fall through 1057 case ISD::ADD: 1058 case ISD::SUB: 1059 case ISD::MUL: 1060 case ISD::SDIV: 1061 case ISD::SREM: 1062 assert(N1.getValueType() == N2.getValueType() && 1063 N1.getValueType() == VT && "Binary operator types must match!"); 1064 break; 1065 1066 case ISD::SHL: 1067 case ISD::SRA: 1068 case ISD::SRL: 1069 assert(VT == N1.getValueType() && 1070 "Shift operators return type must be the same as their first arg"); 1071 assert(MVT::isInteger(VT) && MVT::isInteger(N2.getValueType()) && 1072 VT != MVT::i1 && "Shifts only work on integers"); 1073 break; 1074 case ISD::FP_ROUND_INREG: { 1075 MVT::ValueType EVT = cast<VTSDNode>(N2)->getVT(); 1076 assert(VT == N1.getValueType() && "Not an inreg round!"); 1077 assert(MVT::isFloatingPoint(VT) && MVT::isFloatingPoint(EVT) && 1078 "Cannot FP_ROUND_INREG integer types"); 1079 assert(EVT <= VT && "Not rounding down!"); 1080 break; 1081 } 1082 case ISD::SIGN_EXTEND_INREG: { 1083 MVT::ValueType EVT = cast<VTSDNode>(N2)->getVT(); 1084 assert(VT == N1.getValueType() && "Not an inreg extend!"); 1085 assert(MVT::isInteger(VT) && MVT::isInteger(EVT) && 1086 "Cannot *_EXTEND_INREG FP types"); 1087 assert(EVT <= VT && "Not extending!"); 1088 } 1089 1090 default: break; 1091 } 1092#endif 1093 1094 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1095 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 1096 if (N1C) { 1097 if (N2C) { 1098 uint64_t C1 = N1C->getValue(), C2 = N2C->getValue(); 1099 switch (Opcode) { 1100 case ISD::ADD: return getConstant(C1 + C2, VT); 1101 case ISD::SUB: return getConstant(C1 - C2, VT); 1102 case ISD::MUL: return getConstant(C1 * C2, VT); 1103 case ISD::UDIV: 1104 if (C2) return getConstant(C1 / C2, VT); 1105 break; 1106 case ISD::UREM : 1107 if (C2) return getConstant(C1 % C2, VT); 1108 break; 1109 case ISD::SDIV : 1110 if (C2) return getConstant(N1C->getSignExtended() / 1111 N2C->getSignExtended(), VT); 1112 break; 1113 case ISD::SREM : 1114 if (C2) return getConstant(N1C->getSignExtended() % 1115 N2C->getSignExtended(), VT); 1116 break; 1117 case ISD::AND : return getConstant(C1 & C2, VT); 1118 case ISD::OR : return getConstant(C1 | C2, VT); 1119 case ISD::XOR : return getConstant(C1 ^ C2, VT); 1120 case ISD::SHL : return getConstant(C1 << (int)C2, VT); 1121 case ISD::SRL : return getConstant(C1 >> (unsigned)C2, VT); 1122 case ISD::SRA : return getConstant(N1C->getSignExtended() >>(int)C2, VT); 1123 default: break; 1124 } 1125 1126 } else { // Cannonicalize constant to RHS if commutative 1127 if (isCommutativeBinOp(Opcode)) { 1128 std::swap(N1C, N2C); 1129 std::swap(N1, N2); 1130 } 1131 } 1132 1133 switch (Opcode) { 1134 default: break; 1135 case ISD::SHL: // shl 0, X -> 0 1136 if (N1C->isNullValue()) return N1; 1137 break; 1138 case ISD::SRL: // srl 0, X -> 0 1139 if (N1C->isNullValue()) return N1; 1140 break; 1141 case ISD::SRA: // sra -1, X -> -1 1142 if (N1C->isAllOnesValue()) return N1; 1143 break; 1144 case ISD::SIGN_EXTEND_INREG: // SIGN_EXTEND_INREG N1C, EVT 1145 // Extending a constant? Just return the extended constant. 1146 SDOperand Tmp = getNode(ISD::TRUNCATE, cast<VTSDNode>(N2)->getVT(), N1); 1147 return getNode(ISD::SIGN_EXTEND, VT, Tmp); 1148 } 1149 } 1150 1151 if (N2C) { 1152 uint64_t C2 = N2C->getValue(); 1153 1154 switch (Opcode) { 1155 case ISD::ADD: 1156 if (!C2) return N1; // add X, 0 -> X 1157 break; 1158 case ISD::SUB: 1159 if (!C2) return N1; // sub X, 0 -> X 1160 return getNode(ISD::ADD, VT, N1, getConstant(-C2, VT)); 1161 case ISD::MUL: 1162 if (!C2) return N2; // mul X, 0 -> 0 1163 if (N2C->isAllOnesValue()) // mul X, -1 -> 0-X 1164 return getNode(ISD::SUB, VT, getConstant(0, VT), N1); 1165 1166 // FIXME: Move this to the DAG combiner when it exists. 1167 if ((C2 & C2-1) == 0) { 1168 SDOperand ShAmt = getConstant(Log2_64(C2), TLI.getShiftAmountTy()); 1169 return getNode(ISD::SHL, VT, N1, ShAmt); 1170 } 1171 break; 1172 1173 case ISD::MULHU: 1174 case ISD::MULHS: 1175 if (!C2) return N2; // mul X, 0 -> 0 1176 1177 if (C2 == 1) // 0X*01 -> 0X hi(0X) == 0 1178 return getConstant(0, VT); 1179 1180 // Many others could be handled here, including -1, powers of 2, etc. 1181 break; 1182 1183 case ISD::UDIV: 1184 // FIXME: Move this to the DAG combiner when it exists. 1185 if ((C2 & C2-1) == 0 && C2) { 1186 SDOperand ShAmt = getConstant(Log2_64(C2), TLI.getShiftAmountTy()); 1187 return getNode(ISD::SRL, VT, N1, ShAmt); 1188 } 1189 break; 1190 1191 case ISD::SHL: 1192 case ISD::SRL: 1193 case ISD::SRA: 1194 // If the shift amount is bigger than the size of the data, then all the 1195 // bits are shifted out. Simplify to undef. 1196 if (C2 >= MVT::getSizeInBits(N1.getValueType())) { 1197 return getNode(ISD::UNDEF, N1.getValueType()); 1198 } 1199 if (C2 == 0) return N1; 1200 1201 if (Opcode == ISD::SRA) { 1202 // If the sign bit is known to be zero, switch this to a SRL. 1203 if (MaskedValueIsZero(N1, 1204 1ULL << (MVT::getSizeInBits(N1.getValueType())-1), 1205 TLI)) 1206 return getNode(ISD::SRL, N1.getValueType(), N1, N2); 1207 } else { 1208 // If the part left over is known to be zero, the whole thing is zero. 1209 uint64_t TypeMask = ~0ULL >> (64-MVT::getSizeInBits(N1.getValueType())); 1210 if (Opcode == ISD::SRL) { 1211 if (MaskedValueIsZero(N1, TypeMask << C2, TLI)) 1212 return getConstant(0, N1.getValueType()); 1213 } else if (Opcode == ISD::SHL) { 1214 if (MaskedValueIsZero(N1, TypeMask >> C2, TLI)) 1215 return getConstant(0, N1.getValueType()); 1216 } 1217 } 1218 1219 if (Opcode == ISD::SHL && N1.getNumOperands() == 2) 1220 if (ConstantSDNode *OpSA = dyn_cast<ConstantSDNode>(N1.getOperand(1))) { 1221 unsigned OpSAC = OpSA->getValue(); 1222 if (N1.getOpcode() == ISD::SHL) { 1223 if (C2+OpSAC >= MVT::getSizeInBits(N1.getValueType())) 1224 return getConstant(0, N1.getValueType()); 1225 return getNode(ISD::SHL, N1.getValueType(), N1.getOperand(0), 1226 getConstant(C2+OpSAC, N2.getValueType())); 1227 } else if (N1.getOpcode() == ISD::SRL) { 1228 // (X >> C1) << C2: if C2 > C1, ((X & ~0<<C1) << C2-C1) 1229 SDOperand Mask = getNode(ISD::AND, VT, N1.getOperand(0), 1230 getConstant(~0ULL << OpSAC, VT)); 1231 if (C2 > OpSAC) { 1232 return getNode(ISD::SHL, VT, Mask, 1233 getConstant(C2-OpSAC, N2.getValueType())); 1234 } else { 1235 // (X >> C1) << C2: if C2 <= C1, ((X & ~0<<C1) >> C1-C2) 1236 return getNode(ISD::SRL, VT, Mask, 1237 getConstant(OpSAC-C2, N2.getValueType())); 1238 } 1239 } else if (N1.getOpcode() == ISD::SRA) { 1240 // if C1 == C2, just mask out low bits. 1241 if (C2 == OpSAC) 1242 return getNode(ISD::AND, VT, N1.getOperand(0), 1243 getConstant(~0ULL << C2, VT)); 1244 } 1245 } 1246 break; 1247 1248 case ISD::AND: 1249 if (!C2) return N2; // X and 0 -> 0 1250 if (N2C->isAllOnesValue()) 1251 return N1; // X and -1 -> X 1252 1253 if (MaskedValueIsZero(N1, C2, TLI)) // X and 0 -> 0 1254 return getConstant(0, VT); 1255 1256 { 1257 uint64_t NotC2 = ~C2; 1258 if (VT != MVT::i64) 1259 NotC2 &= (1ULL << MVT::getSizeInBits(VT))-1; 1260 1261 if (MaskedValueIsZero(N1, NotC2, TLI)) 1262 return N1; // if (X & ~C2) -> 0, the and is redundant 1263 } 1264 1265 // FIXME: Should add a corresponding version of this for 1266 // ZERO_EXTEND/SIGN_EXTEND by converting them to an ANY_EXTEND node which 1267 // we don't have yet. 1268 1269 // and (sign_extend_inreg x:16:32), 1 -> and x, 1 1270 if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) { 1271 // If we are masking out the part of our input that was extended, just 1272 // mask the input to the extension directly. 1273 unsigned ExtendBits = 1274 MVT::getSizeInBits(cast<VTSDNode>(N1.getOperand(1))->getVT()); 1275 if ((C2 & (~0ULL << ExtendBits)) == 0) 1276 return getNode(ISD::AND, VT, N1.getOperand(0), N2); 1277 } else if (N1.getOpcode() == ISD::OR) { 1278 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N1.getOperand(1))) 1279 if ((ORI->getValue() & C2) == C2) { 1280 // If the 'or' is setting all of the bits that we are masking for, 1281 // we know the result of the AND will be the AND mask itself. 1282 return N2; 1283 } 1284 } 1285 break; 1286 case ISD::OR: 1287 if (!C2)return N1; // X or 0 -> X 1288 if (N2C->isAllOnesValue()) 1289 return N2; // X or -1 -> -1 1290 break; 1291 case ISD::XOR: 1292 if (!C2) return N1; // X xor 0 -> X 1293 if (N2C->isAllOnesValue()) { 1294 if (N1.Val->getOpcode() == ISD::SETCC){ 1295 SDNode *SetCC = N1.Val; 1296 // !(X op Y) -> (X !op Y) 1297 bool isInteger = MVT::isInteger(SetCC->getOperand(0).getValueType()); 1298 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC->getOperand(2))->get(); 1299 return getSetCC(SetCC->getValueType(0), 1300 SetCC->getOperand(0), SetCC->getOperand(1), 1301 ISD::getSetCCInverse(CC, isInteger)); 1302 } else if (N1.getOpcode() == ISD::AND || N1.getOpcode() == ISD::OR) { 1303 SDNode *Op = N1.Val; 1304 // !(X or Y) -> (!X and !Y) iff X or Y are freely invertible 1305 // !(X and Y) -> (!X or !Y) iff X or Y are freely invertible 1306 SDOperand LHS = Op->getOperand(0), RHS = Op->getOperand(1); 1307 if (isInvertibleForFree(RHS) || isInvertibleForFree(LHS)) { 1308 LHS = getNode(ISD::XOR, VT, LHS, N2); // RHS = ~LHS 1309 RHS = getNode(ISD::XOR, VT, RHS, N2); // RHS = ~RHS 1310 if (Op->getOpcode() == ISD::AND) 1311 return getNode(ISD::OR, VT, LHS, RHS); 1312 return getNode(ISD::AND, VT, LHS, RHS); 1313 } 1314 } 1315 // X xor -1 -> not(x) ? 1316 } 1317 break; 1318 } 1319 1320 // Reassociate ((X op C1) op C2) if possible. 1321 if (N1.getOpcode() == Opcode && isAssociativeBinOp(Opcode)) 1322 if (ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N1.Val->getOperand(1))) 1323 return getNode(Opcode, VT, N1.Val->getOperand(0), 1324 getNode(Opcode, VT, N2, N1.Val->getOperand(1))); 1325 } 1326 1327 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1.Val); 1328 ConstantFPSDNode *N2CFP = dyn_cast<ConstantFPSDNode>(N2.Val); 1329 if (N1CFP) { 1330 if (N2CFP) { 1331 double C1 = N1CFP->getValue(), C2 = N2CFP->getValue(); 1332 switch (Opcode) { 1333 case ISD::ADD: return getConstantFP(C1 + C2, VT); 1334 case ISD::SUB: return getConstantFP(C1 - C2, VT); 1335 case ISD::MUL: return getConstantFP(C1 * C2, VT); 1336 case ISD::SDIV: 1337 if (C2) return getConstantFP(C1 / C2, VT); 1338 break; 1339 case ISD::SREM : 1340 if (C2) return getConstantFP(fmod(C1, C2), VT); 1341 break; 1342 default: break; 1343 } 1344 1345 } else { // Cannonicalize constant to RHS if commutative 1346 if (isCommutativeBinOp(Opcode)) { 1347 std::swap(N1CFP, N2CFP); 1348 std::swap(N1, N2); 1349 } 1350 } 1351 1352 if (Opcode == ISD::FP_ROUND_INREG) 1353 return getNode(ISD::FP_EXTEND, VT, 1354 getNode(ISD::FP_ROUND, cast<VTSDNode>(N2)->getVT(), N1)); 1355 } 1356 1357 // Finally, fold operations that do not require constants. 1358 switch (Opcode) { 1359 case ISD::TokenFactor: 1360 if (N1.getOpcode() == ISD::EntryToken) 1361 return N2; 1362 if (N2.getOpcode() == ISD::EntryToken) 1363 return N1; 1364 break; 1365 1366 case ISD::AND: 1367 case ISD::OR: 1368 if (N1.Val->getOpcode() == ISD::SETCC && N2.Val->getOpcode() == ISD::SETCC){ 1369 SDNode *LHS = N1.Val, *RHS = N2.Val; 1370 SDOperand LL = LHS->getOperand(0), RL = RHS->getOperand(0); 1371 SDOperand LR = LHS->getOperand(1), RR = RHS->getOperand(1); 1372 ISD::CondCode Op1 = cast<CondCodeSDNode>(LHS->getOperand(2))->get(); 1373 ISD::CondCode Op2 = cast<CondCodeSDNode>(RHS->getOperand(2))->get(); 1374 1375 if (LR == RR && isa<ConstantSDNode>(LR) && 1376 Op2 == Op1 && MVT::isInteger(LL.getValueType())) { 1377 // (X != 0) | (Y != 0) -> (X|Y != 0) 1378 // (X == 0) & (Y == 0) -> (X|Y == 0) 1379 // (X < 0) | (Y < 0) -> (X|Y < 0) 1380 if (cast<ConstantSDNode>(LR)->getValue() == 0 && 1381 ((Op2 == ISD::SETEQ && Opcode == ISD::AND) || 1382 (Op2 == ISD::SETNE && Opcode == ISD::OR) || 1383 (Op2 == ISD::SETLT && Opcode == ISD::OR))) 1384 return getSetCC(VT, getNode(ISD::OR, LR.getValueType(), LL, RL), LR, 1385 Op2); 1386 1387 if (cast<ConstantSDNode>(LR)->isAllOnesValue()) { 1388 // (X == -1) & (Y == -1) -> (X&Y == -1) 1389 // (X != -1) | (Y != -1) -> (X&Y != -1) 1390 // (X > -1) | (Y > -1) -> (X&Y > -1) 1391 if ((Opcode == ISD::AND && Op2 == ISD::SETEQ) || 1392 (Opcode == ISD::OR && Op2 == ISD::SETNE) || 1393 (Opcode == ISD::OR && Op2 == ISD::SETGT)) 1394 return getSetCC(VT, getNode(ISD::AND, LR.getValueType(), LL, RL), 1395 LR, Op2); 1396 // (X > -1) & (Y > -1) -> (X|Y > -1) 1397 if (Opcode == ISD::AND && Op2 == ISD::SETGT) 1398 return getSetCC(VT, getNode(ISD::OR, LR.getValueType(), LL, RL), 1399 LR, Op2); 1400 } 1401 } 1402 1403 // (X op1 Y) | (Y op2 X) -> (X op1 Y) | (X swapop2 Y) 1404 if (LL == RR && LR == RL) { 1405 Op2 = ISD::getSetCCSwappedOperands(Op2); 1406 goto MatchedBackwards; 1407 } 1408 1409 if (LL == RL && LR == RR) { 1410 MatchedBackwards: 1411 ISD::CondCode Result; 1412 bool isInteger = MVT::isInteger(LL.getValueType()); 1413 if (Opcode == ISD::OR) 1414 Result = ISD::getSetCCOrOperation(Op1, Op2, isInteger); 1415 else 1416 Result = ISD::getSetCCAndOperation(Op1, Op2, isInteger); 1417 1418 if (Result != ISD::SETCC_INVALID) 1419 return getSetCC(LHS->getValueType(0), LL, LR, Result); 1420 } 1421 } 1422 1423 // and/or zext(a), zext(b) -> zext(and/or a, b) 1424 if (N1.getOpcode() == ISD::ZERO_EXTEND && 1425 N2.getOpcode() == ISD::ZERO_EXTEND && 1426 N1.getOperand(0).getValueType() == N2.getOperand(0).getValueType()) 1427 return getNode(ISD::ZERO_EXTEND, VT, 1428 getNode(Opcode, N1.getOperand(0).getValueType(), 1429 N1.getOperand(0), N2.getOperand(0))); 1430 break; 1431 case ISD::XOR: 1432 if (N1 == N2) return getConstant(0, VT); // xor X, Y -> 0 1433 break; 1434 case ISD::ADD: 1435 if (N2.getOpcode() == ISD::FNEG) // (A+ (-B) -> A-B 1436 return getNode(ISD::SUB, VT, N1, N2.getOperand(0)); 1437 if (N1.getOpcode() == ISD::FNEG) // ((-A)+B) -> B-A 1438 return getNode(ISD::SUB, VT, N2, N1.getOperand(0)); 1439 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 1440 cast<ConstantSDNode>(N1.getOperand(0))->getValue() == 0) 1441 return getNode(ISD::SUB, VT, N2, N1.getOperand(1)); // (0-A)+B -> B-A 1442 if (N2.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N2.getOperand(0)) && 1443 cast<ConstantSDNode>(N2.getOperand(0))->getValue() == 0) 1444 return getNode(ISD::SUB, VT, N1, N2.getOperand(1)); // A+(0-B) -> A-B 1445 if (N2.getOpcode() == ISD::SUB && N1 == N2.Val->getOperand(1) && 1446 !MVT::isFloatingPoint(N2.getValueType())) 1447 return N2.Val->getOperand(0); // A+(B-A) -> B 1448 break; 1449 case ISD::SUB: 1450 if (N1.getOpcode() == ISD::ADD) { 1451 if (N1.Val->getOperand(0) == N2 && 1452 !MVT::isFloatingPoint(N2.getValueType())) 1453 return N1.Val->getOperand(1); // (A+B)-A == B 1454 if (N1.Val->getOperand(1) == N2 && 1455 !MVT::isFloatingPoint(N2.getValueType())) 1456 return N1.Val->getOperand(0); // (A+B)-B == A 1457 } 1458 if (N2.getOpcode() == ISD::FNEG) // (A- (-B) -> A+B 1459 return getNode(ISD::ADD, VT, N1, N2.getOperand(0)); 1460 break; 1461 case ISD::FP_ROUND_INREG: 1462 if (cast<VTSDNode>(N2)->getVT() == VT) return N1; // Not actually rounding. 1463 break; 1464 case ISD::SIGN_EXTEND_INREG: { 1465 MVT::ValueType EVT = cast<VTSDNode>(N2)->getVT(); 1466 if (EVT == VT) return N1; // Not actually extending 1467 1468 // If we are sign extending an extension, use the original source. 1469 if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) 1470 if (cast<VTSDNode>(N1.getOperand(1))->getVT() <= EVT) 1471 return N1; 1472 1473 // If we are sign extending a sextload, return just the load. 1474 if (N1.getOpcode() == ISD::SEXTLOAD) 1475 if (cast<VTSDNode>(N1.getOperand(3))->getVT() <= EVT) 1476 return N1; 1477 1478 // If we are extending the result of a setcc, and we already know the 1479 // contents of the top bits, eliminate the extension. 1480 if (N1.getOpcode() == ISD::SETCC && 1481 TLI.getSetCCResultContents() == 1482 TargetLowering::ZeroOrNegativeOneSetCCResult) 1483 return N1; 1484 1485 // If we are sign extending the result of an (and X, C) operation, and we 1486 // know the extended bits are zeros already, don't do the extend. 1487 if (N1.getOpcode() == ISD::AND) 1488 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getOperand(1))) { 1489 uint64_t Mask = N1C->getValue(); 1490 unsigned NumBits = MVT::getSizeInBits(EVT); 1491 if ((Mask & (~0ULL << (NumBits-1))) == 0) 1492 return N1; 1493 } 1494 break; 1495 } 1496 1497 // FIXME: figure out how to safely handle things like 1498 // int foo(int x) { return 1 << (x & 255); } 1499 // int bar() { return foo(256); } 1500#if 0 1501 case ISD::SHL: 1502 case ISD::SRL: 1503 case ISD::SRA: 1504 if (N2.getOpcode() == ISD::SIGN_EXTEND_INREG && 1505 cast<VTSDNode>(N2.getOperand(1))->getVT() != MVT::i1) 1506 return getNode(Opcode, VT, N1, N2.getOperand(0)); 1507 else if (N2.getOpcode() == ISD::AND) 1508 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(N2.getOperand(1))) { 1509 // If the and is only masking out bits that cannot effect the shift, 1510 // eliminate the and. 1511 unsigned NumBits = MVT::getSizeInBits(VT); 1512 if ((AndRHS->getValue() & (NumBits-1)) == NumBits-1) 1513 return getNode(Opcode, VT, N1, N2.getOperand(0)); 1514 } 1515 break; 1516#endif 1517 } 1518 1519 // Memoize this node if possible. 1520 SDNode *N; 1521 if (Opcode != ISD::CALLSEQ_START && Opcode != ISD::CALLSEQ_END) { 1522 SDNode *&BON = BinaryOps[std::make_pair(Opcode, std::make_pair(N1, N2))]; 1523 if (BON) return SDOperand(BON, 0); 1524 1525 BON = N = new SDNode(Opcode, N1, N2); 1526 } else { 1527 N = new SDNode(Opcode, N1, N2); 1528 } 1529 1530 N->setValueTypes(VT); 1531 AllNodes.push_back(N); 1532 return SDOperand(N, 0); 1533} 1534 1535// setAdjCallChain - This method changes the token chain of an 1536// CALLSEQ_START/END node to be the specified operand. 1537void SDNode::setAdjCallChain(SDOperand N) { 1538 assert(N.getValueType() == MVT::Other); 1539 assert((getOpcode() == ISD::CALLSEQ_START || 1540 getOpcode() == ISD::CALLSEQ_END) && "Cannot adjust this node!"); 1541 1542 Operands[0].Val->removeUser(this); 1543 Operands[0] = N; 1544 N.Val->Uses.push_back(this); 1545} 1546 1547 1548 1549SDOperand SelectionDAG::getLoad(MVT::ValueType VT, 1550 SDOperand Chain, SDOperand Ptr, 1551 SDOperand SV) { 1552 SDNode *&N = Loads[std::make_pair(Ptr, std::make_pair(Chain, VT))]; 1553 if (N) return SDOperand(N, 0); 1554 N = new SDNode(ISD::LOAD, Chain, Ptr, SV); 1555 1556 // Loads have a token chain. 1557 N->setValueTypes(VT, MVT::Other); 1558 AllNodes.push_back(N); 1559 return SDOperand(N, 0); 1560} 1561 1562 1563SDOperand SelectionDAG::getExtLoad(unsigned Opcode, MVT::ValueType VT, 1564 SDOperand Chain, SDOperand Ptr, SDOperand SV, 1565 MVT::ValueType EVT) { 1566 std::vector<SDOperand> Ops; 1567 Ops.reserve(4); 1568 Ops.push_back(Chain); 1569 Ops.push_back(Ptr); 1570 Ops.push_back(SV); 1571 Ops.push_back(getValueType(EVT)); 1572 std::vector<MVT::ValueType> VTs; 1573 VTs.reserve(2); 1574 VTs.push_back(VT); VTs.push_back(MVT::Other); // Add token chain. 1575 return getNode(Opcode, VTs, Ops); 1576} 1577 1578SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, 1579 SDOperand N1, SDOperand N2, SDOperand N3) { 1580 // Perform various simplifications. 1581 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1582 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 1583 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val); 1584 switch (Opcode) { 1585 case ISD::SETCC: { 1586 // Use SimplifySetCC to simplify SETCC's. 1587 SDOperand Simp = SimplifySetCC(VT, N1, N2, cast<CondCodeSDNode>(N3)->get()); 1588 if (Simp.Val) return Simp; 1589 break; 1590 } 1591 case ISD::SELECT: 1592 if (N1C) 1593 if (N1C->getValue()) 1594 return N2; // select true, X, Y -> X 1595 else 1596 return N3; // select false, X, Y -> Y 1597 1598 if (N2 == N3) return N2; // select C, X, X -> X 1599 1600 if (VT == MVT::i1) { // Boolean SELECT 1601 if (N2C) { 1602 if (N2C->getValue()) // select C, 1, X -> C | X 1603 return getNode(ISD::OR, VT, N1, N3); 1604 else // select C, 0, X -> ~C & X 1605 return getNode(ISD::AND, VT, 1606 getNode(ISD::XOR, N1.getValueType(), N1, 1607 getConstant(1, N1.getValueType())), N3); 1608 } else if (N3C) { 1609 if (N3C->getValue()) // select C, X, 1 -> ~C | X 1610 return getNode(ISD::OR, VT, 1611 getNode(ISD::XOR, N1.getValueType(), N1, 1612 getConstant(1, N1.getValueType())), N2); 1613 else // select C, X, 0 -> C & X 1614 return getNode(ISD::AND, VT, N1, N2); 1615 } 1616 1617 if (N1 == N2) // X ? X : Y --> X ? 1 : Y --> X | Y 1618 return getNode(ISD::OR, VT, N1, N3); 1619 if (N1 == N3) // X ? Y : X --> X ? Y : 0 --> X & Y 1620 return getNode(ISD::AND, VT, N1, N2); 1621 } 1622 if (N1.getOpcode() == ISD::SETCC) { 1623 SDOperand Simp = SimplifySelectCC(N1.getOperand(0), N1.getOperand(1), N2, 1624 N3, cast<CondCodeSDNode>(N1.getOperand(2))->get()); 1625 if (Simp.Val) return Simp; 1626 } 1627 break; 1628 case ISD::BRCOND: 1629 if (N2C) 1630 if (N2C->getValue()) // Unconditional branch 1631 return getNode(ISD::BR, MVT::Other, N1, N3); 1632 else 1633 return N1; // Never-taken branch 1634 break; 1635 } 1636 1637 std::vector<SDOperand> Ops; 1638 Ops.reserve(3); 1639 Ops.push_back(N1); 1640 Ops.push_back(N2); 1641 Ops.push_back(N3); 1642 1643 // Memoize nodes. 1644 SDNode *&N = OneResultNodes[std::make_pair(Opcode, std::make_pair(VT, Ops))]; 1645 if (N) return SDOperand(N, 0); 1646 1647 N = new SDNode(Opcode, N1, N2, N3); 1648 N->setValueTypes(VT); 1649 AllNodes.push_back(N); 1650 return SDOperand(N, 0); 1651} 1652 1653SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, 1654 SDOperand N1, SDOperand N2, SDOperand N3, 1655 SDOperand N4) { 1656 std::vector<SDOperand> Ops; 1657 Ops.reserve(4); 1658 Ops.push_back(N1); 1659 Ops.push_back(N2); 1660 Ops.push_back(N3); 1661 Ops.push_back(N4); 1662 return getNode(Opcode, VT, Ops); 1663} 1664 1665SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, 1666 SDOperand N1, SDOperand N2, SDOperand N3, 1667 SDOperand N4, SDOperand N5) { 1668 if (ISD::SELECT_CC == Opcode) { 1669 assert(N1.getValueType() == N2.getValueType() && 1670 "LHS and RHS of condition must have same type!"); 1671 assert(N3.getValueType() == N4.getValueType() && 1672 "True and False arms of SelectCC must have same type!"); 1673 assert(N3.getValueType() == VT && 1674 "select_cc node must be of same type as true and false value!"); 1675 SDOperand Simp = SimplifySelectCC(N1, N2, N3, N4, 1676 cast<CondCodeSDNode>(N5)->get()); 1677 if (Simp.Val) return Simp; 1678 } 1679 1680 std::vector<SDOperand> Ops; 1681 Ops.reserve(5); 1682 Ops.push_back(N1); 1683 Ops.push_back(N2); 1684 Ops.push_back(N3); 1685 Ops.push_back(N4); 1686 Ops.push_back(N5); 1687 return getNode(Opcode, VT, Ops); 1688} 1689 1690 1691SDOperand SelectionDAG::getSrcValue(const Value *V, int Offset) { 1692 assert((!V || isa<PointerType>(V->getType())) && 1693 "SrcValue is not a pointer?"); 1694 SDNode *&N = ValueNodes[std::make_pair(V, Offset)]; 1695 if (N) return SDOperand(N, 0); 1696 1697 N = new SrcValueSDNode(V, Offset); 1698 AllNodes.push_back(N); 1699 return SDOperand(N, 0); 1700} 1701 1702SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, 1703 std::vector<SDOperand> &Ops) { 1704 switch (Ops.size()) { 1705 case 0: return getNode(Opcode, VT); 1706 case 1: return getNode(Opcode, VT, Ops[0]); 1707 case 2: return getNode(Opcode, VT, Ops[0], Ops[1]); 1708 case 3: return getNode(Opcode, VT, Ops[0], Ops[1], Ops[2]); 1709 default: break; 1710 } 1711 1712 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Ops[1].Val); 1713 switch (Opcode) { 1714 default: break; 1715 case ISD::BRCONDTWOWAY: 1716 if (N1C) 1717 if (N1C->getValue()) // Unconditional branch to true dest. 1718 return getNode(ISD::BR, MVT::Other, Ops[0], Ops[2]); 1719 else // Unconditional branch to false dest. 1720 return getNode(ISD::BR, MVT::Other, Ops[0], Ops[3]); 1721 break; 1722 case ISD::BRTWOWAY_CC: 1723 assert(Ops.size() == 6 && "BRTWOWAY_CC takes 6 operands!"); 1724 assert(Ops[2].getValueType() == Ops[3].getValueType() && 1725 "LHS and RHS of comparison must have same type!"); 1726 break; 1727 case ISD::TRUNCSTORE: { 1728 assert(Ops.size() == 5 && "TRUNCSTORE takes 5 operands!"); 1729 MVT::ValueType EVT = cast<VTSDNode>(Ops[4])->getVT(); 1730#if 0 // FIXME: If the target supports EVT natively, convert to a truncate/store 1731 // If this is a truncating store of a constant, convert to the desired type 1732 // and store it instead. 1733 if (isa<Constant>(Ops[0])) { 1734 SDOperand Op = getNode(ISD::TRUNCATE, EVT, N1); 1735 if (isa<Constant>(Op)) 1736 N1 = Op; 1737 } 1738 // Also for ConstantFP? 1739#endif 1740 if (Ops[0].getValueType() == EVT) // Normal store? 1741 return getNode(ISD::STORE, VT, Ops[0], Ops[1], Ops[2], Ops[3]); 1742 assert(Ops[1].getValueType() > EVT && "Not a truncation?"); 1743 assert(MVT::isInteger(Ops[1].getValueType()) == MVT::isInteger(EVT) && 1744 "Can't do FP-INT conversion!"); 1745 break; 1746 } 1747 } 1748 1749 // Memoize nodes. 1750 SDNode *&N = OneResultNodes[std::make_pair(Opcode, std::make_pair(VT, Ops))]; 1751 if (N) return SDOperand(N, 0); 1752 N = new SDNode(Opcode, Ops); 1753 N->setValueTypes(VT); 1754 AllNodes.push_back(N); 1755 return SDOperand(N, 0); 1756} 1757 1758SDOperand SelectionDAG::getNode(unsigned Opcode, 1759 std::vector<MVT::ValueType> &ResultTys, 1760 std::vector<SDOperand> &Ops) { 1761 if (ResultTys.size() == 1) 1762 return getNode(Opcode, ResultTys[0], Ops); 1763 1764 switch (Opcode) { 1765 case ISD::EXTLOAD: 1766 case ISD::SEXTLOAD: 1767 case ISD::ZEXTLOAD: { 1768 MVT::ValueType EVT = cast<VTSDNode>(Ops[3])->getVT(); 1769 assert(Ops.size() == 4 && ResultTys.size() == 2 && "Bad *EXTLOAD!"); 1770 // If they are asking for an extending load from/to the same thing, return a 1771 // normal load. 1772 if (ResultTys[0] == EVT) 1773 return getLoad(ResultTys[0], Ops[0], Ops[1], Ops[2]); 1774 assert(EVT < ResultTys[0] && 1775 "Should only be an extending load, not truncating!"); 1776 assert((Opcode == ISD::EXTLOAD || MVT::isInteger(ResultTys[0])) && 1777 "Cannot sign/zero extend a FP load!"); 1778 assert(MVT::isInteger(ResultTys[0]) == MVT::isInteger(EVT) && 1779 "Cannot convert from FP to Int or Int -> FP!"); 1780 break; 1781 } 1782 1783 // FIXME: figure out how to safely handle things like 1784 // int foo(int x) { return 1 << (x & 255); } 1785 // int bar() { return foo(256); } 1786#if 0 1787 case ISD::SRA_PARTS: 1788 case ISD::SRL_PARTS: 1789 case ISD::SHL_PARTS: 1790 if (N3.getOpcode() == ISD::SIGN_EXTEND_INREG && 1791 cast<VTSDNode>(N3.getOperand(1))->getVT() != MVT::i1) 1792 return getNode(Opcode, VT, N1, N2, N3.getOperand(0)); 1793 else if (N3.getOpcode() == ISD::AND) 1794 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(N3.getOperand(1))) { 1795 // If the and is only masking out bits that cannot effect the shift, 1796 // eliminate the and. 1797 unsigned NumBits = MVT::getSizeInBits(VT)*2; 1798 if ((AndRHS->getValue() & (NumBits-1)) == NumBits-1) 1799 return getNode(Opcode, VT, N1, N2, N3.getOperand(0)); 1800 } 1801 break; 1802#endif 1803 } 1804 1805 // Memoize the node. 1806 SDNode *&N = ArbitraryNodes[std::make_pair(Opcode, std::make_pair(ResultTys, 1807 Ops))]; 1808 if (N) return SDOperand(N, 0); 1809 N = new SDNode(Opcode, Ops); 1810 N->setValueTypes(ResultTys); 1811 AllNodes.push_back(N); 1812 return SDOperand(N, 0); 1813} 1814 1815 1816/// SelectNodeTo - These are used for target selectors to *mutate* the 1817/// specified node to have the specified return type, Target opcode, and 1818/// operands. Note that target opcodes are stored as 1819/// ISD::BUILTIN_OP_END+TargetOpcode in the node opcode field. 1820void SelectionDAG::SelectNodeTo(SDNode *N, MVT::ValueType VT, 1821 unsigned TargetOpc, SDOperand Op1) { 1822 RemoveNodeFromCSEMaps(N); 1823 N->MorphNodeTo(ISD::BUILTIN_OP_END+TargetOpc); 1824 N->setValueTypes(VT); 1825 N->setOperands(Op1); 1826} 1827void SelectionDAG::SelectNodeTo(SDNode *N, MVT::ValueType VT, 1828 unsigned TargetOpc, SDOperand Op1, 1829 SDOperand Op2) { 1830 RemoveNodeFromCSEMaps(N); 1831 N->MorphNodeTo(ISD::BUILTIN_OP_END+TargetOpc); 1832 N->setValueTypes(VT); 1833 N->setOperands(Op1, Op2); 1834} 1835void SelectionDAG::SelectNodeTo(SDNode *N, 1836 MVT::ValueType VT1, MVT::ValueType VT2, 1837 unsigned TargetOpc, SDOperand Op1, 1838 SDOperand Op2) { 1839 RemoveNodeFromCSEMaps(N); 1840 N->MorphNodeTo(ISD::BUILTIN_OP_END+TargetOpc); 1841 N->setValueTypes(VT1, VT2); 1842 N->setOperands(Op1, Op2); 1843} 1844void SelectionDAG::SelectNodeTo(SDNode *N, MVT::ValueType VT, 1845 unsigned TargetOpc, SDOperand Op1, 1846 SDOperand Op2, SDOperand Op3) { 1847 RemoveNodeFromCSEMaps(N); 1848 N->MorphNodeTo(ISD::BUILTIN_OP_END+TargetOpc); 1849 N->setValueTypes(VT); 1850 N->setOperands(Op1, Op2, Op3); 1851} 1852void SelectionDAG::SelectNodeTo(SDNode *N, MVT::ValueType VT1, 1853 MVT::ValueType VT2, 1854 unsigned TargetOpc, SDOperand Op1, 1855 SDOperand Op2, SDOperand Op3) { 1856 RemoveNodeFromCSEMaps(N); 1857 N->MorphNodeTo(ISD::BUILTIN_OP_END+TargetOpc); 1858 N->setValueTypes(VT1, VT2); 1859 N->setOperands(Op1, Op2, Op3); 1860} 1861 1862void SelectionDAG::SelectNodeTo(SDNode *N, MVT::ValueType VT, 1863 unsigned TargetOpc, SDOperand Op1, 1864 SDOperand Op2, SDOperand Op3, SDOperand Op4) { 1865 RemoveNodeFromCSEMaps(N); 1866 N->MorphNodeTo(ISD::BUILTIN_OP_END+TargetOpc); 1867 N->setValueTypes(VT); 1868 N->setOperands(Op1, Op2, Op3, Op4); 1869} 1870void SelectionDAG::SelectNodeTo(SDNode *N, MVT::ValueType VT, 1871 unsigned TargetOpc, SDOperand Op1, 1872 SDOperand Op2, SDOperand Op3, SDOperand Op4, 1873 SDOperand Op5) { 1874 RemoveNodeFromCSEMaps(N); 1875 N->MorphNodeTo(ISD::BUILTIN_OP_END+TargetOpc); 1876 N->setValueTypes(VT); 1877 N->setOperands(Op1, Op2, Op3, Op4, Op5); 1878} 1879 1880/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. 1881/// This can cause recursive merging of nodes in the DAG. 1882/// 1883void SelectionDAG::ReplaceAllUsesWith(SDNode *From, SDNode *To) { 1884 assert(From != To && "Cannot replace uses of with self"); 1885 while (!From->use_empty()) { 1886 // Process users until they are all gone. 1887 SDNode *U = *From->use_begin(); 1888 1889 // This node is about to morph, remove its old self from the CSE maps. 1890 RemoveNodeFromCSEMaps(U); 1891 1892 for (unsigned i = 0, e = U->getNumOperands(); i != e; ++i) 1893 if (U->getOperand(i).Val == From) { 1894 assert(From->getValueType(U->getOperand(i).ResNo) == 1895 To->getValueType(U->getOperand(i).ResNo)); 1896 From->removeUser(U); 1897 U->Operands[i].Val = To; 1898 To->addUser(U); 1899 } 1900 1901 // Now that we have modified U, add it back to the CSE maps. If it already 1902 // exists there, recursively merge the results together. 1903 if (SDNode *Existing = AddNonLeafNodeToCSEMaps(U)) 1904 ReplaceAllUsesWith(U, Existing); 1905 // U is now dead. 1906 } 1907} 1908 1909//===----------------------------------------------------------------------===// 1910// SDNode Class 1911//===----------------------------------------------------------------------===// 1912 1913/// hasNUsesOfValue - Return true if there are exactly NUSES uses of the 1914/// indicated value. This method ignores uses of other values defined by this 1915/// operation. 1916bool SDNode::hasNUsesOfValue(unsigned NUses, unsigned Value) { 1917 assert(Value < getNumValues() && "Bad value!"); 1918 1919 // If there is only one value, this is easy. 1920 if (getNumValues() == 1) 1921 return use_size() == NUses; 1922 if (Uses.size() < NUses) return false; 1923 1924 SDOperand TheValue(this, Value); 1925 1926 std::set<SDNode*> UsersHandled; 1927 1928 for (std::vector<SDNode*>::iterator UI = Uses.begin(), E = Uses.end(); 1929 UI != E; ++UI) { 1930 SDNode *User = *UI; 1931 if (User->getNumOperands() == 1 || 1932 UsersHandled.insert(User).second) // First time we've seen this? 1933 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 1934 if (User->getOperand(i) == TheValue) { 1935 if (NUses == 0) 1936 return false; // too many uses 1937 --NUses; 1938 } 1939 } 1940 1941 // Found exactly the right number of uses? 1942 return NUses == 0; 1943} 1944 1945 1946const char *SDNode::getOperationName(const SelectionDAG *G) const { 1947 switch (getOpcode()) { 1948 default: 1949 if (getOpcode() < ISD::BUILTIN_OP_END) 1950 return "<<Unknown DAG Node>>"; 1951 else { 1952 if (G) 1953 if (const TargetInstrInfo *TII = G->getTarget().getInstrInfo()) 1954 return TII->getName(getOpcode()-ISD::BUILTIN_OP_END); 1955 return "<<Unknown Target Node>>"; 1956 } 1957 1958 case ISD::PCMARKER: return "PCMarker"; 1959 case ISD::SRCVALUE: return "SrcValue"; 1960 case ISD::VALUETYPE: return "ValueType"; 1961 case ISD::EntryToken: return "EntryToken"; 1962 case ISD::TokenFactor: return "TokenFactor"; 1963 case ISD::Constant: return "Constant"; 1964 case ISD::TargetConstant: return "TargetConstant"; 1965 case ISD::ConstantFP: return "ConstantFP"; 1966 case ISD::GlobalAddress: return "GlobalAddress"; 1967 case ISD::TargetGlobalAddress: return "TargetGlobalAddress"; 1968 case ISD::FrameIndex: return "FrameIndex"; 1969 case ISD::BasicBlock: return "BasicBlock"; 1970 case ISD::Register: return "Register"; 1971 case ISD::ExternalSymbol: return "ExternalSymbol"; 1972 case ISD::ConstantPool: return "ConstantPoolIndex"; 1973 case ISD::CopyToReg: return "CopyToReg"; 1974 case ISD::CopyFromReg: return "CopyFromReg"; 1975 case ISD::ImplicitDef: return "ImplicitDef"; 1976 case ISD::UNDEF: return "undef"; 1977 1978 // Unary operators 1979 case ISD::FABS: return "fabs"; 1980 case ISD::FNEG: return "fneg"; 1981 case ISD::FSQRT: return "fsqrt"; 1982 case ISD::FSIN: return "fsin"; 1983 case ISD::FCOS: return "fcos"; 1984 1985 // Binary operators 1986 case ISD::ADD: return "add"; 1987 case ISD::SUB: return "sub"; 1988 case ISD::MUL: return "mul"; 1989 case ISD::MULHU: return "mulhu"; 1990 case ISD::MULHS: return "mulhs"; 1991 case ISD::SDIV: return "sdiv"; 1992 case ISD::UDIV: return "udiv"; 1993 case ISD::SREM: return "srem"; 1994 case ISD::UREM: return "urem"; 1995 case ISD::AND: return "and"; 1996 case ISD::OR: return "or"; 1997 case ISD::XOR: return "xor"; 1998 case ISD::SHL: return "shl"; 1999 case ISD::SRA: return "sra"; 2000 case ISD::SRL: return "srl"; 2001 2002 case ISD::SETCC: return "setcc"; 2003 case ISD::SELECT: return "select"; 2004 case ISD::SELECT_CC: return "select_cc"; 2005 case ISD::ADD_PARTS: return "add_parts"; 2006 case ISD::SUB_PARTS: return "sub_parts"; 2007 case ISD::SHL_PARTS: return "shl_parts"; 2008 case ISD::SRA_PARTS: return "sra_parts"; 2009 case ISD::SRL_PARTS: return "srl_parts"; 2010 2011 // Conversion operators. 2012 case ISD::SIGN_EXTEND: return "sign_extend"; 2013 case ISD::ZERO_EXTEND: return "zero_extend"; 2014 case ISD::SIGN_EXTEND_INREG: return "sign_extend_inreg"; 2015 case ISD::TRUNCATE: return "truncate"; 2016 case ISD::FP_ROUND: return "fp_round"; 2017 case ISD::FP_ROUND_INREG: return "fp_round_inreg"; 2018 case ISD::FP_EXTEND: return "fp_extend"; 2019 2020 case ISD::SINT_TO_FP: return "sint_to_fp"; 2021 case ISD::UINT_TO_FP: return "uint_to_fp"; 2022 case ISD::FP_TO_SINT: return "fp_to_sint"; 2023 case ISD::FP_TO_UINT: return "fp_to_uint"; 2024 2025 // Control flow instructions 2026 case ISD::BR: return "br"; 2027 case ISD::BRCOND: return "brcond"; 2028 case ISD::BRCONDTWOWAY: return "brcondtwoway"; 2029 case ISD::BR_CC: return "br_cc"; 2030 case ISD::BRTWOWAY_CC: return "brtwoway_cc"; 2031 case ISD::RET: return "ret"; 2032 case ISD::CALL: return "call"; 2033 case ISD::TAILCALL:return "tailcall"; 2034 case ISD::CALLSEQ_START: return "callseq_start"; 2035 case ISD::CALLSEQ_END: return "callseq_end"; 2036 2037 // Other operators 2038 case ISD::LOAD: return "load"; 2039 case ISD::STORE: return "store"; 2040 case ISD::EXTLOAD: return "extload"; 2041 case ISD::SEXTLOAD: return "sextload"; 2042 case ISD::ZEXTLOAD: return "zextload"; 2043 case ISD::TRUNCSTORE: return "truncstore"; 2044 2045 case ISD::DYNAMIC_STACKALLOC: return "dynamic_stackalloc"; 2046 case ISD::EXTRACT_ELEMENT: return "extract_element"; 2047 case ISD::BUILD_PAIR: return "build_pair"; 2048 case ISD::MEMSET: return "memset"; 2049 case ISD::MEMCPY: return "memcpy"; 2050 case ISD::MEMMOVE: return "memmove"; 2051 2052 // Bit counting 2053 case ISD::CTPOP: return "ctpop"; 2054 case ISD::CTTZ: return "cttz"; 2055 case ISD::CTLZ: return "ctlz"; 2056 2057 // IO Intrinsics 2058 case ISD::READPORT: return "readport"; 2059 case ISD::WRITEPORT: return "writeport"; 2060 case ISD::READIO: return "readio"; 2061 case ISD::WRITEIO: return "writeio"; 2062 2063 case ISD::CONDCODE: 2064 switch (cast<CondCodeSDNode>(this)->get()) { 2065 default: assert(0 && "Unknown setcc condition!"); 2066 case ISD::SETOEQ: return "setoeq"; 2067 case ISD::SETOGT: return "setogt"; 2068 case ISD::SETOGE: return "setoge"; 2069 case ISD::SETOLT: return "setolt"; 2070 case ISD::SETOLE: return "setole"; 2071 case ISD::SETONE: return "setone"; 2072 2073 case ISD::SETO: return "seto"; 2074 case ISD::SETUO: return "setuo"; 2075 case ISD::SETUEQ: return "setue"; 2076 case ISD::SETUGT: return "setugt"; 2077 case ISD::SETUGE: return "setuge"; 2078 case ISD::SETULT: return "setult"; 2079 case ISD::SETULE: return "setule"; 2080 case ISD::SETUNE: return "setune"; 2081 2082 case ISD::SETEQ: return "seteq"; 2083 case ISD::SETGT: return "setgt"; 2084 case ISD::SETGE: return "setge"; 2085 case ISD::SETLT: return "setlt"; 2086 case ISD::SETLE: return "setle"; 2087 case ISD::SETNE: return "setne"; 2088 } 2089 } 2090} 2091 2092void SDNode::dump() const { dump(0); } 2093void SDNode::dump(const SelectionDAG *G) const { 2094 std::cerr << (void*)this << ": "; 2095 2096 for (unsigned i = 0, e = getNumValues(); i != e; ++i) { 2097 if (i) std::cerr << ","; 2098 if (getValueType(i) == MVT::Other) 2099 std::cerr << "ch"; 2100 else 2101 std::cerr << MVT::getValueTypeString(getValueType(i)); 2102 } 2103 std::cerr << " = " << getOperationName(G); 2104 2105 std::cerr << " "; 2106 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 2107 if (i) std::cerr << ", "; 2108 std::cerr << (void*)getOperand(i).Val; 2109 if (unsigned RN = getOperand(i).ResNo) 2110 std::cerr << ":" << RN; 2111 } 2112 2113 if (const ConstantSDNode *CSDN = dyn_cast<ConstantSDNode>(this)) { 2114 std::cerr << "<" << CSDN->getValue() << ">"; 2115 } else if (const ConstantFPSDNode *CSDN = dyn_cast<ConstantFPSDNode>(this)) { 2116 std::cerr << "<" << CSDN->getValue() << ">"; 2117 } else if (const GlobalAddressSDNode *GADN = 2118 dyn_cast<GlobalAddressSDNode>(this)) { 2119 std::cerr << "<"; 2120 WriteAsOperand(std::cerr, GADN->getGlobal()) << ">"; 2121 } else if (const FrameIndexSDNode *FIDN = dyn_cast<FrameIndexSDNode>(this)) { 2122 std::cerr << "<" << FIDN->getIndex() << ">"; 2123 } else if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(this)){ 2124 std::cerr << "<" << CP->getIndex() << ">"; 2125 } else if (const BasicBlockSDNode *BBDN = dyn_cast<BasicBlockSDNode>(this)) { 2126 std::cerr << "<"; 2127 const Value *LBB = (const Value*)BBDN->getBasicBlock()->getBasicBlock(); 2128 if (LBB) 2129 std::cerr << LBB->getName() << " "; 2130 std::cerr << (const void*)BBDN->getBasicBlock() << ">"; 2131 } else if (const RegisterSDNode *R = dyn_cast<RegisterSDNode>(this)) { 2132 if (G && MRegisterInfo::isPhysicalRegister(R->getReg())) { 2133 std::cerr << " " <<G->getTarget().getRegisterInfo()->getName(R->getReg()); 2134 } else { 2135 std::cerr << " #" << R->getReg(); 2136 } 2137 } else if (const ExternalSymbolSDNode *ES = 2138 dyn_cast<ExternalSymbolSDNode>(this)) { 2139 std::cerr << "'" << ES->getSymbol() << "'"; 2140 } else if (const SrcValueSDNode *M = dyn_cast<SrcValueSDNode>(this)) { 2141 if (M->getValue()) 2142 std::cerr << "<" << M->getValue() << ":" << M->getOffset() << ">"; 2143 else 2144 std::cerr << "<null:" << M->getOffset() << ">"; 2145 } else if (const VTSDNode *N = dyn_cast<VTSDNode>(this)) { 2146 std::cerr << ":" << getValueTypeString(N->getVT()); 2147 } 2148} 2149 2150static void DumpNodes(SDNode *N, unsigned indent, const SelectionDAG *G) { 2151 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 2152 if (N->getOperand(i).Val->hasOneUse()) 2153 DumpNodes(N->getOperand(i).Val, indent+2, G); 2154 else 2155 std::cerr << "\n" << std::string(indent+2, ' ') 2156 << (void*)N->getOperand(i).Val << ": <multiple use>"; 2157 2158 2159 std::cerr << "\n" << std::string(indent, ' '); 2160 N->dump(G); 2161} 2162 2163void SelectionDAG::dump() const { 2164 std::cerr << "SelectionDAG has " << AllNodes.size() << " nodes:"; 2165 std::vector<SDNode*> Nodes(AllNodes); 2166 std::sort(Nodes.begin(), Nodes.end()); 2167 2168 for (unsigned i = 0, e = Nodes.size(); i != e; ++i) { 2169 if (!Nodes[i]->hasOneUse() && Nodes[i] != getRoot().Val) 2170 DumpNodes(Nodes[i], 2, this); 2171 } 2172 2173 DumpNodes(getRoot().Val, 2, this); 2174 2175 std::cerr << "\n\n"; 2176} 2177 2178