SelectionDAG.cpp revision 7cf7e3f33f25544d08492d47cc8a1cbba25dc8d7
1//===-- SelectionDAG.cpp - Implement the SelectionDAG data structures -----===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAG class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/Constants.h" 16#include "llvm/GlobalValue.h" 17#include "llvm/Assembly/Writer.h" 18#include "llvm/CodeGen/MachineBasicBlock.h" 19#include "llvm/Support/MathExtras.h" 20#include "llvm/Target/TargetLowering.h" 21#include <iostream> 22#include <set> 23#include <cmath> 24#include <algorithm> 25using namespace llvm; 26 27static bool isCommutativeBinOp(unsigned Opcode) { 28 switch (Opcode) { 29 case ISD::ADD: 30 case ISD::MUL: 31 case ISD::AND: 32 case ISD::OR: 33 case ISD::XOR: return true; 34 default: return false; // FIXME: Need commutative info for user ops! 35 } 36} 37 38static bool isAssociativeBinOp(unsigned Opcode) { 39 switch (Opcode) { 40 case ISD::ADD: 41 case ISD::MUL: 42 case ISD::AND: 43 case ISD::OR: 44 case ISD::XOR: return true; 45 default: return false; // FIXME: Need associative info for user ops! 46 } 47} 48 49// isInvertibleForFree - Return true if there is no cost to emitting the logical 50// inverse of this node. 51static bool isInvertibleForFree(SDOperand N) { 52 if (isa<ConstantSDNode>(N.Val)) return true; 53 if (N.Val->getOpcode() == ISD::SETCC && N.Val->hasOneUse()) 54 return true; 55 return false; 56} 57 58 59/// getSetCCSwappedOperands - Return the operation corresponding to (Y op X) 60/// when given the operation for (X op Y). 61ISD::CondCode ISD::getSetCCSwappedOperands(ISD::CondCode Operation) { 62 // To perform this operation, we just need to swap the L and G bits of the 63 // operation. 64 unsigned OldL = (Operation >> 2) & 1; 65 unsigned OldG = (Operation >> 1) & 1; 66 return ISD::CondCode((Operation & ~6) | // Keep the N, U, E bits 67 (OldL << 1) | // New G bit 68 (OldG << 2)); // New L bit. 69} 70 71/// getSetCCInverse - Return the operation corresponding to !(X op Y), where 72/// 'op' is a valid SetCC operation. 73ISD::CondCode ISD::getSetCCInverse(ISD::CondCode Op, bool isInteger) { 74 unsigned Operation = Op; 75 if (isInteger) 76 Operation ^= 7; // Flip L, G, E bits, but not U. 77 else 78 Operation ^= 15; // Flip all of the condition bits. 79 if (Operation > ISD::SETTRUE2) 80 Operation &= ~8; // Don't let N and U bits get set. 81 return ISD::CondCode(Operation); 82} 83 84 85/// isSignedOp - For an integer comparison, return 1 if the comparison is a 86/// signed operation and 2 if the result is an unsigned comparison. Return zero 87/// if the operation does not depend on the sign of the input (setne and seteq). 88static int isSignedOp(ISD::CondCode Opcode) { 89 switch (Opcode) { 90 default: assert(0 && "Illegal integer setcc operation!"); 91 case ISD::SETEQ: 92 case ISD::SETNE: return 0; 93 case ISD::SETLT: 94 case ISD::SETLE: 95 case ISD::SETGT: 96 case ISD::SETGE: return 1; 97 case ISD::SETULT: 98 case ISD::SETULE: 99 case ISD::SETUGT: 100 case ISD::SETUGE: return 2; 101 } 102} 103 104/// getSetCCOrOperation - Return the result of a logical OR between different 105/// comparisons of identical values: ((X op1 Y) | (X op2 Y)). This function 106/// returns SETCC_INVALID if it is not possible to represent the resultant 107/// comparison. 108ISD::CondCode ISD::getSetCCOrOperation(ISD::CondCode Op1, ISD::CondCode Op2, 109 bool isInteger) { 110 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 111 // Cannot fold a signed integer setcc with an unsigned integer setcc. 112 return ISD::SETCC_INVALID; 113 114 unsigned Op = Op1 | Op2; // Combine all of the condition bits. 115 116 // If the N and U bits get set then the resultant comparison DOES suddenly 117 // care about orderedness, and is true when ordered. 118 if (Op > ISD::SETTRUE2) 119 Op &= ~16; // Clear the N bit. 120 return ISD::CondCode(Op); 121} 122 123/// getSetCCAndOperation - Return the result of a logical AND between different 124/// comparisons of identical values: ((X op1 Y) & (X op2 Y)). This 125/// function returns zero if it is not possible to represent the resultant 126/// comparison. 127ISD::CondCode ISD::getSetCCAndOperation(ISD::CondCode Op1, ISD::CondCode Op2, 128 bool isInteger) { 129 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 130 // Cannot fold a signed setcc with an unsigned setcc. 131 return ISD::SETCC_INVALID; 132 133 // Combine all of the condition bits. 134 return ISD::CondCode(Op1 & Op2); 135} 136 137const TargetMachine &SelectionDAG::getTarget() const { 138 return TLI.getTargetMachine(); 139} 140 141 142/// RemoveDeadNodes - This method deletes all unreachable nodes in the 143/// SelectionDAG, including nodes (like loads) that have uses of their token 144/// chain but no other uses and no side effect. If a node is passed in as an 145/// argument, it is used as the seed for node deletion. 146void SelectionDAG::RemoveDeadNodes(SDNode *N) { 147 std::set<SDNode*> AllNodeSet(AllNodes.begin(), AllNodes.end()); 148 149 // Create a dummy node (which is not added to allnodes), that adds a reference 150 // to the root node, preventing it from being deleted. 151 SDNode *DummyNode = new SDNode(ISD::EntryToken, getRoot()); 152 153 DeleteNodeIfDead(N, &AllNodeSet); 154 155 Restart: 156 unsigned NumNodes = AllNodeSet.size(); 157 for (std::set<SDNode*>::iterator I = AllNodeSet.begin(), E = AllNodeSet.end(); 158 I != E; ++I) { 159 // Try to delete this node. 160 DeleteNodeIfDead(*I, &AllNodeSet); 161 162 // If we actually deleted any nodes, do not use invalid iterators in 163 // AllNodeSet. 164 if (AllNodeSet.size() != NumNodes) 165 goto Restart; 166 } 167 168 // Restore AllNodes. 169 if (AllNodes.size() != NumNodes) 170 AllNodes.assign(AllNodeSet.begin(), AllNodeSet.end()); 171 172 // If the root changed (e.g. it was a dead load, update the root). 173 setRoot(DummyNode->getOperand(0)); 174 175 // Now that we are done with the dummy node, delete it. 176 DummyNode->getOperand(0).Val->removeUser(DummyNode); 177 delete DummyNode; 178} 179 180void SelectionDAG::DeleteNodeIfDead(SDNode *N, void *NodeSet) { 181 if (!N->use_empty()) 182 return; 183 184 // Okay, we really are going to delete this node. First take this out of the 185 // appropriate CSE map. 186 switch (N->getOpcode()) { 187 case ISD::Constant: 188 Constants.erase(std::make_pair(cast<ConstantSDNode>(N)->getValue(), 189 N->getValueType(0))); 190 break; 191 case ISD::ConstantFP: { 192 union { 193 double DV; 194 uint64_t IV; 195 }; 196 DV = cast<ConstantFPSDNode>(N)->getValue(); 197 ConstantFPs.erase(std::make_pair(IV, N->getValueType(0))); 198 break; 199 } 200 case ISD::CONDCODE: 201 assert(CondCodeNodes[cast<CondCodeSDNode>(N)->get()] && 202 "Cond code doesn't exist!"); 203 CondCodeNodes[cast<CondCodeSDNode>(N)->get()] = 0; 204 break; 205 case ISD::GlobalAddress: 206 GlobalValues.erase(cast<GlobalAddressSDNode>(N)->getGlobal()); 207 break; 208 case ISD::FrameIndex: 209 FrameIndices.erase(cast<FrameIndexSDNode>(N)->getIndex()); 210 break; 211 case ISD::ConstantPool: 212 ConstantPoolIndices.erase(cast<ConstantPoolSDNode>(N)->getIndex()); 213 break; 214 case ISD::BasicBlock: 215 BBNodes.erase(cast<BasicBlockSDNode>(N)->getBasicBlock()); 216 break; 217 case ISD::ExternalSymbol: 218 ExternalSymbols.erase(cast<ExternalSymbolSDNode>(N)->getSymbol()); 219 break; 220 case ISD::VALUETYPE: 221 ValueTypeNodes[cast<VTSDNode>(N)->getVT()] = 0; 222 break; 223 case ISD::SRCVALUE: { 224 SrcValueSDNode *SVN = cast<SrcValueSDNode>(N); 225 ValueNodes.erase(std::make_pair(SVN->getValue(), SVN->getOffset())); 226 break; 227 } 228 case ISD::LOAD: 229 Loads.erase(std::make_pair(N->getOperand(1), 230 std::make_pair(N->getOperand(0), 231 N->getValueType(0)))); 232 break; 233 default: 234 if (N->getNumOperands() == 1) 235 UnaryOps.erase(std::make_pair(N->getOpcode(), 236 std::make_pair(N->getOperand(0), 237 N->getValueType(0)))); 238 else if (N->getNumOperands() == 2) 239 BinaryOps.erase(std::make_pair(N->getOpcode(), 240 std::make_pair(N->getOperand(0), 241 N->getOperand(1)))); 242 else if (N->getNumValues() == 1) { 243 std::vector<SDOperand> Ops(N->op_begin(), N->op_end()); 244 OneResultNodes.erase(std::make_pair(N->getOpcode(), 245 std::make_pair(N->getValueType(0), 246 Ops))); 247 } else { 248 // Remove the node from the ArbitraryNodes map. 249 std::vector<MVT::ValueType> RV(N->value_begin(), N->value_end()); 250 std::vector<SDOperand> Ops(N->op_begin(), N->op_end()); 251 ArbitraryNodes.erase(std::make_pair(N->getOpcode(), 252 std::make_pair(RV, Ops))); 253 } 254 break; 255 } 256 257 // Next, brutally remove the operand list. 258 while (!N->Operands.empty()) { 259 SDNode *O = N->Operands.back().Val; 260 N->Operands.pop_back(); 261 O->removeUser(N); 262 263 // Now that we removed this operand, see if there are no uses of it left. 264 DeleteNodeIfDead(O, NodeSet); 265 } 266 267 // Remove the node from the nodes set and delete it. 268 std::set<SDNode*> &AllNodeSet = *(std::set<SDNode*>*)NodeSet; 269 AllNodeSet.erase(N); 270 271 // Now that the node is gone, check to see if any of the operands of this node 272 // are dead now. 273 delete N; 274} 275 276 277SelectionDAG::~SelectionDAG() { 278 for (unsigned i = 0, e = AllNodes.size(); i != e; ++i) 279 delete AllNodes[i]; 280} 281 282SDOperand SelectionDAG::getZeroExtendInReg(SDOperand Op, MVT::ValueType VT) { 283 if (Op.getValueType() == VT) return Op; 284 int64_t Imm = ~0ULL >> (64-MVT::getSizeInBits(VT)); 285 return getNode(ISD::AND, Op.getValueType(), Op, 286 getConstant(Imm, Op.getValueType())); 287} 288 289SDOperand SelectionDAG::getConstant(uint64_t Val, MVT::ValueType VT) { 290 assert(MVT::isInteger(VT) && "Cannot create FP integer constant!"); 291 // Mask out any bits that are not valid for this constant. 292 if (VT != MVT::i64) 293 Val &= ((uint64_t)1 << MVT::getSizeInBits(VT)) - 1; 294 295 SDNode *&N = Constants[std::make_pair(Val, VT)]; 296 if (N) return SDOperand(N, 0); 297 N = new ConstantSDNode(Val, VT); 298 AllNodes.push_back(N); 299 return SDOperand(N, 0); 300} 301 302SDOperand SelectionDAG::getConstantFP(double Val, MVT::ValueType VT) { 303 assert(MVT::isFloatingPoint(VT) && "Cannot create integer FP constant!"); 304 if (VT == MVT::f32) 305 Val = (float)Val; // Mask out extra precision. 306 307 // Do the map lookup using the actual bit pattern for the floating point 308 // value, so that we don't have problems with 0.0 comparing equal to -0.0, and 309 // we don't have issues with SNANs. 310 union { 311 double DV; 312 uint64_t IV; 313 }; 314 315 DV = Val; 316 317 SDNode *&N = ConstantFPs[std::make_pair(IV, VT)]; 318 if (N) return SDOperand(N, 0); 319 N = new ConstantFPSDNode(Val, VT); 320 AllNodes.push_back(N); 321 return SDOperand(N, 0); 322} 323 324 325 326SDOperand SelectionDAG::getGlobalAddress(const GlobalValue *GV, 327 MVT::ValueType VT) { 328 SDNode *&N = GlobalValues[GV]; 329 if (N) return SDOperand(N, 0); 330 N = new GlobalAddressSDNode(GV,VT); 331 AllNodes.push_back(N); 332 return SDOperand(N, 0); 333} 334 335SDOperand SelectionDAG::getFrameIndex(int FI, MVT::ValueType VT) { 336 SDNode *&N = FrameIndices[FI]; 337 if (N) return SDOperand(N, 0); 338 N = new FrameIndexSDNode(FI, VT); 339 AllNodes.push_back(N); 340 return SDOperand(N, 0); 341} 342 343SDOperand SelectionDAG::getConstantPool(unsigned CPIdx, MVT::ValueType VT) { 344 SDNode *N = ConstantPoolIndices[CPIdx]; 345 if (N) return SDOperand(N, 0); 346 N = new ConstantPoolSDNode(CPIdx, VT); 347 AllNodes.push_back(N); 348 return SDOperand(N, 0); 349} 350 351SDOperand SelectionDAG::getBasicBlock(MachineBasicBlock *MBB) { 352 SDNode *&N = BBNodes[MBB]; 353 if (N) return SDOperand(N, 0); 354 N = new BasicBlockSDNode(MBB); 355 AllNodes.push_back(N); 356 return SDOperand(N, 0); 357} 358 359SDOperand SelectionDAG::getValueType(MVT::ValueType VT) { 360 if ((unsigned)VT >= ValueTypeNodes.size()) 361 ValueTypeNodes.resize(VT+1); 362 if (ValueTypeNodes[VT] == 0) { 363 ValueTypeNodes[VT] = new VTSDNode(VT); 364 AllNodes.push_back(ValueTypeNodes[VT]); 365 } 366 367 return SDOperand(ValueTypeNodes[VT], 0); 368} 369 370SDOperand SelectionDAG::getExternalSymbol(const char *Sym, MVT::ValueType VT) { 371 SDNode *&N = ExternalSymbols[Sym]; 372 if (N) return SDOperand(N, 0); 373 N = new ExternalSymbolSDNode(Sym, VT); 374 AllNodes.push_back(N); 375 return SDOperand(N, 0); 376} 377 378SDOperand SelectionDAG::getCondCode(ISD::CondCode Cond) { 379 if ((unsigned)Cond >= CondCodeNodes.size()) 380 CondCodeNodes.resize(Cond+1); 381 382 if (CondCodeNodes[Cond] == 0) 383 CondCodeNodes[Cond] = new CondCodeSDNode(Cond); 384 return SDOperand(CondCodeNodes[Cond], 0); 385} 386 387SDOperand SelectionDAG::SimplfySetCC(MVT::ValueType VT, SDOperand N1, 388 SDOperand N2, ISD::CondCode Cond) { 389 // These setcc operations always fold. 390 switch (Cond) { 391 default: break; 392 case ISD::SETFALSE: 393 case ISD::SETFALSE2: return getConstant(0, VT); 394 case ISD::SETTRUE: 395 case ISD::SETTRUE2: return getConstant(1, VT); 396 } 397 398 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val)) { 399 uint64_t C2 = N2C->getValue(); 400 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) { 401 uint64_t C1 = N1C->getValue(); 402 403 // Sign extend the operands if required 404 if (ISD::isSignedIntSetCC(Cond)) { 405 C1 = N1C->getSignExtended(); 406 C2 = N2C->getSignExtended(); 407 } 408 409 switch (Cond) { 410 default: assert(0 && "Unknown integer setcc!"); 411 case ISD::SETEQ: return getConstant(C1 == C2, VT); 412 case ISD::SETNE: return getConstant(C1 != C2, VT); 413 case ISD::SETULT: return getConstant(C1 < C2, VT); 414 case ISD::SETUGT: return getConstant(C1 > C2, VT); 415 case ISD::SETULE: return getConstant(C1 <= C2, VT); 416 case ISD::SETUGE: return getConstant(C1 >= C2, VT); 417 case ISD::SETLT: return getConstant((int64_t)C1 < (int64_t)C2, VT); 418 case ISD::SETGT: return getConstant((int64_t)C1 > (int64_t)C2, VT); 419 case ISD::SETLE: return getConstant((int64_t)C1 <= (int64_t)C2, VT); 420 case ISD::SETGE: return getConstant((int64_t)C1 >= (int64_t)C2, VT); 421 } 422 } else { 423 // If the LHS is a ZERO_EXTEND and if this is an ==/!= comparison, perform 424 // the comparison on the input. 425 if (N1.getOpcode() == ISD::ZERO_EXTEND) { 426 unsigned InSize = MVT::getSizeInBits(N1.getOperand(0).getValueType()); 427 428 // If the comparison constant has bits in the upper part, the 429 // zero-extended value could never match. 430 if (C2 & (~0ULL << InSize)) { 431 unsigned VSize = MVT::getSizeInBits(N1.getValueType()); 432 switch (Cond) { 433 case ISD::SETUGT: 434 case ISD::SETUGE: 435 case ISD::SETEQ: return getConstant(0, VT); 436 case ISD::SETULT: 437 case ISD::SETULE: 438 case ISD::SETNE: return getConstant(1, VT); 439 case ISD::SETGT: 440 case ISD::SETGE: 441 // True if the sign bit of C2 is set. 442 return getConstant((C2 & (1ULL << VSize)) != 0, VT); 443 case ISD::SETLT: 444 case ISD::SETLE: 445 // True if the sign bit of C2 isn't set. 446 return getConstant((C2 & (1ULL << VSize)) == 0, VT); 447 default: 448 break; 449 } 450 } 451 452 // Otherwise, we can perform the comparison with the low bits. 453 switch (Cond) { 454 case ISD::SETEQ: 455 case ISD::SETNE: 456 case ISD::SETUGT: 457 case ISD::SETUGE: 458 case ISD::SETULT: 459 case ISD::SETULE: 460 return getSetCC(VT, N1.getOperand(0), 461 getConstant(C2, N1.getOperand(0).getValueType()), 462 Cond); 463 default: 464 break; // todo, be more careful with signed comparisons 465 } 466 } 467 468 uint64_t MinVal, MaxVal; 469 unsigned OperandBitSize = MVT::getSizeInBits(N2C->getValueType(0)); 470 if (ISD::isSignedIntSetCC(Cond)) { 471 MinVal = 1ULL << (OperandBitSize-1); 472 if (OperandBitSize != 1) // Avoid X >> 64, which is undefined. 473 MaxVal = ~0ULL >> (65-OperandBitSize); 474 else 475 MaxVal = 0; 476 } else { 477 MinVal = 0; 478 MaxVal = ~0ULL >> (64-OperandBitSize); 479 } 480 481 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 482 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 483 if (C2 == MinVal) return getConstant(1, VT); // X >= MIN --> true 484 --C2; // X >= C1 --> X > (C1-1) 485 Cond = (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT; 486 N2 = getConstant(C2, N2.getValueType()); 487 N2C = cast<ConstantSDNode>(N2.Val); 488 } 489 490 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 491 if (C2 == MaxVal) return getConstant(1, VT); // X <= MAX --> true 492 ++C2; // X <= C1 --> X < (C1+1) 493 Cond = (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT; 494 N2 = getConstant(C2, N2.getValueType()); 495 N2C = cast<ConstantSDNode>(N2.Val); 496 } 497 498 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C2 == MinVal) 499 return getConstant(0, VT); // X < MIN --> false 500 501 // Canonicalize setgt X, Min --> setne X, Min 502 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C2 == MinVal) 503 return getSetCC(VT, N1, N2, ISD::SETNE); 504 505 // If we have setult X, 1, turn it into seteq X, 0 506 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C2 == MinVal+1) 507 return getSetCC(VT, N1, getConstant(MinVal, N1.getValueType()), 508 ISD::SETEQ); 509 // If we have setugt X, Max-1, turn it into seteq X, Max 510 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C2 == MaxVal-1) 511 return getSetCC(VT, N1, getConstant(MaxVal, N1.getValueType()), 512 ISD::SETEQ); 513 514 // If we have "setcc X, C1", check to see if we can shrink the immediate 515 // by changing cc. 516 517 // SETUGT X, SINTMAX -> SETLT X, 0 518 if (Cond == ISD::SETUGT && OperandBitSize != 1 && 519 C2 == (~0ULL >> (65-OperandBitSize))) 520 return getSetCC(VT, N1, getConstant(0, N2.getValueType()), ISD::SETLT); 521 522 // FIXME: Implement the rest of these. 523 524 525 // Fold bit comparisons when we can. 526 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 527 VT == N1.getValueType() && N1.getOpcode() == ISD::AND) 528 if (ConstantSDNode *AndRHS = 529 dyn_cast<ConstantSDNode>(N1.getOperand(1))) { 530 if (Cond == ISD::SETNE && C2 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 531 // Perform the xform if the AND RHS is a single bit. 532 if ((AndRHS->getValue() & (AndRHS->getValue()-1)) == 0) { 533 return getNode(ISD::SRL, VT, N1, 534 getConstant(Log2_64(AndRHS->getValue()), 535 TLI.getShiftAmountTy())); 536 } 537 } else if (Cond == ISD::SETEQ && C2 == AndRHS->getValue()) { 538 // (X & 8) == 8 --> (X & 8) >> 3 539 // Perform the xform if C2 is a single bit. 540 if ((C2 & (C2-1)) == 0) { 541 return getNode(ISD::SRL, VT, N1, 542 getConstant(Log2_64(C2),TLI.getShiftAmountTy())); 543 } 544 } 545 } 546 } 547 } else if (isa<ConstantSDNode>(N1.Val)) { 548 // Ensure that the constant occurs on the RHS. 549 return getSetCC(VT, N2, N1, ISD::getSetCCSwappedOperands(Cond)); 550 } 551 552 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.Val)) 553 if (ConstantFPSDNode *N2C = dyn_cast<ConstantFPSDNode>(N2.Val)) { 554 double C1 = N1C->getValue(), C2 = N2C->getValue(); 555 556 switch (Cond) { 557 default: break; // FIXME: Implement the rest of these! 558 case ISD::SETEQ: return getConstant(C1 == C2, VT); 559 case ISD::SETNE: return getConstant(C1 != C2, VT); 560 case ISD::SETLT: return getConstant(C1 < C2, VT); 561 case ISD::SETGT: return getConstant(C1 > C2, VT); 562 case ISD::SETLE: return getConstant(C1 <= C2, VT); 563 case ISD::SETGE: return getConstant(C1 >= C2, VT); 564 } 565 } else { 566 // Ensure that the constant occurs on the RHS. 567 Cond = ISD::getSetCCSwappedOperands(Cond); 568 std::swap(N1, N2); 569 } 570 571 if (N1 == N2) { 572 // We can always fold X == Y for integer setcc's. 573 if (MVT::isInteger(N1.getValueType())) 574 return getConstant(ISD::isTrueWhenEqual(Cond), VT); 575 unsigned UOF = ISD::getUnorderedFlavor(Cond); 576 if (UOF == 2) // FP operators that are undefined on NaNs. 577 return getConstant(ISD::isTrueWhenEqual(Cond), VT); 578 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 579 return getConstant(UOF, VT); 580 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 581 // if it is not already. 582 Cond = UOF == 0 ? ISD::SETUO : ISD::SETO; 583 } 584 585 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 586 MVT::isInteger(N1.getValueType())) { 587 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 588 N1.getOpcode() == ISD::XOR) { 589 // Simplify (X+Y) == (X+Z) --> Y == Z 590 if (N1.getOpcode() == N2.getOpcode()) { 591 if (N1.getOperand(0) == N2.getOperand(0)) 592 return getSetCC(VT, N1.getOperand(1), N2.getOperand(1), Cond); 593 if (N1.getOperand(1) == N2.getOperand(1)) 594 return getSetCC(VT, N1.getOperand(0), N2.getOperand(0), Cond); 595 if (isCommutativeBinOp(N1.getOpcode())) { 596 // If X op Y == Y op X, try other combinations. 597 if (N1.getOperand(0) == N2.getOperand(1)) 598 return getSetCC(VT, N1.getOperand(1), N2.getOperand(0), Cond); 599 if (N1.getOperand(1) == N2.getOperand(0)) 600 return getSetCC(VT, N1.getOperand(1), N2.getOperand(1), Cond); 601 } 602 } 603 604 // FIXME: move this stuff to the DAG Combiner when it exists! 605 606 // Simplify (X+Z) == X --> Z == 0 607 if (N1.getOperand(0) == N2) 608 return getSetCC(VT, N1.getOperand(1), 609 getConstant(0, N1.getValueType()), Cond); 610 if (N1.getOperand(1) == N2) { 611 if (isCommutativeBinOp(N1.getOpcode())) 612 return getSetCC(VT, N1.getOperand(0), 613 getConstant(0, N1.getValueType()), Cond); 614 else { 615 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 616 // (Z-X) == X --> Z == X<<1 617 return getSetCC(VT, N1.getOperand(0), 618 getNode(ISD::SHL, N2.getValueType(), 619 N2, getConstant(1, TLI.getShiftAmountTy())), 620 Cond); 621 } 622 } 623 } 624 625 if (N2.getOpcode() == ISD::ADD || N2.getOpcode() == ISD::SUB || 626 N2.getOpcode() == ISD::XOR) { 627 // Simplify X == (X+Z) --> Z == 0 628 if (N2.getOperand(0) == N1) 629 return getSetCC(VT, N2.getOperand(1), 630 getConstant(0, N2.getValueType()), Cond); 631 else if (N2.getOperand(1) == N1) 632 return getSetCC(VT, N2.getOperand(0), getConstant(0, N2.getValueType()), 633 Cond); 634 } 635 } 636 637 // Fold away ALL boolean setcc's. 638 if (N1.getValueType() == MVT::i1) { 639 switch (Cond) { 640 default: assert(0 && "Unknown integer setcc!"); 641 case ISD::SETEQ: // X == Y -> (X^Y)^1 642 N1 = getNode(ISD::XOR, MVT::i1, 643 getNode(ISD::XOR, MVT::i1, N1, N2), 644 getConstant(1, MVT::i1)); 645 break; 646 case ISD::SETNE: // X != Y --> (X^Y) 647 N1 = getNode(ISD::XOR, MVT::i1, N1, N2); 648 break; 649 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y 650 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y 651 N1 = getNode(ISD::AND, MVT::i1, N2, 652 getNode(ISD::XOR, MVT::i1, N1, getConstant(1, MVT::i1))); 653 break; 654 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X 655 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X 656 N1 = getNode(ISD::AND, MVT::i1, N1, 657 getNode(ISD::XOR, MVT::i1, N2, getConstant(1, MVT::i1))); 658 break; 659 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y 660 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y 661 N1 = getNode(ISD::OR, MVT::i1, N2, 662 getNode(ISD::XOR, MVT::i1, N1, getConstant(1, MVT::i1))); 663 break; 664 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X 665 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X 666 N1 = getNode(ISD::OR, MVT::i1, N1, 667 getNode(ISD::XOR, MVT::i1, N2, getConstant(1, MVT::i1))); 668 break; 669 } 670 if (VT != MVT::i1) 671 N1 = getNode(ISD::ZERO_EXTEND, VT, N1); 672 return N1; 673 } 674 675 // Could not fold it. 676 return SDOperand(); 677} 678 679 680 681/// getNode - Gets or creates the specified node. 682/// 683SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT) { 684 SDNode *N = new SDNode(Opcode, VT); 685 AllNodes.push_back(N); 686 return SDOperand(N, 0); 687} 688 689SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, 690 SDOperand Operand) { 691 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Operand.Val)) { 692 uint64_t Val = C->getValue(); 693 switch (Opcode) { 694 default: break; 695 case ISD::SIGN_EXTEND: return getConstant(C->getSignExtended(), VT); 696 case ISD::ZERO_EXTEND: return getConstant(Val, VT); 697 case ISD::TRUNCATE: return getConstant(Val, VT); 698 case ISD::SINT_TO_FP: return getConstantFP(C->getSignExtended(), VT); 699 case ISD::UINT_TO_FP: return getConstantFP(C->getValue(), VT); 700 } 701 } 702 703 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Operand.Val)) 704 switch (Opcode) { 705 case ISD::FNEG: 706 return getConstantFP(-C->getValue(), VT); 707 case ISD::FP_ROUND: 708 case ISD::FP_EXTEND: 709 return getConstantFP(C->getValue(), VT); 710 case ISD::FP_TO_SINT: 711 return getConstant((int64_t)C->getValue(), VT); 712 case ISD::FP_TO_UINT: 713 return getConstant((uint64_t)C->getValue(), VT); 714 } 715 716 unsigned OpOpcode = Operand.Val->getOpcode(); 717 switch (Opcode) { 718 case ISD::TokenFactor: 719 return Operand; // Factor of one node? No factor. 720 case ISD::SIGN_EXTEND: 721 if (Operand.getValueType() == VT) return Operand; // noop extension 722 if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND) 723 return getNode(OpOpcode, VT, Operand.Val->getOperand(0)); 724 break; 725 case ISD::ZERO_EXTEND: 726 if (Operand.getValueType() == VT) return Operand; // noop extension 727 if (OpOpcode == ISD::ZERO_EXTEND) // (zext (zext x)) -> (zext x) 728 return getNode(ISD::ZERO_EXTEND, VT, Operand.Val->getOperand(0)); 729 break; 730 case ISD::TRUNCATE: 731 if (Operand.getValueType() == VT) return Operand; // noop truncate 732 if (OpOpcode == ISD::TRUNCATE) 733 return getNode(ISD::TRUNCATE, VT, Operand.Val->getOperand(0)); 734 else if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND) { 735 // If the source is smaller than the dest, we still need an extend. 736 if (Operand.Val->getOperand(0).getValueType() < VT) 737 return getNode(OpOpcode, VT, Operand.Val->getOperand(0)); 738 else if (Operand.Val->getOperand(0).getValueType() > VT) 739 return getNode(ISD::TRUNCATE, VT, Operand.Val->getOperand(0)); 740 else 741 return Operand.Val->getOperand(0); 742 } 743 break; 744 case ISD::FNEG: 745 if (OpOpcode == ISD::SUB) // -(X-Y) -> (Y-X) 746 return getNode(ISD::SUB, VT, Operand.Val->getOperand(1), 747 Operand.Val->getOperand(0)); 748 if (OpOpcode == ISD::FNEG) // --X -> X 749 return Operand.Val->getOperand(0); 750 break; 751 case ISD::FABS: 752 if (OpOpcode == ISD::FNEG) // abs(-X) -> abs(X) 753 return getNode(ISD::FABS, VT, Operand.Val->getOperand(0)); 754 break; 755 } 756 757 SDNode *&N = UnaryOps[std::make_pair(Opcode, std::make_pair(Operand, VT))]; 758 if (N) return SDOperand(N, 0); 759 N = new SDNode(Opcode, Operand); 760 N->setValueTypes(VT); 761 AllNodes.push_back(N); 762 return SDOperand(N, 0); 763} 764 765/// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero. We use 766/// this predicate to simplify operations downstream. V and Mask are known to 767/// be the same type. 768static bool MaskedValueIsZero(const SDOperand &Op, uint64_t Mask, 769 const TargetLowering &TLI) { 770 unsigned SrcBits; 771 if (Mask == 0) return true; 772 773 // If we know the result of a setcc has the top bits zero, use this info. 774 switch (Op.getOpcode()) { 775 case ISD::Constant: 776 return (cast<ConstantSDNode>(Op)->getValue() & Mask) == 0; 777 778 case ISD::SETCC: 779 return ((Mask & 1) == 0) && 780 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult; 781 782 case ISD::ZEXTLOAD: 783 SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(3))->getVT()); 784 return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits. 785 case ISD::ZERO_EXTEND: 786 SrcBits = MVT::getSizeInBits(Op.getOperand(0).getValueType()); 787 return MaskedValueIsZero(Op.getOperand(0),Mask & ((1ULL << SrcBits)-1),TLI); 788 789 case ISD::AND: 790 // (X & C1) & C2 == 0 iff C1 & C2 == 0. 791 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(Op.getOperand(1))) 792 return MaskedValueIsZero(Op.getOperand(0),AndRHS->getValue() & Mask, TLI); 793 794 // FALL THROUGH 795 case ISD::OR: 796 case ISD::XOR: 797 return MaskedValueIsZero(Op.getOperand(0), Mask, TLI) && 798 MaskedValueIsZero(Op.getOperand(1), Mask, TLI); 799 case ISD::SELECT: 800 return MaskedValueIsZero(Op.getOperand(1), Mask, TLI) && 801 MaskedValueIsZero(Op.getOperand(2), Mask, TLI); 802 803 case ISD::SRL: 804 // (ushr X, C1) & C2 == 0 iff X & (C2 << C1) == 0 805 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 806 uint64_t NewVal = Mask << ShAmt->getValue(); 807 SrcBits = MVT::getSizeInBits(Op.getValueType()); 808 if (SrcBits != 64) NewVal &= (1ULL << SrcBits)-1; 809 return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI); 810 } 811 return false; 812 case ISD::SHL: 813 // (ushl X, C1) & C2 == 0 iff X & (C2 >> C1) == 0 814 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 815 uint64_t NewVal = Mask >> ShAmt->getValue(); 816 return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI); 817 } 818 return false; 819 // TODO we could handle some SRA cases here. 820 default: break; 821 } 822 823 return false; 824} 825 826 827 828SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, 829 SDOperand N1, SDOperand N2) { 830#ifndef NDEBUG 831 switch (Opcode) { 832 case ISD::TokenFactor: 833 assert(VT == MVT::Other && N1.getValueType() == MVT::Other && 834 N2.getValueType() == MVT::Other && "Invalid token factor!"); 835 break; 836 case ISD::AND: 837 case ISD::OR: 838 case ISD::XOR: 839 case ISD::UDIV: 840 case ISD::UREM: 841 case ISD::MULHU: 842 case ISD::MULHS: 843 assert(MVT::isInteger(VT) && "This operator does not apply to FP types!"); 844 // fall through 845 case ISD::ADD: 846 case ISD::SUB: 847 case ISD::MUL: 848 case ISD::SDIV: 849 case ISD::SREM: 850 assert(N1.getValueType() == N2.getValueType() && 851 N1.getValueType() == VT && "Binary operator types must match!"); 852 break; 853 854 case ISD::SHL: 855 case ISD::SRA: 856 case ISD::SRL: 857 assert(VT == N1.getValueType() && 858 "Shift operators return type must be the same as their first arg"); 859 assert(MVT::isInteger(VT) && MVT::isInteger(N2.getValueType()) && 860 VT != MVT::i1 && "Shifts only work on integers"); 861 break; 862 case ISD::FP_ROUND_INREG: { 863 MVT::ValueType EVT = cast<VTSDNode>(N2)->getVT(); 864 assert(VT == N1.getValueType() && "Not an inreg round!"); 865 assert(MVT::isFloatingPoint(VT) && MVT::isFloatingPoint(EVT) && 866 "Cannot FP_ROUND_INREG integer types"); 867 assert(EVT <= VT && "Not rounding down!"); 868 break; 869 } 870 case ISD::SIGN_EXTEND_INREG: { 871 MVT::ValueType EVT = cast<VTSDNode>(N2)->getVT(); 872 assert(VT == N1.getValueType() && "Not an inreg extend!"); 873 assert(MVT::isInteger(VT) && MVT::isInteger(EVT) && 874 "Cannot *_EXTEND_INREG FP types"); 875 assert(EVT <= VT && "Not extending!"); 876 } 877 878 default: break; 879 } 880#endif 881 882 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 883 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 884 if (N1C) { 885 if (N2C) { 886 uint64_t C1 = N1C->getValue(), C2 = N2C->getValue(); 887 switch (Opcode) { 888 case ISD::ADD: return getConstant(C1 + C2, VT); 889 case ISD::SUB: return getConstant(C1 - C2, VT); 890 case ISD::MUL: return getConstant(C1 * C2, VT); 891 case ISD::UDIV: 892 if (C2) return getConstant(C1 / C2, VT); 893 break; 894 case ISD::UREM : 895 if (C2) return getConstant(C1 % C2, VT); 896 break; 897 case ISD::SDIV : 898 if (C2) return getConstant(N1C->getSignExtended() / 899 N2C->getSignExtended(), VT); 900 break; 901 case ISD::SREM : 902 if (C2) return getConstant(N1C->getSignExtended() % 903 N2C->getSignExtended(), VT); 904 break; 905 case ISD::AND : return getConstant(C1 & C2, VT); 906 case ISD::OR : return getConstant(C1 | C2, VT); 907 case ISD::XOR : return getConstant(C1 ^ C2, VT); 908 case ISD::SHL : return getConstant(C1 << (int)C2, VT); 909 case ISD::SRL : return getConstant(C1 >> (unsigned)C2, VT); 910 case ISD::SRA : return getConstant(N1C->getSignExtended() >>(int)C2, VT); 911 default: break; 912 } 913 914 } else { // Cannonicalize constant to RHS if commutative 915 if (isCommutativeBinOp(Opcode)) { 916 std::swap(N1C, N2C); 917 std::swap(N1, N2); 918 } 919 } 920 921 switch (Opcode) { 922 default: break; 923 case ISD::SHL: // shl 0, X -> 0 924 if (N1C->isNullValue()) return N1; 925 break; 926 case ISD::SRL: // srl 0, X -> 0 927 if (N1C->isNullValue()) return N1; 928 break; 929 case ISD::SRA: // sra -1, X -> -1 930 if (N1C->isAllOnesValue()) return N1; 931 break; 932 case ISD::SIGN_EXTEND_INREG: // SIGN_EXTEND_INREG N1C, EVT 933 // Extending a constant? Just return the extended constant. 934 SDOperand Tmp = getNode(ISD::TRUNCATE, cast<VTSDNode>(N2)->getVT(), N1); 935 return getNode(ISD::SIGN_EXTEND, VT, Tmp); 936 } 937 } 938 939 if (N2C) { 940 uint64_t C2 = N2C->getValue(); 941 942 switch (Opcode) { 943 case ISD::ADD: 944 if (!C2) return N1; // add X, 0 -> X 945 break; 946 case ISD::SUB: 947 if (!C2) return N1; // sub X, 0 -> X 948 return getNode(ISD::ADD, VT, N1, getConstant(-C2, VT)); 949 case ISD::MUL: 950 if (!C2) return N2; // mul X, 0 -> 0 951 if (N2C->isAllOnesValue()) // mul X, -1 -> 0-X 952 return getNode(ISD::SUB, VT, getConstant(0, VT), N1); 953 954 // FIXME: Move this to the DAG combiner when it exists. 955 if ((C2 & C2-1) == 0) { 956 SDOperand ShAmt = getConstant(Log2_64(C2), TLI.getShiftAmountTy()); 957 return getNode(ISD::SHL, VT, N1, ShAmt); 958 } 959 break; 960 961 case ISD::MULHU: 962 case ISD::MULHS: 963 if (!C2) return N2; // mul X, 0 -> 0 964 965 if (C2 == 1) // 0X*01 -> 0X hi(0X) == 0 966 return getConstant(0, VT); 967 968 // Many others could be handled here, including -1, powers of 2, etc. 969 break; 970 971 case ISD::UDIV: 972 // FIXME: Move this to the DAG combiner when it exists. 973 if ((C2 & C2-1) == 0 && C2) { 974 SDOperand ShAmt = getConstant(Log2_64(C2), TLI.getShiftAmountTy()); 975 return getNode(ISD::SRL, VT, N1, ShAmt); 976 } 977 break; 978 979 case ISD::SHL: 980 case ISD::SRL: 981 case ISD::SRA: 982 // If the shift amount is bigger than the size of the data, then all the 983 // bits are shifted out. Simplify to undef. 984 if (C2 >= MVT::getSizeInBits(N1.getValueType())) { 985 return getNode(ISD::UNDEF, N1.getValueType()); 986 } 987 if (C2 == 0) return N1; 988 989 if (Opcode == ISD::SHL && N1.getNumOperands() == 2) 990 if (ConstantSDNode *OpSA = dyn_cast<ConstantSDNode>(N1.getOperand(1))) { 991 unsigned OpSAC = OpSA->getValue(); 992 if (N1.getOpcode() == ISD::SHL) { 993 if (C2+OpSAC >= MVT::getSizeInBits(N1.getValueType())) 994 return getConstant(0, N1.getValueType()); 995 return getNode(ISD::SHL, N1.getValueType(), N1.getOperand(0), 996 getConstant(C2+OpSAC, N2.getValueType())); 997 } else if (N1.getOpcode() == ISD::SRL) { 998 // (X >> C1) << C2: if C2 > C1, ((X & ~0<<C1) << C2-C1) 999 SDOperand Mask = getNode(ISD::AND, VT, N1.getOperand(0), 1000 getConstant(~0ULL << OpSAC, VT)); 1001 if (C2 > OpSAC) { 1002 return getNode(ISD::SHL, VT, Mask, 1003 getConstant(C2-OpSAC, N2.getValueType())); 1004 } else { 1005 // (X >> C1) << C2: if C2 <= C1, ((X & ~0<<C1) >> C1-C2) 1006 return getNode(ISD::SRL, VT, Mask, 1007 getConstant(OpSAC-C2, N2.getValueType())); 1008 } 1009 } else if (N1.getOpcode() == ISD::SRA) { 1010 // if C1 == C2, just mask out low bits. 1011 if (C2 == OpSAC) 1012 return getNode(ISD::AND, VT, N1.getOperand(0), 1013 getConstant(~0ULL << C2, VT)); 1014 } 1015 } 1016 break; 1017 1018 case ISD::AND: 1019 if (!C2) return N2; // X and 0 -> 0 1020 if (N2C->isAllOnesValue()) 1021 return N1; // X and -1 -> X 1022 1023 if (MaskedValueIsZero(N1, C2, TLI)) // X and 0 -> 0 1024 return getConstant(0, VT); 1025 1026 { 1027 uint64_t NotC2 = ~C2; 1028 if (VT != MVT::i64) 1029 NotC2 &= (1ULL << MVT::getSizeInBits(VT))-1; 1030 1031 if (MaskedValueIsZero(N1, NotC2, TLI)) 1032 return N1; // if (X & ~C2) -> 0, the and is redundant 1033 } 1034 1035 // FIXME: Should add a corresponding version of this for 1036 // ZERO_EXTEND/SIGN_EXTEND by converting them to an ANY_EXTEND node which 1037 // we don't have yet. 1038 1039 // and (sign_extend_inreg x:16:32), 1 -> and x, 1 1040 if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) { 1041 // If we are masking out the part of our input that was extended, just 1042 // mask the input to the extension directly. 1043 unsigned ExtendBits = 1044 MVT::getSizeInBits(cast<VTSDNode>(N1.getOperand(1))->getVT()); 1045 if ((C2 & (~0ULL << ExtendBits)) == 0) 1046 return getNode(ISD::AND, VT, N1.getOperand(0), N2); 1047 } else if (N1.getOpcode() == ISD::OR) { 1048 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N1.getOperand(1))) 1049 if ((ORI->getValue() & C2) == C2) { 1050 // If the 'or' is setting all of the bits that we are masking for, 1051 // we know the result of the AND will be the AND mask itself. 1052 return N2; 1053 } 1054 } 1055 break; 1056 case ISD::OR: 1057 if (!C2)return N1; // X or 0 -> X 1058 if (N2C->isAllOnesValue()) 1059 return N2; // X or -1 -> -1 1060 break; 1061 case ISD::XOR: 1062 if (!C2) return N1; // X xor 0 -> X 1063 if (N2C->isAllOnesValue()) { 1064 if (N1.Val->getOpcode() == ISD::SETCC){ 1065 SDNode *SetCC = N1.Val; 1066 // !(X op Y) -> (X !op Y) 1067 bool isInteger = MVT::isInteger(SetCC->getOperand(0).getValueType()); 1068 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC->getOperand(2))->get(); 1069 return getSetCC(SetCC->getValueType(0), 1070 SetCC->getOperand(0), SetCC->getOperand(1), 1071 ISD::getSetCCInverse(CC, isInteger)); 1072 } else if (N1.getOpcode() == ISD::AND || N1.getOpcode() == ISD::OR) { 1073 SDNode *Op = N1.Val; 1074 // !(X or Y) -> (!X and !Y) iff X or Y are freely invertible 1075 // !(X and Y) -> (!X or !Y) iff X or Y are freely invertible 1076 SDOperand LHS = Op->getOperand(0), RHS = Op->getOperand(1); 1077 if (isInvertibleForFree(RHS) || isInvertibleForFree(LHS)) { 1078 LHS = getNode(ISD::XOR, VT, LHS, N2); // RHS = ~LHS 1079 RHS = getNode(ISD::XOR, VT, RHS, N2); // RHS = ~RHS 1080 if (Op->getOpcode() == ISD::AND) 1081 return getNode(ISD::OR, VT, LHS, RHS); 1082 return getNode(ISD::AND, VT, LHS, RHS); 1083 } 1084 } 1085 // X xor -1 -> not(x) ? 1086 } 1087 break; 1088 } 1089 1090 // Reassociate ((X op C1) op C2) if possible. 1091 if (N1.getOpcode() == Opcode && isAssociativeBinOp(Opcode)) 1092 if (ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N1.Val->getOperand(1))) 1093 return getNode(Opcode, VT, N1.Val->getOperand(0), 1094 getNode(Opcode, VT, N2, N1.Val->getOperand(1))); 1095 } 1096 1097 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1.Val); 1098 ConstantFPSDNode *N2CFP = dyn_cast<ConstantFPSDNode>(N2.Val); 1099 if (N1CFP) { 1100 if (N2CFP) { 1101 double C1 = N1CFP->getValue(), C2 = N2CFP->getValue(); 1102 switch (Opcode) { 1103 case ISD::ADD: return getConstantFP(C1 + C2, VT); 1104 case ISD::SUB: return getConstantFP(C1 - C2, VT); 1105 case ISD::MUL: return getConstantFP(C1 * C2, VT); 1106 case ISD::SDIV: 1107 if (C2) return getConstantFP(C1 / C2, VT); 1108 break; 1109 case ISD::SREM : 1110 if (C2) return getConstantFP(fmod(C1, C2), VT); 1111 break; 1112 default: break; 1113 } 1114 1115 } else { // Cannonicalize constant to RHS if commutative 1116 if (isCommutativeBinOp(Opcode)) { 1117 std::swap(N1CFP, N2CFP); 1118 std::swap(N1, N2); 1119 } 1120 } 1121 1122 if (Opcode == ISD::FP_ROUND_INREG) 1123 return getNode(ISD::FP_EXTEND, VT, 1124 getNode(ISD::FP_ROUND, cast<VTSDNode>(N2)->getVT(), N1)); 1125 } 1126 1127 // Finally, fold operations that do not require constants. 1128 switch (Opcode) { 1129 case ISD::TokenFactor: 1130 if (N1.getOpcode() == ISD::EntryToken) 1131 return N2; 1132 if (N2.getOpcode() == ISD::EntryToken) 1133 return N1; 1134 break; 1135 1136 case ISD::AND: 1137 case ISD::OR: 1138 if (N1.Val->getOpcode() == ISD::SETCC && N2.Val->getOpcode() == ISD::SETCC){ 1139 SDNode *LHS = N1.Val, *RHS = N2.Val; 1140 SDOperand LL = LHS->getOperand(0), RL = RHS->getOperand(0); 1141 SDOperand LR = LHS->getOperand(1), RR = RHS->getOperand(1); 1142 ISD::CondCode Op1 = cast<CondCodeSDNode>(LHS->getOperand(2))->get(); 1143 ISD::CondCode Op2 = cast<CondCodeSDNode>(RHS->getOperand(2))->get(); 1144 1145 if (LR == RR && isa<ConstantSDNode>(LR) && 1146 Op2 == Op1 && MVT::isInteger(LL.getValueType())) { 1147 // (X != 0) | (Y != 0) -> (X|Y != 0) 1148 // (X == 0) & (Y == 0) -> (X|Y == 0) 1149 // (X < 0) | (Y < 0) -> (X|Y < 0) 1150 if (cast<ConstantSDNode>(LR)->getValue() == 0 && 1151 ((Op2 == ISD::SETEQ && Opcode == ISD::AND) || 1152 (Op2 == ISD::SETNE && Opcode == ISD::OR) || 1153 (Op2 == ISD::SETLT && Opcode == ISD::OR))) 1154 return getSetCC(VT, getNode(ISD::OR, LR.getValueType(), LL, RL), LR, 1155 Op2); 1156 1157 if (cast<ConstantSDNode>(LR)->isAllOnesValue()) { 1158 // (X == -1) & (Y == -1) -> (X&Y == -1) 1159 // (X != -1) | (Y != -1) -> (X&Y != -1) 1160 // (X > -1) | (Y > -1) -> (X&Y > -1) 1161 if ((Opcode == ISD::AND && Op2 == ISD::SETEQ) || 1162 (Opcode == ISD::OR && Op2 == ISD::SETNE) || 1163 (Opcode == ISD::OR && Op2 == ISD::SETGT)) 1164 return getSetCC(VT, getNode(ISD::AND, LR.getValueType(), LL, RL), 1165 LR, Op2); 1166 // (X > -1) & (Y > -1) -> (X|Y > -1) 1167 if (Opcode == ISD::AND && Op2 == ISD::SETGT) 1168 return getSetCC(VT, getNode(ISD::OR, LR.getValueType(), LL, RL), 1169 LR, Op2); 1170 } 1171 } 1172 1173 // (X op1 Y) | (Y op2 X) -> (X op1 Y) | (X swapop2 Y) 1174 if (LL == RR && LR == RL) { 1175 Op2 = ISD::getSetCCSwappedOperands(Op2); 1176 goto MatchedBackwards; 1177 } 1178 1179 if (LL == RL && LR == RR) { 1180 MatchedBackwards: 1181 ISD::CondCode Result; 1182 bool isInteger = MVT::isInteger(LL.getValueType()); 1183 if (Opcode == ISD::OR) 1184 Result = ISD::getSetCCOrOperation(Op1, Op2, isInteger); 1185 else 1186 Result = ISD::getSetCCAndOperation(Op1, Op2, isInteger); 1187 1188 if (Result != ISD::SETCC_INVALID) 1189 return getSetCC(LHS->getValueType(0), LL, LR, Result); 1190 } 1191 } 1192 1193 // and/or zext(a), zext(b) -> zext(and/or a, b) 1194 if (N1.getOpcode() == ISD::ZERO_EXTEND && 1195 N2.getOpcode() == ISD::ZERO_EXTEND && 1196 N1.getOperand(0).getValueType() == N2.getOperand(0).getValueType()) 1197 return getNode(ISD::ZERO_EXTEND, VT, 1198 getNode(Opcode, N1.getOperand(0).getValueType(), 1199 N1.getOperand(0), N2.getOperand(0))); 1200 break; 1201 case ISD::XOR: 1202 if (N1 == N2) return getConstant(0, VT); // xor X, Y -> 0 1203 break; 1204 case ISD::ADD: 1205 if (N2.getOpcode() == ISD::FNEG) // (A+ (-B) -> A-B 1206 return getNode(ISD::SUB, VT, N1, N2.getOperand(0)); 1207 if (N1.getOpcode() == ISD::FNEG) // ((-A)+B) -> B-A 1208 return getNode(ISD::SUB, VT, N2, N1.getOperand(0)); 1209 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 1210 cast<ConstantSDNode>(N1.getOperand(0))->getValue() == 0) 1211 return getNode(ISD::SUB, VT, N2, N1.getOperand(1)); // (0-A)+B -> B-A 1212 if (N2.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N2.getOperand(0)) && 1213 cast<ConstantSDNode>(N2.getOperand(0))->getValue() == 0) 1214 return getNode(ISD::SUB, VT, N1, N2.getOperand(1)); // A+(0-B) -> A-B 1215 if (N2.getOpcode() == ISD::SUB && N1 == N2.Val->getOperand(1) && 1216 !MVT::isFloatingPoint(N2.getValueType())) 1217 return N2.Val->getOperand(0); // A+(B-A) -> B 1218 break; 1219 case ISD::SUB: 1220 if (N1.getOpcode() == ISD::ADD) { 1221 if (N1.Val->getOperand(0) == N2 && 1222 !MVT::isFloatingPoint(N2.getValueType())) 1223 return N1.Val->getOperand(1); // (A+B)-A == B 1224 if (N1.Val->getOperand(1) == N2 && 1225 !MVT::isFloatingPoint(N2.getValueType())) 1226 return N1.Val->getOperand(0); // (A+B)-B == A 1227 } 1228 if (N2.getOpcode() == ISD::FNEG) // (A- (-B) -> A+B 1229 return getNode(ISD::ADD, VT, N1, N2.getOperand(0)); 1230 break; 1231 case ISD::FP_ROUND_INREG: 1232 if (cast<VTSDNode>(N2)->getVT() == VT) return N1; // Not actually rounding. 1233 break; 1234 case ISD::SIGN_EXTEND_INREG: { 1235 MVT::ValueType EVT = cast<VTSDNode>(N2)->getVT(); 1236 if (EVT == VT) return N1; // Not actually extending 1237 1238 // If we are sign extending an extension, use the original source. 1239 if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) 1240 if (cast<VTSDNode>(N1.getOperand(1))->getVT() <= EVT) 1241 return N1; 1242 1243 // If we are sign extending a sextload, return just the load. 1244 if (N1.getOpcode() == ISD::SEXTLOAD) 1245 if (cast<VTSDNode>(N1.getOperand(3))->getVT() <= EVT) 1246 return N1; 1247 1248 // If we are extending the result of a setcc, and we already know the 1249 // contents of the top bits, eliminate the extension. 1250 if (N1.getOpcode() == ISD::SETCC && 1251 TLI.getSetCCResultContents() == 1252 TargetLowering::ZeroOrNegativeOneSetCCResult) 1253 return N1; 1254 1255 // If we are sign extending the result of an (and X, C) operation, and we 1256 // know the extended bits are zeros already, don't do the extend. 1257 if (N1.getOpcode() == ISD::AND) 1258 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getOperand(1))) { 1259 uint64_t Mask = N1C->getValue(); 1260 unsigned NumBits = MVT::getSizeInBits(EVT); 1261 if ((Mask & (~0ULL << (NumBits-1))) == 0) 1262 return N1; 1263 } 1264 break; 1265 } 1266 1267 // FIXME: figure out how to safely handle things like 1268 // int foo(int x) { return 1 << (x & 255); } 1269 // int bar() { return foo(256); } 1270#if 0 1271 case ISD::SHL: 1272 case ISD::SRL: 1273 case ISD::SRA: 1274 if (N2.getOpcode() == ISD::SIGN_EXTEND_INREG && 1275 cast<VTSDNode>(N2.getOperand(1))->getVT() != MVT::i1) 1276 return getNode(Opcode, VT, N1, N2.getOperand(0)); 1277 else if (N2.getOpcode() == ISD::AND) 1278 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(N2.getOperand(1))) { 1279 // If the and is only masking out bits that cannot effect the shift, 1280 // eliminate the and. 1281 unsigned NumBits = MVT::getSizeInBits(VT); 1282 if ((AndRHS->getValue() & (NumBits-1)) == NumBits-1) 1283 return getNode(Opcode, VT, N1, N2.getOperand(0)); 1284 } 1285 break; 1286#endif 1287 } 1288 1289 // Memoize this node if possible. 1290 SDNode *N; 1291 if (Opcode != ISD::CALLSEQ_START && Opcode != ISD::CALLSEQ_END) { 1292 SDNode *&BON = BinaryOps[std::make_pair(Opcode, std::make_pair(N1, N2))]; 1293 if (BON) return SDOperand(BON, 0); 1294 1295 BON = N = new SDNode(Opcode, N1, N2); 1296 } else { 1297 N = new SDNode(Opcode, N1, N2); 1298 } 1299 1300 N->setValueTypes(VT); 1301 AllNodes.push_back(N); 1302 return SDOperand(N, 0); 1303} 1304 1305// setAdjCallChain - This method changes the token chain of an 1306// CALLSEQ_START/END node to be the specified operand. 1307void SDNode::setAdjCallChain(SDOperand N) { 1308 assert(N.getValueType() == MVT::Other); 1309 assert((getOpcode() == ISD::CALLSEQ_START || 1310 getOpcode() == ISD::CALLSEQ_END) && "Cannot adjust this node!"); 1311 1312 Operands[0].Val->removeUser(this); 1313 Operands[0] = N; 1314 N.Val->Uses.push_back(this); 1315} 1316 1317 1318 1319SDOperand SelectionDAG::getLoad(MVT::ValueType VT, 1320 SDOperand Chain, SDOperand Ptr, 1321 SDOperand SV) { 1322 SDNode *&N = Loads[std::make_pair(Ptr, std::make_pair(Chain, VT))]; 1323 if (N) return SDOperand(N, 0); 1324 N = new SDNode(ISD::LOAD, Chain, Ptr, SV); 1325 1326 // Loads have a token chain. 1327 N->setValueTypes(VT, MVT::Other); 1328 AllNodes.push_back(N); 1329 return SDOperand(N, 0); 1330} 1331 1332 1333SDOperand SelectionDAG::getExtLoad(unsigned Opcode, MVT::ValueType VT, 1334 SDOperand Chain, SDOperand Ptr, SDOperand SV, 1335 MVT::ValueType EVT) { 1336 std::vector<SDOperand> Ops; 1337 Ops.reserve(4); 1338 Ops.push_back(Chain); 1339 Ops.push_back(Ptr); 1340 Ops.push_back(SV); 1341 Ops.push_back(getValueType(EVT)); 1342 std::vector<MVT::ValueType> VTs; 1343 VTs.reserve(2); 1344 VTs.push_back(VT); VTs.push_back(MVT::Other); // Add token chain. 1345 return getNode(Opcode, VTs, Ops); 1346} 1347 1348SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, 1349 SDOperand N1, SDOperand N2, SDOperand N3) { 1350 // Perform various simplifications. 1351 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1352 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 1353 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val); 1354 switch (Opcode) { 1355 case ISD::SETCC: { 1356 // Use SimplifySetCC to simplify SETCC's. 1357 SDOperand Simp = SimplfySetCC(VT, N1, N2, cast<CondCodeSDNode>(N3)->get()); 1358 if (Simp.Val) return Simp; 1359 break; 1360 } 1361 case ISD::SELECT: 1362 if (N1C) 1363 if (N1C->getValue()) 1364 return N2; // select true, X, Y -> X 1365 else 1366 return N3; // select false, X, Y -> Y 1367 1368 if (N2 == N3) return N2; // select C, X, X -> X 1369 1370 if (VT == MVT::i1) { // Boolean SELECT 1371 if (N2C) { 1372 if (N2C->getValue()) // select C, 1, X -> C | X 1373 return getNode(ISD::OR, VT, N1, N3); 1374 else // select C, 0, X -> ~C & X 1375 return getNode(ISD::AND, VT, 1376 getNode(ISD::XOR, N1.getValueType(), N1, 1377 getConstant(1, N1.getValueType())), N3); 1378 } else if (N3C) { 1379 if (N3C->getValue()) // select C, X, 1 -> ~C | X 1380 return getNode(ISD::OR, VT, 1381 getNode(ISD::XOR, N1.getValueType(), N1, 1382 getConstant(1, N1.getValueType())), N2); 1383 else // select C, X, 0 -> C & X 1384 return getNode(ISD::AND, VT, N1, N2); 1385 } 1386 1387 if (N1 == N2) // X ? X : Y --> X ? 1 : Y --> X | Y 1388 return getNode(ISD::OR, VT, N1, N3); 1389 if (N1 == N3) // X ? Y : X --> X ? Y : 0 --> X & Y 1390 return getNode(ISD::AND, VT, N1, N2); 1391 } 1392 1393 // If this is a selectcc, check to see if we can simplify the result. 1394 if (N1.Val->getOpcode() == ISD::SETCC) { 1395 SDNode *SetCC = N1.Val; 1396 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC->getOperand(2))->get(); 1397 if (ConstantFPSDNode *CFP = 1398 dyn_cast<ConstantFPSDNode>(SetCC->getOperand(1))) 1399 if (CFP->getValue() == 0.0) { // Allow either -0.0 or 0.0 1400 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 1401 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 1402 N2 == SetCC->getOperand(0) && N3.getOpcode() == ISD::FNEG && 1403 N3.getOperand(0) == N2) 1404 return getNode(ISD::FABS, VT, N2); 1405 1406 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 1407 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 1408 N3 == SetCC->getOperand(0) && N2.getOpcode() == ISD::FNEG && 1409 N2.getOperand(0) == N3) 1410 return getNode(ISD::FABS, VT, N3); 1411 } 1412 // select (setlt X, 0), A, 0 -> and (sra X, size(X)-1), A 1413 if (ConstantSDNode *CN = 1414 dyn_cast<ConstantSDNode>(SetCC->getOperand(1))) 1415 if (CN->getValue() == 0 && N3C && N3C->getValue() == 0) 1416 if (CC == ISD::SETLT) { 1417 MVT::ValueType XType = SetCC->getOperand(0).getValueType(); 1418 MVT::ValueType AType = N2.getValueType(); 1419 if (XType >= AType) { 1420 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 1421 // single-bit constant. FIXME: remove once the dag combiner 1422 // exists. 1423 if (ConstantSDNode *AC = dyn_cast<ConstantSDNode>(N2)) 1424 if ((AC->getValue() & (AC->getValue()-1)) == 0) { 1425 unsigned ShCtV = Log2_64(AC->getValue()); 1426 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1; 1427 SDOperand ShCt = getConstant(ShCtV, TLI.getShiftAmountTy()); 1428 SDOperand Shift = getNode(ISD::SRL, XType, 1429 SetCC->getOperand(0), ShCt); 1430 if (XType > AType) 1431 Shift = getNode(ISD::TRUNCATE, AType, Shift); 1432 return getNode(ISD::AND, AType, Shift, N2); 1433 } 1434 1435 1436 SDOperand Shift = getNode(ISD::SRA, XType, SetCC->getOperand(0), 1437 getConstant(MVT::getSizeInBits(XType)-1, 1438 TLI.getShiftAmountTy())); 1439 if (XType > AType) 1440 Shift = getNode(ISD::TRUNCATE, AType, Shift); 1441 return getNode(ISD::AND, AType, Shift, N2); 1442 } 1443 } 1444 } 1445 break; 1446 case ISD::BRCOND: 1447 if (N2C) 1448 if (N2C->getValue()) // Unconditional branch 1449 return getNode(ISD::BR, MVT::Other, N1, N3); 1450 else 1451 return N1; // Never-taken branch 1452 break; 1453 } 1454 1455 std::vector<SDOperand> Ops; 1456 Ops.reserve(3); 1457 Ops.push_back(N1); 1458 Ops.push_back(N2); 1459 Ops.push_back(N3); 1460 1461 // Memoize nodes. 1462 SDNode *&N = OneResultNodes[std::make_pair(Opcode, std::make_pair(VT, Ops))]; 1463 if (N) return SDOperand(N, 0); 1464 1465 N = new SDNode(Opcode, N1, N2, N3); 1466 N->setValueTypes(VT); 1467 AllNodes.push_back(N); 1468 return SDOperand(N, 0); 1469} 1470 1471SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, 1472 SDOperand N1, SDOperand N2, SDOperand N3, 1473 SDOperand N4) { 1474 std::vector<SDOperand> Ops; 1475 Ops.reserve(4); 1476 Ops.push_back(N1); 1477 Ops.push_back(N2); 1478 Ops.push_back(N3); 1479 Ops.push_back(N4); 1480 return getNode(Opcode, VT, Ops); 1481} 1482 1483SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, 1484 SDOperand N1, SDOperand N2, SDOperand N3, 1485 SDOperand N4, SDOperand N5) { 1486 std::vector<SDOperand> Ops; 1487 Ops.reserve(5); 1488 Ops.push_back(N1); 1489 Ops.push_back(N2); 1490 Ops.push_back(N3); 1491 Ops.push_back(N4); 1492 Ops.push_back(N5); 1493 return getNode(Opcode, VT, Ops); 1494} 1495 1496 1497SDOperand SelectionDAG::getSrcValue(const Value *V, int Offset) { 1498 assert((!V || isa<PointerType>(V->getType())) && 1499 "SrcValue is not a pointer?"); 1500 SDNode *&N = ValueNodes[std::make_pair(V, Offset)]; 1501 if (N) return SDOperand(N, 0); 1502 1503 N = new SrcValueSDNode(V, Offset); 1504 AllNodes.push_back(N); 1505 return SDOperand(N, 0); 1506} 1507 1508SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, 1509 std::vector<SDOperand> &Ops) { 1510 switch (Ops.size()) { 1511 case 0: return getNode(Opcode, VT); 1512 case 1: return getNode(Opcode, VT, Ops[0]); 1513 case 2: return getNode(Opcode, VT, Ops[0], Ops[1]); 1514 case 3: return getNode(Opcode, VT, Ops[0], Ops[1], Ops[2]); 1515 default: break; 1516 } 1517 1518 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Ops[1].Val); 1519 switch (Opcode) { 1520 default: break; 1521 case ISD::BRCONDTWOWAY: 1522 if (N1C) 1523 if (N1C->getValue()) // Unconditional branch to true dest. 1524 return getNode(ISD::BR, MVT::Other, Ops[0], Ops[2]); 1525 else // Unconditional branch to false dest. 1526 return getNode(ISD::BR, MVT::Other, Ops[0], Ops[3]); 1527 break; 1528 1529 case ISD::TRUNCSTORE: { 1530 assert(Ops.size() == 5 && "TRUNCSTORE takes 5 operands!"); 1531 MVT::ValueType EVT = cast<VTSDNode>(Ops[4])->getVT(); 1532#if 0 // FIXME: If the target supports EVT natively, convert to a truncate/store 1533 // If this is a truncating store of a constant, convert to the desired type 1534 // and store it instead. 1535 if (isa<Constant>(Ops[0])) { 1536 SDOperand Op = getNode(ISD::TRUNCATE, EVT, N1); 1537 if (isa<Constant>(Op)) 1538 N1 = Op; 1539 } 1540 // Also for ConstantFP? 1541#endif 1542 if (Ops[0].getValueType() == EVT) // Normal store? 1543 return getNode(ISD::STORE, VT, Ops[0], Ops[1], Ops[2], Ops[3]); 1544 assert(Ops[1].getValueType() > EVT && "Not a truncation?"); 1545 assert(MVT::isInteger(Ops[1].getValueType()) == MVT::isInteger(EVT) && 1546 "Can't do FP-INT conversion!"); 1547 break; 1548 } 1549 } 1550 1551 // Memoize nodes. 1552 SDNode *&N = OneResultNodes[std::make_pair(Opcode, std::make_pair(VT, Ops))]; 1553 if (N) return SDOperand(N, 0); 1554 N = new SDNode(Opcode, Ops); 1555 N->setValueTypes(VT); 1556 AllNodes.push_back(N); 1557 return SDOperand(N, 0); 1558} 1559 1560SDOperand SelectionDAG::getNode(unsigned Opcode, 1561 std::vector<MVT::ValueType> &ResultTys, 1562 std::vector<SDOperand> &Ops) { 1563 if (ResultTys.size() == 1) 1564 return getNode(Opcode, ResultTys[0], Ops); 1565 1566 switch (Opcode) { 1567 case ISD::EXTLOAD: 1568 case ISD::SEXTLOAD: 1569 case ISD::ZEXTLOAD: { 1570 MVT::ValueType EVT = cast<VTSDNode>(Ops[3])->getVT(); 1571 assert(Ops.size() == 4 && ResultTys.size() == 2 && "Bad *EXTLOAD!"); 1572 // If they are asking for an extending load from/to the same thing, return a 1573 // normal load. 1574 if (ResultTys[0] == EVT) 1575 return getLoad(ResultTys[0], Ops[0], Ops[1], Ops[2]); 1576 assert(EVT < ResultTys[0] && 1577 "Should only be an extending load, not truncating!"); 1578 assert((Opcode == ISD::EXTLOAD || MVT::isInteger(ResultTys[0])) && 1579 "Cannot sign/zero extend a FP load!"); 1580 assert(MVT::isInteger(ResultTys[0]) == MVT::isInteger(EVT) && 1581 "Cannot convert from FP to Int or Int -> FP!"); 1582 break; 1583 } 1584 1585 // FIXME: figure out how to safely handle things like 1586 // int foo(int x) { return 1 << (x & 255); } 1587 // int bar() { return foo(256); } 1588#if 0 1589 case ISD::SRA_PARTS: 1590 case ISD::SRL_PARTS: 1591 case ISD::SHL_PARTS: 1592 if (N3.getOpcode() == ISD::SIGN_EXTEND_INREG && 1593 cast<VTSDNode>(N3.getOperand(1))->getVT() != MVT::i1) 1594 return getNode(Opcode, VT, N1, N2, N3.getOperand(0)); 1595 else if (N3.getOpcode() == ISD::AND) 1596 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(N3.getOperand(1))) { 1597 // If the and is only masking out bits that cannot effect the shift, 1598 // eliminate the and. 1599 unsigned NumBits = MVT::getSizeInBits(VT)*2; 1600 if ((AndRHS->getValue() & (NumBits-1)) == NumBits-1) 1601 return getNode(Opcode, VT, N1, N2, N3.getOperand(0)); 1602 } 1603 break; 1604#endif 1605 } 1606 1607 // Memoize the node. 1608 SDNode *&N = ArbitraryNodes[std::make_pair(Opcode, std::make_pair(ResultTys, 1609 Ops))]; 1610 if (N) return SDOperand(N, 0); 1611 N = new SDNode(Opcode, Ops); 1612 N->setValueTypes(ResultTys); 1613 AllNodes.push_back(N); 1614 return SDOperand(N, 0); 1615} 1616 1617/// hasNUsesOfValue - Return true if there are exactly NUSES uses of the 1618/// indicated value. This method ignores uses of other values defined by this 1619/// operation. 1620bool SDNode::hasNUsesOfValue(unsigned NUses, unsigned Value) { 1621 assert(Value < getNumValues() && "Bad value!"); 1622 1623 // If there is only one value, this is easy. 1624 if (getNumValues() == 1) 1625 return use_size() == NUses; 1626 if (Uses.size() < NUses) return false; 1627 1628 SDOperand TheValue(this, Value); 1629 1630 std::set<SDNode*> UsersHandled; 1631 1632 for (std::vector<SDNode*>::iterator UI = Uses.begin(), E = Uses.end(); 1633 UI != E; ++UI) { 1634 SDNode *User = *UI; 1635 if (User->getNumOperands() == 1 || 1636 UsersHandled.insert(User).second) // First time we've seen this? 1637 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 1638 if (User->getOperand(i) == TheValue) { 1639 if (NUses == 0) 1640 return false; // too many uses 1641 --NUses; 1642 } 1643 } 1644 1645 // Found exactly the right number of uses? 1646 return NUses == 0; 1647} 1648 1649 1650const char *SDNode::getOperationName() const { 1651 switch (getOpcode()) { 1652 default: return "<<Unknown>>"; 1653 case ISD::PCMARKER: return "PCMarker"; 1654 case ISD::SRCVALUE: return "SrcValue"; 1655 case ISD::EntryToken: return "EntryToken"; 1656 case ISD::TokenFactor: return "TokenFactor"; 1657 case ISD::Constant: return "Constant"; 1658 case ISD::ConstantFP: return "ConstantFP"; 1659 case ISD::GlobalAddress: return "GlobalAddress"; 1660 case ISD::FrameIndex: return "FrameIndex"; 1661 case ISD::BasicBlock: return "BasicBlock"; 1662 case ISD::ExternalSymbol: return "ExternalSymbol"; 1663 case ISD::ConstantPool: return "ConstantPoolIndex"; 1664 case ISD::CopyToReg: return "CopyToReg"; 1665 case ISD::CopyFromReg: return "CopyFromReg"; 1666 case ISD::ImplicitDef: return "ImplicitDef"; 1667 case ISD::UNDEF: return "undef"; 1668 1669 // Unary operators 1670 case ISD::FABS: return "fabs"; 1671 case ISD::FNEG: return "fneg"; 1672 case ISD::FSQRT: return "fsqrt"; 1673 case ISD::FSIN: return "fsin"; 1674 case ISD::FCOS: return "fcos"; 1675 1676 // Binary operators 1677 case ISD::ADD: return "add"; 1678 case ISD::SUB: return "sub"; 1679 case ISD::MUL: return "mul"; 1680 case ISD::MULHU: return "mulhu"; 1681 case ISD::MULHS: return "mulhs"; 1682 case ISD::SDIV: return "sdiv"; 1683 case ISD::UDIV: return "udiv"; 1684 case ISD::SREM: return "srem"; 1685 case ISD::UREM: return "urem"; 1686 case ISD::AND: return "and"; 1687 case ISD::OR: return "or"; 1688 case ISD::XOR: return "xor"; 1689 case ISD::SHL: return "shl"; 1690 case ISD::SRA: return "sra"; 1691 case ISD::SRL: return "srl"; 1692 1693 case ISD::SETCC: return "setcc"; 1694 case ISD::SELECT: return "select"; 1695 case ISD::ADD_PARTS: return "add_parts"; 1696 case ISD::SUB_PARTS: return "sub_parts"; 1697 case ISD::SHL_PARTS: return "shl_parts"; 1698 case ISD::SRA_PARTS: return "sra_parts"; 1699 case ISD::SRL_PARTS: return "srl_parts"; 1700 1701 // Conversion operators. 1702 case ISD::SIGN_EXTEND: return "sign_extend"; 1703 case ISD::ZERO_EXTEND: return "zero_extend"; 1704 case ISD::SIGN_EXTEND_INREG: return "sign_extend_inreg"; 1705 case ISD::TRUNCATE: return "truncate"; 1706 case ISD::FP_ROUND: return "fp_round"; 1707 case ISD::FP_ROUND_INREG: return "fp_round_inreg"; 1708 case ISD::FP_EXTEND: return "fp_extend"; 1709 1710 case ISD::SINT_TO_FP: return "sint_to_fp"; 1711 case ISD::UINT_TO_FP: return "uint_to_fp"; 1712 case ISD::FP_TO_SINT: return "fp_to_sint"; 1713 case ISD::FP_TO_UINT: return "fp_to_uint"; 1714 1715 // Control flow instructions 1716 case ISD::BR: return "br"; 1717 case ISD::BRCOND: return "brcond"; 1718 case ISD::BRCONDTWOWAY: return "brcondtwoway"; 1719 case ISD::RET: return "ret"; 1720 case ISD::CALL: return "call"; 1721 case ISD::TAILCALL:return "tailcall"; 1722 case ISD::CALLSEQ_START: return "callseq_start"; 1723 case ISD::CALLSEQ_END: return "callseq_end"; 1724 1725 // Other operators 1726 case ISD::LOAD: return "load"; 1727 case ISD::STORE: return "store"; 1728 case ISD::EXTLOAD: return "extload"; 1729 case ISD::SEXTLOAD: return "sextload"; 1730 case ISD::ZEXTLOAD: return "zextload"; 1731 case ISD::TRUNCSTORE: return "truncstore"; 1732 1733 case ISD::DYNAMIC_STACKALLOC: return "dynamic_stackalloc"; 1734 case ISD::EXTRACT_ELEMENT: return "extract_element"; 1735 case ISD::BUILD_PAIR: return "build_pair"; 1736 case ISD::MEMSET: return "memset"; 1737 case ISD::MEMCPY: return "memcpy"; 1738 case ISD::MEMMOVE: return "memmove"; 1739 1740 // Bit counting 1741 case ISD::CTPOP: return "ctpop"; 1742 case ISD::CTTZ: return "cttz"; 1743 case ISD::CTLZ: return "ctlz"; 1744 1745 // IO Intrinsics 1746 case ISD::READPORT: return "readport"; 1747 case ISD::WRITEPORT: return "writeport"; 1748 case ISD::READIO: return "readio"; 1749 case ISD::WRITEIO: return "writeio"; 1750 1751 case ISD::CONDCODE: 1752 switch (cast<CondCodeSDNode>(this)->get()) { 1753 default: assert(0 && "Unknown setcc condition!"); 1754 case ISD::SETOEQ: return "setoeq"; 1755 case ISD::SETOGT: return "setogt"; 1756 case ISD::SETOGE: return "setoge"; 1757 case ISD::SETOLT: return "setolt"; 1758 case ISD::SETOLE: return "setole"; 1759 case ISD::SETONE: return "setone"; 1760 1761 case ISD::SETO: return "seto"; 1762 case ISD::SETUO: return "setuo"; 1763 case ISD::SETUEQ: return "setue"; 1764 case ISD::SETUGT: return "setugt"; 1765 case ISD::SETUGE: return "setuge"; 1766 case ISD::SETULT: return "setult"; 1767 case ISD::SETULE: return "setule"; 1768 case ISD::SETUNE: return "setune"; 1769 1770 case ISD::SETEQ: return "seteq"; 1771 case ISD::SETGT: return "setgt"; 1772 case ISD::SETGE: return "setge"; 1773 case ISD::SETLT: return "setlt"; 1774 case ISD::SETLE: return "setle"; 1775 case ISD::SETNE: return "setne"; 1776 } 1777 } 1778} 1779 1780void SDNode::dump() const { 1781 std::cerr << (void*)this << ": "; 1782 1783 for (unsigned i = 0, e = getNumValues(); i != e; ++i) { 1784 if (i) std::cerr << ","; 1785 if (getValueType(i) == MVT::Other) 1786 std::cerr << "ch"; 1787 else 1788 std::cerr << MVT::getValueTypeString(getValueType(i)); 1789 } 1790 std::cerr << " = " << getOperationName(); 1791 1792 std::cerr << " "; 1793 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1794 if (i) std::cerr << ", "; 1795 std::cerr << (void*)getOperand(i).Val; 1796 if (unsigned RN = getOperand(i).ResNo) 1797 std::cerr << ":" << RN; 1798 } 1799 1800 if (const ConstantSDNode *CSDN = dyn_cast<ConstantSDNode>(this)) { 1801 std::cerr << "<" << CSDN->getValue() << ">"; 1802 } else if (const ConstantFPSDNode *CSDN = dyn_cast<ConstantFPSDNode>(this)) { 1803 std::cerr << "<" << CSDN->getValue() << ">"; 1804 } else if (const GlobalAddressSDNode *GADN = 1805 dyn_cast<GlobalAddressSDNode>(this)) { 1806 std::cerr << "<"; 1807 WriteAsOperand(std::cerr, GADN->getGlobal()) << ">"; 1808 } else if (const FrameIndexSDNode *FIDN = dyn_cast<FrameIndexSDNode>(this)) { 1809 std::cerr << "<" << FIDN->getIndex() << ">"; 1810 } else if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(this)){ 1811 std::cerr << "<" << CP->getIndex() << ">"; 1812 } else if (const BasicBlockSDNode *BBDN = dyn_cast<BasicBlockSDNode>(this)) { 1813 std::cerr << "<"; 1814 const Value *LBB = (const Value*)BBDN->getBasicBlock()->getBasicBlock(); 1815 if (LBB) 1816 std::cerr << LBB->getName() << " "; 1817 std::cerr << (const void*)BBDN->getBasicBlock() << ">"; 1818 } else if (const RegSDNode *C2V = dyn_cast<RegSDNode>(this)) { 1819 std::cerr << "<reg #" << C2V->getReg() << ">"; 1820 } else if (const ExternalSymbolSDNode *ES = 1821 dyn_cast<ExternalSymbolSDNode>(this)) { 1822 std::cerr << "'" << ES->getSymbol() << "'"; 1823 } else if (const SrcValueSDNode *M = dyn_cast<SrcValueSDNode>(this)) { 1824 if (M->getValue()) 1825 std::cerr << "<" << M->getValue() << ":" << M->getOffset() << ">"; 1826 else 1827 std::cerr << "<null:" << M->getOffset() << ">"; 1828 } 1829} 1830 1831static void DumpNodes(SDNode *N, unsigned indent) { 1832 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1833 if (N->getOperand(i).Val->hasOneUse()) 1834 DumpNodes(N->getOperand(i).Val, indent+2); 1835 else 1836 std::cerr << "\n" << std::string(indent+2, ' ') 1837 << (void*)N->getOperand(i).Val << ": <multiple use>"; 1838 1839 1840 std::cerr << "\n" << std::string(indent, ' '); 1841 N->dump(); 1842} 1843 1844void SelectionDAG::dump() const { 1845 std::cerr << "SelectionDAG has " << AllNodes.size() << " nodes:"; 1846 std::vector<SDNode*> Nodes(AllNodes); 1847 std::sort(Nodes.begin(), Nodes.end()); 1848 1849 for (unsigned i = 0, e = Nodes.size(); i != e; ++i) { 1850 if (!Nodes[i]->hasOneUse() && Nodes[i] != getRoot().Val) 1851 DumpNodes(Nodes[i], 2); 1852 } 1853 1854 DumpNodes(getRoot().Val, 2); 1855 1856 std::cerr << "\n\n"; 1857} 1858 1859