SelectionDAG.cpp revision 9468a9b6beed640eca64274c8dcc5aed3b94450b
1//===-- SelectionDAG.cpp - Implement the SelectionDAG data structures -----===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAG class. 11// 12//===----------------------------------------------------------------------===// 13#include "llvm/CodeGen/SelectionDAG.h" 14#include "llvm/Constants.h" 15#include "llvm/Analysis/ValueTracking.h" 16#include "llvm/GlobalAlias.h" 17#include "llvm/GlobalVariable.h" 18#include "llvm/Intrinsics.h" 19#include "llvm/DerivedTypes.h" 20#include "llvm/Assembly/Writer.h" 21#include "llvm/CallingConv.h" 22#include "llvm/CodeGen/MachineBasicBlock.h" 23#include "llvm/CodeGen/MachineConstantPool.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/MachineModuleInfo.h" 26#include "llvm/CodeGen/PseudoSourceValue.h" 27#include "llvm/Target/TargetRegisterInfo.h" 28#include "llvm/Target/TargetData.h" 29#include "llvm/Target/TargetLowering.h" 30#include "llvm/Target/TargetInstrInfo.h" 31#include "llvm/Target/TargetMachine.h" 32#include "llvm/Support/MathExtras.h" 33#include "llvm/Support/raw_ostream.h" 34#include "llvm/ADT/SetVector.h" 35#include "llvm/ADT/SmallPtrSet.h" 36#include "llvm/ADT/SmallSet.h" 37#include "llvm/ADT/SmallVector.h" 38#include "llvm/ADT/StringExtras.h" 39#include <algorithm> 40#include <cmath> 41using namespace llvm; 42 43/// makeVTList - Return an instance of the SDVTList struct initialized with the 44/// specified members. 45static SDVTList makeVTList(const MVT *VTs, unsigned NumVTs) { 46 SDVTList Res = {VTs, NumVTs}; 47 return Res; 48} 49 50static const fltSemantics *MVTToAPFloatSemantics(MVT VT) { 51 switch (VT.getSimpleVT()) { 52 default: assert(0 && "Unknown FP format"); 53 case MVT::f32: return &APFloat::IEEEsingle; 54 case MVT::f64: return &APFloat::IEEEdouble; 55 case MVT::f80: return &APFloat::x87DoubleExtended; 56 case MVT::f128: return &APFloat::IEEEquad; 57 case MVT::ppcf128: return &APFloat::PPCDoubleDouble; 58 } 59} 60 61SelectionDAG::DAGUpdateListener::~DAGUpdateListener() {} 62 63//===----------------------------------------------------------------------===// 64// ConstantFPSDNode Class 65//===----------------------------------------------------------------------===// 66 67/// isExactlyValue - We don't rely on operator== working on double values, as 68/// it returns true for things that are clearly not equal, like -0.0 and 0.0. 69/// As such, this method can be used to do an exact bit-for-bit comparison of 70/// two floating point values. 71bool ConstantFPSDNode::isExactlyValue(const APFloat& V) const { 72 return getValueAPF().bitwiseIsEqual(V); 73} 74 75bool ConstantFPSDNode::isValueValidForType(MVT VT, 76 const APFloat& Val) { 77 assert(VT.isFloatingPoint() && "Can only convert between FP types"); 78 79 // PPC long double cannot be converted to any other type. 80 if (VT == MVT::ppcf128 || 81 &Val.getSemantics() == &APFloat::PPCDoubleDouble) 82 return false; 83 84 // convert modifies in place, so make a copy. 85 APFloat Val2 = APFloat(Val); 86 return Val2.convert(*MVTToAPFloatSemantics(VT), 87 APFloat::rmNearestTiesToEven) == APFloat::opOK; 88} 89 90//===----------------------------------------------------------------------===// 91// ISD Namespace 92//===----------------------------------------------------------------------===// 93 94/// isBuildVectorAllOnes - Return true if the specified node is a 95/// BUILD_VECTOR where all of the elements are ~0 or undef. 96bool ISD::isBuildVectorAllOnes(const SDNode *N) { 97 // Look through a bit convert. 98 if (N->getOpcode() == ISD::BIT_CONVERT) 99 N = N->getOperand(0).getNode(); 100 101 if (N->getOpcode() != ISD::BUILD_VECTOR) return false; 102 103 unsigned i = 0, e = N->getNumOperands(); 104 105 // Skip over all of the undef values. 106 while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF) 107 ++i; 108 109 // Do not accept an all-undef vector. 110 if (i == e) return false; 111 112 // Do not accept build_vectors that aren't all constants or which have non-~0 113 // elements. 114 SDValue NotZero = N->getOperand(i); 115 if (isa<ConstantSDNode>(NotZero)) { 116 if (!cast<ConstantSDNode>(NotZero)->isAllOnesValue()) 117 return false; 118 } else if (isa<ConstantFPSDNode>(NotZero)) { 119 if (!cast<ConstantFPSDNode>(NotZero)->getValueAPF(). 120 convertToAPInt().isAllOnesValue()) 121 return false; 122 } else 123 return false; 124 125 // Okay, we have at least one ~0 value, check to see if the rest match or are 126 // undefs. 127 for (++i; i != e; ++i) 128 if (N->getOperand(i) != NotZero && 129 N->getOperand(i).getOpcode() != ISD::UNDEF) 130 return false; 131 return true; 132} 133 134 135/// isBuildVectorAllZeros - Return true if the specified node is a 136/// BUILD_VECTOR where all of the elements are 0 or undef. 137bool ISD::isBuildVectorAllZeros(const SDNode *N) { 138 // Look through a bit convert. 139 if (N->getOpcode() == ISD::BIT_CONVERT) 140 N = N->getOperand(0).getNode(); 141 142 if (N->getOpcode() != ISD::BUILD_VECTOR) return false; 143 144 unsigned i = 0, e = N->getNumOperands(); 145 146 // Skip over all of the undef values. 147 while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF) 148 ++i; 149 150 // Do not accept an all-undef vector. 151 if (i == e) return false; 152 153 // Do not accept build_vectors that aren't all constants or which have non-~0 154 // elements. 155 SDValue Zero = N->getOperand(i); 156 if (isa<ConstantSDNode>(Zero)) { 157 if (!cast<ConstantSDNode>(Zero)->isNullValue()) 158 return false; 159 } else if (isa<ConstantFPSDNode>(Zero)) { 160 if (!cast<ConstantFPSDNode>(Zero)->getValueAPF().isPosZero()) 161 return false; 162 } else 163 return false; 164 165 // Okay, we have at least one ~0 value, check to see if the rest match or are 166 // undefs. 167 for (++i; i != e; ++i) 168 if (N->getOperand(i) != Zero && 169 N->getOperand(i).getOpcode() != ISD::UNDEF) 170 return false; 171 return true; 172} 173 174/// isScalarToVector - Return true if the specified node is a 175/// ISD::SCALAR_TO_VECTOR node or a BUILD_VECTOR node where only the low 176/// element is not an undef. 177bool ISD::isScalarToVector(const SDNode *N) { 178 if (N->getOpcode() == ISD::SCALAR_TO_VECTOR) 179 return true; 180 181 if (N->getOpcode() != ISD::BUILD_VECTOR) 182 return false; 183 if (N->getOperand(0).getOpcode() == ISD::UNDEF) 184 return false; 185 unsigned NumElems = N->getNumOperands(); 186 for (unsigned i = 1; i < NumElems; ++i) { 187 SDValue V = N->getOperand(i); 188 if (V.getOpcode() != ISD::UNDEF) 189 return false; 190 } 191 return true; 192} 193 194 195/// isDebugLabel - Return true if the specified node represents a debug 196/// label (i.e. ISD::DBG_LABEL or TargetInstrInfo::DBG_LABEL node). 197bool ISD::isDebugLabel(const SDNode *N) { 198 SDValue Zero; 199 if (N->getOpcode() == ISD::DBG_LABEL) 200 return true; 201 if (N->isMachineOpcode() && 202 N->getMachineOpcode() == TargetInstrInfo::DBG_LABEL) 203 return true; 204 return false; 205} 206 207/// getSetCCSwappedOperands - Return the operation corresponding to (Y op X) 208/// when given the operation for (X op Y). 209ISD::CondCode ISD::getSetCCSwappedOperands(ISD::CondCode Operation) { 210 // To perform this operation, we just need to swap the L and G bits of the 211 // operation. 212 unsigned OldL = (Operation >> 2) & 1; 213 unsigned OldG = (Operation >> 1) & 1; 214 return ISD::CondCode((Operation & ~6) | // Keep the N, U, E bits 215 (OldL << 1) | // New G bit 216 (OldG << 2)); // New L bit. 217} 218 219/// getSetCCInverse - Return the operation corresponding to !(X op Y), where 220/// 'op' is a valid SetCC operation. 221ISD::CondCode ISD::getSetCCInverse(ISD::CondCode Op, bool isInteger) { 222 unsigned Operation = Op; 223 if (isInteger) 224 Operation ^= 7; // Flip L, G, E bits, but not U. 225 else 226 Operation ^= 15; // Flip all of the condition bits. 227 if (Operation > ISD::SETTRUE2) 228 Operation &= ~8; // Don't let N and U bits get set. 229 return ISD::CondCode(Operation); 230} 231 232 233/// isSignedOp - For an integer comparison, return 1 if the comparison is a 234/// signed operation and 2 if the result is an unsigned comparison. Return zero 235/// if the operation does not depend on the sign of the input (setne and seteq). 236static int isSignedOp(ISD::CondCode Opcode) { 237 switch (Opcode) { 238 default: assert(0 && "Illegal integer setcc operation!"); 239 case ISD::SETEQ: 240 case ISD::SETNE: return 0; 241 case ISD::SETLT: 242 case ISD::SETLE: 243 case ISD::SETGT: 244 case ISD::SETGE: return 1; 245 case ISD::SETULT: 246 case ISD::SETULE: 247 case ISD::SETUGT: 248 case ISD::SETUGE: return 2; 249 } 250} 251 252/// getSetCCOrOperation - Return the result of a logical OR between different 253/// comparisons of identical values: ((X op1 Y) | (X op2 Y)). This function 254/// returns SETCC_INVALID if it is not possible to represent the resultant 255/// comparison. 256ISD::CondCode ISD::getSetCCOrOperation(ISD::CondCode Op1, ISD::CondCode Op2, 257 bool isInteger) { 258 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 259 // Cannot fold a signed integer setcc with an unsigned integer setcc. 260 return ISD::SETCC_INVALID; 261 262 unsigned Op = Op1 | Op2; // Combine all of the condition bits. 263 264 // If the N and U bits get set then the resultant comparison DOES suddenly 265 // care about orderedness, and is true when ordered. 266 if (Op > ISD::SETTRUE2) 267 Op &= ~16; // Clear the U bit if the N bit is set. 268 269 // Canonicalize illegal integer setcc's. 270 if (isInteger && Op == ISD::SETUNE) // e.g. SETUGT | SETULT 271 Op = ISD::SETNE; 272 273 return ISD::CondCode(Op); 274} 275 276/// getSetCCAndOperation - Return the result of a logical AND between different 277/// comparisons of identical values: ((X op1 Y) & (X op2 Y)). This 278/// function returns zero if it is not possible to represent the resultant 279/// comparison. 280ISD::CondCode ISD::getSetCCAndOperation(ISD::CondCode Op1, ISD::CondCode Op2, 281 bool isInteger) { 282 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 283 // Cannot fold a signed setcc with an unsigned setcc. 284 return ISD::SETCC_INVALID; 285 286 // Combine all of the condition bits. 287 ISD::CondCode Result = ISD::CondCode(Op1 & Op2); 288 289 // Canonicalize illegal integer setcc's. 290 if (isInteger) { 291 switch (Result) { 292 default: break; 293 case ISD::SETUO : Result = ISD::SETFALSE; break; // SETUGT & SETULT 294 case ISD::SETOEQ: // SETEQ & SETU[LG]E 295 case ISD::SETUEQ: Result = ISD::SETEQ ; break; // SETUGE & SETULE 296 case ISD::SETOLT: Result = ISD::SETULT ; break; // SETULT & SETNE 297 case ISD::SETOGT: Result = ISD::SETUGT ; break; // SETUGT & SETNE 298 } 299 } 300 301 return Result; 302} 303 304const TargetMachine &SelectionDAG::getTarget() const { 305 return MF->getTarget(); 306} 307 308//===----------------------------------------------------------------------===// 309// SDNode Profile Support 310//===----------------------------------------------------------------------===// 311 312/// AddNodeIDOpcode - Add the node opcode to the NodeID data. 313/// 314static void AddNodeIDOpcode(FoldingSetNodeID &ID, unsigned OpC) { 315 ID.AddInteger(OpC); 316} 317 318/// AddNodeIDValueTypes - Value type lists are intern'd so we can represent them 319/// solely with their pointer. 320static void AddNodeIDValueTypes(FoldingSetNodeID &ID, SDVTList VTList) { 321 ID.AddPointer(VTList.VTs); 322} 323 324/// AddNodeIDOperands - Various routines for adding operands to the NodeID data. 325/// 326static void AddNodeIDOperands(FoldingSetNodeID &ID, 327 const SDValue *Ops, unsigned NumOps) { 328 for (; NumOps; --NumOps, ++Ops) { 329 ID.AddPointer(Ops->getNode()); 330 ID.AddInteger(Ops->getResNo()); 331 } 332} 333 334/// AddNodeIDOperands - Various routines for adding operands to the NodeID data. 335/// 336static void AddNodeIDOperands(FoldingSetNodeID &ID, 337 const SDUse *Ops, unsigned NumOps) { 338 for (; NumOps; --NumOps, ++Ops) { 339 ID.AddPointer(Ops->getVal()); 340 ID.AddInteger(Ops->getSDValue().getResNo()); 341 } 342} 343 344static void AddNodeIDNode(FoldingSetNodeID &ID, 345 unsigned short OpC, SDVTList VTList, 346 const SDValue *OpList, unsigned N) { 347 AddNodeIDOpcode(ID, OpC); 348 AddNodeIDValueTypes(ID, VTList); 349 AddNodeIDOperands(ID, OpList, N); 350} 351 352 353/// AddNodeIDNode - Generic routine for adding a nodes info to the NodeID 354/// data. 355static void AddNodeIDNode(FoldingSetNodeID &ID, const SDNode *N) { 356 AddNodeIDOpcode(ID, N->getOpcode()); 357 // Add the return value info. 358 AddNodeIDValueTypes(ID, N->getVTList()); 359 // Add the operand info. 360 AddNodeIDOperands(ID, N->op_begin(), N->getNumOperands()); 361 362 // Handle SDNode leafs with special info. 363 switch (N->getOpcode()) { 364 default: break; // Normal nodes don't need extra info. 365 case ISD::ARG_FLAGS: 366 ID.AddInteger(cast<ARG_FLAGSSDNode>(N)->getArgFlags().getRawBits()); 367 break; 368 case ISD::TargetConstant: 369 case ISD::Constant: 370 ID.AddPointer(cast<ConstantSDNode>(N)->getConstantIntValue()); 371 break; 372 case ISD::TargetConstantFP: 373 case ISD::ConstantFP: { 374 ID.AddPointer(cast<ConstantFPSDNode>(N)->getConstantFPValue()); 375 break; 376 } 377 case ISD::TargetGlobalAddress: 378 case ISD::GlobalAddress: 379 case ISD::TargetGlobalTLSAddress: 380 case ISD::GlobalTLSAddress: { 381 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(N); 382 ID.AddPointer(GA->getGlobal()); 383 ID.AddInteger(GA->getOffset()); 384 break; 385 } 386 case ISD::BasicBlock: 387 ID.AddPointer(cast<BasicBlockSDNode>(N)->getBasicBlock()); 388 break; 389 case ISD::Register: 390 ID.AddInteger(cast<RegisterSDNode>(N)->getReg()); 391 break; 392 case ISD::DBG_STOPPOINT: { 393 const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(N); 394 ID.AddInteger(DSP->getLine()); 395 ID.AddInteger(DSP->getColumn()); 396 ID.AddPointer(DSP->getCompileUnit()); 397 break; 398 } 399 case ISD::SRCVALUE: 400 ID.AddPointer(cast<SrcValueSDNode>(N)->getValue()); 401 break; 402 case ISD::MEMOPERAND: { 403 const MachineMemOperand &MO = cast<MemOperandSDNode>(N)->MO; 404 MO.Profile(ID); 405 break; 406 } 407 case ISD::FrameIndex: 408 case ISD::TargetFrameIndex: 409 ID.AddInteger(cast<FrameIndexSDNode>(N)->getIndex()); 410 break; 411 case ISD::JumpTable: 412 case ISD::TargetJumpTable: 413 ID.AddInteger(cast<JumpTableSDNode>(N)->getIndex()); 414 break; 415 case ISD::ConstantPool: 416 case ISD::TargetConstantPool: { 417 const ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(N); 418 ID.AddInteger(CP->getAlignment()); 419 ID.AddInteger(CP->getOffset()); 420 if (CP->isMachineConstantPoolEntry()) 421 CP->getMachineCPVal()->AddSelectionDAGCSEId(ID); 422 else 423 ID.AddPointer(CP->getConstVal()); 424 break; 425 } 426 case ISD::CALL: { 427 const CallSDNode *Call = cast<CallSDNode>(N); 428 ID.AddInteger(Call->getCallingConv()); 429 ID.AddInteger(Call->isVarArg()); 430 break; 431 } 432 case ISD::LOAD: { 433 const LoadSDNode *LD = cast<LoadSDNode>(N); 434 ID.AddInteger(LD->getAddressingMode()); 435 ID.AddInteger(LD->getExtensionType()); 436 ID.AddInteger(LD->getMemoryVT().getRawBits()); 437 ID.AddInteger(LD->getRawFlags()); 438 break; 439 } 440 case ISD::STORE: { 441 const StoreSDNode *ST = cast<StoreSDNode>(N); 442 ID.AddInteger(ST->getAddressingMode()); 443 ID.AddInteger(ST->isTruncatingStore()); 444 ID.AddInteger(ST->getMemoryVT().getRawBits()); 445 ID.AddInteger(ST->getRawFlags()); 446 break; 447 } 448 case ISD::ATOMIC_CMP_SWAP_8: 449 case ISD::ATOMIC_SWAP_8: 450 case ISD::ATOMIC_LOAD_ADD_8: 451 case ISD::ATOMIC_LOAD_SUB_8: 452 case ISD::ATOMIC_LOAD_AND_8: 453 case ISD::ATOMIC_LOAD_OR_8: 454 case ISD::ATOMIC_LOAD_XOR_8: 455 case ISD::ATOMIC_LOAD_NAND_8: 456 case ISD::ATOMIC_LOAD_MIN_8: 457 case ISD::ATOMIC_LOAD_MAX_8: 458 case ISD::ATOMIC_LOAD_UMIN_8: 459 case ISD::ATOMIC_LOAD_UMAX_8: 460 case ISD::ATOMIC_CMP_SWAP_16: 461 case ISD::ATOMIC_SWAP_16: 462 case ISD::ATOMIC_LOAD_ADD_16: 463 case ISD::ATOMIC_LOAD_SUB_16: 464 case ISD::ATOMIC_LOAD_AND_16: 465 case ISD::ATOMIC_LOAD_OR_16: 466 case ISD::ATOMIC_LOAD_XOR_16: 467 case ISD::ATOMIC_LOAD_NAND_16: 468 case ISD::ATOMIC_LOAD_MIN_16: 469 case ISD::ATOMIC_LOAD_MAX_16: 470 case ISD::ATOMIC_LOAD_UMIN_16: 471 case ISD::ATOMIC_LOAD_UMAX_16: 472 case ISD::ATOMIC_CMP_SWAP_32: 473 case ISD::ATOMIC_SWAP_32: 474 case ISD::ATOMIC_LOAD_ADD_32: 475 case ISD::ATOMIC_LOAD_SUB_32: 476 case ISD::ATOMIC_LOAD_AND_32: 477 case ISD::ATOMIC_LOAD_OR_32: 478 case ISD::ATOMIC_LOAD_XOR_32: 479 case ISD::ATOMIC_LOAD_NAND_32: 480 case ISD::ATOMIC_LOAD_MIN_32: 481 case ISD::ATOMIC_LOAD_MAX_32: 482 case ISD::ATOMIC_LOAD_UMIN_32: 483 case ISD::ATOMIC_LOAD_UMAX_32: 484 case ISD::ATOMIC_CMP_SWAP_64: 485 case ISD::ATOMIC_SWAP_64: 486 case ISD::ATOMIC_LOAD_ADD_64: 487 case ISD::ATOMIC_LOAD_SUB_64: 488 case ISD::ATOMIC_LOAD_AND_64: 489 case ISD::ATOMIC_LOAD_OR_64: 490 case ISD::ATOMIC_LOAD_XOR_64: 491 case ISD::ATOMIC_LOAD_NAND_64: 492 case ISD::ATOMIC_LOAD_MIN_64: 493 case ISD::ATOMIC_LOAD_MAX_64: 494 case ISD::ATOMIC_LOAD_UMIN_64: 495 case ISD::ATOMIC_LOAD_UMAX_64: { 496 const AtomicSDNode *AT = cast<AtomicSDNode>(N); 497 ID.AddInteger(AT->getRawFlags()); 498 break; 499 } 500 } // end switch (N->getOpcode()) 501} 502 503/// encodeMemSDNodeFlags - Generic routine for computing a value for use in 504/// the CSE map that carries both alignment and volatility information. 505/// 506static unsigned encodeMemSDNodeFlags(bool isVolatile, unsigned Alignment) { 507 return isVolatile | ((Log2_32(Alignment) + 1) << 1); 508} 509 510//===----------------------------------------------------------------------===// 511// SelectionDAG Class 512//===----------------------------------------------------------------------===// 513 514/// RemoveDeadNodes - This method deletes all unreachable nodes in the 515/// SelectionDAG. 516void SelectionDAG::RemoveDeadNodes() { 517 // Create a dummy node (which is not added to allnodes), that adds a reference 518 // to the root node, preventing it from being deleted. 519 HandleSDNode Dummy(getRoot()); 520 521 SmallVector<SDNode*, 128> DeadNodes; 522 523 // Add all obviously-dead nodes to the DeadNodes worklist. 524 for (allnodes_iterator I = allnodes_begin(), E = allnodes_end(); I != E; ++I) 525 if (I->use_empty()) 526 DeadNodes.push_back(I); 527 528 RemoveDeadNodes(DeadNodes); 529 530 // If the root changed (e.g. it was a dead load, update the root). 531 setRoot(Dummy.getValue()); 532} 533 534/// RemoveDeadNodes - This method deletes the unreachable nodes in the 535/// given list, and any nodes that become unreachable as a result. 536void SelectionDAG::RemoveDeadNodes(SmallVectorImpl<SDNode *> &DeadNodes, 537 DAGUpdateListener *UpdateListener) { 538 539 // Process the worklist, deleting the nodes and adding their uses to the 540 // worklist. 541 while (!DeadNodes.empty()) { 542 SDNode *N = DeadNodes.back(); 543 DeadNodes.pop_back(); 544 545 if (UpdateListener) 546 UpdateListener->NodeDeleted(N, 0); 547 548 // Take the node out of the appropriate CSE map. 549 RemoveNodeFromCSEMaps(N); 550 551 // Next, brutally remove the operand list. This is safe to do, as there are 552 // no cycles in the graph. 553 for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ++I) { 554 SDNode *Operand = I->getVal(); 555 Operand->removeUser(std::distance(N->op_begin(), I), N); 556 557 // Now that we removed this operand, see if there are no uses of it left. 558 if (Operand->use_empty()) 559 DeadNodes.push_back(Operand); 560 } 561 if (N->OperandsNeedDelete) { 562 delete[] N->OperandList; 563 } 564 N->OperandList = 0; 565 N->NumOperands = 0; 566 567 // Finally, remove N itself. 568 NodeAllocator.Deallocate(AllNodes.remove(N)); 569 } 570} 571 572void SelectionDAG::RemoveDeadNode(SDNode *N, DAGUpdateListener *UpdateListener){ 573 SmallVector<SDNode*, 16> DeadNodes(1, N); 574 RemoveDeadNodes(DeadNodes, UpdateListener); 575} 576 577void SelectionDAG::DeleteNode(SDNode *N) { 578 assert(N->use_empty() && "Cannot delete a node that is not dead!"); 579 580 // First take this out of the appropriate CSE map. 581 RemoveNodeFromCSEMaps(N); 582 583 // Finally, remove uses due to operands of this node, remove from the 584 // AllNodes list, and delete the node. 585 DeleteNodeNotInCSEMaps(N); 586} 587 588void SelectionDAG::DeleteNodeNotInCSEMaps(SDNode *N) { 589 590 // Drop all of the operands and decrement used nodes use counts. 591 for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ++I) 592 I->getVal()->removeUser(std::distance(N->op_begin(), I), N); 593 if (N->OperandsNeedDelete) 594 delete[] N->OperandList; 595 596 assert(N != AllNodes.begin()); 597 NodeAllocator.Deallocate(AllNodes.remove(N)); 598} 599 600/// RemoveNodeFromCSEMaps - Take the specified node out of the CSE map that 601/// correspond to it. This is useful when we're about to delete or repurpose 602/// the node. We don't want future request for structurally identical nodes 603/// to return N anymore. 604bool SelectionDAG::RemoveNodeFromCSEMaps(SDNode *N) { 605 bool Erased = false; 606 switch (N->getOpcode()) { 607 case ISD::EntryToken: 608 assert(0 && "EntryToken should not be in CSEMaps!"); 609 return false; 610 case ISD::HANDLENODE: return false; // noop. 611 case ISD::CONDCODE: 612 assert(CondCodeNodes[cast<CondCodeSDNode>(N)->get()] && 613 "Cond code doesn't exist!"); 614 Erased = CondCodeNodes[cast<CondCodeSDNode>(N)->get()] != 0; 615 CondCodeNodes[cast<CondCodeSDNode>(N)->get()] = 0; 616 break; 617 case ISD::Symbol: 618 Erased = Symbols.erase(cast<SymbolSDNode>(N)->getSymbol()); 619 break; 620 case ISD::TargetSymbol: 621 Erased = TargetSymbols.erase(cast<SymbolSDNode>(N)->getSymbol()); 622 break; 623 case ISD::VALUETYPE: { 624 MVT VT = cast<VTSDNode>(N)->getVT(); 625 if (VT.isExtended()) { 626 Erased = ExtendedValueTypeNodes.erase(VT); 627 } else { 628 Erased = ValueTypeNodes[VT.getSimpleVT()] != 0; 629 ValueTypeNodes[VT.getSimpleVT()] = 0; 630 } 631 break; 632 } 633 default: 634 // Remove it from the CSE Map. 635 Erased = CSEMap.RemoveNode(N); 636 break; 637 } 638#ifndef NDEBUG 639 // Verify that the node was actually in one of the CSE maps, unless it has a 640 // flag result (which cannot be CSE'd) or is one of the special cases that are 641 // not subject to CSE. 642 if (!Erased && N->getValueType(N->getNumValues()-1) != MVT::Flag && 643 !N->isMachineOpcode() && 644 N->getOpcode() != ISD::DBG_LABEL && 645 N->getOpcode() != ISD::DBG_STOPPOINT && 646 N->getOpcode() != ISD::EH_LABEL && 647 N->getOpcode() != ISD::DECLARE) { 648 N->dump(this); 649 cerr << "\n"; 650 assert(0 && "Node is not in map!"); 651 } 652#endif 653 return Erased; 654} 655 656/// AddNonLeafNodeToCSEMaps - Add the specified node back to the CSE maps. It 657/// has been taken out and modified in some way. If the specified node already 658/// exists in the CSE maps, do not modify the maps, but return the existing node 659/// instead. If it doesn't exist, add it and return null. 660/// 661SDNode *SelectionDAG::AddNonLeafNodeToCSEMaps(SDNode *N) { 662 assert(N->getNumOperands() && "This is a leaf node!"); 663 664 if (N->getValueType(0) == MVT::Flag) 665 return 0; // Never CSE anything that produces a flag. 666 667 switch (N->getOpcode()) { 668 default: break; 669 case ISD::HANDLENODE: 670 case ISD::DBG_LABEL: 671 case ISD::DBG_STOPPOINT: 672 case ISD::EH_LABEL: 673 case ISD::DECLARE: 674 return 0; // Never add these nodes. 675 } 676 677 // Check that remaining values produced are not flags. 678 for (unsigned i = 1, e = N->getNumValues(); i != e; ++i) 679 if (N->getValueType(i) == MVT::Flag) 680 return 0; // Never CSE anything that produces a flag. 681 682 SDNode *New = CSEMap.GetOrInsertNode(N); 683 if (New != N) return New; // Node already existed. 684 return 0; 685} 686 687/// FindModifiedNodeSlot - Find a slot for the specified node if its operands 688/// were replaced with those specified. If this node is never memoized, 689/// return null, otherwise return a pointer to the slot it would take. If a 690/// node already exists with these operands, the slot will be non-null. 691SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, SDValue Op, 692 void *&InsertPos) { 693 if (N->getValueType(0) == MVT::Flag) 694 return 0; // Never CSE anything that produces a flag. 695 696 switch (N->getOpcode()) { 697 default: break; 698 case ISD::HANDLENODE: 699 case ISD::DBG_LABEL: 700 case ISD::DBG_STOPPOINT: 701 case ISD::EH_LABEL: 702 return 0; // Never add these nodes. 703 } 704 705 // Check that remaining values produced are not flags. 706 for (unsigned i = 1, e = N->getNumValues(); i != e; ++i) 707 if (N->getValueType(i) == MVT::Flag) 708 return 0; // Never CSE anything that produces a flag. 709 710 SDValue Ops[] = { Op }; 711 FoldingSetNodeID ID; 712 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, 1); 713 return CSEMap.FindNodeOrInsertPos(ID, InsertPos); 714} 715 716/// FindModifiedNodeSlot - Find a slot for the specified node if its operands 717/// were replaced with those specified. If this node is never memoized, 718/// return null, otherwise return a pointer to the slot it would take. If a 719/// node already exists with these operands, the slot will be non-null. 720SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, 721 SDValue Op1, SDValue Op2, 722 void *&InsertPos) { 723 if (N->getOpcode() == ISD::HANDLENODE || N->getValueType(0) == MVT::Flag) 724 725 // Check that remaining values produced are not flags. 726 for (unsigned i = 1, e = N->getNumValues(); i != e; ++i) 727 if (N->getValueType(i) == MVT::Flag) 728 return 0; // Never CSE anything that produces a flag. 729 730 SDValue Ops[] = { Op1, Op2 }; 731 FoldingSetNodeID ID; 732 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, 2); 733 return CSEMap.FindNodeOrInsertPos(ID, InsertPos); 734} 735 736 737/// FindModifiedNodeSlot - Find a slot for the specified node if its operands 738/// were replaced with those specified. If this node is never memoized, 739/// return null, otherwise return a pointer to the slot it would take. If a 740/// node already exists with these operands, the slot will be non-null. 741SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, 742 const SDValue *Ops,unsigned NumOps, 743 void *&InsertPos) { 744 if (N->getValueType(0) == MVT::Flag) 745 return 0; // Never CSE anything that produces a flag. 746 747 switch (N->getOpcode()) { 748 default: break; 749 case ISD::HANDLENODE: 750 case ISD::DBG_LABEL: 751 case ISD::DBG_STOPPOINT: 752 case ISD::EH_LABEL: 753 case ISD::DECLARE: 754 return 0; // Never add these nodes. 755 } 756 757 // Check that remaining values produced are not flags. 758 for (unsigned i = 1, e = N->getNumValues(); i != e; ++i) 759 if (N->getValueType(i) == MVT::Flag) 760 return 0; // Never CSE anything that produces a flag. 761 762 FoldingSetNodeID ID; 763 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, NumOps); 764 765 if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 766 ID.AddInteger(LD->getAddressingMode()); 767 ID.AddInteger(LD->getExtensionType()); 768 ID.AddInteger(LD->getMemoryVT().getRawBits()); 769 ID.AddInteger(LD->getRawFlags()); 770 } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 771 ID.AddInteger(ST->getAddressingMode()); 772 ID.AddInteger(ST->isTruncatingStore()); 773 ID.AddInteger(ST->getMemoryVT().getRawBits()); 774 ID.AddInteger(ST->getRawFlags()); 775 } 776 777 return CSEMap.FindNodeOrInsertPos(ID, InsertPos); 778} 779 780/// VerifyNode - Sanity check the given node. Aborts if it is invalid. 781void SelectionDAG::VerifyNode(SDNode *N) { 782 switch (N->getOpcode()) { 783 default: 784 break; 785 case ISD::BUILD_VECTOR: { 786 assert(N->getNumValues() == 1 && "Too many results for BUILD_VECTOR!"); 787 assert(N->getValueType(0).isVector() && "Wrong BUILD_VECTOR return type!"); 788 assert(N->getNumOperands() == N->getValueType(0).getVectorNumElements() && 789 "Wrong number of BUILD_VECTOR operands!"); 790 MVT EltVT = N->getValueType(0).getVectorElementType(); 791 for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ++I) 792 assert(I->getSDValue().getValueType() == EltVT && 793 "Wrong BUILD_VECTOR operand type!"); 794 break; 795 } 796 } 797} 798 799/// getMVTAlignment - Compute the default alignment value for the 800/// given type. 801/// 802unsigned SelectionDAG::getMVTAlignment(MVT VT) const { 803 const Type *Ty = VT == MVT::iPTR ? 804 PointerType::get(Type::Int8Ty, 0) : 805 VT.getTypeForMVT(); 806 807 return TLI.getTargetData()->getABITypeAlignment(Ty); 808} 809 810SelectionDAG::SelectionDAG(TargetLowering &tli, FunctionLoweringInfo &fli) 811 : TLI(tli), FLI(fli), 812 EntryNode(ISD::EntryToken, getVTList(MVT::Other)), 813 Root(getEntryNode()) { 814 AllNodes.push_back(&EntryNode); 815} 816 817void SelectionDAG::init(MachineFunction &mf, MachineModuleInfo *mmi) { 818 MF = &mf; 819 MMI = mmi; 820} 821 822SelectionDAG::~SelectionDAG() { 823 allnodes_clear(); 824} 825 826void SelectionDAG::allnodes_clear() { 827 assert(&*AllNodes.begin() == &EntryNode); 828 AllNodes.remove(AllNodes.begin()); 829 while (!AllNodes.empty()) { 830 SDNode *N = AllNodes.remove(AllNodes.begin()); 831 N->SetNextInBucket(0); 832 if (N->OperandsNeedDelete) 833 delete [] N->OperandList; 834 NodeAllocator.Deallocate(N); 835 } 836} 837 838void SelectionDAG::clear() { 839 allnodes_clear(); 840 OperandAllocator.Reset(); 841 CSEMap.clear(); 842 843 ExtendedValueTypeNodes.clear(); 844 Symbols.clear(); 845 TargetSymbols.clear(); 846 std::fill(CondCodeNodes.begin(), CondCodeNodes.end(), 847 static_cast<CondCodeSDNode*>(0)); 848 std::fill(ValueTypeNodes.begin(), ValueTypeNodes.end(), 849 static_cast<SDNode*>(0)); 850 851 EntryNode.Uses = 0; 852 AllNodes.push_back(&EntryNode); 853 Root = getEntryNode(); 854} 855 856SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, MVT VT) { 857 if (Op.getValueType() == VT) return Op; 858 APInt Imm = APInt::getLowBitsSet(Op.getValueSizeInBits(), 859 VT.getSizeInBits()); 860 return getNode(ISD::AND, Op.getValueType(), Op, 861 getConstant(Imm, Op.getValueType())); 862} 863 864SDValue SelectionDAG::getConstant(uint64_t Val, MVT VT, bool isT) { 865 MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 866 return getConstant(APInt(EltVT.getSizeInBits(), Val), VT, isT); 867} 868 869SDValue SelectionDAG::getConstant(const APInt &Val, MVT VT, bool isT) { 870 return getConstant(*ConstantInt::get(Val), VT, isT); 871} 872 873SDValue SelectionDAG::getConstant(const ConstantInt &Val, MVT VT, bool isT) { 874 assert(VT.isInteger() && "Cannot create FP integer constant!"); 875 876 MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 877 assert(Val.getBitWidth() == EltVT.getSizeInBits() && 878 "APInt size does not match type size!"); 879 880 unsigned Opc = isT ? ISD::TargetConstant : ISD::Constant; 881 FoldingSetNodeID ID; 882 AddNodeIDNode(ID, Opc, getVTList(EltVT), 0, 0); 883 ID.AddPointer(&Val); 884 void *IP = 0; 885 SDNode *N = NULL; 886 if ((N = CSEMap.FindNodeOrInsertPos(ID, IP))) 887 if (!VT.isVector()) 888 return SDValue(N, 0); 889 if (!N) { 890 N = NodeAllocator.Allocate<ConstantSDNode>(); 891 new (N) ConstantSDNode(isT, &Val, EltVT); 892 CSEMap.InsertNode(N, IP); 893 AllNodes.push_back(N); 894 } 895 896 SDValue Result(N, 0); 897 if (VT.isVector()) { 898 SmallVector<SDValue, 8> Ops; 899 Ops.assign(VT.getVectorNumElements(), Result); 900 Result = getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 901 } 902 return Result; 903} 904 905SDValue SelectionDAG::getIntPtrConstant(uint64_t Val, bool isTarget) { 906 return getConstant(Val, TLI.getPointerTy(), isTarget); 907} 908 909 910SDValue SelectionDAG::getConstantFP(const APFloat& V, MVT VT, bool isTarget) { 911 return getConstantFP(*ConstantFP::get(V), VT, isTarget); 912} 913 914SDValue SelectionDAG::getConstantFP(const ConstantFP& V, MVT VT, bool isTarget){ 915 assert(VT.isFloatingPoint() && "Cannot create integer FP constant!"); 916 917 MVT EltVT = 918 VT.isVector() ? VT.getVectorElementType() : VT; 919 920 // Do the map lookup using the actual bit pattern for the floating point 921 // value, so that we don't have problems with 0.0 comparing equal to -0.0, and 922 // we don't have issues with SNANs. 923 unsigned Opc = isTarget ? ISD::TargetConstantFP : ISD::ConstantFP; 924 FoldingSetNodeID ID; 925 AddNodeIDNode(ID, Opc, getVTList(EltVT), 0, 0); 926 ID.AddPointer(&V); 927 void *IP = 0; 928 SDNode *N = NULL; 929 if ((N = CSEMap.FindNodeOrInsertPos(ID, IP))) 930 if (!VT.isVector()) 931 return SDValue(N, 0); 932 if (!N) { 933 N = NodeAllocator.Allocate<ConstantFPSDNode>(); 934 new (N) ConstantFPSDNode(isTarget, &V, EltVT); 935 CSEMap.InsertNode(N, IP); 936 AllNodes.push_back(N); 937 } 938 939 SDValue Result(N, 0); 940 if (VT.isVector()) { 941 SmallVector<SDValue, 8> Ops; 942 Ops.assign(VT.getVectorNumElements(), Result); 943 Result = getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 944 } 945 return Result; 946} 947 948SDValue SelectionDAG::getConstantFP(double Val, MVT VT, bool isTarget) { 949 MVT EltVT = 950 VT.isVector() ? VT.getVectorElementType() : VT; 951 if (EltVT==MVT::f32) 952 return getConstantFP(APFloat((float)Val), VT, isTarget); 953 else 954 return getConstantFP(APFloat(Val), VT, isTarget); 955} 956 957SDValue SelectionDAG::getGlobalAddress(const GlobalValue *GV, 958 MVT VT, int Offset, 959 bool isTargetGA) { 960 unsigned Opc; 961 962 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV); 963 if (!GVar) { 964 // If GV is an alias then use the aliasee for determining thread-localness. 965 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) 966 GVar = dyn_cast_or_null<GlobalVariable>(GA->resolveAliasedGlobal(false)); 967 } 968 969 if (GVar && GVar->isThreadLocal()) 970 Opc = isTargetGA ? ISD::TargetGlobalTLSAddress : ISD::GlobalTLSAddress; 971 else 972 Opc = isTargetGA ? ISD::TargetGlobalAddress : ISD::GlobalAddress; 973 974 FoldingSetNodeID ID; 975 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 976 ID.AddPointer(GV); 977 ID.AddInteger(Offset); 978 void *IP = 0; 979 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 980 return SDValue(E, 0); 981 SDNode *N = NodeAllocator.Allocate<GlobalAddressSDNode>(); 982 new (N) GlobalAddressSDNode(isTargetGA, GV, VT, Offset); 983 CSEMap.InsertNode(N, IP); 984 AllNodes.push_back(N); 985 return SDValue(N, 0); 986} 987 988SDValue SelectionDAG::getFrameIndex(int FI, MVT VT, bool isTarget) { 989 unsigned Opc = isTarget ? ISD::TargetFrameIndex : ISD::FrameIndex; 990 FoldingSetNodeID ID; 991 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 992 ID.AddInteger(FI); 993 void *IP = 0; 994 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 995 return SDValue(E, 0); 996 SDNode *N = NodeAllocator.Allocate<FrameIndexSDNode>(); 997 new (N) FrameIndexSDNode(FI, VT, isTarget); 998 CSEMap.InsertNode(N, IP); 999 AllNodes.push_back(N); 1000 return SDValue(N, 0); 1001} 1002 1003SDValue SelectionDAG::getJumpTable(int JTI, MVT VT, bool isTarget){ 1004 unsigned Opc = isTarget ? ISD::TargetJumpTable : ISD::JumpTable; 1005 FoldingSetNodeID ID; 1006 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 1007 ID.AddInteger(JTI); 1008 void *IP = 0; 1009 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1010 return SDValue(E, 0); 1011 SDNode *N = NodeAllocator.Allocate<JumpTableSDNode>(); 1012 new (N) JumpTableSDNode(JTI, VT, isTarget); 1013 CSEMap.InsertNode(N, IP); 1014 AllNodes.push_back(N); 1015 return SDValue(N, 0); 1016} 1017 1018SDValue SelectionDAG::getConstantPool(Constant *C, MVT VT, 1019 unsigned Alignment, int Offset, 1020 bool isTarget) { 1021 unsigned Opc = isTarget ? ISD::TargetConstantPool : ISD::ConstantPool; 1022 FoldingSetNodeID ID; 1023 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 1024 ID.AddInteger(Alignment); 1025 ID.AddInteger(Offset); 1026 ID.AddPointer(C); 1027 void *IP = 0; 1028 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1029 return SDValue(E, 0); 1030 SDNode *N = NodeAllocator.Allocate<ConstantPoolSDNode>(); 1031 new (N) ConstantPoolSDNode(isTarget, C, VT, Offset, Alignment); 1032 CSEMap.InsertNode(N, IP); 1033 AllNodes.push_back(N); 1034 return SDValue(N, 0); 1035} 1036 1037 1038SDValue SelectionDAG::getConstantPool(MachineConstantPoolValue *C, MVT VT, 1039 unsigned Alignment, int Offset, 1040 bool isTarget) { 1041 unsigned Opc = isTarget ? ISD::TargetConstantPool : ISD::ConstantPool; 1042 FoldingSetNodeID ID; 1043 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 1044 ID.AddInteger(Alignment); 1045 ID.AddInteger(Offset); 1046 C->AddSelectionDAGCSEId(ID); 1047 void *IP = 0; 1048 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1049 return SDValue(E, 0); 1050 SDNode *N = NodeAllocator.Allocate<ConstantPoolSDNode>(); 1051 new (N) ConstantPoolSDNode(isTarget, C, VT, Offset, Alignment); 1052 CSEMap.InsertNode(N, IP); 1053 AllNodes.push_back(N); 1054 return SDValue(N, 0); 1055} 1056 1057 1058SDValue SelectionDAG::getBasicBlock(MachineBasicBlock *MBB) { 1059 FoldingSetNodeID ID; 1060 AddNodeIDNode(ID, ISD::BasicBlock, getVTList(MVT::Other), 0, 0); 1061 ID.AddPointer(MBB); 1062 void *IP = 0; 1063 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1064 return SDValue(E, 0); 1065 SDNode *N = NodeAllocator.Allocate<BasicBlockSDNode>(); 1066 new (N) BasicBlockSDNode(MBB); 1067 CSEMap.InsertNode(N, IP); 1068 AllNodes.push_back(N); 1069 return SDValue(N, 0); 1070} 1071 1072SDValue SelectionDAG::getArgFlags(ISD::ArgFlagsTy Flags) { 1073 FoldingSetNodeID ID; 1074 AddNodeIDNode(ID, ISD::ARG_FLAGS, getVTList(MVT::Other), 0, 0); 1075 ID.AddInteger(Flags.getRawBits()); 1076 void *IP = 0; 1077 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1078 return SDValue(E, 0); 1079 SDNode *N = NodeAllocator.Allocate<ARG_FLAGSSDNode>(); 1080 new (N) ARG_FLAGSSDNode(Flags); 1081 CSEMap.InsertNode(N, IP); 1082 AllNodes.push_back(N); 1083 return SDValue(N, 0); 1084} 1085 1086SDValue SelectionDAG::getValueType(MVT VT) { 1087 if (VT.isSimple() && (unsigned)VT.getSimpleVT() >= ValueTypeNodes.size()) 1088 ValueTypeNodes.resize(VT.getSimpleVT()+1); 1089 1090 SDNode *&N = VT.isExtended() ? 1091 ExtendedValueTypeNodes[VT] : ValueTypeNodes[VT.getSimpleVT()]; 1092 1093 if (N) return SDValue(N, 0); 1094 N = NodeAllocator.Allocate<VTSDNode>(); 1095 new (N) VTSDNode(VT); 1096 AllNodes.push_back(N); 1097 return SDValue(N, 0); 1098} 1099 1100SDValue SelectionDAG::getSymbol(const char *Sym, MVT VT, 1101 GlobalValue::LinkageTypes LT) { 1102 SDNode *&N = Symbols[Sym]; 1103 if (N) return SDValue(N, 0); 1104 N = NodeAllocator.Allocate<SymbolSDNode>(); 1105 new (N) SymbolSDNode(false, Sym, VT, LT); 1106 AllNodes.push_back(N); 1107 return SDValue(N, 0); 1108} 1109 1110SDValue SelectionDAG::getTargetSymbol(const char *Sym, MVT VT, 1111 GlobalValue::LinkageTypes LT) { 1112 SDNode *&N = TargetSymbols[Sym]; 1113 if (N) return SDValue(N, 0); 1114 N = NodeAllocator.Allocate<SymbolSDNode>(); 1115 new (N) SymbolSDNode(true, Sym, VT, LT); 1116 AllNodes.push_back(N); 1117 return SDValue(N, 0); 1118} 1119 1120SDValue SelectionDAG::getCondCode(ISD::CondCode Cond) { 1121 if ((unsigned)Cond >= CondCodeNodes.size()) 1122 CondCodeNodes.resize(Cond+1); 1123 1124 if (CondCodeNodes[Cond] == 0) { 1125 CondCodeSDNode *N = NodeAllocator.Allocate<CondCodeSDNode>(); 1126 new (N) CondCodeSDNode(Cond); 1127 CondCodeNodes[Cond] = N; 1128 AllNodes.push_back(N); 1129 } 1130 return SDValue(CondCodeNodes[Cond], 0); 1131} 1132 1133SDValue SelectionDAG::getRegister(unsigned RegNo, MVT VT) { 1134 FoldingSetNodeID ID; 1135 AddNodeIDNode(ID, ISD::Register, getVTList(VT), 0, 0); 1136 ID.AddInteger(RegNo); 1137 void *IP = 0; 1138 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1139 return SDValue(E, 0); 1140 SDNode *N = NodeAllocator.Allocate<RegisterSDNode>(); 1141 new (N) RegisterSDNode(RegNo, VT); 1142 CSEMap.InsertNode(N, IP); 1143 AllNodes.push_back(N); 1144 return SDValue(N, 0); 1145} 1146 1147SDValue SelectionDAG::getDbgStopPoint(SDValue Root, 1148 unsigned Line, unsigned Col, 1149 const CompileUnitDesc *CU) { 1150 SDNode *N = NodeAllocator.Allocate<DbgStopPointSDNode>(); 1151 new (N) DbgStopPointSDNode(Root, Line, Col, CU); 1152 AllNodes.push_back(N); 1153 return SDValue(N, 0); 1154} 1155 1156SDValue SelectionDAG::getLabel(unsigned Opcode, 1157 SDValue Root, 1158 unsigned LabelID) { 1159 FoldingSetNodeID ID; 1160 SDValue Ops[] = { Root }; 1161 AddNodeIDNode(ID, Opcode, getVTList(MVT::Other), &Ops[0], 1); 1162 ID.AddInteger(LabelID); 1163 void *IP = 0; 1164 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1165 return SDValue(E, 0); 1166 SDNode *N = NodeAllocator.Allocate<LabelSDNode>(); 1167 new (N) LabelSDNode(Opcode, Root, LabelID); 1168 CSEMap.InsertNode(N, IP); 1169 AllNodes.push_back(N); 1170 return SDValue(N, 0); 1171} 1172 1173SDValue SelectionDAG::getSrcValue(const Value *V) { 1174 assert((!V || isa<PointerType>(V->getType())) && 1175 "SrcValue is not a pointer?"); 1176 1177 FoldingSetNodeID ID; 1178 AddNodeIDNode(ID, ISD::SRCVALUE, getVTList(MVT::Other), 0, 0); 1179 ID.AddPointer(V); 1180 1181 void *IP = 0; 1182 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1183 return SDValue(E, 0); 1184 1185 SDNode *N = NodeAllocator.Allocate<SrcValueSDNode>(); 1186 new (N) SrcValueSDNode(V); 1187 CSEMap.InsertNode(N, IP); 1188 AllNodes.push_back(N); 1189 return SDValue(N, 0); 1190} 1191 1192SDValue SelectionDAG::getMemOperand(const MachineMemOperand &MO) { 1193 const Value *v = MO.getValue(); 1194 assert((!v || isa<PointerType>(v->getType())) && 1195 "SrcValue is not a pointer?"); 1196 1197 FoldingSetNodeID ID; 1198 AddNodeIDNode(ID, ISD::MEMOPERAND, getVTList(MVT::Other), 0, 0); 1199 MO.Profile(ID); 1200 1201 void *IP = 0; 1202 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1203 return SDValue(E, 0); 1204 1205 SDNode *N = NodeAllocator.Allocate<MemOperandSDNode>(); 1206 new (N) MemOperandSDNode(MO); 1207 CSEMap.InsertNode(N, IP); 1208 AllNodes.push_back(N); 1209 return SDValue(N, 0); 1210} 1211 1212/// CreateStackTemporary - Create a stack temporary, suitable for holding the 1213/// specified value type. 1214SDValue SelectionDAG::CreateStackTemporary(MVT VT, unsigned minAlign) { 1215 MachineFrameInfo *FrameInfo = getMachineFunction().getFrameInfo(); 1216 unsigned ByteSize = VT.getSizeInBits()/8; 1217 const Type *Ty = VT.getTypeForMVT(); 1218 unsigned StackAlign = 1219 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), minAlign); 1220 1221 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, StackAlign); 1222 return getFrameIndex(FrameIdx, TLI.getPointerTy()); 1223} 1224 1225SDValue SelectionDAG::FoldSetCC(MVT VT, SDValue N1, 1226 SDValue N2, ISD::CondCode Cond) { 1227 // These setcc operations always fold. 1228 switch (Cond) { 1229 default: break; 1230 case ISD::SETFALSE: 1231 case ISD::SETFALSE2: return getConstant(0, VT); 1232 case ISD::SETTRUE: 1233 case ISD::SETTRUE2: return getConstant(1, VT); 1234 1235 case ISD::SETOEQ: 1236 case ISD::SETOGT: 1237 case ISD::SETOGE: 1238 case ISD::SETOLT: 1239 case ISD::SETOLE: 1240 case ISD::SETONE: 1241 case ISD::SETO: 1242 case ISD::SETUO: 1243 case ISD::SETUEQ: 1244 case ISD::SETUNE: 1245 assert(!N1.getValueType().isInteger() && "Illegal setcc for integer!"); 1246 break; 1247 } 1248 1249 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode())) { 1250 const APInt &C2 = N2C->getAPIntValue(); 1251 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) { 1252 const APInt &C1 = N1C->getAPIntValue(); 1253 1254 switch (Cond) { 1255 default: assert(0 && "Unknown integer setcc!"); 1256 case ISD::SETEQ: return getConstant(C1 == C2, VT); 1257 case ISD::SETNE: return getConstant(C1 != C2, VT); 1258 case ISD::SETULT: return getConstant(C1.ult(C2), VT); 1259 case ISD::SETUGT: return getConstant(C1.ugt(C2), VT); 1260 case ISD::SETULE: return getConstant(C1.ule(C2), VT); 1261 case ISD::SETUGE: return getConstant(C1.uge(C2), VT); 1262 case ISD::SETLT: return getConstant(C1.slt(C2), VT); 1263 case ISD::SETGT: return getConstant(C1.sgt(C2), VT); 1264 case ISD::SETLE: return getConstant(C1.sle(C2), VT); 1265 case ISD::SETGE: return getConstant(C1.sge(C2), VT); 1266 } 1267 } 1268 } 1269 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.getNode())) { 1270 if (ConstantFPSDNode *N2C = dyn_cast<ConstantFPSDNode>(N2.getNode())) { 1271 // No compile time operations on this type yet. 1272 if (N1C->getValueType(0) == MVT::ppcf128) 1273 return SDValue(); 1274 1275 APFloat::cmpResult R = N1C->getValueAPF().compare(N2C->getValueAPF()); 1276 switch (Cond) { 1277 default: break; 1278 case ISD::SETEQ: if (R==APFloat::cmpUnordered) 1279 return getNode(ISD::UNDEF, VT); 1280 // fall through 1281 case ISD::SETOEQ: return getConstant(R==APFloat::cmpEqual, VT); 1282 case ISD::SETNE: if (R==APFloat::cmpUnordered) 1283 return getNode(ISD::UNDEF, VT); 1284 // fall through 1285 case ISD::SETONE: return getConstant(R==APFloat::cmpGreaterThan || 1286 R==APFloat::cmpLessThan, VT); 1287 case ISD::SETLT: if (R==APFloat::cmpUnordered) 1288 return getNode(ISD::UNDEF, VT); 1289 // fall through 1290 case ISD::SETOLT: return getConstant(R==APFloat::cmpLessThan, VT); 1291 case ISD::SETGT: if (R==APFloat::cmpUnordered) 1292 return getNode(ISD::UNDEF, VT); 1293 // fall through 1294 case ISD::SETOGT: return getConstant(R==APFloat::cmpGreaterThan, VT); 1295 case ISD::SETLE: if (R==APFloat::cmpUnordered) 1296 return getNode(ISD::UNDEF, VT); 1297 // fall through 1298 case ISD::SETOLE: return getConstant(R==APFloat::cmpLessThan || 1299 R==APFloat::cmpEqual, VT); 1300 case ISD::SETGE: if (R==APFloat::cmpUnordered) 1301 return getNode(ISD::UNDEF, VT); 1302 // fall through 1303 case ISD::SETOGE: return getConstant(R==APFloat::cmpGreaterThan || 1304 R==APFloat::cmpEqual, VT); 1305 case ISD::SETO: return getConstant(R!=APFloat::cmpUnordered, VT); 1306 case ISD::SETUO: return getConstant(R==APFloat::cmpUnordered, VT); 1307 case ISD::SETUEQ: return getConstant(R==APFloat::cmpUnordered || 1308 R==APFloat::cmpEqual, VT); 1309 case ISD::SETUNE: return getConstant(R!=APFloat::cmpEqual, VT); 1310 case ISD::SETULT: return getConstant(R==APFloat::cmpUnordered || 1311 R==APFloat::cmpLessThan, VT); 1312 case ISD::SETUGT: return getConstant(R==APFloat::cmpGreaterThan || 1313 R==APFloat::cmpUnordered, VT); 1314 case ISD::SETULE: return getConstant(R!=APFloat::cmpGreaterThan, VT); 1315 case ISD::SETUGE: return getConstant(R!=APFloat::cmpLessThan, VT); 1316 } 1317 } else { 1318 // Ensure that the constant occurs on the RHS. 1319 return getSetCC(VT, N2, N1, ISD::getSetCCSwappedOperands(Cond)); 1320 } 1321 } 1322 1323 // Could not fold it. 1324 return SDValue(); 1325} 1326 1327/// SignBitIsZero - Return true if the sign bit of Op is known to be zero. We 1328/// use this predicate to simplify operations downstream. 1329bool SelectionDAG::SignBitIsZero(SDValue Op, unsigned Depth) const { 1330 unsigned BitWidth = Op.getValueSizeInBits(); 1331 return MaskedValueIsZero(Op, APInt::getSignBit(BitWidth), Depth); 1332} 1333 1334/// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero. We use 1335/// this predicate to simplify operations downstream. Mask is known to be zero 1336/// for bits that V cannot have. 1337bool SelectionDAG::MaskedValueIsZero(SDValue Op, const APInt &Mask, 1338 unsigned Depth) const { 1339 APInt KnownZero, KnownOne; 1340 ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth); 1341 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1342 return (KnownZero & Mask) == Mask; 1343} 1344 1345/// ComputeMaskedBits - Determine which of the bits specified in Mask are 1346/// known to be either zero or one and return them in the KnownZero/KnownOne 1347/// bitsets. This code only analyzes bits in Mask, in order to short-circuit 1348/// processing. 1349void SelectionDAG::ComputeMaskedBits(SDValue Op, const APInt &Mask, 1350 APInt &KnownZero, APInt &KnownOne, 1351 unsigned Depth) const { 1352 unsigned BitWidth = Mask.getBitWidth(); 1353 assert(BitWidth == Op.getValueType().getSizeInBits() && 1354 "Mask size mismatches value type size!"); 1355 1356 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything. 1357 if (Depth == 6 || Mask == 0) 1358 return; // Limit search depth. 1359 1360 APInt KnownZero2, KnownOne2; 1361 1362 switch (Op.getOpcode()) { 1363 case ISD::Constant: 1364 // We know all of the bits for a constant! 1365 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & Mask; 1366 KnownZero = ~KnownOne & Mask; 1367 return; 1368 case ISD::AND: 1369 // If either the LHS or the RHS are Zero, the result is zero. 1370 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1371 ComputeMaskedBits(Op.getOperand(0), Mask & ~KnownZero, 1372 KnownZero2, KnownOne2, Depth+1); 1373 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1374 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1375 1376 // Output known-1 bits are only known if set in both the LHS & RHS. 1377 KnownOne &= KnownOne2; 1378 // Output known-0 are known to be clear if zero in either the LHS | RHS. 1379 KnownZero |= KnownZero2; 1380 return; 1381 case ISD::OR: 1382 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1383 ComputeMaskedBits(Op.getOperand(0), Mask & ~KnownOne, 1384 KnownZero2, KnownOne2, Depth+1); 1385 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1386 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1387 1388 // Output known-0 bits are only known if clear in both the LHS & RHS. 1389 KnownZero &= KnownZero2; 1390 // Output known-1 are known to be set if set in either the LHS | RHS. 1391 KnownOne |= KnownOne2; 1392 return; 1393 case ISD::XOR: { 1394 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1395 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1); 1396 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1397 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1398 1399 // Output known-0 bits are known if clear or set in both the LHS & RHS. 1400 APInt KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 1401 // Output known-1 are known to be set if set in only one of the LHS, RHS. 1402 KnownOne = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 1403 KnownZero = KnownZeroOut; 1404 return; 1405 } 1406 case ISD::MUL: { 1407 APInt Mask2 = APInt::getAllOnesValue(BitWidth); 1408 ComputeMaskedBits(Op.getOperand(1), Mask2, KnownZero, KnownOne, Depth+1); 1409 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero2, KnownOne2, Depth+1); 1410 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1411 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1412 1413 // If low bits are zero in either operand, output low known-0 bits. 1414 // Also compute a conserative estimate for high known-0 bits. 1415 // More trickiness is possible, but this is sufficient for the 1416 // interesting case of alignment computation. 1417 KnownOne.clear(); 1418 unsigned TrailZ = KnownZero.countTrailingOnes() + 1419 KnownZero2.countTrailingOnes(); 1420 unsigned LeadZ = std::max(KnownZero.countLeadingOnes() + 1421 KnownZero2.countLeadingOnes(), 1422 BitWidth) - BitWidth; 1423 1424 TrailZ = std::min(TrailZ, BitWidth); 1425 LeadZ = std::min(LeadZ, BitWidth); 1426 KnownZero = APInt::getLowBitsSet(BitWidth, TrailZ) | 1427 APInt::getHighBitsSet(BitWidth, LeadZ); 1428 KnownZero &= Mask; 1429 return; 1430 } 1431 case ISD::UDIV: { 1432 // For the purposes of computing leading zeros we can conservatively 1433 // treat a udiv as a logical right shift by the power of 2 known to 1434 // be less than the denominator. 1435 APInt AllOnes = APInt::getAllOnesValue(BitWidth); 1436 ComputeMaskedBits(Op.getOperand(0), 1437 AllOnes, KnownZero2, KnownOne2, Depth+1); 1438 unsigned LeadZ = KnownZero2.countLeadingOnes(); 1439 1440 KnownOne2.clear(); 1441 KnownZero2.clear(); 1442 ComputeMaskedBits(Op.getOperand(1), 1443 AllOnes, KnownZero2, KnownOne2, Depth+1); 1444 unsigned RHSUnknownLeadingOnes = KnownOne2.countLeadingZeros(); 1445 if (RHSUnknownLeadingOnes != BitWidth) 1446 LeadZ = std::min(BitWidth, 1447 LeadZ + BitWidth - RHSUnknownLeadingOnes - 1); 1448 1449 KnownZero = APInt::getHighBitsSet(BitWidth, LeadZ) & Mask; 1450 return; 1451 } 1452 case ISD::SELECT: 1453 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero, KnownOne, Depth+1); 1454 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero2, KnownOne2, Depth+1); 1455 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1456 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1457 1458 // Only known if known in both the LHS and RHS. 1459 KnownOne &= KnownOne2; 1460 KnownZero &= KnownZero2; 1461 return; 1462 case ISD::SELECT_CC: 1463 ComputeMaskedBits(Op.getOperand(3), Mask, KnownZero, KnownOne, Depth+1); 1464 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero2, KnownOne2, Depth+1); 1465 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1466 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1467 1468 // Only known if known in both the LHS and RHS. 1469 KnownOne &= KnownOne2; 1470 KnownZero &= KnownZero2; 1471 return; 1472 case ISD::SETCC: 1473 // If we know the result of a setcc has the top bits zero, use this info. 1474 if (TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult && 1475 BitWidth > 1) 1476 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1); 1477 return; 1478 case ISD::SHL: 1479 // (shl X, C1) & C2 == 0 iff (X & C2 >>u C1) == 0 1480 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1481 unsigned ShAmt = SA->getZExtValue(); 1482 1483 // If the shift count is an invalid immediate, don't do anything. 1484 if (ShAmt >= BitWidth) 1485 return; 1486 1487 ComputeMaskedBits(Op.getOperand(0), Mask.lshr(ShAmt), 1488 KnownZero, KnownOne, Depth+1); 1489 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1490 KnownZero <<= ShAmt; 1491 KnownOne <<= ShAmt; 1492 // low bits known zero. 1493 KnownZero |= APInt::getLowBitsSet(BitWidth, ShAmt); 1494 } 1495 return; 1496 case ISD::SRL: 1497 // (ushr X, C1) & C2 == 0 iff (-1 >> C1) & C2 == 0 1498 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1499 unsigned ShAmt = SA->getZExtValue(); 1500 1501 // If the shift count is an invalid immediate, don't do anything. 1502 if (ShAmt >= BitWidth) 1503 return; 1504 1505 ComputeMaskedBits(Op.getOperand(0), (Mask << ShAmt), 1506 KnownZero, KnownOne, Depth+1); 1507 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1508 KnownZero = KnownZero.lshr(ShAmt); 1509 KnownOne = KnownOne.lshr(ShAmt); 1510 1511 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt) & Mask; 1512 KnownZero |= HighBits; // High bits known zero. 1513 } 1514 return; 1515 case ISD::SRA: 1516 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1517 unsigned ShAmt = SA->getZExtValue(); 1518 1519 // If the shift count is an invalid immediate, don't do anything. 1520 if (ShAmt >= BitWidth) 1521 return; 1522 1523 APInt InDemandedMask = (Mask << ShAmt); 1524 // If any of the demanded bits are produced by the sign extension, we also 1525 // demand the input sign bit. 1526 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt) & Mask; 1527 if (HighBits.getBoolValue()) 1528 InDemandedMask |= APInt::getSignBit(BitWidth); 1529 1530 ComputeMaskedBits(Op.getOperand(0), InDemandedMask, KnownZero, KnownOne, 1531 Depth+1); 1532 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1533 KnownZero = KnownZero.lshr(ShAmt); 1534 KnownOne = KnownOne.lshr(ShAmt); 1535 1536 // Handle the sign bits. 1537 APInt SignBit = APInt::getSignBit(BitWidth); 1538 SignBit = SignBit.lshr(ShAmt); // Adjust to where it is now in the mask. 1539 1540 if (KnownZero.intersects(SignBit)) { 1541 KnownZero |= HighBits; // New bits are known zero. 1542 } else if (KnownOne.intersects(SignBit)) { 1543 KnownOne |= HighBits; // New bits are known one. 1544 } 1545 } 1546 return; 1547 case ISD::SIGN_EXTEND_INREG: { 1548 MVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1549 unsigned EBits = EVT.getSizeInBits(); 1550 1551 // Sign extension. Compute the demanded bits in the result that are not 1552 // present in the input. 1553 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - EBits) & Mask; 1554 1555 APInt InSignBit = APInt::getSignBit(EBits); 1556 APInt InputDemandedBits = Mask & APInt::getLowBitsSet(BitWidth, EBits); 1557 1558 // If the sign extended bits are demanded, we know that the sign 1559 // bit is demanded. 1560 InSignBit.zext(BitWidth); 1561 if (NewBits.getBoolValue()) 1562 InputDemandedBits |= InSignBit; 1563 1564 ComputeMaskedBits(Op.getOperand(0), InputDemandedBits, 1565 KnownZero, KnownOne, Depth+1); 1566 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1567 1568 // If the sign bit of the input is known set or clear, then we know the 1569 // top bits of the result. 1570 if (KnownZero.intersects(InSignBit)) { // Input sign bit known clear 1571 KnownZero |= NewBits; 1572 KnownOne &= ~NewBits; 1573 } else if (KnownOne.intersects(InSignBit)) { // Input sign bit known set 1574 KnownOne |= NewBits; 1575 KnownZero &= ~NewBits; 1576 } else { // Input sign bit unknown 1577 KnownZero &= ~NewBits; 1578 KnownOne &= ~NewBits; 1579 } 1580 return; 1581 } 1582 case ISD::CTTZ: 1583 case ISD::CTLZ: 1584 case ISD::CTPOP: { 1585 unsigned LowBits = Log2_32(BitWidth)+1; 1586 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - LowBits); 1587 KnownOne.clear(); 1588 return; 1589 } 1590 case ISD::LOAD: { 1591 if (ISD::isZEXTLoad(Op.getNode())) { 1592 LoadSDNode *LD = cast<LoadSDNode>(Op); 1593 MVT VT = LD->getMemoryVT(); 1594 unsigned MemBits = VT.getSizeInBits(); 1595 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits) & Mask; 1596 } 1597 return; 1598 } 1599 case ISD::ZERO_EXTEND: { 1600 MVT InVT = Op.getOperand(0).getValueType(); 1601 unsigned InBits = InVT.getSizeInBits(); 1602 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - InBits) & Mask; 1603 APInt InMask = Mask; 1604 InMask.trunc(InBits); 1605 KnownZero.trunc(InBits); 1606 KnownOne.trunc(InBits); 1607 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1608 KnownZero.zext(BitWidth); 1609 KnownOne.zext(BitWidth); 1610 KnownZero |= NewBits; 1611 return; 1612 } 1613 case ISD::SIGN_EXTEND: { 1614 MVT InVT = Op.getOperand(0).getValueType(); 1615 unsigned InBits = InVT.getSizeInBits(); 1616 APInt InSignBit = APInt::getSignBit(InBits); 1617 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - InBits) & Mask; 1618 APInt InMask = Mask; 1619 InMask.trunc(InBits); 1620 1621 // If any of the sign extended bits are demanded, we know that the sign 1622 // bit is demanded. Temporarily set this bit in the mask for our callee. 1623 if (NewBits.getBoolValue()) 1624 InMask |= InSignBit; 1625 1626 KnownZero.trunc(InBits); 1627 KnownOne.trunc(InBits); 1628 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1629 1630 // Note if the sign bit is known to be zero or one. 1631 bool SignBitKnownZero = KnownZero.isNegative(); 1632 bool SignBitKnownOne = KnownOne.isNegative(); 1633 assert(!(SignBitKnownZero && SignBitKnownOne) && 1634 "Sign bit can't be known to be both zero and one!"); 1635 1636 // If the sign bit wasn't actually demanded by our caller, we don't 1637 // want it set in the KnownZero and KnownOne result values. Reset the 1638 // mask and reapply it to the result values. 1639 InMask = Mask; 1640 InMask.trunc(InBits); 1641 KnownZero &= InMask; 1642 KnownOne &= InMask; 1643 1644 KnownZero.zext(BitWidth); 1645 KnownOne.zext(BitWidth); 1646 1647 // If the sign bit is known zero or one, the top bits match. 1648 if (SignBitKnownZero) 1649 KnownZero |= NewBits; 1650 else if (SignBitKnownOne) 1651 KnownOne |= NewBits; 1652 return; 1653 } 1654 case ISD::ANY_EXTEND: { 1655 MVT InVT = Op.getOperand(0).getValueType(); 1656 unsigned InBits = InVT.getSizeInBits(); 1657 APInt InMask = Mask; 1658 InMask.trunc(InBits); 1659 KnownZero.trunc(InBits); 1660 KnownOne.trunc(InBits); 1661 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1662 KnownZero.zext(BitWidth); 1663 KnownOne.zext(BitWidth); 1664 return; 1665 } 1666 case ISD::TRUNCATE: { 1667 MVT InVT = Op.getOperand(0).getValueType(); 1668 unsigned InBits = InVT.getSizeInBits(); 1669 APInt InMask = Mask; 1670 InMask.zext(InBits); 1671 KnownZero.zext(InBits); 1672 KnownOne.zext(InBits); 1673 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1674 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1675 KnownZero.trunc(BitWidth); 1676 KnownOne.trunc(BitWidth); 1677 break; 1678 } 1679 case ISD::AssertZext: { 1680 MVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1681 APInt InMask = APInt::getLowBitsSet(BitWidth, VT.getSizeInBits()); 1682 ComputeMaskedBits(Op.getOperand(0), Mask & InMask, KnownZero, 1683 KnownOne, Depth+1); 1684 KnownZero |= (~InMask) & Mask; 1685 return; 1686 } 1687 case ISD::FGETSIGN: 1688 // All bits are zero except the low bit. 1689 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - 1); 1690 return; 1691 1692 case ISD::SUB: { 1693 if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) { 1694 // We know that the top bits of C-X are clear if X contains less bits 1695 // than C (i.e. no wrap-around can happen). For example, 20-X is 1696 // positive if we can prove that X is >= 0 and < 16. 1697 if (CLHS->getAPIntValue().isNonNegative()) { 1698 unsigned NLZ = (CLHS->getAPIntValue()+1).countLeadingZeros(); 1699 // NLZ can't be BitWidth with no sign bit 1700 APInt MaskV = APInt::getHighBitsSet(BitWidth, NLZ+1); 1701 ComputeMaskedBits(Op.getOperand(1), MaskV, KnownZero2, KnownOne2, 1702 Depth+1); 1703 1704 // If all of the MaskV bits are known to be zero, then we know the 1705 // output top bits are zero, because we now know that the output is 1706 // from [0-C]. 1707 if ((KnownZero2 & MaskV) == MaskV) { 1708 unsigned NLZ2 = CLHS->getAPIntValue().countLeadingZeros(); 1709 // Top bits known zero. 1710 KnownZero = APInt::getHighBitsSet(BitWidth, NLZ2) & Mask; 1711 } 1712 } 1713 } 1714 } 1715 // fall through 1716 case ISD::ADD: { 1717 // Output known-0 bits are known if clear or set in both the low clear bits 1718 // common to both LHS & RHS. For example, 8+(X<<3) is known to have the 1719 // low 3 bits clear. 1720 APInt Mask2 = APInt::getLowBitsSet(BitWidth, Mask.countTrailingOnes()); 1721 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero2, KnownOne2, Depth+1); 1722 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1723 unsigned KnownZeroOut = KnownZero2.countTrailingOnes(); 1724 1725 ComputeMaskedBits(Op.getOperand(1), Mask2, KnownZero2, KnownOne2, Depth+1); 1726 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1727 KnownZeroOut = std::min(KnownZeroOut, 1728 KnownZero2.countTrailingOnes()); 1729 1730 KnownZero |= APInt::getLowBitsSet(BitWidth, KnownZeroOut); 1731 return; 1732 } 1733 case ISD::SREM: 1734 if (ConstantSDNode *Rem = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1735 const APInt &RA = Rem->getAPIntValue(); 1736 if (RA.isPowerOf2() || (-RA).isPowerOf2()) { 1737 APInt LowBits = RA.isStrictlyPositive() ? (RA - 1) : ~RA; 1738 APInt Mask2 = LowBits | APInt::getSignBit(BitWidth); 1739 ComputeMaskedBits(Op.getOperand(0), Mask2,KnownZero2,KnownOne2,Depth+1); 1740 1741 // If the sign bit of the first operand is zero, the sign bit of 1742 // the result is zero. If the first operand has no one bits below 1743 // the second operand's single 1 bit, its sign will be zero. 1744 if (KnownZero2[BitWidth-1] || ((KnownZero2 & LowBits) == LowBits)) 1745 KnownZero2 |= ~LowBits; 1746 1747 KnownZero |= KnownZero2 & Mask; 1748 1749 assert((KnownZero & KnownOne) == 0&&"Bits known to be one AND zero?"); 1750 } 1751 } 1752 return; 1753 case ISD::UREM: { 1754 if (ConstantSDNode *Rem = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1755 const APInt &RA = Rem->getAPIntValue(); 1756 if (RA.isPowerOf2()) { 1757 APInt LowBits = (RA - 1); 1758 APInt Mask2 = LowBits & Mask; 1759 KnownZero |= ~LowBits & Mask; 1760 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero, KnownOne,Depth+1); 1761 assert((KnownZero & KnownOne) == 0&&"Bits known to be one AND zero?"); 1762 break; 1763 } 1764 } 1765 1766 // Since the result is less than or equal to either operand, any leading 1767 // zero bits in either operand must also exist in the result. 1768 APInt AllOnes = APInt::getAllOnesValue(BitWidth); 1769 ComputeMaskedBits(Op.getOperand(0), AllOnes, KnownZero, KnownOne, 1770 Depth+1); 1771 ComputeMaskedBits(Op.getOperand(1), AllOnes, KnownZero2, KnownOne2, 1772 Depth+1); 1773 1774 uint32_t Leaders = std::max(KnownZero.countLeadingOnes(), 1775 KnownZero2.countLeadingOnes()); 1776 KnownOne.clear(); 1777 KnownZero = APInt::getHighBitsSet(BitWidth, Leaders) & Mask; 1778 return; 1779 } 1780 default: 1781 // Allow the target to implement this method for its nodes. 1782 if (Op.getOpcode() >= ISD::BUILTIN_OP_END) { 1783 case ISD::INTRINSIC_WO_CHAIN: 1784 case ISD::INTRINSIC_W_CHAIN: 1785 case ISD::INTRINSIC_VOID: 1786 TLI.computeMaskedBitsForTargetNode(Op, Mask, KnownZero, KnownOne, *this); 1787 } 1788 return; 1789 } 1790} 1791 1792/// ComputeNumSignBits - Return the number of times the sign bit of the 1793/// register is replicated into the other bits. We know that at least 1 bit 1794/// is always equal to the sign bit (itself), but other cases can give us 1795/// information. For example, immediately after an "SRA X, 2", we know that 1796/// the top 3 bits are all equal to each other, so we return 3. 1797unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, unsigned Depth) const{ 1798 MVT VT = Op.getValueType(); 1799 assert(VT.isInteger() && "Invalid VT!"); 1800 unsigned VTBits = VT.getSizeInBits(); 1801 unsigned Tmp, Tmp2; 1802 unsigned FirstAnswer = 1; 1803 1804 if (Depth == 6) 1805 return 1; // Limit search depth. 1806 1807 switch (Op.getOpcode()) { 1808 default: break; 1809 case ISD::AssertSext: 1810 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); 1811 return VTBits-Tmp+1; 1812 case ISD::AssertZext: 1813 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); 1814 return VTBits-Tmp; 1815 1816 case ISD::Constant: { 1817 const APInt &Val = cast<ConstantSDNode>(Op)->getAPIntValue(); 1818 // If negative, return # leading ones. 1819 if (Val.isNegative()) 1820 return Val.countLeadingOnes(); 1821 1822 // Return # leading zeros. 1823 return Val.countLeadingZeros(); 1824 } 1825 1826 case ISD::SIGN_EXTEND: 1827 Tmp = VTBits-Op.getOperand(0).getValueType().getSizeInBits(); 1828 return ComputeNumSignBits(Op.getOperand(0), Depth+1) + Tmp; 1829 1830 case ISD::SIGN_EXTEND_INREG: 1831 // Max of the input and what this extends. 1832 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); 1833 Tmp = VTBits-Tmp+1; 1834 1835 Tmp2 = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1836 return std::max(Tmp, Tmp2); 1837 1838 case ISD::SRA: 1839 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1840 // SRA X, C -> adds C sign bits. 1841 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1842 Tmp += C->getZExtValue(); 1843 if (Tmp > VTBits) Tmp = VTBits; 1844 } 1845 return Tmp; 1846 case ISD::SHL: 1847 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1848 // shl destroys sign bits. 1849 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1850 if (C->getZExtValue() >= VTBits || // Bad shift. 1851 C->getZExtValue() >= Tmp) break; // Shifted all sign bits out. 1852 return Tmp - C->getZExtValue(); 1853 } 1854 break; 1855 case ISD::AND: 1856 case ISD::OR: 1857 case ISD::XOR: // NOT is handled here. 1858 // Logical binary ops preserve the number of sign bits at the worst. 1859 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1860 if (Tmp != 1) { 1861 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 1862 FirstAnswer = std::min(Tmp, Tmp2); 1863 // We computed what we know about the sign bits as our first 1864 // answer. Now proceed to the generic code that uses 1865 // ComputeMaskedBits, and pick whichever answer is better. 1866 } 1867 break; 1868 1869 case ISD::SELECT: 1870 Tmp = ComputeNumSignBits(Op.getOperand(1), Depth+1); 1871 if (Tmp == 1) return 1; // Early out. 1872 Tmp2 = ComputeNumSignBits(Op.getOperand(2), Depth+1); 1873 return std::min(Tmp, Tmp2); 1874 1875 case ISD::SETCC: 1876 // If setcc returns 0/-1, all bits are sign bits. 1877 if (TLI.getSetCCResultContents() == 1878 TargetLowering::ZeroOrNegativeOneSetCCResult) 1879 return VTBits; 1880 break; 1881 case ISD::ROTL: 1882 case ISD::ROTR: 1883 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1884 unsigned RotAmt = C->getZExtValue() & (VTBits-1); 1885 1886 // Handle rotate right by N like a rotate left by 32-N. 1887 if (Op.getOpcode() == ISD::ROTR) 1888 RotAmt = (VTBits-RotAmt) & (VTBits-1); 1889 1890 // If we aren't rotating out all of the known-in sign bits, return the 1891 // number that are left. This handles rotl(sext(x), 1) for example. 1892 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1893 if (Tmp > RotAmt+1) return Tmp-RotAmt; 1894 } 1895 break; 1896 case ISD::ADD: 1897 // Add can have at most one carry bit. Thus we know that the output 1898 // is, at worst, one more bit than the inputs. 1899 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1900 if (Tmp == 1) return 1; // Early out. 1901 1902 // Special case decrementing a value (ADD X, -1): 1903 if (ConstantSDNode *CRHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) 1904 if (CRHS->isAllOnesValue()) { 1905 APInt KnownZero, KnownOne; 1906 APInt Mask = APInt::getAllOnesValue(VTBits); 1907 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1); 1908 1909 // If the input is known to be 0 or 1, the output is 0/-1, which is all 1910 // sign bits set. 1911 if ((KnownZero | APInt(VTBits, 1)) == Mask) 1912 return VTBits; 1913 1914 // If we are subtracting one from a positive number, there is no carry 1915 // out of the result. 1916 if (KnownZero.isNegative()) 1917 return Tmp; 1918 } 1919 1920 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 1921 if (Tmp2 == 1) return 1; 1922 return std::min(Tmp, Tmp2)-1; 1923 break; 1924 1925 case ISD::SUB: 1926 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 1927 if (Tmp2 == 1) return 1; 1928 1929 // Handle NEG. 1930 if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) 1931 if (CLHS->isNullValue()) { 1932 APInt KnownZero, KnownOne; 1933 APInt Mask = APInt::getAllOnesValue(VTBits); 1934 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1935 // If the input is known to be 0 or 1, the output is 0/-1, which is all 1936 // sign bits set. 1937 if ((KnownZero | APInt(VTBits, 1)) == Mask) 1938 return VTBits; 1939 1940 // If the input is known to be positive (the sign bit is known clear), 1941 // the output of the NEG has the same number of sign bits as the input. 1942 if (KnownZero.isNegative()) 1943 return Tmp2; 1944 1945 // Otherwise, we treat this like a SUB. 1946 } 1947 1948 // Sub can have at most one carry bit. Thus we know that the output 1949 // is, at worst, one more bit than the inputs. 1950 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1951 if (Tmp == 1) return 1; // Early out. 1952 return std::min(Tmp, Tmp2)-1; 1953 break; 1954 case ISD::TRUNCATE: 1955 // FIXME: it's tricky to do anything useful for this, but it is an important 1956 // case for targets like X86. 1957 break; 1958 } 1959 1960 // Handle LOADX separately here. EXTLOAD case will fallthrough. 1961 if (Op.getOpcode() == ISD::LOAD) { 1962 LoadSDNode *LD = cast<LoadSDNode>(Op); 1963 unsigned ExtType = LD->getExtensionType(); 1964 switch (ExtType) { 1965 default: break; 1966 case ISD::SEXTLOAD: // '17' bits known 1967 Tmp = LD->getMemoryVT().getSizeInBits(); 1968 return VTBits-Tmp+1; 1969 case ISD::ZEXTLOAD: // '16' bits known 1970 Tmp = LD->getMemoryVT().getSizeInBits(); 1971 return VTBits-Tmp; 1972 } 1973 } 1974 1975 // Allow the target to implement this method for its nodes. 1976 if (Op.getOpcode() >= ISD::BUILTIN_OP_END || 1977 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1978 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1979 Op.getOpcode() == ISD::INTRINSIC_VOID) { 1980 unsigned NumBits = TLI.ComputeNumSignBitsForTargetNode(Op, Depth); 1981 if (NumBits > 1) FirstAnswer = std::max(FirstAnswer, NumBits); 1982 } 1983 1984 // Finally, if we can prove that the top bits of the result are 0's or 1's, 1985 // use this information. 1986 APInt KnownZero, KnownOne; 1987 APInt Mask = APInt::getAllOnesValue(VTBits); 1988 ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth); 1989 1990 if (KnownZero.isNegative()) { // sign bit is 0 1991 Mask = KnownZero; 1992 } else if (KnownOne.isNegative()) { // sign bit is 1; 1993 Mask = KnownOne; 1994 } else { 1995 // Nothing known. 1996 return FirstAnswer; 1997 } 1998 1999 // Okay, we know that the sign bit in Mask is set. Use CLZ to determine 2000 // the number of identical bits in the top of the input value. 2001 Mask = ~Mask; 2002 Mask <<= Mask.getBitWidth()-VTBits; 2003 // Return # leading zeros. We use 'min' here in case Val was zero before 2004 // shifting. We don't want to return '64' as for an i32 "0". 2005 return std::max(FirstAnswer, std::min(VTBits, Mask.countLeadingZeros())); 2006} 2007 2008 2009bool SelectionDAG::isVerifiedDebugInfoDesc(SDValue Op) const { 2010 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op); 2011 if (!GA) return false; 2012 GlobalVariable *GV = dyn_cast<GlobalVariable>(GA->getGlobal()); 2013 if (!GV) return false; 2014 MachineModuleInfo *MMI = getMachineModuleInfo(); 2015 return MMI && MMI->hasDebugInfo() && MMI->isVerified(GV); 2016} 2017 2018 2019/// getShuffleScalarElt - Returns the scalar element that will make up the ith 2020/// element of the result of the vector shuffle. 2021SDValue SelectionDAG::getShuffleScalarElt(const SDNode *N, unsigned i) { 2022 MVT VT = N->getValueType(0); 2023 SDValue PermMask = N->getOperand(2); 2024 SDValue Idx = PermMask.getOperand(i); 2025 if (Idx.getOpcode() == ISD::UNDEF) 2026 return getNode(ISD::UNDEF, VT.getVectorElementType()); 2027 unsigned Index = cast<ConstantSDNode>(Idx)->getZExtValue(); 2028 unsigned NumElems = PermMask.getNumOperands(); 2029 SDValue V = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1); 2030 Index %= NumElems; 2031 2032 if (V.getOpcode() == ISD::BIT_CONVERT) { 2033 V = V.getOperand(0); 2034 if (V.getValueType().getVectorNumElements() != NumElems) 2035 return SDValue(); 2036 } 2037 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) 2038 return (Index == 0) ? V.getOperand(0) 2039 : getNode(ISD::UNDEF, VT.getVectorElementType()); 2040 if (V.getOpcode() == ISD::BUILD_VECTOR) 2041 return V.getOperand(Index); 2042 if (V.getOpcode() == ISD::VECTOR_SHUFFLE) 2043 return getShuffleScalarElt(V.getNode(), Index); 2044 return SDValue(); 2045} 2046 2047 2048/// getNode - Gets or creates the specified node. 2049/// 2050SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT) { 2051 FoldingSetNodeID ID; 2052 AddNodeIDNode(ID, Opcode, getVTList(VT), 0, 0); 2053 void *IP = 0; 2054 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2055 return SDValue(E, 0); 2056 SDNode *N = NodeAllocator.Allocate<SDNode>(); 2057 new (N) SDNode(Opcode, SDNode::getSDVTList(VT)); 2058 CSEMap.InsertNode(N, IP); 2059 2060 AllNodes.push_back(N); 2061#ifndef NDEBUG 2062 VerifyNode(N); 2063#endif 2064 return SDValue(N, 0); 2065} 2066 2067SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, SDValue Operand) { 2068 // Constant fold unary operations with an integer constant operand. 2069 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Operand.getNode())) { 2070 const APInt &Val = C->getAPIntValue(); 2071 unsigned BitWidth = VT.getSizeInBits(); 2072 switch (Opcode) { 2073 default: break; 2074 case ISD::SIGN_EXTEND: 2075 return getConstant(APInt(Val).sextOrTrunc(BitWidth), VT); 2076 case ISD::ANY_EXTEND: 2077 case ISD::ZERO_EXTEND: 2078 case ISD::TRUNCATE: 2079 return getConstant(APInt(Val).zextOrTrunc(BitWidth), VT); 2080 case ISD::UINT_TO_FP: 2081 case ISD::SINT_TO_FP: { 2082 const uint64_t zero[] = {0, 0}; 2083 // No compile time operations on this type. 2084 if (VT==MVT::ppcf128) 2085 break; 2086 APFloat apf = APFloat(APInt(BitWidth, 2, zero)); 2087 (void)apf.convertFromAPInt(Val, 2088 Opcode==ISD::SINT_TO_FP, 2089 APFloat::rmNearestTiesToEven); 2090 return getConstantFP(apf, VT); 2091 } 2092 case ISD::BIT_CONVERT: 2093 if (VT == MVT::f32 && C->getValueType(0) == MVT::i32) 2094 return getConstantFP(Val.bitsToFloat(), VT); 2095 else if (VT == MVT::f64 && C->getValueType(0) == MVT::i64) 2096 return getConstantFP(Val.bitsToDouble(), VT); 2097 break; 2098 case ISD::BSWAP: 2099 return getConstant(Val.byteSwap(), VT); 2100 case ISD::CTPOP: 2101 return getConstant(Val.countPopulation(), VT); 2102 case ISD::CTLZ: 2103 return getConstant(Val.countLeadingZeros(), VT); 2104 case ISD::CTTZ: 2105 return getConstant(Val.countTrailingZeros(), VT); 2106 } 2107 } 2108 2109 // Constant fold unary operations with a floating point constant operand. 2110 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Operand.getNode())) { 2111 APFloat V = C->getValueAPF(); // make copy 2112 if (VT != MVT::ppcf128 && Operand.getValueType() != MVT::ppcf128) { 2113 switch (Opcode) { 2114 case ISD::FNEG: 2115 V.changeSign(); 2116 return getConstantFP(V, VT); 2117 case ISD::FABS: 2118 V.clearSign(); 2119 return getConstantFP(V, VT); 2120 case ISD::FP_ROUND: 2121 case ISD::FP_EXTEND: 2122 // This can return overflow, underflow, or inexact; we don't care. 2123 // FIXME need to be more flexible about rounding mode. 2124 (void)V.convert(*MVTToAPFloatSemantics(VT), 2125 APFloat::rmNearestTiesToEven); 2126 return getConstantFP(V, VT); 2127 case ISD::FP_TO_SINT: 2128 case ISD::FP_TO_UINT: { 2129 integerPart x; 2130 assert(integerPartWidth >= 64); 2131 // FIXME need to be more flexible about rounding mode. 2132 APFloat::opStatus s = V.convertToInteger(&x, 64U, 2133 Opcode==ISD::FP_TO_SINT, 2134 APFloat::rmTowardZero); 2135 if (s==APFloat::opInvalidOp) // inexact is OK, in fact usual 2136 break; 2137 return getConstant(x, VT); 2138 } 2139 case ISD::BIT_CONVERT: 2140 if (VT == MVT::i32 && C->getValueType(0) == MVT::f32) 2141 return getConstant((uint32_t)V.convertToAPInt().getZExtValue(), VT); 2142 else if (VT == MVT::i64 && C->getValueType(0) == MVT::f64) 2143 return getConstant(V.convertToAPInt().getZExtValue(), VT); 2144 break; 2145 } 2146 } 2147 } 2148 2149 unsigned OpOpcode = Operand.getNode()->getOpcode(); 2150 switch (Opcode) { 2151 case ISD::TokenFactor: 2152 case ISD::CONCAT_VECTORS: 2153 return Operand; // Factor or concat of one node? No need. 2154 case ISD::FP_ROUND: assert(0 && "Invalid method to make FP_ROUND node"); 2155 case ISD::FP_EXTEND: 2156 assert(VT.isFloatingPoint() && 2157 Operand.getValueType().isFloatingPoint() && "Invalid FP cast!"); 2158 if (Operand.getValueType() == VT) return Operand; // noop conversion. 2159 if (Operand.getOpcode() == ISD::UNDEF) 2160 return getNode(ISD::UNDEF, VT); 2161 break; 2162 case ISD::SIGN_EXTEND: 2163 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2164 "Invalid SIGN_EXTEND!"); 2165 if (Operand.getValueType() == VT) return Operand; // noop extension 2166 assert(Operand.getValueType().bitsLT(VT) 2167 && "Invalid sext node, dst < src!"); 2168 if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND) 2169 return getNode(OpOpcode, VT, Operand.getNode()->getOperand(0)); 2170 break; 2171 case ISD::ZERO_EXTEND: 2172 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2173 "Invalid ZERO_EXTEND!"); 2174 if (Operand.getValueType() == VT) return Operand; // noop extension 2175 assert(Operand.getValueType().bitsLT(VT) 2176 && "Invalid zext node, dst < src!"); 2177 if (OpOpcode == ISD::ZERO_EXTEND) // (zext (zext x)) -> (zext x) 2178 return getNode(ISD::ZERO_EXTEND, VT, Operand.getNode()->getOperand(0)); 2179 break; 2180 case ISD::ANY_EXTEND: 2181 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2182 "Invalid ANY_EXTEND!"); 2183 if (Operand.getValueType() == VT) return Operand; // noop extension 2184 assert(Operand.getValueType().bitsLT(VT) 2185 && "Invalid anyext node, dst < src!"); 2186 if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND) 2187 // (ext (zext x)) -> (zext x) and (ext (sext x)) -> (sext x) 2188 return getNode(OpOpcode, VT, Operand.getNode()->getOperand(0)); 2189 break; 2190 case ISD::TRUNCATE: 2191 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2192 "Invalid TRUNCATE!"); 2193 if (Operand.getValueType() == VT) return Operand; // noop truncate 2194 assert(Operand.getValueType().bitsGT(VT) 2195 && "Invalid truncate node, src < dst!"); 2196 if (OpOpcode == ISD::TRUNCATE) 2197 return getNode(ISD::TRUNCATE, VT, Operand.getNode()->getOperand(0)); 2198 else if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND || 2199 OpOpcode == ISD::ANY_EXTEND) { 2200 // If the source is smaller than the dest, we still need an extend. 2201 if (Operand.getNode()->getOperand(0).getValueType().bitsLT(VT)) 2202 return getNode(OpOpcode, VT, Operand.getNode()->getOperand(0)); 2203 else if (Operand.getNode()->getOperand(0).getValueType().bitsGT(VT)) 2204 return getNode(ISD::TRUNCATE, VT, Operand.getNode()->getOperand(0)); 2205 else 2206 return Operand.getNode()->getOperand(0); 2207 } 2208 break; 2209 case ISD::BIT_CONVERT: 2210 // Basic sanity checking. 2211 assert(VT.getSizeInBits() == Operand.getValueType().getSizeInBits() 2212 && "Cannot BIT_CONVERT between types of different sizes!"); 2213 if (VT == Operand.getValueType()) return Operand; // noop conversion. 2214 if (OpOpcode == ISD::BIT_CONVERT) // bitconv(bitconv(x)) -> bitconv(x) 2215 return getNode(ISD::BIT_CONVERT, VT, Operand.getOperand(0)); 2216 if (OpOpcode == ISD::UNDEF) 2217 return getNode(ISD::UNDEF, VT); 2218 break; 2219 case ISD::SCALAR_TO_VECTOR: 2220 assert(VT.isVector() && !Operand.getValueType().isVector() && 2221 VT.getVectorElementType() == Operand.getValueType() && 2222 "Illegal SCALAR_TO_VECTOR node!"); 2223 if (OpOpcode == ISD::UNDEF) 2224 return getNode(ISD::UNDEF, VT); 2225 // scalar_to_vector(extract_vector_elt V, 0) -> V, top bits are undefined. 2226 if (OpOpcode == ISD::EXTRACT_VECTOR_ELT && 2227 isa<ConstantSDNode>(Operand.getOperand(1)) && 2228 Operand.getConstantOperandVal(1) == 0 && 2229 Operand.getOperand(0).getValueType() == VT) 2230 return Operand.getOperand(0); 2231 break; 2232 case ISD::FNEG: 2233 if (OpOpcode == ISD::FSUB) // -(X-Y) -> (Y-X) 2234 return getNode(ISD::FSUB, VT, Operand.getNode()->getOperand(1), 2235 Operand.getNode()->getOperand(0)); 2236 if (OpOpcode == ISD::FNEG) // --X -> X 2237 return Operand.getNode()->getOperand(0); 2238 break; 2239 case ISD::FABS: 2240 if (OpOpcode == ISD::FNEG) // abs(-X) -> abs(X) 2241 return getNode(ISD::FABS, VT, Operand.getNode()->getOperand(0)); 2242 break; 2243 } 2244 2245 SDNode *N; 2246 SDVTList VTs = getVTList(VT); 2247 if (VT != MVT::Flag) { // Don't CSE flag producing nodes 2248 FoldingSetNodeID ID; 2249 SDValue Ops[1] = { Operand }; 2250 AddNodeIDNode(ID, Opcode, VTs, Ops, 1); 2251 void *IP = 0; 2252 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2253 return SDValue(E, 0); 2254 N = NodeAllocator.Allocate<UnarySDNode>(); 2255 new (N) UnarySDNode(Opcode, VTs, Operand); 2256 CSEMap.InsertNode(N, IP); 2257 } else { 2258 N = NodeAllocator.Allocate<UnarySDNode>(); 2259 new (N) UnarySDNode(Opcode, VTs, Operand); 2260 } 2261 2262 AllNodes.push_back(N); 2263#ifndef NDEBUG 2264 VerifyNode(N); 2265#endif 2266 return SDValue(N, 0); 2267} 2268 2269SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, 2270 SDValue N1, SDValue N2) { 2271 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 2272 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 2273 switch (Opcode) { 2274 default: break; 2275 case ISD::TokenFactor: 2276 assert(VT == MVT::Other && N1.getValueType() == MVT::Other && 2277 N2.getValueType() == MVT::Other && "Invalid token factor!"); 2278 // Fold trivial token factors. 2279 if (N1.getOpcode() == ISD::EntryToken) return N2; 2280 if (N2.getOpcode() == ISD::EntryToken) return N1; 2281 break; 2282 case ISD::CONCAT_VECTORS: 2283 // A CONCAT_VECTOR with all operands BUILD_VECTOR can be simplified to 2284 // one big BUILD_VECTOR. 2285 if (N1.getOpcode() == ISD::BUILD_VECTOR && 2286 N2.getOpcode() == ISD::BUILD_VECTOR) { 2287 SmallVector<SDValue, 16> Elts(N1.getNode()->op_begin(), N1.getNode()->op_end()); 2288 Elts.insert(Elts.end(), N2.getNode()->op_begin(), N2.getNode()->op_end()); 2289 return getNode(ISD::BUILD_VECTOR, VT, &Elts[0], Elts.size()); 2290 } 2291 break; 2292 case ISD::AND: 2293 assert(VT.isInteger() && N1.getValueType() == N2.getValueType() && 2294 N1.getValueType() == VT && "Binary operator types must match!"); 2295 // (X & 0) -> 0. This commonly occurs when legalizing i64 values, so it's 2296 // worth handling here. 2297 if (N2C && N2C->isNullValue()) 2298 return N2; 2299 if (N2C && N2C->isAllOnesValue()) // X & -1 -> X 2300 return N1; 2301 break; 2302 case ISD::OR: 2303 case ISD::XOR: 2304 case ISD::ADD: 2305 case ISD::SUB: 2306 assert(VT.isInteger() && N1.getValueType() == N2.getValueType() && 2307 N1.getValueType() == VT && "Binary operator types must match!"); 2308 // (X ^|+- 0) -> X. This commonly occurs when legalizing i64 values, so 2309 // it's worth handling here. 2310 if (N2C && N2C->isNullValue()) 2311 return N1; 2312 break; 2313 case ISD::UDIV: 2314 case ISD::UREM: 2315 case ISD::MULHU: 2316 case ISD::MULHS: 2317 assert(VT.isInteger() && "This operator does not apply to FP types!"); 2318 // fall through 2319 case ISD::MUL: 2320 case ISD::SDIV: 2321 case ISD::SREM: 2322 case ISD::FADD: 2323 case ISD::FSUB: 2324 case ISD::FMUL: 2325 case ISD::FDIV: 2326 case ISD::FREM: 2327 assert(N1.getValueType() == N2.getValueType() && 2328 N1.getValueType() == VT && "Binary operator types must match!"); 2329 break; 2330 case ISD::FCOPYSIGN: // N1 and result must match. N1/N2 need not match. 2331 assert(N1.getValueType() == VT && 2332 N1.getValueType().isFloatingPoint() && 2333 N2.getValueType().isFloatingPoint() && 2334 "Invalid FCOPYSIGN!"); 2335 break; 2336 case ISD::SHL: 2337 case ISD::SRA: 2338 case ISD::SRL: 2339 case ISD::ROTL: 2340 case ISD::ROTR: 2341 assert(VT == N1.getValueType() && 2342 "Shift operators return type must be the same as their first arg"); 2343 assert(VT.isInteger() && N2.getValueType().isInteger() && 2344 "Shifts only work on integers"); 2345 2346 // Always fold shifts of i1 values so the code generator doesn't need to 2347 // handle them. Since we know the size of the shift has to be less than the 2348 // size of the value, the shift/rotate count is guaranteed to be zero. 2349 if (VT == MVT::i1) 2350 return N1; 2351 break; 2352 case ISD::FP_ROUND_INREG: { 2353 MVT EVT = cast<VTSDNode>(N2)->getVT(); 2354 assert(VT == N1.getValueType() && "Not an inreg round!"); 2355 assert(VT.isFloatingPoint() && EVT.isFloatingPoint() && 2356 "Cannot FP_ROUND_INREG integer types"); 2357 assert(EVT.bitsLE(VT) && "Not rounding down!"); 2358 if (cast<VTSDNode>(N2)->getVT() == VT) return N1; // Not actually rounding. 2359 break; 2360 } 2361 case ISD::FP_ROUND: 2362 assert(VT.isFloatingPoint() && 2363 N1.getValueType().isFloatingPoint() && 2364 VT.bitsLE(N1.getValueType()) && 2365 isa<ConstantSDNode>(N2) && "Invalid FP_ROUND!"); 2366 if (N1.getValueType() == VT) return N1; // noop conversion. 2367 break; 2368 case ISD::AssertSext: 2369 case ISD::AssertZext: { 2370 MVT EVT = cast<VTSDNode>(N2)->getVT(); 2371 assert(VT == N1.getValueType() && "Not an inreg extend!"); 2372 assert(VT.isInteger() && EVT.isInteger() && 2373 "Cannot *_EXTEND_INREG FP types"); 2374 assert(EVT.bitsLE(VT) && "Not extending!"); 2375 if (VT == EVT) return N1; // noop assertion. 2376 break; 2377 } 2378 case ISD::SIGN_EXTEND_INREG: { 2379 MVT EVT = cast<VTSDNode>(N2)->getVT(); 2380 assert(VT == N1.getValueType() && "Not an inreg extend!"); 2381 assert(VT.isInteger() && EVT.isInteger() && 2382 "Cannot *_EXTEND_INREG FP types"); 2383 assert(EVT.bitsLE(VT) && "Not extending!"); 2384 if (EVT == VT) return N1; // Not actually extending 2385 2386 if (N1C) { 2387 APInt Val = N1C->getAPIntValue(); 2388 unsigned FromBits = cast<VTSDNode>(N2)->getVT().getSizeInBits(); 2389 Val <<= Val.getBitWidth()-FromBits; 2390 Val = Val.ashr(Val.getBitWidth()-FromBits); 2391 return getConstant(Val, VT); 2392 } 2393 break; 2394 } 2395 case ISD::EXTRACT_VECTOR_ELT: 2396 // EXTRACT_VECTOR_ELT of an UNDEF is an UNDEF. 2397 if (N1.getOpcode() == ISD::UNDEF) 2398 return getNode(ISD::UNDEF, VT); 2399 2400 // EXTRACT_VECTOR_ELT of CONCAT_VECTORS is often formed while lowering is 2401 // expanding copies of large vectors from registers. 2402 if (N2C && 2403 N1.getOpcode() == ISD::CONCAT_VECTORS && 2404 N1.getNumOperands() > 0) { 2405 unsigned Factor = 2406 N1.getOperand(0).getValueType().getVectorNumElements(); 2407 return getNode(ISD::EXTRACT_VECTOR_ELT, VT, 2408 N1.getOperand(N2C->getZExtValue() / Factor), 2409 getConstant(N2C->getZExtValue() % Factor, 2410 N2.getValueType())); 2411 } 2412 2413 // EXTRACT_VECTOR_ELT of BUILD_VECTOR is often formed while lowering is 2414 // expanding large vector constants. 2415 if (N2C && N1.getOpcode() == ISD::BUILD_VECTOR) 2416 return N1.getOperand(N2C->getZExtValue()); 2417 2418 // EXTRACT_VECTOR_ELT of INSERT_VECTOR_ELT is often formed when vector 2419 // operations are lowered to scalars. 2420 if (N1.getOpcode() == ISD::INSERT_VECTOR_ELT) { 2421 if (N1.getOperand(2) == N2) 2422 return N1.getOperand(1); 2423 else 2424 return getNode(ISD::EXTRACT_VECTOR_ELT, VT, N1.getOperand(0), N2); 2425 } 2426 break; 2427 case ISD::EXTRACT_ELEMENT: 2428 assert(N2C && (unsigned)N2C->getZExtValue() < 2 && "Bad EXTRACT_ELEMENT!"); 2429 assert(!N1.getValueType().isVector() && !VT.isVector() && 2430 (N1.getValueType().isInteger() == VT.isInteger()) && 2431 "Wrong types for EXTRACT_ELEMENT!"); 2432 2433 // EXTRACT_ELEMENT of BUILD_PAIR is often formed while legalize is expanding 2434 // 64-bit integers into 32-bit parts. Instead of building the extract of 2435 // the BUILD_PAIR, only to have legalize rip it apart, just do it now. 2436 if (N1.getOpcode() == ISD::BUILD_PAIR) 2437 return N1.getOperand(N2C->getZExtValue()); 2438 2439 // EXTRACT_ELEMENT of a constant int is also very common. 2440 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) { 2441 unsigned ElementSize = VT.getSizeInBits(); 2442 unsigned Shift = ElementSize * N2C->getZExtValue(); 2443 APInt ShiftedVal = C->getAPIntValue().lshr(Shift); 2444 return getConstant(ShiftedVal.trunc(ElementSize), VT); 2445 } 2446 break; 2447 case ISD::EXTRACT_SUBVECTOR: 2448 if (N1.getValueType() == VT) // Trivial extraction. 2449 return N1; 2450 break; 2451 } 2452 2453 if (N1C) { 2454 if (N2C) { 2455 const APInt &C1 = N1C->getAPIntValue(), &C2 = N2C->getAPIntValue(); 2456 switch (Opcode) { 2457 case ISD::ADD: return getConstant(C1 + C2, VT); 2458 case ISD::SUB: return getConstant(C1 - C2, VT); 2459 case ISD::MUL: return getConstant(C1 * C2, VT); 2460 case ISD::UDIV: 2461 if (C2.getBoolValue()) return getConstant(C1.udiv(C2), VT); 2462 break; 2463 case ISD::UREM : 2464 if (C2.getBoolValue()) return getConstant(C1.urem(C2), VT); 2465 break; 2466 case ISD::SDIV : 2467 if (C2.getBoolValue()) return getConstant(C1.sdiv(C2), VT); 2468 break; 2469 case ISD::SREM : 2470 if (C2.getBoolValue()) return getConstant(C1.srem(C2), VT); 2471 break; 2472 case ISD::AND : return getConstant(C1 & C2, VT); 2473 case ISD::OR : return getConstant(C1 | C2, VT); 2474 case ISD::XOR : return getConstant(C1 ^ C2, VT); 2475 case ISD::SHL : return getConstant(C1 << C2, VT); 2476 case ISD::SRL : return getConstant(C1.lshr(C2), VT); 2477 case ISD::SRA : return getConstant(C1.ashr(C2), VT); 2478 case ISD::ROTL : return getConstant(C1.rotl(C2), VT); 2479 case ISD::ROTR : return getConstant(C1.rotr(C2), VT); 2480 default: break; 2481 } 2482 } else { // Cannonicalize constant to RHS if commutative 2483 if (isCommutativeBinOp(Opcode)) { 2484 std::swap(N1C, N2C); 2485 std::swap(N1, N2); 2486 } 2487 } 2488 } 2489 2490 // Constant fold FP operations. 2491 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1.getNode()); 2492 ConstantFPSDNode *N2CFP = dyn_cast<ConstantFPSDNode>(N2.getNode()); 2493 if (N1CFP) { 2494 if (!N2CFP && isCommutativeBinOp(Opcode)) { 2495 // Cannonicalize constant to RHS if commutative 2496 std::swap(N1CFP, N2CFP); 2497 std::swap(N1, N2); 2498 } else if (N2CFP && VT != MVT::ppcf128) { 2499 APFloat V1 = N1CFP->getValueAPF(), V2 = N2CFP->getValueAPF(); 2500 APFloat::opStatus s; 2501 switch (Opcode) { 2502 case ISD::FADD: 2503 s = V1.add(V2, APFloat::rmNearestTiesToEven); 2504 if (s != APFloat::opInvalidOp) 2505 return getConstantFP(V1, VT); 2506 break; 2507 case ISD::FSUB: 2508 s = V1.subtract(V2, APFloat::rmNearestTiesToEven); 2509 if (s!=APFloat::opInvalidOp) 2510 return getConstantFP(V1, VT); 2511 break; 2512 case ISD::FMUL: 2513 s = V1.multiply(V2, APFloat::rmNearestTiesToEven); 2514 if (s!=APFloat::opInvalidOp) 2515 return getConstantFP(V1, VT); 2516 break; 2517 case ISD::FDIV: 2518 s = V1.divide(V2, APFloat::rmNearestTiesToEven); 2519 if (s!=APFloat::opInvalidOp && s!=APFloat::opDivByZero) 2520 return getConstantFP(V1, VT); 2521 break; 2522 case ISD::FREM : 2523 s = V1.mod(V2, APFloat::rmNearestTiesToEven); 2524 if (s!=APFloat::opInvalidOp && s!=APFloat::opDivByZero) 2525 return getConstantFP(V1, VT); 2526 break; 2527 case ISD::FCOPYSIGN: 2528 V1.copySign(V2); 2529 return getConstantFP(V1, VT); 2530 default: break; 2531 } 2532 } 2533 } 2534 2535 // Canonicalize an UNDEF to the RHS, even over a constant. 2536 if (N1.getOpcode() == ISD::UNDEF) { 2537 if (isCommutativeBinOp(Opcode)) { 2538 std::swap(N1, N2); 2539 } else { 2540 switch (Opcode) { 2541 case ISD::FP_ROUND_INREG: 2542 case ISD::SIGN_EXTEND_INREG: 2543 case ISD::SUB: 2544 case ISD::FSUB: 2545 case ISD::FDIV: 2546 case ISD::FREM: 2547 case ISD::SRA: 2548 return N1; // fold op(undef, arg2) -> undef 2549 case ISD::UDIV: 2550 case ISD::SDIV: 2551 case ISD::UREM: 2552 case ISD::SREM: 2553 case ISD::SRL: 2554 case ISD::SHL: 2555 if (!VT.isVector()) 2556 return getConstant(0, VT); // fold op(undef, arg2) -> 0 2557 // For vectors, we can't easily build an all zero vector, just return 2558 // the LHS. 2559 return N2; 2560 } 2561 } 2562 } 2563 2564 // Fold a bunch of operators when the RHS is undef. 2565 if (N2.getOpcode() == ISD::UNDEF) { 2566 switch (Opcode) { 2567 case ISD::XOR: 2568 if (N1.getOpcode() == ISD::UNDEF) 2569 // Handle undef ^ undef -> 0 special case. This is a common 2570 // idiom (misuse). 2571 return getConstant(0, VT); 2572 // fallthrough 2573 case ISD::ADD: 2574 case ISD::ADDC: 2575 case ISD::ADDE: 2576 case ISD::SUB: 2577 case ISD::FADD: 2578 case ISD::FSUB: 2579 case ISD::FMUL: 2580 case ISD::FDIV: 2581 case ISD::FREM: 2582 case ISD::UDIV: 2583 case ISD::SDIV: 2584 case ISD::UREM: 2585 case ISD::SREM: 2586 return N2; // fold op(arg1, undef) -> undef 2587 case ISD::MUL: 2588 case ISD::AND: 2589 case ISD::SRL: 2590 case ISD::SHL: 2591 if (!VT.isVector()) 2592 return getConstant(0, VT); // fold op(arg1, undef) -> 0 2593 // For vectors, we can't easily build an all zero vector, just return 2594 // the LHS. 2595 return N1; 2596 case ISD::OR: 2597 if (!VT.isVector()) 2598 return getConstant(VT.getIntegerVTBitMask(), VT); 2599 // For vectors, we can't easily build an all one vector, just return 2600 // the LHS. 2601 return N1; 2602 case ISD::SRA: 2603 return N1; 2604 } 2605 } 2606 2607 // Memoize this node if possible. 2608 SDNode *N; 2609 SDVTList VTs = getVTList(VT); 2610 if (VT != MVT::Flag) { 2611 SDValue Ops[] = { N1, N2 }; 2612 FoldingSetNodeID ID; 2613 AddNodeIDNode(ID, Opcode, VTs, Ops, 2); 2614 void *IP = 0; 2615 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2616 return SDValue(E, 0); 2617 N = NodeAllocator.Allocate<BinarySDNode>(); 2618 new (N) BinarySDNode(Opcode, VTs, N1, N2); 2619 CSEMap.InsertNode(N, IP); 2620 } else { 2621 N = NodeAllocator.Allocate<BinarySDNode>(); 2622 new (N) BinarySDNode(Opcode, VTs, N1, N2); 2623 } 2624 2625 AllNodes.push_back(N); 2626#ifndef NDEBUG 2627 VerifyNode(N); 2628#endif 2629 return SDValue(N, 0); 2630} 2631 2632SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, 2633 SDValue N1, SDValue N2, SDValue N3) { 2634 // Perform various simplifications. 2635 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 2636 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 2637 switch (Opcode) { 2638 case ISD::CONCAT_VECTORS: 2639 // A CONCAT_VECTOR with all operands BUILD_VECTOR can be simplified to 2640 // one big BUILD_VECTOR. 2641 if (N1.getOpcode() == ISD::BUILD_VECTOR && 2642 N2.getOpcode() == ISD::BUILD_VECTOR && 2643 N3.getOpcode() == ISD::BUILD_VECTOR) { 2644 SmallVector<SDValue, 16> Elts(N1.getNode()->op_begin(), N1.getNode()->op_end()); 2645 Elts.insert(Elts.end(), N2.getNode()->op_begin(), N2.getNode()->op_end()); 2646 Elts.insert(Elts.end(), N3.getNode()->op_begin(), N3.getNode()->op_end()); 2647 return getNode(ISD::BUILD_VECTOR, VT, &Elts[0], Elts.size()); 2648 } 2649 break; 2650 case ISD::SETCC: { 2651 // Use FoldSetCC to simplify SETCC's. 2652 SDValue Simp = FoldSetCC(VT, N1, N2, cast<CondCodeSDNode>(N3)->get()); 2653 if (Simp.getNode()) return Simp; 2654 break; 2655 } 2656 case ISD::SELECT: 2657 if (N1C) { 2658 if (N1C->getZExtValue()) 2659 return N2; // select true, X, Y -> X 2660 else 2661 return N3; // select false, X, Y -> Y 2662 } 2663 2664 if (N2 == N3) return N2; // select C, X, X -> X 2665 break; 2666 case ISD::BRCOND: 2667 if (N2C) { 2668 if (N2C->getZExtValue()) // Unconditional branch 2669 return getNode(ISD::BR, MVT::Other, N1, N3); 2670 else 2671 return N1; // Never-taken branch 2672 } 2673 break; 2674 case ISD::VECTOR_SHUFFLE: 2675 assert(VT == N1.getValueType() && VT == N2.getValueType() && 2676 VT.isVector() && N3.getValueType().isVector() && 2677 N3.getOpcode() == ISD::BUILD_VECTOR && 2678 VT.getVectorNumElements() == N3.getNumOperands() && 2679 "Illegal VECTOR_SHUFFLE node!"); 2680 break; 2681 case ISD::BIT_CONVERT: 2682 // Fold bit_convert nodes from a type to themselves. 2683 if (N1.getValueType() == VT) 2684 return N1; 2685 break; 2686 } 2687 2688 // Memoize node if it doesn't produce a flag. 2689 SDNode *N; 2690 SDVTList VTs = getVTList(VT); 2691 if (VT != MVT::Flag) { 2692 SDValue Ops[] = { N1, N2, N3 }; 2693 FoldingSetNodeID ID; 2694 AddNodeIDNode(ID, Opcode, VTs, Ops, 3); 2695 void *IP = 0; 2696 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2697 return SDValue(E, 0); 2698 N = NodeAllocator.Allocate<TernarySDNode>(); 2699 new (N) TernarySDNode(Opcode, VTs, N1, N2, N3); 2700 CSEMap.InsertNode(N, IP); 2701 } else { 2702 N = NodeAllocator.Allocate<TernarySDNode>(); 2703 new (N) TernarySDNode(Opcode, VTs, N1, N2, N3); 2704 } 2705 AllNodes.push_back(N); 2706#ifndef NDEBUG 2707 VerifyNode(N); 2708#endif 2709 return SDValue(N, 0); 2710} 2711 2712SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, 2713 SDValue N1, SDValue N2, SDValue N3, 2714 SDValue N4) { 2715 SDValue Ops[] = { N1, N2, N3, N4 }; 2716 return getNode(Opcode, VT, Ops, 4); 2717} 2718 2719SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, 2720 SDValue N1, SDValue N2, SDValue N3, 2721 SDValue N4, SDValue N5) { 2722 SDValue Ops[] = { N1, N2, N3, N4, N5 }; 2723 return getNode(Opcode, VT, Ops, 5); 2724} 2725 2726/// getMemsetValue - Vectorized representation of the memset value 2727/// operand. 2728static SDValue getMemsetValue(SDValue Value, MVT VT, SelectionDAG &DAG) { 2729 unsigned NumBits = VT.isVector() ? 2730 VT.getVectorElementType().getSizeInBits() : VT.getSizeInBits(); 2731 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) { 2732 APInt Val = APInt(NumBits, C->getZExtValue() & 255); 2733 unsigned Shift = 8; 2734 for (unsigned i = NumBits; i > 8; i >>= 1) { 2735 Val = (Val << Shift) | Val; 2736 Shift <<= 1; 2737 } 2738 if (VT.isInteger()) 2739 return DAG.getConstant(Val, VT); 2740 return DAG.getConstantFP(APFloat(Val), VT); 2741 } 2742 2743 Value = DAG.getNode(ISD::ZERO_EXTEND, VT, Value); 2744 unsigned Shift = 8; 2745 for (unsigned i = NumBits; i > 8; i >>= 1) { 2746 Value = DAG.getNode(ISD::OR, VT, 2747 DAG.getNode(ISD::SHL, VT, Value, 2748 DAG.getConstant(Shift, MVT::i8)), Value); 2749 Shift <<= 1; 2750 } 2751 2752 return Value; 2753} 2754 2755/// getMemsetStringVal - Similar to getMemsetValue. Except this is only 2756/// used when a memcpy is turned into a memset when the source is a constant 2757/// string ptr. 2758static SDValue getMemsetStringVal(MVT VT, SelectionDAG &DAG, 2759 const TargetLowering &TLI, 2760 std::string &Str, unsigned Offset) { 2761 // Handle vector with all elements zero. 2762 if (Str.empty()) { 2763 if (VT.isInteger()) 2764 return DAG.getConstant(0, VT); 2765 unsigned NumElts = VT.getVectorNumElements(); 2766 MVT EltVT = (VT.getVectorElementType() == MVT::f32) ? MVT::i32 : MVT::i64; 2767 return DAG.getNode(ISD::BIT_CONVERT, VT, 2768 DAG.getConstant(0, MVT::getVectorVT(EltVT, NumElts))); 2769 } 2770 2771 assert(!VT.isVector() && "Can't handle vector type here!"); 2772 unsigned NumBits = VT.getSizeInBits(); 2773 unsigned MSB = NumBits / 8; 2774 uint64_t Val = 0; 2775 if (TLI.isLittleEndian()) 2776 Offset = Offset + MSB - 1; 2777 for (unsigned i = 0; i != MSB; ++i) { 2778 Val = (Val << 8) | (unsigned char)Str[Offset]; 2779 Offset += TLI.isLittleEndian() ? -1 : 1; 2780 } 2781 return DAG.getConstant(Val, VT); 2782} 2783 2784/// getMemBasePlusOffset - Returns base and offset node for the 2785/// 2786static SDValue getMemBasePlusOffset(SDValue Base, unsigned Offset, 2787 SelectionDAG &DAG) { 2788 MVT VT = Base.getValueType(); 2789 return DAG.getNode(ISD::ADD, VT, Base, DAG.getConstant(Offset, VT)); 2790} 2791 2792/// isMemSrcFromString - Returns true if memcpy source is a string constant. 2793/// 2794static bool isMemSrcFromString(SDValue Src, std::string &Str) { 2795 unsigned SrcDelta = 0; 2796 GlobalAddressSDNode *G = NULL; 2797 if (Src.getOpcode() == ISD::GlobalAddress) 2798 G = cast<GlobalAddressSDNode>(Src); 2799 else if (Src.getOpcode() == ISD::ADD && 2800 Src.getOperand(0).getOpcode() == ISD::GlobalAddress && 2801 Src.getOperand(1).getOpcode() == ISD::Constant) { 2802 G = cast<GlobalAddressSDNode>(Src.getOperand(0)); 2803 SrcDelta = cast<ConstantSDNode>(Src.getOperand(1))->getZExtValue(); 2804 } 2805 if (!G) 2806 return false; 2807 2808 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal()); 2809 if (GV && GetConstantStringInfo(GV, Str, SrcDelta, false)) 2810 return true; 2811 2812 return false; 2813} 2814 2815/// MeetsMaxMemopRequirement - Determines if the number of memory ops required 2816/// to replace the memset / memcpy is below the threshold. It also returns the 2817/// types of the sequence of memory ops to perform memset / memcpy. 2818static 2819bool MeetsMaxMemopRequirement(std::vector<MVT> &MemOps, 2820 SDValue Dst, SDValue Src, 2821 unsigned Limit, uint64_t Size, unsigned &Align, 2822 std::string &Str, bool &isSrcStr, 2823 SelectionDAG &DAG, 2824 const TargetLowering &TLI) { 2825 isSrcStr = isMemSrcFromString(Src, Str); 2826 bool isSrcConst = isa<ConstantSDNode>(Src); 2827 bool AllowUnalign = TLI.allowsUnalignedMemoryAccesses(); 2828 MVT VT= TLI.getOptimalMemOpType(Size, Align, isSrcConst, isSrcStr); 2829 if (VT != MVT::iAny) { 2830 unsigned NewAlign = (unsigned) 2831 TLI.getTargetData()->getABITypeAlignment(VT.getTypeForMVT()); 2832 // If source is a string constant, this will require an unaligned load. 2833 if (NewAlign > Align && (isSrcConst || AllowUnalign)) { 2834 if (Dst.getOpcode() != ISD::FrameIndex) { 2835 // Can't change destination alignment. It requires a unaligned store. 2836 if (AllowUnalign) 2837 VT = MVT::iAny; 2838 } else { 2839 int FI = cast<FrameIndexSDNode>(Dst)->getIndex(); 2840 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 2841 if (MFI->isFixedObjectIndex(FI)) { 2842 // Can't change destination alignment. It requires a unaligned store. 2843 if (AllowUnalign) 2844 VT = MVT::iAny; 2845 } else { 2846 // Give the stack frame object a larger alignment if needed. 2847 if (MFI->getObjectAlignment(FI) < NewAlign) 2848 MFI->setObjectAlignment(FI, NewAlign); 2849 Align = NewAlign; 2850 } 2851 } 2852 } 2853 } 2854 2855 if (VT == MVT::iAny) { 2856 if (AllowUnalign) { 2857 VT = MVT::i64; 2858 } else { 2859 switch (Align & 7) { 2860 case 0: VT = MVT::i64; break; 2861 case 4: VT = MVT::i32; break; 2862 case 2: VT = MVT::i16; break; 2863 default: VT = MVT::i8; break; 2864 } 2865 } 2866 2867 MVT LVT = MVT::i64; 2868 while (!TLI.isTypeLegal(LVT)) 2869 LVT = (MVT::SimpleValueType)(LVT.getSimpleVT() - 1); 2870 assert(LVT.isInteger()); 2871 2872 if (VT.bitsGT(LVT)) 2873 VT = LVT; 2874 } 2875 2876 unsigned NumMemOps = 0; 2877 while (Size != 0) { 2878 unsigned VTSize = VT.getSizeInBits() / 8; 2879 while (VTSize > Size) { 2880 // For now, only use non-vector load / store's for the left-over pieces. 2881 if (VT.isVector()) { 2882 VT = MVT::i64; 2883 while (!TLI.isTypeLegal(VT)) 2884 VT = (MVT::SimpleValueType)(VT.getSimpleVT() - 1); 2885 VTSize = VT.getSizeInBits() / 8; 2886 } else { 2887 VT = (MVT::SimpleValueType)(VT.getSimpleVT() - 1); 2888 VTSize >>= 1; 2889 } 2890 } 2891 2892 if (++NumMemOps > Limit) 2893 return false; 2894 MemOps.push_back(VT); 2895 Size -= VTSize; 2896 } 2897 2898 return true; 2899} 2900 2901static SDValue getMemcpyLoadsAndStores(SelectionDAG &DAG, 2902 SDValue Chain, SDValue Dst, 2903 SDValue Src, uint64_t Size, 2904 unsigned Align, bool AlwaysInline, 2905 const Value *DstSV, uint64_t DstSVOff, 2906 const Value *SrcSV, uint64_t SrcSVOff){ 2907 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 2908 2909 // Expand memcpy to a series of load and store ops if the size operand falls 2910 // below a certain threshold. 2911 std::vector<MVT> MemOps; 2912 uint64_t Limit = -1; 2913 if (!AlwaysInline) 2914 Limit = TLI.getMaxStoresPerMemcpy(); 2915 unsigned DstAlign = Align; // Destination alignment can change. 2916 std::string Str; 2917 bool CopyFromStr; 2918 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, Limit, Size, DstAlign, 2919 Str, CopyFromStr, DAG, TLI)) 2920 return SDValue(); 2921 2922 2923 bool isZeroStr = CopyFromStr && Str.empty(); 2924 SmallVector<SDValue, 8> OutChains; 2925 unsigned NumMemOps = MemOps.size(); 2926 uint64_t SrcOff = 0, DstOff = 0; 2927 for (unsigned i = 0; i < NumMemOps; i++) { 2928 MVT VT = MemOps[i]; 2929 unsigned VTSize = VT.getSizeInBits() / 8; 2930 SDValue Value, Store; 2931 2932 if (CopyFromStr && (isZeroStr || !VT.isVector())) { 2933 // It's unlikely a store of a vector immediate can be done in a single 2934 // instruction. It would require a load from a constantpool first. 2935 // We also handle store a vector with all zero's. 2936 // FIXME: Handle other cases where store of vector immediate is done in 2937 // a single instruction. 2938 Value = getMemsetStringVal(VT, DAG, TLI, Str, SrcOff); 2939 Store = DAG.getStore(Chain, Value, 2940 getMemBasePlusOffset(Dst, DstOff, DAG), 2941 DstSV, DstSVOff + DstOff, false, DstAlign); 2942 } else { 2943 Value = DAG.getLoad(VT, Chain, 2944 getMemBasePlusOffset(Src, SrcOff, DAG), 2945 SrcSV, SrcSVOff + SrcOff, false, Align); 2946 Store = DAG.getStore(Chain, Value, 2947 getMemBasePlusOffset(Dst, DstOff, DAG), 2948 DstSV, DstSVOff + DstOff, false, DstAlign); 2949 } 2950 OutChains.push_back(Store); 2951 SrcOff += VTSize; 2952 DstOff += VTSize; 2953 } 2954 2955 return DAG.getNode(ISD::TokenFactor, MVT::Other, 2956 &OutChains[0], OutChains.size()); 2957} 2958 2959static SDValue getMemmoveLoadsAndStores(SelectionDAG &DAG, 2960 SDValue Chain, SDValue Dst, 2961 SDValue Src, uint64_t Size, 2962 unsigned Align, bool AlwaysInline, 2963 const Value *DstSV, uint64_t DstSVOff, 2964 const Value *SrcSV, uint64_t SrcSVOff){ 2965 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 2966 2967 // Expand memmove to a series of load and store ops if the size operand falls 2968 // below a certain threshold. 2969 std::vector<MVT> MemOps; 2970 uint64_t Limit = -1; 2971 if (!AlwaysInline) 2972 Limit = TLI.getMaxStoresPerMemmove(); 2973 unsigned DstAlign = Align; // Destination alignment can change. 2974 std::string Str; 2975 bool CopyFromStr; 2976 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, Limit, Size, DstAlign, 2977 Str, CopyFromStr, DAG, TLI)) 2978 return SDValue(); 2979 2980 uint64_t SrcOff = 0, DstOff = 0; 2981 2982 SmallVector<SDValue, 8> LoadValues; 2983 SmallVector<SDValue, 8> LoadChains; 2984 SmallVector<SDValue, 8> OutChains; 2985 unsigned NumMemOps = MemOps.size(); 2986 for (unsigned i = 0; i < NumMemOps; i++) { 2987 MVT VT = MemOps[i]; 2988 unsigned VTSize = VT.getSizeInBits() / 8; 2989 SDValue Value, Store; 2990 2991 Value = DAG.getLoad(VT, Chain, 2992 getMemBasePlusOffset(Src, SrcOff, DAG), 2993 SrcSV, SrcSVOff + SrcOff, false, Align); 2994 LoadValues.push_back(Value); 2995 LoadChains.push_back(Value.getValue(1)); 2996 SrcOff += VTSize; 2997 } 2998 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 2999 &LoadChains[0], LoadChains.size()); 3000 OutChains.clear(); 3001 for (unsigned i = 0; i < NumMemOps; i++) { 3002 MVT VT = MemOps[i]; 3003 unsigned VTSize = VT.getSizeInBits() / 8; 3004 SDValue Value, Store; 3005 3006 Store = DAG.getStore(Chain, LoadValues[i], 3007 getMemBasePlusOffset(Dst, DstOff, DAG), 3008 DstSV, DstSVOff + DstOff, false, DstAlign); 3009 OutChains.push_back(Store); 3010 DstOff += VTSize; 3011 } 3012 3013 return DAG.getNode(ISD::TokenFactor, MVT::Other, 3014 &OutChains[0], OutChains.size()); 3015} 3016 3017static SDValue getMemsetStores(SelectionDAG &DAG, 3018 SDValue Chain, SDValue Dst, 3019 SDValue Src, uint64_t Size, 3020 unsigned Align, 3021 const Value *DstSV, uint64_t DstSVOff) { 3022 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 3023 3024 // Expand memset to a series of load/store ops if the size operand 3025 // falls below a certain threshold. 3026 std::vector<MVT> MemOps; 3027 std::string Str; 3028 bool CopyFromStr; 3029 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, TLI.getMaxStoresPerMemset(), 3030 Size, Align, Str, CopyFromStr, DAG, TLI)) 3031 return SDValue(); 3032 3033 SmallVector<SDValue, 8> OutChains; 3034 uint64_t DstOff = 0; 3035 3036 unsigned NumMemOps = MemOps.size(); 3037 for (unsigned i = 0; i < NumMemOps; i++) { 3038 MVT VT = MemOps[i]; 3039 unsigned VTSize = VT.getSizeInBits() / 8; 3040 SDValue Value = getMemsetValue(Src, VT, DAG); 3041 SDValue Store = DAG.getStore(Chain, Value, 3042 getMemBasePlusOffset(Dst, DstOff, DAG), 3043 DstSV, DstSVOff + DstOff); 3044 OutChains.push_back(Store); 3045 DstOff += VTSize; 3046 } 3047 3048 return DAG.getNode(ISD::TokenFactor, MVT::Other, 3049 &OutChains[0], OutChains.size()); 3050} 3051 3052SDValue SelectionDAG::getMemcpy(SDValue Chain, SDValue Dst, 3053 SDValue Src, SDValue Size, 3054 unsigned Align, bool AlwaysInline, 3055 const Value *DstSV, uint64_t DstSVOff, 3056 const Value *SrcSV, uint64_t SrcSVOff) { 3057 3058 // Check to see if we should lower the memcpy to loads and stores first. 3059 // For cases within the target-specified limits, this is the best choice. 3060 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 3061 if (ConstantSize) { 3062 // Memcpy with size zero? Just return the original chain. 3063 if (ConstantSize->isNullValue()) 3064 return Chain; 3065 3066 SDValue Result = 3067 getMemcpyLoadsAndStores(*this, Chain, Dst, Src, 3068 ConstantSize->getZExtValue(), 3069 Align, false, DstSV, DstSVOff, SrcSV, SrcSVOff); 3070 if (Result.getNode()) 3071 return Result; 3072 } 3073 3074 // Then check to see if we should lower the memcpy with target-specific 3075 // code. If the target chooses to do this, this is the next best. 3076 SDValue Result = 3077 TLI.EmitTargetCodeForMemcpy(*this, Chain, Dst, Src, Size, Align, 3078 AlwaysInline, 3079 DstSV, DstSVOff, SrcSV, SrcSVOff); 3080 if (Result.getNode()) 3081 return Result; 3082 3083 // If we really need inline code and the target declined to provide it, 3084 // use a (potentially long) sequence of loads and stores. 3085 if (AlwaysInline) { 3086 assert(ConstantSize && "AlwaysInline requires a constant size!"); 3087 return getMemcpyLoadsAndStores(*this, Chain, Dst, Src, 3088 ConstantSize->getZExtValue(), Align, true, 3089 DstSV, DstSVOff, SrcSV, SrcSVOff); 3090 } 3091 3092 // Emit a library call. 3093 TargetLowering::ArgListTy Args; 3094 TargetLowering::ArgListEntry Entry; 3095 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 3096 Entry.Node = Dst; Args.push_back(Entry); 3097 Entry.Node = Src; Args.push_back(Entry); 3098 Entry.Node = Size; Args.push_back(Entry); 3099 std::pair<SDValue,SDValue> CallResult = 3100 TLI.LowerCallTo(Chain, Type::VoidTy, 3101 false, false, false, CallingConv::C, false, 3102 getSymbol("memcpy", TLI.getPointerTy()), 3103 Args, *this); 3104 return CallResult.second; 3105} 3106 3107SDValue SelectionDAG::getMemmove(SDValue Chain, SDValue Dst, 3108 SDValue Src, SDValue Size, 3109 unsigned Align, 3110 const Value *DstSV, uint64_t DstSVOff, 3111 const Value *SrcSV, uint64_t SrcSVOff) { 3112 3113 // Check to see if we should lower the memmove to loads and stores first. 3114 // For cases within the target-specified limits, this is the best choice. 3115 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 3116 if (ConstantSize) { 3117 // Memmove with size zero? Just return the original chain. 3118 if (ConstantSize->isNullValue()) 3119 return Chain; 3120 3121 SDValue Result = 3122 getMemmoveLoadsAndStores(*this, Chain, Dst, Src, 3123 ConstantSize->getZExtValue(), 3124 Align, false, DstSV, DstSVOff, SrcSV, SrcSVOff); 3125 if (Result.getNode()) 3126 return Result; 3127 } 3128 3129 // Then check to see if we should lower the memmove with target-specific 3130 // code. If the target chooses to do this, this is the next best. 3131 SDValue Result = 3132 TLI.EmitTargetCodeForMemmove(*this, Chain, Dst, Src, Size, Align, 3133 DstSV, DstSVOff, SrcSV, SrcSVOff); 3134 if (Result.getNode()) 3135 return Result; 3136 3137 // Emit a library call. 3138 TargetLowering::ArgListTy Args; 3139 TargetLowering::ArgListEntry Entry; 3140 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 3141 Entry.Node = Dst; Args.push_back(Entry); 3142 Entry.Node = Src; Args.push_back(Entry); 3143 Entry.Node = Size; Args.push_back(Entry); 3144 std::pair<SDValue,SDValue> CallResult = 3145 TLI.LowerCallTo(Chain, Type::VoidTy, 3146 false, false, false, CallingConv::C, false, 3147 getSymbol("memmove", TLI.getPointerTy()), 3148 Args, *this); 3149 return CallResult.second; 3150} 3151 3152SDValue SelectionDAG::getMemset(SDValue Chain, SDValue Dst, 3153 SDValue Src, SDValue Size, 3154 unsigned Align, 3155 const Value *DstSV, uint64_t DstSVOff) { 3156 3157 // Check to see if we should lower the memset to stores first. 3158 // For cases within the target-specified limits, this is the best choice. 3159 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 3160 if (ConstantSize) { 3161 // Memset with size zero? Just return the original chain. 3162 if (ConstantSize->isNullValue()) 3163 return Chain; 3164 3165 SDValue Result = 3166 getMemsetStores(*this, Chain, Dst, Src, ConstantSize->getZExtValue(), 3167 Align, DstSV, DstSVOff); 3168 if (Result.getNode()) 3169 return Result; 3170 } 3171 3172 // Then check to see if we should lower the memset with target-specific 3173 // code. If the target chooses to do this, this is the next best. 3174 SDValue Result = 3175 TLI.EmitTargetCodeForMemset(*this, Chain, Dst, Src, Size, Align, 3176 DstSV, DstSVOff); 3177 if (Result.getNode()) 3178 return Result; 3179 3180 // Emit a library call. 3181 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType(); 3182 TargetLowering::ArgListTy Args; 3183 TargetLowering::ArgListEntry Entry; 3184 Entry.Node = Dst; Entry.Ty = IntPtrTy; 3185 Args.push_back(Entry); 3186 // Extend or truncate the argument to be an i32 value for the call. 3187 if (Src.getValueType().bitsGT(MVT::i32)) 3188 Src = getNode(ISD::TRUNCATE, MVT::i32, Src); 3189 else 3190 Src = getNode(ISD::ZERO_EXTEND, MVT::i32, Src); 3191 Entry.Node = Src; Entry.Ty = Type::Int32Ty; Entry.isSExt = true; 3192 Args.push_back(Entry); 3193 Entry.Node = Size; Entry.Ty = IntPtrTy; Entry.isSExt = false; 3194 Args.push_back(Entry); 3195 std::pair<SDValue,SDValue> CallResult = 3196 TLI.LowerCallTo(Chain, Type::VoidTy, 3197 false, false, false, CallingConv::C, false, 3198 getSymbol("memset", TLI.getPointerTy()), 3199 Args, *this); 3200 return CallResult.second; 3201} 3202 3203SDValue SelectionDAG::getAtomic(unsigned Opcode, SDValue Chain, 3204 SDValue Ptr, SDValue Cmp, 3205 SDValue Swp, const Value* PtrVal, 3206 unsigned Alignment) { 3207 assert((Opcode == ISD::ATOMIC_CMP_SWAP_8 || 3208 Opcode == ISD::ATOMIC_CMP_SWAP_16 || 3209 Opcode == ISD::ATOMIC_CMP_SWAP_32 || 3210 Opcode == ISD::ATOMIC_CMP_SWAP_64) && "Invalid Atomic Op"); 3211 assert(Cmp.getValueType() == Swp.getValueType() && "Invalid Atomic Op Types"); 3212 3213 MVT VT = Cmp.getValueType(); 3214 3215 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3216 Alignment = getMVTAlignment(VT); 3217 3218 SDVTList VTs = getVTList(VT, MVT::Other); 3219 FoldingSetNodeID ID; 3220 SDValue Ops[] = {Chain, Ptr, Cmp, Swp}; 3221 AddNodeIDNode(ID, Opcode, VTs, Ops, 4); 3222 void* IP = 0; 3223 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3224 return SDValue(E, 0); 3225 SDNode* N = NodeAllocator.Allocate<AtomicSDNode>(); 3226 new (N) AtomicSDNode(Opcode, VTs, Chain, Ptr, Cmp, Swp, PtrVal, Alignment); 3227 CSEMap.InsertNode(N, IP); 3228 AllNodes.push_back(N); 3229 return SDValue(N, 0); 3230} 3231 3232SDValue SelectionDAG::getAtomic(unsigned Opcode, SDValue Chain, 3233 SDValue Ptr, SDValue Val, 3234 const Value* PtrVal, 3235 unsigned Alignment) { 3236 assert((Opcode == ISD::ATOMIC_LOAD_ADD_8 || 3237 Opcode == ISD::ATOMIC_LOAD_SUB_8 || 3238 Opcode == ISD::ATOMIC_LOAD_AND_8 || 3239 Opcode == ISD::ATOMIC_LOAD_OR_8 || 3240 Opcode == ISD::ATOMIC_LOAD_XOR_8 || 3241 Opcode == ISD::ATOMIC_LOAD_NAND_8 || 3242 Opcode == ISD::ATOMIC_LOAD_MIN_8 || 3243 Opcode == ISD::ATOMIC_LOAD_MAX_8 || 3244 Opcode == ISD::ATOMIC_LOAD_UMIN_8 || 3245 Opcode == ISD::ATOMIC_LOAD_UMAX_8 || 3246 Opcode == ISD::ATOMIC_SWAP_8 || 3247 Opcode == ISD::ATOMIC_LOAD_ADD_16 || 3248 Opcode == ISD::ATOMIC_LOAD_SUB_16 || 3249 Opcode == ISD::ATOMIC_LOAD_AND_16 || 3250 Opcode == ISD::ATOMIC_LOAD_OR_16 || 3251 Opcode == ISD::ATOMIC_LOAD_XOR_16 || 3252 Opcode == ISD::ATOMIC_LOAD_NAND_16 || 3253 Opcode == ISD::ATOMIC_LOAD_MIN_16 || 3254 Opcode == ISD::ATOMIC_LOAD_MAX_16 || 3255 Opcode == ISD::ATOMIC_LOAD_UMIN_16 || 3256 Opcode == ISD::ATOMIC_LOAD_UMAX_16 || 3257 Opcode == ISD::ATOMIC_SWAP_16 || 3258 Opcode == ISD::ATOMIC_LOAD_ADD_32 || 3259 Opcode == ISD::ATOMIC_LOAD_SUB_32 || 3260 Opcode == ISD::ATOMIC_LOAD_AND_32 || 3261 Opcode == ISD::ATOMIC_LOAD_OR_32 || 3262 Opcode == ISD::ATOMIC_LOAD_XOR_32 || 3263 Opcode == ISD::ATOMIC_LOAD_NAND_32 || 3264 Opcode == ISD::ATOMIC_LOAD_MIN_32 || 3265 Opcode == ISD::ATOMIC_LOAD_MAX_32 || 3266 Opcode == ISD::ATOMIC_LOAD_UMIN_32 || 3267 Opcode == ISD::ATOMIC_LOAD_UMAX_32 || 3268 Opcode == ISD::ATOMIC_SWAP_32 || 3269 Opcode == ISD::ATOMIC_LOAD_ADD_64 || 3270 Opcode == ISD::ATOMIC_LOAD_SUB_64 || 3271 Opcode == ISD::ATOMIC_LOAD_AND_64 || 3272 Opcode == ISD::ATOMIC_LOAD_OR_64 || 3273 Opcode == ISD::ATOMIC_LOAD_XOR_64 || 3274 Opcode == ISD::ATOMIC_LOAD_NAND_64 || 3275 Opcode == ISD::ATOMIC_LOAD_MIN_64 || 3276 Opcode == ISD::ATOMIC_LOAD_MAX_64 || 3277 Opcode == ISD::ATOMIC_LOAD_UMIN_64 || 3278 Opcode == ISD::ATOMIC_LOAD_UMAX_64 || 3279 Opcode == ISD::ATOMIC_SWAP_64) && "Invalid Atomic Op"); 3280 3281 MVT VT = Val.getValueType(); 3282 3283 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3284 Alignment = getMVTAlignment(VT); 3285 3286 SDVTList VTs = getVTList(VT, MVT::Other); 3287 FoldingSetNodeID ID; 3288 SDValue Ops[] = {Chain, Ptr, Val}; 3289 AddNodeIDNode(ID, Opcode, VTs, Ops, 3); 3290 void* IP = 0; 3291 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3292 return SDValue(E, 0); 3293 SDNode* N = NodeAllocator.Allocate<AtomicSDNode>(); 3294 new (N) AtomicSDNode(Opcode, VTs, Chain, Ptr, Val, PtrVal, Alignment); 3295 CSEMap.InsertNode(N, IP); 3296 AllNodes.push_back(N); 3297 return SDValue(N, 0); 3298} 3299 3300/// getMergeValues - Create a MERGE_VALUES node from the given operands. 3301/// Allowed to return something different (and simpler) if Simplify is true. 3302SDValue SelectionDAG::getMergeValues(const SDValue *Ops, unsigned NumOps, 3303 bool Simplify) { 3304 if (Simplify && NumOps == 1) 3305 return Ops[0]; 3306 3307 SmallVector<MVT, 4> VTs; 3308 VTs.reserve(NumOps); 3309 for (unsigned i = 0; i < NumOps; ++i) 3310 VTs.push_back(Ops[i].getValueType()); 3311 return getNode(ISD::MERGE_VALUES, getVTList(&VTs[0], NumOps), Ops, NumOps); 3312} 3313 3314SDValue 3315SelectionDAG::getCall(unsigned CallingConv, bool IsVarArgs, bool IsTailCall, 3316 SDVTList VTs, 3317 const SDValue *Operands, unsigned NumOperands) { 3318 // Do not include isTailCall in the folding set profile. 3319 FoldingSetNodeID ID; 3320 AddNodeIDNode(ID, ISD::CALL, VTs, Operands, NumOperands); 3321 ID.AddInteger(CallingConv); 3322 ID.AddInteger(IsVarArgs); 3323 void *IP = 0; 3324 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) { 3325 // Instead of including isTailCall in the folding set, we just 3326 // set the flag of the existing node. 3327 if (!IsTailCall) 3328 cast<CallSDNode>(E)->setNotTailCall(); 3329 return SDValue(E, 0); 3330 } 3331 SDNode *N = NodeAllocator.Allocate<CallSDNode>(); 3332 new (N) CallSDNode(CallingConv, IsVarArgs, IsTailCall, 3333 VTs, Operands, NumOperands); 3334 CSEMap.InsertNode(N, IP); 3335 AllNodes.push_back(N); 3336 return SDValue(N, 0); 3337} 3338 3339SDValue 3340SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, 3341 MVT VT, SDValue Chain, 3342 SDValue Ptr, SDValue Offset, 3343 const Value *SV, int SVOffset, MVT EVT, 3344 bool isVolatile, unsigned Alignment) { 3345 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3346 Alignment = getMVTAlignment(VT); 3347 3348 if (VT == EVT) { 3349 ExtType = ISD::NON_EXTLOAD; 3350 } else if (ExtType == ISD::NON_EXTLOAD) { 3351 assert(VT == EVT && "Non-extending load from different memory type!"); 3352 } else { 3353 // Extending load. 3354 if (VT.isVector()) 3355 assert(EVT.getVectorNumElements() == VT.getVectorNumElements() && 3356 "Invalid vector extload!"); 3357 else 3358 assert(EVT.bitsLT(VT) && 3359 "Should only be an extending load, not truncating!"); 3360 assert((ExtType == ISD::EXTLOAD || VT.isInteger()) && 3361 "Cannot sign/zero extend a FP/Vector load!"); 3362 assert(VT.isInteger() == EVT.isInteger() && 3363 "Cannot convert from FP to Int or Int -> FP!"); 3364 } 3365 3366 bool Indexed = AM != ISD::UNINDEXED; 3367 assert((Indexed || Offset.getOpcode() == ISD::UNDEF) && 3368 "Unindexed load with an offset!"); 3369 3370 SDVTList VTs = Indexed ? 3371 getVTList(VT, Ptr.getValueType(), MVT::Other) : getVTList(VT, MVT::Other); 3372 SDValue Ops[] = { Chain, Ptr, Offset }; 3373 FoldingSetNodeID ID; 3374 AddNodeIDNode(ID, ISD::LOAD, VTs, Ops, 3); 3375 ID.AddInteger(AM); 3376 ID.AddInteger(ExtType); 3377 ID.AddInteger(EVT.getRawBits()); 3378 ID.AddInteger(encodeMemSDNodeFlags(isVolatile, Alignment)); 3379 void *IP = 0; 3380 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3381 return SDValue(E, 0); 3382 SDNode *N = NodeAllocator.Allocate<LoadSDNode>(); 3383 new (N) LoadSDNode(Ops, VTs, AM, ExtType, EVT, SV, SVOffset, 3384 Alignment, isVolatile); 3385 CSEMap.InsertNode(N, IP); 3386 AllNodes.push_back(N); 3387 return SDValue(N, 0); 3388} 3389 3390SDValue SelectionDAG::getLoad(MVT VT, 3391 SDValue Chain, SDValue Ptr, 3392 const Value *SV, int SVOffset, 3393 bool isVolatile, unsigned Alignment) { 3394 SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType()); 3395 return getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD, VT, Chain, Ptr, Undef, 3396 SV, SVOffset, VT, isVolatile, Alignment); 3397} 3398 3399SDValue SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, MVT VT, 3400 SDValue Chain, SDValue Ptr, 3401 const Value *SV, 3402 int SVOffset, MVT EVT, 3403 bool isVolatile, unsigned Alignment) { 3404 SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType()); 3405 return getLoad(ISD::UNINDEXED, ExtType, VT, Chain, Ptr, Undef, 3406 SV, SVOffset, EVT, isVolatile, Alignment); 3407} 3408 3409SDValue 3410SelectionDAG::getIndexedLoad(SDValue OrigLoad, SDValue Base, 3411 SDValue Offset, ISD::MemIndexedMode AM) { 3412 LoadSDNode *LD = cast<LoadSDNode>(OrigLoad); 3413 assert(LD->getOffset().getOpcode() == ISD::UNDEF && 3414 "Load is already a indexed load!"); 3415 return getLoad(AM, LD->getExtensionType(), OrigLoad.getValueType(), 3416 LD->getChain(), Base, Offset, LD->getSrcValue(), 3417 LD->getSrcValueOffset(), LD->getMemoryVT(), 3418 LD->isVolatile(), LD->getAlignment()); 3419} 3420 3421SDValue SelectionDAG::getStore(SDValue Chain, SDValue Val, 3422 SDValue Ptr, const Value *SV, int SVOffset, 3423 bool isVolatile, unsigned Alignment) { 3424 MVT VT = Val.getValueType(); 3425 3426 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3427 Alignment = getMVTAlignment(VT); 3428 3429 SDVTList VTs = getVTList(MVT::Other); 3430 SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType()); 3431 SDValue Ops[] = { Chain, Val, Ptr, Undef }; 3432 FoldingSetNodeID ID; 3433 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); 3434 ID.AddInteger(ISD::UNINDEXED); 3435 ID.AddInteger(false); 3436 ID.AddInteger(VT.getRawBits()); 3437 ID.AddInteger(encodeMemSDNodeFlags(isVolatile, Alignment)); 3438 void *IP = 0; 3439 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3440 return SDValue(E, 0); 3441 SDNode *N = NodeAllocator.Allocate<StoreSDNode>(); 3442 new (N) StoreSDNode(Ops, VTs, ISD::UNINDEXED, false, 3443 VT, SV, SVOffset, Alignment, isVolatile); 3444 CSEMap.InsertNode(N, IP); 3445 AllNodes.push_back(N); 3446 return SDValue(N, 0); 3447} 3448 3449SDValue SelectionDAG::getTruncStore(SDValue Chain, SDValue Val, 3450 SDValue Ptr, const Value *SV, 3451 int SVOffset, MVT SVT, 3452 bool isVolatile, unsigned Alignment) { 3453 MVT VT = Val.getValueType(); 3454 3455 if (VT == SVT) 3456 return getStore(Chain, Val, Ptr, SV, SVOffset, isVolatile, Alignment); 3457 3458 assert(VT.bitsGT(SVT) && "Not a truncation?"); 3459 assert(VT.isInteger() == SVT.isInteger() && 3460 "Can't do FP-INT conversion!"); 3461 3462 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3463 Alignment = getMVTAlignment(VT); 3464 3465 SDVTList VTs = getVTList(MVT::Other); 3466 SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType()); 3467 SDValue Ops[] = { Chain, Val, Ptr, Undef }; 3468 FoldingSetNodeID ID; 3469 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); 3470 ID.AddInteger(ISD::UNINDEXED); 3471 ID.AddInteger(1); 3472 ID.AddInteger(SVT.getRawBits()); 3473 ID.AddInteger(encodeMemSDNodeFlags(isVolatile, Alignment)); 3474 void *IP = 0; 3475 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3476 return SDValue(E, 0); 3477 SDNode *N = NodeAllocator.Allocate<StoreSDNode>(); 3478 new (N) StoreSDNode(Ops, VTs, ISD::UNINDEXED, true, 3479 SVT, SV, SVOffset, Alignment, isVolatile); 3480 CSEMap.InsertNode(N, IP); 3481 AllNodes.push_back(N); 3482 return SDValue(N, 0); 3483} 3484 3485SDValue 3486SelectionDAG::getIndexedStore(SDValue OrigStore, SDValue Base, 3487 SDValue Offset, ISD::MemIndexedMode AM) { 3488 StoreSDNode *ST = cast<StoreSDNode>(OrigStore); 3489 assert(ST->getOffset().getOpcode() == ISD::UNDEF && 3490 "Store is already a indexed store!"); 3491 SDVTList VTs = getVTList(Base.getValueType(), MVT::Other); 3492 SDValue Ops[] = { ST->getChain(), ST->getValue(), Base, Offset }; 3493 FoldingSetNodeID ID; 3494 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); 3495 ID.AddInteger(AM); 3496 ID.AddInteger(ST->isTruncatingStore()); 3497 ID.AddInteger(ST->getMemoryVT().getRawBits()); 3498 ID.AddInteger(ST->getRawFlags()); 3499 void *IP = 0; 3500 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3501 return SDValue(E, 0); 3502 SDNode *N = NodeAllocator.Allocate<StoreSDNode>(); 3503 new (N) StoreSDNode(Ops, VTs, AM, 3504 ST->isTruncatingStore(), ST->getMemoryVT(), 3505 ST->getSrcValue(), ST->getSrcValueOffset(), 3506 ST->getAlignment(), ST->isVolatile()); 3507 CSEMap.InsertNode(N, IP); 3508 AllNodes.push_back(N); 3509 return SDValue(N, 0); 3510} 3511 3512SDValue SelectionDAG::getVAArg(MVT VT, 3513 SDValue Chain, SDValue Ptr, 3514 SDValue SV) { 3515 SDValue Ops[] = { Chain, Ptr, SV }; 3516 return getNode(ISD::VAARG, getVTList(VT, MVT::Other), Ops, 3); 3517} 3518 3519SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, 3520 const SDUse *Ops, unsigned NumOps) { 3521 switch (NumOps) { 3522 case 0: return getNode(Opcode, VT); 3523 case 1: return getNode(Opcode, VT, Ops[0]); 3524 case 2: return getNode(Opcode, VT, Ops[0], Ops[1]); 3525 case 3: return getNode(Opcode, VT, Ops[0], Ops[1], Ops[2]); 3526 default: break; 3527 } 3528 3529 // Copy from an SDUse array into an SDValue array for use with 3530 // the regular getNode logic. 3531 SmallVector<SDValue, 8> NewOps(Ops, Ops + NumOps); 3532 return getNode(Opcode, VT, &NewOps[0], NumOps); 3533} 3534 3535SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, 3536 const SDValue *Ops, unsigned NumOps) { 3537 switch (NumOps) { 3538 case 0: return getNode(Opcode, VT); 3539 case 1: return getNode(Opcode, VT, Ops[0]); 3540 case 2: return getNode(Opcode, VT, Ops[0], Ops[1]); 3541 case 3: return getNode(Opcode, VT, Ops[0], Ops[1], Ops[2]); 3542 default: break; 3543 } 3544 3545 switch (Opcode) { 3546 default: break; 3547 case ISD::SELECT_CC: { 3548 assert(NumOps == 5 && "SELECT_CC takes 5 operands!"); 3549 assert(Ops[0].getValueType() == Ops[1].getValueType() && 3550 "LHS and RHS of condition must have same type!"); 3551 assert(Ops[2].getValueType() == Ops[3].getValueType() && 3552 "True and False arms of SelectCC must have same type!"); 3553 assert(Ops[2].getValueType() == VT && 3554 "select_cc node must be of same type as true and false value!"); 3555 break; 3556 } 3557 case ISD::BR_CC: { 3558 assert(NumOps == 5 && "BR_CC takes 5 operands!"); 3559 assert(Ops[2].getValueType() == Ops[3].getValueType() && 3560 "LHS/RHS of comparison should match types!"); 3561 break; 3562 } 3563 } 3564 3565 // Memoize nodes. 3566 SDNode *N; 3567 SDVTList VTs = getVTList(VT); 3568 if (VT != MVT::Flag) { 3569 FoldingSetNodeID ID; 3570 AddNodeIDNode(ID, Opcode, VTs, Ops, NumOps); 3571 void *IP = 0; 3572 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3573 return SDValue(E, 0); 3574 N = NodeAllocator.Allocate<SDNode>(); 3575 new (N) SDNode(Opcode, VTs, Ops, NumOps); 3576 CSEMap.InsertNode(N, IP); 3577 } else { 3578 N = NodeAllocator.Allocate<SDNode>(); 3579 new (N) SDNode(Opcode, VTs, Ops, NumOps); 3580 } 3581 AllNodes.push_back(N); 3582#ifndef NDEBUG 3583 VerifyNode(N); 3584#endif 3585 return SDValue(N, 0); 3586} 3587 3588SDValue SelectionDAG::getNode(unsigned Opcode, 3589 const std::vector<MVT> &ResultTys, 3590 const SDValue *Ops, unsigned NumOps) { 3591 return getNode(Opcode, getNodeValueTypes(ResultTys), ResultTys.size(), 3592 Ops, NumOps); 3593} 3594 3595SDValue SelectionDAG::getNode(unsigned Opcode, 3596 const MVT *VTs, unsigned NumVTs, 3597 const SDValue *Ops, unsigned NumOps) { 3598 if (NumVTs == 1) 3599 return getNode(Opcode, VTs[0], Ops, NumOps); 3600 return getNode(Opcode, makeVTList(VTs, NumVTs), Ops, NumOps); 3601} 3602 3603SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, 3604 const SDValue *Ops, unsigned NumOps) { 3605 if (VTList.NumVTs == 1) 3606 return getNode(Opcode, VTList.VTs[0], Ops, NumOps); 3607 3608 switch (Opcode) { 3609 // FIXME: figure out how to safely handle things like 3610 // int foo(int x) { return 1 << (x & 255); } 3611 // int bar() { return foo(256); } 3612#if 0 3613 case ISD::SRA_PARTS: 3614 case ISD::SRL_PARTS: 3615 case ISD::SHL_PARTS: 3616 if (N3.getOpcode() == ISD::SIGN_EXTEND_INREG && 3617 cast<VTSDNode>(N3.getOperand(1))->getVT() != MVT::i1) 3618 return getNode(Opcode, VT, N1, N2, N3.getOperand(0)); 3619 else if (N3.getOpcode() == ISD::AND) 3620 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(N3.getOperand(1))) { 3621 // If the and is only masking out bits that cannot effect the shift, 3622 // eliminate the and. 3623 unsigned NumBits = VT.getSizeInBits()*2; 3624 if ((AndRHS->getValue() & (NumBits-1)) == NumBits-1) 3625 return getNode(Opcode, VT, N1, N2, N3.getOperand(0)); 3626 } 3627 break; 3628#endif 3629 } 3630 3631 // Memoize the node unless it returns a flag. 3632 SDNode *N; 3633 if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) { 3634 FoldingSetNodeID ID; 3635 AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps); 3636 void *IP = 0; 3637 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3638 return SDValue(E, 0); 3639 if (NumOps == 1) { 3640 N = NodeAllocator.Allocate<UnarySDNode>(); 3641 new (N) UnarySDNode(Opcode, VTList, Ops[0]); 3642 } else if (NumOps == 2) { 3643 N = NodeAllocator.Allocate<BinarySDNode>(); 3644 new (N) BinarySDNode(Opcode, VTList, Ops[0], Ops[1]); 3645 } else if (NumOps == 3) { 3646 N = NodeAllocator.Allocate<TernarySDNode>(); 3647 new (N) TernarySDNode(Opcode, VTList, Ops[0], Ops[1], Ops[2]); 3648 } else { 3649 N = NodeAllocator.Allocate<SDNode>(); 3650 new (N) SDNode(Opcode, VTList, Ops, NumOps); 3651 } 3652 CSEMap.InsertNode(N, IP); 3653 } else { 3654 if (NumOps == 1) { 3655 N = NodeAllocator.Allocate<UnarySDNode>(); 3656 new (N) UnarySDNode(Opcode, VTList, Ops[0]); 3657 } else if (NumOps == 2) { 3658 N = NodeAllocator.Allocate<BinarySDNode>(); 3659 new (N) BinarySDNode(Opcode, VTList, Ops[0], Ops[1]); 3660 } else if (NumOps == 3) { 3661 N = NodeAllocator.Allocate<TernarySDNode>(); 3662 new (N) TernarySDNode(Opcode, VTList, Ops[0], Ops[1], Ops[2]); 3663 } else { 3664 N = NodeAllocator.Allocate<SDNode>(); 3665 new (N) SDNode(Opcode, VTList, Ops, NumOps); 3666 } 3667 } 3668 AllNodes.push_back(N); 3669#ifndef NDEBUG 3670 VerifyNode(N); 3671#endif 3672 return SDValue(N, 0); 3673} 3674 3675SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList) { 3676 return getNode(Opcode, VTList, 0, 0); 3677} 3678 3679SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, 3680 SDValue N1) { 3681 SDValue Ops[] = { N1 }; 3682 return getNode(Opcode, VTList, Ops, 1); 3683} 3684 3685SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, 3686 SDValue N1, SDValue N2) { 3687 SDValue Ops[] = { N1, N2 }; 3688 return getNode(Opcode, VTList, Ops, 2); 3689} 3690 3691SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, 3692 SDValue N1, SDValue N2, SDValue N3) { 3693 SDValue Ops[] = { N1, N2, N3 }; 3694 return getNode(Opcode, VTList, Ops, 3); 3695} 3696 3697SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, 3698 SDValue N1, SDValue N2, SDValue N3, 3699 SDValue N4) { 3700 SDValue Ops[] = { N1, N2, N3, N4 }; 3701 return getNode(Opcode, VTList, Ops, 4); 3702} 3703 3704SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, 3705 SDValue N1, SDValue N2, SDValue N3, 3706 SDValue N4, SDValue N5) { 3707 SDValue Ops[] = { N1, N2, N3, N4, N5 }; 3708 return getNode(Opcode, VTList, Ops, 5); 3709} 3710 3711SDVTList SelectionDAG::getVTList(MVT VT) { 3712 return makeVTList(SDNode::getValueTypeList(VT), 1); 3713} 3714 3715SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2) { 3716 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 3717 E = VTList.rend(); I != E; ++I) 3718 if (I->NumVTs == 2 && I->VTs[0] == VT1 && I->VTs[1] == VT2) 3719 return *I; 3720 3721 MVT *Array = Allocator.Allocate<MVT>(2); 3722 Array[0] = VT1; 3723 Array[1] = VT2; 3724 SDVTList Result = makeVTList(Array, 2); 3725 VTList.push_back(Result); 3726 return Result; 3727} 3728 3729SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2, MVT VT3) { 3730 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 3731 E = VTList.rend(); I != E; ++I) 3732 if (I->NumVTs == 3 && I->VTs[0] == VT1 && I->VTs[1] == VT2 && 3733 I->VTs[2] == VT3) 3734 return *I; 3735 3736 MVT *Array = Allocator.Allocate<MVT>(3); 3737 Array[0] = VT1; 3738 Array[1] = VT2; 3739 Array[2] = VT3; 3740 SDVTList Result = makeVTList(Array, 3); 3741 VTList.push_back(Result); 3742 return Result; 3743} 3744 3745SDVTList SelectionDAG::getVTList(const MVT *VTs, unsigned NumVTs) { 3746 switch (NumVTs) { 3747 case 0: assert(0 && "Cannot have nodes without results!"); 3748 case 1: return getVTList(VTs[0]); 3749 case 2: return getVTList(VTs[0], VTs[1]); 3750 case 3: return getVTList(VTs[0], VTs[1], VTs[2]); 3751 default: break; 3752 } 3753 3754 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 3755 E = VTList.rend(); I != E; ++I) { 3756 if (I->NumVTs != NumVTs || VTs[0] != I->VTs[0] || VTs[1] != I->VTs[1]) 3757 continue; 3758 3759 bool NoMatch = false; 3760 for (unsigned i = 2; i != NumVTs; ++i) 3761 if (VTs[i] != I->VTs[i]) { 3762 NoMatch = true; 3763 break; 3764 } 3765 if (!NoMatch) 3766 return *I; 3767 } 3768 3769 MVT *Array = Allocator.Allocate<MVT>(NumVTs); 3770 std::copy(VTs, VTs+NumVTs, Array); 3771 SDVTList Result = makeVTList(Array, NumVTs); 3772 VTList.push_back(Result); 3773 return Result; 3774} 3775 3776 3777/// UpdateNodeOperands - *Mutate* the specified node in-place to have the 3778/// specified operands. If the resultant node already exists in the DAG, 3779/// this does not modify the specified node, instead it returns the node that 3780/// already exists. If the resultant node does not exist in the DAG, the 3781/// input node is returned. As a degenerate case, if you specify the same 3782/// input operands as the node already has, the input node is returned. 3783SDValue SelectionDAG::UpdateNodeOperands(SDValue InN, SDValue Op) { 3784 SDNode *N = InN.getNode(); 3785 assert(N->getNumOperands() == 1 && "Update with wrong number of operands"); 3786 3787 // Check to see if there is no change. 3788 if (Op == N->getOperand(0)) return InN; 3789 3790 // See if the modified node already exists. 3791 void *InsertPos = 0; 3792 if (SDNode *Existing = FindModifiedNodeSlot(N, Op, InsertPos)) 3793 return SDValue(Existing, InN.getResNo()); 3794 3795 // Nope it doesn't. Remove the node from its current place in the maps. 3796 if (InsertPos) 3797 if (!RemoveNodeFromCSEMaps(N)) 3798 InsertPos = 0; 3799 3800 // Now we update the operands. 3801 N->OperandList[0].getVal()->removeUser(0, N); 3802 N->OperandList[0] = Op; 3803 N->OperandList[0].setUser(N); 3804 Op.getNode()->addUser(0, N); 3805 3806 // If this gets put into a CSE map, add it. 3807 if (InsertPos) CSEMap.InsertNode(N, InsertPos); 3808 return InN; 3809} 3810 3811SDValue SelectionDAG:: 3812UpdateNodeOperands(SDValue InN, SDValue Op1, SDValue Op2) { 3813 SDNode *N = InN.getNode(); 3814 assert(N->getNumOperands() == 2 && "Update with wrong number of operands"); 3815 3816 // Check to see if there is no change. 3817 if (Op1 == N->getOperand(0) && Op2 == N->getOperand(1)) 3818 return InN; // No operands changed, just return the input node. 3819 3820 // See if the modified node already exists. 3821 void *InsertPos = 0; 3822 if (SDNode *Existing = FindModifiedNodeSlot(N, Op1, Op2, InsertPos)) 3823 return SDValue(Existing, InN.getResNo()); 3824 3825 // Nope it doesn't. Remove the node from its current place in the maps. 3826 if (InsertPos) 3827 if (!RemoveNodeFromCSEMaps(N)) 3828 InsertPos = 0; 3829 3830 // Now we update the operands. 3831 if (N->OperandList[0] != Op1) { 3832 N->OperandList[0].getVal()->removeUser(0, N); 3833 N->OperandList[0] = Op1; 3834 N->OperandList[0].setUser(N); 3835 Op1.getNode()->addUser(0, N); 3836 } 3837 if (N->OperandList[1] != Op2) { 3838 N->OperandList[1].getVal()->removeUser(1, N); 3839 N->OperandList[1] = Op2; 3840 N->OperandList[1].setUser(N); 3841 Op2.getNode()->addUser(1, N); 3842 } 3843 3844 // If this gets put into a CSE map, add it. 3845 if (InsertPos) CSEMap.InsertNode(N, InsertPos); 3846 return InN; 3847} 3848 3849SDValue SelectionDAG:: 3850UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, SDValue Op3) { 3851 SDValue Ops[] = { Op1, Op2, Op3 }; 3852 return UpdateNodeOperands(N, Ops, 3); 3853} 3854 3855SDValue SelectionDAG:: 3856UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, 3857 SDValue Op3, SDValue Op4) { 3858 SDValue Ops[] = { Op1, Op2, Op3, Op4 }; 3859 return UpdateNodeOperands(N, Ops, 4); 3860} 3861 3862SDValue SelectionDAG:: 3863UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, 3864 SDValue Op3, SDValue Op4, SDValue Op5) { 3865 SDValue Ops[] = { Op1, Op2, Op3, Op4, Op5 }; 3866 return UpdateNodeOperands(N, Ops, 5); 3867} 3868 3869SDValue SelectionDAG:: 3870UpdateNodeOperands(SDValue InN, const SDValue *Ops, unsigned NumOps) { 3871 SDNode *N = InN.getNode(); 3872 assert(N->getNumOperands() == NumOps && 3873 "Update with wrong number of operands"); 3874 3875 // Check to see if there is no change. 3876 bool AnyChange = false; 3877 for (unsigned i = 0; i != NumOps; ++i) { 3878 if (Ops[i] != N->getOperand(i)) { 3879 AnyChange = true; 3880 break; 3881 } 3882 } 3883 3884 // No operands changed, just return the input node. 3885 if (!AnyChange) return InN; 3886 3887 // See if the modified node already exists. 3888 void *InsertPos = 0; 3889 if (SDNode *Existing = FindModifiedNodeSlot(N, Ops, NumOps, InsertPos)) 3890 return SDValue(Existing, InN.getResNo()); 3891 3892 // Nope it doesn't. Remove the node from its current place in the maps. 3893 if (InsertPos) 3894 if (!RemoveNodeFromCSEMaps(N)) 3895 InsertPos = 0; 3896 3897 // Now we update the operands. 3898 for (unsigned i = 0; i != NumOps; ++i) { 3899 if (N->OperandList[i] != Ops[i]) { 3900 N->OperandList[i].getVal()->removeUser(i, N); 3901 N->OperandList[i] = Ops[i]; 3902 N->OperandList[i].setUser(N); 3903 Ops[i].getNode()->addUser(i, N); 3904 } 3905 } 3906 3907 // If this gets put into a CSE map, add it. 3908 if (InsertPos) CSEMap.InsertNode(N, InsertPos); 3909 return InN; 3910} 3911 3912/// DropOperands - Release the operands and set this node to have 3913/// zero operands. 3914void SDNode::DropOperands() { 3915 // Unlike the code in MorphNodeTo that does this, we don't need to 3916 // watch for dead nodes here. 3917 for (op_iterator I = op_begin(), E = op_end(); I != E; ++I) 3918 I->getVal()->removeUser(std::distance(op_begin(), I), this); 3919 3920 NumOperands = 0; 3921} 3922 3923/// SelectNodeTo - These are wrappers around MorphNodeTo that accept a 3924/// machine opcode. 3925/// 3926SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 3927 MVT VT) { 3928 SDVTList VTs = getVTList(VT); 3929 return SelectNodeTo(N, MachineOpc, VTs, 0, 0); 3930} 3931 3932SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 3933 MVT VT, SDValue Op1) { 3934 SDVTList VTs = getVTList(VT); 3935 SDValue Ops[] = { Op1 }; 3936 return SelectNodeTo(N, MachineOpc, VTs, Ops, 1); 3937} 3938 3939SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 3940 MVT VT, SDValue Op1, 3941 SDValue Op2) { 3942 SDVTList VTs = getVTList(VT); 3943 SDValue Ops[] = { Op1, Op2 }; 3944 return SelectNodeTo(N, MachineOpc, VTs, Ops, 2); 3945} 3946 3947SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 3948 MVT VT, SDValue Op1, 3949 SDValue Op2, SDValue Op3) { 3950 SDVTList VTs = getVTList(VT); 3951 SDValue Ops[] = { Op1, Op2, Op3 }; 3952 return SelectNodeTo(N, MachineOpc, VTs, Ops, 3); 3953} 3954 3955SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 3956 MVT VT, const SDValue *Ops, 3957 unsigned NumOps) { 3958 SDVTList VTs = getVTList(VT); 3959 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 3960} 3961 3962SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 3963 MVT VT1, MVT VT2, const SDValue *Ops, 3964 unsigned NumOps) { 3965 SDVTList VTs = getVTList(VT1, VT2); 3966 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 3967} 3968 3969SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 3970 MVT VT1, MVT VT2) { 3971 SDVTList VTs = getVTList(VT1, VT2); 3972 return SelectNodeTo(N, MachineOpc, VTs, (SDValue *)0, 0); 3973} 3974 3975SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 3976 MVT VT1, MVT VT2, MVT VT3, 3977 const SDValue *Ops, unsigned NumOps) { 3978 SDVTList VTs = getVTList(VT1, VT2, VT3); 3979 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 3980} 3981 3982SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 3983 MVT VT1, MVT VT2, 3984 SDValue Op1) { 3985 SDVTList VTs = getVTList(VT1, VT2); 3986 SDValue Ops[] = { Op1 }; 3987 return SelectNodeTo(N, MachineOpc, VTs, Ops, 1); 3988} 3989 3990SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 3991 MVT VT1, MVT VT2, 3992 SDValue Op1, SDValue Op2) { 3993 SDVTList VTs = getVTList(VT1, VT2); 3994 SDValue Ops[] = { Op1, Op2 }; 3995 return SelectNodeTo(N, MachineOpc, VTs, Ops, 2); 3996} 3997 3998SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 3999 MVT VT1, MVT VT2, 4000 SDValue Op1, SDValue Op2, 4001 SDValue Op3) { 4002 SDVTList VTs = getVTList(VT1, VT2); 4003 SDValue Ops[] = { Op1, Op2, Op3 }; 4004 return SelectNodeTo(N, MachineOpc, VTs, Ops, 3); 4005} 4006 4007SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4008 SDVTList VTs, const SDValue *Ops, 4009 unsigned NumOps) { 4010 return MorphNodeTo(N, ~MachineOpc, VTs, Ops, NumOps); 4011} 4012 4013SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4014 MVT VT) { 4015 SDVTList VTs = getVTList(VT); 4016 return MorphNodeTo(N, Opc, VTs, 0, 0); 4017} 4018 4019SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4020 MVT VT, SDValue Op1) { 4021 SDVTList VTs = getVTList(VT); 4022 SDValue Ops[] = { Op1 }; 4023 return MorphNodeTo(N, Opc, VTs, Ops, 1); 4024} 4025 4026SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4027 MVT VT, SDValue Op1, 4028 SDValue Op2) { 4029 SDVTList VTs = getVTList(VT); 4030 SDValue Ops[] = { Op1, Op2 }; 4031 return MorphNodeTo(N, Opc, VTs, Ops, 2); 4032} 4033 4034SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4035 MVT VT, SDValue Op1, 4036 SDValue Op2, SDValue Op3) { 4037 SDVTList VTs = getVTList(VT); 4038 SDValue Ops[] = { Op1, Op2, Op3 }; 4039 return MorphNodeTo(N, Opc, VTs, Ops, 3); 4040} 4041 4042SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4043 MVT VT, const SDValue *Ops, 4044 unsigned NumOps) { 4045 SDVTList VTs = getVTList(VT); 4046 return MorphNodeTo(N, Opc, VTs, Ops, NumOps); 4047} 4048 4049SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4050 MVT VT1, MVT VT2, const SDValue *Ops, 4051 unsigned NumOps) { 4052 SDVTList VTs = getVTList(VT1, VT2); 4053 return MorphNodeTo(N, Opc, VTs, Ops, NumOps); 4054} 4055 4056SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4057 MVT VT1, MVT VT2) { 4058 SDVTList VTs = getVTList(VT1, VT2); 4059 return MorphNodeTo(N, Opc, VTs, (SDValue *)0, 0); 4060} 4061 4062SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4063 MVT VT1, MVT VT2, MVT VT3, 4064 const SDValue *Ops, unsigned NumOps) { 4065 SDVTList VTs = getVTList(VT1, VT2, VT3); 4066 return MorphNodeTo(N, Opc, VTs, Ops, NumOps); 4067} 4068 4069SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4070 MVT VT1, MVT VT2, 4071 SDValue Op1) { 4072 SDVTList VTs = getVTList(VT1, VT2); 4073 SDValue Ops[] = { Op1 }; 4074 return MorphNodeTo(N, Opc, VTs, Ops, 1); 4075} 4076 4077SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4078 MVT VT1, MVT VT2, 4079 SDValue Op1, SDValue Op2) { 4080 SDVTList VTs = getVTList(VT1, VT2); 4081 SDValue Ops[] = { Op1, Op2 }; 4082 return MorphNodeTo(N, Opc, VTs, Ops, 2); 4083} 4084 4085SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4086 MVT VT1, MVT VT2, 4087 SDValue Op1, SDValue Op2, 4088 SDValue Op3) { 4089 SDVTList VTs = getVTList(VT1, VT2); 4090 SDValue Ops[] = { Op1, Op2, Op3 }; 4091 return MorphNodeTo(N, Opc, VTs, Ops, 3); 4092} 4093 4094/// MorphNodeTo - These *mutate* the specified node to have the specified 4095/// return type, opcode, and operands. 4096/// 4097/// Note that MorphNodeTo returns the resultant node. If there is already a 4098/// node of the specified opcode and operands, it returns that node instead of 4099/// the current one. 4100/// 4101/// Using MorphNodeTo is faster than creating a new node and swapping it in 4102/// with ReplaceAllUsesWith both because it often avoids allocating a new 4103/// node, and because it doesn't require CSE recalculation for any of 4104/// the node's users. 4105/// 4106SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4107 SDVTList VTs, const SDValue *Ops, 4108 unsigned NumOps) { 4109 // If an identical node already exists, use it. 4110 void *IP = 0; 4111 if (VTs.VTs[VTs.NumVTs-1] != MVT::Flag) { 4112 FoldingSetNodeID ID; 4113 AddNodeIDNode(ID, Opc, VTs, Ops, NumOps); 4114 if (SDNode *ON = CSEMap.FindNodeOrInsertPos(ID, IP)) 4115 return ON; 4116 } 4117 4118 if (!RemoveNodeFromCSEMaps(N)) 4119 IP = 0; 4120 4121 // Start the morphing. 4122 N->NodeType = Opc; 4123 N->ValueList = VTs.VTs; 4124 N->NumValues = VTs.NumVTs; 4125 4126 // Clear the operands list, updating used nodes to remove this from their 4127 // use list. Keep track of any operands that become dead as a result. 4128 SmallPtrSet<SDNode*, 16> DeadNodeSet; 4129 for (SDNode::op_iterator B = N->op_begin(), I = B, E = N->op_end(); 4130 I != E; ++I) { 4131 SDNode *Used = I->getVal(); 4132 Used->removeUser(std::distance(B, I), N); 4133 if (Used->use_empty()) 4134 DeadNodeSet.insert(Used); 4135 } 4136 4137 // If NumOps is larger than the # of operands we currently have, reallocate 4138 // the operand list. 4139 if (NumOps > N->NumOperands) { 4140 if (N->OperandsNeedDelete) 4141 delete[] N->OperandList; 4142 if (N->isMachineOpcode()) { 4143 // We're creating a final node that will live unmorphed for the 4144 // remainder of the current SelectionDAG iteration, so we can allocate 4145 // the operands directly out of a pool with no recycling metadata. 4146 N->OperandList = OperandAllocator.Allocate<SDUse>(NumOps); 4147 N->OperandsNeedDelete = false; 4148 } else { 4149 N->OperandList = new SDUse[NumOps]; 4150 N->OperandsNeedDelete = true; 4151 } 4152 } 4153 4154 // Assign the new operands. 4155 N->NumOperands = NumOps; 4156 for (unsigned i = 0, e = NumOps; i != e; ++i) { 4157 N->OperandList[i] = Ops[i]; 4158 N->OperandList[i].setUser(N); 4159 SDNode *ToUse = N->OperandList[i].getVal(); 4160 ToUse->addUser(i, N); 4161 } 4162 4163 // Delete any nodes that are still dead after adding the uses for the 4164 // new operands. 4165 SmallVector<SDNode *, 16> DeadNodes; 4166 for (SmallPtrSet<SDNode *, 16>::iterator I = DeadNodeSet.begin(), 4167 E = DeadNodeSet.end(); I != E; ++I) 4168 if ((*I)->use_empty()) 4169 DeadNodes.push_back(*I); 4170 RemoveDeadNodes(DeadNodes); 4171 4172 if (IP) 4173 CSEMap.InsertNode(N, IP); // Memoize the new node. 4174 return N; 4175} 4176 4177 4178/// getTargetNode - These are used for target selectors to create a new node 4179/// with specified return type(s), target opcode, and operands. 4180/// 4181/// Note that getTargetNode returns the resultant node. If there is already a 4182/// node of the specified opcode and operands, it returns that node instead of 4183/// the current one. 4184SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT) { 4185 return getNode(~Opcode, VT).getNode(); 4186} 4187SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT, SDValue Op1) { 4188 return getNode(~Opcode, VT, Op1).getNode(); 4189} 4190SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT, 4191 SDValue Op1, SDValue Op2) { 4192 return getNode(~Opcode, VT, Op1, Op2).getNode(); 4193} 4194SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT, 4195 SDValue Op1, SDValue Op2, 4196 SDValue Op3) { 4197 return getNode(~Opcode, VT, Op1, Op2, Op3).getNode(); 4198} 4199SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT, 4200 const SDValue *Ops, unsigned NumOps) { 4201 return getNode(~Opcode, VT, Ops, NumOps).getNode(); 4202} 4203SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2) { 4204 const MVT *VTs = getNodeValueTypes(VT1, VT2); 4205 SDValue Op; 4206 return getNode(~Opcode, VTs, 2, &Op, 0).getNode(); 4207} 4208SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, 4209 MVT VT2, SDValue Op1) { 4210 const MVT *VTs = getNodeValueTypes(VT1, VT2); 4211 return getNode(~Opcode, VTs, 2, &Op1, 1).getNode(); 4212} 4213SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, 4214 MVT VT2, SDValue Op1, 4215 SDValue Op2) { 4216 const MVT *VTs = getNodeValueTypes(VT1, VT2); 4217 SDValue Ops[] = { Op1, Op2 }; 4218 return getNode(~Opcode, VTs, 2, Ops, 2).getNode(); 4219} 4220SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, 4221 MVT VT2, SDValue Op1, 4222 SDValue Op2, SDValue Op3) { 4223 const MVT *VTs = getNodeValueTypes(VT1, VT2); 4224 SDValue Ops[] = { Op1, Op2, Op3 }; 4225 return getNode(~Opcode, VTs, 2, Ops, 3).getNode(); 4226} 4227SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, 4228 const SDValue *Ops, unsigned NumOps) { 4229 const MVT *VTs = getNodeValueTypes(VT1, VT2); 4230 return getNode(~Opcode, VTs, 2, Ops, NumOps).getNode(); 4231} 4232SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3, 4233 SDValue Op1, SDValue Op2) { 4234 const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3); 4235 SDValue Ops[] = { Op1, Op2 }; 4236 return getNode(~Opcode, VTs, 3, Ops, 2).getNode(); 4237} 4238SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3, 4239 SDValue Op1, SDValue Op2, 4240 SDValue Op3) { 4241 const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3); 4242 SDValue Ops[] = { Op1, Op2, Op3 }; 4243 return getNode(~Opcode, VTs, 3, Ops, 3).getNode(); 4244} 4245SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3, 4246 const SDValue *Ops, unsigned NumOps) { 4247 const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3); 4248 return getNode(~Opcode, VTs, 3, Ops, NumOps).getNode(); 4249} 4250SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, 4251 MVT VT2, MVT VT3, MVT VT4, 4252 const SDValue *Ops, unsigned NumOps) { 4253 std::vector<MVT> VTList; 4254 VTList.push_back(VT1); 4255 VTList.push_back(VT2); 4256 VTList.push_back(VT3); 4257 VTList.push_back(VT4); 4258 const MVT *VTs = getNodeValueTypes(VTList); 4259 return getNode(~Opcode, VTs, 4, Ops, NumOps).getNode(); 4260} 4261SDNode *SelectionDAG::getTargetNode(unsigned Opcode, 4262 const std::vector<MVT> &ResultTys, 4263 const SDValue *Ops, unsigned NumOps) { 4264 const MVT *VTs = getNodeValueTypes(ResultTys); 4265 return getNode(~Opcode, VTs, ResultTys.size(), 4266 Ops, NumOps).getNode(); 4267} 4268 4269/// getNodeIfExists - Get the specified node if it's already available, or 4270/// else return NULL. 4271SDNode *SelectionDAG::getNodeIfExists(unsigned Opcode, SDVTList VTList, 4272 const SDValue *Ops, unsigned NumOps) { 4273 if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) { 4274 FoldingSetNodeID ID; 4275 AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps); 4276 void *IP = 0; 4277 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 4278 return E; 4279 } 4280 return NULL; 4281} 4282 4283 4284/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. 4285/// This can cause recursive merging of nodes in the DAG. 4286/// 4287/// This version assumes From has a single result value. 4288/// 4289void SelectionDAG::ReplaceAllUsesWith(SDValue FromN, SDValue To, 4290 DAGUpdateListener *UpdateListener) { 4291 SDNode *From = FromN.getNode(); 4292 assert(From->getNumValues() == 1 && FromN.getResNo() == 0 && 4293 "Cannot replace with this method!"); 4294 assert(From != To.getNode() && "Cannot replace uses of with self"); 4295 4296 while (!From->use_empty()) { 4297 SDNode::use_iterator UI = From->use_begin(); 4298 SDNode *U = *UI; 4299 4300 // This node is about to morph, remove its old self from the CSE maps. 4301 RemoveNodeFromCSEMaps(U); 4302 int operandNum = 0; 4303 for (SDNode::op_iterator I = U->op_begin(), E = U->op_end(); 4304 I != E; ++I, ++operandNum) 4305 if (I->getVal() == From) { 4306 From->removeUser(operandNum, U); 4307 *I = To; 4308 I->setUser(U); 4309 To.getNode()->addUser(operandNum, U); 4310 } 4311 4312 // Now that we have modified U, add it back to the CSE maps. If it already 4313 // exists there, recursively merge the results together. 4314 if (SDNode *Existing = AddNonLeafNodeToCSEMaps(U)) { 4315 ReplaceAllUsesWith(U, Existing, UpdateListener); 4316 // U is now dead. Inform the listener if it exists and delete it. 4317 if (UpdateListener) 4318 UpdateListener->NodeDeleted(U, Existing); 4319 DeleteNodeNotInCSEMaps(U); 4320 } else { 4321 // If the node doesn't already exist, we updated it. Inform a listener if 4322 // it exists. 4323 if (UpdateListener) 4324 UpdateListener->NodeUpdated(U); 4325 } 4326 } 4327} 4328 4329/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. 4330/// This can cause recursive merging of nodes in the DAG. 4331/// 4332/// This version assumes From/To have matching types and numbers of result 4333/// values. 4334/// 4335void SelectionDAG::ReplaceAllUsesWith(SDNode *From, SDNode *To, 4336 DAGUpdateListener *UpdateListener) { 4337 assert(From->getVTList().VTs == To->getVTList().VTs && 4338 From->getNumValues() == To->getNumValues() && 4339 "Cannot use this version of ReplaceAllUsesWith!"); 4340 4341 // Handle the trivial case. 4342 if (From == To) 4343 return; 4344 4345 while (!From->use_empty()) { 4346 SDNode::use_iterator UI = From->use_begin(); 4347 SDNode *U = *UI; 4348 4349 // This node is about to morph, remove its old self from the CSE maps. 4350 RemoveNodeFromCSEMaps(U); 4351 int operandNum = 0; 4352 for (SDNode::op_iterator I = U->op_begin(), E = U->op_end(); 4353 I != E; ++I, ++operandNum) 4354 if (I->getVal() == From) { 4355 From->removeUser(operandNum, U); 4356 I->getSDValue().setNode(To); 4357 To->addUser(operandNum, U); 4358 } 4359 4360 // Now that we have modified U, add it back to the CSE maps. If it already 4361 // exists there, recursively merge the results together. 4362 if (SDNode *Existing = AddNonLeafNodeToCSEMaps(U)) { 4363 ReplaceAllUsesWith(U, Existing, UpdateListener); 4364 // U is now dead. Inform the listener if it exists and delete it. 4365 if (UpdateListener) 4366 UpdateListener->NodeDeleted(U, Existing); 4367 DeleteNodeNotInCSEMaps(U); 4368 } else { 4369 // If the node doesn't already exist, we updated it. Inform a listener if 4370 // it exists. 4371 if (UpdateListener) 4372 UpdateListener->NodeUpdated(U); 4373 } 4374 } 4375} 4376 4377/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. 4378/// This can cause recursive merging of nodes in the DAG. 4379/// 4380/// This version can replace From with any result values. To must match the 4381/// number and types of values returned by From. 4382void SelectionDAG::ReplaceAllUsesWith(SDNode *From, 4383 const SDValue *To, 4384 DAGUpdateListener *UpdateListener) { 4385 if (From->getNumValues() == 1) // Handle the simple case efficiently. 4386 return ReplaceAllUsesWith(SDValue(From, 0), To[0], UpdateListener); 4387 4388 while (!From->use_empty()) { 4389 SDNode::use_iterator UI = From->use_begin(); 4390 SDNode *U = *UI; 4391 4392 // This node is about to morph, remove its old self from the CSE maps. 4393 RemoveNodeFromCSEMaps(U); 4394 int operandNum = 0; 4395 for (SDNode::op_iterator I = U->op_begin(), E = U->op_end(); 4396 I != E; ++I, ++operandNum) 4397 if (I->getVal() == From) { 4398 const SDValue &ToOp = To[I->getSDValue().getResNo()]; 4399 From->removeUser(operandNum, U); 4400 *I = ToOp; 4401 I->setUser(U); 4402 ToOp.getNode()->addUser(operandNum, U); 4403 } 4404 4405 // Now that we have modified U, add it back to the CSE maps. If it already 4406 // exists there, recursively merge the results together. 4407 if (SDNode *Existing = AddNonLeafNodeToCSEMaps(U)) { 4408 ReplaceAllUsesWith(U, Existing, UpdateListener); 4409 // U is now dead. Inform the listener if it exists and delete it. 4410 if (UpdateListener) 4411 UpdateListener->NodeDeleted(U, Existing); 4412 DeleteNodeNotInCSEMaps(U); 4413 } else { 4414 // If the node doesn't already exist, we updated it. Inform a listener if 4415 // it exists. 4416 if (UpdateListener) 4417 UpdateListener->NodeUpdated(U); 4418 } 4419 } 4420} 4421 4422/// ReplaceAllUsesOfValueWith - Replace any uses of From with To, leaving 4423/// uses of other values produced by From.getVal() alone. The Deleted vector is 4424/// handled the same way as for ReplaceAllUsesWith. 4425void SelectionDAG::ReplaceAllUsesOfValueWith(SDValue From, SDValue To, 4426 DAGUpdateListener *UpdateListener){ 4427 // Handle the really simple, really trivial case efficiently. 4428 if (From == To) return; 4429 4430 // Handle the simple, trivial, case efficiently. 4431 if (From.getNode()->getNumValues() == 1) { 4432 ReplaceAllUsesWith(From, To, UpdateListener); 4433 return; 4434 } 4435 4436 // Get all of the users of From.getNode(). We want these in a nice, 4437 // deterministically ordered and uniqued set, so we use a SmallSetVector. 4438 SmallSetVector<SDNode*, 16> Users(From.getNode()->use_begin(), From.getNode()->use_end()); 4439 4440 while (!Users.empty()) { 4441 // We know that this user uses some value of From. If it is the right 4442 // value, update it. 4443 SDNode *User = Users.back(); 4444 Users.pop_back(); 4445 4446 // Scan for an operand that matches From. 4447 SDNode::op_iterator Op = User->op_begin(), E = User->op_end(); 4448 for (; Op != E; ++Op) 4449 if (*Op == From) break; 4450 4451 // If there are no matches, the user must use some other result of From. 4452 if (Op == E) continue; 4453 4454 // Okay, we know this user needs to be updated. Remove its old self 4455 // from the CSE maps. 4456 RemoveNodeFromCSEMaps(User); 4457 4458 // Update all operands that match "From" in case there are multiple uses. 4459 for (; Op != E; ++Op) { 4460 if (*Op == From) { 4461 From.getNode()->removeUser(Op-User->op_begin(), User); 4462 *Op = To; 4463 Op->setUser(User); 4464 To.getNode()->addUser(Op-User->op_begin(), User); 4465 } 4466 } 4467 4468 // Now that we have modified User, add it back to the CSE maps. If it 4469 // already exists there, recursively merge the results together. 4470 SDNode *Existing = AddNonLeafNodeToCSEMaps(User); 4471 if (!Existing) { 4472 if (UpdateListener) UpdateListener->NodeUpdated(User); 4473 continue; // Continue on to next user. 4474 } 4475 4476 // If there was already an existing matching node, use ReplaceAllUsesWith 4477 // to replace the dead one with the existing one. This can cause 4478 // recursive merging of other unrelated nodes down the line. 4479 ReplaceAllUsesWith(User, Existing, UpdateListener); 4480 4481 // User is now dead. Notify a listener if present. 4482 if (UpdateListener) UpdateListener->NodeDeleted(User, Existing); 4483 DeleteNodeNotInCSEMaps(User); 4484 } 4485} 4486 4487/// ReplaceAllUsesOfValuesWith - Replace any uses of From with To, leaving 4488/// uses of other values produced by From.getVal() alone. The same value may 4489/// appear in both the From and To list. The Deleted vector is 4490/// handled the same way as for ReplaceAllUsesWith. 4491void SelectionDAG::ReplaceAllUsesOfValuesWith(const SDValue *From, 4492 const SDValue *To, 4493 unsigned Num, 4494 DAGUpdateListener *UpdateListener){ 4495 // Handle the simple, trivial case efficiently. 4496 if (Num == 1) 4497 return ReplaceAllUsesOfValueWith(*From, *To, UpdateListener); 4498 4499 SmallVector<std::pair<SDNode *, unsigned>, 16> Users; 4500 for (unsigned i = 0; i != Num; ++i) 4501 for (SDNode::use_iterator UI = From[i].getNode()->use_begin(), 4502 E = From[i].getNode()->use_end(); UI != E; ++UI) 4503 Users.push_back(std::make_pair(*UI, i)); 4504 4505 while (!Users.empty()) { 4506 // We know that this user uses some value of From. If it is the right 4507 // value, update it. 4508 SDNode *User = Users.back().first; 4509 unsigned i = Users.back().second; 4510 Users.pop_back(); 4511 4512 // Scan for an operand that matches From. 4513 SDNode::op_iterator Op = User->op_begin(), E = User->op_end(); 4514 for (; Op != E; ++Op) 4515 if (*Op == From[i]) break; 4516 4517 // If there are no matches, the user must use some other result of From. 4518 if (Op == E) continue; 4519 4520 // Okay, we know this user needs to be updated. Remove its old self 4521 // from the CSE maps. 4522 RemoveNodeFromCSEMaps(User); 4523 4524 // Update all operands that match "From" in case there are multiple uses. 4525 for (; Op != E; ++Op) { 4526 if (*Op == From[i]) { 4527 From[i].getNode()->removeUser(Op-User->op_begin(), User); 4528 *Op = To[i]; 4529 Op->setUser(User); 4530 To[i].getNode()->addUser(Op-User->op_begin(), User); 4531 } 4532 } 4533 4534 // Now that we have modified User, add it back to the CSE maps. If it 4535 // already exists there, recursively merge the results together. 4536 SDNode *Existing = AddNonLeafNodeToCSEMaps(User); 4537 if (!Existing) { 4538 if (UpdateListener) UpdateListener->NodeUpdated(User); 4539 continue; // Continue on to next user. 4540 } 4541 4542 // If there was already an existing matching node, use ReplaceAllUsesWith 4543 // to replace the dead one with the existing one. This can cause 4544 // recursive merging of other unrelated nodes down the line. 4545 ReplaceAllUsesWith(User, Existing, UpdateListener); 4546 4547 // User is now dead. Notify a listener if present. 4548 if (UpdateListener) UpdateListener->NodeDeleted(User, Existing); 4549 DeleteNodeNotInCSEMaps(User); 4550 } 4551} 4552 4553/// AssignTopologicalOrder - Assign a unique node id for each node in the DAG 4554/// based on their topological order. It returns the maximum id and a vector 4555/// of the SDNodes* in assigned order by reference. 4556unsigned SelectionDAG::AssignTopologicalOrder(std::vector<SDNode*> &TopOrder) { 4557 unsigned DAGSize = AllNodes.size(); 4558 std::vector<SDNode*> Sources; 4559 4560 for (allnodes_iterator I = allnodes_begin(),E = allnodes_end(); I != E; ++I){ 4561 SDNode *N = I; 4562 unsigned Degree = N->use_size(); 4563 // Temporarily use the Node Id as scratch space for the degree count. 4564 N->setNodeId(Degree); 4565 if (Degree == 0) 4566 Sources.push_back(N); 4567 } 4568 4569 TopOrder.clear(); 4570 TopOrder.reserve(DAGSize); 4571 int Id = 0; 4572 while (!Sources.empty()) { 4573 SDNode *N = Sources.back(); 4574 Sources.pop_back(); 4575 TopOrder.push_back(N); 4576 N->setNodeId(Id++); 4577 for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ++I) { 4578 SDNode *P = I->getVal(); 4579 unsigned Degree = P->getNodeId(); 4580 --Degree; 4581 P->setNodeId(Degree); 4582 if (Degree == 0) 4583 Sources.push_back(P); 4584 } 4585 } 4586 4587 return Id; 4588} 4589 4590 4591 4592//===----------------------------------------------------------------------===// 4593// SDNode Class 4594//===----------------------------------------------------------------------===// 4595 4596// Out-of-line virtual method to give class a home. 4597void SDNode::ANCHOR() {} 4598void UnarySDNode::ANCHOR() {} 4599void BinarySDNode::ANCHOR() {} 4600void TernarySDNode::ANCHOR() {} 4601void HandleSDNode::ANCHOR() {} 4602void ConstantSDNode::ANCHOR() {} 4603void ConstantFPSDNode::ANCHOR() {} 4604void GlobalAddressSDNode::ANCHOR() {} 4605void FrameIndexSDNode::ANCHOR() {} 4606void JumpTableSDNode::ANCHOR() {} 4607void ConstantPoolSDNode::ANCHOR() {} 4608void BasicBlockSDNode::ANCHOR() {} 4609void SrcValueSDNode::ANCHOR() {} 4610void MemOperandSDNode::ANCHOR() {} 4611void RegisterSDNode::ANCHOR() {} 4612void DbgStopPointSDNode::ANCHOR() {} 4613void LabelSDNode::ANCHOR() {} 4614void SymbolSDNode::ANCHOR() {} 4615void CondCodeSDNode::ANCHOR() {} 4616void ARG_FLAGSSDNode::ANCHOR() {} 4617void VTSDNode::ANCHOR() {} 4618void MemSDNode::ANCHOR() {} 4619void LoadSDNode::ANCHOR() {} 4620void StoreSDNode::ANCHOR() {} 4621void AtomicSDNode::ANCHOR() {} 4622void CallSDNode::ANCHOR() {} 4623 4624HandleSDNode::~HandleSDNode() { 4625 DropOperands(); 4626} 4627 4628GlobalAddressSDNode::GlobalAddressSDNode(bool isTarget, const GlobalValue *GA, 4629 MVT VT, int o) 4630 : SDNode(isa<GlobalVariable>(GA) && 4631 cast<GlobalVariable>(GA)->isThreadLocal() ? 4632 // Thread Local 4633 (isTarget ? ISD::TargetGlobalTLSAddress : ISD::GlobalTLSAddress) : 4634 // Non Thread Local 4635 (isTarget ? ISD::TargetGlobalAddress : ISD::GlobalAddress), 4636 getSDVTList(VT)), Offset(o) { 4637 TheGlobal = const_cast<GlobalValue*>(GA); 4638} 4639 4640MemSDNode::MemSDNode(unsigned Opc, SDVTList VTs, MVT memvt, 4641 const Value *srcValue, int SVO, 4642 unsigned alignment, bool vol) 4643 : SDNode(Opc, VTs), MemoryVT(memvt), SrcValue(srcValue), SVOffset(SVO), 4644 Flags(encodeMemSDNodeFlags(vol, alignment)) { 4645 4646 assert(isPowerOf2_32(alignment) && "Alignment is not a power of 2!"); 4647 assert(getAlignment() == alignment && "Alignment representation error!"); 4648 assert(isVolatile() == vol && "Volatile representation error!"); 4649} 4650 4651/// getMemOperand - Return a MachineMemOperand object describing the memory 4652/// reference performed by this memory reference. 4653MachineMemOperand MemSDNode::getMemOperand() const { 4654 int Flags; 4655 if (isa<LoadSDNode>(this)) 4656 Flags = MachineMemOperand::MOLoad; 4657 else if (isa<StoreSDNode>(this)) 4658 Flags = MachineMemOperand::MOStore; 4659 else { 4660 assert(isa<AtomicSDNode>(this) && "Unknown MemSDNode opcode!"); 4661 Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore; 4662 } 4663 4664 int Size = (getMemoryVT().getSizeInBits() + 7) >> 3; 4665 if (isVolatile()) Flags |= MachineMemOperand::MOVolatile; 4666 4667 // Check if the memory reference references a frame index 4668 const FrameIndexSDNode *FI = 4669 dyn_cast<const FrameIndexSDNode>(getBasePtr().getNode()); 4670 if (!getSrcValue() && FI) 4671 return MachineMemOperand(PseudoSourceValue::getFixedStack(FI->getIndex()), 4672 Flags, 0, Size, getAlignment()); 4673 else 4674 return MachineMemOperand(getSrcValue(), Flags, getSrcValueOffset(), 4675 Size, getAlignment()); 4676} 4677 4678/// Profile - Gather unique data for the node. 4679/// 4680void SDNode::Profile(FoldingSetNodeID &ID) const { 4681 AddNodeIDNode(ID, this); 4682} 4683 4684/// getValueTypeList - Return a pointer to the specified value type. 4685/// 4686const MVT *SDNode::getValueTypeList(MVT VT) { 4687 if (VT.isExtended()) { 4688 static std::set<MVT, MVT::compareRawBits> EVTs; 4689 return &(*EVTs.insert(VT).first); 4690 } else { 4691 static MVT VTs[MVT::LAST_VALUETYPE]; 4692 VTs[VT.getSimpleVT()] = VT; 4693 return &VTs[VT.getSimpleVT()]; 4694 } 4695} 4696 4697/// hasNUsesOfValue - Return true if there are exactly NUSES uses of the 4698/// indicated value. This method ignores uses of other values defined by this 4699/// operation. 4700bool SDNode::hasNUsesOfValue(unsigned NUses, unsigned Value) const { 4701 assert(Value < getNumValues() && "Bad value!"); 4702 4703 // TODO: Only iterate over uses of a given value of the node 4704 for (SDNode::use_iterator UI = use_begin(), E = use_end(); UI != E; ++UI) { 4705 if (UI.getUse().getSDValue().getResNo() == Value) { 4706 if (NUses == 0) 4707 return false; 4708 --NUses; 4709 } 4710 } 4711 4712 // Found exactly the right number of uses? 4713 return NUses == 0; 4714} 4715 4716 4717/// hasAnyUseOfValue - Return true if there are any use of the indicated 4718/// value. This method ignores uses of other values defined by this operation. 4719bool SDNode::hasAnyUseOfValue(unsigned Value) const { 4720 assert(Value < getNumValues() && "Bad value!"); 4721 4722 for (SDNode::use_iterator UI = use_begin(), E = use_end(); UI != E; ++UI) 4723 if (UI.getUse().getSDValue().getResNo() == Value) 4724 return true; 4725 4726 return false; 4727} 4728 4729 4730/// isOnlyUserOf - Return true if this node is the only use of N. 4731/// 4732bool SDNode::isOnlyUserOf(SDNode *N) const { 4733 bool Seen = false; 4734 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 4735 SDNode *User = *I; 4736 if (User == this) 4737 Seen = true; 4738 else 4739 return false; 4740 } 4741 4742 return Seen; 4743} 4744 4745/// isOperand - Return true if this node is an operand of N. 4746/// 4747bool SDValue::isOperandOf(SDNode *N) const { 4748 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 4749 if (*this == N->getOperand(i)) 4750 return true; 4751 return false; 4752} 4753 4754bool SDNode::isOperandOf(SDNode *N) const { 4755 for (unsigned i = 0, e = N->NumOperands; i != e; ++i) 4756 if (this == N->OperandList[i].getVal()) 4757 return true; 4758 return false; 4759} 4760 4761/// reachesChainWithoutSideEffects - Return true if this operand (which must 4762/// be a chain) reaches the specified operand without crossing any 4763/// side-effecting instructions. In practice, this looks through token 4764/// factors and non-volatile loads. In order to remain efficient, this only 4765/// looks a couple of nodes in, it does not do an exhaustive search. 4766bool SDValue::reachesChainWithoutSideEffects(SDValue Dest, 4767 unsigned Depth) const { 4768 if (*this == Dest) return true; 4769 4770 // Don't search too deeply, we just want to be able to see through 4771 // TokenFactor's etc. 4772 if (Depth == 0) return false; 4773 4774 // If this is a token factor, all inputs to the TF happen in parallel. If any 4775 // of the operands of the TF reach dest, then we can do the xform. 4776 if (getOpcode() == ISD::TokenFactor) { 4777 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) 4778 if (getOperand(i).reachesChainWithoutSideEffects(Dest, Depth-1)) 4779 return true; 4780 return false; 4781 } 4782 4783 // Loads don't have side effects, look through them. 4784 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(*this)) { 4785 if (!Ld->isVolatile()) 4786 return Ld->getChain().reachesChainWithoutSideEffects(Dest, Depth-1); 4787 } 4788 return false; 4789} 4790 4791 4792static void findPredecessor(SDNode *N, const SDNode *P, bool &found, 4793 SmallPtrSet<SDNode *, 32> &Visited) { 4794 if (found || !Visited.insert(N)) 4795 return; 4796 4797 for (unsigned i = 0, e = N->getNumOperands(); !found && i != e; ++i) { 4798 SDNode *Op = N->getOperand(i).getNode(); 4799 if (Op == P) { 4800 found = true; 4801 return; 4802 } 4803 findPredecessor(Op, P, found, Visited); 4804 } 4805} 4806 4807/// isPredecessorOf - Return true if this node is a predecessor of N. This node 4808/// is either an operand of N or it can be reached by recursively traversing 4809/// up the operands. 4810/// NOTE: this is an expensive method. Use it carefully. 4811bool SDNode::isPredecessorOf(SDNode *N) const { 4812 SmallPtrSet<SDNode *, 32> Visited; 4813 bool found = false; 4814 findPredecessor(N, this, found, Visited); 4815 return found; 4816} 4817 4818uint64_t SDNode::getConstantOperandVal(unsigned Num) const { 4819 assert(Num < NumOperands && "Invalid child # of SDNode!"); 4820 return cast<ConstantSDNode>(OperandList[Num])->getZExtValue(); 4821} 4822 4823std::string SDNode::getOperationName(const SelectionDAG *G) const { 4824 switch (getOpcode()) { 4825 default: 4826 if (getOpcode() < ISD::BUILTIN_OP_END) 4827 return "<<Unknown DAG Node>>"; 4828 if (isMachineOpcode()) { 4829 if (G) 4830 if (const TargetInstrInfo *TII = G->getTarget().getInstrInfo()) 4831 if (getMachineOpcode() < TII->getNumOpcodes()) 4832 return TII->get(getMachineOpcode()).getName(); 4833 return "<<Unknown Machine Node>>"; 4834 } 4835 if (G) { 4836 TargetLowering &TLI = G->getTargetLoweringInfo(); 4837 const char *Name = TLI.getTargetNodeName(getOpcode()); 4838 if (Name) return Name; 4839 return "<<Unknown Target Node>>"; 4840 } 4841 return "<<Unknown Node>>"; 4842 4843#ifndef NDEBUG 4844 case ISD::DELETED_NODE: 4845 return "<<Deleted Node!>>"; 4846#endif 4847 case ISD::PREFETCH: return "Prefetch"; 4848 case ISD::MEMBARRIER: return "MemBarrier"; 4849 case ISD::ATOMIC_CMP_SWAP_8: return "AtomicCmpSwap8"; 4850 case ISD::ATOMIC_SWAP_8: return "AtomicSwap8"; 4851 case ISD::ATOMIC_LOAD_ADD_8: return "AtomicLoadAdd8"; 4852 case ISD::ATOMIC_LOAD_SUB_8: return "AtomicLoadSub8"; 4853 case ISD::ATOMIC_LOAD_AND_8: return "AtomicLoadAnd8"; 4854 case ISD::ATOMIC_LOAD_OR_8: return "AtomicLoadOr8"; 4855 case ISD::ATOMIC_LOAD_XOR_8: return "AtomicLoadXor8"; 4856 case ISD::ATOMIC_LOAD_NAND_8: return "AtomicLoadNand8"; 4857 case ISD::ATOMIC_LOAD_MIN_8: return "AtomicLoadMin8"; 4858 case ISD::ATOMIC_LOAD_MAX_8: return "AtomicLoadMax8"; 4859 case ISD::ATOMIC_LOAD_UMIN_8: return "AtomicLoadUMin8"; 4860 case ISD::ATOMIC_LOAD_UMAX_8: return "AtomicLoadUMax8"; 4861 case ISD::ATOMIC_CMP_SWAP_16: return "AtomicCmpSwap16"; 4862 case ISD::ATOMIC_SWAP_16: return "AtomicSwap16"; 4863 case ISD::ATOMIC_LOAD_ADD_16: return "AtomicLoadAdd16"; 4864 case ISD::ATOMIC_LOAD_SUB_16: return "AtomicLoadSub16"; 4865 case ISD::ATOMIC_LOAD_AND_16: return "AtomicLoadAnd16"; 4866 case ISD::ATOMIC_LOAD_OR_16: return "AtomicLoadOr16"; 4867 case ISD::ATOMIC_LOAD_XOR_16: return "AtomicLoadXor16"; 4868 case ISD::ATOMIC_LOAD_NAND_16: return "AtomicLoadNand16"; 4869 case ISD::ATOMIC_LOAD_MIN_16: return "AtomicLoadMin16"; 4870 case ISD::ATOMIC_LOAD_MAX_16: return "AtomicLoadMax16"; 4871 case ISD::ATOMIC_LOAD_UMIN_16: return "AtomicLoadUMin16"; 4872 case ISD::ATOMIC_LOAD_UMAX_16: return "AtomicLoadUMax16"; 4873 case ISD::ATOMIC_CMP_SWAP_32: return "AtomicCmpSwap32"; 4874 case ISD::ATOMIC_SWAP_32: return "AtomicSwap32"; 4875 case ISD::ATOMIC_LOAD_ADD_32: return "AtomicLoadAdd32"; 4876 case ISD::ATOMIC_LOAD_SUB_32: return "AtomicLoadSub32"; 4877 case ISD::ATOMIC_LOAD_AND_32: return "AtomicLoadAnd32"; 4878 case ISD::ATOMIC_LOAD_OR_32: return "AtomicLoadOr32"; 4879 case ISD::ATOMIC_LOAD_XOR_32: return "AtomicLoadXor32"; 4880 case ISD::ATOMIC_LOAD_NAND_32: return "AtomicLoadNand32"; 4881 case ISD::ATOMIC_LOAD_MIN_32: return "AtomicLoadMin32"; 4882 case ISD::ATOMIC_LOAD_MAX_32: return "AtomicLoadMax32"; 4883 case ISD::ATOMIC_LOAD_UMIN_32: return "AtomicLoadUMin32"; 4884 case ISD::ATOMIC_LOAD_UMAX_32: return "AtomicLoadUMax32"; 4885 case ISD::ATOMIC_CMP_SWAP_64: return "AtomicCmpSwap64"; 4886 case ISD::ATOMIC_SWAP_64: return "AtomicSwap64"; 4887 case ISD::ATOMIC_LOAD_ADD_64: return "AtomicLoadAdd64"; 4888 case ISD::ATOMIC_LOAD_SUB_64: return "AtomicLoadSub64"; 4889 case ISD::ATOMIC_LOAD_AND_64: return "AtomicLoadAnd64"; 4890 case ISD::ATOMIC_LOAD_OR_64: return "AtomicLoadOr64"; 4891 case ISD::ATOMIC_LOAD_XOR_64: return "AtomicLoadXor64"; 4892 case ISD::ATOMIC_LOAD_NAND_64: return "AtomicLoadNand64"; 4893 case ISD::ATOMIC_LOAD_MIN_64: return "AtomicLoadMin64"; 4894 case ISD::ATOMIC_LOAD_MAX_64: return "AtomicLoadMax64"; 4895 case ISD::ATOMIC_LOAD_UMIN_64: return "AtomicLoadUMin64"; 4896 case ISD::ATOMIC_LOAD_UMAX_64: return "AtomicLoadUMax64"; 4897 case ISD::PCMARKER: return "PCMarker"; 4898 case ISD::READCYCLECOUNTER: return "ReadCycleCounter"; 4899 case ISD::SRCVALUE: return "SrcValue"; 4900 case ISD::MEMOPERAND: return "MemOperand"; 4901 case ISD::EntryToken: return "EntryToken"; 4902 case ISD::TokenFactor: return "TokenFactor"; 4903 case ISD::AssertSext: return "AssertSext"; 4904 case ISD::AssertZext: return "AssertZext"; 4905 4906 case ISD::BasicBlock: return "BasicBlock"; 4907 case ISD::ARG_FLAGS: return "ArgFlags"; 4908 case ISD::VALUETYPE: return "ValueType"; 4909 case ISD::Register: return "Register"; 4910 4911 case ISD::Constant: return "Constant"; 4912 case ISD::ConstantFP: return "ConstantFP"; 4913 case ISD::GlobalAddress: return "GlobalAddress"; 4914 case ISD::GlobalTLSAddress: return "GlobalTLSAddress"; 4915 case ISD::FrameIndex: return "FrameIndex"; 4916 case ISD::JumpTable: return "JumpTable"; 4917 case ISD::GLOBAL_OFFSET_TABLE: return "GLOBAL_OFFSET_TABLE"; 4918 case ISD::RETURNADDR: return "RETURNADDR"; 4919 case ISD::FRAMEADDR: return "FRAMEADDR"; 4920 case ISD::FRAME_TO_ARGS_OFFSET: return "FRAME_TO_ARGS_OFFSET"; 4921 case ISD::EXCEPTIONADDR: return "EXCEPTIONADDR"; 4922 case ISD::EHSELECTION: return "EHSELECTION"; 4923 case ISD::EH_RETURN: return "EH_RETURN"; 4924 case ISD::ConstantPool: return "ConstantPool"; 4925 case ISD::Symbol: return "Symbol"; 4926 case ISD::INTRINSIC_WO_CHAIN: { 4927 unsigned IID = cast<ConstantSDNode>(getOperand(0))->getZExtValue(); 4928 return Intrinsic::getName((Intrinsic::ID)IID); 4929 } 4930 case ISD::INTRINSIC_VOID: 4931 case ISD::INTRINSIC_W_CHAIN: { 4932 unsigned IID = cast<ConstantSDNode>(getOperand(1))->getZExtValue(); 4933 return Intrinsic::getName((Intrinsic::ID)IID); 4934 } 4935 4936 case ISD::BUILD_VECTOR: return "BUILD_VECTOR"; 4937 case ISD::TargetConstant: return "TargetConstant"; 4938 case ISD::TargetConstantFP:return "TargetConstantFP"; 4939 case ISD::TargetGlobalAddress: return "TargetGlobalAddress"; 4940 case ISD::TargetGlobalTLSAddress: return "TargetGlobalTLSAddress"; 4941 case ISD::TargetFrameIndex: return "TargetFrameIndex"; 4942 case ISD::TargetJumpTable: return "TargetJumpTable"; 4943 case ISD::TargetConstantPool: return "TargetConstantPool"; 4944 case ISD::TargetSymbol: return "TargetSymbol"; 4945 4946 case ISD::CopyToReg: return "CopyToReg"; 4947 case ISD::CopyFromReg: return "CopyFromReg"; 4948 case ISD::UNDEF: return "undef"; 4949 case ISD::MERGE_VALUES: return "merge_values"; 4950 case ISD::INLINEASM: return "inlineasm"; 4951 case ISD::DBG_LABEL: return "dbg_label"; 4952 case ISD::EH_LABEL: return "eh_label"; 4953 case ISD::DECLARE: return "declare"; 4954 case ISD::HANDLENODE: return "handlenode"; 4955 case ISD::FORMAL_ARGUMENTS: return "formal_arguments"; 4956 case ISD::CALL: return "call"; 4957 4958 // Unary operators 4959 case ISD::FABS: return "fabs"; 4960 case ISD::FNEG: return "fneg"; 4961 case ISD::FSQRT: return "fsqrt"; 4962 case ISD::FSIN: return "fsin"; 4963 case ISD::FCOS: return "fcos"; 4964 case ISD::FPOWI: return "fpowi"; 4965 case ISD::FPOW: return "fpow"; 4966 case ISD::FTRUNC: return "ftrunc"; 4967 case ISD::FFLOOR: return "ffloor"; 4968 case ISD::FCEIL: return "fceil"; 4969 case ISD::FRINT: return "frint"; 4970 case ISD::FNEARBYINT: return "fnearbyint"; 4971 4972 // Binary operators 4973 case ISD::ADD: return "add"; 4974 case ISD::SUB: return "sub"; 4975 case ISD::MUL: return "mul"; 4976 case ISD::MULHU: return "mulhu"; 4977 case ISD::MULHS: return "mulhs"; 4978 case ISD::SDIV: return "sdiv"; 4979 case ISD::UDIV: return "udiv"; 4980 case ISD::SREM: return "srem"; 4981 case ISD::UREM: return "urem"; 4982 case ISD::SMUL_LOHI: return "smul_lohi"; 4983 case ISD::UMUL_LOHI: return "umul_lohi"; 4984 case ISD::SDIVREM: return "sdivrem"; 4985 case ISD::UDIVREM: return "udivrem"; 4986 case ISD::AND: return "and"; 4987 case ISD::OR: return "or"; 4988 case ISD::XOR: return "xor"; 4989 case ISD::SHL: return "shl"; 4990 case ISD::SRA: return "sra"; 4991 case ISD::SRL: return "srl"; 4992 case ISD::ROTL: return "rotl"; 4993 case ISD::ROTR: return "rotr"; 4994 case ISD::FADD: return "fadd"; 4995 case ISD::FSUB: return "fsub"; 4996 case ISD::FMUL: return "fmul"; 4997 case ISD::FDIV: return "fdiv"; 4998 case ISD::FREM: return "frem"; 4999 case ISD::FCOPYSIGN: return "fcopysign"; 5000 case ISD::FGETSIGN: return "fgetsign"; 5001 5002 case ISD::SETCC: return "setcc"; 5003 case ISD::VSETCC: return "vsetcc"; 5004 case ISD::SELECT: return "select"; 5005 case ISD::SELECT_CC: return "select_cc"; 5006 case ISD::INSERT_VECTOR_ELT: return "insert_vector_elt"; 5007 case ISD::EXTRACT_VECTOR_ELT: return "extract_vector_elt"; 5008 case ISD::CONCAT_VECTORS: return "concat_vectors"; 5009 case ISD::EXTRACT_SUBVECTOR: return "extract_subvector"; 5010 case ISD::SCALAR_TO_VECTOR: return "scalar_to_vector"; 5011 case ISD::VECTOR_SHUFFLE: return "vector_shuffle"; 5012 case ISD::CARRY_FALSE: return "carry_false"; 5013 case ISD::ADDC: return "addc"; 5014 case ISD::ADDE: return "adde"; 5015 case ISD::SUBC: return "subc"; 5016 case ISD::SUBE: return "sube"; 5017 case ISD::SHL_PARTS: return "shl_parts"; 5018 case ISD::SRA_PARTS: return "sra_parts"; 5019 case ISD::SRL_PARTS: return "srl_parts"; 5020 5021 case ISD::EXTRACT_SUBREG: return "extract_subreg"; 5022 case ISD::INSERT_SUBREG: return "insert_subreg"; 5023 5024 // Conversion operators. 5025 case ISD::SIGN_EXTEND: return "sign_extend"; 5026 case ISD::ZERO_EXTEND: return "zero_extend"; 5027 case ISD::ANY_EXTEND: return "any_extend"; 5028 case ISD::SIGN_EXTEND_INREG: return "sign_extend_inreg"; 5029 case ISD::TRUNCATE: return "truncate"; 5030 case ISD::FP_ROUND: return "fp_round"; 5031 case ISD::FLT_ROUNDS_: return "flt_rounds"; 5032 case ISD::FP_ROUND_INREG: return "fp_round_inreg"; 5033 case ISD::FP_EXTEND: return "fp_extend"; 5034 5035 case ISD::SINT_TO_FP: return "sint_to_fp"; 5036 case ISD::UINT_TO_FP: return "uint_to_fp"; 5037 case ISD::FP_TO_SINT: return "fp_to_sint"; 5038 case ISD::FP_TO_UINT: return "fp_to_uint"; 5039 case ISD::BIT_CONVERT: return "bit_convert"; 5040 5041 // Control flow instructions 5042 case ISD::BR: return "br"; 5043 case ISD::BRIND: return "brind"; 5044 case ISD::BR_JT: return "br_jt"; 5045 case ISD::BRCOND: return "brcond"; 5046 case ISD::BR_CC: return "br_cc"; 5047 case ISD::RET: return "ret"; 5048 case ISD::CALLSEQ_START: return "callseq_start"; 5049 case ISD::CALLSEQ_END: return "callseq_end"; 5050 5051 // Other operators 5052 case ISD::LOAD: return "load"; 5053 case ISD::STORE: return "store"; 5054 case ISD::VAARG: return "vaarg"; 5055 case ISD::VACOPY: return "vacopy"; 5056 case ISD::VAEND: return "vaend"; 5057 case ISD::VASTART: return "vastart"; 5058 case ISD::DYNAMIC_STACKALLOC: return "dynamic_stackalloc"; 5059 case ISD::EXTRACT_ELEMENT: return "extract_element"; 5060 case ISD::BUILD_PAIR: return "build_pair"; 5061 case ISD::STACKSAVE: return "stacksave"; 5062 case ISD::STACKRESTORE: return "stackrestore"; 5063 case ISD::TRAP: return "trap"; 5064 5065 // Bit manipulation 5066 case ISD::BSWAP: return "bswap"; 5067 case ISD::CTPOP: return "ctpop"; 5068 case ISD::CTTZ: return "cttz"; 5069 case ISD::CTLZ: return "ctlz"; 5070 5071 // Debug info 5072 case ISD::DBG_STOPPOINT: return "dbg_stoppoint"; 5073 case ISD::DEBUG_LOC: return "debug_loc"; 5074 5075 // Trampolines 5076 case ISD::TRAMPOLINE: return "trampoline"; 5077 5078 case ISD::CONDCODE: 5079 switch (cast<CondCodeSDNode>(this)->get()) { 5080 default: assert(0 && "Unknown setcc condition!"); 5081 case ISD::SETOEQ: return "setoeq"; 5082 case ISD::SETOGT: return "setogt"; 5083 case ISD::SETOGE: return "setoge"; 5084 case ISD::SETOLT: return "setolt"; 5085 case ISD::SETOLE: return "setole"; 5086 case ISD::SETONE: return "setone"; 5087 5088 case ISD::SETO: return "seto"; 5089 case ISD::SETUO: return "setuo"; 5090 case ISD::SETUEQ: return "setue"; 5091 case ISD::SETUGT: return "setugt"; 5092 case ISD::SETUGE: return "setuge"; 5093 case ISD::SETULT: return "setult"; 5094 case ISD::SETULE: return "setule"; 5095 case ISD::SETUNE: return "setune"; 5096 5097 case ISD::SETEQ: return "seteq"; 5098 case ISD::SETGT: return "setgt"; 5099 case ISD::SETGE: return "setge"; 5100 case ISD::SETLT: return "setlt"; 5101 case ISD::SETLE: return "setle"; 5102 case ISD::SETNE: return "setne"; 5103 } 5104 } 5105} 5106 5107const char *SDNode::getIndexedModeName(ISD::MemIndexedMode AM) { 5108 switch (AM) { 5109 default: 5110 return ""; 5111 case ISD::PRE_INC: 5112 return "<pre-inc>"; 5113 case ISD::PRE_DEC: 5114 return "<pre-dec>"; 5115 case ISD::POST_INC: 5116 return "<post-inc>"; 5117 case ISD::POST_DEC: 5118 return "<post-dec>"; 5119 } 5120} 5121 5122std::string ISD::ArgFlagsTy::getArgFlagsString() { 5123 std::string S = "< "; 5124 5125 if (isZExt()) 5126 S += "zext "; 5127 if (isSExt()) 5128 S += "sext "; 5129 if (isInReg()) 5130 S += "inreg "; 5131 if (isSRet()) 5132 S += "sret "; 5133 if (isByVal()) 5134 S += "byval "; 5135 if (isNest()) 5136 S += "nest "; 5137 if (getByValAlign()) 5138 S += "byval-align:" + utostr(getByValAlign()) + " "; 5139 if (getOrigAlign()) 5140 S += "orig-align:" + utostr(getOrigAlign()) + " "; 5141 if (getByValSize()) 5142 S += "byval-size:" + utostr(getByValSize()) + " "; 5143 return S + ">"; 5144} 5145 5146void SDNode::dump() const { dump(0); } 5147void SDNode::dump(const SelectionDAG *G) const { 5148 print(errs(), G); 5149 errs().flush(); 5150} 5151 5152void SDNode::print(raw_ostream &OS, const SelectionDAG *G) const { 5153 OS << (void*)this << ": "; 5154 5155 for (unsigned i = 0, e = getNumValues(); i != e; ++i) { 5156 if (i) OS << ","; 5157 if (getValueType(i) == MVT::Other) 5158 OS << "ch"; 5159 else 5160 OS << getValueType(i).getMVTString(); 5161 } 5162 OS << " = " << getOperationName(G); 5163 5164 OS << " "; 5165 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 5166 if (i) OS << ", "; 5167 OS << (void*)getOperand(i).getNode(); 5168 if (unsigned RN = getOperand(i).getResNo()) 5169 OS << ":" << RN; 5170 } 5171 5172 if (!isTargetOpcode() && getOpcode() == ISD::VECTOR_SHUFFLE) { 5173 SDNode *Mask = getOperand(2).getNode(); 5174 OS << "<"; 5175 for (unsigned i = 0, e = Mask->getNumOperands(); i != e; ++i) { 5176 if (i) OS << ","; 5177 if (Mask->getOperand(i).getOpcode() == ISD::UNDEF) 5178 OS << "u"; 5179 else 5180 OS << cast<ConstantSDNode>(Mask->getOperand(i))->getZExtValue(); 5181 } 5182 OS << ">"; 5183 } 5184 5185 if (const ConstantSDNode *CSDN = dyn_cast<ConstantSDNode>(this)) { 5186 OS << '<' << CSDN->getAPIntValue() << '>'; 5187 } else if (const ConstantFPSDNode *CSDN = dyn_cast<ConstantFPSDNode>(this)) { 5188 if (&CSDN->getValueAPF().getSemantics()==&APFloat::IEEEsingle) 5189 OS << '<' << CSDN->getValueAPF().convertToFloat() << '>'; 5190 else if (&CSDN->getValueAPF().getSemantics()==&APFloat::IEEEdouble) 5191 OS << '<' << CSDN->getValueAPF().convertToDouble() << '>'; 5192 else { 5193 OS << "<APFloat("; 5194 CSDN->getValueAPF().convertToAPInt().dump(); 5195 OS << ")>"; 5196 } 5197 } else if (const GlobalAddressSDNode *GADN = 5198 dyn_cast<GlobalAddressSDNode>(this)) { 5199 int offset = GADN->getOffset(); 5200 OS << '<'; 5201 WriteAsOperand(OS, GADN->getGlobal()); 5202 OS << '>'; 5203 if (offset > 0) 5204 OS << " + " << offset; 5205 else 5206 OS << " " << offset; 5207 } else if (const FrameIndexSDNode *FIDN = dyn_cast<FrameIndexSDNode>(this)) { 5208 OS << "<" << FIDN->getIndex() << ">"; 5209 } else if (const JumpTableSDNode *JTDN = dyn_cast<JumpTableSDNode>(this)) { 5210 OS << "<" << JTDN->getIndex() << ">"; 5211 } else if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(this)){ 5212 int offset = CP->getOffset(); 5213 if (CP->isMachineConstantPoolEntry()) 5214 OS << "<" << *CP->getMachineCPVal() << ">"; 5215 else 5216 OS << "<" << *CP->getConstVal() << ">"; 5217 if (offset > 0) 5218 OS << " + " << offset; 5219 else 5220 OS << " " << offset; 5221 } else if (const BasicBlockSDNode *BBDN = dyn_cast<BasicBlockSDNode>(this)) { 5222 OS << "<"; 5223 const Value *LBB = (const Value*)BBDN->getBasicBlock()->getBasicBlock(); 5224 if (LBB) 5225 OS << LBB->getName() << " "; 5226 OS << (const void*)BBDN->getBasicBlock() << ">"; 5227 } else if (const RegisterSDNode *R = dyn_cast<RegisterSDNode>(this)) { 5228 if (G && R->getReg() && 5229 TargetRegisterInfo::isPhysicalRegister(R->getReg())) { 5230 OS << " " << G->getTarget().getRegisterInfo()->getName(R->getReg()); 5231 } else { 5232 OS << " #" << R->getReg(); 5233 } 5234 } else if (const SymbolSDNode *S = 5235 dyn_cast<SymbolSDNode>(this)) { 5236 OS << "'" << S->getSymbol() << "' "; 5237 5238 switch (S->getLinkage()) { 5239 default: assert(0 && "Invalid linkage type!"); break; 5240 case GlobalValue::ExternalLinkage: OS << "[external]"; break; 5241 case GlobalValue::LinkOnceLinkage: OS << "[once]"; break; 5242 case GlobalValue::WeakLinkage: OS << "[weak]"; break; 5243 case GlobalValue::AppendingLinkage: OS << "[appending]"; break; 5244 case GlobalValue::InternalLinkage: OS << "[internal]"; break; 5245 case GlobalValue::DLLImportLinkage: OS << "[dllimport]"; break; 5246 case GlobalValue::DLLExportLinkage: OS << "[dllexport]"; break; 5247 case GlobalValue::ExternalWeakLinkage: OS << "[externweak]"; break; 5248 case GlobalValue::GhostLinkage: OS << "[ghost]"; break; 5249 case GlobalValue::CommonLinkage: OS << "[common]"; break; 5250 } 5251 } else if (const SrcValueSDNode *M = dyn_cast<SrcValueSDNode>(this)) { 5252 if (M->getValue()) 5253 OS << "<" << M->getValue() << ">"; 5254 else 5255 OS << "<null>"; 5256 } else if (const MemOperandSDNode *M = dyn_cast<MemOperandSDNode>(this)) { 5257 if (M->MO.getValue()) 5258 OS << "<" << M->MO.getValue() << ":" << M->MO.getOffset() << ">"; 5259 else 5260 OS << "<null:" << M->MO.getOffset() << ">"; 5261 } else if (const ARG_FLAGSSDNode *N = dyn_cast<ARG_FLAGSSDNode>(this)) { 5262 OS << N->getArgFlags().getArgFlagsString(); 5263 } else if (const VTSDNode *N = dyn_cast<VTSDNode>(this)) { 5264 OS << ":" << N->getVT().getMVTString(); 5265 } 5266 else if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(this)) { 5267 const Value *SrcValue = LD->getSrcValue(); 5268 int SrcOffset = LD->getSrcValueOffset(); 5269 OS << " <"; 5270 if (SrcValue) 5271 OS << SrcValue; 5272 else 5273 OS << "null"; 5274 OS << ":" << SrcOffset << ">"; 5275 5276 bool doExt = true; 5277 switch (LD->getExtensionType()) { 5278 default: doExt = false; break; 5279 case ISD::EXTLOAD: OS << " <anyext "; break; 5280 case ISD::SEXTLOAD: OS << " <sext "; break; 5281 case ISD::ZEXTLOAD: OS << " <zext "; break; 5282 } 5283 if (doExt) 5284 OS << LD->getMemoryVT().getMVTString() << ">"; 5285 5286 const char *AM = getIndexedModeName(LD->getAddressingMode()); 5287 if (*AM) 5288 OS << " " << AM; 5289 if (LD->isVolatile()) 5290 OS << " <volatile>"; 5291 OS << " alignment=" << LD->getAlignment(); 5292 } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(this)) { 5293 const Value *SrcValue = ST->getSrcValue(); 5294 int SrcOffset = ST->getSrcValueOffset(); 5295 OS << " <"; 5296 if (SrcValue) 5297 OS << SrcValue; 5298 else 5299 OS << "null"; 5300 OS << ":" << SrcOffset << ">"; 5301 5302 if (ST->isTruncatingStore()) 5303 OS << " <trunc " << ST->getMemoryVT().getMVTString() << ">"; 5304 5305 const char *AM = getIndexedModeName(ST->getAddressingMode()); 5306 if (*AM) 5307 OS << " " << AM; 5308 if (ST->isVolatile()) 5309 OS << " <volatile>"; 5310 OS << " alignment=" << ST->getAlignment(); 5311 } else if (const AtomicSDNode* AT = dyn_cast<AtomicSDNode>(this)) { 5312 const Value *SrcValue = AT->getSrcValue(); 5313 int SrcOffset = AT->getSrcValueOffset(); 5314 OS << " <"; 5315 if (SrcValue) 5316 OS << SrcValue; 5317 else 5318 OS << "null"; 5319 OS << ":" << SrcOffset << ">"; 5320 if (AT->isVolatile()) 5321 OS << " <volatile>"; 5322 OS << " alignment=" << AT->getAlignment(); 5323 } 5324} 5325 5326static void DumpNodes(const SDNode *N, unsigned indent, const SelectionDAG *G) { 5327 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 5328 if (N->getOperand(i).getNode()->hasOneUse()) 5329 DumpNodes(N->getOperand(i).getNode(), indent+2, G); 5330 else 5331 cerr << "\n" << std::string(indent+2, ' ') 5332 << (void*)N->getOperand(i).getNode() << ": <multiple use>"; 5333 5334 5335 cerr << "\n" << std::string(indent, ' '); 5336 N->dump(G); 5337} 5338 5339void SelectionDAG::dump() const { 5340 cerr << "SelectionDAG has " << AllNodes.size() << " nodes:"; 5341 5342 for (allnodes_const_iterator I = allnodes_begin(), E = allnodes_end(); 5343 I != E; ++I) { 5344 const SDNode *N = I; 5345 if (!N->hasOneUse() && N != getRoot().getNode()) 5346 DumpNodes(N, 2, this); 5347 } 5348 5349 if (getRoot().getNode()) DumpNodes(getRoot().getNode(), 2, this); 5350 5351 cerr << "\n\n"; 5352} 5353 5354const Type *ConstantPoolSDNode::getType() const { 5355 if (isMachineConstantPoolEntry()) 5356 return Val.MachineCPVal->getType(); 5357 return Val.ConstVal->getType(); 5358} 5359