SelectionDAG.cpp revision 9a9719eea1d134809c582754188cc10df1021717
10c355f691e91ff0d6dfd3765bf72b04cce8a1cebChiao Cheng//===-- SelectionDAG.cpp - Implement the SelectionDAG data structures -----===// 20c355f691e91ff0d6dfd3765bf72b04cce8a1cebChiao Cheng// 30c355f691e91ff0d6dfd3765bf72b04cce8a1cebChiao Cheng// The LLVM Compiler Infrastructure 40c355f691e91ff0d6dfd3765bf72b04cce8a1cebChiao Cheng// 50c355f691e91ff0d6dfd3765bf72b04cce8a1cebChiao Cheng// This file was developed by the LLVM research group and is distributed under 60c355f691e91ff0d6dfd3765bf72b04cce8a1cebChiao Cheng// the University of Illinois Open Source License. See LICENSE.TXT for details. 70c355f691e91ff0d6dfd3765bf72b04cce8a1cebChiao Cheng// 80c355f691e91ff0d6dfd3765bf72b04cce8a1cebChiao Cheng//===----------------------------------------------------------------------===// 90c355f691e91ff0d6dfd3765bf72b04cce8a1cebChiao Cheng// 100c355f691e91ff0d6dfd3765bf72b04cce8a1cebChiao Cheng// This implements the SelectionDAG class. 110c355f691e91ff0d6dfd3765bf72b04cce8a1cebChiao Cheng// 120c355f691e91ff0d6dfd3765bf72b04cce8a1cebChiao Cheng//===----------------------------------------------------------------------===// 130c355f691e91ff0d6dfd3765bf72b04cce8a1cebChiao Cheng 140c355f691e91ff0d6dfd3765bf72b04cce8a1cebChiao Cheng#include "llvm/CodeGen/SelectionDAG.h" 150c355f691e91ff0d6dfd3765bf72b04cce8a1cebChiao Cheng#include "llvm/Constants.h" 160c355f691e91ff0d6dfd3765bf72b04cce8a1cebChiao Cheng#include "llvm/GlobalValue.h" 170c355f691e91ff0d6dfd3765bf72b04cce8a1cebChiao Cheng#include "llvm/Assembly/Writer.h" 180c355f691e91ff0d6dfd3765bf72b04cce8a1cebChiao Cheng#include "llvm/CodeGen/MachineBasicBlock.h" 197dfb24822010e130fa31612e5a488cbc4e9a798dYorke Lee#include "llvm/Support/MathExtras.h" 207dfb24822010e130fa31612e5a488cbc4e9a798dYorke Lee#include "llvm/Target/MRegisterInfo.h" 21b2c826a4c935a42f458ab187b257cd0b6a47bfb4Jay Shrauner#include "llvm/Target/TargetLowering.h" 2263ac534dcf60e9a6c651ef2434557bec922b9a7dChiao Cheng#include "llvm/Target/TargetInstrInfo.h" 23d305a6e633b7315cdd1ce4711c0d3a2b18b3c05fChiao Cheng#include "llvm/Target/TargetMachine.h" 2463ac534dcf60e9a6c651ef2434557bec922b9a7dChiao Cheng#include <iostream> 25d305a6e633b7315cdd1ce4711c0d3a2b18b3c05fChiao Cheng#include <set> 260c355f691e91ff0d6dfd3765bf72b04cce8a1cebChiao Cheng#include <cmath> 270c355f691e91ff0d6dfd3765bf72b04cce8a1cebChiao Cheng#include <algorithm> 280c355f691e91ff0d6dfd3765bf72b04cce8a1cebChiao Chengusing namespace llvm; 2963ac534dcf60e9a6c651ef2434557bec922b9a7dChiao Cheng 3063ac534dcf60e9a6c651ef2434557bec922b9a7dChiao Cheng// Temporary boolean for testing the dag combiner 310c355f691e91ff0d6dfd3765bf72b04cce8a1cebChiao Chengnamespace llvm { 32d305a6e633b7315cdd1ce4711c0d3a2b18b3c05fChiao Cheng extern bool CombinerEnabled; 33d305a6e633b7315cdd1ce4711c0d3a2b18b3c05fChiao Cheng} 340c355f691e91ff0d6dfd3765bf72b04cce8a1cebChiao Cheng 350c355f691e91ff0d6dfd3765bf72b04cce8a1cebChiao Chengstatic bool isCommutativeBinOp(unsigned Opcode) { 360c355f691e91ff0d6dfd3765bf72b04cce8a1cebChiao Cheng switch (Opcode) { 370c355f691e91ff0d6dfd3765bf72b04cce8a1cebChiao Cheng case ISD::ADD: 380c355f691e91ff0d6dfd3765bf72b04cce8a1cebChiao Cheng case ISD::MUL: 39b2c826a4c935a42f458ab187b257cd0b6a47bfb4Jay Shrauner case ISD::FADD: 40b2c826a4c935a42f458ab187b257cd0b6a47bfb4Jay Shrauner case ISD::FMUL: 410c355f691e91ff0d6dfd3765bf72b04cce8a1cebChiao Cheng case ISD::AND: 420c355f691e91ff0d6dfd3765bf72b04cce8a1cebChiao Cheng case ISD::OR: 430c355f691e91ff0d6dfd3765bf72b04cce8a1cebChiao Cheng case ISD::XOR: return true; 440c355f691e91ff0d6dfd3765bf72b04cce8a1cebChiao Cheng default: return false; // FIXME: Need commutative info for user ops! 450c355f691e91ff0d6dfd3765bf72b04cce8a1cebChiao Cheng } 460c355f691e91ff0d6dfd3765bf72b04cce8a1cebChiao Cheng} 470c355f691e91ff0d6dfd3765bf72b04cce8a1cebChiao Cheng 48b2c826a4c935a42f458ab187b257cd0b6a47bfb4Jay Shraunerstatic bool isAssociativeBinOp(unsigned Opcode) { 490c355f691e91ff0d6dfd3765bf72b04cce8a1cebChiao Cheng switch (Opcode) { 500c355f691e91ff0d6dfd3765bf72b04cce8a1cebChiao Cheng case ISD::ADD: 510c355f691e91ff0d6dfd3765bf72b04cce8a1cebChiao Cheng case ISD::MUL: 520c355f691e91ff0d6dfd3765bf72b04cce8a1cebChiao Cheng case ISD::AND: 530c355f691e91ff0d6dfd3765bf72b04cce8a1cebChiao Cheng case ISD::OR: 540c355f691e91ff0d6dfd3765bf72b04cce8a1cebChiao Cheng case ISD::XOR: return true; 550c355f691e91ff0d6dfd3765bf72b04cce8a1cebChiao Cheng default: return false; // FIXME: Need associative info for user ops! 560c355f691e91ff0d6dfd3765bf72b04cce8a1cebChiao Cheng } 570c355f691e91ff0d6dfd3765bf72b04cce8a1cebChiao Cheng} 580c355f691e91ff0d6dfd3765bf72b04cce8a1cebChiao Cheng 590c355f691e91ff0d6dfd3765bf72b04cce8a1cebChiao Cheng// isInvertibleForFree - Return true if there is no cost to emitting the logical 600c355f691e91ff0d6dfd3765bf72b04cce8a1cebChiao Cheng// inverse of this node. 610c355f691e91ff0d6dfd3765bf72b04cce8a1cebChiao Chengstatic bool isInvertibleForFree(SDOperand N) { 620c355f691e91ff0d6dfd3765bf72b04cce8a1cebChiao Cheng if (isa<ConstantSDNode>(N.Val)) return true; 630c355f691e91ff0d6dfd3765bf72b04cce8a1cebChiao Cheng if (N.Val->getOpcode() == ISD::SETCC && N.Val->hasOneUse()) 640c355f691e91ff0d6dfd3765bf72b04cce8a1cebChiao Cheng return true; 650c355f691e91ff0d6dfd3765bf72b04cce8a1cebChiao Cheng return false; 660c355f691e91ff0d6dfd3765bf72b04cce8a1cebChiao Cheng} 670c355f691e91ff0d6dfd3765bf72b04cce8a1cebChiao Cheng 6845d8dd98608fe7dc65becf1b5e34e7ec8c097371Paul Soulos//===----------------------------------------------------------------------===// 69b2c826a4c935a42f458ab187b257cd0b6a47bfb4Jay Shrauner// ConstantFPSDNode Class 70b2c826a4c935a42f458ab187b257cd0b6a47bfb4Jay Shrauner//===----------------------------------------------------------------------===// 71b2c826a4c935a42f458ab187b257cd0b6a47bfb4Jay Shrauner 72b2c826a4c935a42f458ab187b257cd0b6a47bfb4Jay Shrauner/// isExactlyValue - We don't rely on operator== working on double values, as 73b2c826a4c935a42f458ab187b257cd0b6a47bfb4Jay Shrauner/// it returns true for things that are clearly not equal, like -0.0 and 0.0. 74b2c826a4c935a42f458ab187b257cd0b6a47bfb4Jay Shrauner/// As such, this method can be used to do an exact bit-for-bit comparison of 75b2c826a4c935a42f458ab187b257cd0b6a47bfb4Jay Shrauner/// two floating point values. 76b2c826a4c935a42f458ab187b257cd0b6a47bfb4Jay Shraunerbool ConstantFPSDNode::isExactlyValue(double V) const { 77b2c826a4c935a42f458ab187b257cd0b6a47bfb4Jay Shrauner return DoubleToBits(V) == DoubleToBits(Value); 78b2c826a4c935a42f458ab187b257cd0b6a47bfb4Jay Shrauner} 79b2c826a4c935a42f458ab187b257cd0b6a47bfb4Jay Shrauner 80b2c826a4c935a42f458ab187b257cd0b6a47bfb4Jay Shrauner//===----------------------------------------------------------------------===// 810c355f691e91ff0d6dfd3765bf72b04cce8a1cebChiao Cheng// ISD Class 82b2c826a4c935a42f458ab187b257cd0b6a47bfb4Jay Shrauner//===----------------------------------------------------------------------===// 83b2c826a4c935a42f458ab187b257cd0b6a47bfb4Jay Shrauner 840c355f691e91ff0d6dfd3765bf72b04cce8a1cebChiao Cheng/// getSetCCSwappedOperands - Return the operation corresponding to (Y op X) 85b2c826a4c935a42f458ab187b257cd0b6a47bfb4Jay Shrauner/// when given the operation for (X op Y). 86939837d76f33abdd3b44ce986329293d808ed41cChiao ChengISD::CondCode ISD::getSetCCSwappedOperands(ISD::CondCode Operation) { 87939837d76f33abdd3b44ce986329293d808ed41cChiao Cheng // To perform this operation, we just need to swap the L and G bits of the 88b2c826a4c935a42f458ab187b257cd0b6a47bfb4Jay Shrauner // operation. 89b2c826a4c935a42f458ab187b257cd0b6a47bfb4Jay Shrauner unsigned OldL = (Operation >> 2) & 1; 90b2c826a4c935a42f458ab187b257cd0b6a47bfb4Jay Shrauner unsigned OldG = (Operation >> 1) & 1; 91b2c826a4c935a42f458ab187b257cd0b6a47bfb4Jay Shrauner return ISD::CondCode((Operation & ~6) | // Keep the N, U, E bits 92b2c826a4c935a42f458ab187b257cd0b6a47bfb4Jay Shrauner (OldL << 1) | // New G bit 93b2c826a4c935a42f458ab187b257cd0b6a47bfb4Jay Shrauner (OldG << 2)); // New L bit. 94b2c826a4c935a42f458ab187b257cd0b6a47bfb4Jay Shrauner} 95b2c826a4c935a42f458ab187b257cd0b6a47bfb4Jay Shrauner 96b2c826a4c935a42f458ab187b257cd0b6a47bfb4Jay Shrauner/// getSetCCInverse - Return the operation corresponding to !(X op Y), where 97b2c826a4c935a42f458ab187b257cd0b6a47bfb4Jay Shrauner/// 'op' is a valid SetCC operation. 98b2c826a4c935a42f458ab187b257cd0b6a47bfb4Jay ShraunerISD::CondCode ISD::getSetCCInverse(ISD::CondCode Op, bool isInteger) { 99b2c826a4c935a42f458ab187b257cd0b6a47bfb4Jay Shrauner unsigned Operation = Op; 100939837d76f33abdd3b44ce986329293d808ed41cChiao Cheng if (isInteger) 101939837d76f33abdd3b44ce986329293d808ed41cChiao Cheng Operation ^= 7; // Flip L, G, E bits, but not U. 102939837d76f33abdd3b44ce986329293d808ed41cChiao Cheng else 103939837d76f33abdd3b44ce986329293d808ed41cChiao Cheng Operation ^= 15; // Flip all of the condition bits. 104939837d76f33abdd3b44ce986329293d808ed41cChiao Cheng if (Operation > ISD::SETTRUE2) 105939837d76f33abdd3b44ce986329293d808ed41cChiao Cheng Operation &= ~8; // Don't let N and U bits get set. 106939837d76f33abdd3b44ce986329293d808ed41cChiao Cheng return ISD::CondCode(Operation); 107939837d76f33abdd3b44ce986329293d808ed41cChiao Cheng} 108939837d76f33abdd3b44ce986329293d808ed41cChiao Cheng 109939837d76f33abdd3b44ce986329293d808ed41cChiao Cheng 110939837d76f33abdd3b44ce986329293d808ed41cChiao Cheng/// isSignedOp - For an integer comparison, return 1 if the comparison is a 111939837d76f33abdd3b44ce986329293d808ed41cChiao Cheng/// signed operation and 2 if the result is an unsigned comparison. Return zero 112939837d76f33abdd3b44ce986329293d808ed41cChiao Cheng/// if the operation does not depend on the sign of the input (setne and seteq). 113939837d76f33abdd3b44ce986329293d808ed41cChiao Chengstatic int isSignedOp(ISD::CondCode Opcode) { 114939837d76f33abdd3b44ce986329293d808ed41cChiao Cheng switch (Opcode) { 115939837d76f33abdd3b44ce986329293d808ed41cChiao Cheng default: assert(0 && "Illegal integer setcc operation!"); 116939837d76f33abdd3b44ce986329293d808ed41cChiao Cheng case ISD::SETEQ: 117939837d76f33abdd3b44ce986329293d808ed41cChiao Cheng case ISD::SETNE: return 0; 118939837d76f33abdd3b44ce986329293d808ed41cChiao Cheng case ISD::SETLT: 119939837d76f33abdd3b44ce986329293d808ed41cChiao Cheng case ISD::SETLE: 120939837d76f33abdd3b44ce986329293d808ed41cChiao Cheng case ISD::SETGT: 121939837d76f33abdd3b44ce986329293d808ed41cChiao Cheng case ISD::SETGE: return 1; 122939837d76f33abdd3b44ce986329293d808ed41cChiao Cheng case ISD::SETULT: 123939837d76f33abdd3b44ce986329293d808ed41cChiao Cheng case ISD::SETULE: 124939837d76f33abdd3b44ce986329293d808ed41cChiao Cheng case ISD::SETUGT: 125939837d76f33abdd3b44ce986329293d808ed41cChiao Cheng case ISD::SETUGE: return 2; 126939837d76f33abdd3b44ce986329293d808ed41cChiao Cheng } 127939837d76f33abdd3b44ce986329293d808ed41cChiao Cheng} 128939837d76f33abdd3b44ce986329293d808ed41cChiao Cheng 129939837d76f33abdd3b44ce986329293d808ed41cChiao Cheng/// getSetCCOrOperation - Return the result of a logical OR between different 130939837d76f33abdd3b44ce986329293d808ed41cChiao Cheng/// comparisons of identical values: ((X op1 Y) | (X op2 Y)). This function 131939837d76f33abdd3b44ce986329293d808ed41cChiao Cheng/// returns SETCC_INVALID if it is not possible to represent the resultant 132939837d76f33abdd3b44ce986329293d808ed41cChiao Cheng/// comparison. 133939837d76f33abdd3b44ce986329293d808ed41cChiao ChengISD::CondCode ISD::getSetCCOrOperation(ISD::CondCode Op1, ISD::CondCode Op2, 134939837d76f33abdd3b44ce986329293d808ed41cChiao Cheng bool isInteger) { 135939837d76f33abdd3b44ce986329293d808ed41cChiao Cheng if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 136939837d76f33abdd3b44ce986329293d808ed41cChiao Cheng // Cannot fold a signed integer setcc with an unsigned integer setcc. 137b2c826a4c935a42f458ab187b257cd0b6a47bfb4Jay Shrauner return ISD::SETCC_INVALID; 138b2c826a4c935a42f458ab187b257cd0b6a47bfb4Jay Shrauner 139b2c826a4c935a42f458ab187b257cd0b6a47bfb4Jay Shrauner unsigned Op = Op1 | Op2; // Combine all of the condition bits. 140939837d76f33abdd3b44ce986329293d808ed41cChiao Cheng 141939837d76f33abdd3b44ce986329293d808ed41cChiao Cheng // If the N and U bits get set then the resultant comparison DOES suddenly 142939837d76f33abdd3b44ce986329293d808ed41cChiao Cheng // care about orderedness, and is true when ordered. 143939837d76f33abdd3b44ce986329293d808ed41cChiao Cheng if (Op > ISD::SETTRUE2) 144939837d76f33abdd3b44ce986329293d808ed41cChiao Cheng Op &= ~16; // Clear the N bit. 145939837d76f33abdd3b44ce986329293d808ed41cChiao Cheng return ISD::CondCode(Op); 146939837d76f33abdd3b44ce986329293d808ed41cChiao Cheng} 147939837d76f33abdd3b44ce986329293d808ed41cChiao Cheng 148939837d76f33abdd3b44ce986329293d808ed41cChiao Cheng/// getSetCCAndOperation - Return the result of a logical AND between different 149939837d76f33abdd3b44ce986329293d808ed41cChiao Cheng/// comparisons of identical values: ((X op1 Y) & (X op2 Y)). This 150939837d76f33abdd3b44ce986329293d808ed41cChiao Cheng/// function returns zero if it is not possible to represent the resultant 151939837d76f33abdd3b44ce986329293d808ed41cChiao Cheng/// comparison. 152939837d76f33abdd3b44ce986329293d808ed41cChiao ChengISD::CondCode ISD::getSetCCAndOperation(ISD::CondCode Op1, ISD::CondCode Op2, 153939837d76f33abdd3b44ce986329293d808ed41cChiao Cheng bool isInteger) { 154939837d76f33abdd3b44ce986329293d808ed41cChiao Cheng if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 155b2c826a4c935a42f458ab187b257cd0b6a47bfb4Jay Shrauner // Cannot fold a signed setcc with an unsigned setcc. 156b2c826a4c935a42f458ab187b257cd0b6a47bfb4Jay Shrauner return ISD::SETCC_INVALID; 157b2c826a4c935a42f458ab187b257cd0b6a47bfb4Jay Shrauner 158b2c826a4c935a42f458ab187b257cd0b6a47bfb4Jay Shrauner // Combine all of the condition bits. 159b2c826a4c935a42f458ab187b257cd0b6a47bfb4Jay Shrauner return ISD::CondCode(Op1 & Op2); 160b2c826a4c935a42f458ab187b257cd0b6a47bfb4Jay Shrauner} 161b2c826a4c935a42f458ab187b257cd0b6a47bfb4Jay Shrauner 162b2c826a4c935a42f458ab187b257cd0b6a47bfb4Jay Shraunerconst TargetMachine &SelectionDAG::getTarget() const { 1630c355f691e91ff0d6dfd3765bf72b04cce8a1cebChiao Cheng return TLI.getTargetMachine(); 164b2c826a4c935a42f458ab187b257cd0b6a47bfb4Jay Shrauner} 1650c355f691e91ff0d6dfd3765bf72b04cce8a1cebChiao Cheng 16663ac534dcf60e9a6c651ef2434557bec922b9a7dChiao Cheng//===----------------------------------------------------------------------===// 16763ac534dcf60e9a6c651ef2434557bec922b9a7dChiao Cheng// SelectionDAG Class 16863ac534dcf60e9a6c651ef2434557bec922b9a7dChiao Cheng//===----------------------------------------------------------------------===// 16963ac534dcf60e9a6c651ef2434557bec922b9a7dChiao Cheng 17063ac534dcf60e9a6c651ef2434557bec922b9a7dChiao Cheng/// RemoveDeadNodes - This method deletes all unreachable nodes in the 17163ac534dcf60e9a6c651ef2434557bec922b9a7dChiao Cheng/// SelectionDAG, including nodes (like loads) that have uses of their token 17263ac534dcf60e9a6c651ef2434557bec922b9a7dChiao Cheng/// chain but no other uses and no side effect. If a node is passed in as an 173039b4d46787bd06f2faeaac8c332459c86f3cffeYorke Lee/// argument, it is used as the seed for node deletion. 17463ac534dcf60e9a6c651ef2434557bec922b9a7dChiao Chengvoid SelectionDAG::RemoveDeadNodes(SDNode *N) { 17563ac534dcf60e9a6c651ef2434557bec922b9a7dChiao Cheng std::set<SDNode*> AllNodeSet(AllNodes.begin(), AllNodes.end()); 17663ac534dcf60e9a6c651ef2434557bec922b9a7dChiao Cheng 17763ac534dcf60e9a6c651ef2434557bec922b9a7dChiao Cheng // Create a dummy node (which is not added to allnodes), that adds a reference 178039b4d46787bd06f2faeaac8c332459c86f3cffeYorke Lee // to the root node, preventing it from being deleted. 179039b4d46787bd06f2faeaac8c332459c86f3cffeYorke Lee HandleSDNode Dummy(getRoot()); 180039b4d46787bd06f2faeaac8c332459c86f3cffeYorke Lee 181039b4d46787bd06f2faeaac8c332459c86f3cffeYorke Lee // If we have a hint to start from, use it. 18263ac534dcf60e9a6c651ef2434557bec922b9a7dChiao Cheng if (N) DeleteNodeIfDead(N, &AllNodeSet); 18363ac534dcf60e9a6c651ef2434557bec922b9a7dChiao Cheng 18463ac534dcf60e9a6c651ef2434557bec922b9a7dChiao Cheng Restart: 18563ac534dcf60e9a6c651ef2434557bec922b9a7dChiao Cheng unsigned NumNodes = AllNodeSet.size(); 18663ac534dcf60e9a6c651ef2434557bec922b9a7dChiao Cheng for (std::set<SDNode*>::iterator I = AllNodeSet.begin(), E = AllNodeSet.end(); 18763ac534dcf60e9a6c651ef2434557bec922b9a7dChiao Cheng I != E; ++I) { 18863ac534dcf60e9a6c651ef2434557bec922b9a7dChiao Cheng // Try to delete this node. 1893c4e8501b8fe4a6f508a256fd133004e1f1936a4Brian Attwell DeleteNodeIfDead(*I, &AllNodeSet); 1903c4e8501b8fe4a6f508a256fd133004e1f1936a4Brian Attwell 19163ac534dcf60e9a6c651ef2434557bec922b9a7dChiao Cheng // If we actually deleted any nodes, do not use invalid iterators in 1923c4e8501b8fe4a6f508a256fd133004e1f1936a4Brian Attwell // AllNodeSet. 19363ac534dcf60e9a6c651ef2434557bec922b9a7dChiao Cheng if (AllNodeSet.size() != NumNodes) 194d305a6e633b7315cdd1ce4711c0d3a2b18b3c05fChiao Cheng goto Restart; 195d305a6e633b7315cdd1ce4711c0d3a2b18b3c05fChiao Cheng } 1963c4e8501b8fe4a6f508a256fd133004e1f1936a4Brian Attwell 1973c4e8501b8fe4a6f508a256fd133004e1f1936a4Brian Attwell // Restore AllNodes. 1983c4e8501b8fe4a6f508a256fd133004e1f1936a4Brian Attwell if (AllNodes.size() != NumNodes) 1993c4e8501b8fe4a6f508a256fd133004e1f1936a4Brian Attwell AllNodes.assign(AllNodeSet.begin(), AllNodeSet.end()); 2003c4e8501b8fe4a6f508a256fd133004e1f1936a4Brian Attwell 2013c4e8501b8fe4a6f508a256fd133004e1f1936a4Brian Attwell // If the root changed (e.g. it was a dead load, update the root). 2023c4e8501b8fe4a6f508a256fd133004e1f1936a4Brian Attwell setRoot(Dummy.getValue()); 2033c4e8501b8fe4a6f508a256fd133004e1f1936a4Brian Attwell} 2043c4e8501b8fe4a6f508a256fd133004e1f1936a4Brian Attwell 2053c4e8501b8fe4a6f508a256fd133004e1f1936a4Brian Attwell 2063c4e8501b8fe4a6f508a256fd133004e1f1936a4Brian Attwellvoid SelectionDAG::DeleteNodeIfDead(SDNode *N, void *NodeSet) { 2073c4e8501b8fe4a6f508a256fd133004e1f1936a4Brian Attwell if (!N->use_empty()) 2083c4e8501b8fe4a6f508a256fd133004e1f1936a4Brian Attwell return; 2093c4e8501b8fe4a6f508a256fd133004e1f1936a4Brian Attwell 2103c4e8501b8fe4a6f508a256fd133004e1f1936a4Brian Attwell // Okay, we really are going to delete this node. First take this out of the 2113c4e8501b8fe4a6f508a256fd133004e1f1936a4Brian Attwell // appropriate CSE map. 2123c4e8501b8fe4a6f508a256fd133004e1f1936a4Brian Attwell RemoveNodeFromCSEMaps(N); 2133c4e8501b8fe4a6f508a256fd133004e1f1936a4Brian Attwell 2143c4e8501b8fe4a6f508a256fd133004e1f1936a4Brian Attwell // Next, brutally remove the operand list. This is safe to do, as there are 215d305a6e633b7315cdd1ce4711c0d3a2b18b3c05fChiao Cheng // no cycles in the graph. 216d305a6e633b7315cdd1ce4711c0d3a2b18b3c05fChiao Cheng while (!N->Operands.empty()) { 217d305a6e633b7315cdd1ce4711c0d3a2b18b3c05fChiao Cheng SDNode *O = N->Operands.back().Val; 218d305a6e633b7315cdd1ce4711c0d3a2b18b3c05fChiao Cheng N->Operands.pop_back(); 219d305a6e633b7315cdd1ce4711c0d3a2b18b3c05fChiao Cheng O->removeUser(N); 220d305a6e633b7315cdd1ce4711c0d3a2b18b3c05fChiao Cheng 221d305a6e633b7315cdd1ce4711c0d3a2b18b3c05fChiao Cheng // Now that we removed this operand, see if there are no uses of it left. 222d305a6e633b7315cdd1ce4711c0d3a2b18b3c05fChiao Cheng DeleteNodeIfDead(O, NodeSet); 223d305a6e633b7315cdd1ce4711c0d3a2b18b3c05fChiao Cheng } 224d305a6e633b7315cdd1ce4711c0d3a2b18b3c05fChiao Cheng 225d305a6e633b7315cdd1ce4711c0d3a2b18b3c05fChiao Cheng // Remove the node from the nodes set and delete it. 226d305a6e633b7315cdd1ce4711c0d3a2b18b3c05fChiao Cheng std::set<SDNode*> &AllNodeSet = *(std::set<SDNode*>*)NodeSet; 227d305a6e633b7315cdd1ce4711c0d3a2b18b3c05fChiao Cheng AllNodeSet.erase(N); 228d305a6e633b7315cdd1ce4711c0d3a2b18b3c05fChiao Cheng 229d305a6e633b7315cdd1ce4711c0d3a2b18b3c05fChiao Cheng // Now that the node is gone, check to see if any of the operands of this node 230d305a6e633b7315cdd1ce4711c0d3a2b18b3c05fChiao Cheng // are dead now. 231d305a6e633b7315cdd1ce4711c0d3a2b18b3c05fChiao Cheng delete N; 232d305a6e633b7315cdd1ce4711c0d3a2b18b3c05fChiao Cheng} 233d305a6e633b7315cdd1ce4711c0d3a2b18b3c05fChiao Cheng 234d305a6e633b7315cdd1ce4711c0d3a2b18b3c05fChiao Chengvoid SelectionDAG::DeleteNode(SDNode *N) { 2350c355f691e91ff0d6dfd3765bf72b04cce8a1cebChiao Cheng assert(N->use_empty() && "Cannot delete a node that is not dead!"); 236 237 // First take this out of the appropriate CSE map. 238 RemoveNodeFromCSEMaps(N); 239 240 // Finally, remove uses due to operands of this node, remove from the 241 // AllNodes list, and delete the node. 242 DeleteNodeNotInCSEMaps(N); 243} 244 245void SelectionDAG::DeleteNodeNotInCSEMaps(SDNode *N) { 246 247 // Remove it from the AllNodes list. 248 for (std::vector<SDNode*>::iterator I = AllNodes.begin(); ; ++I) { 249 assert(I != AllNodes.end() && "Node not in AllNodes list??"); 250 if (*I == N) { 251 // Erase from the vector, which is not ordered. 252 std::swap(*I, AllNodes.back()); 253 AllNodes.pop_back(); 254 break; 255 } 256 } 257 258 // Drop all of the operands and decrement used nodes use counts. 259 while (!N->Operands.empty()) { 260 SDNode *O = N->Operands.back().Val; 261 N->Operands.pop_back(); 262 O->removeUser(N); 263 } 264 265 delete N; 266} 267 268/// RemoveNodeFromCSEMaps - Take the specified node out of the CSE map that 269/// correspond to it. This is useful when we're about to delete or repurpose 270/// the node. We don't want future request for structurally identical nodes 271/// to return N anymore. 272void SelectionDAG::RemoveNodeFromCSEMaps(SDNode *N) { 273 bool Erased = false; 274 switch (N->getOpcode()) { 275 case ISD::HANDLENODE: return; // noop. 276 case ISD::Constant: 277 Erased = Constants.erase(std::make_pair(cast<ConstantSDNode>(N)->getValue(), 278 N->getValueType(0))); 279 break; 280 case ISD::TargetConstant: 281 Erased = TargetConstants.erase(std::make_pair( 282 cast<ConstantSDNode>(N)->getValue(), 283 N->getValueType(0))); 284 break; 285 case ISD::ConstantFP: { 286 uint64_t V = DoubleToBits(cast<ConstantFPSDNode>(N)->getValue()); 287 Erased = ConstantFPs.erase(std::make_pair(V, N->getValueType(0))); 288 break; 289 } 290 case ISD::CONDCODE: 291 assert(CondCodeNodes[cast<CondCodeSDNode>(N)->get()] && 292 "Cond code doesn't exist!"); 293 Erased = CondCodeNodes[cast<CondCodeSDNode>(N)->get()] != 0; 294 CondCodeNodes[cast<CondCodeSDNode>(N)->get()] = 0; 295 break; 296 case ISD::GlobalAddress: 297 Erased = GlobalValues.erase(cast<GlobalAddressSDNode>(N)->getGlobal()); 298 break; 299 case ISD::TargetGlobalAddress: 300 Erased =TargetGlobalValues.erase(cast<GlobalAddressSDNode>(N)->getGlobal()); 301 break; 302 case ISD::FrameIndex: 303 Erased = FrameIndices.erase(cast<FrameIndexSDNode>(N)->getIndex()); 304 break; 305 case ISD::TargetFrameIndex: 306 Erased = TargetFrameIndices.erase(cast<FrameIndexSDNode>(N)->getIndex()); 307 break; 308 case ISD::ConstantPool: 309 Erased = ConstantPoolIndices.erase(cast<ConstantPoolSDNode>(N)->get()); 310 break; 311 case ISD::TargetConstantPool: 312 Erased =TargetConstantPoolIndices.erase(cast<ConstantPoolSDNode>(N)->get()); 313 break; 314 case ISD::BasicBlock: 315 Erased = BBNodes.erase(cast<BasicBlockSDNode>(N)->getBasicBlock()); 316 break; 317 case ISD::ExternalSymbol: 318 Erased = ExternalSymbols.erase(cast<ExternalSymbolSDNode>(N)->getSymbol()); 319 break; 320 case ISD::VALUETYPE: 321 Erased = ValueTypeNodes[cast<VTSDNode>(N)->getVT()] != 0; 322 ValueTypeNodes[cast<VTSDNode>(N)->getVT()] = 0; 323 break; 324 case ISD::Register: 325 Erased = RegNodes.erase(std::make_pair(cast<RegisterSDNode>(N)->getReg(), 326 N->getValueType(0))); 327 break; 328 case ISD::SRCVALUE: { 329 SrcValueSDNode *SVN = cast<SrcValueSDNode>(N); 330 Erased =ValueNodes.erase(std::make_pair(SVN->getValue(), SVN->getOffset())); 331 break; 332 } 333 case ISD::LOAD: 334 Erased = Loads.erase(std::make_pair(N->getOperand(1), 335 std::make_pair(N->getOperand(0), 336 N->getValueType(0)))); 337 break; 338 default: 339 if (N->getNumValues() == 1) { 340 if (N->getNumOperands() == 0) { 341 Erased = NullaryOps.erase(std::make_pair(N->getOpcode(), 342 N->getValueType(0))); 343 } else if (N->getNumOperands() == 1) { 344 Erased = 345 UnaryOps.erase(std::make_pair(N->getOpcode(), 346 std::make_pair(N->getOperand(0), 347 N->getValueType(0)))); 348 } else if (N->getNumOperands() == 2) { 349 Erased = 350 BinaryOps.erase(std::make_pair(N->getOpcode(), 351 std::make_pair(N->getOperand(0), 352 N->getOperand(1)))); 353 } else { 354 std::vector<SDOperand> Ops(N->op_begin(), N->op_end()); 355 Erased = 356 OneResultNodes.erase(std::make_pair(N->getOpcode(), 357 std::make_pair(N->getValueType(0), 358 Ops))); 359 } 360 } else { 361 // Remove the node from the ArbitraryNodes map. 362 std::vector<MVT::ValueType> RV(N->value_begin(), N->value_end()); 363 std::vector<SDOperand> Ops(N->op_begin(), N->op_end()); 364 Erased = 365 ArbitraryNodes.erase(std::make_pair(N->getOpcode(), 366 std::make_pair(RV, Ops))); 367 } 368 break; 369 } 370#ifndef NDEBUG 371 // Verify that the node was actually in one of the CSE maps, unless it has a 372 // flag result (which cannot be CSE'd) or is one of the special cases that are 373 // not subject to CSE. 374 if (!Erased && N->getValueType(N->getNumValues()-1) != MVT::Flag && 375 N->getOpcode() != ISD::CALL && N->getOpcode() != ISD::CALLSEQ_START && 376 N->getOpcode() != ISD::CALLSEQ_END && !N->isTargetOpcode()) { 377 378 N->dump(); 379 assert(0 && "Node is not in map!"); 380 } 381#endif 382} 383 384/// AddNonLeafNodeToCSEMaps - Add the specified node back to the CSE maps. It 385/// has been taken out and modified in some way. If the specified node already 386/// exists in the CSE maps, do not modify the maps, but return the existing node 387/// instead. If it doesn't exist, add it and return null. 388/// 389SDNode *SelectionDAG::AddNonLeafNodeToCSEMaps(SDNode *N) { 390 assert(N->getNumOperands() && "This is a leaf node!"); 391 if (N->getOpcode() == ISD::LOAD) { 392 SDNode *&L = Loads[std::make_pair(N->getOperand(1), 393 std::make_pair(N->getOperand(0), 394 N->getValueType(0)))]; 395 if (L) return L; 396 L = N; 397 } else if (N->getOpcode() == ISD::HANDLENODE) { 398 return 0; // never add it. 399 } else if (N->getNumOperands() == 1) { 400 SDNode *&U = UnaryOps[std::make_pair(N->getOpcode(), 401 std::make_pair(N->getOperand(0), 402 N->getValueType(0)))]; 403 if (U) return U; 404 U = N; 405 } else if (N->getNumOperands() == 2) { 406 SDNode *&B = BinaryOps[std::make_pair(N->getOpcode(), 407 std::make_pair(N->getOperand(0), 408 N->getOperand(1)))]; 409 if (B) return B; 410 B = N; 411 } else if (N->getNumValues() == 1) { 412 std::vector<SDOperand> Ops(N->op_begin(), N->op_end()); 413 SDNode *&ORN = OneResultNodes[std::make_pair(N->getOpcode(), 414 std::make_pair(N->getValueType(0), Ops))]; 415 if (ORN) return ORN; 416 ORN = N; 417 } else { 418 // Remove the node from the ArbitraryNodes map. 419 std::vector<MVT::ValueType> RV(N->value_begin(), N->value_end()); 420 std::vector<SDOperand> Ops(N->op_begin(), N->op_end()); 421 SDNode *&AN = ArbitraryNodes[std::make_pair(N->getOpcode(), 422 std::make_pair(RV, Ops))]; 423 if (AN) return AN; 424 AN = N; 425 } 426 return 0; 427 428} 429 430 431 432SelectionDAG::~SelectionDAG() { 433 for (unsigned i = 0, e = AllNodes.size(); i != e; ++i) 434 delete AllNodes[i]; 435} 436 437SDOperand SelectionDAG::getZeroExtendInReg(SDOperand Op, MVT::ValueType VT) { 438 if (Op.getValueType() == VT) return Op; 439 int64_t Imm = ~0ULL >> (64-MVT::getSizeInBits(VT)); 440 return getNode(ISD::AND, Op.getValueType(), Op, 441 getConstant(Imm, Op.getValueType())); 442} 443 444SDOperand SelectionDAG::getConstant(uint64_t Val, MVT::ValueType VT) { 445 assert(MVT::isInteger(VT) && "Cannot create FP integer constant!"); 446 // Mask out any bits that are not valid for this constant. 447 if (VT != MVT::i64) 448 Val &= ((uint64_t)1 << MVT::getSizeInBits(VT)) - 1; 449 450 SDNode *&N = Constants[std::make_pair(Val, VT)]; 451 if (N) return SDOperand(N, 0); 452 N = new ConstantSDNode(false, Val, VT); 453 AllNodes.push_back(N); 454 return SDOperand(N, 0); 455} 456 457SDOperand SelectionDAG::getTargetConstant(uint64_t Val, MVT::ValueType VT) { 458 assert(MVT::isInteger(VT) && "Cannot create FP integer constant!"); 459 // Mask out any bits that are not valid for this constant. 460 if (VT != MVT::i64) 461 Val &= ((uint64_t)1 << MVT::getSizeInBits(VT)) - 1; 462 463 SDNode *&N = TargetConstants[std::make_pair(Val, VT)]; 464 if (N) return SDOperand(N, 0); 465 N = new ConstantSDNode(true, Val, VT); 466 AllNodes.push_back(N); 467 return SDOperand(N, 0); 468} 469 470SDOperand SelectionDAG::getConstantFP(double Val, MVT::ValueType VT) { 471 assert(MVT::isFloatingPoint(VT) && "Cannot create integer FP constant!"); 472 if (VT == MVT::f32) 473 Val = (float)Val; // Mask out extra precision. 474 475 // Do the map lookup using the actual bit pattern for the floating point 476 // value, so that we don't have problems with 0.0 comparing equal to -0.0, and 477 // we don't have issues with SNANs. 478 SDNode *&N = ConstantFPs[std::make_pair(DoubleToBits(Val), VT)]; 479 if (N) return SDOperand(N, 0); 480 N = new ConstantFPSDNode(Val, VT); 481 AllNodes.push_back(N); 482 return SDOperand(N, 0); 483} 484 485 486 487SDOperand SelectionDAG::getGlobalAddress(const GlobalValue *GV, 488 MVT::ValueType VT) { 489 SDNode *&N = GlobalValues[GV]; 490 if (N) return SDOperand(N, 0); 491 N = new GlobalAddressSDNode(false, GV, VT); 492 AllNodes.push_back(N); 493 return SDOperand(N, 0); 494} 495 496SDOperand SelectionDAG::getTargetGlobalAddress(const GlobalValue *GV, 497 MVT::ValueType VT) { 498 SDNode *&N = TargetGlobalValues[GV]; 499 if (N) return SDOperand(N, 0); 500 N = new GlobalAddressSDNode(true, GV, VT); 501 AllNodes.push_back(N); 502 return SDOperand(N, 0); 503} 504 505SDOperand SelectionDAG::getFrameIndex(int FI, MVT::ValueType VT) { 506 SDNode *&N = FrameIndices[FI]; 507 if (N) return SDOperand(N, 0); 508 N = new FrameIndexSDNode(FI, VT, false); 509 AllNodes.push_back(N); 510 return SDOperand(N, 0); 511} 512 513SDOperand SelectionDAG::getTargetFrameIndex(int FI, MVT::ValueType VT) { 514 SDNode *&N = TargetFrameIndices[FI]; 515 if (N) return SDOperand(N, 0); 516 N = new FrameIndexSDNode(FI, VT, true); 517 AllNodes.push_back(N); 518 return SDOperand(N, 0); 519} 520 521SDOperand SelectionDAG::getConstantPool(Constant *C, MVT::ValueType VT) { 522 SDNode *&N = ConstantPoolIndices[C]; 523 if (N) return SDOperand(N, 0); 524 N = new ConstantPoolSDNode(C, VT, false); 525 AllNodes.push_back(N); 526 return SDOperand(N, 0); 527} 528 529SDOperand SelectionDAG::getTargetConstantPool(Constant *C, MVT::ValueType VT) { 530 SDNode *&N = TargetConstantPoolIndices[C]; 531 if (N) return SDOperand(N, 0); 532 N = new ConstantPoolSDNode(C, VT, true); 533 AllNodes.push_back(N); 534 return SDOperand(N, 0); 535} 536 537SDOperand SelectionDAG::getBasicBlock(MachineBasicBlock *MBB) { 538 SDNode *&N = BBNodes[MBB]; 539 if (N) return SDOperand(N, 0); 540 N = new BasicBlockSDNode(MBB); 541 AllNodes.push_back(N); 542 return SDOperand(N, 0); 543} 544 545SDOperand SelectionDAG::getValueType(MVT::ValueType VT) { 546 if ((unsigned)VT >= ValueTypeNodes.size()) 547 ValueTypeNodes.resize(VT+1); 548 if (ValueTypeNodes[VT] == 0) { 549 ValueTypeNodes[VT] = new VTSDNode(VT); 550 AllNodes.push_back(ValueTypeNodes[VT]); 551 } 552 553 return SDOperand(ValueTypeNodes[VT], 0); 554} 555 556SDOperand SelectionDAG::getExternalSymbol(const char *Sym, MVT::ValueType VT) { 557 SDNode *&N = ExternalSymbols[Sym]; 558 if (N) return SDOperand(N, 0); 559 N = new ExternalSymbolSDNode(Sym, VT); 560 AllNodes.push_back(N); 561 return SDOperand(N, 0); 562} 563 564SDOperand SelectionDAG::getCondCode(ISD::CondCode Cond) { 565 if ((unsigned)Cond >= CondCodeNodes.size()) 566 CondCodeNodes.resize(Cond+1); 567 568 if (CondCodeNodes[Cond] == 0) { 569 CondCodeNodes[Cond] = new CondCodeSDNode(Cond); 570 AllNodes.push_back(CondCodeNodes[Cond]); 571 } 572 return SDOperand(CondCodeNodes[Cond], 0); 573} 574 575SDOperand SelectionDAG::getRegister(unsigned RegNo, MVT::ValueType VT) { 576 RegisterSDNode *&Reg = RegNodes[std::make_pair(RegNo, VT)]; 577 if (!Reg) { 578 Reg = new RegisterSDNode(RegNo, VT); 579 AllNodes.push_back(Reg); 580 } 581 return SDOperand(Reg, 0); 582} 583 584/// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero. We use 585/// this predicate to simplify operations downstream. V and Mask are known to 586/// be the same type. 587static bool MaskedValueIsZero(const SDOperand &Op, uint64_t Mask, 588 const TargetLowering &TLI) { 589 unsigned SrcBits; 590 if (Mask == 0) return true; 591 592 // If we know the result of a setcc has the top bits zero, use this info. 593 switch (Op.getOpcode()) { 594 case ISD::Constant: 595 return (cast<ConstantSDNode>(Op)->getValue() & Mask) == 0; 596 597 case ISD::SETCC: 598 return ((Mask & 1) == 0) && 599 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult; 600 601 case ISD::ZEXTLOAD: 602 SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(3))->getVT()); 603 return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits. 604 case ISD::ZERO_EXTEND: 605 SrcBits = MVT::getSizeInBits(Op.getOperand(0).getValueType()); 606 return MaskedValueIsZero(Op.getOperand(0),Mask & ((1ULL << SrcBits)-1),TLI); 607 case ISD::AssertZext: 608 SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(1))->getVT()); 609 return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits. 610 case ISD::AND: 611 // (X & C1) & C2 == 0 iff C1 & C2 == 0. 612 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(Op.getOperand(1))) 613 return MaskedValueIsZero(Op.getOperand(0),AndRHS->getValue() & Mask, TLI); 614 615 // FALL THROUGH 616 case ISD::OR: 617 case ISD::XOR: 618 return MaskedValueIsZero(Op.getOperand(0), Mask, TLI) && 619 MaskedValueIsZero(Op.getOperand(1), Mask, TLI); 620 case ISD::SELECT: 621 return MaskedValueIsZero(Op.getOperand(1), Mask, TLI) && 622 MaskedValueIsZero(Op.getOperand(2), Mask, TLI); 623 case ISD::SELECT_CC: 624 return MaskedValueIsZero(Op.getOperand(2), Mask, TLI) && 625 MaskedValueIsZero(Op.getOperand(3), Mask, TLI); 626 case ISD::SRL: 627 // (ushr X, C1) & C2 == 0 iff X & (C2 << C1) == 0 628 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 629 uint64_t NewVal = Mask << ShAmt->getValue(); 630 SrcBits = MVT::getSizeInBits(Op.getValueType()); 631 if (SrcBits != 64) NewVal &= (1ULL << SrcBits)-1; 632 return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI); 633 } 634 return false; 635 case ISD::SHL: 636 // (ushl X, C1) & C2 == 0 iff X & (C2 >> C1) == 0 637 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 638 uint64_t NewVal = Mask >> ShAmt->getValue(); 639 return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI); 640 } 641 return false; 642 case ISD::SUB: 643 if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) { 644 // We know that the top bits of C-X are clear if X contains less bits 645 // than C (i.e. no wrap-around can happen). For example, 20-X is 646 // positive if we can prove that X is >= 0 and < 16. 647 unsigned Bits = MVT::getSizeInBits(CLHS->getValueType(0)); 648 if ((CLHS->getValue() & (1 << (Bits-1))) == 0) { // sign bit clear 649 unsigned NLZ = CountLeadingZeros_64(CLHS->getValue()+1); 650 uint64_t MaskV = (1ULL << (63-NLZ))-1; 651 if (MaskedValueIsZero(Op.getOperand(1), ~MaskV, TLI)) { 652 // High bits are clear this value is known to be >= C. 653 unsigned NLZ2 = CountLeadingZeros_64(CLHS->getValue()); 654 if ((Mask & ((1ULL << (64-NLZ2))-1)) == 0) 655 return true; 656 } 657 } 658 } 659 break; 660 case ISD::CTTZ: 661 case ISD::CTLZ: 662 case ISD::CTPOP: 663 // Bit counting instructions can not set the high bits of the result 664 // register. The max number of bits sets depends on the input. 665 return (Mask & (MVT::getSizeInBits(Op.getValueType())*2-1)) == 0; 666 667 // TODO we could handle some SRA cases here. 668 default: break; 669 } 670 671 return false; 672} 673 674 675 676SDOperand SelectionDAG::SimplifySetCC(MVT::ValueType VT, SDOperand N1, 677 SDOperand N2, ISD::CondCode Cond) { 678 // These setcc operations always fold. 679 switch (Cond) { 680 default: break; 681 case ISD::SETFALSE: 682 case ISD::SETFALSE2: return getConstant(0, VT); 683 case ISD::SETTRUE: 684 case ISD::SETTRUE2: return getConstant(1, VT); 685 } 686 687 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val)) { 688 uint64_t C2 = N2C->getValue(); 689 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) { 690 uint64_t C1 = N1C->getValue(); 691 692 // Sign extend the operands if required 693 if (ISD::isSignedIntSetCC(Cond)) { 694 C1 = N1C->getSignExtended(); 695 C2 = N2C->getSignExtended(); 696 } 697 698 switch (Cond) { 699 default: assert(0 && "Unknown integer setcc!"); 700 case ISD::SETEQ: return getConstant(C1 == C2, VT); 701 case ISD::SETNE: return getConstant(C1 != C2, VT); 702 case ISD::SETULT: return getConstant(C1 < C2, VT); 703 case ISD::SETUGT: return getConstant(C1 > C2, VT); 704 case ISD::SETULE: return getConstant(C1 <= C2, VT); 705 case ISD::SETUGE: return getConstant(C1 >= C2, VT); 706 case ISD::SETLT: return getConstant((int64_t)C1 < (int64_t)C2, VT); 707 case ISD::SETGT: return getConstant((int64_t)C1 > (int64_t)C2, VT); 708 case ISD::SETLE: return getConstant((int64_t)C1 <= (int64_t)C2, VT); 709 case ISD::SETGE: return getConstant((int64_t)C1 >= (int64_t)C2, VT); 710 } 711 } else { 712 // If the LHS is a ZERO_EXTEND, perform the comparison on the input. 713 if (N1.getOpcode() == ISD::ZERO_EXTEND) { 714 unsigned InSize = MVT::getSizeInBits(N1.getOperand(0).getValueType()); 715 716 // If the comparison constant has bits in the upper part, the 717 // zero-extended value could never match. 718 if (C2 & (~0ULL << InSize)) { 719 unsigned VSize = MVT::getSizeInBits(N1.getValueType()); 720 switch (Cond) { 721 case ISD::SETUGT: 722 case ISD::SETUGE: 723 case ISD::SETEQ: return getConstant(0, VT); 724 case ISD::SETULT: 725 case ISD::SETULE: 726 case ISD::SETNE: return getConstant(1, VT); 727 case ISD::SETGT: 728 case ISD::SETGE: 729 // True if the sign bit of C2 is set. 730 return getConstant((C2 & (1ULL << VSize)) != 0, VT); 731 case ISD::SETLT: 732 case ISD::SETLE: 733 // True if the sign bit of C2 isn't set. 734 return getConstant((C2 & (1ULL << VSize)) == 0, VT); 735 default: 736 break; 737 } 738 } 739 740 // Otherwise, we can perform the comparison with the low bits. 741 switch (Cond) { 742 case ISD::SETEQ: 743 case ISD::SETNE: 744 case ISD::SETUGT: 745 case ISD::SETUGE: 746 case ISD::SETULT: 747 case ISD::SETULE: 748 return getSetCC(VT, N1.getOperand(0), 749 getConstant(C2, N1.getOperand(0).getValueType()), 750 Cond); 751 default: 752 break; // todo, be more careful with signed comparisons 753 } 754 } else if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG && 755 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 756 MVT::ValueType ExtSrcTy = cast<VTSDNode>(N1.getOperand(1))->getVT(); 757 unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy); 758 MVT::ValueType ExtDstTy = N1.getValueType(); 759 unsigned ExtDstTyBits = MVT::getSizeInBits(ExtDstTy); 760 761 // If the extended part has any inconsistent bits, it cannot ever 762 // compare equal. In other words, they have to be all ones or all 763 // zeros. 764 uint64_t ExtBits = 765 (~0ULL >> (64-ExtSrcTyBits)) & (~0ULL << (ExtDstTyBits-1)); 766 if ((C2 & ExtBits) != 0 && (C2 & ExtBits) != ExtBits) 767 return getConstant(Cond == ISD::SETNE, VT); 768 769 // Otherwise, make this a use of a zext. 770 return getSetCC(VT, getZeroExtendInReg(N1.getOperand(0), ExtSrcTy), 771 getConstant(C2 & (~0ULL>>(64-ExtSrcTyBits)), ExtDstTy), 772 Cond); 773 } 774 775 uint64_t MinVal, MaxVal; 776 unsigned OperandBitSize = MVT::getSizeInBits(N2C->getValueType(0)); 777 if (ISD::isSignedIntSetCC(Cond)) { 778 MinVal = 1ULL << (OperandBitSize-1); 779 if (OperandBitSize != 1) // Avoid X >> 64, which is undefined. 780 MaxVal = ~0ULL >> (65-OperandBitSize); 781 else 782 MaxVal = 0; 783 } else { 784 MinVal = 0; 785 MaxVal = ~0ULL >> (64-OperandBitSize); 786 } 787 788 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 789 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 790 if (C2 == MinVal) return getConstant(1, VT); // X >= MIN --> true 791 --C2; // X >= C1 --> X > (C1-1) 792 return getSetCC(VT, N1, getConstant(C2, N2.getValueType()), 793 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); 794 } 795 796 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 797 if (C2 == MaxVal) return getConstant(1, VT); // X <= MAX --> true 798 ++C2; // X <= C1 --> X < (C1+1) 799 return getSetCC(VT, N1, getConstant(C2, N2.getValueType()), 800 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); 801 } 802 803 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C2 == MinVal) 804 return getConstant(0, VT); // X < MIN --> false 805 806 // Canonicalize setgt X, Min --> setne X, Min 807 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C2 == MinVal) 808 return getSetCC(VT, N1, N2, ISD::SETNE); 809 810 // If we have setult X, 1, turn it into seteq X, 0 811 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C2 == MinVal+1) 812 return getSetCC(VT, N1, getConstant(MinVal, N1.getValueType()), 813 ISD::SETEQ); 814 // If we have setugt X, Max-1, turn it into seteq X, Max 815 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C2 == MaxVal-1) 816 return getSetCC(VT, N1, getConstant(MaxVal, N1.getValueType()), 817 ISD::SETEQ); 818 819 // If we have "setcc X, C1", check to see if we can shrink the immediate 820 // by changing cc. 821 822 // SETUGT X, SINTMAX -> SETLT X, 0 823 if (Cond == ISD::SETUGT && OperandBitSize != 1 && 824 C2 == (~0ULL >> (65-OperandBitSize))) 825 return getSetCC(VT, N1, getConstant(0, N2.getValueType()), ISD::SETLT); 826 827 // FIXME: Implement the rest of these. 828 829 830 // Fold bit comparisons when we can. 831 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 832 VT == N1.getValueType() && N1.getOpcode() == ISD::AND) 833 if (ConstantSDNode *AndRHS = 834 dyn_cast<ConstantSDNode>(N1.getOperand(1))) { 835 if (Cond == ISD::SETNE && C2 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 836 // Perform the xform if the AND RHS is a single bit. 837 if ((AndRHS->getValue() & (AndRHS->getValue()-1)) == 0) { 838 return getNode(ISD::SRL, VT, N1, 839 getConstant(Log2_64(AndRHS->getValue()), 840 TLI.getShiftAmountTy())); 841 } 842 } else if (Cond == ISD::SETEQ && C2 == AndRHS->getValue()) { 843 // (X & 8) == 8 --> (X & 8) >> 3 844 // Perform the xform if C2 is a single bit. 845 if ((C2 & (C2-1)) == 0) { 846 return getNode(ISD::SRL, VT, N1, 847 getConstant(Log2_64(C2),TLI.getShiftAmountTy())); 848 } 849 } 850 } 851 } 852 } else if (isa<ConstantSDNode>(N1.Val)) { 853 // Ensure that the constant occurs on the RHS. 854 return getSetCC(VT, N2, N1, ISD::getSetCCSwappedOperands(Cond)); 855 } 856 857 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.Val)) 858 if (ConstantFPSDNode *N2C = dyn_cast<ConstantFPSDNode>(N2.Val)) { 859 double C1 = N1C->getValue(), C2 = N2C->getValue(); 860 861 switch (Cond) { 862 default: break; // FIXME: Implement the rest of these! 863 case ISD::SETEQ: return getConstant(C1 == C2, VT); 864 case ISD::SETNE: return getConstant(C1 != C2, VT); 865 case ISD::SETLT: return getConstant(C1 < C2, VT); 866 case ISD::SETGT: return getConstant(C1 > C2, VT); 867 case ISD::SETLE: return getConstant(C1 <= C2, VT); 868 case ISD::SETGE: return getConstant(C1 >= C2, VT); 869 } 870 } else { 871 // Ensure that the constant occurs on the RHS. 872 return getSetCC(VT, N2, N1, ISD::getSetCCSwappedOperands(Cond)); 873 } 874 875 if (!CombinerEnabled) { 876 if (N1 == N2) { 877 // We can always fold X == Y for integer setcc's. 878 if (MVT::isInteger(N1.getValueType())) 879 return getConstant(ISD::isTrueWhenEqual(Cond), VT); 880 unsigned UOF = ISD::getUnorderedFlavor(Cond); 881 if (UOF == 2) // FP operators that are undefined on NaNs. 882 return getConstant(ISD::isTrueWhenEqual(Cond), VT); 883 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 884 return getConstant(UOF, VT); 885 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 886 // if it is not already. 887 ISD::CondCode NewCond = UOF == 0 ? ISD::SETUO : ISD::SETO; 888 if (NewCond != Cond) 889 return getSetCC(VT, N1, N2, NewCond); 890 } 891 892 if (Cond == ISD::SETEQ || Cond == ISD::SETNE) { 893 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 894 N1.getOpcode() == ISD::XOR) { 895 // Simplify (X+Y) == (X+Z) --> Y == Z 896 if (N1.getOpcode() == N2.getOpcode()) { 897 if (N1.getOperand(0) == N2.getOperand(0)) 898 return getSetCC(VT, N1.getOperand(1), N2.getOperand(1), Cond); 899 if (N1.getOperand(1) == N2.getOperand(1)) 900 return getSetCC(VT, N1.getOperand(0), N2.getOperand(0), Cond); 901 if (isCommutativeBinOp(N1.getOpcode())) { 902 // If X op Y == Y op X, try other combinations. 903 if (N1.getOperand(0) == N2.getOperand(1)) 904 return getSetCC(VT, N1.getOperand(1), N2.getOperand(0), Cond); 905 if (N1.getOperand(1) == N2.getOperand(0)) 906 return getSetCC(VT, N1.getOperand(1), N2.getOperand(1), Cond); 907 } 908 } 909 910 // FIXME: move this stuff to the DAG Combiner when it exists! 911 912 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. Common for condcodes. 913 if (N1.getOpcode() == ISD::XOR) 914 if (ConstantSDNode *XORC = dyn_cast<ConstantSDNode>(N1.getOperand(1))) 915 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N2)) { 916 // If we know that all of the inverted bits are zero, don't bother 917 // performing the inversion. 918 if (MaskedValueIsZero(N1.getOperand(0), ~XORC->getValue(), TLI)) 919 return getSetCC(VT, N1.getOperand(0), 920 getConstant(XORC->getValue()^RHSC->getValue(), 921 N1.getValueType()), Cond); 922 } 923 924 // Simplify (X+Z) == X --> Z == 0 925 if (N1.getOperand(0) == N2) 926 return getSetCC(VT, N1.getOperand(1), 927 getConstant(0, N1.getValueType()), Cond); 928 if (N1.getOperand(1) == N2) { 929 if (isCommutativeBinOp(N1.getOpcode())) 930 return getSetCC(VT, N1.getOperand(0), 931 getConstant(0, N1.getValueType()), Cond); 932 else { 933 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 934 // (Z-X) == X --> Z == X<<1 935 return getSetCC(VT, N1.getOperand(0), 936 getNode(ISD::SHL, N2.getValueType(), 937 N2, getConstant(1, TLI.getShiftAmountTy())), 938 Cond); 939 } 940 } 941 } 942 943 if (N2.getOpcode() == ISD::ADD || N2.getOpcode() == ISD::SUB || 944 N2.getOpcode() == ISD::XOR) { 945 // Simplify X == (X+Z) --> Z == 0 946 if (N2.getOperand(0) == N1) { 947 return getSetCC(VT, N2.getOperand(1), 948 getConstant(0, N2.getValueType()), Cond); 949 } else if (N2.getOperand(1) == N1) { 950 if (isCommutativeBinOp(N2.getOpcode())) { 951 return getSetCC(VT, N2.getOperand(0), 952 getConstant(0, N2.getValueType()), Cond); 953 } else { 954 assert(N2.getOpcode() == ISD::SUB && "Unexpected operation!"); 955 // X == (Z-X) --> X<<1 == Z 956 return getSetCC(VT, getNode(ISD::SHL, N2.getValueType(), N1, 957 getConstant(1, TLI.getShiftAmountTy())), 958 N2.getOperand(0), Cond); 959 } 960 } 961 } 962 } 963 964 // Fold away ALL boolean setcc's. 965 if (N1.getValueType() == MVT::i1) { 966 switch (Cond) { 967 default: assert(0 && "Unknown integer setcc!"); 968 case ISD::SETEQ: // X == Y -> (X^Y)^1 969 N1 = getNode(ISD::XOR, MVT::i1, 970 getNode(ISD::XOR, MVT::i1, N1, N2), 971 getConstant(1, MVT::i1)); 972 break; 973 case ISD::SETNE: // X != Y --> (X^Y) 974 N1 = getNode(ISD::XOR, MVT::i1, N1, N2); 975 break; 976 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y 977 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y 978 N1 = getNode(ISD::AND, MVT::i1, N2, 979 getNode(ISD::XOR, MVT::i1, N1, getConstant(1, MVT::i1))); 980 break; 981 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X 982 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X 983 N1 = getNode(ISD::AND, MVT::i1, N1, 984 getNode(ISD::XOR, MVT::i1, N2, getConstant(1, MVT::i1))); 985 break; 986 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y 987 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y 988 N1 = getNode(ISD::OR, MVT::i1, N2, 989 getNode(ISD::XOR, MVT::i1, N1, getConstant(1, MVT::i1))); 990 break; 991 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X 992 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X 993 N1 = getNode(ISD::OR, MVT::i1, N1, 994 getNode(ISD::XOR, MVT::i1, N2, getConstant(1, MVT::i1))); 995 break; 996 } 997 if (VT != MVT::i1) 998 N1 = getNode(ISD::ZERO_EXTEND, VT, N1); 999 return N1; 1000 } 1001 } 1002 // Could not fold it. 1003 return SDOperand(); 1004} 1005 1006SDOperand SelectionDAG::SimplifySelectCC(SDOperand N1, SDOperand N2, 1007 SDOperand N3, SDOperand N4, 1008 ISD::CondCode CC) { 1009 MVT::ValueType VT = N3.getValueType(); 1010 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1011 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 1012 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val); 1013 ConstantSDNode *N4C = dyn_cast<ConstantSDNode>(N4.Val); 1014 1015 // Check to see if we can simplify the select into an fabs node 1016 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N2)) { 1017 // Allow either -0.0 or 0.0 1018 if (CFP->getValue() == 0.0) { 1019 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 1020 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 1021 N1 == N3 && N4.getOpcode() == ISD::FNEG && 1022 N1 == N4.getOperand(0)) 1023 return getNode(ISD::FABS, VT, N1); 1024 1025 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 1026 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 1027 N1 == N4 && N3.getOpcode() == ISD::FNEG && 1028 N3.getOperand(0) == N4) 1029 return getNode(ISD::FABS, VT, N4); 1030 } 1031 } 1032 1033 // check to see if we're select_cc'ing a select_cc. 1034 // this allows us to turn: 1035 // select_cc set[eq,ne] (select_cc cc, lhs, rhs, 1, 0), 0, true, false -> 1036 // select_cc cc, lhs, rhs, true, false 1037 if ((N1C && N1C->isNullValue() && N2.getOpcode() == ISD::SELECT_CC) || 1038 (N2C && N2C->isNullValue() && N1.getOpcode() == ISD::SELECT_CC) && 1039 (CC == ISD::SETEQ || CC == ISD::SETNE)) { 1040 SDOperand SCC = N1C ? N2 : N1; 1041 ConstantSDNode *SCCT = dyn_cast<ConstantSDNode>(SCC.getOperand(2)); 1042 ConstantSDNode *SCCF = dyn_cast<ConstantSDNode>(SCC.getOperand(3)); 1043 if (SCCT && SCCF && SCCF->isNullValue() && SCCT->getValue() == 1ULL) { 1044 if (CC == ISD::SETEQ) std::swap(N3, N4); 1045 return getNode(ISD::SELECT_CC, N3.getValueType(), SCC.getOperand(0), 1046 SCC.getOperand(1), N3, N4, SCC.getOperand(4)); 1047 } 1048 } 1049 1050 // Check to see if we can perform the "gzip trick", transforming 1051 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A 1052 if (N2C && N2C->isNullValue() && N4C && N4C->isNullValue() && 1053 MVT::isInteger(N1.getValueType()) && 1054 MVT::isInteger(N3.getValueType()) && CC == ISD::SETLT) { 1055 MVT::ValueType XType = N1.getValueType(); 1056 MVT::ValueType AType = N3.getValueType(); 1057 if (XType >= AType) { 1058 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 1059 // single-bit constant. FIXME: remove once the dag combiner 1060 // exists. 1061 if (N3C && ((N3C->getValue() & (N3C->getValue()-1)) == 0)) { 1062 unsigned ShCtV = Log2_64(N3C->getValue()); 1063 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1; 1064 SDOperand ShCt = getConstant(ShCtV, TLI.getShiftAmountTy()); 1065 SDOperand Shift = getNode(ISD::SRL, XType, N1, ShCt); 1066 if (XType > AType) 1067 Shift = getNode(ISD::TRUNCATE, AType, Shift); 1068 return getNode(ISD::AND, AType, Shift, N3); 1069 } 1070 SDOperand Shift = getNode(ISD::SRA, XType, N1, 1071 getConstant(MVT::getSizeInBits(XType)-1, 1072 TLI.getShiftAmountTy())); 1073 if (XType > AType) 1074 Shift = getNode(ISD::TRUNCATE, AType, Shift); 1075 return getNode(ISD::AND, AType, Shift, N3); 1076 } 1077 } 1078 1079 // Check to see if this is the equivalent of setcc 1080 if (N4C && N4C->isNullValue() && N3C && (N3C->getValue() == 1ULL)) { 1081 MVT::ValueType XType = N1.getValueType(); 1082 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) { 1083 SDOperand Res = getSetCC(TLI.getSetCCResultTy(), N1, N2, CC); 1084 if (Res.getValueType() != VT) 1085 Res = getNode(ISD::ZERO_EXTEND, VT, Res); 1086 return Res; 1087 } 1088 1089 // seteq X, 0 -> srl (ctlz X, log2(size(X))) 1090 if (N2C && N2C->isNullValue() && CC == ISD::SETEQ && 1091 TLI.isOperationLegal(ISD::CTLZ, XType)) { 1092 SDOperand Ctlz = getNode(ISD::CTLZ, XType, N1); 1093 return getNode(ISD::SRL, XType, Ctlz, 1094 getConstant(Log2_32(MVT::getSizeInBits(XType)), 1095 TLI.getShiftAmountTy())); 1096 } 1097 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1) 1098 if (N2C && N2C->isNullValue() && CC == ISD::SETGT) { 1099 SDOperand NegN1 = getNode(ISD::SUB, XType, getConstant(0, XType), N1); 1100 SDOperand NotN1 = getNode(ISD::XOR, XType, N1, getConstant(~0ULL, XType)); 1101 return getNode(ISD::SRL, XType, getNode(ISD::AND, XType, NegN1, NotN1), 1102 getConstant(MVT::getSizeInBits(XType)-1, 1103 TLI.getShiftAmountTy())); 1104 } 1105 // setgt X, -1 -> xor (srl (X, size(X)-1), 1) 1106 if (N2C && N2C->isAllOnesValue() && CC == ISD::SETGT) { 1107 SDOperand Sign = getNode(ISD::SRL, XType, N1, 1108 getConstant(MVT::getSizeInBits(XType)-1, 1109 TLI.getShiftAmountTy())); 1110 return getNode(ISD::XOR, XType, Sign, getConstant(1, XType)); 1111 } 1112 } 1113 1114 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 1115 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 1116 if (N2C && N2C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 1117 N1 == N4 && N3.getOpcode() == ISD::SUB && N1 == N3.getOperand(1)) { 1118 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) { 1119 MVT::ValueType XType = N1.getValueType(); 1120 if (SubC->isNullValue() && MVT::isInteger(XType)) { 1121 SDOperand Shift = getNode(ISD::SRA, XType, N1, 1122 getConstant(MVT::getSizeInBits(XType)-1, 1123 TLI.getShiftAmountTy())); 1124 return getNode(ISD::XOR, XType, getNode(ISD::ADD, XType, N1, Shift), 1125 Shift); 1126 } 1127 } 1128 } 1129 1130 // Could not fold it. 1131 return SDOperand(); 1132} 1133 1134/// getNode - Gets or creates the specified node. 1135/// 1136SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT) { 1137 SDNode *&N = NullaryOps[std::make_pair(Opcode, VT)]; 1138 if (!N) { 1139 N = new SDNode(Opcode, VT); 1140 AllNodes.push_back(N); 1141 } 1142 return SDOperand(N, 0); 1143} 1144 1145SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, 1146 SDOperand Operand) { 1147 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Operand.Val)) { 1148 uint64_t Val = C->getValue(); 1149 switch (Opcode) { 1150 default: break; 1151 case ISD::SIGN_EXTEND: return getConstant(C->getSignExtended(), VT); 1152 case ISD::ANY_EXTEND: 1153 case ISD::ZERO_EXTEND: return getConstant(Val, VT); 1154 case ISD::TRUNCATE: return getConstant(Val, VT); 1155 case ISD::SINT_TO_FP: return getConstantFP(C->getSignExtended(), VT); 1156 case ISD::UINT_TO_FP: return getConstantFP(C->getValue(), VT); 1157 } 1158 } 1159 1160 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Operand.Val)) 1161 switch (Opcode) { 1162 case ISD::FNEG: 1163 return getConstantFP(-C->getValue(), VT); 1164 case ISD::FP_ROUND: 1165 case ISD::FP_EXTEND: 1166 return getConstantFP(C->getValue(), VT); 1167 case ISD::FP_TO_SINT: 1168 return getConstant((int64_t)C->getValue(), VT); 1169 case ISD::FP_TO_UINT: 1170 return getConstant((uint64_t)C->getValue(), VT); 1171 } 1172 1173 unsigned OpOpcode = Operand.Val->getOpcode(); 1174 switch (Opcode) { 1175 case ISD::TokenFactor: 1176 return Operand; // Factor of one node? No factor. 1177 case ISD::SIGN_EXTEND: 1178 if (Operand.getValueType() == VT) return Operand; // noop extension 1179 if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND) 1180 return getNode(OpOpcode, VT, Operand.Val->getOperand(0)); 1181 break; 1182 case ISD::ZERO_EXTEND: 1183 if (Operand.getValueType() == VT) return Operand; // noop extension 1184 if (OpOpcode == ISD::ZERO_EXTEND) // (zext (zext x)) -> (zext x) 1185 return getNode(ISD::ZERO_EXTEND, VT, Operand.Val->getOperand(0)); 1186 break; 1187 case ISD::ANY_EXTEND: 1188 if (Operand.getValueType() == VT) return Operand; // noop extension 1189 if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND) 1190 // (ext (zext x)) -> (zext x) and (ext (sext x)) -> (sext x) 1191 return getNode(OpOpcode, VT, Operand.Val->getOperand(0)); 1192 break; 1193 case ISD::TRUNCATE: 1194 if (Operand.getValueType() == VT) return Operand; // noop truncate 1195 if (OpOpcode == ISD::TRUNCATE) 1196 return getNode(ISD::TRUNCATE, VT, Operand.Val->getOperand(0)); 1197 else if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND || 1198 OpOpcode == ISD::ANY_EXTEND) { 1199 // If the source is smaller than the dest, we still need an extend. 1200 if (Operand.Val->getOperand(0).getValueType() < VT) 1201 return getNode(OpOpcode, VT, Operand.Val->getOperand(0)); 1202 else if (Operand.Val->getOperand(0).getValueType() > VT) 1203 return getNode(ISD::TRUNCATE, VT, Operand.Val->getOperand(0)); 1204 else 1205 return Operand.Val->getOperand(0); 1206 } 1207 break; 1208 case ISD::FNEG: 1209 if (OpOpcode == ISD::FSUB) // -(X-Y) -> (Y-X) 1210 return getNode(ISD::FSUB, VT, Operand.Val->getOperand(1), 1211 Operand.Val->getOperand(0)); 1212 if (OpOpcode == ISD::FNEG) // --X -> X 1213 return Operand.Val->getOperand(0); 1214 break; 1215 case ISD::FABS: 1216 if (OpOpcode == ISD::FNEG) // abs(-X) -> abs(X) 1217 return getNode(ISD::FABS, VT, Operand.Val->getOperand(0)); 1218 break; 1219 } 1220 1221 SDNode *N; 1222 if (VT != MVT::Flag) { // Don't CSE flag producing nodes 1223 SDNode *&E = UnaryOps[std::make_pair(Opcode, std::make_pair(Operand, VT))]; 1224 if (E) return SDOperand(E, 0); 1225 E = N = new SDNode(Opcode, Operand); 1226 } else { 1227 N = new SDNode(Opcode, Operand); 1228 } 1229 N->setValueTypes(VT); 1230 AllNodes.push_back(N); 1231 return SDOperand(N, 0); 1232} 1233 1234 1235 1236SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, 1237 SDOperand N1, SDOperand N2) { 1238#ifndef NDEBUG 1239 switch (Opcode) { 1240 case ISD::TokenFactor: 1241 assert(VT == MVT::Other && N1.getValueType() == MVT::Other && 1242 N2.getValueType() == MVT::Other && "Invalid token factor!"); 1243 break; 1244 case ISD::AND: 1245 case ISD::OR: 1246 case ISD::XOR: 1247 case ISD::UDIV: 1248 case ISD::UREM: 1249 case ISD::MULHU: 1250 case ISD::MULHS: 1251 assert(MVT::isInteger(VT) && "This operator does not apply to FP types!"); 1252 // fall through 1253 case ISD::ADD: 1254 case ISD::SUB: 1255 case ISD::MUL: 1256 case ISD::SDIV: 1257 case ISD::SREM: 1258 assert(MVT::isInteger(N1.getValueType()) && "Should use F* for FP ops"); 1259 // fall through. 1260 case ISD::FADD: 1261 case ISD::FSUB: 1262 case ISD::FMUL: 1263 case ISD::FDIV: 1264 case ISD::FREM: 1265 assert(N1.getValueType() == N2.getValueType() && 1266 N1.getValueType() == VT && "Binary operator types must match!"); 1267 break; 1268 1269 case ISD::SHL: 1270 case ISD::SRA: 1271 case ISD::SRL: 1272 assert(VT == N1.getValueType() && 1273 "Shift operators return type must be the same as their first arg"); 1274 assert(MVT::isInteger(VT) && MVT::isInteger(N2.getValueType()) && 1275 VT != MVT::i1 && "Shifts only work on integers"); 1276 break; 1277 case ISD::FP_ROUND_INREG: { 1278 MVT::ValueType EVT = cast<VTSDNode>(N2)->getVT(); 1279 assert(VT == N1.getValueType() && "Not an inreg round!"); 1280 assert(MVT::isFloatingPoint(VT) && MVT::isFloatingPoint(EVT) && 1281 "Cannot FP_ROUND_INREG integer types"); 1282 assert(EVT <= VT && "Not rounding down!"); 1283 break; 1284 } 1285 case ISD::AssertSext: 1286 case ISD::AssertZext: 1287 case ISD::SIGN_EXTEND_INREG: { 1288 MVT::ValueType EVT = cast<VTSDNode>(N2)->getVT(); 1289 assert(VT == N1.getValueType() && "Not an inreg extend!"); 1290 assert(MVT::isInteger(VT) && MVT::isInteger(EVT) && 1291 "Cannot *_EXTEND_INREG FP types"); 1292 assert(EVT <= VT && "Not extending!"); 1293 } 1294 1295 default: break; 1296 } 1297#endif 1298 1299 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1300 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 1301 if (N1C) { 1302 if (N2C) { 1303 uint64_t C1 = N1C->getValue(), C2 = N2C->getValue(); 1304 switch (Opcode) { 1305 case ISD::ADD: return getConstant(C1 + C2, VT); 1306 case ISD::SUB: return getConstant(C1 - C2, VT); 1307 case ISD::MUL: return getConstant(C1 * C2, VT); 1308 case ISD::UDIV: 1309 if (C2) return getConstant(C1 / C2, VT); 1310 break; 1311 case ISD::UREM : 1312 if (C2) return getConstant(C1 % C2, VT); 1313 break; 1314 case ISD::SDIV : 1315 if (C2) return getConstant(N1C->getSignExtended() / 1316 N2C->getSignExtended(), VT); 1317 break; 1318 case ISD::SREM : 1319 if (C2) return getConstant(N1C->getSignExtended() % 1320 N2C->getSignExtended(), VT); 1321 break; 1322 case ISD::AND : return getConstant(C1 & C2, VT); 1323 case ISD::OR : return getConstant(C1 | C2, VT); 1324 case ISD::XOR : return getConstant(C1 ^ C2, VT); 1325 case ISD::SHL : return getConstant(C1 << C2, VT); 1326 case ISD::SRL : return getConstant(C1 >> C2, VT); 1327 case ISD::SRA : return getConstant(N1C->getSignExtended() >>(int)C2, VT); 1328 default: break; 1329 } 1330 } else { // Cannonicalize constant to RHS if commutative 1331 if (isCommutativeBinOp(Opcode)) { 1332 std::swap(N1C, N2C); 1333 std::swap(N1, N2); 1334 } 1335 } 1336 1337 if (!CombinerEnabled) { 1338 switch (Opcode) { 1339 default: break; 1340 case ISD::SHL: // shl 0, X -> 0 1341 if (N1C->isNullValue()) return N1; 1342 break; 1343 case ISD::SRL: // srl 0, X -> 0 1344 if (N1C->isNullValue()) return N1; 1345 break; 1346 case ISD::SRA: // sra -1, X -> -1 1347 if (N1C->isAllOnesValue()) return N1; 1348 break; 1349 case ISD::SIGN_EXTEND_INREG: // SIGN_EXTEND_INREG N1C, EVT 1350 // Extending a constant? Just return the extended constant. 1351 SDOperand Tmp = getNode(ISD::TRUNCATE, cast<VTSDNode>(N2)->getVT(), N1); 1352 return getNode(ISD::SIGN_EXTEND, VT, Tmp); 1353 } 1354 } 1355 } 1356 1357 if (!CombinerEnabled) { 1358 if (N2C) { 1359 uint64_t C2 = N2C->getValue(); 1360 1361 switch (Opcode) { 1362 case ISD::ADD: 1363 if (!C2) return N1; // add X, 0 -> X 1364 break; 1365 case ISD::SUB: 1366 if (!C2) return N1; // sub X, 0 -> X 1367 return getNode(ISD::ADD, VT, N1, getConstant(-C2, VT)); 1368 case ISD::MUL: 1369 if (!C2) return N2; // mul X, 0 -> 0 1370 if (N2C->isAllOnesValue()) // mul X, -1 -> 0-X 1371 return getNode(ISD::SUB, VT, getConstant(0, VT), N1); 1372 1373 // FIXME: Move this to the DAG combiner when it exists. 1374 if ((C2 & C2-1) == 0) { 1375 SDOperand ShAmt = getConstant(Log2_64(C2), TLI.getShiftAmountTy()); 1376 return getNode(ISD::SHL, VT, N1, ShAmt); 1377 } 1378 break; 1379 1380 case ISD::MULHU: 1381 case ISD::MULHS: 1382 if (!C2) return N2; // mul X, 0 -> 0 1383 1384 if (C2 == 1) // 0X*01 -> 0X hi(0X) == 0 1385 return getConstant(0, VT); 1386 1387 // Many others could be handled here, including -1, powers of 2, etc. 1388 break; 1389 1390 case ISD::UDIV: 1391 // FIXME: Move this to the DAG combiner when it exists. 1392 if ((C2 & C2-1) == 0 && C2) { 1393 SDOperand ShAmt = getConstant(Log2_64(C2), TLI.getShiftAmountTy()); 1394 return getNode(ISD::SRL, VT, N1, ShAmt); 1395 } 1396 break; 1397 1398 case ISD::SHL: 1399 case ISD::SRL: 1400 case ISD::SRA: 1401 // If the shift amount is bigger than the size of the data, then all the 1402 // bits are shifted out. Simplify to undef. 1403 if (C2 >= MVT::getSizeInBits(N1.getValueType())) { 1404 return getNode(ISD::UNDEF, N1.getValueType()); 1405 } 1406 if (C2 == 0) return N1; 1407 1408 if (Opcode == ISD::SRA) { 1409 // If the sign bit is known to be zero, switch this to a SRL. 1410 if (MaskedValueIsZero(N1, 1411 1ULL << (MVT::getSizeInBits(N1.getValueType())-1), 1412 TLI)) 1413 return getNode(ISD::SRL, N1.getValueType(), N1, N2); 1414 } else { 1415 // If the part left over is known to be zero, the whole thing is zero. 1416 uint64_t TypeMask = ~0ULL >> (64-MVT::getSizeInBits(N1.getValueType())); 1417 if (Opcode == ISD::SRL) { 1418 if (MaskedValueIsZero(N1, TypeMask << C2, TLI)) 1419 return getConstant(0, N1.getValueType()); 1420 } else if (Opcode == ISD::SHL) { 1421 if (MaskedValueIsZero(N1, TypeMask >> C2, TLI)) 1422 return getConstant(0, N1.getValueType()); 1423 } 1424 } 1425 1426 if (Opcode == ISD::SHL && N1.getNumOperands() == 2) 1427 if (ConstantSDNode *OpSA = dyn_cast<ConstantSDNode>(N1.getOperand(1))) { 1428 unsigned OpSAC = OpSA->getValue(); 1429 if (N1.getOpcode() == ISD::SHL) { 1430 if (C2+OpSAC >= MVT::getSizeInBits(N1.getValueType())) 1431 return getConstant(0, N1.getValueType()); 1432 return getNode(ISD::SHL, N1.getValueType(), N1.getOperand(0), 1433 getConstant(C2+OpSAC, N2.getValueType())); 1434 } else if (N1.getOpcode() == ISD::SRL) { 1435 // (X >> C1) << C2: if C2 > C1, ((X & ~0<<C1) << C2-C1) 1436 SDOperand Mask = getNode(ISD::AND, VT, N1.getOperand(0), 1437 getConstant(~0ULL << OpSAC, VT)); 1438 if (C2 > OpSAC) { 1439 return getNode(ISD::SHL, VT, Mask, 1440 getConstant(C2-OpSAC, N2.getValueType())); 1441 } else { 1442 // (X >> C1) << C2: if C2 <= C1, ((X & ~0<<C1) >> C1-C2) 1443 return getNode(ISD::SRL, VT, Mask, 1444 getConstant(OpSAC-C2, N2.getValueType())); 1445 } 1446 } else if (N1.getOpcode() == ISD::SRA) { 1447 // if C1 == C2, just mask out low bits. 1448 if (C2 == OpSAC) 1449 return getNode(ISD::AND, VT, N1.getOperand(0), 1450 getConstant(~0ULL << C2, VT)); 1451 } 1452 } 1453 break; 1454 1455 case ISD::AND: 1456 if (!C2) return N2; // X and 0 -> 0 1457 if (N2C->isAllOnesValue()) 1458 return N1; // X and -1 -> X 1459 1460 if (MaskedValueIsZero(N1, C2, TLI)) // X and 0 -> 0 1461 return getConstant(0, VT); 1462 1463 { 1464 uint64_t NotC2 = ~C2; 1465 if (VT != MVT::i64) 1466 NotC2 &= (1ULL << MVT::getSizeInBits(VT))-1; 1467 1468 if (MaskedValueIsZero(N1, NotC2, TLI)) 1469 return N1; // if (X & ~C2) -> 0, the and is redundant 1470 } 1471 1472 // FIXME: Should add a corresponding version of this for 1473 // ZERO_EXTEND/SIGN_EXTEND by converting them to an ANY_EXTEND node which 1474 // we don't have yet. 1475 // FIXME: NOW WE DO, add this. 1476 1477 // and (sign_extend_inreg x:16:32), 1 -> and x, 1 1478 if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) { 1479 // If we are masking out the part of our input that was extended, just 1480 // mask the input to the extension directly. 1481 unsigned ExtendBits = 1482 MVT::getSizeInBits(cast<VTSDNode>(N1.getOperand(1))->getVT()); 1483 if ((C2 & (~0ULL << ExtendBits)) == 0) 1484 return getNode(ISD::AND, VT, N1.getOperand(0), N2); 1485 } else if (N1.getOpcode() == ISD::OR) { 1486 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N1.getOperand(1))) 1487 if ((ORI->getValue() & C2) == C2) { 1488 // If the 'or' is setting all of the bits that we are masking for, 1489 // we know the result of the AND will be the AND mask itself. 1490 return N2; 1491 } 1492 } 1493 break; 1494 case ISD::OR: 1495 if (!C2)return N1; // X or 0 -> X 1496 if (N2C->isAllOnesValue()) 1497 return N2; // X or -1 -> -1 1498 break; 1499 case ISD::XOR: 1500 if (!C2) return N1; // X xor 0 -> X 1501 if (N2C->getValue() == 1 && N1.Val->getOpcode() == ISD::SETCC) { 1502 SDNode *SetCC = N1.Val; 1503 // !(X op Y) -> (X !op Y) 1504 bool isInteger = MVT::isInteger(SetCC->getOperand(0).getValueType()); 1505 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC->getOperand(2))->get(); 1506 return getSetCC(SetCC->getValueType(0), 1507 SetCC->getOperand(0), SetCC->getOperand(1), 1508 ISD::getSetCCInverse(CC, isInteger)); 1509 } else if (N2C->isAllOnesValue()) { 1510 if (N1.getOpcode() == ISD::AND || N1.getOpcode() == ISD::OR) { 1511 SDNode *Op = N1.Val; 1512 // !(X or Y) -> (!X and !Y) iff X or Y are freely invertible 1513 // !(X and Y) -> (!X or !Y) iff X or Y are freely invertible 1514 SDOperand LHS = Op->getOperand(0), RHS = Op->getOperand(1); 1515 if (isInvertibleForFree(RHS) || isInvertibleForFree(LHS)) { 1516 LHS = getNode(ISD::XOR, VT, LHS, N2); // RHS = ~LHS 1517 RHS = getNode(ISD::XOR, VT, RHS, N2); // RHS = ~RHS 1518 if (Op->getOpcode() == ISD::AND) 1519 return getNode(ISD::OR, VT, LHS, RHS); 1520 return getNode(ISD::AND, VT, LHS, RHS); 1521 } 1522 } 1523 // X xor -1 -> not(x) ? 1524 } 1525 break; 1526 } 1527 1528 // Reassociate ((X op C1) op C2) if possible. 1529 if (N1.getOpcode() == Opcode && isAssociativeBinOp(Opcode)) 1530 if (ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N1.Val->getOperand(1))) 1531 return getNode(Opcode, VT, N1.Val->getOperand(0), 1532 getNode(Opcode, VT, N2, N1.Val->getOperand(1))); 1533 } 1534 } 1535 1536 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1.Val); 1537 ConstantFPSDNode *N2CFP = dyn_cast<ConstantFPSDNode>(N2.Val); 1538 if (N1CFP) { 1539 if (N2CFP) { 1540 double C1 = N1CFP->getValue(), C2 = N2CFP->getValue(); 1541 switch (Opcode) { 1542 case ISD::FADD: return getConstantFP(C1 + C2, VT); 1543 case ISD::FSUB: return getConstantFP(C1 - C2, VT); 1544 case ISD::FMUL: return getConstantFP(C1 * C2, VT); 1545 case ISD::FDIV: 1546 if (C2) return getConstantFP(C1 / C2, VT); 1547 break; 1548 case ISD::FREM : 1549 if (C2) return getConstantFP(fmod(C1, C2), VT); 1550 break; 1551 default: break; 1552 } 1553 } else { // Cannonicalize constant to RHS if commutative 1554 if (isCommutativeBinOp(Opcode)) { 1555 std::swap(N1CFP, N2CFP); 1556 std::swap(N1, N2); 1557 } 1558 } 1559 1560 if (!CombinerEnabled) { 1561 if (Opcode == ISD::FP_ROUND_INREG) 1562 return getNode(ISD::FP_EXTEND, VT, 1563 getNode(ISD::FP_ROUND, cast<VTSDNode>(N2)->getVT(), N1)); 1564 } 1565 } 1566 1567 // Finally, fold operations that do not require constants. 1568 switch (Opcode) { 1569 case ISD::TokenFactor: 1570 if (!CombinerEnabled) { 1571 if (N1.getOpcode() == ISD::EntryToken) 1572 return N2; 1573 if (N2.getOpcode() == ISD::EntryToken) 1574 return N1; 1575 } 1576 break; 1577 case ISD::SDIV: { 1578 if (CombinerEnabled) break; 1579 1580 // If we know the sign bits of both operands are zero, strength reduce to a 1581 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1582 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1); 1583 if (MaskedValueIsZero(N2, SignBit, TLI) && 1584 MaskedValueIsZero(N1, SignBit, TLI)) 1585 return getNode(ISD::UDIV, VT, N1, N2); 1586 break; 1587 } 1588 1589 case ISD::AND: 1590 case ISD::OR: 1591 if (!CombinerEnabled) { 1592 if (N1.Val->getOpcode() == ISD::SETCC && N2.Val->getOpcode() == ISD::SETCC){ 1593 SDNode *LHS = N1.Val, *RHS = N2.Val; 1594 SDOperand LL = LHS->getOperand(0), RL = RHS->getOperand(0); 1595 SDOperand LR = LHS->getOperand(1), RR = RHS->getOperand(1); 1596 ISD::CondCode Op1 = cast<CondCodeSDNode>(LHS->getOperand(2))->get(); 1597 ISD::CondCode Op2 = cast<CondCodeSDNode>(RHS->getOperand(2))->get(); 1598 1599 if (LR == RR && isa<ConstantSDNode>(LR) && 1600 Op2 == Op1 && MVT::isInteger(LL.getValueType())) { 1601 // (X != 0) | (Y != 0) -> (X|Y != 0) 1602 // (X == 0) & (Y == 0) -> (X|Y == 0) 1603 // (X < 0) | (Y < 0) -> (X|Y < 0) 1604 if (cast<ConstantSDNode>(LR)->getValue() == 0 && 1605 ((Op2 == ISD::SETEQ && Opcode == ISD::AND) || 1606 (Op2 == ISD::SETNE && Opcode == ISD::OR) || 1607 (Op2 == ISD::SETLT && Opcode == ISD::OR))) 1608 return getSetCC(VT, getNode(ISD::OR, LR.getValueType(), LL, RL), LR, 1609 Op2); 1610 1611 if (cast<ConstantSDNode>(LR)->isAllOnesValue()) { 1612 // (X == -1) & (Y == -1) -> (X&Y == -1) 1613 // (X != -1) | (Y != -1) -> (X&Y != -1) 1614 // (X > -1) | (Y > -1) -> (X&Y > -1) 1615 if ((Opcode == ISD::AND && Op2 == ISD::SETEQ) || 1616 (Opcode == ISD::OR && Op2 == ISD::SETNE) || 1617 (Opcode == ISD::OR && Op2 == ISD::SETGT)) 1618 return getSetCC(VT, getNode(ISD::AND, LR.getValueType(), LL, RL), 1619 LR, Op2); 1620 // (X > -1) & (Y > -1) -> (X|Y > -1) 1621 if (Opcode == ISD::AND && Op2 == ISD::SETGT) 1622 return getSetCC(VT, getNode(ISD::OR, LR.getValueType(), LL, RL), 1623 LR, Op2); 1624 } 1625 } 1626 1627 // (X op1 Y) | (Y op2 X) -> (X op1 Y) | (X swapop2 Y) 1628 if (LL == RR && LR == RL) { 1629 Op2 = ISD::getSetCCSwappedOperands(Op2); 1630 goto MatchedBackwards; 1631 } 1632 1633 if (LL == RL && LR == RR) { 1634 MatchedBackwards: 1635 ISD::CondCode Result; 1636 bool isInteger = MVT::isInteger(LL.getValueType()); 1637 if (Opcode == ISD::OR) 1638 Result = ISD::getSetCCOrOperation(Op1, Op2, isInteger); 1639 else 1640 Result = ISD::getSetCCAndOperation(Op1, Op2, isInteger); 1641 1642 if (Result != ISD::SETCC_INVALID) 1643 return getSetCC(LHS->getValueType(0), LL, LR, Result); 1644 } 1645 } 1646 1647 // and/or zext(a), zext(b) -> zext(and/or a, b) 1648 if (N1.getOpcode() == ISD::ZERO_EXTEND && 1649 N2.getOpcode() == ISD::ZERO_EXTEND && 1650 N1.getOperand(0).getValueType() == N2.getOperand(0).getValueType()) 1651 return getNode(ISD::ZERO_EXTEND, VT, 1652 getNode(Opcode, N1.getOperand(0).getValueType(), 1653 N1.getOperand(0), N2.getOperand(0))); 1654 } 1655 break; 1656 case ISD::XOR: 1657 if (!CombinerEnabled) { 1658 if (N1 == N2) return getConstant(0, VT); // xor X, Y -> 0 1659 } 1660 break; 1661 case ISD::ADD: 1662 if (!CombinerEnabled) { 1663 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 1664 cast<ConstantSDNode>(N1.getOperand(0))->getValue() == 0) 1665 return getNode(ISD::SUB, VT, N2, N1.getOperand(1)); // (0-A)+B -> B-A 1666 if (N2.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N2.getOperand(0)) && 1667 cast<ConstantSDNode>(N2.getOperand(0))->getValue() == 0) 1668 return getNode(ISD::SUB, VT, N1, N2.getOperand(1)); // A+(0-B) -> A-B 1669 if (N2.getOpcode() == ISD::SUB && N1 == N2.Val->getOperand(1)) 1670 return N2.Val->getOperand(0); // A+(B-A) -> B 1671 } 1672 break; 1673 case ISD::FADD: 1674 if (!CombinerEnabled) { 1675 if (N2.getOpcode() == ISD::FNEG) // (A+ (-B) -> A-B 1676 return getNode(ISD::FSUB, VT, N1, N2.getOperand(0)); 1677 if (N1.getOpcode() == ISD::FNEG) // ((-A)+B) -> B-A 1678 return getNode(ISD::FSUB, VT, N2, N1.getOperand(0)); 1679 } 1680 break; 1681 1682 case ISD::SUB: 1683 if (!CombinerEnabled) { 1684 if (N1.getOpcode() == ISD::ADD) { 1685 if (N1.Val->getOperand(0) == N2) 1686 return N1.Val->getOperand(1); // (A+B)-A == B 1687 if (N1.Val->getOperand(1) == N2) 1688 return N1.Val->getOperand(0); // (A+B)-B == A 1689 } 1690 } 1691 break; 1692 case ISD::FSUB: 1693 if (!CombinerEnabled) { 1694 if (N2.getOpcode() == ISD::FNEG) // (A- (-B) -> A+B 1695 return getNode(ISD::FADD, VT, N1, N2.getOperand(0)); 1696 } 1697 break; 1698 case ISD::FP_ROUND_INREG: 1699 if (cast<VTSDNode>(N2)->getVT() == VT) return N1; // Not actually rounding. 1700 break; 1701 case ISD::SIGN_EXTEND_INREG: { 1702 MVT::ValueType EVT = cast<VTSDNode>(N2)->getVT(); 1703 if (EVT == VT) return N1; // Not actually extending 1704 if (!CombinerEnabled) { 1705 // If we are sign extending an extension, use the original source. 1706 if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG || 1707 N1.getOpcode() == ISD::AssertSext) 1708 if (cast<VTSDNode>(N1.getOperand(1))->getVT() <= EVT) 1709 return N1; 1710 1711 // If we are sign extending a sextload, return just the load. 1712 if (N1.getOpcode() == ISD::SEXTLOAD) 1713 if (cast<VTSDNode>(N1.getOperand(3))->getVT() <= EVT) 1714 return N1; 1715 1716 // If we are extending the result of a setcc, and we already know the 1717 // contents of the top bits, eliminate the extension. 1718 if (N1.getOpcode() == ISD::SETCC && 1719 TLI.getSetCCResultContents() == 1720 TargetLowering::ZeroOrNegativeOneSetCCResult) 1721 return N1; 1722 1723 // If we are sign extending the result of an (and X, C) operation, and we 1724 // know the extended bits are zeros already, don't do the extend. 1725 if (N1.getOpcode() == ISD::AND) 1726 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getOperand(1))) { 1727 uint64_t Mask = N1C->getValue(); 1728 unsigned NumBits = MVT::getSizeInBits(EVT); 1729 if ((Mask & (~0ULL << (NumBits-1))) == 0) 1730 return N1; 1731 } 1732 } 1733 break; 1734 } 1735 1736 // FIXME: figure out how to safely handle things like 1737 // int foo(int x) { return 1 << (x & 255); } 1738 // int bar() { return foo(256); } 1739#if 0 1740 case ISD::SHL: 1741 case ISD::SRL: 1742 case ISD::SRA: 1743 if (N2.getOpcode() == ISD::SIGN_EXTEND_INREG && 1744 cast<VTSDNode>(N2.getOperand(1))->getVT() != MVT::i1) 1745 return getNode(Opcode, VT, N1, N2.getOperand(0)); 1746 else if (N2.getOpcode() == ISD::AND) 1747 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(N2.getOperand(1))) { 1748 // If the and is only masking out bits that cannot effect the shift, 1749 // eliminate the and. 1750 unsigned NumBits = MVT::getSizeInBits(VT); 1751 if ((AndRHS->getValue() & (NumBits-1)) == NumBits-1) 1752 return getNode(Opcode, VT, N1, N2.getOperand(0)); 1753 } 1754 break; 1755#endif 1756 } 1757 1758 // Memoize this node if possible. 1759 SDNode *N; 1760 if (Opcode != ISD::CALLSEQ_START && Opcode != ISD::CALLSEQ_END && 1761 VT != MVT::Flag) { 1762 SDNode *&BON = BinaryOps[std::make_pair(Opcode, std::make_pair(N1, N2))]; 1763 if (BON) return SDOperand(BON, 0); 1764 1765 BON = N = new SDNode(Opcode, N1, N2); 1766 } else { 1767 N = new SDNode(Opcode, N1, N2); 1768 } 1769 1770 N->setValueTypes(VT); 1771 AllNodes.push_back(N); 1772 return SDOperand(N, 0); 1773} 1774 1775// setAdjCallChain - This method changes the token chain of an 1776// CALLSEQ_START/END node to be the specified operand. 1777void SDNode::setAdjCallChain(SDOperand N) { 1778 assert(N.getValueType() == MVT::Other); 1779 assert((getOpcode() == ISD::CALLSEQ_START || 1780 getOpcode() == ISD::CALLSEQ_END) && "Cannot adjust this node!"); 1781 1782 Operands[0].Val->removeUser(this); 1783 Operands[0] = N; 1784 N.Val->Uses.push_back(this); 1785} 1786 1787 1788 1789SDOperand SelectionDAG::getLoad(MVT::ValueType VT, 1790 SDOperand Chain, SDOperand Ptr, 1791 SDOperand SV) { 1792 SDNode *&N = Loads[std::make_pair(Ptr, std::make_pair(Chain, VT))]; 1793 if (N) return SDOperand(N, 0); 1794 N = new SDNode(ISD::LOAD, Chain, Ptr, SV); 1795 1796 // Loads have a token chain. 1797 N->setValueTypes(VT, MVT::Other); 1798 AllNodes.push_back(N); 1799 return SDOperand(N, 0); 1800} 1801 1802 1803SDOperand SelectionDAG::getExtLoad(unsigned Opcode, MVT::ValueType VT, 1804 SDOperand Chain, SDOperand Ptr, SDOperand SV, 1805 MVT::ValueType EVT) { 1806 std::vector<SDOperand> Ops; 1807 Ops.reserve(4); 1808 Ops.push_back(Chain); 1809 Ops.push_back(Ptr); 1810 Ops.push_back(SV); 1811 Ops.push_back(getValueType(EVT)); 1812 std::vector<MVT::ValueType> VTs; 1813 VTs.reserve(2); 1814 VTs.push_back(VT); VTs.push_back(MVT::Other); // Add token chain. 1815 return getNode(Opcode, VTs, Ops); 1816} 1817 1818SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, 1819 SDOperand N1, SDOperand N2, SDOperand N3) { 1820 // Perform various simplifications. 1821 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1822 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 1823 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val); 1824 switch (Opcode) { 1825 case ISD::SETCC: { 1826 // Use SimplifySetCC to simplify SETCC's. 1827 SDOperand Simp = SimplifySetCC(VT, N1, N2, cast<CondCodeSDNode>(N3)->get()); 1828 if (Simp.Val) return Simp; 1829 break; 1830 } 1831 case ISD::SELECT: 1832 if (N1C) 1833 if (N1C->getValue()) 1834 return N2; // select true, X, Y -> X 1835 else 1836 return N3; // select false, X, Y -> Y 1837 1838 if (N2 == N3) return N2; // select C, X, X -> X 1839 1840 if (!CombinerEnabled) { 1841 if (VT == MVT::i1) { // Boolean SELECT 1842 if (N2C) { 1843 if (N2C->getValue()) // select C, 1, X -> C | X 1844 return getNode(ISD::OR, VT, N1, N3); 1845 else // select C, 0, X -> ~C & X 1846 return getNode(ISD::AND, VT, 1847 getNode(ISD::XOR, N1.getValueType(), N1, 1848 getConstant(1, N1.getValueType())), N3); 1849 } else if (N3C) { 1850 if (N3C->getValue()) // select C, X, 1 -> ~C | X 1851 return getNode(ISD::OR, VT, 1852 getNode(ISD::XOR, N1.getValueType(), N1, 1853 getConstant(1, N1.getValueType())), N2); 1854 else // select C, X, 0 -> C & X 1855 return getNode(ISD::AND, VT, N1, N2); 1856 } 1857 1858 if (N1 == N2) // X ? X : Y --> X ? 1 : Y --> X | Y 1859 return getNode(ISD::OR, VT, N1, N3); 1860 if (N1 == N3) // X ? Y : X --> X ? Y : 0 --> X & Y 1861 return getNode(ISD::AND, VT, N1, N2); 1862 } 1863 if (N1.getOpcode() == ISD::SETCC) { 1864 SDOperand Simp = SimplifySelectCC(N1.getOperand(0), N1.getOperand(1), N2, 1865 N3, cast<CondCodeSDNode>(N1.getOperand(2))->get()); 1866 if (Simp.Val) return Simp; 1867 } 1868 } 1869 break; 1870 case ISD::BRCOND: 1871 if (N2C) 1872 if (N2C->getValue()) // Unconditional branch 1873 return getNode(ISD::BR, MVT::Other, N1, N3); 1874 else 1875 return N1; // Never-taken branch 1876 break; 1877 } 1878 1879 std::vector<SDOperand> Ops; 1880 Ops.reserve(3); 1881 Ops.push_back(N1); 1882 Ops.push_back(N2); 1883 Ops.push_back(N3); 1884 1885 // Memoize node if it doesn't produce a flag. 1886 SDNode *N; 1887 if (VT != MVT::Flag) { 1888 SDNode *&E = OneResultNodes[std::make_pair(Opcode,std::make_pair(VT, Ops))]; 1889 if (E) return SDOperand(E, 0); 1890 E = N = new SDNode(Opcode, N1, N2, N3); 1891 } else { 1892 N = new SDNode(Opcode, N1, N2, N3); 1893 } 1894 N->setValueTypes(VT); 1895 AllNodes.push_back(N); 1896 return SDOperand(N, 0); 1897} 1898 1899SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, 1900 SDOperand N1, SDOperand N2, SDOperand N3, 1901 SDOperand N4) { 1902 std::vector<SDOperand> Ops; 1903 Ops.reserve(4); 1904 Ops.push_back(N1); 1905 Ops.push_back(N2); 1906 Ops.push_back(N3); 1907 Ops.push_back(N4); 1908 return getNode(Opcode, VT, Ops); 1909} 1910 1911SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, 1912 SDOperand N1, SDOperand N2, SDOperand N3, 1913 SDOperand N4, SDOperand N5) { 1914 std::vector<SDOperand> Ops; 1915 Ops.reserve(5); 1916 Ops.push_back(N1); 1917 Ops.push_back(N2); 1918 Ops.push_back(N3); 1919 Ops.push_back(N4); 1920 Ops.push_back(N5); 1921 return getNode(Opcode, VT, Ops); 1922} 1923 1924 1925SDOperand SelectionDAG::getSrcValue(const Value *V, int Offset) { 1926 assert((!V || isa<PointerType>(V->getType())) && 1927 "SrcValue is not a pointer?"); 1928 SDNode *&N = ValueNodes[std::make_pair(V, Offset)]; 1929 if (N) return SDOperand(N, 0); 1930 1931 N = new SrcValueSDNode(V, Offset); 1932 AllNodes.push_back(N); 1933 return SDOperand(N, 0); 1934} 1935 1936SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, 1937 std::vector<SDOperand> &Ops) { 1938 switch (Ops.size()) { 1939 case 0: return getNode(Opcode, VT); 1940 case 1: return getNode(Opcode, VT, Ops[0]); 1941 case 2: return getNode(Opcode, VT, Ops[0], Ops[1]); 1942 case 3: return getNode(Opcode, VT, Ops[0], Ops[1], Ops[2]); 1943 default: break; 1944 } 1945 1946 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Ops[1].Val); 1947 switch (Opcode) { 1948 default: break; 1949 case ISD::BRCONDTWOWAY: 1950 if (N1C) 1951 if (N1C->getValue()) // Unconditional branch to true dest. 1952 return getNode(ISD::BR, MVT::Other, Ops[0], Ops[2]); 1953 else // Unconditional branch to false dest. 1954 return getNode(ISD::BR, MVT::Other, Ops[0], Ops[3]); 1955 break; 1956 case ISD::BRTWOWAY_CC: 1957 assert(Ops.size() == 6 && "BRTWOWAY_CC takes 6 operands!"); 1958 assert(Ops[2].getValueType() == Ops[3].getValueType() && 1959 "LHS and RHS of comparison must have same type!"); 1960 break; 1961 case ISD::TRUNCSTORE: { 1962 assert(Ops.size() == 5 && "TRUNCSTORE takes 5 operands!"); 1963 MVT::ValueType EVT = cast<VTSDNode>(Ops[4])->getVT(); 1964#if 0 // FIXME: If the target supports EVT natively, convert to a truncate/store 1965 // If this is a truncating store of a constant, convert to the desired type 1966 // and store it instead. 1967 if (isa<Constant>(Ops[0])) { 1968 SDOperand Op = getNode(ISD::TRUNCATE, EVT, N1); 1969 if (isa<Constant>(Op)) 1970 N1 = Op; 1971 } 1972 // Also for ConstantFP? 1973#endif 1974 if (Ops[0].getValueType() == EVT) // Normal store? 1975 return getNode(ISD::STORE, VT, Ops[0], Ops[1], Ops[2], Ops[3]); 1976 assert(Ops[1].getValueType() > EVT && "Not a truncation?"); 1977 assert(MVT::isInteger(Ops[1].getValueType()) == MVT::isInteger(EVT) && 1978 "Can't do FP-INT conversion!"); 1979 break; 1980 } 1981 case ISD::SELECT_CC: { 1982 assert(Ops.size() == 5 && "SELECT_CC takes 5 operands!"); 1983 assert(Ops[0].getValueType() == Ops[1].getValueType() && 1984 "LHS and RHS of condition must have same type!"); 1985 assert(Ops[2].getValueType() == Ops[3].getValueType() && 1986 "True and False arms of SelectCC must have same type!"); 1987 assert(Ops[2].getValueType() == VT && 1988 "select_cc node must be of same type as true and false value!"); 1989 SDOperand Simp = SimplifySelectCC(Ops[0], Ops[1], Ops[2], Ops[3], 1990 cast<CondCodeSDNode>(Ops[4])->get()); 1991 if (Simp.Val) return Simp; 1992 break; 1993 } 1994 case ISD::BR_CC: { 1995 assert(Ops.size() == 5 && "BR_CC takes 5 operands!"); 1996 assert(Ops[2].getValueType() == Ops[3].getValueType() && 1997 "LHS/RHS of comparison should match types!"); 1998 1999 if (CombinerEnabled) break; // xforms moved to dag combine. 2000 2001 // Use SimplifySetCC to simplify SETCC's. 2002 SDOperand Simp = SimplifySetCC(MVT::i1, Ops[2], Ops[3], 2003 cast<CondCodeSDNode>(Ops[1])->get()); 2004 if (Simp.Val) { 2005 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Simp)) { 2006 if (C->getValue() & 1) // Unconditional branch 2007 return getNode(ISD::BR, MVT::Other, Ops[0], Ops[4]); 2008 else 2009 return Ops[0]; // Unconditional Fall through 2010 } else if (Simp.Val->getOpcode() == ISD::SETCC) { 2011 Ops[2] = Simp.getOperand(0); 2012 Ops[3] = Simp.getOperand(1); 2013 Ops[1] = Simp.getOperand(2); 2014 } 2015 } 2016 break; 2017 } 2018 } 2019 2020 // Memoize nodes. 2021 SDNode *N; 2022 if (VT != MVT::Flag) { 2023 SDNode *&E = 2024 OneResultNodes[std::make_pair(Opcode, std::make_pair(VT, Ops))]; 2025 if (E) return SDOperand(E, 0); 2026 E = N = new SDNode(Opcode, Ops); 2027 } else { 2028 N = new SDNode(Opcode, Ops); 2029 } 2030 N->setValueTypes(VT); 2031 AllNodes.push_back(N); 2032 return SDOperand(N, 0); 2033} 2034 2035SDOperand SelectionDAG::getNode(unsigned Opcode, 2036 std::vector<MVT::ValueType> &ResultTys, 2037 std::vector<SDOperand> &Ops) { 2038 if (ResultTys.size() == 1) 2039 return getNode(Opcode, ResultTys[0], Ops); 2040 2041 switch (Opcode) { 2042 case ISD::EXTLOAD: 2043 case ISD::SEXTLOAD: 2044 case ISD::ZEXTLOAD: { 2045 MVT::ValueType EVT = cast<VTSDNode>(Ops[3])->getVT(); 2046 assert(Ops.size() == 4 && ResultTys.size() == 2 && "Bad *EXTLOAD!"); 2047 // If they are asking for an extending load from/to the same thing, return a 2048 // normal load. 2049 if (ResultTys[0] == EVT) 2050 return getLoad(ResultTys[0], Ops[0], Ops[1], Ops[2]); 2051 assert(EVT < ResultTys[0] && 2052 "Should only be an extending load, not truncating!"); 2053 assert((Opcode == ISD::EXTLOAD || MVT::isInteger(ResultTys[0])) && 2054 "Cannot sign/zero extend a FP load!"); 2055 assert(MVT::isInteger(ResultTys[0]) == MVT::isInteger(EVT) && 2056 "Cannot convert from FP to Int or Int -> FP!"); 2057 break; 2058 } 2059 2060 // FIXME: figure out how to safely handle things like 2061 // int foo(int x) { return 1 << (x & 255); } 2062 // int bar() { return foo(256); } 2063#if 0 2064 case ISD::SRA_PARTS: 2065 case ISD::SRL_PARTS: 2066 case ISD::SHL_PARTS: 2067 if (N3.getOpcode() == ISD::SIGN_EXTEND_INREG && 2068 cast<VTSDNode>(N3.getOperand(1))->getVT() != MVT::i1) 2069 return getNode(Opcode, VT, N1, N2, N3.getOperand(0)); 2070 else if (N3.getOpcode() == ISD::AND) 2071 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(N3.getOperand(1))) { 2072 // If the and is only masking out bits that cannot effect the shift, 2073 // eliminate the and. 2074 unsigned NumBits = MVT::getSizeInBits(VT)*2; 2075 if ((AndRHS->getValue() & (NumBits-1)) == NumBits-1) 2076 return getNode(Opcode, VT, N1, N2, N3.getOperand(0)); 2077 } 2078 break; 2079#endif 2080 } 2081 2082 // Memoize the node unless it returns a flag. 2083 SDNode *N; 2084 if (ResultTys.back() != MVT::Flag) { 2085 SDNode *&E = 2086 ArbitraryNodes[std::make_pair(Opcode, std::make_pair(ResultTys, Ops))]; 2087 if (E) return SDOperand(E, 0); 2088 E = N = new SDNode(Opcode, Ops); 2089 } else { 2090 N = new SDNode(Opcode, Ops); 2091 } 2092 N->setValueTypes(ResultTys); 2093 AllNodes.push_back(N); 2094 return SDOperand(N, 0); 2095} 2096 2097 2098/// SelectNodeTo - These are used for target selectors to *mutate* the 2099/// specified node to have the specified return type, Target opcode, and 2100/// operands. Note that target opcodes are stored as 2101/// ISD::BUILTIN_OP_END+TargetOpcode in the node opcode field. 2102void SelectionDAG::SelectNodeTo(SDNode *N, unsigned TargetOpc, 2103 MVT::ValueType VT) { 2104 RemoveNodeFromCSEMaps(N); 2105 N->MorphNodeTo(ISD::BUILTIN_OP_END+TargetOpc); 2106 N->setValueTypes(VT); 2107} 2108void SelectionDAG::SelectNodeTo(SDNode *N, unsigned TargetOpc, 2109 MVT::ValueType VT, SDOperand Op1) { 2110 RemoveNodeFromCSEMaps(N); 2111 N->MorphNodeTo(ISD::BUILTIN_OP_END+TargetOpc); 2112 N->setValueTypes(VT); 2113 N->setOperands(Op1); 2114} 2115void SelectionDAG::SelectNodeTo(SDNode *N, unsigned TargetOpc, 2116 MVT::ValueType VT, SDOperand Op1, 2117 SDOperand Op2) { 2118 RemoveNodeFromCSEMaps(N); 2119 N->MorphNodeTo(ISD::BUILTIN_OP_END+TargetOpc); 2120 N->setValueTypes(VT); 2121 N->setOperands(Op1, Op2); 2122} 2123void SelectionDAG::SelectNodeTo(SDNode *N, unsigned TargetOpc, 2124 MVT::ValueType VT1, MVT::ValueType VT2, 2125 SDOperand Op1, SDOperand Op2) { 2126 RemoveNodeFromCSEMaps(N); 2127 N->MorphNodeTo(ISD::BUILTIN_OP_END+TargetOpc); 2128 N->setValueTypes(VT1, VT2); 2129 N->setOperands(Op1, Op2); 2130} 2131void SelectionDAG::SelectNodeTo(SDNode *N, unsigned TargetOpc, 2132 MVT::ValueType VT, SDOperand Op1, 2133 SDOperand Op2, SDOperand Op3) { 2134 RemoveNodeFromCSEMaps(N); 2135 N->MorphNodeTo(ISD::BUILTIN_OP_END+TargetOpc); 2136 N->setValueTypes(VT); 2137 N->setOperands(Op1, Op2, Op3); 2138} 2139void SelectionDAG::SelectNodeTo(SDNode *N, unsigned TargetOpc, 2140 MVT::ValueType VT1, MVT::ValueType VT2, 2141 SDOperand Op1, SDOperand Op2, SDOperand Op3) { 2142 RemoveNodeFromCSEMaps(N); 2143 N->MorphNodeTo(ISD::BUILTIN_OP_END+TargetOpc); 2144 N->setValueTypes(VT1, VT2); 2145 N->setOperands(Op1, Op2, Op3); 2146} 2147 2148void SelectionDAG::SelectNodeTo(SDNode *N, unsigned TargetOpc, 2149 MVT::ValueType VT, SDOperand Op1, 2150 SDOperand Op2, SDOperand Op3, SDOperand Op4) { 2151 RemoveNodeFromCSEMaps(N); 2152 N->MorphNodeTo(ISD::BUILTIN_OP_END+TargetOpc); 2153 N->setValueTypes(VT); 2154 N->setOperands(Op1, Op2, Op3, Op4); 2155} 2156void SelectionDAG::SelectNodeTo(SDNode *N, unsigned TargetOpc, 2157 MVT::ValueType VT, SDOperand Op1, 2158 SDOperand Op2, SDOperand Op3, SDOperand Op4, 2159 SDOperand Op5) { 2160 RemoveNodeFromCSEMaps(N); 2161 N->MorphNodeTo(ISD::BUILTIN_OP_END+TargetOpc); 2162 N->setValueTypes(VT); 2163 N->setOperands(Op1, Op2, Op3, Op4, Op5); 2164} 2165 2166/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. 2167/// This can cause recursive merging of nodes in the DAG. 2168/// 2169/// This version assumes From/To have a single result value. 2170/// 2171void SelectionDAG::ReplaceAllUsesWith(SDOperand FromN, SDOperand ToN, 2172 std::vector<SDNode*> *Deleted) { 2173 SDNode *From = FromN.Val, *To = ToN.Val; 2174 assert(From->getNumValues() == 1 && To->getNumValues() == 1 && 2175 "Cannot replace with this method!"); 2176 assert(From != To && "Cannot replace uses of with self"); 2177 2178 while (!From->use_empty()) { 2179 // Process users until they are all gone. 2180 SDNode *U = *From->use_begin(); 2181 2182 // This node is about to morph, remove its old self from the CSE maps. 2183 RemoveNodeFromCSEMaps(U); 2184 2185 for (unsigned i = 0, e = U->getNumOperands(); i != e; ++i) 2186 if (U->getOperand(i).Val == From) { 2187 From->removeUser(U); 2188 U->Operands[i].Val = To; 2189 To->addUser(U); 2190 } 2191 2192 // Now that we have modified U, add it back to the CSE maps. If it already 2193 // exists there, recursively merge the results together. 2194 if (SDNode *Existing = AddNonLeafNodeToCSEMaps(U)) { 2195 ReplaceAllUsesWith(U, Existing, Deleted); 2196 // U is now dead. 2197 if (Deleted) Deleted->push_back(U); 2198 DeleteNodeNotInCSEMaps(U); 2199 } 2200 } 2201} 2202 2203/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. 2204/// This can cause recursive merging of nodes in the DAG. 2205/// 2206/// This version assumes From/To have matching types and numbers of result 2207/// values. 2208/// 2209void SelectionDAG::ReplaceAllUsesWith(SDNode *From, SDNode *To, 2210 std::vector<SDNode*> *Deleted) { 2211 assert(From != To && "Cannot replace uses of with self"); 2212 assert(From->getNumValues() == To->getNumValues() && 2213 "Cannot use this version of ReplaceAllUsesWith!"); 2214 if (From->getNumValues() == 1) { // If possible, use the faster version. 2215 ReplaceAllUsesWith(SDOperand(From, 0), SDOperand(To, 0), Deleted); 2216 return; 2217 } 2218 2219 while (!From->use_empty()) { 2220 // Process users until they are all gone. 2221 SDNode *U = *From->use_begin(); 2222 2223 // This node is about to morph, remove its old self from the CSE maps. 2224 RemoveNodeFromCSEMaps(U); 2225 2226 for (unsigned i = 0, e = U->getNumOperands(); i != e; ++i) 2227 if (U->getOperand(i).Val == From) { 2228 From->removeUser(U); 2229 U->Operands[i].Val = To; 2230 To->addUser(U); 2231 } 2232 2233 // Now that we have modified U, add it back to the CSE maps. If it already 2234 // exists there, recursively merge the results together. 2235 if (SDNode *Existing = AddNonLeafNodeToCSEMaps(U)) { 2236 ReplaceAllUsesWith(U, Existing, Deleted); 2237 // U is now dead. 2238 if (Deleted) Deleted->push_back(U); 2239 DeleteNodeNotInCSEMaps(U); 2240 } 2241 } 2242} 2243 2244/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. 2245/// This can cause recursive merging of nodes in the DAG. 2246/// 2247/// This version can replace From with any result values. To must match the 2248/// number and types of values returned by From. 2249void SelectionDAG::ReplaceAllUsesWith(SDNode *From, 2250 const std::vector<SDOperand> &To, 2251 std::vector<SDNode*> *Deleted) { 2252 assert(From->getNumValues() == To.size() && 2253 "Incorrect number of values to replace with!"); 2254 if (To.size() == 1 && To[0].Val->getNumValues() == 1) { 2255 // Degenerate case handled above. 2256 ReplaceAllUsesWith(SDOperand(From, 0), To[0], Deleted); 2257 return; 2258 } 2259 2260 while (!From->use_empty()) { 2261 // Process users until they are all gone. 2262 SDNode *U = *From->use_begin(); 2263 2264 // This node is about to morph, remove its old self from the CSE maps. 2265 RemoveNodeFromCSEMaps(U); 2266 2267 for (unsigned i = 0, e = U->getNumOperands(); i != e; ++i) 2268 if (U->getOperand(i).Val == From) { 2269 const SDOperand &ToOp = To[U->getOperand(i).ResNo]; 2270 From->removeUser(U); 2271 U->Operands[i] = ToOp; 2272 ToOp.Val->addUser(U); 2273 } 2274 2275 // Now that we have modified U, add it back to the CSE maps. If it already 2276 // exists there, recursively merge the results together. 2277 if (SDNode *Existing = AddNonLeafNodeToCSEMaps(U)) { 2278 ReplaceAllUsesWith(U, Existing, Deleted); 2279 // U is now dead. 2280 if (Deleted) Deleted->push_back(U); 2281 DeleteNodeNotInCSEMaps(U); 2282 } 2283 } 2284} 2285 2286 2287//===----------------------------------------------------------------------===// 2288// SDNode Class 2289//===----------------------------------------------------------------------===// 2290 2291/// hasNUsesOfValue - Return true if there are exactly NUSES uses of the 2292/// indicated value. This method ignores uses of other values defined by this 2293/// operation. 2294bool SDNode::hasNUsesOfValue(unsigned NUses, unsigned Value) { 2295 assert(Value < getNumValues() && "Bad value!"); 2296 2297 // If there is only one value, this is easy. 2298 if (getNumValues() == 1) 2299 return use_size() == NUses; 2300 if (Uses.size() < NUses) return false; 2301 2302 SDOperand TheValue(this, Value); 2303 2304 std::set<SDNode*> UsersHandled; 2305 2306 for (std::vector<SDNode*>::iterator UI = Uses.begin(), E = Uses.end(); 2307 UI != E; ++UI) { 2308 SDNode *User = *UI; 2309 if (User->getNumOperands() == 1 || 2310 UsersHandled.insert(User).second) // First time we've seen this? 2311 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 2312 if (User->getOperand(i) == TheValue) { 2313 if (NUses == 0) 2314 return false; // too many uses 2315 --NUses; 2316 } 2317 } 2318 2319 // Found exactly the right number of uses? 2320 return NUses == 0; 2321} 2322 2323 2324const char *SDNode::getOperationName(const SelectionDAG *G) const { 2325 switch (getOpcode()) { 2326 default: 2327 if (getOpcode() < ISD::BUILTIN_OP_END) 2328 return "<<Unknown DAG Node>>"; 2329 else { 2330 if (G) 2331 if (const TargetInstrInfo *TII = G->getTarget().getInstrInfo()) 2332 if (getOpcode()-ISD::BUILTIN_OP_END < TII->getNumOpcodes()) 2333 return TII->getName(getOpcode()-ISD::BUILTIN_OP_END); 2334 return "<<Unknown Target Node>>"; 2335 } 2336 2337 case ISD::PCMARKER: return "PCMarker"; 2338 case ISD::SRCVALUE: return "SrcValue"; 2339 case ISD::VALUETYPE: return "ValueType"; 2340 case ISD::EntryToken: return "EntryToken"; 2341 case ISD::TokenFactor: return "TokenFactor"; 2342 case ISD::AssertSext: return "AssertSext"; 2343 case ISD::AssertZext: return "AssertZext"; 2344 case ISD::Constant: return "Constant"; 2345 case ISD::TargetConstant: return "TargetConstant"; 2346 case ISD::ConstantFP: return "ConstantFP"; 2347 case ISD::GlobalAddress: return "GlobalAddress"; 2348 case ISD::TargetGlobalAddress: return "TargetGlobalAddress"; 2349 case ISD::FrameIndex: return "FrameIndex"; 2350 case ISD::TargetFrameIndex: return "TargetFrameIndex"; 2351 case ISD::BasicBlock: return "BasicBlock"; 2352 case ISD::Register: return "Register"; 2353 case ISD::ExternalSymbol: return "ExternalSymbol"; 2354 case ISD::ConstantPool: return "ConstantPool"; 2355 case ISD::TargetConstantPool: return "TargetConstantPool"; 2356 case ISD::CopyToReg: return "CopyToReg"; 2357 case ISD::CopyFromReg: return "CopyFromReg"; 2358 case ISD::ImplicitDef: return "ImplicitDef"; 2359 case ISD::UNDEF: return "undef"; 2360 2361 // Unary operators 2362 case ISD::FABS: return "fabs"; 2363 case ISD::FNEG: return "fneg"; 2364 case ISD::FSQRT: return "fsqrt"; 2365 case ISD::FSIN: return "fsin"; 2366 case ISD::FCOS: return "fcos"; 2367 2368 // Binary operators 2369 case ISD::ADD: return "add"; 2370 case ISD::SUB: return "sub"; 2371 case ISD::MUL: return "mul"; 2372 case ISD::MULHU: return "mulhu"; 2373 case ISD::MULHS: return "mulhs"; 2374 case ISD::SDIV: return "sdiv"; 2375 case ISD::UDIV: return "udiv"; 2376 case ISD::SREM: return "srem"; 2377 case ISD::UREM: return "urem"; 2378 case ISD::AND: return "and"; 2379 case ISD::OR: return "or"; 2380 case ISD::XOR: return "xor"; 2381 case ISD::SHL: return "shl"; 2382 case ISD::SRA: return "sra"; 2383 case ISD::SRL: return "srl"; 2384 case ISD::FADD: return "fadd"; 2385 case ISD::FSUB: return "fsub"; 2386 case ISD::FMUL: return "fmul"; 2387 case ISD::FDIV: return "fdiv"; 2388 case ISD::FREM: return "frem"; 2389 2390 case ISD::SETCC: return "setcc"; 2391 case ISD::SELECT: return "select"; 2392 case ISD::SELECT_CC: return "select_cc"; 2393 case ISD::ADD_PARTS: return "add_parts"; 2394 case ISD::SUB_PARTS: return "sub_parts"; 2395 case ISD::SHL_PARTS: return "shl_parts"; 2396 case ISD::SRA_PARTS: return "sra_parts"; 2397 case ISD::SRL_PARTS: return "srl_parts"; 2398 2399 // Conversion operators. 2400 case ISD::SIGN_EXTEND: return "sign_extend"; 2401 case ISD::ZERO_EXTEND: return "zero_extend"; 2402 case ISD::ANY_EXTEND: return "any_extend"; 2403 case ISD::SIGN_EXTEND_INREG: return "sign_extend_inreg"; 2404 case ISD::TRUNCATE: return "truncate"; 2405 case ISD::FP_ROUND: return "fp_round"; 2406 case ISD::FP_ROUND_INREG: return "fp_round_inreg"; 2407 case ISD::FP_EXTEND: return "fp_extend"; 2408 2409 case ISD::SINT_TO_FP: return "sint_to_fp"; 2410 case ISD::UINT_TO_FP: return "uint_to_fp"; 2411 case ISD::FP_TO_SINT: return "fp_to_sint"; 2412 case ISD::FP_TO_UINT: return "fp_to_uint"; 2413 2414 // Control flow instructions 2415 case ISD::BR: return "br"; 2416 case ISD::BRCOND: return "brcond"; 2417 case ISD::BRCONDTWOWAY: return "brcondtwoway"; 2418 case ISD::BR_CC: return "br_cc"; 2419 case ISD::BRTWOWAY_CC: return "brtwoway_cc"; 2420 case ISD::RET: return "ret"; 2421 case ISD::CALL: return "call"; 2422 case ISD::TAILCALL:return "tailcall"; 2423 case ISD::CALLSEQ_START: return "callseq_start"; 2424 case ISD::CALLSEQ_END: return "callseq_end"; 2425 2426 // Other operators 2427 case ISD::LOAD: return "load"; 2428 case ISD::STORE: return "store"; 2429 case ISD::EXTLOAD: return "extload"; 2430 case ISD::SEXTLOAD: return "sextload"; 2431 case ISD::ZEXTLOAD: return "zextload"; 2432 case ISD::TRUNCSTORE: return "truncstore"; 2433 2434 case ISD::DYNAMIC_STACKALLOC: return "dynamic_stackalloc"; 2435 case ISD::EXTRACT_ELEMENT: return "extract_element"; 2436 case ISD::BUILD_PAIR: return "build_pair"; 2437 case ISD::MEMSET: return "memset"; 2438 case ISD::MEMCPY: return "memcpy"; 2439 case ISD::MEMMOVE: return "memmove"; 2440 2441 // Bit counting 2442 case ISD::CTPOP: return "ctpop"; 2443 case ISD::CTTZ: return "cttz"; 2444 case ISD::CTLZ: return "ctlz"; 2445 2446 // IO Intrinsics 2447 case ISD::READPORT: return "readport"; 2448 case ISD::WRITEPORT: return "writeport"; 2449 case ISD::READIO: return "readio"; 2450 case ISD::WRITEIO: return "writeio"; 2451 2452 case ISD::CONDCODE: 2453 switch (cast<CondCodeSDNode>(this)->get()) { 2454 default: assert(0 && "Unknown setcc condition!"); 2455 case ISD::SETOEQ: return "setoeq"; 2456 case ISD::SETOGT: return "setogt"; 2457 case ISD::SETOGE: return "setoge"; 2458 case ISD::SETOLT: return "setolt"; 2459 case ISD::SETOLE: return "setole"; 2460 case ISD::SETONE: return "setone"; 2461 2462 case ISD::SETO: return "seto"; 2463 case ISD::SETUO: return "setuo"; 2464 case ISD::SETUEQ: return "setue"; 2465 case ISD::SETUGT: return "setugt"; 2466 case ISD::SETUGE: return "setuge"; 2467 case ISD::SETULT: return "setult"; 2468 case ISD::SETULE: return "setule"; 2469 case ISD::SETUNE: return "setune"; 2470 2471 case ISD::SETEQ: return "seteq"; 2472 case ISD::SETGT: return "setgt"; 2473 case ISD::SETGE: return "setge"; 2474 case ISD::SETLT: return "setlt"; 2475 case ISD::SETLE: return "setle"; 2476 case ISD::SETNE: return "setne"; 2477 } 2478 } 2479} 2480 2481void SDNode::dump() const { dump(0); } 2482void SDNode::dump(const SelectionDAG *G) const { 2483 std::cerr << (void*)this << ": "; 2484 2485 for (unsigned i = 0, e = getNumValues(); i != e; ++i) { 2486 if (i) std::cerr << ","; 2487 if (getValueType(i) == MVT::Other) 2488 std::cerr << "ch"; 2489 else 2490 std::cerr << MVT::getValueTypeString(getValueType(i)); 2491 } 2492 std::cerr << " = " << getOperationName(G); 2493 2494 std::cerr << " "; 2495 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 2496 if (i) std::cerr << ", "; 2497 std::cerr << (void*)getOperand(i).Val; 2498 if (unsigned RN = getOperand(i).ResNo) 2499 std::cerr << ":" << RN; 2500 } 2501 2502 if (const ConstantSDNode *CSDN = dyn_cast<ConstantSDNode>(this)) { 2503 std::cerr << "<" << CSDN->getValue() << ">"; 2504 } else if (const ConstantFPSDNode *CSDN = dyn_cast<ConstantFPSDNode>(this)) { 2505 std::cerr << "<" << CSDN->getValue() << ">"; 2506 } else if (const GlobalAddressSDNode *GADN = 2507 dyn_cast<GlobalAddressSDNode>(this)) { 2508 std::cerr << "<"; 2509 WriteAsOperand(std::cerr, GADN->getGlobal()) << ">"; 2510 } else if (const FrameIndexSDNode *FIDN = dyn_cast<FrameIndexSDNode>(this)) { 2511 std::cerr << "<" << FIDN->getIndex() << ">"; 2512 } else if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(this)){ 2513 std::cerr << "<" << *CP->get() << ">"; 2514 } else if (const BasicBlockSDNode *BBDN = dyn_cast<BasicBlockSDNode>(this)) { 2515 std::cerr << "<"; 2516 const Value *LBB = (const Value*)BBDN->getBasicBlock()->getBasicBlock(); 2517 if (LBB) 2518 std::cerr << LBB->getName() << " "; 2519 std::cerr << (const void*)BBDN->getBasicBlock() << ">"; 2520 } else if (const RegisterSDNode *R = dyn_cast<RegisterSDNode>(this)) { 2521 if (G && MRegisterInfo::isPhysicalRegister(R->getReg())) { 2522 std::cerr << " " <<G->getTarget().getRegisterInfo()->getName(R->getReg()); 2523 } else { 2524 std::cerr << " #" << R->getReg(); 2525 } 2526 } else if (const ExternalSymbolSDNode *ES = 2527 dyn_cast<ExternalSymbolSDNode>(this)) { 2528 std::cerr << "'" << ES->getSymbol() << "'"; 2529 } else if (const SrcValueSDNode *M = dyn_cast<SrcValueSDNode>(this)) { 2530 if (M->getValue()) 2531 std::cerr << "<" << M->getValue() << ":" << M->getOffset() << ">"; 2532 else 2533 std::cerr << "<null:" << M->getOffset() << ">"; 2534 } else if (const VTSDNode *N = dyn_cast<VTSDNode>(this)) { 2535 std::cerr << ":" << getValueTypeString(N->getVT()); 2536 } 2537} 2538 2539static void DumpNodes(SDNode *N, unsigned indent, const SelectionDAG *G) { 2540 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 2541 if (N->getOperand(i).Val->hasOneUse()) 2542 DumpNodes(N->getOperand(i).Val, indent+2, G); 2543 else 2544 std::cerr << "\n" << std::string(indent+2, ' ') 2545 << (void*)N->getOperand(i).Val << ": <multiple use>"; 2546 2547 2548 std::cerr << "\n" << std::string(indent, ' '); 2549 N->dump(G); 2550} 2551 2552void SelectionDAG::dump() const { 2553 std::cerr << "SelectionDAG has " << AllNodes.size() << " nodes:"; 2554 std::vector<SDNode*> Nodes(AllNodes); 2555 std::sort(Nodes.begin(), Nodes.end()); 2556 2557 for (unsigned i = 0, e = Nodes.size(); i != e; ++i) { 2558 if (!Nodes[i]->hasOneUse() && Nodes[i] != getRoot().Val) 2559 DumpNodes(Nodes[i], 2, this); 2560 } 2561 2562 DumpNodes(getRoot().Val, 2, this); 2563 2564 std::cerr << "\n\n"; 2565} 2566 2567