SelectionDAG.cpp revision a60832b0187642d01fd726dc766cd62587f6add0
1//===-- SelectionDAG.cpp - Implement the SelectionDAG data structures -----===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAG class. 11// 12//===----------------------------------------------------------------------===// 13#include "llvm/CodeGen/SelectionDAG.h" 14#include "llvm/Constants.h" 15#include "llvm/Analysis/ValueTracking.h" 16#include "llvm/GlobalAlias.h" 17#include "llvm/GlobalVariable.h" 18#include "llvm/Intrinsics.h" 19#include "llvm/DerivedTypes.h" 20#include "llvm/Assembly/Writer.h" 21#include "llvm/CallingConv.h" 22#include "llvm/CodeGen/MachineBasicBlock.h" 23#include "llvm/CodeGen/MachineConstantPool.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/MachineModuleInfo.h" 26#include "llvm/CodeGen/PseudoSourceValue.h" 27#include "llvm/Support/MathExtras.h" 28#include "llvm/Target/TargetRegisterInfo.h" 29#include "llvm/Target/TargetData.h" 30#include "llvm/Target/TargetLowering.h" 31#include "llvm/Target/TargetInstrInfo.h" 32#include "llvm/Target/TargetMachine.h" 33#include "llvm/ADT/SetVector.h" 34#include "llvm/ADT/SmallPtrSet.h" 35#include "llvm/ADT/SmallSet.h" 36#include "llvm/ADT/SmallVector.h" 37#include "llvm/ADT/StringExtras.h" 38#include <algorithm> 39#include <cmath> 40using namespace llvm; 41 42/// makeVTList - Return an instance of the SDVTList struct initialized with the 43/// specified members. 44static SDVTList makeVTList(const MVT *VTs, unsigned NumVTs) { 45 SDVTList Res = {VTs, NumVTs}; 46 return Res; 47} 48 49static const fltSemantics *MVTToAPFloatSemantics(MVT VT) { 50 switch (VT.getSimpleVT()) { 51 default: assert(0 && "Unknown FP format"); 52 case MVT::f32: return &APFloat::IEEEsingle; 53 case MVT::f64: return &APFloat::IEEEdouble; 54 case MVT::f80: return &APFloat::x87DoubleExtended; 55 case MVT::f128: return &APFloat::IEEEquad; 56 case MVT::ppcf128: return &APFloat::PPCDoubleDouble; 57 } 58} 59 60SelectionDAG::DAGUpdateListener::~DAGUpdateListener() {} 61 62//===----------------------------------------------------------------------===// 63// ConstantFPSDNode Class 64//===----------------------------------------------------------------------===// 65 66/// isExactlyValue - We don't rely on operator== working on double values, as 67/// it returns true for things that are clearly not equal, like -0.0 and 0.0. 68/// As such, this method can be used to do an exact bit-for-bit comparison of 69/// two floating point values. 70bool ConstantFPSDNode::isExactlyValue(const APFloat& V) const { 71 return Value.bitwiseIsEqual(V); 72} 73 74bool ConstantFPSDNode::isValueValidForType(MVT VT, 75 const APFloat& Val) { 76 assert(VT.isFloatingPoint() && "Can only convert between FP types"); 77 78 // PPC long double cannot be converted to any other type. 79 if (VT == MVT::ppcf128 || 80 &Val.getSemantics() == &APFloat::PPCDoubleDouble) 81 return false; 82 83 // convert modifies in place, so make a copy. 84 APFloat Val2 = APFloat(Val); 85 return Val2.convert(*MVTToAPFloatSemantics(VT), 86 APFloat::rmNearestTiesToEven) == APFloat::opOK; 87} 88 89//===----------------------------------------------------------------------===// 90// ISD Namespace 91//===----------------------------------------------------------------------===// 92 93/// isBuildVectorAllOnes - Return true if the specified node is a 94/// BUILD_VECTOR where all of the elements are ~0 or undef. 95bool ISD::isBuildVectorAllOnes(const SDNode *N) { 96 // Look through a bit convert. 97 if (N->getOpcode() == ISD::BIT_CONVERT) 98 N = N->getOperand(0).Val; 99 100 if (N->getOpcode() != ISD::BUILD_VECTOR) return false; 101 102 unsigned i = 0, e = N->getNumOperands(); 103 104 // Skip over all of the undef values. 105 while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF) 106 ++i; 107 108 // Do not accept an all-undef vector. 109 if (i == e) return false; 110 111 // Do not accept build_vectors that aren't all constants or which have non-~0 112 // elements. 113 SDValue NotZero = N->getOperand(i); 114 if (isa<ConstantSDNode>(NotZero)) { 115 if (!cast<ConstantSDNode>(NotZero)->isAllOnesValue()) 116 return false; 117 } else if (isa<ConstantFPSDNode>(NotZero)) { 118 if (!cast<ConstantFPSDNode>(NotZero)->getValueAPF(). 119 convertToAPInt().isAllOnesValue()) 120 return false; 121 } else 122 return false; 123 124 // Okay, we have at least one ~0 value, check to see if the rest match or are 125 // undefs. 126 for (++i; i != e; ++i) 127 if (N->getOperand(i) != NotZero && 128 N->getOperand(i).getOpcode() != ISD::UNDEF) 129 return false; 130 return true; 131} 132 133 134/// isBuildVectorAllZeros - Return true if the specified node is a 135/// BUILD_VECTOR where all of the elements are 0 or undef. 136bool ISD::isBuildVectorAllZeros(const SDNode *N) { 137 // Look through a bit convert. 138 if (N->getOpcode() == ISD::BIT_CONVERT) 139 N = N->getOperand(0).Val; 140 141 if (N->getOpcode() != ISD::BUILD_VECTOR) return false; 142 143 unsigned i = 0, e = N->getNumOperands(); 144 145 // Skip over all of the undef values. 146 while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF) 147 ++i; 148 149 // Do not accept an all-undef vector. 150 if (i == e) return false; 151 152 // Do not accept build_vectors that aren't all constants or which have non-~0 153 // elements. 154 SDValue Zero = N->getOperand(i); 155 if (isa<ConstantSDNode>(Zero)) { 156 if (!cast<ConstantSDNode>(Zero)->isNullValue()) 157 return false; 158 } else if (isa<ConstantFPSDNode>(Zero)) { 159 if (!cast<ConstantFPSDNode>(Zero)->getValueAPF().isPosZero()) 160 return false; 161 } else 162 return false; 163 164 // Okay, we have at least one ~0 value, check to see if the rest match or are 165 // undefs. 166 for (++i; i != e; ++i) 167 if (N->getOperand(i) != Zero && 168 N->getOperand(i).getOpcode() != ISD::UNDEF) 169 return false; 170 return true; 171} 172 173/// isScalarToVector - Return true if the specified node is a 174/// ISD::SCALAR_TO_VECTOR node or a BUILD_VECTOR node where only the low 175/// element is not an undef. 176bool ISD::isScalarToVector(const SDNode *N) { 177 if (N->getOpcode() == ISD::SCALAR_TO_VECTOR) 178 return true; 179 180 if (N->getOpcode() != ISD::BUILD_VECTOR) 181 return false; 182 if (N->getOperand(0).getOpcode() == ISD::UNDEF) 183 return false; 184 unsigned NumElems = N->getNumOperands(); 185 for (unsigned i = 1; i < NumElems; ++i) { 186 SDValue V = N->getOperand(i); 187 if (V.getOpcode() != ISD::UNDEF) 188 return false; 189 } 190 return true; 191} 192 193 194/// isDebugLabel - Return true if the specified node represents a debug 195/// label (i.e. ISD::DBG_LABEL or TargetInstrInfo::DBG_LABEL node). 196bool ISD::isDebugLabel(const SDNode *N) { 197 SDValue Zero; 198 if (N->getOpcode() == ISD::DBG_LABEL) 199 return true; 200 if (N->isMachineOpcode() && 201 N->getMachineOpcode() == TargetInstrInfo::DBG_LABEL) 202 return true; 203 return false; 204} 205 206/// getSetCCSwappedOperands - Return the operation corresponding to (Y op X) 207/// when given the operation for (X op Y). 208ISD::CondCode ISD::getSetCCSwappedOperands(ISD::CondCode Operation) { 209 // To perform this operation, we just need to swap the L and G bits of the 210 // operation. 211 unsigned OldL = (Operation >> 2) & 1; 212 unsigned OldG = (Operation >> 1) & 1; 213 return ISD::CondCode((Operation & ~6) | // Keep the N, U, E bits 214 (OldL << 1) | // New G bit 215 (OldG << 2)); // New L bit. 216} 217 218/// getSetCCInverse - Return the operation corresponding to !(X op Y), where 219/// 'op' is a valid SetCC operation. 220ISD::CondCode ISD::getSetCCInverse(ISD::CondCode Op, bool isInteger) { 221 unsigned Operation = Op; 222 if (isInteger) 223 Operation ^= 7; // Flip L, G, E bits, but not U. 224 else 225 Operation ^= 15; // Flip all of the condition bits. 226 if (Operation > ISD::SETTRUE2) 227 Operation &= ~8; // Don't let N and U bits get set. 228 return ISD::CondCode(Operation); 229} 230 231 232/// isSignedOp - For an integer comparison, return 1 if the comparison is a 233/// signed operation and 2 if the result is an unsigned comparison. Return zero 234/// if the operation does not depend on the sign of the input (setne and seteq). 235static int isSignedOp(ISD::CondCode Opcode) { 236 switch (Opcode) { 237 default: assert(0 && "Illegal integer setcc operation!"); 238 case ISD::SETEQ: 239 case ISD::SETNE: return 0; 240 case ISD::SETLT: 241 case ISD::SETLE: 242 case ISD::SETGT: 243 case ISD::SETGE: return 1; 244 case ISD::SETULT: 245 case ISD::SETULE: 246 case ISD::SETUGT: 247 case ISD::SETUGE: return 2; 248 } 249} 250 251/// getSetCCOrOperation - Return the result of a logical OR between different 252/// comparisons of identical values: ((X op1 Y) | (X op2 Y)). This function 253/// returns SETCC_INVALID if it is not possible to represent the resultant 254/// comparison. 255ISD::CondCode ISD::getSetCCOrOperation(ISD::CondCode Op1, ISD::CondCode Op2, 256 bool isInteger) { 257 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 258 // Cannot fold a signed integer setcc with an unsigned integer setcc. 259 return ISD::SETCC_INVALID; 260 261 unsigned Op = Op1 | Op2; // Combine all of the condition bits. 262 263 // If the N and U bits get set then the resultant comparison DOES suddenly 264 // care about orderedness, and is true when ordered. 265 if (Op > ISD::SETTRUE2) 266 Op &= ~16; // Clear the U bit if the N bit is set. 267 268 // Canonicalize illegal integer setcc's. 269 if (isInteger && Op == ISD::SETUNE) // e.g. SETUGT | SETULT 270 Op = ISD::SETNE; 271 272 return ISD::CondCode(Op); 273} 274 275/// getSetCCAndOperation - Return the result of a logical AND between different 276/// comparisons of identical values: ((X op1 Y) & (X op2 Y)). This 277/// function returns zero if it is not possible to represent the resultant 278/// comparison. 279ISD::CondCode ISD::getSetCCAndOperation(ISD::CondCode Op1, ISD::CondCode Op2, 280 bool isInteger) { 281 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 282 // Cannot fold a signed setcc with an unsigned setcc. 283 return ISD::SETCC_INVALID; 284 285 // Combine all of the condition bits. 286 ISD::CondCode Result = ISD::CondCode(Op1 & Op2); 287 288 // Canonicalize illegal integer setcc's. 289 if (isInteger) { 290 switch (Result) { 291 default: break; 292 case ISD::SETUO : Result = ISD::SETFALSE; break; // SETUGT & SETULT 293 case ISD::SETOEQ: // SETEQ & SETU[LG]E 294 case ISD::SETUEQ: Result = ISD::SETEQ ; break; // SETUGE & SETULE 295 case ISD::SETOLT: Result = ISD::SETULT ; break; // SETULT & SETNE 296 case ISD::SETOGT: Result = ISD::SETUGT ; break; // SETUGT & SETNE 297 } 298 } 299 300 return Result; 301} 302 303const TargetMachine &SelectionDAG::getTarget() const { 304 return TLI.getTargetMachine(); 305} 306 307//===----------------------------------------------------------------------===// 308// SDNode Profile Support 309//===----------------------------------------------------------------------===// 310 311/// AddNodeIDOpcode - Add the node opcode to the NodeID data. 312/// 313static void AddNodeIDOpcode(FoldingSetNodeID &ID, unsigned OpC) { 314 ID.AddInteger(OpC); 315} 316 317/// AddNodeIDValueTypes - Value type lists are intern'd so we can represent them 318/// solely with their pointer. 319static void AddNodeIDValueTypes(FoldingSetNodeID &ID, SDVTList VTList) { 320 ID.AddPointer(VTList.VTs); 321} 322 323/// AddNodeIDOperands - Various routines for adding operands to the NodeID data. 324/// 325static void AddNodeIDOperands(FoldingSetNodeID &ID, 326 const SDValue *Ops, unsigned NumOps) { 327 for (; NumOps; --NumOps, ++Ops) { 328 ID.AddPointer(Ops->Val); 329 ID.AddInteger(Ops->ResNo); 330 } 331} 332 333/// AddNodeIDOperands - Various routines for adding operands to the NodeID data. 334/// 335static void AddNodeIDOperands(FoldingSetNodeID &ID, 336 const SDUse *Ops, unsigned NumOps) { 337 for (; NumOps; --NumOps, ++Ops) { 338 ID.AddPointer(Ops->getVal()); 339 ID.AddInteger(Ops->getSDValue().ResNo); 340 } 341} 342 343static void AddNodeIDNode(FoldingSetNodeID &ID, 344 unsigned short OpC, SDVTList VTList, 345 const SDValue *OpList, unsigned N) { 346 AddNodeIDOpcode(ID, OpC); 347 AddNodeIDValueTypes(ID, VTList); 348 AddNodeIDOperands(ID, OpList, N); 349} 350 351 352/// AddNodeIDNode - Generic routine for adding a nodes info to the NodeID 353/// data. 354static void AddNodeIDNode(FoldingSetNodeID &ID, SDNode *N) { 355 AddNodeIDOpcode(ID, N->getOpcode()); 356 // Add the return value info. 357 AddNodeIDValueTypes(ID, N->getVTList()); 358 // Add the operand info. 359 AddNodeIDOperands(ID, N->op_begin(), N->getNumOperands()); 360 361 // Handle SDNode leafs with special info. 362 switch (N->getOpcode()) { 363 default: break; // Normal nodes don't need extra info. 364 case ISD::ARG_FLAGS: 365 ID.AddInteger(cast<ARG_FLAGSSDNode>(N)->getArgFlags().getRawBits()); 366 break; 367 case ISD::TargetConstant: 368 case ISD::Constant: 369 ID.Add(cast<ConstantSDNode>(N)->getAPIntValue()); 370 break; 371 case ISD::TargetConstantFP: 372 case ISD::ConstantFP: { 373 ID.Add(cast<ConstantFPSDNode>(N)->getValueAPF()); 374 break; 375 } 376 case ISD::TargetGlobalAddress: 377 case ISD::GlobalAddress: 378 case ISD::TargetGlobalTLSAddress: 379 case ISD::GlobalTLSAddress: { 380 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(N); 381 ID.AddPointer(GA->getGlobal()); 382 ID.AddInteger(GA->getOffset()); 383 break; 384 } 385 case ISD::BasicBlock: 386 ID.AddPointer(cast<BasicBlockSDNode>(N)->getBasicBlock()); 387 break; 388 case ISD::Register: 389 ID.AddInteger(cast<RegisterSDNode>(N)->getReg()); 390 break; 391 case ISD::DBG_STOPPOINT: { 392 const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(N); 393 ID.AddInteger(DSP->getLine()); 394 ID.AddInteger(DSP->getColumn()); 395 ID.AddPointer(DSP->getCompileUnit()); 396 break; 397 } 398 case ISD::SRCVALUE: 399 ID.AddPointer(cast<SrcValueSDNode>(N)->getValue()); 400 break; 401 case ISD::MEMOPERAND: { 402 const MachineMemOperand &MO = cast<MemOperandSDNode>(N)->MO; 403 ID.AddPointer(MO.getValue()); 404 ID.AddInteger(MO.getFlags()); 405 ID.AddInteger(MO.getOffset()); 406 ID.AddInteger(MO.getSize()); 407 ID.AddInteger(MO.getAlignment()); 408 break; 409 } 410 case ISD::FrameIndex: 411 case ISD::TargetFrameIndex: 412 ID.AddInteger(cast<FrameIndexSDNode>(N)->getIndex()); 413 break; 414 case ISD::JumpTable: 415 case ISD::TargetJumpTable: 416 ID.AddInteger(cast<JumpTableSDNode>(N)->getIndex()); 417 break; 418 case ISD::ConstantPool: 419 case ISD::TargetConstantPool: { 420 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(N); 421 ID.AddInteger(CP->getAlignment()); 422 ID.AddInteger(CP->getOffset()); 423 if (CP->isMachineConstantPoolEntry()) 424 CP->getMachineCPVal()->AddSelectionDAGCSEId(ID); 425 else 426 ID.AddPointer(CP->getConstVal()); 427 break; 428 } 429 case ISD::LOAD: { 430 LoadSDNode *LD = cast<LoadSDNode>(N); 431 ID.AddInteger(LD->getAddressingMode()); 432 ID.AddInteger(LD->getExtensionType()); 433 ID.AddInteger(LD->getMemoryVT().getRawBits()); 434 ID.AddInteger(LD->getAlignment()); 435 ID.AddInteger(LD->isVolatile()); 436 break; 437 } 438 case ISD::STORE: { 439 StoreSDNode *ST = cast<StoreSDNode>(N); 440 ID.AddInteger(ST->getAddressingMode()); 441 ID.AddInteger(ST->isTruncatingStore()); 442 ID.AddInteger(ST->getMemoryVT().getRawBits()); 443 ID.AddInteger(ST->getAlignment()); 444 ID.AddInteger(ST->isVolatile()); 445 break; 446 } 447 case ISD::ATOMIC_CMP_SWAP: 448 case ISD::ATOMIC_LOAD_ADD: 449 case ISD::ATOMIC_SWAP: 450 case ISD::ATOMIC_LOAD_SUB: 451 case ISD::ATOMIC_LOAD_AND: 452 case ISD::ATOMIC_LOAD_OR: 453 case ISD::ATOMIC_LOAD_XOR: 454 case ISD::ATOMIC_LOAD_NAND: 455 case ISD::ATOMIC_LOAD_MIN: 456 case ISD::ATOMIC_LOAD_MAX: 457 case ISD::ATOMIC_LOAD_UMIN: 458 case ISD::ATOMIC_LOAD_UMAX: { 459 AtomicSDNode *AT = cast<AtomicSDNode>(N); 460 ID.AddInteger(AT->getAlignment()); 461 ID.AddInteger(AT->isVolatile()); 462 break; 463 } 464 } // end switch (N->getOpcode()) 465} 466 467//===----------------------------------------------------------------------===// 468// SelectionDAG Class 469//===----------------------------------------------------------------------===// 470 471/// RemoveDeadNodes - This method deletes all unreachable nodes in the 472/// SelectionDAG. 473void SelectionDAG::RemoveDeadNodes() { 474 // Create a dummy node (which is not added to allnodes), that adds a reference 475 // to the root node, preventing it from being deleted. 476 HandleSDNode Dummy(getRoot()); 477 478 SmallVector<SDNode*, 128> DeadNodes; 479 480 // Add all obviously-dead nodes to the DeadNodes worklist. 481 for (allnodes_iterator I = allnodes_begin(), E = allnodes_end(); I != E; ++I) 482 if (I->use_empty()) 483 DeadNodes.push_back(I); 484 485 RemoveDeadNodes(DeadNodes); 486 487 // If the root changed (e.g. it was a dead load, update the root). 488 setRoot(Dummy.getValue()); 489} 490 491/// RemoveDeadNodes - This method deletes the unreachable nodes in the 492/// given list, and any nodes that become unreachable as a result. 493void SelectionDAG::RemoveDeadNodes(SmallVectorImpl<SDNode *> &DeadNodes, 494 DAGUpdateListener *UpdateListener) { 495 496 // Process the worklist, deleting the nodes and adding their uses to the 497 // worklist. 498 while (!DeadNodes.empty()) { 499 SDNode *N = DeadNodes.back(); 500 DeadNodes.pop_back(); 501 502 if (UpdateListener) 503 UpdateListener->NodeDeleted(N, 0); 504 505 // Take the node out of the appropriate CSE map. 506 RemoveNodeFromCSEMaps(N); 507 508 // Next, brutally remove the operand list. This is safe to do, as there are 509 // no cycles in the graph. 510 for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ++I) { 511 SDNode *Operand = I->getVal(); 512 Operand->removeUser(std::distance(N->op_begin(), I), N); 513 514 // Now that we removed this operand, see if there are no uses of it left. 515 if (Operand->use_empty()) 516 DeadNodes.push_back(Operand); 517 } 518 if (N->OperandsNeedDelete) { 519 delete[] N->OperandList; 520 } 521 N->OperandList = 0; 522 N->NumOperands = 0; 523 524 // Finally, remove N itself. 525 AllNodes.remove(N); 526 } 527} 528 529void SelectionDAG::RemoveDeadNode(SDNode *N, DAGUpdateListener *UpdateListener){ 530 SmallVector<SDNode*, 16> DeadNodes(1, N); 531 RemoveDeadNodes(DeadNodes, UpdateListener); 532} 533 534void SelectionDAG::DeleteNode(SDNode *N) { 535 assert(N->use_empty() && "Cannot delete a node that is not dead!"); 536 537 // First take this out of the appropriate CSE map. 538 RemoveNodeFromCSEMaps(N); 539 540 // Finally, remove uses due to operands of this node, remove from the 541 // AllNodes list, and delete the node. 542 DeleteNodeNotInCSEMaps(N); 543} 544 545void SelectionDAG::DeleteNodeNotInCSEMaps(SDNode *N) { 546 547 // Drop all of the operands and decrement used nodes use counts. 548 for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ++I) 549 I->getVal()->removeUser(std::distance(N->op_begin(), I), N); 550 if (N->OperandsNeedDelete) { 551 delete[] N->OperandList; 552 } 553 N->OperandList = 0; 554 N->NumOperands = 0; 555 556 AllNodes.remove(N); 557} 558 559/// RemoveNodeFromCSEMaps - Take the specified node out of the CSE map that 560/// correspond to it. This is useful when we're about to delete or repurpose 561/// the node. We don't want future request for structurally identical nodes 562/// to return N anymore. 563void SelectionDAG::RemoveNodeFromCSEMaps(SDNode *N) { 564 bool Erased = false; 565 switch (N->getOpcode()) { 566 case ISD::HANDLENODE: return; // noop. 567 case ISD::CONDCODE: 568 assert(CondCodeNodes[cast<CondCodeSDNode>(N)->get()] && 569 "Cond code doesn't exist!"); 570 Erased = CondCodeNodes[cast<CondCodeSDNode>(N)->get()] != 0; 571 CondCodeNodes[cast<CondCodeSDNode>(N)->get()] = 0; 572 break; 573 case ISD::ExternalSymbol: 574 Erased = ExternalSymbols.erase(cast<ExternalSymbolSDNode>(N)->getSymbol()); 575 break; 576 case ISD::TargetExternalSymbol: 577 Erased = 578 TargetExternalSymbols.erase(cast<ExternalSymbolSDNode>(N)->getSymbol()); 579 break; 580 case ISD::VALUETYPE: { 581 MVT VT = cast<VTSDNode>(N)->getVT(); 582 if (VT.isExtended()) { 583 Erased = ExtendedValueTypeNodes.erase(VT); 584 } else { 585 Erased = ValueTypeNodes[VT.getSimpleVT()] != 0; 586 ValueTypeNodes[VT.getSimpleVT()] = 0; 587 } 588 break; 589 } 590 default: 591 // Remove it from the CSE Map. 592 Erased = CSEMap.RemoveNode(N); 593 break; 594 } 595#ifndef NDEBUG 596 // Verify that the node was actually in one of the CSE maps, unless it has a 597 // flag result (which cannot be CSE'd) or is one of the special cases that are 598 // not subject to CSE. 599 if (!Erased && N->getValueType(N->getNumValues()-1) != MVT::Flag && 600 !N->isTargetOpcode() && 601 N->getOpcode() != ISD::DBG_LABEL && 602 N->getOpcode() != ISD::DBG_STOPPOINT && 603 N->getOpcode() != ISD::EH_LABEL && 604 N->getOpcode() != ISD::DECLARE) { 605 N->dump(this); 606 cerr << "\n"; 607 assert(0 && "Node is not in map!"); 608 } 609#endif 610} 611 612/// AddNonLeafNodeToCSEMaps - Add the specified node back to the CSE maps. It 613/// has been taken out and modified in some way. If the specified node already 614/// exists in the CSE maps, do not modify the maps, but return the existing node 615/// instead. If it doesn't exist, add it and return null. 616/// 617SDNode *SelectionDAG::AddNonLeafNodeToCSEMaps(SDNode *N) { 618 assert(N->getNumOperands() && "This is a leaf node!"); 619 620 if (N->getValueType(0) == MVT::Flag) 621 return 0; // Never CSE anything that produces a flag. 622 623 switch (N->getOpcode()) { 624 default: break; 625 case ISD::HANDLENODE: 626 case ISD::DBG_LABEL: 627 case ISD::DBG_STOPPOINT: 628 case ISD::EH_LABEL: 629 case ISD::DECLARE: 630 return 0; // Never add these nodes. 631 } 632 633 // Check that remaining values produced are not flags. 634 for (unsigned i = 1, e = N->getNumValues(); i != e; ++i) 635 if (N->getValueType(i) == MVT::Flag) 636 return 0; // Never CSE anything that produces a flag. 637 638 SDNode *New = CSEMap.GetOrInsertNode(N); 639 if (New != N) return New; // Node already existed. 640 return 0; 641} 642 643/// FindModifiedNodeSlot - Find a slot for the specified node if its operands 644/// were replaced with those specified. If this node is never memoized, 645/// return null, otherwise return a pointer to the slot it would take. If a 646/// node already exists with these operands, the slot will be non-null. 647SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, SDValue Op, 648 void *&InsertPos) { 649 if (N->getValueType(0) == MVT::Flag) 650 return 0; // Never CSE anything that produces a flag. 651 652 switch (N->getOpcode()) { 653 default: break; 654 case ISD::HANDLENODE: 655 case ISD::DBG_LABEL: 656 case ISD::DBG_STOPPOINT: 657 case ISD::EH_LABEL: 658 return 0; // Never add these nodes. 659 } 660 661 // Check that remaining values produced are not flags. 662 for (unsigned i = 1, e = N->getNumValues(); i != e; ++i) 663 if (N->getValueType(i) == MVT::Flag) 664 return 0; // Never CSE anything that produces a flag. 665 666 SDValue Ops[] = { Op }; 667 FoldingSetNodeID ID; 668 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, 1); 669 return CSEMap.FindNodeOrInsertPos(ID, InsertPos); 670} 671 672/// FindModifiedNodeSlot - Find a slot for the specified node if its operands 673/// were replaced with those specified. If this node is never memoized, 674/// return null, otherwise return a pointer to the slot it would take. If a 675/// node already exists with these operands, the slot will be non-null. 676SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, 677 SDValue Op1, SDValue Op2, 678 void *&InsertPos) { 679 if (N->getOpcode() == ISD::HANDLENODE || N->getValueType(0) == MVT::Flag) 680 681 // Check that remaining values produced are not flags. 682 for (unsigned i = 1, e = N->getNumValues(); i != e; ++i) 683 if (N->getValueType(i) == MVT::Flag) 684 return 0; // Never CSE anything that produces a flag. 685 686 SDValue Ops[] = { Op1, Op2 }; 687 FoldingSetNodeID ID; 688 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, 2); 689 return CSEMap.FindNodeOrInsertPos(ID, InsertPos); 690} 691 692 693/// FindModifiedNodeSlot - Find a slot for the specified node if its operands 694/// were replaced with those specified. If this node is never memoized, 695/// return null, otherwise return a pointer to the slot it would take. If a 696/// node already exists with these operands, the slot will be non-null. 697SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, 698 const SDValue *Ops,unsigned NumOps, 699 void *&InsertPos) { 700 if (N->getValueType(0) == MVT::Flag) 701 return 0; // Never CSE anything that produces a flag. 702 703 switch (N->getOpcode()) { 704 default: break; 705 case ISD::HANDLENODE: 706 case ISD::DBG_LABEL: 707 case ISD::DBG_STOPPOINT: 708 case ISD::EH_LABEL: 709 case ISD::DECLARE: 710 return 0; // Never add these nodes. 711 } 712 713 // Check that remaining values produced are not flags. 714 for (unsigned i = 1, e = N->getNumValues(); i != e; ++i) 715 if (N->getValueType(i) == MVT::Flag) 716 return 0; // Never CSE anything that produces a flag. 717 718 FoldingSetNodeID ID; 719 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, NumOps); 720 721 if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 722 ID.AddInteger(LD->getAddressingMode()); 723 ID.AddInteger(LD->getExtensionType()); 724 ID.AddInteger(LD->getMemoryVT().getRawBits()); 725 ID.AddInteger(LD->getAlignment()); 726 ID.AddInteger(LD->isVolatile()); 727 } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 728 ID.AddInteger(ST->getAddressingMode()); 729 ID.AddInteger(ST->isTruncatingStore()); 730 ID.AddInteger(ST->getMemoryVT().getRawBits()); 731 ID.AddInteger(ST->getAlignment()); 732 ID.AddInteger(ST->isVolatile()); 733 } 734 735 return CSEMap.FindNodeOrInsertPos(ID, InsertPos); 736} 737 738/// VerifyNode - Sanity check the given node. Aborts if it is invalid. 739void SelectionDAG::VerifyNode(SDNode *N) { 740 switch (N->getOpcode()) { 741 default: 742 break; 743 case ISD::BUILD_VECTOR: { 744 assert(N->getNumValues() == 1 && "Too many results for BUILD_VECTOR!"); 745 assert(N->getValueType(0).isVector() && "Wrong BUILD_VECTOR return type!"); 746 assert(N->getNumOperands() == N->getValueType(0).getVectorNumElements() && 747 "Wrong number of BUILD_VECTOR operands!"); 748 MVT EltVT = N->getValueType(0).getVectorElementType(); 749 for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ++I) 750 assert(I->getSDValue().getValueType() == EltVT && 751 "Wrong BUILD_VECTOR operand type!"); 752 break; 753 } 754 } 755} 756 757/// getMVTAlignment - Compute the default alignment value for the 758/// given type. 759/// 760unsigned SelectionDAG::getMVTAlignment(MVT VT) const { 761 const Type *Ty = VT == MVT::iPTR ? 762 PointerType::get(Type::Int8Ty, 0) : 763 VT.getTypeForMVT(); 764 765 return TLI.getTargetData()->getABITypeAlignment(Ty); 766} 767 768SelectionDAG::~SelectionDAG() { 769 while (!AllNodes.empty()) { 770 SDNode *N = AllNodes.remove(AllNodes.begin()); 771 N->SetNextInBucket(0); 772 if (N->OperandsNeedDelete) { 773 delete [] N->OperandList; 774 } 775 N->OperandList = 0; 776 N->NumOperands = 0; 777 } 778} 779 780SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, MVT VT) { 781 if (Op.getValueType() == VT) return Op; 782 APInt Imm = APInt::getLowBitsSet(Op.getValueSizeInBits(), 783 VT.getSizeInBits()); 784 return getNode(ISD::AND, Op.getValueType(), Op, 785 getConstant(Imm, Op.getValueType())); 786} 787 788SDValue SelectionDAG::getConstant(uint64_t Val, MVT VT, bool isT) { 789 MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 790 return getConstant(APInt(EltVT.getSizeInBits(), Val), VT, isT); 791} 792 793SDValue SelectionDAG::getConstant(const APInt &Val, MVT VT, bool isT) { 794 assert(VT.isInteger() && "Cannot create FP integer constant!"); 795 796 MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 797 assert(Val.getBitWidth() == EltVT.getSizeInBits() && 798 "APInt size does not match type size!"); 799 800 unsigned Opc = isT ? ISD::TargetConstant : ISD::Constant; 801 FoldingSetNodeID ID; 802 AddNodeIDNode(ID, Opc, getVTList(EltVT), 0, 0); 803 ID.Add(Val); 804 void *IP = 0; 805 SDNode *N = NULL; 806 if ((N = CSEMap.FindNodeOrInsertPos(ID, IP))) 807 if (!VT.isVector()) 808 return SDValue(N, 0); 809 if (!N) { 810 N = NodeAllocator.Allocate<ConstantSDNode>(); 811 new (N) ConstantSDNode(isT, Val, EltVT); 812 CSEMap.InsertNode(N, IP); 813 AllNodes.push_back(N); 814 } 815 816 SDValue Result(N, 0); 817 if (VT.isVector()) { 818 SmallVector<SDValue, 8> Ops; 819 Ops.assign(VT.getVectorNumElements(), Result); 820 Result = getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 821 } 822 return Result; 823} 824 825SDValue SelectionDAG::getIntPtrConstant(uint64_t Val, bool isTarget) { 826 return getConstant(Val, TLI.getPointerTy(), isTarget); 827} 828 829 830SDValue SelectionDAG::getConstantFP(const APFloat& V, MVT VT, bool isTarget) { 831 assert(VT.isFloatingPoint() && "Cannot create integer FP constant!"); 832 833 MVT EltVT = 834 VT.isVector() ? VT.getVectorElementType() : VT; 835 836 // Do the map lookup using the actual bit pattern for the floating point 837 // value, so that we don't have problems with 0.0 comparing equal to -0.0, and 838 // we don't have issues with SNANs. 839 unsigned Opc = isTarget ? ISD::TargetConstantFP : ISD::ConstantFP; 840 FoldingSetNodeID ID; 841 AddNodeIDNode(ID, Opc, getVTList(EltVT), 0, 0); 842 ID.Add(V); 843 void *IP = 0; 844 SDNode *N = NULL; 845 if ((N = CSEMap.FindNodeOrInsertPos(ID, IP))) 846 if (!VT.isVector()) 847 return SDValue(N, 0); 848 if (!N) { 849 N = NodeAllocator.Allocate<ConstantFPSDNode>(); 850 new (N) ConstantFPSDNode(isTarget, V, EltVT); 851 CSEMap.InsertNode(N, IP); 852 AllNodes.push_back(N); 853 } 854 855 SDValue Result(N, 0); 856 if (VT.isVector()) { 857 SmallVector<SDValue, 8> Ops; 858 Ops.assign(VT.getVectorNumElements(), Result); 859 Result = getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 860 } 861 return Result; 862} 863 864SDValue SelectionDAG::getConstantFP(double Val, MVT VT, bool isTarget) { 865 MVT EltVT = 866 VT.isVector() ? VT.getVectorElementType() : VT; 867 if (EltVT==MVT::f32) 868 return getConstantFP(APFloat((float)Val), VT, isTarget); 869 else 870 return getConstantFP(APFloat(Val), VT, isTarget); 871} 872 873SDValue SelectionDAG::getGlobalAddress(const GlobalValue *GV, 874 MVT VT, int Offset, 875 bool isTargetGA) { 876 unsigned Opc; 877 878 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV); 879 if (!GVar) { 880 // If GV is an alias then use the aliasee for determining thread-localness. 881 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) 882 GVar = dyn_cast_or_null<GlobalVariable>(GA->resolveAliasedGlobal()); 883 } 884 885 if (GVar && GVar->isThreadLocal()) 886 Opc = isTargetGA ? ISD::TargetGlobalTLSAddress : ISD::GlobalTLSAddress; 887 else 888 Opc = isTargetGA ? ISD::TargetGlobalAddress : ISD::GlobalAddress; 889 890 FoldingSetNodeID ID; 891 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 892 ID.AddPointer(GV); 893 ID.AddInteger(Offset); 894 void *IP = 0; 895 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 896 return SDValue(E, 0); 897 SDNode *N = NodeAllocator.Allocate<GlobalAddressSDNode>(); 898 new (N) GlobalAddressSDNode(isTargetGA, GV, VT, Offset); 899 CSEMap.InsertNode(N, IP); 900 AllNodes.push_back(N); 901 return SDValue(N, 0); 902} 903 904SDValue SelectionDAG::getFrameIndex(int FI, MVT VT, bool isTarget) { 905 unsigned Opc = isTarget ? ISD::TargetFrameIndex : ISD::FrameIndex; 906 FoldingSetNodeID ID; 907 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 908 ID.AddInteger(FI); 909 void *IP = 0; 910 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 911 return SDValue(E, 0); 912 SDNode *N = NodeAllocator.Allocate<FrameIndexSDNode>(); 913 new (N) FrameIndexSDNode(FI, VT, isTarget); 914 CSEMap.InsertNode(N, IP); 915 AllNodes.push_back(N); 916 return SDValue(N, 0); 917} 918 919SDValue SelectionDAG::getJumpTable(int JTI, MVT VT, bool isTarget){ 920 unsigned Opc = isTarget ? ISD::TargetJumpTable : ISD::JumpTable; 921 FoldingSetNodeID ID; 922 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 923 ID.AddInteger(JTI); 924 void *IP = 0; 925 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 926 return SDValue(E, 0); 927 SDNode *N = NodeAllocator.Allocate<JumpTableSDNode>(); 928 new (N) JumpTableSDNode(JTI, VT, isTarget); 929 CSEMap.InsertNode(N, IP); 930 AllNodes.push_back(N); 931 return SDValue(N, 0); 932} 933 934SDValue SelectionDAG::getConstantPool(Constant *C, MVT VT, 935 unsigned Alignment, int Offset, 936 bool isTarget) { 937 unsigned Opc = isTarget ? ISD::TargetConstantPool : ISD::ConstantPool; 938 FoldingSetNodeID ID; 939 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 940 ID.AddInteger(Alignment); 941 ID.AddInteger(Offset); 942 ID.AddPointer(C); 943 void *IP = 0; 944 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 945 return SDValue(E, 0); 946 SDNode *N = NodeAllocator.Allocate<ConstantPoolSDNode>(); 947 new (N) ConstantPoolSDNode(isTarget, C, VT, Offset, Alignment); 948 CSEMap.InsertNode(N, IP); 949 AllNodes.push_back(N); 950 return SDValue(N, 0); 951} 952 953 954SDValue SelectionDAG::getConstantPool(MachineConstantPoolValue *C, MVT VT, 955 unsigned Alignment, int Offset, 956 bool isTarget) { 957 unsigned Opc = isTarget ? ISD::TargetConstantPool : ISD::ConstantPool; 958 FoldingSetNodeID ID; 959 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 960 ID.AddInteger(Alignment); 961 ID.AddInteger(Offset); 962 C->AddSelectionDAGCSEId(ID); 963 void *IP = 0; 964 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 965 return SDValue(E, 0); 966 SDNode *N = NodeAllocator.Allocate<ConstantPoolSDNode>(); 967 new (N) ConstantPoolSDNode(isTarget, C, VT, Offset, Alignment); 968 CSEMap.InsertNode(N, IP); 969 AllNodes.push_back(N); 970 return SDValue(N, 0); 971} 972 973 974SDValue SelectionDAG::getBasicBlock(MachineBasicBlock *MBB) { 975 FoldingSetNodeID ID; 976 AddNodeIDNode(ID, ISD::BasicBlock, getVTList(MVT::Other), 0, 0); 977 ID.AddPointer(MBB); 978 void *IP = 0; 979 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 980 return SDValue(E, 0); 981 SDNode *N = NodeAllocator.Allocate<BasicBlockSDNode>(); 982 new (N) BasicBlockSDNode(MBB); 983 CSEMap.InsertNode(N, IP); 984 AllNodes.push_back(N); 985 return SDValue(N, 0); 986} 987 988SDValue SelectionDAG::getArgFlags(ISD::ArgFlagsTy Flags) { 989 FoldingSetNodeID ID; 990 AddNodeIDNode(ID, ISD::ARG_FLAGS, getVTList(MVT::Other), 0, 0); 991 ID.AddInteger(Flags.getRawBits()); 992 void *IP = 0; 993 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 994 return SDValue(E, 0); 995 SDNode *N = NodeAllocator.Allocate<ARG_FLAGSSDNode>(); 996 new (N) ARG_FLAGSSDNode(Flags); 997 CSEMap.InsertNode(N, IP); 998 AllNodes.push_back(N); 999 return SDValue(N, 0); 1000} 1001 1002SDValue SelectionDAG::getValueType(MVT VT) { 1003 if (VT.isSimple() && (unsigned)VT.getSimpleVT() >= ValueTypeNodes.size()) 1004 ValueTypeNodes.resize(VT.getSimpleVT()+1); 1005 1006 SDNode *&N = VT.isExtended() ? 1007 ExtendedValueTypeNodes[VT] : ValueTypeNodes[VT.getSimpleVT()]; 1008 1009 if (N) return SDValue(N, 0); 1010 N = NodeAllocator.Allocate<VTSDNode>(); 1011 new (N) VTSDNode(VT); 1012 AllNodes.push_back(N); 1013 return SDValue(N, 0); 1014} 1015 1016SDValue SelectionDAG::getExternalSymbol(const char *Sym, MVT VT) { 1017 SDNode *&N = ExternalSymbols[Sym]; 1018 if (N) return SDValue(N, 0); 1019 N = NodeAllocator.Allocate<ExternalSymbolSDNode>(); 1020 new (N) ExternalSymbolSDNode(false, Sym, VT); 1021 AllNodes.push_back(N); 1022 return SDValue(N, 0); 1023} 1024 1025SDValue SelectionDAG::getTargetExternalSymbol(const char *Sym, MVT VT) { 1026 SDNode *&N = TargetExternalSymbols[Sym]; 1027 if (N) return SDValue(N, 0); 1028 N = NodeAllocator.Allocate<ExternalSymbolSDNode>(); 1029 new (N) ExternalSymbolSDNode(true, Sym, VT); 1030 AllNodes.push_back(N); 1031 return SDValue(N, 0); 1032} 1033 1034SDValue SelectionDAG::getCondCode(ISD::CondCode Cond) { 1035 if ((unsigned)Cond >= CondCodeNodes.size()) 1036 CondCodeNodes.resize(Cond+1); 1037 1038 if (CondCodeNodes[Cond] == 0) { 1039 CondCodeSDNode *N = NodeAllocator.Allocate<CondCodeSDNode>(); 1040 new (N) CondCodeSDNode(Cond); 1041 CondCodeNodes[Cond] = N; 1042 AllNodes.push_back(N); 1043 } 1044 return SDValue(CondCodeNodes[Cond], 0); 1045} 1046 1047SDValue SelectionDAG::getRegister(unsigned RegNo, MVT VT) { 1048 FoldingSetNodeID ID; 1049 AddNodeIDNode(ID, ISD::Register, getVTList(VT), 0, 0); 1050 ID.AddInteger(RegNo); 1051 void *IP = 0; 1052 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1053 return SDValue(E, 0); 1054 SDNode *N = NodeAllocator.Allocate<RegisterSDNode>(); 1055 new (N) RegisterSDNode(RegNo, VT); 1056 CSEMap.InsertNode(N, IP); 1057 AllNodes.push_back(N); 1058 return SDValue(N, 0); 1059} 1060 1061SDValue SelectionDAG::getDbgStopPoint(SDValue Root, 1062 unsigned Line, unsigned Col, 1063 const CompileUnitDesc *CU) { 1064 SDNode *N = NodeAllocator.Allocate<DbgStopPointSDNode>(); 1065 new (N) DbgStopPointSDNode(Root, Line, Col, CU); 1066 AllNodes.push_back(N); 1067 return SDValue(N, 0); 1068} 1069 1070SDValue SelectionDAG::getLabel(unsigned Opcode, 1071 SDValue Root, 1072 unsigned LabelID) { 1073 FoldingSetNodeID ID; 1074 SDValue Ops[] = { Root }; 1075 AddNodeIDNode(ID, Opcode, getVTList(MVT::Other), &Ops[0], 1); 1076 ID.AddInteger(LabelID); 1077 void *IP = 0; 1078 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1079 return SDValue(E, 0); 1080 SDNode *N = NodeAllocator.Allocate<LabelSDNode>(); 1081 new (N) LabelSDNode(Opcode, Root, LabelID); 1082 CSEMap.InsertNode(N, IP); 1083 AllNodes.push_back(N); 1084 return SDValue(N, 0); 1085} 1086 1087SDValue SelectionDAG::getSrcValue(const Value *V) { 1088 assert((!V || isa<PointerType>(V->getType())) && 1089 "SrcValue is not a pointer?"); 1090 1091 FoldingSetNodeID ID; 1092 AddNodeIDNode(ID, ISD::SRCVALUE, getVTList(MVT::Other), 0, 0); 1093 ID.AddPointer(V); 1094 1095 void *IP = 0; 1096 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1097 return SDValue(E, 0); 1098 1099 SDNode *N = NodeAllocator.Allocate<SrcValueSDNode>(); 1100 new (N) SrcValueSDNode(V); 1101 CSEMap.InsertNode(N, IP); 1102 AllNodes.push_back(N); 1103 return SDValue(N, 0); 1104} 1105 1106SDValue SelectionDAG::getMemOperand(const MachineMemOperand &MO) { 1107 const Value *v = MO.getValue(); 1108 assert((!v || isa<PointerType>(v->getType())) && 1109 "SrcValue is not a pointer?"); 1110 1111 FoldingSetNodeID ID; 1112 AddNodeIDNode(ID, ISD::MEMOPERAND, getVTList(MVT::Other), 0, 0); 1113 ID.AddPointer(v); 1114 ID.AddInteger(MO.getFlags()); 1115 ID.AddInteger(MO.getOffset()); 1116 ID.AddInteger(MO.getSize()); 1117 ID.AddInteger(MO.getAlignment()); 1118 1119 void *IP = 0; 1120 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1121 return SDValue(E, 0); 1122 1123 SDNode *N = NodeAllocator.Allocate<MemOperandSDNode>(); 1124 new (N) MemOperandSDNode(MO); 1125 CSEMap.InsertNode(N, IP); 1126 AllNodes.push_back(N); 1127 return SDValue(N, 0); 1128} 1129 1130/// CreateStackTemporary - Create a stack temporary, suitable for holding the 1131/// specified value type. 1132SDValue SelectionDAG::CreateStackTemporary(MVT VT, unsigned minAlign) { 1133 MachineFrameInfo *FrameInfo = getMachineFunction().getFrameInfo(); 1134 unsigned ByteSize = VT.getSizeInBits()/8; 1135 const Type *Ty = VT.getTypeForMVT(); 1136 unsigned StackAlign = 1137 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), minAlign); 1138 1139 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, StackAlign); 1140 return getFrameIndex(FrameIdx, TLI.getPointerTy()); 1141} 1142 1143SDValue SelectionDAG::FoldSetCC(MVT VT, SDValue N1, 1144 SDValue N2, ISD::CondCode Cond) { 1145 // These setcc operations always fold. 1146 switch (Cond) { 1147 default: break; 1148 case ISD::SETFALSE: 1149 case ISD::SETFALSE2: return getConstant(0, VT); 1150 case ISD::SETTRUE: 1151 case ISD::SETTRUE2: return getConstant(1, VT); 1152 1153 case ISD::SETOEQ: 1154 case ISD::SETOGT: 1155 case ISD::SETOGE: 1156 case ISD::SETOLT: 1157 case ISD::SETOLE: 1158 case ISD::SETONE: 1159 case ISD::SETO: 1160 case ISD::SETUO: 1161 case ISD::SETUEQ: 1162 case ISD::SETUNE: 1163 assert(!N1.getValueType().isInteger() && "Illegal setcc for integer!"); 1164 break; 1165 } 1166 1167 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val)) { 1168 const APInt &C2 = N2C->getAPIntValue(); 1169 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) { 1170 const APInt &C1 = N1C->getAPIntValue(); 1171 1172 switch (Cond) { 1173 default: assert(0 && "Unknown integer setcc!"); 1174 case ISD::SETEQ: return getConstant(C1 == C2, VT); 1175 case ISD::SETNE: return getConstant(C1 != C2, VT); 1176 case ISD::SETULT: return getConstant(C1.ult(C2), VT); 1177 case ISD::SETUGT: return getConstant(C1.ugt(C2), VT); 1178 case ISD::SETULE: return getConstant(C1.ule(C2), VT); 1179 case ISD::SETUGE: return getConstant(C1.uge(C2), VT); 1180 case ISD::SETLT: return getConstant(C1.slt(C2), VT); 1181 case ISD::SETGT: return getConstant(C1.sgt(C2), VT); 1182 case ISD::SETLE: return getConstant(C1.sle(C2), VT); 1183 case ISD::SETGE: return getConstant(C1.sge(C2), VT); 1184 } 1185 } 1186 } 1187 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.Val)) { 1188 if (ConstantFPSDNode *N2C = dyn_cast<ConstantFPSDNode>(N2.Val)) { 1189 // No compile time operations on this type yet. 1190 if (N1C->getValueType(0) == MVT::ppcf128) 1191 return SDValue(); 1192 1193 APFloat::cmpResult R = N1C->getValueAPF().compare(N2C->getValueAPF()); 1194 switch (Cond) { 1195 default: break; 1196 case ISD::SETEQ: if (R==APFloat::cmpUnordered) 1197 return getNode(ISD::UNDEF, VT); 1198 // fall through 1199 case ISD::SETOEQ: return getConstant(R==APFloat::cmpEqual, VT); 1200 case ISD::SETNE: if (R==APFloat::cmpUnordered) 1201 return getNode(ISD::UNDEF, VT); 1202 // fall through 1203 case ISD::SETONE: return getConstant(R==APFloat::cmpGreaterThan || 1204 R==APFloat::cmpLessThan, VT); 1205 case ISD::SETLT: if (R==APFloat::cmpUnordered) 1206 return getNode(ISD::UNDEF, VT); 1207 // fall through 1208 case ISD::SETOLT: return getConstant(R==APFloat::cmpLessThan, VT); 1209 case ISD::SETGT: if (R==APFloat::cmpUnordered) 1210 return getNode(ISD::UNDEF, VT); 1211 // fall through 1212 case ISD::SETOGT: return getConstant(R==APFloat::cmpGreaterThan, VT); 1213 case ISD::SETLE: if (R==APFloat::cmpUnordered) 1214 return getNode(ISD::UNDEF, VT); 1215 // fall through 1216 case ISD::SETOLE: return getConstant(R==APFloat::cmpLessThan || 1217 R==APFloat::cmpEqual, VT); 1218 case ISD::SETGE: if (R==APFloat::cmpUnordered) 1219 return getNode(ISD::UNDEF, VT); 1220 // fall through 1221 case ISD::SETOGE: return getConstant(R==APFloat::cmpGreaterThan || 1222 R==APFloat::cmpEqual, VT); 1223 case ISD::SETO: return getConstant(R!=APFloat::cmpUnordered, VT); 1224 case ISD::SETUO: return getConstant(R==APFloat::cmpUnordered, VT); 1225 case ISD::SETUEQ: return getConstant(R==APFloat::cmpUnordered || 1226 R==APFloat::cmpEqual, VT); 1227 case ISD::SETUNE: return getConstant(R!=APFloat::cmpEqual, VT); 1228 case ISD::SETULT: return getConstant(R==APFloat::cmpUnordered || 1229 R==APFloat::cmpLessThan, VT); 1230 case ISD::SETUGT: return getConstant(R==APFloat::cmpGreaterThan || 1231 R==APFloat::cmpUnordered, VT); 1232 case ISD::SETULE: return getConstant(R!=APFloat::cmpGreaterThan, VT); 1233 case ISD::SETUGE: return getConstant(R!=APFloat::cmpLessThan, VT); 1234 } 1235 } else { 1236 // Ensure that the constant occurs on the RHS. 1237 return getSetCC(VT, N2, N1, ISD::getSetCCSwappedOperands(Cond)); 1238 } 1239 } 1240 1241 // Could not fold it. 1242 return SDValue(); 1243} 1244 1245/// SignBitIsZero - Return true if the sign bit of Op is known to be zero. We 1246/// use this predicate to simplify operations downstream. 1247bool SelectionDAG::SignBitIsZero(SDValue Op, unsigned Depth) const { 1248 unsigned BitWidth = Op.getValueSizeInBits(); 1249 return MaskedValueIsZero(Op, APInt::getSignBit(BitWidth), Depth); 1250} 1251 1252/// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero. We use 1253/// this predicate to simplify operations downstream. Mask is known to be zero 1254/// for bits that V cannot have. 1255bool SelectionDAG::MaskedValueIsZero(SDValue Op, const APInt &Mask, 1256 unsigned Depth) const { 1257 APInt KnownZero, KnownOne; 1258 ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth); 1259 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1260 return (KnownZero & Mask) == Mask; 1261} 1262 1263/// ComputeMaskedBits - Determine which of the bits specified in Mask are 1264/// known to be either zero or one and return them in the KnownZero/KnownOne 1265/// bitsets. This code only analyzes bits in Mask, in order to short-circuit 1266/// processing. 1267void SelectionDAG::ComputeMaskedBits(SDValue Op, const APInt &Mask, 1268 APInt &KnownZero, APInt &KnownOne, 1269 unsigned Depth) const { 1270 unsigned BitWidth = Mask.getBitWidth(); 1271 assert(BitWidth == Op.getValueType().getSizeInBits() && 1272 "Mask size mismatches value type size!"); 1273 1274 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything. 1275 if (Depth == 6 || Mask == 0) 1276 return; // Limit search depth. 1277 1278 APInt KnownZero2, KnownOne2; 1279 1280 switch (Op.getOpcode()) { 1281 case ISD::Constant: 1282 // We know all of the bits for a constant! 1283 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & Mask; 1284 KnownZero = ~KnownOne & Mask; 1285 return; 1286 case ISD::AND: 1287 // If either the LHS or the RHS are Zero, the result is zero. 1288 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1289 ComputeMaskedBits(Op.getOperand(0), Mask & ~KnownZero, 1290 KnownZero2, KnownOne2, Depth+1); 1291 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1292 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1293 1294 // Output known-1 bits are only known if set in both the LHS & RHS. 1295 KnownOne &= KnownOne2; 1296 // Output known-0 are known to be clear if zero in either the LHS | RHS. 1297 KnownZero |= KnownZero2; 1298 return; 1299 case ISD::OR: 1300 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1301 ComputeMaskedBits(Op.getOperand(0), Mask & ~KnownOne, 1302 KnownZero2, KnownOne2, Depth+1); 1303 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1304 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1305 1306 // Output known-0 bits are only known if clear in both the LHS & RHS. 1307 KnownZero &= KnownZero2; 1308 // Output known-1 are known to be set if set in either the LHS | RHS. 1309 KnownOne |= KnownOne2; 1310 return; 1311 case ISD::XOR: { 1312 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1313 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1); 1314 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1315 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1316 1317 // Output known-0 bits are known if clear or set in both the LHS & RHS. 1318 APInt KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 1319 // Output known-1 are known to be set if set in only one of the LHS, RHS. 1320 KnownOne = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 1321 KnownZero = KnownZeroOut; 1322 return; 1323 } 1324 case ISD::MUL: { 1325 APInt Mask2 = APInt::getAllOnesValue(BitWidth); 1326 ComputeMaskedBits(Op.getOperand(1), Mask2, KnownZero, KnownOne, Depth+1); 1327 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero2, KnownOne2, Depth+1); 1328 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1329 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1330 1331 // If low bits are zero in either operand, output low known-0 bits. 1332 // Also compute a conserative estimate for high known-0 bits. 1333 // More trickiness is possible, but this is sufficient for the 1334 // interesting case of alignment computation. 1335 KnownOne.clear(); 1336 unsigned TrailZ = KnownZero.countTrailingOnes() + 1337 KnownZero2.countTrailingOnes(); 1338 unsigned LeadZ = std::max(KnownZero.countLeadingOnes() + 1339 KnownZero2.countLeadingOnes(), 1340 BitWidth) - BitWidth; 1341 1342 TrailZ = std::min(TrailZ, BitWidth); 1343 LeadZ = std::min(LeadZ, BitWidth); 1344 KnownZero = APInt::getLowBitsSet(BitWidth, TrailZ) | 1345 APInt::getHighBitsSet(BitWidth, LeadZ); 1346 KnownZero &= Mask; 1347 return; 1348 } 1349 case ISD::UDIV: { 1350 // For the purposes of computing leading zeros we can conservatively 1351 // treat a udiv as a logical right shift by the power of 2 known to 1352 // be less than the denominator. 1353 APInt AllOnes = APInt::getAllOnesValue(BitWidth); 1354 ComputeMaskedBits(Op.getOperand(0), 1355 AllOnes, KnownZero2, KnownOne2, Depth+1); 1356 unsigned LeadZ = KnownZero2.countLeadingOnes(); 1357 1358 KnownOne2.clear(); 1359 KnownZero2.clear(); 1360 ComputeMaskedBits(Op.getOperand(1), 1361 AllOnes, KnownZero2, KnownOne2, Depth+1); 1362 unsigned RHSUnknownLeadingOnes = KnownOne2.countLeadingZeros(); 1363 if (RHSUnknownLeadingOnes != BitWidth) 1364 LeadZ = std::min(BitWidth, 1365 LeadZ + BitWidth - RHSUnknownLeadingOnes - 1); 1366 1367 KnownZero = APInt::getHighBitsSet(BitWidth, LeadZ) & Mask; 1368 return; 1369 } 1370 case ISD::SELECT: 1371 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero, KnownOne, Depth+1); 1372 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero2, KnownOne2, Depth+1); 1373 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1374 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1375 1376 // Only known if known in both the LHS and RHS. 1377 KnownOne &= KnownOne2; 1378 KnownZero &= KnownZero2; 1379 return; 1380 case ISD::SELECT_CC: 1381 ComputeMaskedBits(Op.getOperand(3), Mask, KnownZero, KnownOne, Depth+1); 1382 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero2, KnownOne2, Depth+1); 1383 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1384 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1385 1386 // Only known if known in both the LHS and RHS. 1387 KnownOne &= KnownOne2; 1388 KnownZero &= KnownZero2; 1389 return; 1390 case ISD::SETCC: 1391 // If we know the result of a setcc has the top bits zero, use this info. 1392 if (TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult && 1393 BitWidth > 1) 1394 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1); 1395 return; 1396 case ISD::SHL: 1397 // (shl X, C1) & C2 == 0 iff (X & C2 >>u C1) == 0 1398 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1399 unsigned ShAmt = SA->getValue(); 1400 1401 // If the shift count is an invalid immediate, don't do anything. 1402 if (ShAmt >= BitWidth) 1403 return; 1404 1405 ComputeMaskedBits(Op.getOperand(0), Mask.lshr(ShAmt), 1406 KnownZero, KnownOne, Depth+1); 1407 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1408 KnownZero <<= ShAmt; 1409 KnownOne <<= ShAmt; 1410 // low bits known zero. 1411 KnownZero |= APInt::getLowBitsSet(BitWidth, ShAmt); 1412 } 1413 return; 1414 case ISD::SRL: 1415 // (ushr X, C1) & C2 == 0 iff (-1 >> C1) & C2 == 0 1416 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1417 unsigned ShAmt = SA->getValue(); 1418 1419 // If the shift count is an invalid immediate, don't do anything. 1420 if (ShAmt >= BitWidth) 1421 return; 1422 1423 ComputeMaskedBits(Op.getOperand(0), (Mask << ShAmt), 1424 KnownZero, KnownOne, Depth+1); 1425 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1426 KnownZero = KnownZero.lshr(ShAmt); 1427 KnownOne = KnownOne.lshr(ShAmt); 1428 1429 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt) & Mask; 1430 KnownZero |= HighBits; // High bits known zero. 1431 } 1432 return; 1433 case ISD::SRA: 1434 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1435 unsigned ShAmt = SA->getValue(); 1436 1437 // If the shift count is an invalid immediate, don't do anything. 1438 if (ShAmt >= BitWidth) 1439 return; 1440 1441 APInt InDemandedMask = (Mask << ShAmt); 1442 // If any of the demanded bits are produced by the sign extension, we also 1443 // demand the input sign bit. 1444 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt) & Mask; 1445 if (HighBits.getBoolValue()) 1446 InDemandedMask |= APInt::getSignBit(BitWidth); 1447 1448 ComputeMaskedBits(Op.getOperand(0), InDemandedMask, KnownZero, KnownOne, 1449 Depth+1); 1450 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1451 KnownZero = KnownZero.lshr(ShAmt); 1452 KnownOne = KnownOne.lshr(ShAmt); 1453 1454 // Handle the sign bits. 1455 APInt SignBit = APInt::getSignBit(BitWidth); 1456 SignBit = SignBit.lshr(ShAmt); // Adjust to where it is now in the mask. 1457 1458 if (KnownZero.intersects(SignBit)) { 1459 KnownZero |= HighBits; // New bits are known zero. 1460 } else if (KnownOne.intersects(SignBit)) { 1461 KnownOne |= HighBits; // New bits are known one. 1462 } 1463 } 1464 return; 1465 case ISD::SIGN_EXTEND_INREG: { 1466 MVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1467 unsigned EBits = EVT.getSizeInBits(); 1468 1469 // Sign extension. Compute the demanded bits in the result that are not 1470 // present in the input. 1471 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - EBits) & Mask; 1472 1473 APInt InSignBit = APInt::getSignBit(EBits); 1474 APInt InputDemandedBits = Mask & APInt::getLowBitsSet(BitWidth, EBits); 1475 1476 // If the sign extended bits are demanded, we know that the sign 1477 // bit is demanded. 1478 InSignBit.zext(BitWidth); 1479 if (NewBits.getBoolValue()) 1480 InputDemandedBits |= InSignBit; 1481 1482 ComputeMaskedBits(Op.getOperand(0), InputDemandedBits, 1483 KnownZero, KnownOne, Depth+1); 1484 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1485 1486 // If the sign bit of the input is known set or clear, then we know the 1487 // top bits of the result. 1488 if (KnownZero.intersects(InSignBit)) { // Input sign bit known clear 1489 KnownZero |= NewBits; 1490 KnownOne &= ~NewBits; 1491 } else if (KnownOne.intersects(InSignBit)) { // Input sign bit known set 1492 KnownOne |= NewBits; 1493 KnownZero &= ~NewBits; 1494 } else { // Input sign bit unknown 1495 KnownZero &= ~NewBits; 1496 KnownOne &= ~NewBits; 1497 } 1498 return; 1499 } 1500 case ISD::CTTZ: 1501 case ISD::CTLZ: 1502 case ISD::CTPOP: { 1503 unsigned LowBits = Log2_32(BitWidth)+1; 1504 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - LowBits); 1505 KnownOne.clear(); 1506 return; 1507 } 1508 case ISD::LOAD: { 1509 if (ISD::isZEXTLoad(Op.Val)) { 1510 LoadSDNode *LD = cast<LoadSDNode>(Op); 1511 MVT VT = LD->getMemoryVT(); 1512 unsigned MemBits = VT.getSizeInBits(); 1513 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits) & Mask; 1514 } 1515 return; 1516 } 1517 case ISD::ZERO_EXTEND: { 1518 MVT InVT = Op.getOperand(0).getValueType(); 1519 unsigned InBits = InVT.getSizeInBits(); 1520 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - InBits) & Mask; 1521 APInt InMask = Mask; 1522 InMask.trunc(InBits); 1523 KnownZero.trunc(InBits); 1524 KnownOne.trunc(InBits); 1525 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1526 KnownZero.zext(BitWidth); 1527 KnownOne.zext(BitWidth); 1528 KnownZero |= NewBits; 1529 return; 1530 } 1531 case ISD::SIGN_EXTEND: { 1532 MVT InVT = Op.getOperand(0).getValueType(); 1533 unsigned InBits = InVT.getSizeInBits(); 1534 APInt InSignBit = APInt::getSignBit(InBits); 1535 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - InBits) & Mask; 1536 APInt InMask = Mask; 1537 InMask.trunc(InBits); 1538 1539 // If any of the sign extended bits are demanded, we know that the sign 1540 // bit is demanded. Temporarily set this bit in the mask for our callee. 1541 if (NewBits.getBoolValue()) 1542 InMask |= InSignBit; 1543 1544 KnownZero.trunc(InBits); 1545 KnownOne.trunc(InBits); 1546 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1547 1548 // Note if the sign bit is known to be zero or one. 1549 bool SignBitKnownZero = KnownZero.isNegative(); 1550 bool SignBitKnownOne = KnownOne.isNegative(); 1551 assert(!(SignBitKnownZero && SignBitKnownOne) && 1552 "Sign bit can't be known to be both zero and one!"); 1553 1554 // If the sign bit wasn't actually demanded by our caller, we don't 1555 // want it set in the KnownZero and KnownOne result values. Reset the 1556 // mask and reapply it to the result values. 1557 InMask = Mask; 1558 InMask.trunc(InBits); 1559 KnownZero &= InMask; 1560 KnownOne &= InMask; 1561 1562 KnownZero.zext(BitWidth); 1563 KnownOne.zext(BitWidth); 1564 1565 // If the sign bit is known zero or one, the top bits match. 1566 if (SignBitKnownZero) 1567 KnownZero |= NewBits; 1568 else if (SignBitKnownOne) 1569 KnownOne |= NewBits; 1570 return; 1571 } 1572 case ISD::ANY_EXTEND: { 1573 MVT InVT = Op.getOperand(0).getValueType(); 1574 unsigned InBits = InVT.getSizeInBits(); 1575 APInt InMask = Mask; 1576 InMask.trunc(InBits); 1577 KnownZero.trunc(InBits); 1578 KnownOne.trunc(InBits); 1579 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1580 KnownZero.zext(BitWidth); 1581 KnownOne.zext(BitWidth); 1582 return; 1583 } 1584 case ISD::TRUNCATE: { 1585 MVT InVT = Op.getOperand(0).getValueType(); 1586 unsigned InBits = InVT.getSizeInBits(); 1587 APInt InMask = Mask; 1588 InMask.zext(InBits); 1589 KnownZero.zext(InBits); 1590 KnownOne.zext(InBits); 1591 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1592 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1593 KnownZero.trunc(BitWidth); 1594 KnownOne.trunc(BitWidth); 1595 break; 1596 } 1597 case ISD::AssertZext: { 1598 MVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1599 APInt InMask = APInt::getLowBitsSet(BitWidth, VT.getSizeInBits()); 1600 ComputeMaskedBits(Op.getOperand(0), Mask & InMask, KnownZero, 1601 KnownOne, Depth+1); 1602 KnownZero |= (~InMask) & Mask; 1603 return; 1604 } 1605 case ISD::FGETSIGN: 1606 // All bits are zero except the low bit. 1607 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - 1); 1608 return; 1609 1610 case ISD::SUB: { 1611 if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) { 1612 // We know that the top bits of C-X are clear if X contains less bits 1613 // than C (i.e. no wrap-around can happen). For example, 20-X is 1614 // positive if we can prove that X is >= 0 and < 16. 1615 if (CLHS->getAPIntValue().isNonNegative()) { 1616 unsigned NLZ = (CLHS->getAPIntValue()+1).countLeadingZeros(); 1617 // NLZ can't be BitWidth with no sign bit 1618 APInt MaskV = APInt::getHighBitsSet(BitWidth, NLZ+1); 1619 ComputeMaskedBits(Op.getOperand(1), MaskV, KnownZero2, KnownOne2, 1620 Depth+1); 1621 1622 // If all of the MaskV bits are known to be zero, then we know the 1623 // output top bits are zero, because we now know that the output is 1624 // from [0-C]. 1625 if ((KnownZero2 & MaskV) == MaskV) { 1626 unsigned NLZ2 = CLHS->getAPIntValue().countLeadingZeros(); 1627 // Top bits known zero. 1628 KnownZero = APInt::getHighBitsSet(BitWidth, NLZ2) & Mask; 1629 } 1630 } 1631 } 1632 } 1633 // fall through 1634 case ISD::ADD: { 1635 // Output known-0 bits are known if clear or set in both the low clear bits 1636 // common to both LHS & RHS. For example, 8+(X<<3) is known to have the 1637 // low 3 bits clear. 1638 APInt Mask2 = APInt::getLowBitsSet(BitWidth, Mask.countTrailingOnes()); 1639 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero2, KnownOne2, Depth+1); 1640 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1641 unsigned KnownZeroOut = KnownZero2.countTrailingOnes(); 1642 1643 ComputeMaskedBits(Op.getOperand(1), Mask2, KnownZero2, KnownOne2, Depth+1); 1644 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1645 KnownZeroOut = std::min(KnownZeroOut, 1646 KnownZero2.countTrailingOnes()); 1647 1648 KnownZero |= APInt::getLowBitsSet(BitWidth, KnownZeroOut); 1649 return; 1650 } 1651 case ISD::SREM: 1652 if (ConstantSDNode *Rem = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1653 const APInt &RA = Rem->getAPIntValue(); 1654 if (RA.isPowerOf2() || (-RA).isPowerOf2()) { 1655 APInt LowBits = RA.isStrictlyPositive() ? (RA - 1) : ~RA; 1656 APInt Mask2 = LowBits | APInt::getSignBit(BitWidth); 1657 ComputeMaskedBits(Op.getOperand(0), Mask2,KnownZero2,KnownOne2,Depth+1); 1658 1659 // If the sign bit of the first operand is zero, the sign bit of 1660 // the result is zero. If the first operand has no one bits below 1661 // the second operand's single 1 bit, its sign will be zero. 1662 if (KnownZero2[BitWidth-1] || ((KnownZero2 & LowBits) == LowBits)) 1663 KnownZero2 |= ~LowBits; 1664 1665 KnownZero |= KnownZero2 & Mask; 1666 1667 assert((KnownZero & KnownOne) == 0&&"Bits known to be one AND zero?"); 1668 } 1669 } 1670 return; 1671 case ISD::UREM: { 1672 if (ConstantSDNode *Rem = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1673 const APInt &RA = Rem->getAPIntValue(); 1674 if (RA.isPowerOf2()) { 1675 APInt LowBits = (RA - 1); 1676 APInt Mask2 = LowBits & Mask; 1677 KnownZero |= ~LowBits & Mask; 1678 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero, KnownOne,Depth+1); 1679 assert((KnownZero & KnownOne) == 0&&"Bits known to be one AND zero?"); 1680 break; 1681 } 1682 } 1683 1684 // Since the result is less than or equal to either operand, any leading 1685 // zero bits in either operand must also exist in the result. 1686 APInt AllOnes = APInt::getAllOnesValue(BitWidth); 1687 ComputeMaskedBits(Op.getOperand(0), AllOnes, KnownZero, KnownOne, 1688 Depth+1); 1689 ComputeMaskedBits(Op.getOperand(1), AllOnes, KnownZero2, KnownOne2, 1690 Depth+1); 1691 1692 uint32_t Leaders = std::max(KnownZero.countLeadingOnes(), 1693 KnownZero2.countLeadingOnes()); 1694 KnownOne.clear(); 1695 KnownZero = APInt::getHighBitsSet(BitWidth, Leaders) & Mask; 1696 return; 1697 } 1698 default: 1699 // Allow the target to implement this method for its nodes. 1700 if (Op.getOpcode() >= ISD::BUILTIN_OP_END) { 1701 case ISD::INTRINSIC_WO_CHAIN: 1702 case ISD::INTRINSIC_W_CHAIN: 1703 case ISD::INTRINSIC_VOID: 1704 TLI.computeMaskedBitsForTargetNode(Op, Mask, KnownZero, KnownOne, *this); 1705 } 1706 return; 1707 } 1708} 1709 1710/// ComputeNumSignBits - Return the number of times the sign bit of the 1711/// register is replicated into the other bits. We know that at least 1 bit 1712/// is always equal to the sign bit (itself), but other cases can give us 1713/// information. For example, immediately after an "SRA X, 2", we know that 1714/// the top 3 bits are all equal to each other, so we return 3. 1715unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, unsigned Depth) const{ 1716 MVT VT = Op.getValueType(); 1717 assert(VT.isInteger() && "Invalid VT!"); 1718 unsigned VTBits = VT.getSizeInBits(); 1719 unsigned Tmp, Tmp2; 1720 unsigned FirstAnswer = 1; 1721 1722 if (Depth == 6) 1723 return 1; // Limit search depth. 1724 1725 switch (Op.getOpcode()) { 1726 default: break; 1727 case ISD::AssertSext: 1728 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); 1729 return VTBits-Tmp+1; 1730 case ISD::AssertZext: 1731 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); 1732 return VTBits-Tmp; 1733 1734 case ISD::Constant: { 1735 const APInt &Val = cast<ConstantSDNode>(Op)->getAPIntValue(); 1736 // If negative, return # leading ones. 1737 if (Val.isNegative()) 1738 return Val.countLeadingOnes(); 1739 1740 // Return # leading zeros. 1741 return Val.countLeadingZeros(); 1742 } 1743 1744 case ISD::SIGN_EXTEND: 1745 Tmp = VTBits-Op.getOperand(0).getValueType().getSizeInBits(); 1746 return ComputeNumSignBits(Op.getOperand(0), Depth+1) + Tmp; 1747 1748 case ISD::SIGN_EXTEND_INREG: 1749 // Max of the input and what this extends. 1750 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); 1751 Tmp = VTBits-Tmp+1; 1752 1753 Tmp2 = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1754 return std::max(Tmp, Tmp2); 1755 1756 case ISD::SRA: 1757 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1758 // SRA X, C -> adds C sign bits. 1759 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1760 Tmp += C->getValue(); 1761 if (Tmp > VTBits) Tmp = VTBits; 1762 } 1763 return Tmp; 1764 case ISD::SHL: 1765 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1766 // shl destroys sign bits. 1767 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1768 if (C->getValue() >= VTBits || // Bad shift. 1769 C->getValue() >= Tmp) break; // Shifted all sign bits out. 1770 return Tmp - C->getValue(); 1771 } 1772 break; 1773 case ISD::AND: 1774 case ISD::OR: 1775 case ISD::XOR: // NOT is handled here. 1776 // Logical binary ops preserve the number of sign bits at the worst. 1777 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1778 if (Tmp != 1) { 1779 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 1780 FirstAnswer = std::min(Tmp, Tmp2); 1781 // We computed what we know about the sign bits as our first 1782 // answer. Now proceed to the generic code that uses 1783 // ComputeMaskedBits, and pick whichever answer is better. 1784 } 1785 break; 1786 1787 case ISD::SELECT: 1788 Tmp = ComputeNumSignBits(Op.getOperand(1), Depth+1); 1789 if (Tmp == 1) return 1; // Early out. 1790 Tmp2 = ComputeNumSignBits(Op.getOperand(2), Depth+1); 1791 return std::min(Tmp, Tmp2); 1792 1793 case ISD::SETCC: 1794 // If setcc returns 0/-1, all bits are sign bits. 1795 if (TLI.getSetCCResultContents() == 1796 TargetLowering::ZeroOrNegativeOneSetCCResult) 1797 return VTBits; 1798 break; 1799 case ISD::ROTL: 1800 case ISD::ROTR: 1801 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1802 unsigned RotAmt = C->getValue() & (VTBits-1); 1803 1804 // Handle rotate right by N like a rotate left by 32-N. 1805 if (Op.getOpcode() == ISD::ROTR) 1806 RotAmt = (VTBits-RotAmt) & (VTBits-1); 1807 1808 // If we aren't rotating out all of the known-in sign bits, return the 1809 // number that are left. This handles rotl(sext(x), 1) for example. 1810 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1811 if (Tmp > RotAmt+1) return Tmp-RotAmt; 1812 } 1813 break; 1814 case ISD::ADD: 1815 // Add can have at most one carry bit. Thus we know that the output 1816 // is, at worst, one more bit than the inputs. 1817 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1818 if (Tmp == 1) return 1; // Early out. 1819 1820 // Special case decrementing a value (ADD X, -1): 1821 if (ConstantSDNode *CRHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) 1822 if (CRHS->isAllOnesValue()) { 1823 APInt KnownZero, KnownOne; 1824 APInt Mask = APInt::getAllOnesValue(VTBits); 1825 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1); 1826 1827 // If the input is known to be 0 or 1, the output is 0/-1, which is all 1828 // sign bits set. 1829 if ((KnownZero | APInt(VTBits, 1)) == Mask) 1830 return VTBits; 1831 1832 // If we are subtracting one from a positive number, there is no carry 1833 // out of the result. 1834 if (KnownZero.isNegative()) 1835 return Tmp; 1836 } 1837 1838 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 1839 if (Tmp2 == 1) return 1; 1840 return std::min(Tmp, Tmp2)-1; 1841 break; 1842 1843 case ISD::SUB: 1844 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 1845 if (Tmp2 == 1) return 1; 1846 1847 // Handle NEG. 1848 if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) 1849 if (CLHS->isNullValue()) { 1850 APInt KnownZero, KnownOne; 1851 APInt Mask = APInt::getAllOnesValue(VTBits); 1852 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1853 // If the input is known to be 0 or 1, the output is 0/-1, which is all 1854 // sign bits set. 1855 if ((KnownZero | APInt(VTBits, 1)) == Mask) 1856 return VTBits; 1857 1858 // If the input is known to be positive (the sign bit is known clear), 1859 // the output of the NEG has the same number of sign bits as the input. 1860 if (KnownZero.isNegative()) 1861 return Tmp2; 1862 1863 // Otherwise, we treat this like a SUB. 1864 } 1865 1866 // Sub can have at most one carry bit. Thus we know that the output 1867 // is, at worst, one more bit than the inputs. 1868 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1869 if (Tmp == 1) return 1; // Early out. 1870 return std::min(Tmp, Tmp2)-1; 1871 break; 1872 case ISD::TRUNCATE: 1873 // FIXME: it's tricky to do anything useful for this, but it is an important 1874 // case for targets like X86. 1875 break; 1876 } 1877 1878 // Handle LOADX separately here. EXTLOAD case will fallthrough. 1879 if (Op.getOpcode() == ISD::LOAD) { 1880 LoadSDNode *LD = cast<LoadSDNode>(Op); 1881 unsigned ExtType = LD->getExtensionType(); 1882 switch (ExtType) { 1883 default: break; 1884 case ISD::SEXTLOAD: // '17' bits known 1885 Tmp = LD->getMemoryVT().getSizeInBits(); 1886 return VTBits-Tmp+1; 1887 case ISD::ZEXTLOAD: // '16' bits known 1888 Tmp = LD->getMemoryVT().getSizeInBits(); 1889 return VTBits-Tmp; 1890 } 1891 } 1892 1893 // Allow the target to implement this method for its nodes. 1894 if (Op.getOpcode() >= ISD::BUILTIN_OP_END || 1895 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1896 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1897 Op.getOpcode() == ISD::INTRINSIC_VOID) { 1898 unsigned NumBits = TLI.ComputeNumSignBitsForTargetNode(Op, Depth); 1899 if (NumBits > 1) FirstAnswer = std::max(FirstAnswer, NumBits); 1900 } 1901 1902 // Finally, if we can prove that the top bits of the result are 0's or 1's, 1903 // use this information. 1904 APInt KnownZero, KnownOne; 1905 APInt Mask = APInt::getAllOnesValue(VTBits); 1906 ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth); 1907 1908 if (KnownZero.isNegative()) { // sign bit is 0 1909 Mask = KnownZero; 1910 } else if (KnownOne.isNegative()) { // sign bit is 1; 1911 Mask = KnownOne; 1912 } else { 1913 // Nothing known. 1914 return FirstAnswer; 1915 } 1916 1917 // Okay, we know that the sign bit in Mask is set. Use CLZ to determine 1918 // the number of identical bits in the top of the input value. 1919 Mask = ~Mask; 1920 Mask <<= Mask.getBitWidth()-VTBits; 1921 // Return # leading zeros. We use 'min' here in case Val was zero before 1922 // shifting. We don't want to return '64' as for an i32 "0". 1923 return std::max(FirstAnswer, std::min(VTBits, Mask.countLeadingZeros())); 1924} 1925 1926 1927bool SelectionDAG::isVerifiedDebugInfoDesc(SDValue Op) const { 1928 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op); 1929 if (!GA) return false; 1930 GlobalVariable *GV = dyn_cast<GlobalVariable>(GA->getGlobal()); 1931 if (!GV) return false; 1932 MachineModuleInfo *MMI = getMachineModuleInfo(); 1933 return MMI && MMI->hasDebugInfo() && MMI->isVerified(GV); 1934} 1935 1936 1937/// getShuffleScalarElt - Returns the scalar element that will make up the ith 1938/// element of the result of the vector shuffle. 1939SDValue SelectionDAG::getShuffleScalarElt(const SDNode *N, unsigned i) { 1940 MVT VT = N->getValueType(0); 1941 SDValue PermMask = N->getOperand(2); 1942 SDValue Idx = PermMask.getOperand(i); 1943 if (Idx.getOpcode() == ISD::UNDEF) 1944 return getNode(ISD::UNDEF, VT.getVectorElementType()); 1945 unsigned Index = cast<ConstantSDNode>(Idx)->getValue(); 1946 unsigned NumElems = PermMask.getNumOperands(); 1947 SDValue V = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1); 1948 Index %= NumElems; 1949 1950 if (V.getOpcode() == ISD::BIT_CONVERT) { 1951 V = V.getOperand(0); 1952 if (V.getValueType().getVectorNumElements() != NumElems) 1953 return SDValue(); 1954 } 1955 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) 1956 return (Index == 0) ? V.getOperand(0) 1957 : getNode(ISD::UNDEF, VT.getVectorElementType()); 1958 if (V.getOpcode() == ISD::BUILD_VECTOR) 1959 return V.getOperand(Index); 1960 if (V.getOpcode() == ISD::VECTOR_SHUFFLE) 1961 return getShuffleScalarElt(V.Val, Index); 1962 return SDValue(); 1963} 1964 1965 1966/// getNode - Gets or creates the specified node. 1967/// 1968SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT) { 1969 FoldingSetNodeID ID; 1970 AddNodeIDNode(ID, Opcode, getVTList(VT), 0, 0); 1971 void *IP = 0; 1972 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1973 return SDValue(E, 0); 1974 SDNode *N = NodeAllocator.Allocate<SDNode>(); 1975 new (N) SDNode(Opcode, SDNode::getSDVTList(VT)); 1976 CSEMap.InsertNode(N, IP); 1977 1978 AllNodes.push_back(N); 1979#ifndef NDEBUG 1980 VerifyNode(N); 1981#endif 1982 return SDValue(N, 0); 1983} 1984 1985SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, SDValue Operand) { 1986 // Constant fold unary operations with an integer constant operand. 1987 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Operand.Val)) { 1988 const APInt &Val = C->getAPIntValue(); 1989 unsigned BitWidth = VT.getSizeInBits(); 1990 switch (Opcode) { 1991 default: break; 1992 case ISD::SIGN_EXTEND: 1993 return getConstant(APInt(Val).sextOrTrunc(BitWidth), VT); 1994 case ISD::ANY_EXTEND: 1995 case ISD::ZERO_EXTEND: 1996 case ISD::TRUNCATE: 1997 return getConstant(APInt(Val).zextOrTrunc(BitWidth), VT); 1998 case ISD::UINT_TO_FP: 1999 case ISD::SINT_TO_FP: { 2000 const uint64_t zero[] = {0, 0}; 2001 // No compile time operations on this type. 2002 if (VT==MVT::ppcf128) 2003 break; 2004 APFloat apf = APFloat(APInt(BitWidth, 2, zero)); 2005 (void)apf.convertFromAPInt(Val, 2006 Opcode==ISD::SINT_TO_FP, 2007 APFloat::rmNearestTiesToEven); 2008 return getConstantFP(apf, VT); 2009 } 2010 case ISD::BIT_CONVERT: 2011 if (VT == MVT::f32 && C->getValueType(0) == MVT::i32) 2012 return getConstantFP(Val.bitsToFloat(), VT); 2013 else if (VT == MVT::f64 && C->getValueType(0) == MVT::i64) 2014 return getConstantFP(Val.bitsToDouble(), VT); 2015 break; 2016 case ISD::BSWAP: 2017 return getConstant(Val.byteSwap(), VT); 2018 case ISD::CTPOP: 2019 return getConstant(Val.countPopulation(), VT); 2020 case ISD::CTLZ: 2021 return getConstant(Val.countLeadingZeros(), VT); 2022 case ISD::CTTZ: 2023 return getConstant(Val.countTrailingZeros(), VT); 2024 } 2025 } 2026 2027 // Constant fold unary operations with a floating point constant operand. 2028 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Operand.Val)) { 2029 APFloat V = C->getValueAPF(); // make copy 2030 if (VT != MVT::ppcf128 && Operand.getValueType() != MVT::ppcf128) { 2031 switch (Opcode) { 2032 case ISD::FNEG: 2033 V.changeSign(); 2034 return getConstantFP(V, VT); 2035 case ISD::FABS: 2036 V.clearSign(); 2037 return getConstantFP(V, VT); 2038 case ISD::FP_ROUND: 2039 case ISD::FP_EXTEND: 2040 // This can return overflow, underflow, or inexact; we don't care. 2041 // FIXME need to be more flexible about rounding mode. 2042 (void)V.convert(*MVTToAPFloatSemantics(VT), 2043 APFloat::rmNearestTiesToEven); 2044 return getConstantFP(V, VT); 2045 case ISD::FP_TO_SINT: 2046 case ISD::FP_TO_UINT: { 2047 integerPart x; 2048 assert(integerPartWidth >= 64); 2049 // FIXME need to be more flexible about rounding mode. 2050 APFloat::opStatus s = V.convertToInteger(&x, 64U, 2051 Opcode==ISD::FP_TO_SINT, 2052 APFloat::rmTowardZero); 2053 if (s==APFloat::opInvalidOp) // inexact is OK, in fact usual 2054 break; 2055 return getConstant(x, VT); 2056 } 2057 case ISD::BIT_CONVERT: 2058 if (VT == MVT::i32 && C->getValueType(0) == MVT::f32) 2059 return getConstant((uint32_t)V.convertToAPInt().getZExtValue(), VT); 2060 else if (VT == MVT::i64 && C->getValueType(0) == MVT::f64) 2061 return getConstant(V.convertToAPInt().getZExtValue(), VT); 2062 break; 2063 } 2064 } 2065 } 2066 2067 unsigned OpOpcode = Operand.Val->getOpcode(); 2068 switch (Opcode) { 2069 case ISD::TokenFactor: 2070 return Operand; // Factor of one node? No need. 2071 case ISD::FP_ROUND: assert(0 && "Invalid method to make FP_ROUND node"); 2072 case ISD::FP_EXTEND: 2073 assert(VT.isFloatingPoint() && 2074 Operand.getValueType().isFloatingPoint() && "Invalid FP cast!"); 2075 if (Operand.getValueType() == VT) return Operand; // noop conversion. 2076 if (Operand.getOpcode() == ISD::UNDEF) 2077 return getNode(ISD::UNDEF, VT); 2078 break; 2079 case ISD::SIGN_EXTEND: 2080 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2081 "Invalid SIGN_EXTEND!"); 2082 if (Operand.getValueType() == VT) return Operand; // noop extension 2083 assert(Operand.getValueType().bitsLT(VT) 2084 && "Invalid sext node, dst < src!"); 2085 if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND) 2086 return getNode(OpOpcode, VT, Operand.Val->getOperand(0)); 2087 break; 2088 case ISD::ZERO_EXTEND: 2089 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2090 "Invalid ZERO_EXTEND!"); 2091 if (Operand.getValueType() == VT) return Operand; // noop extension 2092 assert(Operand.getValueType().bitsLT(VT) 2093 && "Invalid zext node, dst < src!"); 2094 if (OpOpcode == ISD::ZERO_EXTEND) // (zext (zext x)) -> (zext x) 2095 return getNode(ISD::ZERO_EXTEND, VT, Operand.Val->getOperand(0)); 2096 break; 2097 case ISD::ANY_EXTEND: 2098 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2099 "Invalid ANY_EXTEND!"); 2100 if (Operand.getValueType() == VT) return Operand; // noop extension 2101 assert(Operand.getValueType().bitsLT(VT) 2102 && "Invalid anyext node, dst < src!"); 2103 if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND) 2104 // (ext (zext x)) -> (zext x) and (ext (sext x)) -> (sext x) 2105 return getNode(OpOpcode, VT, Operand.Val->getOperand(0)); 2106 break; 2107 case ISD::TRUNCATE: 2108 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2109 "Invalid TRUNCATE!"); 2110 if (Operand.getValueType() == VT) return Operand; // noop truncate 2111 assert(Operand.getValueType().bitsGT(VT) 2112 && "Invalid truncate node, src < dst!"); 2113 if (OpOpcode == ISD::TRUNCATE) 2114 return getNode(ISD::TRUNCATE, VT, Operand.Val->getOperand(0)); 2115 else if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND || 2116 OpOpcode == ISD::ANY_EXTEND) { 2117 // If the source is smaller than the dest, we still need an extend. 2118 if (Operand.Val->getOperand(0).getValueType().bitsLT(VT)) 2119 return getNode(OpOpcode, VT, Operand.Val->getOperand(0)); 2120 else if (Operand.Val->getOperand(0).getValueType().bitsGT(VT)) 2121 return getNode(ISD::TRUNCATE, VT, Operand.Val->getOperand(0)); 2122 else 2123 return Operand.Val->getOperand(0); 2124 } 2125 break; 2126 case ISD::BIT_CONVERT: 2127 // Basic sanity checking. 2128 assert(VT.getSizeInBits() == Operand.getValueType().getSizeInBits() 2129 && "Cannot BIT_CONVERT between types of different sizes!"); 2130 if (VT == Operand.getValueType()) return Operand; // noop conversion. 2131 if (OpOpcode == ISD::BIT_CONVERT) // bitconv(bitconv(x)) -> bitconv(x) 2132 return getNode(ISD::BIT_CONVERT, VT, Operand.getOperand(0)); 2133 if (OpOpcode == ISD::UNDEF) 2134 return getNode(ISD::UNDEF, VT); 2135 break; 2136 case ISD::SCALAR_TO_VECTOR: 2137 assert(VT.isVector() && !Operand.getValueType().isVector() && 2138 VT.getVectorElementType() == Operand.getValueType() && 2139 "Illegal SCALAR_TO_VECTOR node!"); 2140 if (OpOpcode == ISD::UNDEF) 2141 return getNode(ISD::UNDEF, VT); 2142 // scalar_to_vector(extract_vector_elt V, 0) -> V, top bits are undefined. 2143 if (OpOpcode == ISD::EXTRACT_VECTOR_ELT && 2144 isa<ConstantSDNode>(Operand.getOperand(1)) && 2145 Operand.getConstantOperandVal(1) == 0 && 2146 Operand.getOperand(0).getValueType() == VT) 2147 return Operand.getOperand(0); 2148 break; 2149 case ISD::FNEG: 2150 if (OpOpcode == ISD::FSUB) // -(X-Y) -> (Y-X) 2151 return getNode(ISD::FSUB, VT, Operand.Val->getOperand(1), 2152 Operand.Val->getOperand(0)); 2153 if (OpOpcode == ISD::FNEG) // --X -> X 2154 return Operand.Val->getOperand(0); 2155 break; 2156 case ISD::FABS: 2157 if (OpOpcode == ISD::FNEG) // abs(-X) -> abs(X) 2158 return getNode(ISD::FABS, VT, Operand.Val->getOperand(0)); 2159 break; 2160 } 2161 2162 SDNode *N; 2163 SDVTList VTs = getVTList(VT); 2164 if (VT != MVT::Flag) { // Don't CSE flag producing nodes 2165 FoldingSetNodeID ID; 2166 SDValue Ops[1] = { Operand }; 2167 AddNodeIDNode(ID, Opcode, VTs, Ops, 1); 2168 void *IP = 0; 2169 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2170 return SDValue(E, 0); 2171 N = NodeAllocator.Allocate<UnarySDNode>(); 2172 new (N) UnarySDNode(Opcode, VTs, Operand); 2173 CSEMap.InsertNode(N, IP); 2174 } else { 2175 N = NodeAllocator.Allocate<UnarySDNode>(); 2176 new (N) UnarySDNode(Opcode, VTs, Operand); 2177 } 2178 2179 AllNodes.push_back(N); 2180#ifndef NDEBUG 2181 VerifyNode(N); 2182#endif 2183 return SDValue(N, 0); 2184} 2185 2186SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, 2187 SDValue N1, SDValue N2) { 2188 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 2189 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 2190 switch (Opcode) { 2191 default: break; 2192 case ISD::TokenFactor: 2193 assert(VT == MVT::Other && N1.getValueType() == MVT::Other && 2194 N2.getValueType() == MVT::Other && "Invalid token factor!"); 2195 // Fold trivial token factors. 2196 if (N1.getOpcode() == ISD::EntryToken) return N2; 2197 if (N2.getOpcode() == ISD::EntryToken) return N1; 2198 break; 2199 case ISD::AND: 2200 assert(VT.isInteger() && N1.getValueType() == N2.getValueType() && 2201 N1.getValueType() == VT && "Binary operator types must match!"); 2202 // (X & 0) -> 0. This commonly occurs when legalizing i64 values, so it's 2203 // worth handling here. 2204 if (N2C && N2C->isNullValue()) 2205 return N2; 2206 if (N2C && N2C->isAllOnesValue()) // X & -1 -> X 2207 return N1; 2208 break; 2209 case ISD::OR: 2210 case ISD::XOR: 2211 case ISD::ADD: 2212 case ISD::SUB: 2213 assert(VT.isInteger() && N1.getValueType() == N2.getValueType() && 2214 N1.getValueType() == VT && "Binary operator types must match!"); 2215 // (X ^|+- 0) -> X. This commonly occurs when legalizing i64 values, so 2216 // it's worth handling here. 2217 if (N2C && N2C->isNullValue()) 2218 return N1; 2219 break; 2220 case ISD::UDIV: 2221 case ISD::UREM: 2222 case ISD::MULHU: 2223 case ISD::MULHS: 2224 assert(VT.isInteger() && "This operator does not apply to FP types!"); 2225 // fall through 2226 case ISD::MUL: 2227 case ISD::SDIV: 2228 case ISD::SREM: 2229 case ISD::FADD: 2230 case ISD::FSUB: 2231 case ISD::FMUL: 2232 case ISD::FDIV: 2233 case ISD::FREM: 2234 assert(N1.getValueType() == N2.getValueType() && 2235 N1.getValueType() == VT && "Binary operator types must match!"); 2236 break; 2237 case ISD::FCOPYSIGN: // N1 and result must match. N1/N2 need not match. 2238 assert(N1.getValueType() == VT && 2239 N1.getValueType().isFloatingPoint() && 2240 N2.getValueType().isFloatingPoint() && 2241 "Invalid FCOPYSIGN!"); 2242 break; 2243 case ISD::SHL: 2244 case ISD::SRA: 2245 case ISD::SRL: 2246 case ISD::ROTL: 2247 case ISD::ROTR: 2248 assert(VT == N1.getValueType() && 2249 "Shift operators return type must be the same as their first arg"); 2250 assert(VT.isInteger() && N2.getValueType().isInteger() && 2251 "Shifts only work on integers"); 2252 2253 // Always fold shifts of i1 values so the code generator doesn't need to 2254 // handle them. Since we know the size of the shift has to be less than the 2255 // size of the value, the shift/rotate count is guaranteed to be zero. 2256 if (VT == MVT::i1) 2257 return N1; 2258 break; 2259 case ISD::FP_ROUND_INREG: { 2260 MVT EVT = cast<VTSDNode>(N2)->getVT(); 2261 assert(VT == N1.getValueType() && "Not an inreg round!"); 2262 assert(VT.isFloatingPoint() && EVT.isFloatingPoint() && 2263 "Cannot FP_ROUND_INREG integer types"); 2264 assert(EVT.bitsLE(VT) && "Not rounding down!"); 2265 if (cast<VTSDNode>(N2)->getVT() == VT) return N1; // Not actually rounding. 2266 break; 2267 } 2268 case ISD::FP_ROUND: 2269 assert(VT.isFloatingPoint() && 2270 N1.getValueType().isFloatingPoint() && 2271 VT.bitsLE(N1.getValueType()) && 2272 isa<ConstantSDNode>(N2) && "Invalid FP_ROUND!"); 2273 if (N1.getValueType() == VT) return N1; // noop conversion. 2274 break; 2275 case ISD::AssertSext: 2276 case ISD::AssertZext: { 2277 MVT EVT = cast<VTSDNode>(N2)->getVT(); 2278 assert(VT == N1.getValueType() && "Not an inreg extend!"); 2279 assert(VT.isInteger() && EVT.isInteger() && 2280 "Cannot *_EXTEND_INREG FP types"); 2281 assert(EVT.bitsLE(VT) && "Not extending!"); 2282 if (VT == EVT) return N1; // noop assertion. 2283 break; 2284 } 2285 case ISD::SIGN_EXTEND_INREG: { 2286 MVT EVT = cast<VTSDNode>(N2)->getVT(); 2287 assert(VT == N1.getValueType() && "Not an inreg extend!"); 2288 assert(VT.isInteger() && EVT.isInteger() && 2289 "Cannot *_EXTEND_INREG FP types"); 2290 assert(EVT.bitsLE(VT) && "Not extending!"); 2291 if (EVT == VT) return N1; // Not actually extending 2292 2293 if (N1C) { 2294 APInt Val = N1C->getAPIntValue(); 2295 unsigned FromBits = cast<VTSDNode>(N2)->getVT().getSizeInBits(); 2296 Val <<= Val.getBitWidth()-FromBits; 2297 Val = Val.ashr(Val.getBitWidth()-FromBits); 2298 return getConstant(Val, VT); 2299 } 2300 break; 2301 } 2302 case ISD::EXTRACT_VECTOR_ELT: 2303 // EXTRACT_VECTOR_ELT of an UNDEF is an UNDEF. 2304 if (N1.getOpcode() == ISD::UNDEF) 2305 return getNode(ISD::UNDEF, VT); 2306 2307 // EXTRACT_VECTOR_ELT of CONCAT_VECTORS is often formed while lowering is 2308 // expanding copies of large vectors from registers. 2309 if (N2C && 2310 N1.getOpcode() == ISD::CONCAT_VECTORS && 2311 N1.getNumOperands() > 0) { 2312 unsigned Factor = 2313 N1.getOperand(0).getValueType().getVectorNumElements(); 2314 return getNode(ISD::EXTRACT_VECTOR_ELT, VT, 2315 N1.getOperand(N2C->getValue() / Factor), 2316 getConstant(N2C->getValue() % Factor, N2.getValueType())); 2317 } 2318 2319 // EXTRACT_VECTOR_ELT of BUILD_VECTOR is often formed while lowering is 2320 // expanding large vector constants. 2321 if (N2C && N1.getOpcode() == ISD::BUILD_VECTOR) 2322 return N1.getOperand(N2C->getValue()); 2323 2324 // EXTRACT_VECTOR_ELT of INSERT_VECTOR_ELT is often formed when vector 2325 // operations are lowered to scalars. 2326 if (N1.getOpcode() == ISD::INSERT_VECTOR_ELT) { 2327 if (N1.getOperand(2) == N2) 2328 return N1.getOperand(1); 2329 else 2330 return getNode(ISD::EXTRACT_VECTOR_ELT, VT, N1.getOperand(0), N2); 2331 } 2332 break; 2333 case ISD::EXTRACT_ELEMENT: 2334 assert(N2C && (unsigned)N2C->getValue() < 2 && "Bad EXTRACT_ELEMENT!"); 2335 assert(!N1.getValueType().isVector() && !VT.isVector() && 2336 (N1.getValueType().isInteger() == VT.isInteger()) && 2337 "Wrong types for EXTRACT_ELEMENT!"); 2338 2339 // EXTRACT_ELEMENT of BUILD_PAIR is often formed while legalize is expanding 2340 // 64-bit integers into 32-bit parts. Instead of building the extract of 2341 // the BUILD_PAIR, only to have legalize rip it apart, just do it now. 2342 if (N1.getOpcode() == ISD::BUILD_PAIR) 2343 return N1.getOperand(N2C->getValue()); 2344 2345 // EXTRACT_ELEMENT of a constant int is also very common. 2346 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) { 2347 unsigned ElementSize = VT.getSizeInBits(); 2348 unsigned Shift = ElementSize * N2C->getValue(); 2349 APInt ShiftedVal = C->getAPIntValue().lshr(Shift); 2350 return getConstant(ShiftedVal.trunc(ElementSize), VT); 2351 } 2352 break; 2353 case ISD::EXTRACT_SUBVECTOR: 2354 if (N1.getValueType() == VT) // Trivial extraction. 2355 return N1; 2356 break; 2357 } 2358 2359 if (N1C) { 2360 if (N2C) { 2361 const APInt &C1 = N1C->getAPIntValue(), &C2 = N2C->getAPIntValue(); 2362 switch (Opcode) { 2363 case ISD::ADD: return getConstant(C1 + C2, VT); 2364 case ISD::SUB: return getConstant(C1 - C2, VT); 2365 case ISD::MUL: return getConstant(C1 * C2, VT); 2366 case ISD::UDIV: 2367 if (C2.getBoolValue()) return getConstant(C1.udiv(C2), VT); 2368 break; 2369 case ISD::UREM : 2370 if (C2.getBoolValue()) return getConstant(C1.urem(C2), VT); 2371 break; 2372 case ISD::SDIV : 2373 if (C2.getBoolValue()) return getConstant(C1.sdiv(C2), VT); 2374 break; 2375 case ISD::SREM : 2376 if (C2.getBoolValue()) return getConstant(C1.srem(C2), VT); 2377 break; 2378 case ISD::AND : return getConstant(C1 & C2, VT); 2379 case ISD::OR : return getConstant(C1 | C2, VT); 2380 case ISD::XOR : return getConstant(C1 ^ C2, VT); 2381 case ISD::SHL : return getConstant(C1 << C2, VT); 2382 case ISD::SRL : return getConstant(C1.lshr(C2), VT); 2383 case ISD::SRA : return getConstant(C1.ashr(C2), VT); 2384 case ISD::ROTL : return getConstant(C1.rotl(C2), VT); 2385 case ISD::ROTR : return getConstant(C1.rotr(C2), VT); 2386 default: break; 2387 } 2388 } else { // Cannonicalize constant to RHS if commutative 2389 if (isCommutativeBinOp(Opcode)) { 2390 std::swap(N1C, N2C); 2391 std::swap(N1, N2); 2392 } 2393 } 2394 } 2395 2396 // Constant fold FP operations. 2397 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1.Val); 2398 ConstantFPSDNode *N2CFP = dyn_cast<ConstantFPSDNode>(N2.Val); 2399 if (N1CFP) { 2400 if (!N2CFP && isCommutativeBinOp(Opcode)) { 2401 // Cannonicalize constant to RHS if commutative 2402 std::swap(N1CFP, N2CFP); 2403 std::swap(N1, N2); 2404 } else if (N2CFP && VT != MVT::ppcf128) { 2405 APFloat V1 = N1CFP->getValueAPF(), V2 = N2CFP->getValueAPF(); 2406 APFloat::opStatus s; 2407 switch (Opcode) { 2408 case ISD::FADD: 2409 s = V1.add(V2, APFloat::rmNearestTiesToEven); 2410 if (s != APFloat::opInvalidOp) 2411 return getConstantFP(V1, VT); 2412 break; 2413 case ISD::FSUB: 2414 s = V1.subtract(V2, APFloat::rmNearestTiesToEven); 2415 if (s!=APFloat::opInvalidOp) 2416 return getConstantFP(V1, VT); 2417 break; 2418 case ISD::FMUL: 2419 s = V1.multiply(V2, APFloat::rmNearestTiesToEven); 2420 if (s!=APFloat::opInvalidOp) 2421 return getConstantFP(V1, VT); 2422 break; 2423 case ISD::FDIV: 2424 s = V1.divide(V2, APFloat::rmNearestTiesToEven); 2425 if (s!=APFloat::opInvalidOp && s!=APFloat::opDivByZero) 2426 return getConstantFP(V1, VT); 2427 break; 2428 case ISD::FREM : 2429 s = V1.mod(V2, APFloat::rmNearestTiesToEven); 2430 if (s!=APFloat::opInvalidOp && s!=APFloat::opDivByZero) 2431 return getConstantFP(V1, VT); 2432 break; 2433 case ISD::FCOPYSIGN: 2434 V1.copySign(V2); 2435 return getConstantFP(V1, VT); 2436 default: break; 2437 } 2438 } 2439 } 2440 2441 // Canonicalize an UNDEF to the RHS, even over a constant. 2442 if (N1.getOpcode() == ISD::UNDEF) { 2443 if (isCommutativeBinOp(Opcode)) { 2444 std::swap(N1, N2); 2445 } else { 2446 switch (Opcode) { 2447 case ISD::FP_ROUND_INREG: 2448 case ISD::SIGN_EXTEND_INREG: 2449 case ISD::SUB: 2450 case ISD::FSUB: 2451 case ISD::FDIV: 2452 case ISD::FREM: 2453 case ISD::SRA: 2454 return N1; // fold op(undef, arg2) -> undef 2455 case ISD::UDIV: 2456 case ISD::SDIV: 2457 case ISD::UREM: 2458 case ISD::SREM: 2459 case ISD::SRL: 2460 case ISD::SHL: 2461 if (!VT.isVector()) 2462 return getConstant(0, VT); // fold op(undef, arg2) -> 0 2463 // For vectors, we can't easily build an all zero vector, just return 2464 // the LHS. 2465 return N2; 2466 } 2467 } 2468 } 2469 2470 // Fold a bunch of operators when the RHS is undef. 2471 if (N2.getOpcode() == ISD::UNDEF) { 2472 switch (Opcode) { 2473 case ISD::XOR: 2474 if (N1.getOpcode() == ISD::UNDEF) 2475 // Handle undef ^ undef -> 0 special case. This is a common 2476 // idiom (misuse). 2477 return getConstant(0, VT); 2478 // fallthrough 2479 case ISD::ADD: 2480 case ISD::ADDC: 2481 case ISD::ADDE: 2482 case ISD::SUB: 2483 case ISD::FADD: 2484 case ISD::FSUB: 2485 case ISD::FMUL: 2486 case ISD::FDIV: 2487 case ISD::FREM: 2488 case ISD::UDIV: 2489 case ISD::SDIV: 2490 case ISD::UREM: 2491 case ISD::SREM: 2492 return N2; // fold op(arg1, undef) -> undef 2493 case ISD::MUL: 2494 case ISD::AND: 2495 case ISD::SRL: 2496 case ISD::SHL: 2497 if (!VT.isVector()) 2498 return getConstant(0, VT); // fold op(arg1, undef) -> 0 2499 // For vectors, we can't easily build an all zero vector, just return 2500 // the LHS. 2501 return N1; 2502 case ISD::OR: 2503 if (!VT.isVector()) 2504 return getConstant(VT.getIntegerVTBitMask(), VT); 2505 // For vectors, we can't easily build an all one vector, just return 2506 // the LHS. 2507 return N1; 2508 case ISD::SRA: 2509 return N1; 2510 } 2511 } 2512 2513 // Memoize this node if possible. 2514 SDNode *N; 2515 SDVTList VTs = getVTList(VT); 2516 if (VT != MVT::Flag) { 2517 SDValue Ops[] = { N1, N2 }; 2518 FoldingSetNodeID ID; 2519 AddNodeIDNode(ID, Opcode, VTs, Ops, 2); 2520 void *IP = 0; 2521 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2522 return SDValue(E, 0); 2523 N = NodeAllocator.Allocate<BinarySDNode>(); 2524 new (N) BinarySDNode(Opcode, VTs, N1, N2); 2525 CSEMap.InsertNode(N, IP); 2526 } else { 2527 N = NodeAllocator.Allocate<BinarySDNode>(); 2528 new (N) BinarySDNode(Opcode, VTs, N1, N2); 2529 } 2530 2531 AllNodes.push_back(N); 2532#ifndef NDEBUG 2533 VerifyNode(N); 2534#endif 2535 return SDValue(N, 0); 2536} 2537 2538SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, 2539 SDValue N1, SDValue N2, SDValue N3) { 2540 // Perform various simplifications. 2541 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 2542 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 2543 switch (Opcode) { 2544 case ISD::SETCC: { 2545 // Use FoldSetCC to simplify SETCC's. 2546 SDValue Simp = FoldSetCC(VT, N1, N2, cast<CondCodeSDNode>(N3)->get()); 2547 if (Simp.Val) return Simp; 2548 break; 2549 } 2550 case ISD::SELECT: 2551 if (N1C) { 2552 if (N1C->getValue()) 2553 return N2; // select true, X, Y -> X 2554 else 2555 return N3; // select false, X, Y -> Y 2556 } 2557 2558 if (N2 == N3) return N2; // select C, X, X -> X 2559 break; 2560 case ISD::BRCOND: 2561 if (N2C) { 2562 if (N2C->getValue()) // Unconditional branch 2563 return getNode(ISD::BR, MVT::Other, N1, N3); 2564 else 2565 return N1; // Never-taken branch 2566 } 2567 break; 2568 case ISD::VECTOR_SHUFFLE: 2569 assert(VT == N1.getValueType() && VT == N2.getValueType() && 2570 VT.isVector() && N3.getValueType().isVector() && 2571 N3.getOpcode() == ISD::BUILD_VECTOR && 2572 VT.getVectorNumElements() == N3.getNumOperands() && 2573 "Illegal VECTOR_SHUFFLE node!"); 2574 break; 2575 case ISD::BIT_CONVERT: 2576 // Fold bit_convert nodes from a type to themselves. 2577 if (N1.getValueType() == VT) 2578 return N1; 2579 break; 2580 } 2581 2582 // Memoize node if it doesn't produce a flag. 2583 SDNode *N; 2584 SDVTList VTs = getVTList(VT); 2585 if (VT != MVT::Flag) { 2586 SDValue Ops[] = { N1, N2, N3 }; 2587 FoldingSetNodeID ID; 2588 AddNodeIDNode(ID, Opcode, VTs, Ops, 3); 2589 void *IP = 0; 2590 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2591 return SDValue(E, 0); 2592 N = NodeAllocator.Allocate<TernarySDNode>(); 2593 new (N) TernarySDNode(Opcode, VTs, N1, N2, N3); 2594 CSEMap.InsertNode(N, IP); 2595 } else { 2596 N = NodeAllocator.Allocate<TernarySDNode>(); 2597 new (N) TernarySDNode(Opcode, VTs, N1, N2, N3); 2598 } 2599 AllNodes.push_back(N); 2600#ifndef NDEBUG 2601 VerifyNode(N); 2602#endif 2603 return SDValue(N, 0); 2604} 2605 2606SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, 2607 SDValue N1, SDValue N2, SDValue N3, 2608 SDValue N4) { 2609 SDValue Ops[] = { N1, N2, N3, N4 }; 2610 return getNode(Opcode, VT, Ops, 4); 2611} 2612 2613SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, 2614 SDValue N1, SDValue N2, SDValue N3, 2615 SDValue N4, SDValue N5) { 2616 SDValue Ops[] = { N1, N2, N3, N4, N5 }; 2617 return getNode(Opcode, VT, Ops, 5); 2618} 2619 2620/// getMemsetValue - Vectorized representation of the memset value 2621/// operand. 2622static SDValue getMemsetValue(SDValue Value, MVT VT, SelectionDAG &DAG) { 2623 unsigned NumBits = VT.isVector() ? 2624 VT.getVectorElementType().getSizeInBits() : VT.getSizeInBits(); 2625 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) { 2626 APInt Val = APInt(NumBits, C->getValue() & 255); 2627 unsigned Shift = 8; 2628 for (unsigned i = NumBits; i > 8; i >>= 1) { 2629 Val = (Val << Shift) | Val; 2630 Shift <<= 1; 2631 } 2632 if (VT.isInteger()) 2633 return DAG.getConstant(Val, VT); 2634 return DAG.getConstantFP(APFloat(Val), VT); 2635 } 2636 2637 Value = DAG.getNode(ISD::ZERO_EXTEND, VT, Value); 2638 unsigned Shift = 8; 2639 for (unsigned i = NumBits; i > 8; i >>= 1) { 2640 Value = DAG.getNode(ISD::OR, VT, 2641 DAG.getNode(ISD::SHL, VT, Value, 2642 DAG.getConstant(Shift, MVT::i8)), Value); 2643 Shift <<= 1; 2644 } 2645 2646 return Value; 2647} 2648 2649/// getMemsetStringVal - Similar to getMemsetValue. Except this is only 2650/// used when a memcpy is turned into a memset when the source is a constant 2651/// string ptr. 2652static SDValue getMemsetStringVal(MVT VT, SelectionDAG &DAG, 2653 const TargetLowering &TLI, 2654 std::string &Str, unsigned Offset) { 2655 // Handle vector with all elements zero. 2656 if (Str.empty()) { 2657 if (VT.isInteger()) 2658 return DAG.getConstant(0, VT); 2659 unsigned NumElts = VT.getVectorNumElements(); 2660 MVT EltVT = (VT.getVectorElementType() == MVT::f32) ? MVT::i32 : MVT::i64; 2661 return DAG.getNode(ISD::BIT_CONVERT, VT, 2662 DAG.getConstant(0, MVT::getVectorVT(EltVT, NumElts))); 2663 } 2664 2665 assert(!VT.isVector() && "Can't handle vector type here!"); 2666 unsigned NumBits = VT.getSizeInBits(); 2667 unsigned MSB = NumBits / 8; 2668 uint64_t Val = 0; 2669 if (TLI.isLittleEndian()) 2670 Offset = Offset + MSB - 1; 2671 for (unsigned i = 0; i != MSB; ++i) { 2672 Val = (Val << 8) | (unsigned char)Str[Offset]; 2673 Offset += TLI.isLittleEndian() ? -1 : 1; 2674 } 2675 return DAG.getConstant(Val, VT); 2676} 2677 2678/// getMemBasePlusOffset - Returns base and offset node for the 2679/// 2680static SDValue getMemBasePlusOffset(SDValue Base, unsigned Offset, 2681 SelectionDAG &DAG) { 2682 MVT VT = Base.getValueType(); 2683 return DAG.getNode(ISD::ADD, VT, Base, DAG.getConstant(Offset, VT)); 2684} 2685 2686/// isMemSrcFromString - Returns true if memcpy source is a string constant. 2687/// 2688static bool isMemSrcFromString(SDValue Src, std::string &Str) { 2689 unsigned SrcDelta = 0; 2690 GlobalAddressSDNode *G = NULL; 2691 if (Src.getOpcode() == ISD::GlobalAddress) 2692 G = cast<GlobalAddressSDNode>(Src); 2693 else if (Src.getOpcode() == ISD::ADD && 2694 Src.getOperand(0).getOpcode() == ISD::GlobalAddress && 2695 Src.getOperand(1).getOpcode() == ISD::Constant) { 2696 G = cast<GlobalAddressSDNode>(Src.getOperand(0)); 2697 SrcDelta = cast<ConstantSDNode>(Src.getOperand(1))->getValue(); 2698 } 2699 if (!G) 2700 return false; 2701 2702 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal()); 2703 if (GV && GetConstantStringInfo(GV, Str, SrcDelta, false)) 2704 return true; 2705 2706 return false; 2707} 2708 2709/// MeetsMaxMemopRequirement - Determines if the number of memory ops required 2710/// to replace the memset / memcpy is below the threshold. It also returns the 2711/// types of the sequence of memory ops to perform memset / memcpy. 2712static 2713bool MeetsMaxMemopRequirement(std::vector<MVT> &MemOps, 2714 SDValue Dst, SDValue Src, 2715 unsigned Limit, uint64_t Size, unsigned &Align, 2716 std::string &Str, bool &isSrcStr, 2717 SelectionDAG &DAG, 2718 const TargetLowering &TLI) { 2719 isSrcStr = isMemSrcFromString(Src, Str); 2720 bool isSrcConst = isa<ConstantSDNode>(Src); 2721 bool AllowUnalign = TLI.allowsUnalignedMemoryAccesses(); 2722 MVT VT= TLI.getOptimalMemOpType(Size, Align, isSrcConst, isSrcStr); 2723 if (VT != MVT::iAny) { 2724 unsigned NewAlign = (unsigned) 2725 TLI.getTargetData()->getABITypeAlignment(VT.getTypeForMVT()); 2726 // If source is a string constant, this will require an unaligned load. 2727 if (NewAlign > Align && (isSrcConst || AllowUnalign)) { 2728 if (Dst.getOpcode() != ISD::FrameIndex) { 2729 // Can't change destination alignment. It requires a unaligned store. 2730 if (AllowUnalign) 2731 VT = MVT::iAny; 2732 } else { 2733 int FI = cast<FrameIndexSDNode>(Dst)->getIndex(); 2734 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 2735 if (MFI->isFixedObjectIndex(FI)) { 2736 // Can't change destination alignment. It requires a unaligned store. 2737 if (AllowUnalign) 2738 VT = MVT::iAny; 2739 } else { 2740 // Give the stack frame object a larger alignment if needed. 2741 if (MFI->getObjectAlignment(FI) < NewAlign) 2742 MFI->setObjectAlignment(FI, NewAlign); 2743 Align = NewAlign; 2744 } 2745 } 2746 } 2747 } 2748 2749 if (VT == MVT::iAny) { 2750 if (AllowUnalign) { 2751 VT = MVT::i64; 2752 } else { 2753 switch (Align & 7) { 2754 case 0: VT = MVT::i64; break; 2755 case 4: VT = MVT::i32; break; 2756 case 2: VT = MVT::i16; break; 2757 default: VT = MVT::i8; break; 2758 } 2759 } 2760 2761 MVT LVT = MVT::i64; 2762 while (!TLI.isTypeLegal(LVT)) 2763 LVT = (MVT::SimpleValueType)(LVT.getSimpleVT() - 1); 2764 assert(LVT.isInteger()); 2765 2766 if (VT.bitsGT(LVT)) 2767 VT = LVT; 2768 } 2769 2770 unsigned NumMemOps = 0; 2771 while (Size != 0) { 2772 unsigned VTSize = VT.getSizeInBits() / 8; 2773 while (VTSize > Size) { 2774 // For now, only use non-vector load / store's for the left-over pieces. 2775 if (VT.isVector()) { 2776 VT = MVT::i64; 2777 while (!TLI.isTypeLegal(VT)) 2778 VT = (MVT::SimpleValueType)(VT.getSimpleVT() - 1); 2779 VTSize = VT.getSizeInBits() / 8; 2780 } else { 2781 VT = (MVT::SimpleValueType)(VT.getSimpleVT() - 1); 2782 VTSize >>= 1; 2783 } 2784 } 2785 2786 if (++NumMemOps > Limit) 2787 return false; 2788 MemOps.push_back(VT); 2789 Size -= VTSize; 2790 } 2791 2792 return true; 2793} 2794 2795static SDValue getMemcpyLoadsAndStores(SelectionDAG &DAG, 2796 SDValue Chain, SDValue Dst, 2797 SDValue Src, uint64_t Size, 2798 unsigned Align, bool AlwaysInline, 2799 const Value *DstSV, uint64_t DstSVOff, 2800 const Value *SrcSV, uint64_t SrcSVOff){ 2801 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 2802 2803 // Expand memcpy to a series of load and store ops if the size operand falls 2804 // below a certain threshold. 2805 std::vector<MVT> MemOps; 2806 uint64_t Limit = -1; 2807 if (!AlwaysInline) 2808 Limit = TLI.getMaxStoresPerMemcpy(); 2809 unsigned DstAlign = Align; // Destination alignment can change. 2810 std::string Str; 2811 bool CopyFromStr; 2812 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, Limit, Size, DstAlign, 2813 Str, CopyFromStr, DAG, TLI)) 2814 return SDValue(); 2815 2816 2817 bool isZeroStr = CopyFromStr && Str.empty(); 2818 SmallVector<SDValue, 8> OutChains; 2819 unsigned NumMemOps = MemOps.size(); 2820 uint64_t SrcOff = 0, DstOff = 0; 2821 for (unsigned i = 0; i < NumMemOps; i++) { 2822 MVT VT = MemOps[i]; 2823 unsigned VTSize = VT.getSizeInBits() / 8; 2824 SDValue Value, Store; 2825 2826 if (CopyFromStr && (isZeroStr || !VT.isVector())) { 2827 // It's unlikely a store of a vector immediate can be done in a single 2828 // instruction. It would require a load from a constantpool first. 2829 // We also handle store a vector with all zero's. 2830 // FIXME: Handle other cases where store of vector immediate is done in 2831 // a single instruction. 2832 Value = getMemsetStringVal(VT, DAG, TLI, Str, SrcOff); 2833 Store = DAG.getStore(Chain, Value, 2834 getMemBasePlusOffset(Dst, DstOff, DAG), 2835 DstSV, DstSVOff + DstOff, false, DstAlign); 2836 } else { 2837 Value = DAG.getLoad(VT, Chain, 2838 getMemBasePlusOffset(Src, SrcOff, DAG), 2839 SrcSV, SrcSVOff + SrcOff, false, Align); 2840 Store = DAG.getStore(Chain, Value, 2841 getMemBasePlusOffset(Dst, DstOff, DAG), 2842 DstSV, DstSVOff + DstOff, false, DstAlign); 2843 } 2844 OutChains.push_back(Store); 2845 SrcOff += VTSize; 2846 DstOff += VTSize; 2847 } 2848 2849 return DAG.getNode(ISD::TokenFactor, MVT::Other, 2850 &OutChains[0], OutChains.size()); 2851} 2852 2853static SDValue getMemmoveLoadsAndStores(SelectionDAG &DAG, 2854 SDValue Chain, SDValue Dst, 2855 SDValue Src, uint64_t Size, 2856 unsigned Align, bool AlwaysInline, 2857 const Value *DstSV, uint64_t DstSVOff, 2858 const Value *SrcSV, uint64_t SrcSVOff){ 2859 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 2860 2861 // Expand memmove to a series of load and store ops if the size operand falls 2862 // below a certain threshold. 2863 std::vector<MVT> MemOps; 2864 uint64_t Limit = -1; 2865 if (!AlwaysInline) 2866 Limit = TLI.getMaxStoresPerMemmove(); 2867 unsigned DstAlign = Align; // Destination alignment can change. 2868 std::string Str; 2869 bool CopyFromStr; 2870 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, Limit, Size, DstAlign, 2871 Str, CopyFromStr, DAG, TLI)) 2872 return SDValue(); 2873 2874 uint64_t SrcOff = 0, DstOff = 0; 2875 2876 SmallVector<SDValue, 8> LoadValues; 2877 SmallVector<SDValue, 8> LoadChains; 2878 SmallVector<SDValue, 8> OutChains; 2879 unsigned NumMemOps = MemOps.size(); 2880 for (unsigned i = 0; i < NumMemOps; i++) { 2881 MVT VT = MemOps[i]; 2882 unsigned VTSize = VT.getSizeInBits() / 8; 2883 SDValue Value, Store; 2884 2885 Value = DAG.getLoad(VT, Chain, 2886 getMemBasePlusOffset(Src, SrcOff, DAG), 2887 SrcSV, SrcSVOff + SrcOff, false, Align); 2888 LoadValues.push_back(Value); 2889 LoadChains.push_back(Value.getValue(1)); 2890 SrcOff += VTSize; 2891 } 2892 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 2893 &LoadChains[0], LoadChains.size()); 2894 OutChains.clear(); 2895 for (unsigned i = 0; i < NumMemOps; i++) { 2896 MVT VT = MemOps[i]; 2897 unsigned VTSize = VT.getSizeInBits() / 8; 2898 SDValue Value, Store; 2899 2900 Store = DAG.getStore(Chain, LoadValues[i], 2901 getMemBasePlusOffset(Dst, DstOff, DAG), 2902 DstSV, DstSVOff + DstOff, false, DstAlign); 2903 OutChains.push_back(Store); 2904 DstOff += VTSize; 2905 } 2906 2907 return DAG.getNode(ISD::TokenFactor, MVT::Other, 2908 &OutChains[0], OutChains.size()); 2909} 2910 2911static SDValue getMemsetStores(SelectionDAG &DAG, 2912 SDValue Chain, SDValue Dst, 2913 SDValue Src, uint64_t Size, 2914 unsigned Align, 2915 const Value *DstSV, uint64_t DstSVOff) { 2916 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 2917 2918 // Expand memset to a series of load/store ops if the size operand 2919 // falls below a certain threshold. 2920 std::vector<MVT> MemOps; 2921 std::string Str; 2922 bool CopyFromStr; 2923 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, TLI.getMaxStoresPerMemset(), 2924 Size, Align, Str, CopyFromStr, DAG, TLI)) 2925 return SDValue(); 2926 2927 SmallVector<SDValue, 8> OutChains; 2928 uint64_t DstOff = 0; 2929 2930 unsigned NumMemOps = MemOps.size(); 2931 for (unsigned i = 0; i < NumMemOps; i++) { 2932 MVT VT = MemOps[i]; 2933 unsigned VTSize = VT.getSizeInBits() / 8; 2934 SDValue Value = getMemsetValue(Src, VT, DAG); 2935 SDValue Store = DAG.getStore(Chain, Value, 2936 getMemBasePlusOffset(Dst, DstOff, DAG), 2937 DstSV, DstSVOff + DstOff); 2938 OutChains.push_back(Store); 2939 DstOff += VTSize; 2940 } 2941 2942 return DAG.getNode(ISD::TokenFactor, MVT::Other, 2943 &OutChains[0], OutChains.size()); 2944} 2945 2946SDValue SelectionDAG::getMemcpy(SDValue Chain, SDValue Dst, 2947 SDValue Src, SDValue Size, 2948 unsigned Align, bool AlwaysInline, 2949 const Value *DstSV, uint64_t DstSVOff, 2950 const Value *SrcSV, uint64_t SrcSVOff) { 2951 2952 // Check to see if we should lower the memcpy to loads and stores first. 2953 // For cases within the target-specified limits, this is the best choice. 2954 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 2955 if (ConstantSize) { 2956 // Memcpy with size zero? Just return the original chain. 2957 if (ConstantSize->isNullValue()) 2958 return Chain; 2959 2960 SDValue Result = 2961 getMemcpyLoadsAndStores(*this, Chain, Dst, Src, ConstantSize->getValue(), 2962 Align, false, DstSV, DstSVOff, SrcSV, SrcSVOff); 2963 if (Result.Val) 2964 return Result; 2965 } 2966 2967 // Then check to see if we should lower the memcpy with target-specific 2968 // code. If the target chooses to do this, this is the next best. 2969 SDValue Result = 2970 TLI.EmitTargetCodeForMemcpy(*this, Chain, Dst, Src, Size, Align, 2971 AlwaysInline, 2972 DstSV, DstSVOff, SrcSV, SrcSVOff); 2973 if (Result.Val) 2974 return Result; 2975 2976 // If we really need inline code and the target declined to provide it, 2977 // use a (potentially long) sequence of loads and stores. 2978 if (AlwaysInline) { 2979 assert(ConstantSize && "AlwaysInline requires a constant size!"); 2980 return getMemcpyLoadsAndStores(*this, Chain, Dst, Src, 2981 ConstantSize->getValue(), Align, true, 2982 DstSV, DstSVOff, SrcSV, SrcSVOff); 2983 } 2984 2985 // Emit a library call. 2986 TargetLowering::ArgListTy Args; 2987 TargetLowering::ArgListEntry Entry; 2988 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 2989 Entry.Node = Dst; Args.push_back(Entry); 2990 Entry.Node = Src; Args.push_back(Entry); 2991 Entry.Node = Size; Args.push_back(Entry); 2992 std::pair<SDValue,SDValue> CallResult = 2993 TLI.LowerCallTo(Chain, Type::VoidTy, 2994 false, false, false, CallingConv::C, false, 2995 getExternalSymbol("memcpy", TLI.getPointerTy()), 2996 Args, *this); 2997 return CallResult.second; 2998} 2999 3000SDValue SelectionDAG::getMemmove(SDValue Chain, SDValue Dst, 3001 SDValue Src, SDValue Size, 3002 unsigned Align, 3003 const Value *DstSV, uint64_t DstSVOff, 3004 const Value *SrcSV, uint64_t SrcSVOff) { 3005 3006 // Check to see if we should lower the memmove to loads and stores first. 3007 // For cases within the target-specified limits, this is the best choice. 3008 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 3009 if (ConstantSize) { 3010 // Memmove with size zero? Just return the original chain. 3011 if (ConstantSize->isNullValue()) 3012 return Chain; 3013 3014 SDValue Result = 3015 getMemmoveLoadsAndStores(*this, Chain, Dst, Src, ConstantSize->getValue(), 3016 Align, false, DstSV, DstSVOff, SrcSV, SrcSVOff); 3017 if (Result.Val) 3018 return Result; 3019 } 3020 3021 // Then check to see if we should lower the memmove with target-specific 3022 // code. If the target chooses to do this, this is the next best. 3023 SDValue Result = 3024 TLI.EmitTargetCodeForMemmove(*this, Chain, Dst, Src, Size, Align, 3025 DstSV, DstSVOff, SrcSV, SrcSVOff); 3026 if (Result.Val) 3027 return Result; 3028 3029 // Emit a library call. 3030 TargetLowering::ArgListTy Args; 3031 TargetLowering::ArgListEntry Entry; 3032 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 3033 Entry.Node = Dst; Args.push_back(Entry); 3034 Entry.Node = Src; Args.push_back(Entry); 3035 Entry.Node = Size; Args.push_back(Entry); 3036 std::pair<SDValue,SDValue> CallResult = 3037 TLI.LowerCallTo(Chain, Type::VoidTy, 3038 false, false, false, CallingConv::C, false, 3039 getExternalSymbol("memmove", TLI.getPointerTy()), 3040 Args, *this); 3041 return CallResult.second; 3042} 3043 3044SDValue SelectionDAG::getMemset(SDValue Chain, SDValue Dst, 3045 SDValue Src, SDValue Size, 3046 unsigned Align, 3047 const Value *DstSV, uint64_t DstSVOff) { 3048 3049 // Check to see if we should lower the memset to stores first. 3050 // For cases within the target-specified limits, this is the best choice. 3051 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 3052 if (ConstantSize) { 3053 // Memset with size zero? Just return the original chain. 3054 if (ConstantSize->isNullValue()) 3055 return Chain; 3056 3057 SDValue Result = 3058 getMemsetStores(*this, Chain, Dst, Src, ConstantSize->getValue(), Align, 3059 DstSV, DstSVOff); 3060 if (Result.Val) 3061 return Result; 3062 } 3063 3064 // Then check to see if we should lower the memset with target-specific 3065 // code. If the target chooses to do this, this is the next best. 3066 SDValue Result = 3067 TLI.EmitTargetCodeForMemset(*this, Chain, Dst, Src, Size, Align, 3068 DstSV, DstSVOff); 3069 if (Result.Val) 3070 return Result; 3071 3072 // Emit a library call. 3073 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType(); 3074 TargetLowering::ArgListTy Args; 3075 TargetLowering::ArgListEntry Entry; 3076 Entry.Node = Dst; Entry.Ty = IntPtrTy; 3077 Args.push_back(Entry); 3078 // Extend or truncate the argument to be an i32 value for the call. 3079 if (Src.getValueType().bitsGT(MVT::i32)) 3080 Src = getNode(ISD::TRUNCATE, MVT::i32, Src); 3081 else 3082 Src = getNode(ISD::ZERO_EXTEND, MVT::i32, Src); 3083 Entry.Node = Src; Entry.Ty = Type::Int32Ty; Entry.isSExt = true; 3084 Args.push_back(Entry); 3085 Entry.Node = Size; Entry.Ty = IntPtrTy; Entry.isSExt = false; 3086 Args.push_back(Entry); 3087 std::pair<SDValue,SDValue> CallResult = 3088 TLI.LowerCallTo(Chain, Type::VoidTy, 3089 false, false, false, CallingConv::C, false, 3090 getExternalSymbol("memset", TLI.getPointerTy()), 3091 Args, *this); 3092 return CallResult.second; 3093} 3094 3095SDValue SelectionDAG::getAtomic(unsigned Opcode, SDValue Chain, 3096 SDValue Ptr, SDValue Cmp, 3097 SDValue Swp, const Value* PtrVal, 3098 unsigned Alignment) { 3099 assert(Opcode == ISD::ATOMIC_CMP_SWAP && "Invalid Atomic Op"); 3100 assert(Cmp.getValueType() == Swp.getValueType() && "Invalid Atomic Op Types"); 3101 3102 MVT VT = Cmp.getValueType(); 3103 3104 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3105 Alignment = getMVTAlignment(VT); 3106 3107 SDVTList VTs = getVTList(VT, MVT::Other); 3108 FoldingSetNodeID ID; 3109 SDValue Ops[] = {Chain, Ptr, Cmp, Swp}; 3110 AddNodeIDNode(ID, Opcode, VTs, Ops, 4); 3111 void* IP = 0; 3112 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3113 return SDValue(E, 0); 3114 SDNode* N = NodeAllocator.Allocate<AtomicSDNode>(); 3115 new (N) AtomicSDNode(Opcode, VTs, Chain, Ptr, Cmp, Swp, PtrVal, Alignment); 3116 CSEMap.InsertNode(N, IP); 3117 AllNodes.push_back(N); 3118 return SDValue(N, 0); 3119} 3120 3121SDValue SelectionDAG::getAtomic(unsigned Opcode, SDValue Chain, 3122 SDValue Ptr, SDValue Val, 3123 const Value* PtrVal, 3124 unsigned Alignment) { 3125 assert(( Opcode == ISD::ATOMIC_LOAD_ADD || Opcode == ISD::ATOMIC_LOAD_SUB 3126 || Opcode == ISD::ATOMIC_SWAP || Opcode == ISD::ATOMIC_LOAD_AND 3127 || Opcode == ISD::ATOMIC_LOAD_OR || Opcode == ISD::ATOMIC_LOAD_XOR 3128 || Opcode == ISD::ATOMIC_LOAD_NAND 3129 || Opcode == ISD::ATOMIC_LOAD_MIN || Opcode == ISD::ATOMIC_LOAD_MAX 3130 || Opcode == ISD::ATOMIC_LOAD_UMIN || Opcode == ISD::ATOMIC_LOAD_UMAX) 3131 && "Invalid Atomic Op"); 3132 3133 MVT VT = Val.getValueType(); 3134 3135 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3136 Alignment = getMVTAlignment(VT); 3137 3138 SDVTList VTs = getVTList(VT, MVT::Other); 3139 FoldingSetNodeID ID; 3140 SDValue Ops[] = {Chain, Ptr, Val}; 3141 AddNodeIDNode(ID, Opcode, VTs, Ops, 3); 3142 void* IP = 0; 3143 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3144 return SDValue(E, 0); 3145 SDNode* N = NodeAllocator.Allocate<AtomicSDNode>(); 3146 new (N) AtomicSDNode(Opcode, VTs, Chain, Ptr, Val, PtrVal, Alignment); 3147 CSEMap.InsertNode(N, IP); 3148 AllNodes.push_back(N); 3149 return SDValue(N, 0); 3150} 3151 3152/// getMergeValues - Create a MERGE_VALUES node from the given operands. 3153/// Allowed to return something different (and simpler) if Simplify is true. 3154SDValue SelectionDAG::getMergeValues(const SDValue *Ops, unsigned NumOps, 3155 bool Simplify) { 3156 if (Simplify && NumOps == 1) 3157 return Ops[0]; 3158 3159 SmallVector<MVT, 4> VTs; 3160 VTs.reserve(NumOps); 3161 for (unsigned i = 0; i < NumOps; ++i) 3162 VTs.push_back(Ops[i].getValueType()); 3163 return getNode(ISD::MERGE_VALUES, getVTList(&VTs[0], NumOps), Ops, NumOps); 3164} 3165 3166SDValue 3167SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, 3168 MVT VT, SDValue Chain, 3169 SDValue Ptr, SDValue Offset, 3170 const Value *SV, int SVOffset, MVT EVT, 3171 bool isVolatile, unsigned Alignment) { 3172 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3173 Alignment = getMVTAlignment(VT); 3174 3175 if (VT == EVT) { 3176 ExtType = ISD::NON_EXTLOAD; 3177 } else if (ExtType == ISD::NON_EXTLOAD) { 3178 assert(VT == EVT && "Non-extending load from different memory type!"); 3179 } else { 3180 // Extending load. 3181 if (VT.isVector()) 3182 assert(EVT == VT.getVectorElementType() && "Invalid vector extload!"); 3183 else 3184 assert(EVT.bitsLT(VT) && 3185 "Should only be an extending load, not truncating!"); 3186 assert((ExtType == ISD::EXTLOAD || VT.isInteger()) && 3187 "Cannot sign/zero extend a FP/Vector load!"); 3188 assert(VT.isInteger() == EVT.isInteger() && 3189 "Cannot convert from FP to Int or Int -> FP!"); 3190 } 3191 3192 bool Indexed = AM != ISD::UNINDEXED; 3193 assert((Indexed || Offset.getOpcode() == ISD::UNDEF) && 3194 "Unindexed load with an offset!"); 3195 3196 SDVTList VTs = Indexed ? 3197 getVTList(VT, Ptr.getValueType(), MVT::Other) : getVTList(VT, MVT::Other); 3198 SDValue Ops[] = { Chain, Ptr, Offset }; 3199 FoldingSetNodeID ID; 3200 AddNodeIDNode(ID, ISD::LOAD, VTs, Ops, 3); 3201 ID.AddInteger(AM); 3202 ID.AddInteger(ExtType); 3203 ID.AddInteger(EVT.getRawBits()); 3204 ID.AddInteger(Alignment); 3205 ID.AddInteger(isVolatile); 3206 void *IP = 0; 3207 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3208 return SDValue(E, 0); 3209 SDNode *N = NodeAllocator.Allocate<LoadSDNode>(); 3210 new (N) LoadSDNode(Ops, VTs, AM, ExtType, EVT, SV, SVOffset, 3211 Alignment, isVolatile); 3212 CSEMap.InsertNode(N, IP); 3213 AllNodes.push_back(N); 3214 return SDValue(N, 0); 3215} 3216 3217SDValue SelectionDAG::getLoad(MVT VT, 3218 SDValue Chain, SDValue Ptr, 3219 const Value *SV, int SVOffset, 3220 bool isVolatile, unsigned Alignment) { 3221 SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType()); 3222 return getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD, VT, Chain, Ptr, Undef, 3223 SV, SVOffset, VT, isVolatile, Alignment); 3224} 3225 3226SDValue SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, MVT VT, 3227 SDValue Chain, SDValue Ptr, 3228 const Value *SV, 3229 int SVOffset, MVT EVT, 3230 bool isVolatile, unsigned Alignment) { 3231 SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType()); 3232 return getLoad(ISD::UNINDEXED, ExtType, VT, Chain, Ptr, Undef, 3233 SV, SVOffset, EVT, isVolatile, Alignment); 3234} 3235 3236SDValue 3237SelectionDAG::getIndexedLoad(SDValue OrigLoad, SDValue Base, 3238 SDValue Offset, ISD::MemIndexedMode AM) { 3239 LoadSDNode *LD = cast<LoadSDNode>(OrigLoad); 3240 assert(LD->getOffset().getOpcode() == ISD::UNDEF && 3241 "Load is already a indexed load!"); 3242 return getLoad(AM, LD->getExtensionType(), OrigLoad.getValueType(), 3243 LD->getChain(), Base, Offset, LD->getSrcValue(), 3244 LD->getSrcValueOffset(), LD->getMemoryVT(), 3245 LD->isVolatile(), LD->getAlignment()); 3246} 3247 3248SDValue SelectionDAG::getStore(SDValue Chain, SDValue Val, 3249 SDValue Ptr, const Value *SV, int SVOffset, 3250 bool isVolatile, unsigned Alignment) { 3251 MVT VT = Val.getValueType(); 3252 3253 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3254 Alignment = getMVTAlignment(VT); 3255 3256 SDVTList VTs = getVTList(MVT::Other); 3257 SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType()); 3258 SDValue Ops[] = { Chain, Val, Ptr, Undef }; 3259 FoldingSetNodeID ID; 3260 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); 3261 ID.AddInteger(ISD::UNINDEXED); 3262 ID.AddInteger(false); 3263 ID.AddInteger(VT.getRawBits()); 3264 ID.AddInteger(Alignment); 3265 ID.AddInteger(isVolatile); 3266 void *IP = 0; 3267 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3268 return SDValue(E, 0); 3269 SDNode *N = NodeAllocator.Allocate<StoreSDNode>(); 3270 new (N) StoreSDNode(Ops, VTs, ISD::UNINDEXED, false, 3271 VT, SV, SVOffset, Alignment, isVolatile); 3272 CSEMap.InsertNode(N, IP); 3273 AllNodes.push_back(N); 3274 return SDValue(N, 0); 3275} 3276 3277SDValue SelectionDAG::getTruncStore(SDValue Chain, SDValue Val, 3278 SDValue Ptr, const Value *SV, 3279 int SVOffset, MVT SVT, 3280 bool isVolatile, unsigned Alignment) { 3281 MVT VT = Val.getValueType(); 3282 3283 if (VT == SVT) 3284 return getStore(Chain, Val, Ptr, SV, SVOffset, isVolatile, Alignment); 3285 3286 assert(VT.bitsGT(SVT) && "Not a truncation?"); 3287 assert(VT.isInteger() == SVT.isInteger() && 3288 "Can't do FP-INT conversion!"); 3289 3290 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3291 Alignment = getMVTAlignment(VT); 3292 3293 SDVTList VTs = getVTList(MVT::Other); 3294 SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType()); 3295 SDValue Ops[] = { Chain, Val, Ptr, Undef }; 3296 FoldingSetNodeID ID; 3297 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); 3298 ID.AddInteger(ISD::UNINDEXED); 3299 ID.AddInteger(1); 3300 ID.AddInteger(SVT.getRawBits()); 3301 ID.AddInteger(Alignment); 3302 ID.AddInteger(isVolatile); 3303 void *IP = 0; 3304 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3305 return SDValue(E, 0); 3306 SDNode *N = NodeAllocator.Allocate<StoreSDNode>(); 3307 new (N) StoreSDNode(Ops, VTs, ISD::UNINDEXED, true, 3308 SVT, SV, SVOffset, Alignment, isVolatile); 3309 CSEMap.InsertNode(N, IP); 3310 AllNodes.push_back(N); 3311 return SDValue(N, 0); 3312} 3313 3314SDValue 3315SelectionDAG::getIndexedStore(SDValue OrigStore, SDValue Base, 3316 SDValue Offset, ISD::MemIndexedMode AM) { 3317 StoreSDNode *ST = cast<StoreSDNode>(OrigStore); 3318 assert(ST->getOffset().getOpcode() == ISD::UNDEF && 3319 "Store is already a indexed store!"); 3320 SDVTList VTs = getVTList(Base.getValueType(), MVT::Other); 3321 SDValue Ops[] = { ST->getChain(), ST->getValue(), Base, Offset }; 3322 FoldingSetNodeID ID; 3323 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); 3324 ID.AddInteger(AM); 3325 ID.AddInteger(ST->isTruncatingStore()); 3326 ID.AddInteger(ST->getMemoryVT().getRawBits()); 3327 ID.AddInteger(ST->getAlignment()); 3328 ID.AddInteger(ST->isVolatile()); 3329 void *IP = 0; 3330 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3331 return SDValue(E, 0); 3332 SDNode *N = NodeAllocator.Allocate<StoreSDNode>(); 3333 new (N) StoreSDNode(Ops, VTs, AM, 3334 ST->isTruncatingStore(), ST->getMemoryVT(), 3335 ST->getSrcValue(), ST->getSrcValueOffset(), 3336 ST->getAlignment(), ST->isVolatile()); 3337 CSEMap.InsertNode(N, IP); 3338 AllNodes.push_back(N); 3339 return SDValue(N, 0); 3340} 3341 3342SDValue SelectionDAG::getVAArg(MVT VT, 3343 SDValue Chain, SDValue Ptr, 3344 SDValue SV) { 3345 SDValue Ops[] = { Chain, Ptr, SV }; 3346 return getNode(ISD::VAARG, getVTList(VT, MVT::Other), Ops, 3); 3347} 3348 3349SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, 3350 const SDUse *Ops, unsigned NumOps) { 3351 switch (NumOps) { 3352 case 0: return getNode(Opcode, VT); 3353 case 1: return getNode(Opcode, VT, Ops[0]); 3354 case 2: return getNode(Opcode, VT, Ops[0], Ops[1]); 3355 case 3: return getNode(Opcode, VT, Ops[0], Ops[1], Ops[2]); 3356 default: break; 3357 } 3358 3359 // Copy from an SDUse array into an SDValue array for use with 3360 // the regular getNode logic. 3361 SmallVector<SDValue, 8> NewOps(Ops, Ops + NumOps); 3362 return getNode(Opcode, VT, &NewOps[0], NumOps); 3363} 3364 3365SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, 3366 const SDValue *Ops, unsigned NumOps) { 3367 switch (NumOps) { 3368 case 0: return getNode(Opcode, VT); 3369 case 1: return getNode(Opcode, VT, Ops[0]); 3370 case 2: return getNode(Opcode, VT, Ops[0], Ops[1]); 3371 case 3: return getNode(Opcode, VT, Ops[0], Ops[1], Ops[2]); 3372 default: break; 3373 } 3374 3375 switch (Opcode) { 3376 default: break; 3377 case ISD::SELECT_CC: { 3378 assert(NumOps == 5 && "SELECT_CC takes 5 operands!"); 3379 assert(Ops[0].getValueType() == Ops[1].getValueType() && 3380 "LHS and RHS of condition must have same type!"); 3381 assert(Ops[2].getValueType() == Ops[3].getValueType() && 3382 "True and False arms of SelectCC must have same type!"); 3383 assert(Ops[2].getValueType() == VT && 3384 "select_cc node must be of same type as true and false value!"); 3385 break; 3386 } 3387 case ISD::BR_CC: { 3388 assert(NumOps == 5 && "BR_CC takes 5 operands!"); 3389 assert(Ops[2].getValueType() == Ops[3].getValueType() && 3390 "LHS/RHS of comparison should match types!"); 3391 break; 3392 } 3393 } 3394 3395 // Memoize nodes. 3396 SDNode *N; 3397 SDVTList VTs = getVTList(VT); 3398 if (VT != MVT::Flag) { 3399 FoldingSetNodeID ID; 3400 AddNodeIDNode(ID, Opcode, VTs, Ops, NumOps); 3401 void *IP = 0; 3402 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3403 return SDValue(E, 0); 3404 N = NodeAllocator.Allocate<SDNode>(); 3405 new (N) SDNode(Opcode, VTs, Ops, NumOps); 3406 CSEMap.InsertNode(N, IP); 3407 } else { 3408 N = NodeAllocator.Allocate<SDNode>(); 3409 new (N) SDNode(Opcode, VTs, Ops, NumOps); 3410 } 3411 AllNodes.push_back(N); 3412#ifndef NDEBUG 3413 VerifyNode(N); 3414#endif 3415 return SDValue(N, 0); 3416} 3417 3418SDValue SelectionDAG::getNode(unsigned Opcode, 3419 const std::vector<MVT> &ResultTys, 3420 const SDValue *Ops, unsigned NumOps) { 3421 return getNode(Opcode, getNodeValueTypes(ResultTys), ResultTys.size(), 3422 Ops, NumOps); 3423} 3424 3425SDValue SelectionDAG::getNode(unsigned Opcode, 3426 const MVT *VTs, unsigned NumVTs, 3427 const SDValue *Ops, unsigned NumOps) { 3428 if (NumVTs == 1) 3429 return getNode(Opcode, VTs[0], Ops, NumOps); 3430 return getNode(Opcode, makeVTList(VTs, NumVTs), Ops, NumOps); 3431} 3432 3433SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, 3434 const SDValue *Ops, unsigned NumOps) { 3435 if (VTList.NumVTs == 1) 3436 return getNode(Opcode, VTList.VTs[0], Ops, NumOps); 3437 3438 switch (Opcode) { 3439 // FIXME: figure out how to safely handle things like 3440 // int foo(int x) { return 1 << (x & 255); } 3441 // int bar() { return foo(256); } 3442#if 0 3443 case ISD::SRA_PARTS: 3444 case ISD::SRL_PARTS: 3445 case ISD::SHL_PARTS: 3446 if (N3.getOpcode() == ISD::SIGN_EXTEND_INREG && 3447 cast<VTSDNode>(N3.getOperand(1))->getVT() != MVT::i1) 3448 return getNode(Opcode, VT, N1, N2, N3.getOperand(0)); 3449 else if (N3.getOpcode() == ISD::AND) 3450 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(N3.getOperand(1))) { 3451 // If the and is only masking out bits that cannot effect the shift, 3452 // eliminate the and. 3453 unsigned NumBits = VT.getSizeInBits()*2; 3454 if ((AndRHS->getValue() & (NumBits-1)) == NumBits-1) 3455 return getNode(Opcode, VT, N1, N2, N3.getOperand(0)); 3456 } 3457 break; 3458#endif 3459 } 3460 3461 // Memoize the node unless it returns a flag. 3462 SDNode *N; 3463 if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) { 3464 FoldingSetNodeID ID; 3465 AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps); 3466 void *IP = 0; 3467 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3468 return SDValue(E, 0); 3469 if (NumOps == 1) { 3470 N = NodeAllocator.Allocate<UnarySDNode>(); 3471 new (N) UnarySDNode(Opcode, VTList, Ops[0]); 3472 } else if (NumOps == 2) { 3473 N = NodeAllocator.Allocate<BinarySDNode>(); 3474 new (N) BinarySDNode(Opcode, VTList, Ops[0], Ops[1]); 3475 } else if (NumOps == 3) { 3476 N = NodeAllocator.Allocate<TernarySDNode>(); 3477 new (N) TernarySDNode(Opcode, VTList, Ops[0], Ops[1], Ops[2]); 3478 } else { 3479 N = NodeAllocator.Allocate<SDNode>(); 3480 new (N) SDNode(Opcode, VTList, Ops, NumOps); 3481 } 3482 CSEMap.InsertNode(N, IP); 3483 } else { 3484 if (NumOps == 1) { 3485 N = NodeAllocator.Allocate<UnarySDNode>(); 3486 new (N) UnarySDNode(Opcode, VTList, Ops[0]); 3487 } else if (NumOps == 2) { 3488 N = NodeAllocator.Allocate<BinarySDNode>(); 3489 new (N) BinarySDNode(Opcode, VTList, Ops[0], Ops[1]); 3490 } else if (NumOps == 3) { 3491 N = NodeAllocator.Allocate<TernarySDNode>(); 3492 new (N) TernarySDNode(Opcode, VTList, Ops[0], Ops[1], Ops[2]); 3493 } else { 3494 N = NodeAllocator.Allocate<SDNode>(); 3495 new (N) SDNode(Opcode, VTList, Ops, NumOps); 3496 } 3497 } 3498 AllNodes.push_back(N); 3499#ifndef NDEBUG 3500 VerifyNode(N); 3501#endif 3502 return SDValue(N, 0); 3503} 3504 3505SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList) { 3506 return getNode(Opcode, VTList, 0, 0); 3507} 3508 3509SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, 3510 SDValue N1) { 3511 SDValue Ops[] = { N1 }; 3512 return getNode(Opcode, VTList, Ops, 1); 3513} 3514 3515SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, 3516 SDValue N1, SDValue N2) { 3517 SDValue Ops[] = { N1, N2 }; 3518 return getNode(Opcode, VTList, Ops, 2); 3519} 3520 3521SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, 3522 SDValue N1, SDValue N2, SDValue N3) { 3523 SDValue Ops[] = { N1, N2, N3 }; 3524 return getNode(Opcode, VTList, Ops, 3); 3525} 3526 3527SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, 3528 SDValue N1, SDValue N2, SDValue N3, 3529 SDValue N4) { 3530 SDValue Ops[] = { N1, N2, N3, N4 }; 3531 return getNode(Opcode, VTList, Ops, 4); 3532} 3533 3534SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, 3535 SDValue N1, SDValue N2, SDValue N3, 3536 SDValue N4, SDValue N5) { 3537 SDValue Ops[] = { N1, N2, N3, N4, N5 }; 3538 return getNode(Opcode, VTList, Ops, 5); 3539} 3540 3541SDVTList SelectionDAG::getVTList(MVT VT) { 3542 return makeVTList(SDNode::getValueTypeList(VT), 1); 3543} 3544 3545SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2) { 3546 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 3547 E = VTList.rend(); I != E; ++I) 3548 if (I->NumVTs == 2 && I->VTs[0] == VT1 && I->VTs[1] == VT2) 3549 return *I; 3550 3551 MVT *Array = Allocator.Allocate<MVT>(2); 3552 Array[0] = VT1; 3553 Array[1] = VT2; 3554 SDVTList Result = makeVTList(Array, 2); 3555 VTList.push_back(Result); 3556 return Result; 3557} 3558 3559SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2, MVT VT3) { 3560 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 3561 E = VTList.rend(); I != E; ++I) 3562 if (I->NumVTs == 3 && I->VTs[0] == VT1 && I->VTs[1] == VT2 && 3563 I->VTs[2] == VT3) 3564 return *I; 3565 3566 MVT *Array = Allocator.Allocate<MVT>(3); 3567 Array[0] = VT1; 3568 Array[1] = VT2; 3569 Array[2] = VT3; 3570 SDVTList Result = makeVTList(Array, 3); 3571 VTList.push_back(Result); 3572 return Result; 3573} 3574 3575SDVTList SelectionDAG::getVTList(const MVT *VTs, unsigned NumVTs) { 3576 switch (NumVTs) { 3577 case 0: assert(0 && "Cannot have nodes without results!"); 3578 case 1: return getVTList(VTs[0]); 3579 case 2: return getVTList(VTs[0], VTs[1]); 3580 case 3: return getVTList(VTs[0], VTs[1], VTs[2]); 3581 default: break; 3582 } 3583 3584 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 3585 E = VTList.rend(); I != E; ++I) { 3586 if (I->NumVTs != NumVTs || VTs[0] != I->VTs[0] || VTs[1] != I->VTs[1]) 3587 continue; 3588 3589 bool NoMatch = false; 3590 for (unsigned i = 2; i != NumVTs; ++i) 3591 if (VTs[i] != I->VTs[i]) { 3592 NoMatch = true; 3593 break; 3594 } 3595 if (!NoMatch) 3596 return *I; 3597 } 3598 3599 MVT *Array = Allocator.Allocate<MVT>(NumVTs); 3600 std::copy(VTs, VTs+NumVTs, Array); 3601 SDVTList Result = makeVTList(Array, NumVTs); 3602 VTList.push_back(Result); 3603 return Result; 3604} 3605 3606 3607/// UpdateNodeOperands - *Mutate* the specified node in-place to have the 3608/// specified operands. If the resultant node already exists in the DAG, 3609/// this does not modify the specified node, instead it returns the node that 3610/// already exists. If the resultant node does not exist in the DAG, the 3611/// input node is returned. As a degenerate case, if you specify the same 3612/// input operands as the node already has, the input node is returned. 3613SDValue SelectionDAG::UpdateNodeOperands(SDValue InN, SDValue Op) { 3614 SDNode *N = InN.Val; 3615 assert(N->getNumOperands() == 1 && "Update with wrong number of operands"); 3616 3617 // Check to see if there is no change. 3618 if (Op == N->getOperand(0)) return InN; 3619 3620 // See if the modified node already exists. 3621 void *InsertPos = 0; 3622 if (SDNode *Existing = FindModifiedNodeSlot(N, Op, InsertPos)) 3623 return SDValue(Existing, InN.ResNo); 3624 3625 // Nope it doesn't. Remove the node from its current place in the maps. 3626 if (InsertPos) 3627 RemoveNodeFromCSEMaps(N); 3628 3629 // Now we update the operands. 3630 N->OperandList[0].getVal()->removeUser(0, N); 3631 N->OperandList[0] = Op; 3632 N->OperandList[0].setUser(N); 3633 Op.Val->addUser(0, N); 3634 3635 // If this gets put into a CSE map, add it. 3636 if (InsertPos) CSEMap.InsertNode(N, InsertPos); 3637 return InN; 3638} 3639 3640SDValue SelectionDAG:: 3641UpdateNodeOperands(SDValue InN, SDValue Op1, SDValue Op2) { 3642 SDNode *N = InN.Val; 3643 assert(N->getNumOperands() == 2 && "Update with wrong number of operands"); 3644 3645 // Check to see if there is no change. 3646 if (Op1 == N->getOperand(0) && Op2 == N->getOperand(1)) 3647 return InN; // No operands changed, just return the input node. 3648 3649 // See if the modified node already exists. 3650 void *InsertPos = 0; 3651 if (SDNode *Existing = FindModifiedNodeSlot(N, Op1, Op2, InsertPos)) 3652 return SDValue(Existing, InN.ResNo); 3653 3654 // Nope it doesn't. Remove the node from its current place in the maps. 3655 if (InsertPos) 3656 RemoveNodeFromCSEMaps(N); 3657 3658 // Now we update the operands. 3659 if (N->OperandList[0] != Op1) { 3660 N->OperandList[0].getVal()->removeUser(0, N); 3661 N->OperandList[0] = Op1; 3662 N->OperandList[0].setUser(N); 3663 Op1.Val->addUser(0, N); 3664 } 3665 if (N->OperandList[1] != Op2) { 3666 N->OperandList[1].getVal()->removeUser(1, N); 3667 N->OperandList[1] = Op2; 3668 N->OperandList[1].setUser(N); 3669 Op2.Val->addUser(1, N); 3670 } 3671 3672 // If this gets put into a CSE map, add it. 3673 if (InsertPos) CSEMap.InsertNode(N, InsertPos); 3674 return InN; 3675} 3676 3677SDValue SelectionDAG:: 3678UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, SDValue Op3) { 3679 SDValue Ops[] = { Op1, Op2, Op3 }; 3680 return UpdateNodeOperands(N, Ops, 3); 3681} 3682 3683SDValue SelectionDAG:: 3684UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, 3685 SDValue Op3, SDValue Op4) { 3686 SDValue Ops[] = { Op1, Op2, Op3, Op4 }; 3687 return UpdateNodeOperands(N, Ops, 4); 3688} 3689 3690SDValue SelectionDAG:: 3691UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, 3692 SDValue Op3, SDValue Op4, SDValue Op5) { 3693 SDValue Ops[] = { Op1, Op2, Op3, Op4, Op5 }; 3694 return UpdateNodeOperands(N, Ops, 5); 3695} 3696 3697SDValue SelectionDAG:: 3698UpdateNodeOperands(SDValue InN, const SDValue *Ops, unsigned NumOps) { 3699 SDNode *N = InN.Val; 3700 assert(N->getNumOperands() == NumOps && 3701 "Update with wrong number of operands"); 3702 3703 // Check to see if there is no change. 3704 bool AnyChange = false; 3705 for (unsigned i = 0; i != NumOps; ++i) { 3706 if (Ops[i] != N->getOperand(i)) { 3707 AnyChange = true; 3708 break; 3709 } 3710 } 3711 3712 // No operands changed, just return the input node. 3713 if (!AnyChange) return InN; 3714 3715 // See if the modified node already exists. 3716 void *InsertPos = 0; 3717 if (SDNode *Existing = FindModifiedNodeSlot(N, Ops, NumOps, InsertPos)) 3718 return SDValue(Existing, InN.ResNo); 3719 3720 // Nope it doesn't. Remove the node from its current place in the maps. 3721 if (InsertPos) 3722 RemoveNodeFromCSEMaps(N); 3723 3724 // Now we update the operands. 3725 for (unsigned i = 0; i != NumOps; ++i) { 3726 if (N->OperandList[i] != Ops[i]) { 3727 N->OperandList[i].getVal()->removeUser(i, N); 3728 N->OperandList[i] = Ops[i]; 3729 N->OperandList[i].setUser(N); 3730 Ops[i].Val->addUser(i, N); 3731 } 3732 } 3733 3734 // If this gets put into a CSE map, add it. 3735 if (InsertPos) CSEMap.InsertNode(N, InsertPos); 3736 return InN; 3737} 3738 3739/// DropOperands - Release the operands and set this node to have 3740/// zero operands. 3741void SDNode::DropOperands() { 3742 // Unlike the code in MorphNodeTo that does this, we don't need to 3743 // watch for dead nodes here. 3744 for (op_iterator I = op_begin(), E = op_end(); I != E; ++I) 3745 I->getVal()->removeUser(std::distance(op_begin(), I), this); 3746 3747 NumOperands = 0; 3748} 3749 3750/// SelectNodeTo - These are wrappers around MorphNodeTo that accept a 3751/// machine opcode. 3752/// 3753SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 3754 MVT VT) { 3755 SDVTList VTs = getVTList(VT); 3756 return SelectNodeTo(N, MachineOpc, VTs, 0, 0); 3757} 3758 3759SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 3760 MVT VT, SDValue Op1) { 3761 SDVTList VTs = getVTList(VT); 3762 SDValue Ops[] = { Op1 }; 3763 return SelectNodeTo(N, MachineOpc, VTs, Ops, 1); 3764} 3765 3766SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 3767 MVT VT, SDValue Op1, 3768 SDValue Op2) { 3769 SDVTList VTs = getVTList(VT); 3770 SDValue Ops[] = { Op1, Op2 }; 3771 return SelectNodeTo(N, MachineOpc, VTs, Ops, 2); 3772} 3773 3774SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 3775 MVT VT, SDValue Op1, 3776 SDValue Op2, SDValue Op3) { 3777 SDVTList VTs = getVTList(VT); 3778 SDValue Ops[] = { Op1, Op2, Op3 }; 3779 return SelectNodeTo(N, MachineOpc, VTs, Ops, 3); 3780} 3781 3782SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 3783 MVT VT, const SDValue *Ops, 3784 unsigned NumOps) { 3785 SDVTList VTs = getVTList(VT); 3786 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 3787} 3788 3789SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 3790 MVT VT1, MVT VT2, const SDValue *Ops, 3791 unsigned NumOps) { 3792 SDVTList VTs = getVTList(VT1, VT2); 3793 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 3794} 3795 3796SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 3797 MVT VT1, MVT VT2) { 3798 SDVTList VTs = getVTList(VT1, VT2); 3799 return SelectNodeTo(N, MachineOpc, VTs, (SDValue *)0, 0); 3800} 3801 3802SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 3803 MVT VT1, MVT VT2, MVT VT3, 3804 const SDValue *Ops, unsigned NumOps) { 3805 SDVTList VTs = getVTList(VT1, VT2, VT3); 3806 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 3807} 3808 3809SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 3810 MVT VT1, MVT VT2, 3811 SDValue Op1) { 3812 SDVTList VTs = getVTList(VT1, VT2); 3813 SDValue Ops[] = { Op1 }; 3814 return SelectNodeTo(N, MachineOpc, VTs, Ops, 1); 3815} 3816 3817SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 3818 MVT VT1, MVT VT2, 3819 SDValue Op1, SDValue Op2) { 3820 SDVTList VTs = getVTList(VT1, VT2); 3821 SDValue Ops[] = { Op1, Op2 }; 3822 return SelectNodeTo(N, MachineOpc, VTs, Ops, 2); 3823} 3824 3825SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 3826 MVT VT1, MVT VT2, 3827 SDValue Op1, SDValue Op2, 3828 SDValue Op3) { 3829 SDVTList VTs = getVTList(VT1, VT2); 3830 SDValue Ops[] = { Op1, Op2, Op3 }; 3831 return SelectNodeTo(N, MachineOpc, VTs, Ops, 3); 3832} 3833 3834SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 3835 SDVTList VTs, const SDValue *Ops, 3836 unsigned NumOps) { 3837 return MorphNodeTo(N, ~MachineOpc, VTs, Ops, NumOps); 3838} 3839 3840SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 3841 MVT VT) { 3842 SDVTList VTs = getVTList(VT); 3843 return MorphNodeTo(N, Opc, VTs, 0, 0); 3844} 3845 3846SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 3847 MVT VT, SDValue Op1) { 3848 SDVTList VTs = getVTList(VT); 3849 SDValue Ops[] = { Op1 }; 3850 return MorphNodeTo(N, Opc, VTs, Ops, 1); 3851} 3852 3853SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 3854 MVT VT, SDValue Op1, 3855 SDValue Op2) { 3856 SDVTList VTs = getVTList(VT); 3857 SDValue Ops[] = { Op1, Op2 }; 3858 return MorphNodeTo(N, Opc, VTs, Ops, 2); 3859} 3860 3861SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 3862 MVT VT, SDValue Op1, 3863 SDValue Op2, SDValue Op3) { 3864 SDVTList VTs = getVTList(VT); 3865 SDValue Ops[] = { Op1, Op2, Op3 }; 3866 return MorphNodeTo(N, Opc, VTs, Ops, 3); 3867} 3868 3869SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 3870 MVT VT, const SDValue *Ops, 3871 unsigned NumOps) { 3872 SDVTList VTs = getVTList(VT); 3873 return MorphNodeTo(N, Opc, VTs, Ops, NumOps); 3874} 3875 3876SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 3877 MVT VT1, MVT VT2, const SDValue *Ops, 3878 unsigned NumOps) { 3879 SDVTList VTs = getVTList(VT1, VT2); 3880 return MorphNodeTo(N, Opc, VTs, Ops, NumOps); 3881} 3882 3883SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 3884 MVT VT1, MVT VT2) { 3885 SDVTList VTs = getVTList(VT1, VT2); 3886 return MorphNodeTo(N, Opc, VTs, (SDValue *)0, 0); 3887} 3888 3889SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 3890 MVT VT1, MVT VT2, MVT VT3, 3891 const SDValue *Ops, unsigned NumOps) { 3892 SDVTList VTs = getVTList(VT1, VT2, VT3); 3893 return MorphNodeTo(N, Opc, VTs, Ops, NumOps); 3894} 3895 3896SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 3897 MVT VT1, MVT VT2, 3898 SDValue Op1) { 3899 SDVTList VTs = getVTList(VT1, VT2); 3900 SDValue Ops[] = { Op1 }; 3901 return MorphNodeTo(N, Opc, VTs, Ops, 1); 3902} 3903 3904SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 3905 MVT VT1, MVT VT2, 3906 SDValue Op1, SDValue Op2) { 3907 SDVTList VTs = getVTList(VT1, VT2); 3908 SDValue Ops[] = { Op1, Op2 }; 3909 return MorphNodeTo(N, Opc, VTs, Ops, 2); 3910} 3911 3912SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 3913 MVT VT1, MVT VT2, 3914 SDValue Op1, SDValue Op2, 3915 SDValue Op3) { 3916 SDVTList VTs = getVTList(VT1, VT2); 3917 SDValue Ops[] = { Op1, Op2, Op3 }; 3918 return MorphNodeTo(N, Opc, VTs, Ops, 3); 3919} 3920 3921/// MorphNodeTo - These *mutate* the specified node to have the specified 3922/// return type, opcode, and operands. 3923/// 3924/// Note that MorphNodeTo returns the resultant node. If there is already a 3925/// node of the specified opcode and operands, it returns that node instead of 3926/// the current one. 3927/// 3928/// Using MorphNodeTo is faster than creating a new node and swapping it in 3929/// with ReplaceAllUsesWith both because it often avoids allocating a new 3930/// node, and because it doesn't require CSE recalulation for any of 3931/// the node's users. 3932/// 3933SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 3934 SDVTList VTs, const SDValue *Ops, 3935 unsigned NumOps) { 3936 // If an identical node already exists, use it. 3937 void *IP = 0; 3938 if (VTs.VTs[VTs.NumVTs-1] != MVT::Flag) { 3939 FoldingSetNodeID ID; 3940 AddNodeIDNode(ID, Opc, VTs, Ops, NumOps); 3941 if (SDNode *ON = CSEMap.FindNodeOrInsertPos(ID, IP)) 3942 return ON; 3943 } 3944 3945 RemoveNodeFromCSEMaps(N); 3946 3947 // Start the morphing. 3948 N->NodeType = Opc; 3949 N->ValueList = VTs.VTs; 3950 N->NumValues = VTs.NumVTs; 3951 3952 // Clear the operands list, updating used nodes to remove this from their 3953 // use list. Keep track of any operands that become dead as a result. 3954 SmallPtrSet<SDNode*, 16> DeadNodeSet; 3955 for (SDNode::op_iterator B = N->op_begin(), I = B, E = N->op_end(); 3956 I != E; ++I) { 3957 SDNode *Used = I->getVal(); 3958 Used->removeUser(std::distance(B, I), N); 3959 if (Used->use_empty()) 3960 DeadNodeSet.insert(Used); 3961 } 3962 3963 // If NumOps is larger than the # of operands we currently have, reallocate 3964 // the operand list. 3965 if (NumOps > N->NumOperands) { 3966 if (N->OperandsNeedDelete) 3967 delete[] N->OperandList; 3968 if (N->isMachineOpcode()) { 3969 // We're creating a final node that will live unmorphed for the 3970 // remainder of this SelectionDAG's duration, so we can allocate the 3971 // operands directly out of the pool with no recycling metadata. 3972 N->OperandList = Allocator.Allocate<SDUse>(NumOps); 3973 N->OperandsNeedDelete = false; 3974 } else { 3975 N->OperandList = new SDUse[NumOps]; 3976 N->OperandsNeedDelete = true; 3977 } 3978 } 3979 3980 // Assign the new operands. 3981 N->NumOperands = NumOps; 3982 for (unsigned i = 0, e = NumOps; i != e; ++i) { 3983 N->OperandList[i] = Ops[i]; 3984 N->OperandList[i].setUser(N); 3985 SDNode *ToUse = N->OperandList[i].getVal(); 3986 ToUse->addUser(i, N); 3987 DeadNodeSet.erase(ToUse); 3988 } 3989 3990 // Delete any nodes that are still dead after adding the uses for the 3991 // new operands. 3992 SmallVector<SDNode *, 16> DeadNodes; 3993 for (SmallPtrSet<SDNode *, 16>::iterator I = DeadNodeSet.begin(), 3994 E = DeadNodeSet.end(); I != E; ++I) 3995 if ((*I)->use_empty()) 3996 DeadNodes.push_back(*I); 3997 RemoveDeadNodes(DeadNodes); 3998 3999 if (IP) 4000 CSEMap.InsertNode(N, IP); // Memoize the new node. 4001 return N; 4002} 4003 4004 4005/// getTargetNode - These are used for target selectors to create a new node 4006/// with specified return type(s), target opcode, and operands. 4007/// 4008/// Note that getTargetNode returns the resultant node. If there is already a 4009/// node of the specified opcode and operands, it returns that node instead of 4010/// the current one. 4011SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT) { 4012 return getNode(~Opcode, VT).Val; 4013} 4014SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT, SDValue Op1) { 4015 return getNode(~Opcode, VT, Op1).Val; 4016} 4017SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT, 4018 SDValue Op1, SDValue Op2) { 4019 return getNode(~Opcode, VT, Op1, Op2).Val; 4020} 4021SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT, 4022 SDValue Op1, SDValue Op2, 4023 SDValue Op3) { 4024 return getNode(~Opcode, VT, Op1, Op2, Op3).Val; 4025} 4026SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT, 4027 const SDValue *Ops, unsigned NumOps) { 4028 return getNode(~Opcode, VT, Ops, NumOps).Val; 4029} 4030SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2) { 4031 const MVT *VTs = getNodeValueTypes(VT1, VT2); 4032 SDValue Op; 4033 return getNode(~Opcode, VTs, 2, &Op, 0).Val; 4034} 4035SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, 4036 MVT VT2, SDValue Op1) { 4037 const MVT *VTs = getNodeValueTypes(VT1, VT2); 4038 return getNode(~Opcode, VTs, 2, &Op1, 1).Val; 4039} 4040SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, 4041 MVT VT2, SDValue Op1, 4042 SDValue Op2) { 4043 const MVT *VTs = getNodeValueTypes(VT1, VT2); 4044 SDValue Ops[] = { Op1, Op2 }; 4045 return getNode(~Opcode, VTs, 2, Ops, 2).Val; 4046} 4047SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, 4048 MVT VT2, SDValue Op1, 4049 SDValue Op2, SDValue Op3) { 4050 const MVT *VTs = getNodeValueTypes(VT1, VT2); 4051 SDValue Ops[] = { Op1, Op2, Op3 }; 4052 return getNode(~Opcode, VTs, 2, Ops, 3).Val; 4053} 4054SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, 4055 const SDValue *Ops, unsigned NumOps) { 4056 const MVT *VTs = getNodeValueTypes(VT1, VT2); 4057 return getNode(~Opcode, VTs, 2, Ops, NumOps).Val; 4058} 4059SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3, 4060 SDValue Op1, SDValue Op2) { 4061 const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3); 4062 SDValue Ops[] = { Op1, Op2 }; 4063 return getNode(~Opcode, VTs, 3, Ops, 2).Val; 4064} 4065SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3, 4066 SDValue Op1, SDValue Op2, 4067 SDValue Op3) { 4068 const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3); 4069 SDValue Ops[] = { Op1, Op2, Op3 }; 4070 return getNode(~Opcode, VTs, 3, Ops, 3).Val; 4071} 4072SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3, 4073 const SDValue *Ops, unsigned NumOps) { 4074 const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3); 4075 return getNode(~Opcode, VTs, 3, Ops, NumOps).Val; 4076} 4077SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, 4078 MVT VT2, MVT VT3, MVT VT4, 4079 const SDValue *Ops, unsigned NumOps) { 4080 std::vector<MVT> VTList; 4081 VTList.push_back(VT1); 4082 VTList.push_back(VT2); 4083 VTList.push_back(VT3); 4084 VTList.push_back(VT4); 4085 const MVT *VTs = getNodeValueTypes(VTList); 4086 return getNode(~Opcode, VTs, 4, Ops, NumOps).Val; 4087} 4088SDNode *SelectionDAG::getTargetNode(unsigned Opcode, 4089 const std::vector<MVT> &ResultTys, 4090 const SDValue *Ops, unsigned NumOps) { 4091 const MVT *VTs = getNodeValueTypes(ResultTys); 4092 return getNode(~Opcode, VTs, ResultTys.size(), 4093 Ops, NumOps).Val; 4094} 4095 4096/// getNodeIfExists - Get the specified node if it's already available, or 4097/// else return NULL. 4098SDNode *SelectionDAG::getNodeIfExists(unsigned Opcode, SDVTList VTList, 4099 const SDValue *Ops, unsigned NumOps) { 4100 if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) { 4101 FoldingSetNodeID ID; 4102 AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps); 4103 void *IP = 0; 4104 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 4105 return E; 4106 } 4107 return NULL; 4108} 4109 4110 4111/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. 4112/// This can cause recursive merging of nodes in the DAG. 4113/// 4114/// This version assumes From has a single result value. 4115/// 4116void SelectionDAG::ReplaceAllUsesWith(SDValue FromN, SDValue To, 4117 DAGUpdateListener *UpdateListener) { 4118 SDNode *From = FromN.Val; 4119 assert(From->getNumValues() == 1 && FromN.ResNo == 0 && 4120 "Cannot replace with this method!"); 4121 assert(From != To.Val && "Cannot replace uses of with self"); 4122 4123 while (!From->use_empty()) { 4124 SDNode::use_iterator UI = From->use_begin(); 4125 SDNode *U = *UI; 4126 4127 // This node is about to morph, remove its old self from the CSE maps. 4128 RemoveNodeFromCSEMaps(U); 4129 int operandNum = 0; 4130 for (SDNode::op_iterator I = U->op_begin(), E = U->op_end(); 4131 I != E; ++I, ++operandNum) 4132 if (I->getVal() == From) { 4133 From->removeUser(operandNum, U); 4134 *I = To; 4135 I->setUser(U); 4136 To.Val->addUser(operandNum, U); 4137 } 4138 4139 // Now that we have modified U, add it back to the CSE maps. If it already 4140 // exists there, recursively merge the results together. 4141 if (SDNode *Existing = AddNonLeafNodeToCSEMaps(U)) { 4142 ReplaceAllUsesWith(U, Existing, UpdateListener); 4143 // U is now dead. Inform the listener if it exists and delete it. 4144 if (UpdateListener) 4145 UpdateListener->NodeDeleted(U, Existing); 4146 DeleteNodeNotInCSEMaps(U); 4147 } else { 4148 // If the node doesn't already exist, we updated it. Inform a listener if 4149 // it exists. 4150 if (UpdateListener) 4151 UpdateListener->NodeUpdated(U); 4152 } 4153 } 4154} 4155 4156/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. 4157/// This can cause recursive merging of nodes in the DAG. 4158/// 4159/// This version assumes From/To have matching types and numbers of result 4160/// values. 4161/// 4162void SelectionDAG::ReplaceAllUsesWith(SDNode *From, SDNode *To, 4163 DAGUpdateListener *UpdateListener) { 4164 assert(From->getVTList().VTs == To->getVTList().VTs && 4165 From->getNumValues() == To->getNumValues() && 4166 "Cannot use this version of ReplaceAllUsesWith!"); 4167 4168 // Handle the trivial case. 4169 if (From == To) 4170 return; 4171 4172 while (!From->use_empty()) { 4173 SDNode::use_iterator UI = From->use_begin(); 4174 SDNode *U = *UI; 4175 4176 // This node is about to morph, remove its old self from the CSE maps. 4177 RemoveNodeFromCSEMaps(U); 4178 int operandNum = 0; 4179 for (SDNode::op_iterator I = U->op_begin(), E = U->op_end(); 4180 I != E; ++I, ++operandNum) 4181 if (I->getVal() == From) { 4182 From->removeUser(operandNum, U); 4183 I->getVal() = To; 4184 To->addUser(operandNum, U); 4185 } 4186 4187 // Now that we have modified U, add it back to the CSE maps. If it already 4188 // exists there, recursively merge the results together. 4189 if (SDNode *Existing = AddNonLeafNodeToCSEMaps(U)) { 4190 ReplaceAllUsesWith(U, Existing, UpdateListener); 4191 // U is now dead. Inform the listener if it exists and delete it. 4192 if (UpdateListener) 4193 UpdateListener->NodeDeleted(U, Existing); 4194 DeleteNodeNotInCSEMaps(U); 4195 } else { 4196 // If the node doesn't already exist, we updated it. Inform a listener if 4197 // it exists. 4198 if (UpdateListener) 4199 UpdateListener->NodeUpdated(U); 4200 } 4201 } 4202} 4203 4204/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. 4205/// This can cause recursive merging of nodes in the DAG. 4206/// 4207/// This version can replace From with any result values. To must match the 4208/// number and types of values returned by From. 4209void SelectionDAG::ReplaceAllUsesWith(SDNode *From, 4210 const SDValue *To, 4211 DAGUpdateListener *UpdateListener) { 4212 if (From->getNumValues() == 1) // Handle the simple case efficiently. 4213 return ReplaceAllUsesWith(SDValue(From, 0), To[0], UpdateListener); 4214 4215 while (!From->use_empty()) { 4216 SDNode::use_iterator UI = From->use_begin(); 4217 SDNode *U = *UI; 4218 4219 // This node is about to morph, remove its old self from the CSE maps. 4220 RemoveNodeFromCSEMaps(U); 4221 int operandNum = 0; 4222 for (SDNode::op_iterator I = U->op_begin(), E = U->op_end(); 4223 I != E; ++I, ++operandNum) 4224 if (I->getVal() == From) { 4225 const SDValue &ToOp = To[I->getSDValue().ResNo]; 4226 From->removeUser(operandNum, U); 4227 *I = ToOp; 4228 I->setUser(U); 4229 ToOp.Val->addUser(operandNum, U); 4230 } 4231 4232 // Now that we have modified U, add it back to the CSE maps. If it already 4233 // exists there, recursively merge the results together. 4234 if (SDNode *Existing = AddNonLeafNodeToCSEMaps(U)) { 4235 ReplaceAllUsesWith(U, Existing, UpdateListener); 4236 // U is now dead. Inform the listener if it exists and delete it. 4237 if (UpdateListener) 4238 UpdateListener->NodeDeleted(U, Existing); 4239 DeleteNodeNotInCSEMaps(U); 4240 } else { 4241 // If the node doesn't already exist, we updated it. Inform a listener if 4242 // it exists. 4243 if (UpdateListener) 4244 UpdateListener->NodeUpdated(U); 4245 } 4246 } 4247} 4248 4249/// ReplaceAllUsesOfValueWith - Replace any uses of From with To, leaving 4250/// uses of other values produced by From.Val alone. The Deleted vector is 4251/// handled the same way as for ReplaceAllUsesWith. 4252void SelectionDAG::ReplaceAllUsesOfValueWith(SDValue From, SDValue To, 4253 DAGUpdateListener *UpdateListener){ 4254 // Handle the really simple, really trivial case efficiently. 4255 if (From == To) return; 4256 4257 // Handle the simple, trivial, case efficiently. 4258 if (From.Val->getNumValues() == 1) { 4259 ReplaceAllUsesWith(From, To, UpdateListener); 4260 return; 4261 } 4262 4263 // Get all of the users of From.Val. We want these in a nice, 4264 // deterministically ordered and uniqued set, so we use a SmallSetVector. 4265 SmallSetVector<SDNode*, 16> Users(From.Val->use_begin(), From.Val->use_end()); 4266 4267 while (!Users.empty()) { 4268 // We know that this user uses some value of From. If it is the right 4269 // value, update it. 4270 SDNode *User = Users.back(); 4271 Users.pop_back(); 4272 4273 // Scan for an operand that matches From. 4274 SDNode::op_iterator Op = User->op_begin(), E = User->op_end(); 4275 for (; Op != E; ++Op) 4276 if (*Op == From) break; 4277 4278 // If there are no matches, the user must use some other result of From. 4279 if (Op == E) continue; 4280 4281 // Okay, we know this user needs to be updated. Remove its old self 4282 // from the CSE maps. 4283 RemoveNodeFromCSEMaps(User); 4284 4285 // Update all operands that match "From" in case there are multiple uses. 4286 for (; Op != E; ++Op) { 4287 if (*Op == From) { 4288 From.Val->removeUser(Op-User->op_begin(), User); 4289 *Op = To; 4290 Op->setUser(User); 4291 To.Val->addUser(Op-User->op_begin(), User); 4292 } 4293 } 4294 4295 // Now that we have modified User, add it back to the CSE maps. If it 4296 // already exists there, recursively merge the results together. 4297 SDNode *Existing = AddNonLeafNodeToCSEMaps(User); 4298 if (!Existing) { 4299 if (UpdateListener) UpdateListener->NodeUpdated(User); 4300 continue; // Continue on to next user. 4301 } 4302 4303 // If there was already an existing matching node, use ReplaceAllUsesWith 4304 // to replace the dead one with the existing one. This can cause 4305 // recursive merging of other unrelated nodes down the line. 4306 ReplaceAllUsesWith(User, Existing, UpdateListener); 4307 4308 // User is now dead. Notify a listener if present. 4309 if (UpdateListener) UpdateListener->NodeDeleted(User, Existing); 4310 DeleteNodeNotInCSEMaps(User); 4311 } 4312} 4313 4314/// ReplaceAllUsesOfValuesWith - Replace any uses of From with To, leaving 4315/// uses of other values produced by From.Val alone. The same value may 4316/// appear in both the From and To list. The Deleted vector is 4317/// handled the same way as for ReplaceAllUsesWith. 4318void SelectionDAG::ReplaceAllUsesOfValuesWith(const SDValue *From, 4319 const SDValue *To, 4320 unsigned Num, 4321 DAGUpdateListener *UpdateListener){ 4322 // Handle the simple, trivial case efficiently. 4323 if (Num == 1) 4324 return ReplaceAllUsesOfValueWith(*From, *To, UpdateListener); 4325 4326 SmallVector<std::pair<SDNode *, unsigned>, 16> Users; 4327 for (unsigned i = 0; i != Num; ++i) 4328 for (SDNode::use_iterator UI = From[i].Val->use_begin(), 4329 E = From[i].Val->use_end(); UI != E; ++UI) 4330 Users.push_back(std::make_pair(*UI, i)); 4331 4332 while (!Users.empty()) { 4333 // We know that this user uses some value of From. If it is the right 4334 // value, update it. 4335 SDNode *User = Users.back().first; 4336 unsigned i = Users.back().second; 4337 Users.pop_back(); 4338 4339 // Scan for an operand that matches From. 4340 SDNode::op_iterator Op = User->op_begin(), E = User->op_end(); 4341 for (; Op != E; ++Op) 4342 if (*Op == From[i]) break; 4343 4344 // If there are no matches, the user must use some other result of From. 4345 if (Op == E) continue; 4346 4347 // Okay, we know this user needs to be updated. Remove its old self 4348 // from the CSE maps. 4349 RemoveNodeFromCSEMaps(User); 4350 4351 // Update all operands that match "From" in case there are multiple uses. 4352 for (; Op != E; ++Op) { 4353 if (*Op == From[i]) { 4354 From[i].Val->removeUser(Op-User->op_begin(), User); 4355 *Op = To[i]; 4356 Op->setUser(User); 4357 To[i].Val->addUser(Op-User->op_begin(), User); 4358 } 4359 } 4360 4361 // Now that we have modified User, add it back to the CSE maps. If it 4362 // already exists there, recursively merge the results together. 4363 SDNode *Existing = AddNonLeafNodeToCSEMaps(User); 4364 if (!Existing) { 4365 if (UpdateListener) UpdateListener->NodeUpdated(User); 4366 continue; // Continue on to next user. 4367 } 4368 4369 // If there was already an existing matching node, use ReplaceAllUsesWith 4370 // to replace the dead one with the existing one. This can cause 4371 // recursive merging of other unrelated nodes down the line. 4372 ReplaceAllUsesWith(User, Existing, UpdateListener); 4373 4374 // User is now dead. Notify a listener if present. 4375 if (UpdateListener) UpdateListener->NodeDeleted(User, Existing); 4376 DeleteNodeNotInCSEMaps(User); 4377 } 4378} 4379 4380/// AssignTopologicalOrder - Assign a unique node id for each node in the DAG 4381/// based on their topological order. It returns the maximum id and a vector 4382/// of the SDNodes* in assigned order by reference. 4383unsigned SelectionDAG::AssignTopologicalOrder(std::vector<SDNode*> &TopOrder) { 4384 unsigned DAGSize = AllNodes.size(); 4385 std::vector<unsigned> InDegree(DAGSize); 4386 std::vector<SDNode*> Sources; 4387 4388 // Use a two pass approach to avoid using a std::map which is slow. 4389 unsigned Id = 0; 4390 for (allnodes_iterator I = allnodes_begin(),E = allnodes_end(); I != E; ++I){ 4391 SDNode *N = I; 4392 N->setNodeId(Id++); 4393 unsigned Degree = N->use_size(); 4394 InDegree[N->getNodeId()] = Degree; 4395 if (Degree == 0) 4396 Sources.push_back(N); 4397 } 4398 4399 TopOrder.clear(); 4400 TopOrder.reserve(DAGSize); 4401 while (!Sources.empty()) { 4402 SDNode *N = Sources.back(); 4403 Sources.pop_back(); 4404 TopOrder.push_back(N); 4405 for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ++I) { 4406 SDNode *P = I->getVal(); 4407 unsigned Degree = --InDegree[P->getNodeId()]; 4408 if (Degree == 0) 4409 Sources.push_back(P); 4410 } 4411 } 4412 4413 // Second pass, assign the actual topological order as node ids. 4414 Id = 0; 4415 for (std::vector<SDNode*>::iterator TI = TopOrder.begin(),TE = TopOrder.end(); 4416 TI != TE; ++TI) 4417 (*TI)->setNodeId(Id++); 4418 4419 return Id; 4420} 4421 4422 4423 4424//===----------------------------------------------------------------------===// 4425// SDNode Class 4426//===----------------------------------------------------------------------===// 4427 4428// Out-of-line virtual method to give class a home. 4429void SDNode::ANCHOR() {} 4430void UnarySDNode::ANCHOR() {} 4431void BinarySDNode::ANCHOR() {} 4432void TernarySDNode::ANCHOR() {} 4433void HandleSDNode::ANCHOR() {} 4434void ConstantSDNode::ANCHOR() {} 4435void ConstantFPSDNode::ANCHOR() {} 4436void GlobalAddressSDNode::ANCHOR() {} 4437void FrameIndexSDNode::ANCHOR() {} 4438void JumpTableSDNode::ANCHOR() {} 4439void ConstantPoolSDNode::ANCHOR() {} 4440void BasicBlockSDNode::ANCHOR() {} 4441void SrcValueSDNode::ANCHOR() {} 4442void MemOperandSDNode::ANCHOR() {} 4443void RegisterSDNode::ANCHOR() {} 4444void DbgStopPointSDNode::ANCHOR() {} 4445void LabelSDNode::ANCHOR() {} 4446void ExternalSymbolSDNode::ANCHOR() {} 4447void CondCodeSDNode::ANCHOR() {} 4448void ARG_FLAGSSDNode::ANCHOR() {} 4449void VTSDNode::ANCHOR() {} 4450void MemSDNode::ANCHOR() {} 4451void LoadSDNode::ANCHOR() {} 4452void StoreSDNode::ANCHOR() {} 4453void AtomicSDNode::ANCHOR() {} 4454 4455HandleSDNode::~HandleSDNode() { 4456 DropOperands(); 4457} 4458 4459GlobalAddressSDNode::GlobalAddressSDNode(bool isTarget, const GlobalValue *GA, 4460 MVT VT, int o) 4461 : SDNode(isa<GlobalVariable>(GA) && 4462 cast<GlobalVariable>(GA)->isThreadLocal() ? 4463 // Thread Local 4464 (isTarget ? ISD::TargetGlobalTLSAddress : ISD::GlobalTLSAddress) : 4465 // Non Thread Local 4466 (isTarget ? ISD::TargetGlobalAddress : ISD::GlobalAddress), 4467 getSDVTList(VT)), Offset(o) { 4468 TheGlobal = const_cast<GlobalValue*>(GA); 4469} 4470 4471MemSDNode::MemSDNode(unsigned Opc, SDVTList VTs, MVT memvt, 4472 const Value *srcValue, int SVO, 4473 unsigned alignment, bool vol) 4474 : SDNode(Opc, VTs), MemoryVT(memvt), SrcValue(srcValue), SVOffset(SVO), 4475 Flags(vol | ((Log2_32(alignment) + 1) << 1)) { 4476 4477 assert(isPowerOf2_32(alignment) && "Alignment is not a power of 2!"); 4478 assert(getAlignment() == alignment && "Alignment representation error!"); 4479 assert(isVolatile() == vol && "Volatile representation error!"); 4480} 4481 4482/// getMemOperand - Return a MachineMemOperand object describing the memory 4483/// reference performed by this memory reference. 4484MachineMemOperand MemSDNode::getMemOperand() const { 4485 int Flags; 4486 if (isa<LoadSDNode>(this)) 4487 Flags = MachineMemOperand::MOLoad; 4488 else if (isa<StoreSDNode>(this)) 4489 Flags = MachineMemOperand::MOStore; 4490 else { 4491 assert(isa<AtomicSDNode>(this) && "Unknown MemSDNode opcode!"); 4492 Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore; 4493 } 4494 4495 int Size = (getMemoryVT().getSizeInBits() + 7) >> 3; 4496 if (isVolatile()) Flags |= MachineMemOperand::MOVolatile; 4497 4498 // Check if the memory reference references a frame index 4499 const FrameIndexSDNode *FI = 4500 dyn_cast<const FrameIndexSDNode>(getBasePtr().Val); 4501 if (!getSrcValue() && FI) 4502 return MachineMemOperand(PseudoSourceValue::getFixedStack(FI->getIndex()), 4503 Flags, 0, Size, getAlignment()); 4504 else 4505 return MachineMemOperand(getSrcValue(), Flags, getSrcValueOffset(), 4506 Size, getAlignment()); 4507} 4508 4509/// Profile - Gather unique data for the node. 4510/// 4511void SDNode::Profile(FoldingSetNodeID &ID) { 4512 AddNodeIDNode(ID, this); 4513} 4514 4515/// getValueTypeList - Return a pointer to the specified value type. 4516/// 4517const MVT *SDNode::getValueTypeList(MVT VT) { 4518 if (VT.isExtended()) { 4519 static std::set<MVT, MVT::compareRawBits> EVTs; 4520 return &(*EVTs.insert(VT).first); 4521 } else { 4522 static MVT VTs[MVT::LAST_VALUETYPE]; 4523 VTs[VT.getSimpleVT()] = VT; 4524 return &VTs[VT.getSimpleVT()]; 4525 } 4526} 4527 4528/// hasNUsesOfValue - Return true if there are exactly NUSES uses of the 4529/// indicated value. This method ignores uses of other values defined by this 4530/// operation. 4531bool SDNode::hasNUsesOfValue(unsigned NUses, unsigned Value) const { 4532 assert(Value < getNumValues() && "Bad value!"); 4533 4534 // TODO: Only iterate over uses of a given value of the node 4535 for (SDNode::use_iterator UI = use_begin(), E = use_end(); UI != E; ++UI) { 4536 if (UI.getUse().getSDValue().ResNo == Value) { 4537 if (NUses == 0) 4538 return false; 4539 --NUses; 4540 } 4541 } 4542 4543 // Found exactly the right number of uses? 4544 return NUses == 0; 4545} 4546 4547 4548/// hasAnyUseOfValue - Return true if there are any use of the indicated 4549/// value. This method ignores uses of other values defined by this operation. 4550bool SDNode::hasAnyUseOfValue(unsigned Value) const { 4551 assert(Value < getNumValues() && "Bad value!"); 4552 4553 for (SDNode::use_iterator UI = use_begin(), E = use_end(); UI != E; ++UI) 4554 if (UI.getUse().getSDValue().ResNo == Value) 4555 return true; 4556 4557 return false; 4558} 4559 4560 4561/// isOnlyUserOf - Return true if this node is the only use of N. 4562/// 4563bool SDNode::isOnlyUserOf(SDNode *N) const { 4564 bool Seen = false; 4565 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 4566 SDNode *User = *I; 4567 if (User == this) 4568 Seen = true; 4569 else 4570 return false; 4571 } 4572 4573 return Seen; 4574} 4575 4576/// isOperand - Return true if this node is an operand of N. 4577/// 4578bool SDValue::isOperandOf(SDNode *N) const { 4579 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 4580 if (*this == N->getOperand(i)) 4581 return true; 4582 return false; 4583} 4584 4585bool SDNode::isOperandOf(SDNode *N) const { 4586 for (unsigned i = 0, e = N->NumOperands; i != e; ++i) 4587 if (this == N->OperandList[i].getVal()) 4588 return true; 4589 return false; 4590} 4591 4592/// reachesChainWithoutSideEffects - Return true if this operand (which must 4593/// be a chain) reaches the specified operand without crossing any 4594/// side-effecting instructions. In practice, this looks through token 4595/// factors and non-volatile loads. In order to remain efficient, this only 4596/// looks a couple of nodes in, it does not do an exhaustive search. 4597bool SDValue::reachesChainWithoutSideEffects(SDValue Dest, 4598 unsigned Depth) const { 4599 if (*this == Dest) return true; 4600 4601 // Don't search too deeply, we just want to be able to see through 4602 // TokenFactor's etc. 4603 if (Depth == 0) return false; 4604 4605 // If this is a token factor, all inputs to the TF happen in parallel. If any 4606 // of the operands of the TF reach dest, then we can do the xform. 4607 if (getOpcode() == ISD::TokenFactor) { 4608 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) 4609 if (getOperand(i).reachesChainWithoutSideEffects(Dest, Depth-1)) 4610 return true; 4611 return false; 4612 } 4613 4614 // Loads don't have side effects, look through them. 4615 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(*this)) { 4616 if (!Ld->isVolatile()) 4617 return Ld->getChain().reachesChainWithoutSideEffects(Dest, Depth-1); 4618 } 4619 return false; 4620} 4621 4622 4623static void findPredecessor(SDNode *N, const SDNode *P, bool &found, 4624 SmallPtrSet<SDNode *, 32> &Visited) { 4625 if (found || !Visited.insert(N)) 4626 return; 4627 4628 for (unsigned i = 0, e = N->getNumOperands(); !found && i != e; ++i) { 4629 SDNode *Op = N->getOperand(i).Val; 4630 if (Op == P) { 4631 found = true; 4632 return; 4633 } 4634 findPredecessor(Op, P, found, Visited); 4635 } 4636} 4637 4638/// isPredecessorOf - Return true if this node is a predecessor of N. This node 4639/// is either an operand of N or it can be reached by recursively traversing 4640/// up the operands. 4641/// NOTE: this is an expensive method. Use it carefully. 4642bool SDNode::isPredecessorOf(SDNode *N) const { 4643 SmallPtrSet<SDNode *, 32> Visited; 4644 bool found = false; 4645 findPredecessor(N, this, found, Visited); 4646 return found; 4647} 4648 4649uint64_t SDNode::getConstantOperandVal(unsigned Num) const { 4650 assert(Num < NumOperands && "Invalid child # of SDNode!"); 4651 return cast<ConstantSDNode>(OperandList[Num])->getValue(); 4652} 4653 4654std::string SDNode::getOperationName(const SelectionDAG *G) const { 4655 switch (getOpcode()) { 4656 default: 4657 if (getOpcode() < ISD::BUILTIN_OP_END) 4658 return "<<Unknown DAG Node>>"; 4659 if (isMachineOpcode()) { 4660 if (G) 4661 if (const TargetInstrInfo *TII = G->getTarget().getInstrInfo()) 4662 if (getMachineOpcode() < TII->getNumOpcodes()) 4663 return TII->get(getMachineOpcode()).getName(); 4664 return "<<Unknown Machine Node>>"; 4665 } 4666 if (G) { 4667 TargetLowering &TLI = G->getTargetLoweringInfo(); 4668 const char *Name = TLI.getTargetNodeName(getOpcode()); 4669 if (Name) return Name; 4670 return "<<Unknown Target Node>>"; 4671 } 4672 return "<<Unknown Node>>"; 4673 4674#ifndef NDEBUG 4675 case ISD::DELETED_NODE: 4676 return "<<Deleted Node!>>"; 4677#endif 4678 case ISD::PREFETCH: return "Prefetch"; 4679 case ISD::MEMBARRIER: return "MemBarrier"; 4680 case ISD::ATOMIC_CMP_SWAP: return "AtomicCmpSwap"; 4681 case ISD::ATOMIC_LOAD_ADD: return "AtomicLoadAdd"; 4682 case ISD::ATOMIC_LOAD_SUB: return "AtomicLoadSub"; 4683 case ISD::ATOMIC_LOAD_AND: return "AtomicLoadAnd"; 4684 case ISD::ATOMIC_LOAD_OR: return "AtomicLoadOr"; 4685 case ISD::ATOMIC_LOAD_XOR: return "AtomicLoadXor"; 4686 case ISD::ATOMIC_LOAD_NAND: return "AtomicLoadNand"; 4687 case ISD::ATOMIC_LOAD_MIN: return "AtomicLoadMin"; 4688 case ISD::ATOMIC_LOAD_MAX: return "AtomicLoadMax"; 4689 case ISD::ATOMIC_LOAD_UMIN: return "AtomicLoadUMin"; 4690 case ISD::ATOMIC_LOAD_UMAX: return "AtomicLoadUMax"; 4691 case ISD::ATOMIC_SWAP: return "AtomicSWAP"; 4692 case ISD::PCMARKER: return "PCMarker"; 4693 case ISD::READCYCLECOUNTER: return "ReadCycleCounter"; 4694 case ISD::SRCVALUE: return "SrcValue"; 4695 case ISD::MEMOPERAND: return "MemOperand"; 4696 case ISD::EntryToken: return "EntryToken"; 4697 case ISD::TokenFactor: return "TokenFactor"; 4698 case ISD::AssertSext: return "AssertSext"; 4699 case ISD::AssertZext: return "AssertZext"; 4700 4701 case ISD::BasicBlock: return "BasicBlock"; 4702 case ISD::ARG_FLAGS: return "ArgFlags"; 4703 case ISD::VALUETYPE: return "ValueType"; 4704 case ISD::Register: return "Register"; 4705 4706 case ISD::Constant: return "Constant"; 4707 case ISD::ConstantFP: return "ConstantFP"; 4708 case ISD::GlobalAddress: return "GlobalAddress"; 4709 case ISD::GlobalTLSAddress: return "GlobalTLSAddress"; 4710 case ISD::FrameIndex: return "FrameIndex"; 4711 case ISD::JumpTable: return "JumpTable"; 4712 case ISD::GLOBAL_OFFSET_TABLE: return "GLOBAL_OFFSET_TABLE"; 4713 case ISD::RETURNADDR: return "RETURNADDR"; 4714 case ISD::FRAMEADDR: return "FRAMEADDR"; 4715 case ISD::FRAME_TO_ARGS_OFFSET: return "FRAME_TO_ARGS_OFFSET"; 4716 case ISD::EXCEPTIONADDR: return "EXCEPTIONADDR"; 4717 case ISD::EHSELECTION: return "EHSELECTION"; 4718 case ISD::EH_RETURN: return "EH_RETURN"; 4719 case ISD::ConstantPool: return "ConstantPool"; 4720 case ISD::ExternalSymbol: return "ExternalSymbol"; 4721 case ISD::INTRINSIC_WO_CHAIN: { 4722 unsigned IID = cast<ConstantSDNode>(getOperand(0))->getValue(); 4723 return Intrinsic::getName((Intrinsic::ID)IID); 4724 } 4725 case ISD::INTRINSIC_VOID: 4726 case ISD::INTRINSIC_W_CHAIN: { 4727 unsigned IID = cast<ConstantSDNode>(getOperand(1))->getValue(); 4728 return Intrinsic::getName((Intrinsic::ID)IID); 4729 } 4730 4731 case ISD::BUILD_VECTOR: return "BUILD_VECTOR"; 4732 case ISD::TargetConstant: return "TargetConstant"; 4733 case ISD::TargetConstantFP:return "TargetConstantFP"; 4734 case ISD::TargetGlobalAddress: return "TargetGlobalAddress"; 4735 case ISD::TargetGlobalTLSAddress: return "TargetGlobalTLSAddress"; 4736 case ISD::TargetFrameIndex: return "TargetFrameIndex"; 4737 case ISD::TargetJumpTable: return "TargetJumpTable"; 4738 case ISD::TargetConstantPool: return "TargetConstantPool"; 4739 case ISD::TargetExternalSymbol: return "TargetExternalSymbol"; 4740 4741 case ISD::CopyToReg: return "CopyToReg"; 4742 case ISD::CopyFromReg: return "CopyFromReg"; 4743 case ISD::UNDEF: return "undef"; 4744 case ISD::MERGE_VALUES: return "merge_values"; 4745 case ISD::INLINEASM: return "inlineasm"; 4746 case ISD::DBG_LABEL: return "dbg_label"; 4747 case ISD::EH_LABEL: return "eh_label"; 4748 case ISD::DECLARE: return "declare"; 4749 case ISD::HANDLENODE: return "handlenode"; 4750 case ISD::FORMAL_ARGUMENTS: return "formal_arguments"; 4751 case ISD::CALL: return "call"; 4752 4753 // Unary operators 4754 case ISD::FABS: return "fabs"; 4755 case ISD::FNEG: return "fneg"; 4756 case ISD::FSQRT: return "fsqrt"; 4757 case ISD::FSIN: return "fsin"; 4758 case ISD::FCOS: return "fcos"; 4759 case ISD::FPOWI: return "fpowi"; 4760 case ISD::FPOW: return "fpow"; 4761 4762 // Binary operators 4763 case ISD::ADD: return "add"; 4764 case ISD::SUB: return "sub"; 4765 case ISD::MUL: return "mul"; 4766 case ISD::MULHU: return "mulhu"; 4767 case ISD::MULHS: return "mulhs"; 4768 case ISD::SDIV: return "sdiv"; 4769 case ISD::UDIV: return "udiv"; 4770 case ISD::SREM: return "srem"; 4771 case ISD::UREM: return "urem"; 4772 case ISD::SMUL_LOHI: return "smul_lohi"; 4773 case ISD::UMUL_LOHI: return "umul_lohi"; 4774 case ISD::SDIVREM: return "sdivrem"; 4775 case ISD::UDIVREM: return "divrem"; 4776 case ISD::AND: return "and"; 4777 case ISD::OR: return "or"; 4778 case ISD::XOR: return "xor"; 4779 case ISD::SHL: return "shl"; 4780 case ISD::SRA: return "sra"; 4781 case ISD::SRL: return "srl"; 4782 case ISD::ROTL: return "rotl"; 4783 case ISD::ROTR: return "rotr"; 4784 case ISD::FADD: return "fadd"; 4785 case ISD::FSUB: return "fsub"; 4786 case ISD::FMUL: return "fmul"; 4787 case ISD::FDIV: return "fdiv"; 4788 case ISD::FREM: return "frem"; 4789 case ISD::FCOPYSIGN: return "fcopysign"; 4790 case ISD::FGETSIGN: return "fgetsign"; 4791 4792 case ISD::SETCC: return "setcc"; 4793 case ISD::VSETCC: return "vsetcc"; 4794 case ISD::SELECT: return "select"; 4795 case ISD::SELECT_CC: return "select_cc"; 4796 case ISD::INSERT_VECTOR_ELT: return "insert_vector_elt"; 4797 case ISD::EXTRACT_VECTOR_ELT: return "extract_vector_elt"; 4798 case ISD::CONCAT_VECTORS: return "concat_vectors"; 4799 case ISD::EXTRACT_SUBVECTOR: return "extract_subvector"; 4800 case ISD::SCALAR_TO_VECTOR: return "scalar_to_vector"; 4801 case ISD::VECTOR_SHUFFLE: return "vector_shuffle"; 4802 case ISD::CARRY_FALSE: return "carry_false"; 4803 case ISD::ADDC: return "addc"; 4804 case ISD::ADDE: return "adde"; 4805 case ISD::SUBC: return "subc"; 4806 case ISD::SUBE: return "sube"; 4807 case ISD::SHL_PARTS: return "shl_parts"; 4808 case ISD::SRA_PARTS: return "sra_parts"; 4809 case ISD::SRL_PARTS: return "srl_parts"; 4810 4811 case ISD::EXTRACT_SUBREG: return "extract_subreg"; 4812 case ISD::INSERT_SUBREG: return "insert_subreg"; 4813 4814 // Conversion operators. 4815 case ISD::SIGN_EXTEND: return "sign_extend"; 4816 case ISD::ZERO_EXTEND: return "zero_extend"; 4817 case ISD::ANY_EXTEND: return "any_extend"; 4818 case ISD::SIGN_EXTEND_INREG: return "sign_extend_inreg"; 4819 case ISD::TRUNCATE: return "truncate"; 4820 case ISD::FP_ROUND: return "fp_round"; 4821 case ISD::FLT_ROUNDS_: return "flt_rounds"; 4822 case ISD::FP_ROUND_INREG: return "fp_round_inreg"; 4823 case ISD::FP_EXTEND: return "fp_extend"; 4824 4825 case ISD::SINT_TO_FP: return "sint_to_fp"; 4826 case ISD::UINT_TO_FP: return "uint_to_fp"; 4827 case ISD::FP_TO_SINT: return "fp_to_sint"; 4828 case ISD::FP_TO_UINT: return "fp_to_uint"; 4829 case ISD::BIT_CONVERT: return "bit_convert"; 4830 4831 // Control flow instructions 4832 case ISD::BR: return "br"; 4833 case ISD::BRIND: return "brind"; 4834 case ISD::BR_JT: return "br_jt"; 4835 case ISD::BRCOND: return "brcond"; 4836 case ISD::BR_CC: return "br_cc"; 4837 case ISD::RET: return "ret"; 4838 case ISD::CALLSEQ_START: return "callseq_start"; 4839 case ISD::CALLSEQ_END: return "callseq_end"; 4840 4841 // Other operators 4842 case ISD::LOAD: return "load"; 4843 case ISD::STORE: return "store"; 4844 case ISD::VAARG: return "vaarg"; 4845 case ISD::VACOPY: return "vacopy"; 4846 case ISD::VAEND: return "vaend"; 4847 case ISD::VASTART: return "vastart"; 4848 case ISD::DYNAMIC_STACKALLOC: return "dynamic_stackalloc"; 4849 case ISD::EXTRACT_ELEMENT: return "extract_element"; 4850 case ISD::BUILD_PAIR: return "build_pair"; 4851 case ISD::STACKSAVE: return "stacksave"; 4852 case ISD::STACKRESTORE: return "stackrestore"; 4853 case ISD::TRAP: return "trap"; 4854 4855 // Bit manipulation 4856 case ISD::BSWAP: return "bswap"; 4857 case ISD::CTPOP: return "ctpop"; 4858 case ISD::CTTZ: return "cttz"; 4859 case ISD::CTLZ: return "ctlz"; 4860 4861 // Debug info 4862 case ISD::DBG_STOPPOINT: return "dbg_stoppoint"; 4863 case ISD::DEBUG_LOC: return "debug_loc"; 4864 4865 // Trampolines 4866 case ISD::TRAMPOLINE: return "trampoline"; 4867 4868 case ISD::CONDCODE: 4869 switch (cast<CondCodeSDNode>(this)->get()) { 4870 default: assert(0 && "Unknown setcc condition!"); 4871 case ISD::SETOEQ: return "setoeq"; 4872 case ISD::SETOGT: return "setogt"; 4873 case ISD::SETOGE: return "setoge"; 4874 case ISD::SETOLT: return "setolt"; 4875 case ISD::SETOLE: return "setole"; 4876 case ISD::SETONE: return "setone"; 4877 4878 case ISD::SETO: return "seto"; 4879 case ISD::SETUO: return "setuo"; 4880 case ISD::SETUEQ: return "setue"; 4881 case ISD::SETUGT: return "setugt"; 4882 case ISD::SETUGE: return "setuge"; 4883 case ISD::SETULT: return "setult"; 4884 case ISD::SETULE: return "setule"; 4885 case ISD::SETUNE: return "setune"; 4886 4887 case ISD::SETEQ: return "seteq"; 4888 case ISD::SETGT: return "setgt"; 4889 case ISD::SETGE: return "setge"; 4890 case ISD::SETLT: return "setlt"; 4891 case ISD::SETLE: return "setle"; 4892 case ISD::SETNE: return "setne"; 4893 } 4894 } 4895} 4896 4897const char *SDNode::getIndexedModeName(ISD::MemIndexedMode AM) { 4898 switch (AM) { 4899 default: 4900 return ""; 4901 case ISD::PRE_INC: 4902 return "<pre-inc>"; 4903 case ISD::PRE_DEC: 4904 return "<pre-dec>"; 4905 case ISD::POST_INC: 4906 return "<post-inc>"; 4907 case ISD::POST_DEC: 4908 return "<post-dec>"; 4909 } 4910} 4911 4912std::string ISD::ArgFlagsTy::getArgFlagsString() { 4913 std::string S = "< "; 4914 4915 if (isZExt()) 4916 S += "zext "; 4917 if (isSExt()) 4918 S += "sext "; 4919 if (isInReg()) 4920 S += "inreg "; 4921 if (isSRet()) 4922 S += "sret "; 4923 if (isByVal()) 4924 S += "byval "; 4925 if (isNest()) 4926 S += "nest "; 4927 if (getByValAlign()) 4928 S += "byval-align:" + utostr(getByValAlign()) + " "; 4929 if (getOrigAlign()) 4930 S += "orig-align:" + utostr(getOrigAlign()) + " "; 4931 if (getByValSize()) 4932 S += "byval-size:" + utostr(getByValSize()) + " "; 4933 return S + ">"; 4934} 4935 4936void SDNode::dump() const { dump(0); } 4937void SDNode::dump(const SelectionDAG *G) const { 4938 cerr << (void*)this << ": "; 4939 4940 for (unsigned i = 0, e = getNumValues(); i != e; ++i) { 4941 if (i) cerr << ","; 4942 if (getValueType(i) == MVT::Other) 4943 cerr << "ch"; 4944 else 4945 cerr << getValueType(i).getMVTString(); 4946 } 4947 cerr << " = " << getOperationName(G); 4948 4949 cerr << " "; 4950 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 4951 if (i) cerr << ", "; 4952 cerr << (void*)getOperand(i).Val; 4953 if (unsigned RN = getOperand(i).ResNo) 4954 cerr << ":" << RN; 4955 } 4956 4957 if (!isTargetOpcode() && getOpcode() == ISD::VECTOR_SHUFFLE) { 4958 SDNode *Mask = getOperand(2).Val; 4959 cerr << "<"; 4960 for (unsigned i = 0, e = Mask->getNumOperands(); i != e; ++i) { 4961 if (i) cerr << ","; 4962 if (Mask->getOperand(i).getOpcode() == ISD::UNDEF) 4963 cerr << "u"; 4964 else 4965 cerr << cast<ConstantSDNode>(Mask->getOperand(i))->getValue(); 4966 } 4967 cerr << ">"; 4968 } 4969 4970 if (const ConstantSDNode *CSDN = dyn_cast<ConstantSDNode>(this)) { 4971 cerr << "<" << CSDN->getAPIntValue().toStringUnsigned() << ">"; 4972 } else if (const ConstantFPSDNode *CSDN = dyn_cast<ConstantFPSDNode>(this)) { 4973 if (&CSDN->getValueAPF().getSemantics()==&APFloat::IEEEsingle) 4974 cerr << "<" << CSDN->getValueAPF().convertToFloat() << ">"; 4975 else if (&CSDN->getValueAPF().getSemantics()==&APFloat::IEEEdouble) 4976 cerr << "<" << CSDN->getValueAPF().convertToDouble() << ">"; 4977 else { 4978 cerr << "<APFloat("; 4979 CSDN->getValueAPF().convertToAPInt().dump(); 4980 cerr << ")>"; 4981 } 4982 } else if (const GlobalAddressSDNode *GADN = 4983 dyn_cast<GlobalAddressSDNode>(this)) { 4984 int offset = GADN->getOffset(); 4985 cerr << "<"; 4986 WriteAsOperand(*cerr.stream(), GADN->getGlobal()) << ">"; 4987 if (offset > 0) 4988 cerr << " + " << offset; 4989 else 4990 cerr << " " << offset; 4991 } else if (const FrameIndexSDNode *FIDN = dyn_cast<FrameIndexSDNode>(this)) { 4992 cerr << "<" << FIDN->getIndex() << ">"; 4993 } else if (const JumpTableSDNode *JTDN = dyn_cast<JumpTableSDNode>(this)) { 4994 cerr << "<" << JTDN->getIndex() << ">"; 4995 } else if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(this)){ 4996 int offset = CP->getOffset(); 4997 if (CP->isMachineConstantPoolEntry()) 4998 cerr << "<" << *CP->getMachineCPVal() << ">"; 4999 else 5000 cerr << "<" << *CP->getConstVal() << ">"; 5001 if (offset > 0) 5002 cerr << " + " << offset; 5003 else 5004 cerr << " " << offset; 5005 } else if (const BasicBlockSDNode *BBDN = dyn_cast<BasicBlockSDNode>(this)) { 5006 cerr << "<"; 5007 const Value *LBB = (const Value*)BBDN->getBasicBlock()->getBasicBlock(); 5008 if (LBB) 5009 cerr << LBB->getName() << " "; 5010 cerr << (const void*)BBDN->getBasicBlock() << ">"; 5011 } else if (const RegisterSDNode *R = dyn_cast<RegisterSDNode>(this)) { 5012 if (G && R->getReg() && 5013 TargetRegisterInfo::isPhysicalRegister(R->getReg())) { 5014 cerr << " " << G->getTarget().getRegisterInfo()->getName(R->getReg()); 5015 } else { 5016 cerr << " #" << R->getReg(); 5017 } 5018 } else if (const ExternalSymbolSDNode *ES = 5019 dyn_cast<ExternalSymbolSDNode>(this)) { 5020 cerr << "'" << ES->getSymbol() << "'"; 5021 } else if (const SrcValueSDNode *M = dyn_cast<SrcValueSDNode>(this)) { 5022 if (M->getValue()) 5023 cerr << "<" << M->getValue() << ">"; 5024 else 5025 cerr << "<null>"; 5026 } else if (const MemOperandSDNode *M = dyn_cast<MemOperandSDNode>(this)) { 5027 if (M->MO.getValue()) 5028 cerr << "<" << M->MO.getValue() << ":" << M->MO.getOffset() << ">"; 5029 else 5030 cerr << "<null:" << M->MO.getOffset() << ">"; 5031 } else if (const ARG_FLAGSSDNode *N = dyn_cast<ARG_FLAGSSDNode>(this)) { 5032 cerr << N->getArgFlags().getArgFlagsString(); 5033 } else if (const VTSDNode *N = dyn_cast<VTSDNode>(this)) { 5034 cerr << ":" << N->getVT().getMVTString(); 5035 } 5036 else if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(this)) { 5037 const Value *SrcValue = LD->getSrcValue(); 5038 int SrcOffset = LD->getSrcValueOffset(); 5039 cerr << " <"; 5040 if (SrcValue) 5041 cerr << SrcValue; 5042 else 5043 cerr << "null"; 5044 cerr << ":" << SrcOffset << ">"; 5045 5046 bool doExt = true; 5047 switch (LD->getExtensionType()) { 5048 default: doExt = false; break; 5049 case ISD::EXTLOAD: 5050 cerr << " <anyext "; 5051 break; 5052 case ISD::SEXTLOAD: 5053 cerr << " <sext "; 5054 break; 5055 case ISD::ZEXTLOAD: 5056 cerr << " <zext "; 5057 break; 5058 } 5059 if (doExt) 5060 cerr << LD->getMemoryVT().getMVTString() << ">"; 5061 5062 const char *AM = getIndexedModeName(LD->getAddressingMode()); 5063 if (*AM) 5064 cerr << " " << AM; 5065 if (LD->isVolatile()) 5066 cerr << " <volatile>"; 5067 cerr << " alignment=" << LD->getAlignment(); 5068 } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(this)) { 5069 const Value *SrcValue = ST->getSrcValue(); 5070 int SrcOffset = ST->getSrcValueOffset(); 5071 cerr << " <"; 5072 if (SrcValue) 5073 cerr << SrcValue; 5074 else 5075 cerr << "null"; 5076 cerr << ":" << SrcOffset << ">"; 5077 5078 if (ST->isTruncatingStore()) 5079 cerr << " <trunc " 5080 << ST->getMemoryVT().getMVTString() << ">"; 5081 5082 const char *AM = getIndexedModeName(ST->getAddressingMode()); 5083 if (*AM) 5084 cerr << " " << AM; 5085 if (ST->isVolatile()) 5086 cerr << " <volatile>"; 5087 cerr << " alignment=" << ST->getAlignment(); 5088 } else if (const AtomicSDNode* AT = dyn_cast<AtomicSDNode>(this)) { 5089 const Value *SrcValue = AT->getSrcValue(); 5090 int SrcOffset = AT->getSrcValueOffset(); 5091 cerr << " <"; 5092 if (SrcValue) 5093 cerr << SrcValue; 5094 else 5095 cerr << "null"; 5096 cerr << ":" << SrcOffset << ">"; 5097 if (AT->isVolatile()) 5098 cerr << " <volatile>"; 5099 cerr << " alignment=" << AT->getAlignment(); 5100 } 5101} 5102 5103static void DumpNodes(const SDNode *N, unsigned indent, const SelectionDAG *G) { 5104 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 5105 if (N->getOperand(i).Val->hasOneUse()) 5106 DumpNodes(N->getOperand(i).Val, indent+2, G); 5107 else 5108 cerr << "\n" << std::string(indent+2, ' ') 5109 << (void*)N->getOperand(i).Val << ": <multiple use>"; 5110 5111 5112 cerr << "\n" << std::string(indent, ' '); 5113 N->dump(G); 5114} 5115 5116void SelectionDAG::dump() const { 5117 cerr << "SelectionDAG has " << AllNodes.size() << " nodes:"; 5118 5119 for (allnodes_const_iterator I = allnodes_begin(), E = allnodes_end(); 5120 I != E; ++I) { 5121 const SDNode *N = I; 5122 if (!N->hasOneUse() && N != getRoot().Val) 5123 DumpNodes(N, 2, this); 5124 } 5125 5126 if (getRoot().Val) DumpNodes(getRoot().Val, 2, this); 5127 5128 cerr << "\n\n"; 5129} 5130 5131const Type *ConstantPoolSDNode::getType() const { 5132 if (isMachineConstantPoolEntry()) 5133 return Val.MachineCPVal->getType(); 5134 return Val.ConstVal->getType(); 5135} 5136