SelectionDAG.cpp revision aeb06d246254e4829a49164a11eacced9a43d9d4
1//===-- SelectionDAG.cpp - Implement the SelectionDAG data structures -----===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAG class. 11// 12//===----------------------------------------------------------------------===// 13#include "llvm/CodeGen/SelectionDAG.h" 14#include "llvm/Constants.h" 15#include "llvm/Analysis/ValueTracking.h" 16#include "llvm/GlobalAlias.h" 17#include "llvm/GlobalVariable.h" 18#include "llvm/Intrinsics.h" 19#include "llvm/DerivedTypes.h" 20#include "llvm/Assembly/Writer.h" 21#include "llvm/CallingConv.h" 22#include "llvm/CodeGen/MachineBasicBlock.h" 23#include "llvm/CodeGen/MachineConstantPool.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/MachineModuleInfo.h" 26#include "llvm/CodeGen/PseudoSourceValue.h" 27#include "llvm/Target/TargetRegisterInfo.h" 28#include "llvm/Target/TargetData.h" 29#include "llvm/Target/TargetLowering.h" 30#include "llvm/Target/TargetInstrInfo.h" 31#include "llvm/Target/TargetMachine.h" 32#include "llvm/Support/CommandLine.h" 33#include "llvm/Support/MathExtras.h" 34#include "llvm/Support/raw_ostream.h" 35#include "llvm/ADT/SetVector.h" 36#include "llvm/ADT/SmallPtrSet.h" 37#include "llvm/ADT/SmallSet.h" 38#include "llvm/ADT/SmallVector.h" 39#include "llvm/ADT/StringExtras.h" 40#include <algorithm> 41#include <cmath> 42using namespace llvm; 43 44/// makeVTList - Return an instance of the SDVTList struct initialized with the 45/// specified members. 46static SDVTList makeVTList(const MVT *VTs, unsigned NumVTs) { 47 SDVTList Res = {VTs, NumVTs}; 48 return Res; 49} 50 51static const fltSemantics *MVTToAPFloatSemantics(MVT VT) { 52 switch (VT.getSimpleVT()) { 53 default: assert(0 && "Unknown FP format"); 54 case MVT::f32: return &APFloat::IEEEsingle; 55 case MVT::f64: return &APFloat::IEEEdouble; 56 case MVT::f80: return &APFloat::x87DoubleExtended; 57 case MVT::f128: return &APFloat::IEEEquad; 58 case MVT::ppcf128: return &APFloat::PPCDoubleDouble; 59 } 60} 61 62SelectionDAG::DAGUpdateListener::~DAGUpdateListener() {} 63 64//===----------------------------------------------------------------------===// 65// ConstantFPSDNode Class 66//===----------------------------------------------------------------------===// 67 68/// isExactlyValue - We don't rely on operator== working on double values, as 69/// it returns true for things that are clearly not equal, like -0.0 and 0.0. 70/// As such, this method can be used to do an exact bit-for-bit comparison of 71/// two floating point values. 72bool ConstantFPSDNode::isExactlyValue(const APFloat& V) const { 73 return getValueAPF().bitwiseIsEqual(V); 74} 75 76bool ConstantFPSDNode::isValueValidForType(MVT VT, 77 const APFloat& Val) { 78 assert(VT.isFloatingPoint() && "Can only convert between FP types"); 79 80 // PPC long double cannot be converted to any other type. 81 if (VT == MVT::ppcf128 || 82 &Val.getSemantics() == &APFloat::PPCDoubleDouble) 83 return false; 84 85 // convert modifies in place, so make a copy. 86 APFloat Val2 = APFloat(Val); 87 bool losesInfo; 88 (void) Val2.convert(*MVTToAPFloatSemantics(VT), APFloat::rmNearestTiesToEven, 89 &losesInfo); 90 return !losesInfo; 91} 92 93//===----------------------------------------------------------------------===// 94// ISD Namespace 95//===----------------------------------------------------------------------===// 96 97/// isBuildVectorAllOnes - Return true if the specified node is a 98/// BUILD_VECTOR where all of the elements are ~0 or undef. 99bool ISD::isBuildVectorAllOnes(const SDNode *N) { 100 // Look through a bit convert. 101 if (N->getOpcode() == ISD::BIT_CONVERT) 102 N = N->getOperand(0).getNode(); 103 104 if (N->getOpcode() != ISD::BUILD_VECTOR) return false; 105 106 unsigned i = 0, e = N->getNumOperands(); 107 108 // Skip over all of the undef values. 109 while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF) 110 ++i; 111 112 // Do not accept an all-undef vector. 113 if (i == e) return false; 114 115 // Do not accept build_vectors that aren't all constants or which have non-~0 116 // elements. 117 SDValue NotZero = N->getOperand(i); 118 if (isa<ConstantSDNode>(NotZero)) { 119 if (!cast<ConstantSDNode>(NotZero)->isAllOnesValue()) 120 return false; 121 } else if (isa<ConstantFPSDNode>(NotZero)) { 122 if (!cast<ConstantFPSDNode>(NotZero)->getValueAPF(). 123 bitcastToAPInt().isAllOnesValue()) 124 return false; 125 } else 126 return false; 127 128 // Okay, we have at least one ~0 value, check to see if the rest match or are 129 // undefs. 130 for (++i; i != e; ++i) 131 if (N->getOperand(i) != NotZero && 132 N->getOperand(i).getOpcode() != ISD::UNDEF) 133 return false; 134 return true; 135} 136 137 138/// isBuildVectorAllZeros - Return true if the specified node is a 139/// BUILD_VECTOR where all of the elements are 0 or undef. 140bool ISD::isBuildVectorAllZeros(const SDNode *N) { 141 // Look through a bit convert. 142 if (N->getOpcode() == ISD::BIT_CONVERT) 143 N = N->getOperand(0).getNode(); 144 145 if (N->getOpcode() != ISD::BUILD_VECTOR) return false; 146 147 unsigned i = 0, e = N->getNumOperands(); 148 149 // Skip over all of the undef values. 150 while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF) 151 ++i; 152 153 // Do not accept an all-undef vector. 154 if (i == e) return false; 155 156 // Do not accept build_vectors that aren't all constants or which have non-~0 157 // elements. 158 SDValue Zero = N->getOperand(i); 159 if (isa<ConstantSDNode>(Zero)) { 160 if (!cast<ConstantSDNode>(Zero)->isNullValue()) 161 return false; 162 } else if (isa<ConstantFPSDNode>(Zero)) { 163 if (!cast<ConstantFPSDNode>(Zero)->getValueAPF().isPosZero()) 164 return false; 165 } else 166 return false; 167 168 // Okay, we have at least one ~0 value, check to see if the rest match or are 169 // undefs. 170 for (++i; i != e; ++i) 171 if (N->getOperand(i) != Zero && 172 N->getOperand(i).getOpcode() != ISD::UNDEF) 173 return false; 174 return true; 175} 176 177/// isScalarToVector - Return true if the specified node is a 178/// ISD::SCALAR_TO_VECTOR node or a BUILD_VECTOR node where only the low 179/// element is not an undef. 180bool ISD::isScalarToVector(const SDNode *N) { 181 if (N->getOpcode() == ISD::SCALAR_TO_VECTOR) 182 return true; 183 184 if (N->getOpcode() != ISD::BUILD_VECTOR) 185 return false; 186 if (N->getOperand(0).getOpcode() == ISD::UNDEF) 187 return false; 188 unsigned NumElems = N->getNumOperands(); 189 for (unsigned i = 1; i < NumElems; ++i) { 190 SDValue V = N->getOperand(i); 191 if (V.getOpcode() != ISD::UNDEF) 192 return false; 193 } 194 return true; 195} 196 197 198/// isDebugLabel - Return true if the specified node represents a debug 199/// label (i.e. ISD::DBG_LABEL or TargetInstrInfo::DBG_LABEL node). 200bool ISD::isDebugLabel(const SDNode *N) { 201 SDValue Zero; 202 if (N->getOpcode() == ISD::DBG_LABEL) 203 return true; 204 if (N->isMachineOpcode() && 205 N->getMachineOpcode() == TargetInstrInfo::DBG_LABEL) 206 return true; 207 return false; 208} 209 210/// getSetCCSwappedOperands - Return the operation corresponding to (Y op X) 211/// when given the operation for (X op Y). 212ISD::CondCode ISD::getSetCCSwappedOperands(ISD::CondCode Operation) { 213 // To perform this operation, we just need to swap the L and G bits of the 214 // operation. 215 unsigned OldL = (Operation >> 2) & 1; 216 unsigned OldG = (Operation >> 1) & 1; 217 return ISD::CondCode((Operation & ~6) | // Keep the N, U, E bits 218 (OldL << 1) | // New G bit 219 (OldG << 2)); // New L bit. 220} 221 222/// getSetCCInverse - Return the operation corresponding to !(X op Y), where 223/// 'op' is a valid SetCC operation. 224ISD::CondCode ISD::getSetCCInverse(ISD::CondCode Op, bool isInteger) { 225 unsigned Operation = Op; 226 if (isInteger) 227 Operation ^= 7; // Flip L, G, E bits, but not U. 228 else 229 Operation ^= 15; // Flip all of the condition bits. 230 231 if (Operation > ISD::SETTRUE2) 232 Operation &= ~8; // Don't let N and U bits get set. 233 234 return ISD::CondCode(Operation); 235} 236 237 238/// isSignedOp - For an integer comparison, return 1 if the comparison is a 239/// signed operation and 2 if the result is an unsigned comparison. Return zero 240/// if the operation does not depend on the sign of the input (setne and seteq). 241static int isSignedOp(ISD::CondCode Opcode) { 242 switch (Opcode) { 243 default: assert(0 && "Illegal integer setcc operation!"); 244 case ISD::SETEQ: 245 case ISD::SETNE: return 0; 246 case ISD::SETLT: 247 case ISD::SETLE: 248 case ISD::SETGT: 249 case ISD::SETGE: return 1; 250 case ISD::SETULT: 251 case ISD::SETULE: 252 case ISD::SETUGT: 253 case ISD::SETUGE: return 2; 254 } 255} 256 257/// getSetCCOrOperation - Return the result of a logical OR between different 258/// comparisons of identical values: ((X op1 Y) | (X op2 Y)). This function 259/// returns SETCC_INVALID if it is not possible to represent the resultant 260/// comparison. 261ISD::CondCode ISD::getSetCCOrOperation(ISD::CondCode Op1, ISD::CondCode Op2, 262 bool isInteger) { 263 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 264 // Cannot fold a signed integer setcc with an unsigned integer setcc. 265 return ISD::SETCC_INVALID; 266 267 unsigned Op = Op1 | Op2; // Combine all of the condition bits. 268 269 // If the N and U bits get set then the resultant comparison DOES suddenly 270 // care about orderedness, and is true when ordered. 271 if (Op > ISD::SETTRUE2) 272 Op &= ~16; // Clear the U bit if the N bit is set. 273 274 // Canonicalize illegal integer setcc's. 275 if (isInteger && Op == ISD::SETUNE) // e.g. SETUGT | SETULT 276 Op = ISD::SETNE; 277 278 return ISD::CondCode(Op); 279} 280 281/// getSetCCAndOperation - Return the result of a logical AND between different 282/// comparisons of identical values: ((X op1 Y) & (X op2 Y)). This 283/// function returns zero if it is not possible to represent the resultant 284/// comparison. 285ISD::CondCode ISD::getSetCCAndOperation(ISD::CondCode Op1, ISD::CondCode Op2, 286 bool isInteger) { 287 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 288 // Cannot fold a signed setcc with an unsigned setcc. 289 return ISD::SETCC_INVALID; 290 291 // Combine all of the condition bits. 292 ISD::CondCode Result = ISD::CondCode(Op1 & Op2); 293 294 // Canonicalize illegal integer setcc's. 295 if (isInteger) { 296 switch (Result) { 297 default: break; 298 case ISD::SETUO : Result = ISD::SETFALSE; break; // SETUGT & SETULT 299 case ISD::SETOEQ: // SETEQ & SETU[LG]E 300 case ISD::SETUEQ: Result = ISD::SETEQ ; break; // SETUGE & SETULE 301 case ISD::SETOLT: Result = ISD::SETULT ; break; // SETULT & SETNE 302 case ISD::SETOGT: Result = ISD::SETUGT ; break; // SETUGT & SETNE 303 } 304 } 305 306 return Result; 307} 308 309const TargetMachine &SelectionDAG::getTarget() const { 310 return MF->getTarget(); 311} 312 313//===----------------------------------------------------------------------===// 314// SDNode Profile Support 315//===----------------------------------------------------------------------===// 316 317/// AddNodeIDOpcode - Add the node opcode to the NodeID data. 318/// 319static void AddNodeIDOpcode(FoldingSetNodeID &ID, unsigned OpC) { 320 ID.AddInteger(OpC); 321} 322 323/// AddNodeIDValueTypes - Value type lists are intern'd so we can represent them 324/// solely with their pointer. 325static void AddNodeIDValueTypes(FoldingSetNodeID &ID, SDVTList VTList) { 326 ID.AddPointer(VTList.VTs); 327} 328 329/// AddNodeIDOperands - Various routines for adding operands to the NodeID data. 330/// 331static void AddNodeIDOperands(FoldingSetNodeID &ID, 332 const SDValue *Ops, unsigned NumOps) { 333 for (; NumOps; --NumOps, ++Ops) { 334 ID.AddPointer(Ops->getNode()); 335 ID.AddInteger(Ops->getResNo()); 336 } 337} 338 339/// AddNodeIDOperands - Various routines for adding operands to the NodeID data. 340/// 341static void AddNodeIDOperands(FoldingSetNodeID &ID, 342 const SDUse *Ops, unsigned NumOps) { 343 for (; NumOps; --NumOps, ++Ops) { 344 ID.AddPointer(Ops->getVal()); 345 ID.AddInteger(Ops->getSDValue().getResNo()); 346 } 347} 348 349static void AddNodeIDNode(FoldingSetNodeID &ID, 350 unsigned short OpC, SDVTList VTList, 351 const SDValue *OpList, unsigned N) { 352 AddNodeIDOpcode(ID, OpC); 353 AddNodeIDValueTypes(ID, VTList); 354 AddNodeIDOperands(ID, OpList, N); 355} 356 357/// AddNodeIDCustom - If this is an SDNode with special info, add this info to 358/// the NodeID data. 359static void AddNodeIDCustom(FoldingSetNodeID &ID, const SDNode *N) { 360 switch (N->getOpcode()) { 361 default: break; // Normal nodes don't need extra info. 362 case ISD::ARG_FLAGS: 363 ID.AddInteger(cast<ARG_FLAGSSDNode>(N)->getArgFlags().getRawBits()); 364 break; 365 case ISD::TargetConstant: 366 case ISD::Constant: 367 ID.AddPointer(cast<ConstantSDNode>(N)->getConstantIntValue()); 368 break; 369 case ISD::TargetConstantFP: 370 case ISD::ConstantFP: { 371 ID.AddPointer(cast<ConstantFPSDNode>(N)->getConstantFPValue()); 372 break; 373 } 374 case ISD::TargetGlobalAddress: 375 case ISD::GlobalAddress: 376 case ISD::TargetGlobalTLSAddress: 377 case ISD::GlobalTLSAddress: { 378 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(N); 379 ID.AddPointer(GA->getGlobal()); 380 ID.AddInteger(GA->getOffset()); 381 break; 382 } 383 case ISD::BasicBlock: 384 ID.AddPointer(cast<BasicBlockSDNode>(N)->getBasicBlock()); 385 break; 386 case ISD::Register: 387 ID.AddInteger(cast<RegisterSDNode>(N)->getReg()); 388 break; 389 case ISD::DBG_STOPPOINT: { 390 const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(N); 391 ID.AddInteger(DSP->getLine()); 392 ID.AddInteger(DSP->getColumn()); 393 ID.AddPointer(DSP->getCompileUnit()); 394 break; 395 } 396 case ISD::SRCVALUE: 397 ID.AddPointer(cast<SrcValueSDNode>(N)->getValue()); 398 break; 399 case ISD::MEMOPERAND: { 400 const MachineMemOperand &MO = cast<MemOperandSDNode>(N)->MO; 401 MO.Profile(ID); 402 break; 403 } 404 case ISD::FrameIndex: 405 case ISD::TargetFrameIndex: 406 ID.AddInteger(cast<FrameIndexSDNode>(N)->getIndex()); 407 break; 408 case ISD::JumpTable: 409 case ISD::TargetJumpTable: 410 ID.AddInteger(cast<JumpTableSDNode>(N)->getIndex()); 411 break; 412 case ISD::ConstantPool: 413 case ISD::TargetConstantPool: { 414 const ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(N); 415 ID.AddInteger(CP->getAlignment()); 416 ID.AddInteger(CP->getOffset()); 417 if (CP->isMachineConstantPoolEntry()) 418 CP->getMachineCPVal()->AddSelectionDAGCSEId(ID); 419 else 420 ID.AddPointer(CP->getConstVal()); 421 break; 422 } 423 case ISD::CALL: { 424 const CallSDNode *Call = cast<CallSDNode>(N); 425 ID.AddInteger(Call->getCallingConv()); 426 ID.AddInteger(Call->isVarArg()); 427 break; 428 } 429 case ISD::LOAD: { 430 const LoadSDNode *LD = cast<LoadSDNode>(N); 431 ID.AddInteger(LD->getAddressingMode()); 432 ID.AddInteger(LD->getExtensionType()); 433 ID.AddInteger(LD->getMemoryVT().getRawBits()); 434 ID.AddInteger(LD->getRawFlags()); 435 break; 436 } 437 case ISD::STORE: { 438 const StoreSDNode *ST = cast<StoreSDNode>(N); 439 ID.AddInteger(ST->getAddressingMode()); 440 ID.AddInteger(ST->isTruncatingStore()); 441 ID.AddInteger(ST->getMemoryVT().getRawBits()); 442 ID.AddInteger(ST->getRawFlags()); 443 break; 444 } 445 case ISD::ATOMIC_CMP_SWAP_8: 446 case ISD::ATOMIC_SWAP_8: 447 case ISD::ATOMIC_LOAD_ADD_8: 448 case ISD::ATOMIC_LOAD_SUB_8: 449 case ISD::ATOMIC_LOAD_AND_8: 450 case ISD::ATOMIC_LOAD_OR_8: 451 case ISD::ATOMIC_LOAD_XOR_8: 452 case ISD::ATOMIC_LOAD_NAND_8: 453 case ISD::ATOMIC_LOAD_MIN_8: 454 case ISD::ATOMIC_LOAD_MAX_8: 455 case ISD::ATOMIC_LOAD_UMIN_8: 456 case ISD::ATOMIC_LOAD_UMAX_8: 457 case ISD::ATOMIC_CMP_SWAP_16: 458 case ISD::ATOMIC_SWAP_16: 459 case ISD::ATOMIC_LOAD_ADD_16: 460 case ISD::ATOMIC_LOAD_SUB_16: 461 case ISD::ATOMIC_LOAD_AND_16: 462 case ISD::ATOMIC_LOAD_OR_16: 463 case ISD::ATOMIC_LOAD_XOR_16: 464 case ISD::ATOMIC_LOAD_NAND_16: 465 case ISD::ATOMIC_LOAD_MIN_16: 466 case ISD::ATOMIC_LOAD_MAX_16: 467 case ISD::ATOMIC_LOAD_UMIN_16: 468 case ISD::ATOMIC_LOAD_UMAX_16: 469 case ISD::ATOMIC_CMP_SWAP_32: 470 case ISD::ATOMIC_SWAP_32: 471 case ISD::ATOMIC_LOAD_ADD_32: 472 case ISD::ATOMIC_LOAD_SUB_32: 473 case ISD::ATOMIC_LOAD_AND_32: 474 case ISD::ATOMIC_LOAD_OR_32: 475 case ISD::ATOMIC_LOAD_XOR_32: 476 case ISD::ATOMIC_LOAD_NAND_32: 477 case ISD::ATOMIC_LOAD_MIN_32: 478 case ISD::ATOMIC_LOAD_MAX_32: 479 case ISD::ATOMIC_LOAD_UMIN_32: 480 case ISD::ATOMIC_LOAD_UMAX_32: 481 case ISD::ATOMIC_CMP_SWAP_64: 482 case ISD::ATOMIC_SWAP_64: 483 case ISD::ATOMIC_LOAD_ADD_64: 484 case ISD::ATOMIC_LOAD_SUB_64: 485 case ISD::ATOMIC_LOAD_AND_64: 486 case ISD::ATOMIC_LOAD_OR_64: 487 case ISD::ATOMIC_LOAD_XOR_64: 488 case ISD::ATOMIC_LOAD_NAND_64: 489 case ISD::ATOMIC_LOAD_MIN_64: 490 case ISD::ATOMIC_LOAD_MAX_64: 491 case ISD::ATOMIC_LOAD_UMIN_64: 492 case ISD::ATOMIC_LOAD_UMAX_64: { 493 const AtomicSDNode *AT = cast<AtomicSDNode>(N); 494 ID.AddInteger(AT->getRawFlags()); 495 break; 496 } 497 } // end switch (N->getOpcode()) 498} 499 500/// AddNodeIDNode - Generic routine for adding a nodes info to the NodeID 501/// data. 502static void AddNodeIDNode(FoldingSetNodeID &ID, const SDNode *N) { 503 AddNodeIDOpcode(ID, N->getOpcode()); 504 // Add the return value info. 505 AddNodeIDValueTypes(ID, N->getVTList()); 506 // Add the operand info. 507 AddNodeIDOperands(ID, N->op_begin(), N->getNumOperands()); 508 509 // Handle SDNode leafs with special info. 510 AddNodeIDCustom(ID, N); 511} 512 513/// encodeMemSDNodeFlags - Generic routine for computing a value for use in 514/// the CSE map that carries both alignment and volatility information. 515/// 516static inline unsigned 517encodeMemSDNodeFlags(bool isVolatile, unsigned Alignment) { 518 return isVolatile | ((Log2_32(Alignment) + 1) << 1); 519} 520 521//===----------------------------------------------------------------------===// 522// SelectionDAG Class 523//===----------------------------------------------------------------------===// 524 525/// doNotCSE - Return true if CSE should not be performed for this node. 526static bool doNotCSE(SDNode *N) { 527 if (N->getValueType(0) == MVT::Flag) 528 return true; // Never CSE anything that produces a flag. 529 530 switch (N->getOpcode()) { 531 default: break; 532 case ISD::HANDLENODE: 533 case ISD::DBG_LABEL: 534 case ISD::DBG_STOPPOINT: 535 case ISD::EH_LABEL: 536 case ISD::DECLARE: 537 return true; // Never CSE these nodes. 538 } 539 540 // Check that remaining values produced are not flags. 541 for (unsigned i = 1, e = N->getNumValues(); i != e; ++i) 542 if (N->getValueType(i) == MVT::Flag) 543 return true; // Never CSE anything that produces a flag. 544 545 return false; 546} 547 548/// RemoveDeadNodes - This method deletes all unreachable nodes in the 549/// SelectionDAG. 550void SelectionDAG::RemoveDeadNodes() { 551 // Create a dummy node (which is not added to allnodes), that adds a reference 552 // to the root node, preventing it from being deleted. 553 HandleSDNode Dummy(getRoot()); 554 555 SmallVector<SDNode*, 128> DeadNodes; 556 557 // Add all obviously-dead nodes to the DeadNodes worklist. 558 for (allnodes_iterator I = allnodes_begin(), E = allnodes_end(); I != E; ++I) 559 if (I->use_empty()) 560 DeadNodes.push_back(I); 561 562 RemoveDeadNodes(DeadNodes); 563 564 // If the root changed (e.g. it was a dead load, update the root). 565 setRoot(Dummy.getValue()); 566} 567 568/// RemoveDeadNodes - This method deletes the unreachable nodes in the 569/// given list, and any nodes that become unreachable as a result. 570void SelectionDAG::RemoveDeadNodes(SmallVectorImpl<SDNode *> &DeadNodes, 571 DAGUpdateListener *UpdateListener) { 572 573 // Process the worklist, deleting the nodes and adding their uses to the 574 // worklist. 575 while (!DeadNodes.empty()) { 576 SDNode *N = DeadNodes.back(); 577 DeadNodes.pop_back(); 578 579 if (UpdateListener) 580 UpdateListener->NodeDeleted(N, 0); 581 582 // Take the node out of the appropriate CSE map. 583 RemoveNodeFromCSEMaps(N); 584 585 // Next, brutally remove the operand list. This is safe to do, as there are 586 // no cycles in the graph. 587 for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ++I) { 588 SDNode *Operand = I->getVal(); 589 Operand->removeUser(std::distance(N->op_begin(), I), N); 590 591 // Now that we removed this operand, see if there are no uses of it left. 592 if (Operand->use_empty()) 593 DeadNodes.push_back(Operand); 594 } 595 596 if (N->OperandsNeedDelete) 597 delete[] N->OperandList; 598 599 N->OperandList = 0; 600 N->NumOperands = 0; 601 602 // Finally, remove N itself. 603 NodeAllocator.Deallocate(AllNodes.remove(N)); 604 } 605} 606 607void SelectionDAG::RemoveDeadNode(SDNode *N, DAGUpdateListener *UpdateListener){ 608 SmallVector<SDNode*, 16> DeadNodes(1, N); 609 RemoveDeadNodes(DeadNodes, UpdateListener); 610} 611 612void SelectionDAG::DeleteNode(SDNode *N) { 613 assert(N->use_empty() && "Cannot delete a node that is not dead!"); 614 615 // First take this out of the appropriate CSE map. 616 RemoveNodeFromCSEMaps(N); 617 618 // Finally, remove uses due to operands of this node, remove from the 619 // AllNodes list, and delete the node. 620 DeleteNodeNotInCSEMaps(N); 621} 622 623void SelectionDAG::DeleteNodeNotInCSEMaps(SDNode *N) { 624 // Drop all of the operands and decrement used node's use counts. 625 for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ++I) 626 I->getVal()->removeUser(std::distance(N->op_begin(), I), N); 627 628 if (N->OperandsNeedDelete) { 629 delete[] N->OperandList; 630 N->OperandList = 0; 631 } 632 633 assert(N != AllNodes.begin()); 634 NodeAllocator.Deallocate(AllNodes.remove(N)); 635} 636 637/// RemoveNodeFromCSEMaps - Take the specified node out of the CSE map that 638/// correspond to it. This is useful when we're about to delete or repurpose 639/// the node. We don't want future request for structurally identical nodes 640/// to return N anymore. 641bool SelectionDAG::RemoveNodeFromCSEMaps(SDNode *N) { 642 bool Erased = false; 643 switch (N->getOpcode()) { 644 case ISD::EntryToken: 645 assert(0 && "EntryToken should not be in CSEMaps!"); 646 return false; 647 case ISD::HANDLENODE: return false; // noop. 648 case ISD::CONDCODE: 649 assert(CondCodeNodes[cast<CondCodeSDNode>(N)->get()] && 650 "Cond code doesn't exist!"); 651 Erased = CondCodeNodes[cast<CondCodeSDNode>(N)->get()] != 0; 652 CondCodeNodes[cast<CondCodeSDNode>(N)->get()] = 0; 653 break; 654 case ISD::ExternalSymbol: 655 Erased = ExternalSymbols.erase(cast<ExternalSymbolSDNode>(N)->getSymbol()); 656 break; 657 case ISD::TargetExternalSymbol: 658 Erased = 659 TargetExternalSymbols.erase(cast<ExternalSymbolSDNode>(N)->getSymbol()); 660 break; 661 case ISD::VALUETYPE: { 662 MVT VT = cast<VTSDNode>(N)->getVT(); 663 if (VT.isExtended()) { 664 Erased = ExtendedValueTypeNodes.erase(VT); 665 } else { 666 Erased = ValueTypeNodes[VT.getSimpleVT()] != 0; 667 ValueTypeNodes[VT.getSimpleVT()] = 0; 668 } 669 break; 670 } 671 default: 672 // Remove it from the CSE Map. 673 Erased = CSEMap.RemoveNode(N); 674 break; 675 } 676#ifndef NDEBUG 677 // Verify that the node was actually in one of the CSE maps, unless it has a 678 // flag result (which cannot be CSE'd) or is one of the special cases that are 679 // not subject to CSE. 680 if (!Erased && N->getValueType(N->getNumValues()-1) != MVT::Flag && 681 !N->isMachineOpcode() && !doNotCSE(N)) { 682 N->dump(this); 683 cerr << "\n"; 684 assert(0 && "Node is not in map!"); 685 } 686#endif 687 return Erased; 688} 689 690/// AddNonLeafNodeToCSEMaps - Add the specified node back to the CSE maps. It 691/// has been taken out and modified in some way. If the specified node already 692/// exists in the CSE maps, do not modify the maps, but return the existing node 693/// instead. If it doesn't exist, add it and return null. 694/// 695SDNode *SelectionDAG::AddNonLeafNodeToCSEMaps(SDNode *N) { 696 assert(N->getNumOperands() && "This is a leaf node!"); 697 698 if (doNotCSE(N)) 699 return 0; 700 701 SDNode *New = CSEMap.GetOrInsertNode(N); 702 if (New != N) return New; // Node already existed. 703 return 0; 704} 705 706/// FindModifiedNodeSlot - Find a slot for the specified node if its operands 707/// were replaced with those specified. If this node is never memoized, 708/// return null, otherwise return a pointer to the slot it would take. If a 709/// node already exists with these operands, the slot will be non-null. 710SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, SDValue Op, 711 void *&InsertPos) { 712 if (doNotCSE(N)) 713 return 0; 714 715 SDValue Ops[] = { Op }; 716 FoldingSetNodeID ID; 717 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, 1); 718 AddNodeIDCustom(ID, N); 719 return CSEMap.FindNodeOrInsertPos(ID, InsertPos); 720} 721 722/// FindModifiedNodeSlot - Find a slot for the specified node if its operands 723/// were replaced with those specified. If this node is never memoized, 724/// return null, otherwise return a pointer to the slot it would take. If a 725/// node already exists with these operands, the slot will be non-null. 726SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, 727 SDValue Op1, SDValue Op2, 728 void *&InsertPos) { 729 if (doNotCSE(N)) 730 return 0; 731 732 SDValue Ops[] = { Op1, Op2 }; 733 FoldingSetNodeID ID; 734 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, 2); 735 AddNodeIDCustom(ID, N); 736 return CSEMap.FindNodeOrInsertPos(ID, InsertPos); 737} 738 739 740/// FindModifiedNodeSlot - Find a slot for the specified node if its operands 741/// were replaced with those specified. If this node is never memoized, 742/// return null, otherwise return a pointer to the slot it would take. If a 743/// node already exists with these operands, the slot will be non-null. 744SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, 745 const SDValue *Ops,unsigned NumOps, 746 void *&InsertPos) { 747 if (doNotCSE(N)) 748 return 0; 749 750 FoldingSetNodeID ID; 751 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, NumOps); 752 AddNodeIDCustom(ID, N); 753 return CSEMap.FindNodeOrInsertPos(ID, InsertPos); 754} 755 756/// VerifyNode - Sanity check the given node. Aborts if it is invalid. 757void SelectionDAG::VerifyNode(SDNode *N) { 758 switch (N->getOpcode()) { 759 default: 760 break; 761 case ISD::BUILD_PAIR: { 762 MVT VT = N->getValueType(0); 763 assert(N->getNumValues() == 1 && "Too many results!"); 764 assert(!VT.isVector() && (VT.isInteger() || VT.isFloatingPoint()) && 765 "Wrong return type!"); 766 assert(N->getNumOperands() == 2 && "Wrong number of operands!"); 767 assert(N->getOperand(0).getValueType() == N->getOperand(1).getValueType() && 768 "Mismatched operand types!"); 769 assert(N->getOperand(0).getValueType().isInteger() == VT.isInteger() && 770 "Wrong operand type!"); 771 assert(VT.getSizeInBits() == 2 * N->getOperand(0).getValueSizeInBits() && 772 "Wrong return type size"); 773 break; 774 } 775 case ISD::BUILD_VECTOR: { 776 assert(N->getNumValues() == 1 && "Too many results!"); 777 assert(N->getValueType(0).isVector() && "Wrong return type!"); 778 assert(N->getNumOperands() == N->getValueType(0).getVectorNumElements() && 779 "Wrong number of operands!"); 780 // FIXME: Change vector_shuffle to a variadic node with mask elements being 781 // operands of the node. Currently the mask is a BUILD_VECTOR passed as an 782 // operand, and it is not always possible to legalize it. Turning off the 783 // following checks at least makes it possible to legalize most of the time. 784// MVT EltVT = N->getValueType(0).getVectorElementType(); 785// for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ++I) 786// assert(I->getSDValue().getValueType() == EltVT && 787// "Wrong operand type!"); 788 break; 789 } 790 } 791} 792 793/// getMVTAlignment - Compute the default alignment value for the 794/// given type. 795/// 796unsigned SelectionDAG::getMVTAlignment(MVT VT) const { 797 const Type *Ty = VT == MVT::iPTR ? 798 PointerType::get(Type::Int8Ty, 0) : 799 VT.getTypeForMVT(); 800 801 return TLI.getTargetData()->getABITypeAlignment(Ty); 802} 803 804SelectionDAG::SelectionDAG(TargetLowering &tli, FunctionLoweringInfo &fli) 805 : TLI(tli), FLI(fli), 806 EntryNode(ISD::EntryToken, getVTList(MVT::Other)), 807 Root(getEntryNode()) { 808 AllNodes.push_back(&EntryNode); 809} 810 811void SelectionDAG::init(MachineFunction &mf, MachineModuleInfo *mmi) { 812 MF = &mf; 813 MMI = mmi; 814} 815 816SelectionDAG::~SelectionDAG() { 817 allnodes_clear(); 818} 819 820void SelectionDAG::allnodes_clear() { 821 assert(&*AllNodes.begin() == &EntryNode); 822 AllNodes.remove(AllNodes.begin()); 823 while (!AllNodes.empty()) { 824 SDNode *N = AllNodes.remove(AllNodes.begin()); 825 N->SetNextInBucket(0); 826 827 if (N->OperandsNeedDelete) { 828 delete [] N->OperandList; 829 N->OperandList = 0; 830 } 831 832 NodeAllocator.Deallocate(N); 833 } 834} 835 836void SelectionDAG::clear() { 837 allnodes_clear(); 838 OperandAllocator.Reset(); 839 CSEMap.clear(); 840 841 ExtendedValueTypeNodes.clear(); 842 ExternalSymbols.clear(); 843 TargetExternalSymbols.clear(); 844 std::fill(CondCodeNodes.begin(), CondCodeNodes.end(), 845 static_cast<CondCodeSDNode*>(0)); 846 std::fill(ValueTypeNodes.begin(), ValueTypeNodes.end(), 847 static_cast<SDNode*>(0)); 848 849 EntryNode.Uses = 0; 850 AllNodes.push_back(&EntryNode); 851 Root = getEntryNode(); 852} 853 854SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, MVT VT) { 855 if (Op.getValueType() == VT) return Op; 856 APInt Imm = APInt::getLowBitsSet(Op.getValueSizeInBits(), 857 VT.getSizeInBits()); 858 return getNode(ISD::AND, Op.getValueType(), Op, 859 getConstant(Imm, Op.getValueType())); 860} 861 862SDValue SelectionDAG::getConstant(uint64_t Val, MVT VT, bool isT) { 863 MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 864 return getConstant(APInt(EltVT.getSizeInBits(), Val), VT, isT); 865} 866 867SDValue SelectionDAG::getConstant(const APInt &Val, MVT VT, bool isT) { 868 return getConstant(*ConstantInt::get(Val), VT, isT); 869} 870 871SDValue SelectionDAG::getConstant(const ConstantInt &Val, MVT VT, bool isT) { 872 assert(VT.isInteger() && "Cannot create FP integer constant!"); 873 874 MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 875 assert(Val.getBitWidth() == EltVT.getSizeInBits() && 876 "APInt size does not match type size!"); 877 878 unsigned Opc = isT ? ISD::TargetConstant : ISD::Constant; 879 FoldingSetNodeID ID; 880 AddNodeIDNode(ID, Opc, getVTList(EltVT), 0, 0); 881 ID.AddPointer(&Val); 882 void *IP = 0; 883 SDNode *N = NULL; 884 if ((N = CSEMap.FindNodeOrInsertPos(ID, IP))) 885 if (!VT.isVector()) 886 return SDValue(N, 0); 887 if (!N) { 888 N = NodeAllocator.Allocate<ConstantSDNode>(); 889 new (N) ConstantSDNode(isT, &Val, EltVT); 890 CSEMap.InsertNode(N, IP); 891 AllNodes.push_back(N); 892 } 893 894 SDValue Result(N, 0); 895 if (VT.isVector()) { 896 SmallVector<SDValue, 8> Ops; 897 Ops.assign(VT.getVectorNumElements(), Result); 898 Result = getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 899 } 900 return Result; 901} 902 903SDValue SelectionDAG::getIntPtrConstant(uint64_t Val, bool isTarget) { 904 return getConstant(Val, TLI.getPointerTy(), isTarget); 905} 906 907 908SDValue SelectionDAG::getConstantFP(const APFloat& V, MVT VT, bool isTarget) { 909 return getConstantFP(*ConstantFP::get(V), VT, isTarget); 910} 911 912SDValue SelectionDAG::getConstantFP(const ConstantFP& V, MVT VT, bool isTarget){ 913 assert(VT.isFloatingPoint() && "Cannot create integer FP constant!"); 914 915 MVT EltVT = 916 VT.isVector() ? VT.getVectorElementType() : VT; 917 918 // Do the map lookup using the actual bit pattern for the floating point 919 // value, so that we don't have problems with 0.0 comparing equal to -0.0, and 920 // we don't have issues with SNANs. 921 unsigned Opc = isTarget ? ISD::TargetConstantFP : ISD::ConstantFP; 922 FoldingSetNodeID ID; 923 AddNodeIDNode(ID, Opc, getVTList(EltVT), 0, 0); 924 ID.AddPointer(&V); 925 void *IP = 0; 926 SDNode *N = NULL; 927 if ((N = CSEMap.FindNodeOrInsertPos(ID, IP))) 928 if (!VT.isVector()) 929 return SDValue(N, 0); 930 if (!N) { 931 N = NodeAllocator.Allocate<ConstantFPSDNode>(); 932 new (N) ConstantFPSDNode(isTarget, &V, EltVT); 933 CSEMap.InsertNode(N, IP); 934 AllNodes.push_back(N); 935 } 936 937 SDValue Result(N, 0); 938 if (VT.isVector()) { 939 SmallVector<SDValue, 8> Ops; 940 Ops.assign(VT.getVectorNumElements(), Result); 941 Result = getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 942 } 943 return Result; 944} 945 946SDValue SelectionDAG::getConstantFP(double Val, MVT VT, bool isTarget) { 947 MVT EltVT = 948 VT.isVector() ? VT.getVectorElementType() : VT; 949 if (EltVT==MVT::f32) 950 return getConstantFP(APFloat((float)Val), VT, isTarget); 951 else 952 return getConstantFP(APFloat(Val), VT, isTarget); 953} 954 955SDValue SelectionDAG::getGlobalAddress(const GlobalValue *GV, 956 MVT VT, int64_t Offset, 957 bool isTargetGA) { 958 unsigned Opc; 959 960 // Truncate (with sign-extension) the offset value to the pointer size. 961 unsigned BitWidth = TLI.getPointerTy().getSizeInBits(); 962 if (BitWidth < 64) 963 Offset = (Offset << (64 - BitWidth) >> (64 - BitWidth)); 964 965 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV); 966 if (!GVar) { 967 // If GV is an alias then use the aliasee for determining thread-localness. 968 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) 969 GVar = dyn_cast_or_null<GlobalVariable>(GA->resolveAliasedGlobal(false)); 970 } 971 972 if (GVar && GVar->isThreadLocal()) 973 Opc = isTargetGA ? ISD::TargetGlobalTLSAddress : ISD::GlobalTLSAddress; 974 else 975 Opc = isTargetGA ? ISD::TargetGlobalAddress : ISD::GlobalAddress; 976 977 FoldingSetNodeID ID; 978 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 979 ID.AddPointer(GV); 980 ID.AddInteger(Offset); 981 void *IP = 0; 982 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 983 return SDValue(E, 0); 984 SDNode *N = NodeAllocator.Allocate<GlobalAddressSDNode>(); 985 new (N) GlobalAddressSDNode(isTargetGA, GV, VT, Offset); 986 CSEMap.InsertNode(N, IP); 987 AllNodes.push_back(N); 988 return SDValue(N, 0); 989} 990 991SDValue SelectionDAG::getFrameIndex(int FI, MVT VT, bool isTarget) { 992 unsigned Opc = isTarget ? ISD::TargetFrameIndex : ISD::FrameIndex; 993 FoldingSetNodeID ID; 994 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 995 ID.AddInteger(FI); 996 void *IP = 0; 997 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 998 return SDValue(E, 0); 999 SDNode *N = NodeAllocator.Allocate<FrameIndexSDNode>(); 1000 new (N) FrameIndexSDNode(FI, VT, isTarget); 1001 CSEMap.InsertNode(N, IP); 1002 AllNodes.push_back(N); 1003 return SDValue(N, 0); 1004} 1005 1006SDValue SelectionDAG::getJumpTable(int JTI, MVT VT, bool isTarget){ 1007 unsigned Opc = isTarget ? ISD::TargetJumpTable : ISD::JumpTable; 1008 FoldingSetNodeID ID; 1009 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 1010 ID.AddInteger(JTI); 1011 void *IP = 0; 1012 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1013 return SDValue(E, 0); 1014 SDNode *N = NodeAllocator.Allocate<JumpTableSDNode>(); 1015 new (N) JumpTableSDNode(JTI, VT, isTarget); 1016 CSEMap.InsertNode(N, IP); 1017 AllNodes.push_back(N); 1018 return SDValue(N, 0); 1019} 1020 1021SDValue SelectionDAG::getConstantPool(Constant *C, MVT VT, 1022 unsigned Alignment, int Offset, 1023 bool isTarget) { 1024 if (Alignment == 0) 1025 Alignment = 1026 TLI.getTargetData()->getPreferredTypeAlignmentShift(C->getType()); 1027 unsigned Opc = isTarget ? ISD::TargetConstantPool : ISD::ConstantPool; 1028 FoldingSetNodeID ID; 1029 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 1030 ID.AddInteger(Alignment); 1031 ID.AddInteger(Offset); 1032 ID.AddPointer(C); 1033 void *IP = 0; 1034 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1035 return SDValue(E, 0); 1036 SDNode *N = NodeAllocator.Allocate<ConstantPoolSDNode>(); 1037 new (N) ConstantPoolSDNode(isTarget, C, VT, Offset, Alignment); 1038 CSEMap.InsertNode(N, IP); 1039 AllNodes.push_back(N); 1040 return SDValue(N, 0); 1041} 1042 1043 1044SDValue SelectionDAG::getConstantPool(MachineConstantPoolValue *C, MVT VT, 1045 unsigned Alignment, int Offset, 1046 bool isTarget) { 1047 if (Alignment == 0) 1048 Alignment = 1049 TLI.getTargetData()->getPreferredTypeAlignmentShift(C->getType()); 1050 unsigned Opc = isTarget ? ISD::TargetConstantPool : ISD::ConstantPool; 1051 FoldingSetNodeID ID; 1052 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 1053 ID.AddInteger(Alignment); 1054 ID.AddInteger(Offset); 1055 C->AddSelectionDAGCSEId(ID); 1056 void *IP = 0; 1057 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1058 return SDValue(E, 0); 1059 SDNode *N = NodeAllocator.Allocate<ConstantPoolSDNode>(); 1060 new (N) ConstantPoolSDNode(isTarget, C, VT, Offset, Alignment); 1061 CSEMap.InsertNode(N, IP); 1062 AllNodes.push_back(N); 1063 return SDValue(N, 0); 1064} 1065 1066 1067SDValue SelectionDAG::getBasicBlock(MachineBasicBlock *MBB) { 1068 FoldingSetNodeID ID; 1069 AddNodeIDNode(ID, ISD::BasicBlock, getVTList(MVT::Other), 0, 0); 1070 ID.AddPointer(MBB); 1071 void *IP = 0; 1072 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1073 return SDValue(E, 0); 1074 SDNode *N = NodeAllocator.Allocate<BasicBlockSDNode>(); 1075 new (N) BasicBlockSDNode(MBB); 1076 CSEMap.InsertNode(N, IP); 1077 AllNodes.push_back(N); 1078 return SDValue(N, 0); 1079} 1080 1081SDValue SelectionDAG::getArgFlags(ISD::ArgFlagsTy Flags) { 1082 FoldingSetNodeID ID; 1083 AddNodeIDNode(ID, ISD::ARG_FLAGS, getVTList(MVT::Other), 0, 0); 1084 ID.AddInteger(Flags.getRawBits()); 1085 void *IP = 0; 1086 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1087 return SDValue(E, 0); 1088 SDNode *N = NodeAllocator.Allocate<ARG_FLAGSSDNode>(); 1089 new (N) ARG_FLAGSSDNode(Flags); 1090 CSEMap.InsertNode(N, IP); 1091 AllNodes.push_back(N); 1092 return SDValue(N, 0); 1093} 1094 1095SDValue SelectionDAG::getValueType(MVT VT) { 1096 if (VT.isSimple() && (unsigned)VT.getSimpleVT() >= ValueTypeNodes.size()) 1097 ValueTypeNodes.resize(VT.getSimpleVT()+1); 1098 1099 SDNode *&N = VT.isExtended() ? 1100 ExtendedValueTypeNodes[VT] : ValueTypeNodes[VT.getSimpleVT()]; 1101 1102 if (N) return SDValue(N, 0); 1103 N = NodeAllocator.Allocate<VTSDNode>(); 1104 new (N) VTSDNode(VT); 1105 AllNodes.push_back(N); 1106 return SDValue(N, 0); 1107} 1108 1109SDValue SelectionDAG::getExternalSymbol(const char *Sym, MVT VT) { 1110 SDNode *&N = ExternalSymbols[Sym]; 1111 if (N) return SDValue(N, 0); 1112 N = NodeAllocator.Allocate<ExternalSymbolSDNode>(); 1113 new (N) ExternalSymbolSDNode(false, Sym, VT); 1114 AllNodes.push_back(N); 1115 return SDValue(N, 0); 1116} 1117 1118SDValue SelectionDAG::getTargetExternalSymbol(const char *Sym, MVT VT) { 1119 SDNode *&N = TargetExternalSymbols[Sym]; 1120 if (N) return SDValue(N, 0); 1121 N = NodeAllocator.Allocate<ExternalSymbolSDNode>(); 1122 new (N) ExternalSymbolSDNode(true, Sym, VT); 1123 AllNodes.push_back(N); 1124 return SDValue(N, 0); 1125} 1126 1127SDValue SelectionDAG::getCondCode(ISD::CondCode Cond) { 1128 if ((unsigned)Cond >= CondCodeNodes.size()) 1129 CondCodeNodes.resize(Cond+1); 1130 1131 if (CondCodeNodes[Cond] == 0) { 1132 CondCodeSDNode *N = NodeAllocator.Allocate<CondCodeSDNode>(); 1133 new (N) CondCodeSDNode(Cond); 1134 CondCodeNodes[Cond] = N; 1135 AllNodes.push_back(N); 1136 } 1137 return SDValue(CondCodeNodes[Cond], 0); 1138} 1139 1140SDValue SelectionDAG::getRegister(unsigned RegNo, MVT VT) { 1141 FoldingSetNodeID ID; 1142 AddNodeIDNode(ID, ISD::Register, getVTList(VT), 0, 0); 1143 ID.AddInteger(RegNo); 1144 void *IP = 0; 1145 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1146 return SDValue(E, 0); 1147 SDNode *N = NodeAllocator.Allocate<RegisterSDNode>(); 1148 new (N) RegisterSDNode(RegNo, VT); 1149 CSEMap.InsertNode(N, IP); 1150 AllNodes.push_back(N); 1151 return SDValue(N, 0); 1152} 1153 1154SDValue SelectionDAG::getDbgStopPoint(SDValue Root, 1155 unsigned Line, unsigned Col, 1156 const CompileUnitDesc *CU) { 1157 SDNode *N = NodeAllocator.Allocate<DbgStopPointSDNode>(); 1158 new (N) DbgStopPointSDNode(Root, Line, Col, CU); 1159 AllNodes.push_back(N); 1160 return SDValue(N, 0); 1161} 1162 1163SDValue SelectionDAG::getLabel(unsigned Opcode, 1164 SDValue Root, 1165 unsigned LabelID) { 1166 FoldingSetNodeID ID; 1167 SDValue Ops[] = { Root }; 1168 AddNodeIDNode(ID, Opcode, getVTList(MVT::Other), &Ops[0], 1); 1169 ID.AddInteger(LabelID); 1170 void *IP = 0; 1171 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1172 return SDValue(E, 0); 1173 SDNode *N = NodeAllocator.Allocate<LabelSDNode>(); 1174 new (N) LabelSDNode(Opcode, Root, LabelID); 1175 CSEMap.InsertNode(N, IP); 1176 AllNodes.push_back(N); 1177 return SDValue(N, 0); 1178} 1179 1180SDValue SelectionDAG::getSrcValue(const Value *V) { 1181 assert((!V || isa<PointerType>(V->getType())) && 1182 "SrcValue is not a pointer?"); 1183 1184 FoldingSetNodeID ID; 1185 AddNodeIDNode(ID, ISD::SRCVALUE, getVTList(MVT::Other), 0, 0); 1186 ID.AddPointer(V); 1187 1188 void *IP = 0; 1189 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1190 return SDValue(E, 0); 1191 1192 SDNode *N = NodeAllocator.Allocate<SrcValueSDNode>(); 1193 new (N) SrcValueSDNode(V); 1194 CSEMap.InsertNode(N, IP); 1195 AllNodes.push_back(N); 1196 return SDValue(N, 0); 1197} 1198 1199SDValue SelectionDAG::getMemOperand(const MachineMemOperand &MO) { 1200 const Value *v = MO.getValue(); 1201 assert((!v || isa<PointerType>(v->getType())) && 1202 "SrcValue is not a pointer?"); 1203 1204 FoldingSetNodeID ID; 1205 AddNodeIDNode(ID, ISD::MEMOPERAND, getVTList(MVT::Other), 0, 0); 1206 MO.Profile(ID); 1207 1208 void *IP = 0; 1209 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1210 return SDValue(E, 0); 1211 1212 SDNode *N = NodeAllocator.Allocate<MemOperandSDNode>(); 1213 new (N) MemOperandSDNode(MO); 1214 CSEMap.InsertNode(N, IP); 1215 AllNodes.push_back(N); 1216 return SDValue(N, 0); 1217} 1218 1219/// CreateStackTemporary - Create a stack temporary, suitable for holding the 1220/// specified value type. 1221SDValue SelectionDAG::CreateStackTemporary(MVT VT, unsigned minAlign) { 1222 MachineFrameInfo *FrameInfo = getMachineFunction().getFrameInfo(); 1223 unsigned ByteSize = VT.getSizeInBits()/8; 1224 const Type *Ty = VT.getTypeForMVT(); 1225 unsigned StackAlign = 1226 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), minAlign); 1227 1228 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, StackAlign); 1229 return getFrameIndex(FrameIdx, TLI.getPointerTy()); 1230} 1231 1232SDValue SelectionDAG::FoldSetCC(MVT VT, SDValue N1, 1233 SDValue N2, ISD::CondCode Cond) { 1234 // These setcc operations always fold. 1235 switch (Cond) { 1236 default: break; 1237 case ISD::SETFALSE: 1238 case ISD::SETFALSE2: return getConstant(0, VT); 1239 case ISD::SETTRUE: 1240 case ISD::SETTRUE2: return getConstant(1, VT); 1241 1242 case ISD::SETOEQ: 1243 case ISD::SETOGT: 1244 case ISD::SETOGE: 1245 case ISD::SETOLT: 1246 case ISD::SETOLE: 1247 case ISD::SETONE: 1248 case ISD::SETO: 1249 case ISD::SETUO: 1250 case ISD::SETUEQ: 1251 case ISD::SETUNE: 1252 assert(!N1.getValueType().isInteger() && "Illegal setcc for integer!"); 1253 break; 1254 } 1255 1256 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode())) { 1257 const APInt &C2 = N2C->getAPIntValue(); 1258 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) { 1259 const APInt &C1 = N1C->getAPIntValue(); 1260 1261 switch (Cond) { 1262 default: assert(0 && "Unknown integer setcc!"); 1263 case ISD::SETEQ: return getConstant(C1 == C2, VT); 1264 case ISD::SETNE: return getConstant(C1 != C2, VT); 1265 case ISD::SETULT: return getConstant(C1.ult(C2), VT); 1266 case ISD::SETUGT: return getConstant(C1.ugt(C2), VT); 1267 case ISD::SETULE: return getConstant(C1.ule(C2), VT); 1268 case ISD::SETUGE: return getConstant(C1.uge(C2), VT); 1269 case ISD::SETLT: return getConstant(C1.slt(C2), VT); 1270 case ISD::SETGT: return getConstant(C1.sgt(C2), VT); 1271 case ISD::SETLE: return getConstant(C1.sle(C2), VT); 1272 case ISD::SETGE: return getConstant(C1.sge(C2), VT); 1273 } 1274 } 1275 } 1276 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.getNode())) { 1277 if (ConstantFPSDNode *N2C = dyn_cast<ConstantFPSDNode>(N2.getNode())) { 1278 // No compile time operations on this type yet. 1279 if (N1C->getValueType(0) == MVT::ppcf128) 1280 return SDValue(); 1281 1282 APFloat::cmpResult R = N1C->getValueAPF().compare(N2C->getValueAPF()); 1283 switch (Cond) { 1284 default: break; 1285 case ISD::SETEQ: if (R==APFloat::cmpUnordered) 1286 return getNode(ISD::UNDEF, VT); 1287 // fall through 1288 case ISD::SETOEQ: return getConstant(R==APFloat::cmpEqual, VT); 1289 case ISD::SETNE: if (R==APFloat::cmpUnordered) 1290 return getNode(ISD::UNDEF, VT); 1291 // fall through 1292 case ISD::SETONE: return getConstant(R==APFloat::cmpGreaterThan || 1293 R==APFloat::cmpLessThan, VT); 1294 case ISD::SETLT: if (R==APFloat::cmpUnordered) 1295 return getNode(ISD::UNDEF, VT); 1296 // fall through 1297 case ISD::SETOLT: return getConstant(R==APFloat::cmpLessThan, VT); 1298 case ISD::SETGT: if (R==APFloat::cmpUnordered) 1299 return getNode(ISD::UNDEF, VT); 1300 // fall through 1301 case ISD::SETOGT: return getConstant(R==APFloat::cmpGreaterThan, VT); 1302 case ISD::SETLE: if (R==APFloat::cmpUnordered) 1303 return getNode(ISD::UNDEF, VT); 1304 // fall through 1305 case ISD::SETOLE: return getConstant(R==APFloat::cmpLessThan || 1306 R==APFloat::cmpEqual, VT); 1307 case ISD::SETGE: if (R==APFloat::cmpUnordered) 1308 return getNode(ISD::UNDEF, VT); 1309 // fall through 1310 case ISD::SETOGE: return getConstant(R==APFloat::cmpGreaterThan || 1311 R==APFloat::cmpEqual, VT); 1312 case ISD::SETO: return getConstant(R!=APFloat::cmpUnordered, VT); 1313 case ISD::SETUO: return getConstant(R==APFloat::cmpUnordered, VT); 1314 case ISD::SETUEQ: return getConstant(R==APFloat::cmpUnordered || 1315 R==APFloat::cmpEqual, VT); 1316 case ISD::SETUNE: return getConstant(R!=APFloat::cmpEqual, VT); 1317 case ISD::SETULT: return getConstant(R==APFloat::cmpUnordered || 1318 R==APFloat::cmpLessThan, VT); 1319 case ISD::SETUGT: return getConstant(R==APFloat::cmpGreaterThan || 1320 R==APFloat::cmpUnordered, VT); 1321 case ISD::SETULE: return getConstant(R!=APFloat::cmpGreaterThan, VT); 1322 case ISD::SETUGE: return getConstant(R!=APFloat::cmpLessThan, VT); 1323 } 1324 } else { 1325 // Ensure that the constant occurs on the RHS. 1326 return getSetCC(VT, N2, N1, ISD::getSetCCSwappedOperands(Cond)); 1327 } 1328 } 1329 1330 // Could not fold it. 1331 return SDValue(); 1332} 1333 1334/// SignBitIsZero - Return true if the sign bit of Op is known to be zero. We 1335/// use this predicate to simplify operations downstream. 1336bool SelectionDAG::SignBitIsZero(SDValue Op, unsigned Depth) const { 1337 unsigned BitWidth = Op.getValueSizeInBits(); 1338 return MaskedValueIsZero(Op, APInt::getSignBit(BitWidth), Depth); 1339} 1340 1341/// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero. We use 1342/// this predicate to simplify operations downstream. Mask is known to be zero 1343/// for bits that V cannot have. 1344bool SelectionDAG::MaskedValueIsZero(SDValue Op, const APInt &Mask, 1345 unsigned Depth) const { 1346 APInt KnownZero, KnownOne; 1347 ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth); 1348 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1349 return (KnownZero & Mask) == Mask; 1350} 1351 1352/// ComputeMaskedBits - Determine which of the bits specified in Mask are 1353/// known to be either zero or one and return them in the KnownZero/KnownOne 1354/// bitsets. This code only analyzes bits in Mask, in order to short-circuit 1355/// processing. 1356void SelectionDAG::ComputeMaskedBits(SDValue Op, const APInt &Mask, 1357 APInt &KnownZero, APInt &KnownOne, 1358 unsigned Depth) const { 1359 unsigned BitWidth = Mask.getBitWidth(); 1360 assert(BitWidth == Op.getValueType().getSizeInBits() && 1361 "Mask size mismatches value type size!"); 1362 1363 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything. 1364 if (Depth == 6 || Mask == 0) 1365 return; // Limit search depth. 1366 1367 APInt KnownZero2, KnownOne2; 1368 1369 switch (Op.getOpcode()) { 1370 case ISD::Constant: 1371 // We know all of the bits for a constant! 1372 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & Mask; 1373 KnownZero = ~KnownOne & Mask; 1374 return; 1375 case ISD::AND: 1376 // If either the LHS or the RHS are Zero, the result is zero. 1377 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1378 ComputeMaskedBits(Op.getOperand(0), Mask & ~KnownZero, 1379 KnownZero2, KnownOne2, Depth+1); 1380 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1381 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1382 1383 // Output known-1 bits are only known if set in both the LHS & RHS. 1384 KnownOne &= KnownOne2; 1385 // Output known-0 are known to be clear if zero in either the LHS | RHS. 1386 KnownZero |= KnownZero2; 1387 return; 1388 case ISD::OR: 1389 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1390 ComputeMaskedBits(Op.getOperand(0), Mask & ~KnownOne, 1391 KnownZero2, KnownOne2, Depth+1); 1392 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1393 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1394 1395 // Output known-0 bits are only known if clear in both the LHS & RHS. 1396 KnownZero &= KnownZero2; 1397 // Output known-1 are known to be set if set in either the LHS | RHS. 1398 KnownOne |= KnownOne2; 1399 return; 1400 case ISD::XOR: { 1401 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1402 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1); 1403 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1404 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1405 1406 // Output known-0 bits are known if clear or set in both the LHS & RHS. 1407 APInt KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 1408 // Output known-1 are known to be set if set in only one of the LHS, RHS. 1409 KnownOne = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 1410 KnownZero = KnownZeroOut; 1411 return; 1412 } 1413 case ISD::MUL: { 1414 APInt Mask2 = APInt::getAllOnesValue(BitWidth); 1415 ComputeMaskedBits(Op.getOperand(1), Mask2, KnownZero, KnownOne, Depth+1); 1416 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero2, KnownOne2, Depth+1); 1417 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1418 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1419 1420 // If low bits are zero in either operand, output low known-0 bits. 1421 // Also compute a conserative estimate for high known-0 bits. 1422 // More trickiness is possible, but this is sufficient for the 1423 // interesting case of alignment computation. 1424 KnownOne.clear(); 1425 unsigned TrailZ = KnownZero.countTrailingOnes() + 1426 KnownZero2.countTrailingOnes(); 1427 unsigned LeadZ = std::max(KnownZero.countLeadingOnes() + 1428 KnownZero2.countLeadingOnes(), 1429 BitWidth) - BitWidth; 1430 1431 TrailZ = std::min(TrailZ, BitWidth); 1432 LeadZ = std::min(LeadZ, BitWidth); 1433 KnownZero = APInt::getLowBitsSet(BitWidth, TrailZ) | 1434 APInt::getHighBitsSet(BitWidth, LeadZ); 1435 KnownZero &= Mask; 1436 return; 1437 } 1438 case ISD::UDIV: { 1439 // For the purposes of computing leading zeros we can conservatively 1440 // treat a udiv as a logical right shift by the power of 2 known to 1441 // be less than the denominator. 1442 APInt AllOnes = APInt::getAllOnesValue(BitWidth); 1443 ComputeMaskedBits(Op.getOperand(0), 1444 AllOnes, KnownZero2, KnownOne2, Depth+1); 1445 unsigned LeadZ = KnownZero2.countLeadingOnes(); 1446 1447 KnownOne2.clear(); 1448 KnownZero2.clear(); 1449 ComputeMaskedBits(Op.getOperand(1), 1450 AllOnes, KnownZero2, KnownOne2, Depth+1); 1451 unsigned RHSUnknownLeadingOnes = KnownOne2.countLeadingZeros(); 1452 if (RHSUnknownLeadingOnes != BitWidth) 1453 LeadZ = std::min(BitWidth, 1454 LeadZ + BitWidth - RHSUnknownLeadingOnes - 1); 1455 1456 KnownZero = APInt::getHighBitsSet(BitWidth, LeadZ) & Mask; 1457 return; 1458 } 1459 case ISD::SELECT: 1460 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero, KnownOne, Depth+1); 1461 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero2, KnownOne2, Depth+1); 1462 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1463 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1464 1465 // Only known if known in both the LHS and RHS. 1466 KnownOne &= KnownOne2; 1467 KnownZero &= KnownZero2; 1468 return; 1469 case ISD::SELECT_CC: 1470 ComputeMaskedBits(Op.getOperand(3), Mask, KnownZero, KnownOne, Depth+1); 1471 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero2, KnownOne2, Depth+1); 1472 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1473 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1474 1475 // Only known if known in both the LHS and RHS. 1476 KnownOne &= KnownOne2; 1477 KnownZero &= KnownZero2; 1478 return; 1479 case ISD::SETCC: 1480 // If we know the result of a setcc has the top bits zero, use this info. 1481 if (TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult && 1482 BitWidth > 1) 1483 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1); 1484 return; 1485 case ISD::SHL: 1486 // (shl X, C1) & C2 == 0 iff (X & C2 >>u C1) == 0 1487 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1488 unsigned ShAmt = SA->getZExtValue(); 1489 1490 // If the shift count is an invalid immediate, don't do anything. 1491 if (ShAmt >= BitWidth) 1492 return; 1493 1494 ComputeMaskedBits(Op.getOperand(0), Mask.lshr(ShAmt), 1495 KnownZero, KnownOne, Depth+1); 1496 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1497 KnownZero <<= ShAmt; 1498 KnownOne <<= ShAmt; 1499 // low bits known zero. 1500 KnownZero |= APInt::getLowBitsSet(BitWidth, ShAmt); 1501 } 1502 return; 1503 case ISD::SRL: 1504 // (ushr X, C1) & C2 == 0 iff (-1 >> C1) & C2 == 0 1505 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1506 unsigned ShAmt = SA->getZExtValue(); 1507 1508 // If the shift count is an invalid immediate, don't do anything. 1509 if (ShAmt >= BitWidth) 1510 return; 1511 1512 ComputeMaskedBits(Op.getOperand(0), (Mask << ShAmt), 1513 KnownZero, KnownOne, Depth+1); 1514 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1515 KnownZero = KnownZero.lshr(ShAmt); 1516 KnownOne = KnownOne.lshr(ShAmt); 1517 1518 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt) & Mask; 1519 KnownZero |= HighBits; // High bits known zero. 1520 } 1521 return; 1522 case ISD::SRA: 1523 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1524 unsigned ShAmt = SA->getZExtValue(); 1525 1526 // If the shift count is an invalid immediate, don't do anything. 1527 if (ShAmt >= BitWidth) 1528 return; 1529 1530 APInt InDemandedMask = (Mask << ShAmt); 1531 // If any of the demanded bits are produced by the sign extension, we also 1532 // demand the input sign bit. 1533 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt) & Mask; 1534 if (HighBits.getBoolValue()) 1535 InDemandedMask |= APInt::getSignBit(BitWidth); 1536 1537 ComputeMaskedBits(Op.getOperand(0), InDemandedMask, KnownZero, KnownOne, 1538 Depth+1); 1539 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1540 KnownZero = KnownZero.lshr(ShAmt); 1541 KnownOne = KnownOne.lshr(ShAmt); 1542 1543 // Handle the sign bits. 1544 APInt SignBit = APInt::getSignBit(BitWidth); 1545 SignBit = SignBit.lshr(ShAmt); // Adjust to where it is now in the mask. 1546 1547 if (KnownZero.intersects(SignBit)) { 1548 KnownZero |= HighBits; // New bits are known zero. 1549 } else if (KnownOne.intersects(SignBit)) { 1550 KnownOne |= HighBits; // New bits are known one. 1551 } 1552 } 1553 return; 1554 case ISD::SIGN_EXTEND_INREG: { 1555 MVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1556 unsigned EBits = EVT.getSizeInBits(); 1557 1558 // Sign extension. Compute the demanded bits in the result that are not 1559 // present in the input. 1560 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - EBits) & Mask; 1561 1562 APInt InSignBit = APInt::getSignBit(EBits); 1563 APInt InputDemandedBits = Mask & APInt::getLowBitsSet(BitWidth, EBits); 1564 1565 // If the sign extended bits are demanded, we know that the sign 1566 // bit is demanded. 1567 InSignBit.zext(BitWidth); 1568 if (NewBits.getBoolValue()) 1569 InputDemandedBits |= InSignBit; 1570 1571 ComputeMaskedBits(Op.getOperand(0), InputDemandedBits, 1572 KnownZero, KnownOne, Depth+1); 1573 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1574 1575 // If the sign bit of the input is known set or clear, then we know the 1576 // top bits of the result. 1577 if (KnownZero.intersects(InSignBit)) { // Input sign bit known clear 1578 KnownZero |= NewBits; 1579 KnownOne &= ~NewBits; 1580 } else if (KnownOne.intersects(InSignBit)) { // Input sign bit known set 1581 KnownOne |= NewBits; 1582 KnownZero &= ~NewBits; 1583 } else { // Input sign bit unknown 1584 KnownZero &= ~NewBits; 1585 KnownOne &= ~NewBits; 1586 } 1587 return; 1588 } 1589 case ISD::CTTZ: 1590 case ISD::CTLZ: 1591 case ISD::CTPOP: { 1592 unsigned LowBits = Log2_32(BitWidth)+1; 1593 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - LowBits); 1594 KnownOne.clear(); 1595 return; 1596 } 1597 case ISD::LOAD: { 1598 if (ISD::isZEXTLoad(Op.getNode())) { 1599 LoadSDNode *LD = cast<LoadSDNode>(Op); 1600 MVT VT = LD->getMemoryVT(); 1601 unsigned MemBits = VT.getSizeInBits(); 1602 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits) & Mask; 1603 } 1604 return; 1605 } 1606 case ISD::ZERO_EXTEND: { 1607 MVT InVT = Op.getOperand(0).getValueType(); 1608 unsigned InBits = InVT.getSizeInBits(); 1609 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - InBits) & Mask; 1610 APInt InMask = Mask; 1611 InMask.trunc(InBits); 1612 KnownZero.trunc(InBits); 1613 KnownOne.trunc(InBits); 1614 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1615 KnownZero.zext(BitWidth); 1616 KnownOne.zext(BitWidth); 1617 KnownZero |= NewBits; 1618 return; 1619 } 1620 case ISD::SIGN_EXTEND: { 1621 MVT InVT = Op.getOperand(0).getValueType(); 1622 unsigned InBits = InVT.getSizeInBits(); 1623 APInt InSignBit = APInt::getSignBit(InBits); 1624 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - InBits) & Mask; 1625 APInt InMask = Mask; 1626 InMask.trunc(InBits); 1627 1628 // If any of the sign extended bits are demanded, we know that the sign 1629 // bit is demanded. Temporarily set this bit in the mask for our callee. 1630 if (NewBits.getBoolValue()) 1631 InMask |= InSignBit; 1632 1633 KnownZero.trunc(InBits); 1634 KnownOne.trunc(InBits); 1635 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1636 1637 // Note if the sign bit is known to be zero or one. 1638 bool SignBitKnownZero = KnownZero.isNegative(); 1639 bool SignBitKnownOne = KnownOne.isNegative(); 1640 assert(!(SignBitKnownZero && SignBitKnownOne) && 1641 "Sign bit can't be known to be both zero and one!"); 1642 1643 // If the sign bit wasn't actually demanded by our caller, we don't 1644 // want it set in the KnownZero and KnownOne result values. Reset the 1645 // mask and reapply it to the result values. 1646 InMask = Mask; 1647 InMask.trunc(InBits); 1648 KnownZero &= InMask; 1649 KnownOne &= InMask; 1650 1651 KnownZero.zext(BitWidth); 1652 KnownOne.zext(BitWidth); 1653 1654 // If the sign bit is known zero or one, the top bits match. 1655 if (SignBitKnownZero) 1656 KnownZero |= NewBits; 1657 else if (SignBitKnownOne) 1658 KnownOne |= NewBits; 1659 return; 1660 } 1661 case ISD::ANY_EXTEND: { 1662 MVT InVT = Op.getOperand(0).getValueType(); 1663 unsigned InBits = InVT.getSizeInBits(); 1664 APInt InMask = Mask; 1665 InMask.trunc(InBits); 1666 KnownZero.trunc(InBits); 1667 KnownOne.trunc(InBits); 1668 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1669 KnownZero.zext(BitWidth); 1670 KnownOne.zext(BitWidth); 1671 return; 1672 } 1673 case ISD::TRUNCATE: { 1674 MVT InVT = Op.getOperand(0).getValueType(); 1675 unsigned InBits = InVT.getSizeInBits(); 1676 APInt InMask = Mask; 1677 InMask.zext(InBits); 1678 KnownZero.zext(InBits); 1679 KnownOne.zext(InBits); 1680 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1681 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1682 KnownZero.trunc(BitWidth); 1683 KnownOne.trunc(BitWidth); 1684 break; 1685 } 1686 case ISD::AssertZext: { 1687 MVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1688 APInt InMask = APInt::getLowBitsSet(BitWidth, VT.getSizeInBits()); 1689 ComputeMaskedBits(Op.getOperand(0), Mask & InMask, KnownZero, 1690 KnownOne, Depth+1); 1691 KnownZero |= (~InMask) & Mask; 1692 return; 1693 } 1694 case ISD::FGETSIGN: 1695 // All bits are zero except the low bit. 1696 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - 1); 1697 return; 1698 1699 case ISD::SUB: { 1700 if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) { 1701 // We know that the top bits of C-X are clear if X contains less bits 1702 // than C (i.e. no wrap-around can happen). For example, 20-X is 1703 // positive if we can prove that X is >= 0 and < 16. 1704 if (CLHS->getAPIntValue().isNonNegative()) { 1705 unsigned NLZ = (CLHS->getAPIntValue()+1).countLeadingZeros(); 1706 // NLZ can't be BitWidth with no sign bit 1707 APInt MaskV = APInt::getHighBitsSet(BitWidth, NLZ+1); 1708 ComputeMaskedBits(Op.getOperand(1), MaskV, KnownZero2, KnownOne2, 1709 Depth+1); 1710 1711 // If all of the MaskV bits are known to be zero, then we know the 1712 // output top bits are zero, because we now know that the output is 1713 // from [0-C]. 1714 if ((KnownZero2 & MaskV) == MaskV) { 1715 unsigned NLZ2 = CLHS->getAPIntValue().countLeadingZeros(); 1716 // Top bits known zero. 1717 KnownZero = APInt::getHighBitsSet(BitWidth, NLZ2) & Mask; 1718 } 1719 } 1720 } 1721 } 1722 // fall through 1723 case ISD::ADD: { 1724 // Output known-0 bits are known if clear or set in both the low clear bits 1725 // common to both LHS & RHS. For example, 8+(X<<3) is known to have the 1726 // low 3 bits clear. 1727 APInt Mask2 = APInt::getLowBitsSet(BitWidth, Mask.countTrailingOnes()); 1728 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero2, KnownOne2, Depth+1); 1729 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1730 unsigned KnownZeroOut = KnownZero2.countTrailingOnes(); 1731 1732 ComputeMaskedBits(Op.getOperand(1), Mask2, KnownZero2, KnownOne2, Depth+1); 1733 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1734 KnownZeroOut = std::min(KnownZeroOut, 1735 KnownZero2.countTrailingOnes()); 1736 1737 KnownZero |= APInt::getLowBitsSet(BitWidth, KnownZeroOut); 1738 return; 1739 } 1740 case ISD::SREM: 1741 if (ConstantSDNode *Rem = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1742 const APInt &RA = Rem->getAPIntValue(); 1743 if (RA.isPowerOf2() || (-RA).isPowerOf2()) { 1744 APInt LowBits = RA.isStrictlyPositive() ? (RA - 1) : ~RA; 1745 APInt Mask2 = LowBits | APInt::getSignBit(BitWidth); 1746 ComputeMaskedBits(Op.getOperand(0), Mask2,KnownZero2,KnownOne2,Depth+1); 1747 1748 // If the sign bit of the first operand is zero, the sign bit of 1749 // the result is zero. If the first operand has no one bits below 1750 // the second operand's single 1 bit, its sign will be zero. 1751 if (KnownZero2[BitWidth-1] || ((KnownZero2 & LowBits) == LowBits)) 1752 KnownZero2 |= ~LowBits; 1753 1754 KnownZero |= KnownZero2 & Mask; 1755 1756 assert((KnownZero & KnownOne) == 0&&"Bits known to be one AND zero?"); 1757 } 1758 } 1759 return; 1760 case ISD::UREM: { 1761 if (ConstantSDNode *Rem = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1762 const APInt &RA = Rem->getAPIntValue(); 1763 if (RA.isPowerOf2()) { 1764 APInt LowBits = (RA - 1); 1765 APInt Mask2 = LowBits & Mask; 1766 KnownZero |= ~LowBits & Mask; 1767 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero, KnownOne,Depth+1); 1768 assert((KnownZero & KnownOne) == 0&&"Bits known to be one AND zero?"); 1769 break; 1770 } 1771 } 1772 1773 // Since the result is less than or equal to either operand, any leading 1774 // zero bits in either operand must also exist in the result. 1775 APInt AllOnes = APInt::getAllOnesValue(BitWidth); 1776 ComputeMaskedBits(Op.getOperand(0), AllOnes, KnownZero, KnownOne, 1777 Depth+1); 1778 ComputeMaskedBits(Op.getOperand(1), AllOnes, KnownZero2, KnownOne2, 1779 Depth+1); 1780 1781 uint32_t Leaders = std::max(KnownZero.countLeadingOnes(), 1782 KnownZero2.countLeadingOnes()); 1783 KnownOne.clear(); 1784 KnownZero = APInt::getHighBitsSet(BitWidth, Leaders) & Mask; 1785 return; 1786 } 1787 default: 1788 // Allow the target to implement this method for its nodes. 1789 if (Op.getOpcode() >= ISD::BUILTIN_OP_END) { 1790 case ISD::INTRINSIC_WO_CHAIN: 1791 case ISD::INTRINSIC_W_CHAIN: 1792 case ISD::INTRINSIC_VOID: 1793 TLI.computeMaskedBitsForTargetNode(Op, Mask, KnownZero, KnownOne, *this); 1794 } 1795 return; 1796 } 1797} 1798 1799/// ComputeNumSignBits - Return the number of times the sign bit of the 1800/// register is replicated into the other bits. We know that at least 1 bit 1801/// is always equal to the sign bit (itself), but other cases can give us 1802/// information. For example, immediately after an "SRA X, 2", we know that 1803/// the top 3 bits are all equal to each other, so we return 3. 1804unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, unsigned Depth) const{ 1805 MVT VT = Op.getValueType(); 1806 assert(VT.isInteger() && "Invalid VT!"); 1807 unsigned VTBits = VT.getSizeInBits(); 1808 unsigned Tmp, Tmp2; 1809 unsigned FirstAnswer = 1; 1810 1811 if (Depth == 6) 1812 return 1; // Limit search depth. 1813 1814 switch (Op.getOpcode()) { 1815 default: break; 1816 case ISD::AssertSext: 1817 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); 1818 return VTBits-Tmp+1; 1819 case ISD::AssertZext: 1820 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); 1821 return VTBits-Tmp; 1822 1823 case ISD::Constant: { 1824 const APInt &Val = cast<ConstantSDNode>(Op)->getAPIntValue(); 1825 // If negative, return # leading ones. 1826 if (Val.isNegative()) 1827 return Val.countLeadingOnes(); 1828 1829 // Return # leading zeros. 1830 return Val.countLeadingZeros(); 1831 } 1832 1833 case ISD::SIGN_EXTEND: 1834 Tmp = VTBits-Op.getOperand(0).getValueType().getSizeInBits(); 1835 return ComputeNumSignBits(Op.getOperand(0), Depth+1) + Tmp; 1836 1837 case ISD::SIGN_EXTEND_INREG: 1838 // Max of the input and what this extends. 1839 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); 1840 Tmp = VTBits-Tmp+1; 1841 1842 Tmp2 = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1843 return std::max(Tmp, Tmp2); 1844 1845 case ISD::SRA: 1846 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1847 // SRA X, C -> adds C sign bits. 1848 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1849 Tmp += C->getZExtValue(); 1850 if (Tmp > VTBits) Tmp = VTBits; 1851 } 1852 return Tmp; 1853 case ISD::SHL: 1854 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1855 // shl destroys sign bits. 1856 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1857 if (C->getZExtValue() >= VTBits || // Bad shift. 1858 C->getZExtValue() >= Tmp) break; // Shifted all sign bits out. 1859 return Tmp - C->getZExtValue(); 1860 } 1861 break; 1862 case ISD::AND: 1863 case ISD::OR: 1864 case ISD::XOR: // NOT is handled here. 1865 // Logical binary ops preserve the number of sign bits at the worst. 1866 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1867 if (Tmp != 1) { 1868 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 1869 FirstAnswer = std::min(Tmp, Tmp2); 1870 // We computed what we know about the sign bits as our first 1871 // answer. Now proceed to the generic code that uses 1872 // ComputeMaskedBits, and pick whichever answer is better. 1873 } 1874 break; 1875 1876 case ISD::SELECT: 1877 Tmp = ComputeNumSignBits(Op.getOperand(1), Depth+1); 1878 if (Tmp == 1) return 1; // Early out. 1879 Tmp2 = ComputeNumSignBits(Op.getOperand(2), Depth+1); 1880 return std::min(Tmp, Tmp2); 1881 1882 case ISD::SETCC: 1883 // If setcc returns 0/-1, all bits are sign bits. 1884 if (TLI.getSetCCResultContents() == 1885 TargetLowering::ZeroOrNegativeOneSetCCResult) 1886 return VTBits; 1887 break; 1888 case ISD::ROTL: 1889 case ISD::ROTR: 1890 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1891 unsigned RotAmt = C->getZExtValue() & (VTBits-1); 1892 1893 // Handle rotate right by N like a rotate left by 32-N. 1894 if (Op.getOpcode() == ISD::ROTR) 1895 RotAmt = (VTBits-RotAmt) & (VTBits-1); 1896 1897 // If we aren't rotating out all of the known-in sign bits, return the 1898 // number that are left. This handles rotl(sext(x), 1) for example. 1899 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1900 if (Tmp > RotAmt+1) return Tmp-RotAmt; 1901 } 1902 break; 1903 case ISD::ADD: 1904 // Add can have at most one carry bit. Thus we know that the output 1905 // is, at worst, one more bit than the inputs. 1906 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1907 if (Tmp == 1) return 1; // Early out. 1908 1909 // Special case decrementing a value (ADD X, -1): 1910 if (ConstantSDNode *CRHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) 1911 if (CRHS->isAllOnesValue()) { 1912 APInt KnownZero, KnownOne; 1913 APInt Mask = APInt::getAllOnesValue(VTBits); 1914 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1); 1915 1916 // If the input is known to be 0 or 1, the output is 0/-1, which is all 1917 // sign bits set. 1918 if ((KnownZero | APInt(VTBits, 1)) == Mask) 1919 return VTBits; 1920 1921 // If we are subtracting one from a positive number, there is no carry 1922 // out of the result. 1923 if (KnownZero.isNegative()) 1924 return Tmp; 1925 } 1926 1927 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 1928 if (Tmp2 == 1) return 1; 1929 return std::min(Tmp, Tmp2)-1; 1930 break; 1931 1932 case ISD::SUB: 1933 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 1934 if (Tmp2 == 1) return 1; 1935 1936 // Handle NEG. 1937 if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) 1938 if (CLHS->isNullValue()) { 1939 APInt KnownZero, KnownOne; 1940 APInt Mask = APInt::getAllOnesValue(VTBits); 1941 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1942 // If the input is known to be 0 or 1, the output is 0/-1, which is all 1943 // sign bits set. 1944 if ((KnownZero | APInt(VTBits, 1)) == Mask) 1945 return VTBits; 1946 1947 // If the input is known to be positive (the sign bit is known clear), 1948 // the output of the NEG has the same number of sign bits as the input. 1949 if (KnownZero.isNegative()) 1950 return Tmp2; 1951 1952 // Otherwise, we treat this like a SUB. 1953 } 1954 1955 // Sub can have at most one carry bit. Thus we know that the output 1956 // is, at worst, one more bit than the inputs. 1957 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1958 if (Tmp == 1) return 1; // Early out. 1959 return std::min(Tmp, Tmp2)-1; 1960 break; 1961 case ISD::TRUNCATE: 1962 // FIXME: it's tricky to do anything useful for this, but it is an important 1963 // case for targets like X86. 1964 break; 1965 } 1966 1967 // Handle LOADX separately here. EXTLOAD case will fallthrough. 1968 if (Op.getOpcode() == ISD::LOAD) { 1969 LoadSDNode *LD = cast<LoadSDNode>(Op); 1970 unsigned ExtType = LD->getExtensionType(); 1971 switch (ExtType) { 1972 default: break; 1973 case ISD::SEXTLOAD: // '17' bits known 1974 Tmp = LD->getMemoryVT().getSizeInBits(); 1975 return VTBits-Tmp+1; 1976 case ISD::ZEXTLOAD: // '16' bits known 1977 Tmp = LD->getMemoryVT().getSizeInBits(); 1978 return VTBits-Tmp; 1979 } 1980 } 1981 1982 // Allow the target to implement this method for its nodes. 1983 if (Op.getOpcode() >= ISD::BUILTIN_OP_END || 1984 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1985 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1986 Op.getOpcode() == ISD::INTRINSIC_VOID) { 1987 unsigned NumBits = TLI.ComputeNumSignBitsForTargetNode(Op, Depth); 1988 if (NumBits > 1) FirstAnswer = std::max(FirstAnswer, NumBits); 1989 } 1990 1991 // Finally, if we can prove that the top bits of the result are 0's or 1's, 1992 // use this information. 1993 APInt KnownZero, KnownOne; 1994 APInt Mask = APInt::getAllOnesValue(VTBits); 1995 ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth); 1996 1997 if (KnownZero.isNegative()) { // sign bit is 0 1998 Mask = KnownZero; 1999 } else if (KnownOne.isNegative()) { // sign bit is 1; 2000 Mask = KnownOne; 2001 } else { 2002 // Nothing known. 2003 return FirstAnswer; 2004 } 2005 2006 // Okay, we know that the sign bit in Mask is set. Use CLZ to determine 2007 // the number of identical bits in the top of the input value. 2008 Mask = ~Mask; 2009 Mask <<= Mask.getBitWidth()-VTBits; 2010 // Return # leading zeros. We use 'min' here in case Val was zero before 2011 // shifting. We don't want to return '64' as for an i32 "0". 2012 return std::max(FirstAnswer, std::min(VTBits, Mask.countLeadingZeros())); 2013} 2014 2015 2016bool SelectionDAG::isVerifiedDebugInfoDesc(SDValue Op) const { 2017 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op); 2018 if (!GA) return false; 2019 if (GA->getOffset() != 0) return false; 2020 GlobalVariable *GV = dyn_cast<GlobalVariable>(GA->getGlobal()); 2021 if (!GV) return false; 2022 MachineModuleInfo *MMI = getMachineModuleInfo(); 2023 return MMI && MMI->hasDebugInfo() && MMI->isVerified(GV); 2024} 2025 2026 2027/// getShuffleScalarElt - Returns the scalar element that will make up the ith 2028/// element of the result of the vector shuffle. 2029SDValue SelectionDAG::getShuffleScalarElt(const SDNode *N, unsigned i) { 2030 MVT VT = N->getValueType(0); 2031 SDValue PermMask = N->getOperand(2); 2032 SDValue Idx = PermMask.getOperand(i); 2033 if (Idx.getOpcode() == ISD::UNDEF) 2034 return getNode(ISD::UNDEF, VT.getVectorElementType()); 2035 unsigned Index = cast<ConstantSDNode>(Idx)->getZExtValue(); 2036 unsigned NumElems = PermMask.getNumOperands(); 2037 SDValue V = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1); 2038 Index %= NumElems; 2039 2040 if (V.getOpcode() == ISD::BIT_CONVERT) { 2041 V = V.getOperand(0); 2042 if (V.getValueType().getVectorNumElements() != NumElems) 2043 return SDValue(); 2044 } 2045 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) 2046 return (Index == 0) ? V.getOperand(0) 2047 : getNode(ISD::UNDEF, VT.getVectorElementType()); 2048 if (V.getOpcode() == ISD::BUILD_VECTOR) 2049 return V.getOperand(Index); 2050 if (V.getOpcode() == ISD::VECTOR_SHUFFLE) 2051 return getShuffleScalarElt(V.getNode(), Index); 2052 return SDValue(); 2053} 2054 2055 2056/// getNode - Gets or creates the specified node. 2057/// 2058SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT) { 2059 FoldingSetNodeID ID; 2060 AddNodeIDNode(ID, Opcode, getVTList(VT), 0, 0); 2061 void *IP = 0; 2062 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2063 return SDValue(E, 0); 2064 SDNode *N = NodeAllocator.Allocate<SDNode>(); 2065 new (N) SDNode(Opcode, SDNode::getSDVTList(VT)); 2066 CSEMap.InsertNode(N, IP); 2067 2068 AllNodes.push_back(N); 2069#ifndef NDEBUG 2070 VerifyNode(N); 2071#endif 2072 return SDValue(N, 0); 2073} 2074 2075SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, SDValue Operand) { 2076 // Constant fold unary operations with an integer constant operand. 2077 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Operand.getNode())) { 2078 const APInt &Val = C->getAPIntValue(); 2079 unsigned BitWidth = VT.getSizeInBits(); 2080 switch (Opcode) { 2081 default: break; 2082 case ISD::SIGN_EXTEND: 2083 return getConstant(APInt(Val).sextOrTrunc(BitWidth), VT); 2084 case ISD::ANY_EXTEND: 2085 case ISD::ZERO_EXTEND: 2086 case ISD::TRUNCATE: 2087 return getConstant(APInt(Val).zextOrTrunc(BitWidth), VT); 2088 case ISD::UINT_TO_FP: 2089 case ISD::SINT_TO_FP: { 2090 const uint64_t zero[] = {0, 0}; 2091 // No compile time operations on this type. 2092 if (VT==MVT::ppcf128) 2093 break; 2094 APFloat apf = APFloat(APInt(BitWidth, 2, zero)); 2095 (void)apf.convertFromAPInt(Val, 2096 Opcode==ISD::SINT_TO_FP, 2097 APFloat::rmNearestTiesToEven); 2098 return getConstantFP(apf, VT); 2099 } 2100 case ISD::BIT_CONVERT: 2101 if (VT == MVT::f32 && C->getValueType(0) == MVT::i32) 2102 return getConstantFP(Val.bitsToFloat(), VT); 2103 else if (VT == MVT::f64 && C->getValueType(0) == MVT::i64) 2104 return getConstantFP(Val.bitsToDouble(), VT); 2105 break; 2106 case ISD::BSWAP: 2107 return getConstant(Val.byteSwap(), VT); 2108 case ISD::CTPOP: 2109 return getConstant(Val.countPopulation(), VT); 2110 case ISD::CTLZ: 2111 return getConstant(Val.countLeadingZeros(), VT); 2112 case ISD::CTTZ: 2113 return getConstant(Val.countTrailingZeros(), VT); 2114 } 2115 } 2116 2117 // Constant fold unary operations with a floating point constant operand. 2118 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Operand.getNode())) { 2119 APFloat V = C->getValueAPF(); // make copy 2120 if (VT != MVT::ppcf128 && Operand.getValueType() != MVT::ppcf128) { 2121 switch (Opcode) { 2122 case ISD::FNEG: 2123 V.changeSign(); 2124 return getConstantFP(V, VT); 2125 case ISD::FABS: 2126 V.clearSign(); 2127 return getConstantFP(V, VT); 2128 case ISD::FP_ROUND: 2129 case ISD::FP_EXTEND: { 2130 bool ignored; 2131 // This can return overflow, underflow, or inexact; we don't care. 2132 // FIXME need to be more flexible about rounding mode. 2133 (void)V.convert(*MVTToAPFloatSemantics(VT), 2134 APFloat::rmNearestTiesToEven, &ignored); 2135 return getConstantFP(V, VT); 2136 } 2137 case ISD::FP_TO_SINT: 2138 case ISD::FP_TO_UINT: { 2139 integerPart x; 2140 bool ignored; 2141 assert(integerPartWidth >= 64); 2142 // FIXME need to be more flexible about rounding mode. 2143 APFloat::opStatus s = V.convertToInteger(&x, 64U, 2144 Opcode==ISD::FP_TO_SINT, 2145 APFloat::rmTowardZero, &ignored); 2146 if (s==APFloat::opInvalidOp) // inexact is OK, in fact usual 2147 break; 2148 return getConstant(x, VT); 2149 } 2150 case ISD::BIT_CONVERT: 2151 if (VT == MVT::i32 && C->getValueType(0) == MVT::f32) 2152 return getConstant((uint32_t)V.bitcastToAPInt().getZExtValue(), VT); 2153 else if (VT == MVT::i64 && C->getValueType(0) == MVT::f64) 2154 return getConstant(V.bitcastToAPInt().getZExtValue(), VT); 2155 break; 2156 } 2157 } 2158 } 2159 2160 unsigned OpOpcode = Operand.getNode()->getOpcode(); 2161 switch (Opcode) { 2162 case ISD::TokenFactor: 2163 case ISD::CONCAT_VECTORS: 2164 return Operand; // Factor or concat of one node? No need. 2165 case ISD::FP_ROUND: assert(0 && "Invalid method to make FP_ROUND node"); 2166 case ISD::FP_EXTEND: 2167 assert(VT.isFloatingPoint() && 2168 Operand.getValueType().isFloatingPoint() && "Invalid FP cast!"); 2169 if (Operand.getValueType() == VT) return Operand; // noop conversion. 2170 if (Operand.getOpcode() == ISD::UNDEF) 2171 return getNode(ISD::UNDEF, VT); 2172 break; 2173 case ISD::SIGN_EXTEND: 2174 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2175 "Invalid SIGN_EXTEND!"); 2176 if (Operand.getValueType() == VT) return Operand; // noop extension 2177 assert(Operand.getValueType().bitsLT(VT) 2178 && "Invalid sext node, dst < src!"); 2179 if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND) 2180 return getNode(OpOpcode, VT, Operand.getNode()->getOperand(0)); 2181 break; 2182 case ISD::ZERO_EXTEND: 2183 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2184 "Invalid ZERO_EXTEND!"); 2185 if (Operand.getValueType() == VT) return Operand; // noop extension 2186 assert(Operand.getValueType().bitsLT(VT) 2187 && "Invalid zext node, dst < src!"); 2188 if (OpOpcode == ISD::ZERO_EXTEND) // (zext (zext x)) -> (zext x) 2189 return getNode(ISD::ZERO_EXTEND, VT, Operand.getNode()->getOperand(0)); 2190 break; 2191 case ISD::ANY_EXTEND: 2192 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2193 "Invalid ANY_EXTEND!"); 2194 if (Operand.getValueType() == VT) return Operand; // noop extension 2195 assert(Operand.getValueType().bitsLT(VT) 2196 && "Invalid anyext node, dst < src!"); 2197 if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND) 2198 // (ext (zext x)) -> (zext x) and (ext (sext x)) -> (sext x) 2199 return getNode(OpOpcode, VT, Operand.getNode()->getOperand(0)); 2200 break; 2201 case ISD::TRUNCATE: 2202 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2203 "Invalid TRUNCATE!"); 2204 if (Operand.getValueType() == VT) return Operand; // noop truncate 2205 assert(Operand.getValueType().bitsGT(VT) 2206 && "Invalid truncate node, src < dst!"); 2207 if (OpOpcode == ISD::TRUNCATE) 2208 return getNode(ISD::TRUNCATE, VT, Operand.getNode()->getOperand(0)); 2209 else if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND || 2210 OpOpcode == ISD::ANY_EXTEND) { 2211 // If the source is smaller than the dest, we still need an extend. 2212 if (Operand.getNode()->getOperand(0).getValueType().bitsLT(VT)) 2213 return getNode(OpOpcode, VT, Operand.getNode()->getOperand(0)); 2214 else if (Operand.getNode()->getOperand(0).getValueType().bitsGT(VT)) 2215 return getNode(ISD::TRUNCATE, VT, Operand.getNode()->getOperand(0)); 2216 else 2217 return Operand.getNode()->getOperand(0); 2218 } 2219 break; 2220 case ISD::BIT_CONVERT: 2221 // Basic sanity checking. 2222 assert(VT.getSizeInBits() == Operand.getValueType().getSizeInBits() 2223 && "Cannot BIT_CONVERT between types of different sizes!"); 2224 if (VT == Operand.getValueType()) return Operand; // noop conversion. 2225 if (OpOpcode == ISD::BIT_CONVERT) // bitconv(bitconv(x)) -> bitconv(x) 2226 return getNode(ISD::BIT_CONVERT, VT, Operand.getOperand(0)); 2227 if (OpOpcode == ISD::UNDEF) 2228 return getNode(ISD::UNDEF, VT); 2229 break; 2230 case ISD::SCALAR_TO_VECTOR: 2231 assert(VT.isVector() && !Operand.getValueType().isVector() && 2232 VT.getVectorElementType() == Operand.getValueType() && 2233 "Illegal SCALAR_TO_VECTOR node!"); 2234 if (OpOpcode == ISD::UNDEF) 2235 return getNode(ISD::UNDEF, VT); 2236 // scalar_to_vector(extract_vector_elt V, 0) -> V, top bits are undefined. 2237 if (OpOpcode == ISD::EXTRACT_VECTOR_ELT && 2238 isa<ConstantSDNode>(Operand.getOperand(1)) && 2239 Operand.getConstantOperandVal(1) == 0 && 2240 Operand.getOperand(0).getValueType() == VT) 2241 return Operand.getOperand(0); 2242 break; 2243 case ISD::FNEG: 2244 if (OpOpcode == ISD::FSUB) // -(X-Y) -> (Y-X) 2245 return getNode(ISD::FSUB, VT, Operand.getNode()->getOperand(1), 2246 Operand.getNode()->getOperand(0)); 2247 if (OpOpcode == ISD::FNEG) // --X -> X 2248 return Operand.getNode()->getOperand(0); 2249 break; 2250 case ISD::FABS: 2251 if (OpOpcode == ISD::FNEG) // abs(-X) -> abs(X) 2252 return getNode(ISD::FABS, VT, Operand.getNode()->getOperand(0)); 2253 break; 2254 } 2255 2256 SDNode *N; 2257 SDVTList VTs = getVTList(VT); 2258 if (VT != MVT::Flag) { // Don't CSE flag producing nodes 2259 FoldingSetNodeID ID; 2260 SDValue Ops[1] = { Operand }; 2261 AddNodeIDNode(ID, Opcode, VTs, Ops, 1); 2262 void *IP = 0; 2263 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2264 return SDValue(E, 0); 2265 N = NodeAllocator.Allocate<UnarySDNode>(); 2266 new (N) UnarySDNode(Opcode, VTs, Operand); 2267 CSEMap.InsertNode(N, IP); 2268 } else { 2269 N = NodeAllocator.Allocate<UnarySDNode>(); 2270 new (N) UnarySDNode(Opcode, VTs, Operand); 2271 } 2272 2273 AllNodes.push_back(N); 2274#ifndef NDEBUG 2275 VerifyNode(N); 2276#endif 2277 return SDValue(N, 0); 2278} 2279 2280SDValue SelectionDAG::FoldConstantArithmetic(unsigned Opcode, 2281 MVT VT, 2282 ConstantSDNode *Cst1, 2283 ConstantSDNode *Cst2) { 2284 const APInt &C1 = Cst1->getAPIntValue(), &C2 = Cst2->getAPIntValue(); 2285 2286 switch (Opcode) { 2287 case ISD::ADD: return getConstant(C1 + C2, VT); 2288 case ISD::SUB: return getConstant(C1 - C2, VT); 2289 case ISD::MUL: return getConstant(C1 * C2, VT); 2290 case ISD::UDIV: 2291 if (C2.getBoolValue()) return getConstant(C1.udiv(C2), VT); 2292 break; 2293 case ISD::UREM: 2294 if (C2.getBoolValue()) return getConstant(C1.urem(C2), VT); 2295 break; 2296 case ISD::SDIV: 2297 if (C2.getBoolValue()) return getConstant(C1.sdiv(C2), VT); 2298 break; 2299 case ISD::SREM: 2300 if (C2.getBoolValue()) return getConstant(C1.srem(C2), VT); 2301 break; 2302 case ISD::AND: return getConstant(C1 & C2, VT); 2303 case ISD::OR: return getConstant(C1 | C2, VT); 2304 case ISD::XOR: return getConstant(C1 ^ C2, VT); 2305 case ISD::SHL: return getConstant(C1 << C2, VT); 2306 case ISD::SRL: return getConstant(C1.lshr(C2), VT); 2307 case ISD::SRA: return getConstant(C1.ashr(C2), VT); 2308 case ISD::ROTL: return getConstant(C1.rotl(C2), VT); 2309 case ISD::ROTR: return getConstant(C1.rotr(C2), VT); 2310 default: break; 2311 } 2312 2313 return SDValue(); 2314} 2315 2316SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, 2317 SDValue N1, SDValue N2) { 2318 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 2319 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 2320 switch (Opcode) { 2321 default: break; 2322 case ISD::TokenFactor: 2323 assert(VT == MVT::Other && N1.getValueType() == MVT::Other && 2324 N2.getValueType() == MVT::Other && "Invalid token factor!"); 2325 // Fold trivial token factors. 2326 if (N1.getOpcode() == ISD::EntryToken) return N2; 2327 if (N2.getOpcode() == ISD::EntryToken) return N1; 2328 if (N1 == N2) return N1; 2329 break; 2330 case ISD::CONCAT_VECTORS: 2331 // A CONCAT_VECTOR with all operands BUILD_VECTOR can be simplified to 2332 // one big BUILD_VECTOR. 2333 if (N1.getOpcode() == ISD::BUILD_VECTOR && 2334 N2.getOpcode() == ISD::BUILD_VECTOR) { 2335 SmallVector<SDValue, 16> Elts(N1.getNode()->op_begin(), N1.getNode()->op_end()); 2336 Elts.insert(Elts.end(), N2.getNode()->op_begin(), N2.getNode()->op_end()); 2337 return getNode(ISD::BUILD_VECTOR, VT, &Elts[0], Elts.size()); 2338 } 2339 break; 2340 case ISD::AND: 2341 assert(VT.isInteger() && N1.getValueType() == N2.getValueType() && 2342 N1.getValueType() == VT && "Binary operator types must match!"); 2343 // (X & 0) -> 0. This commonly occurs when legalizing i64 values, so it's 2344 // worth handling here. 2345 if (N2C && N2C->isNullValue()) 2346 return N2; 2347 if (N2C && N2C->isAllOnesValue()) // X & -1 -> X 2348 return N1; 2349 break; 2350 case ISD::OR: 2351 case ISD::XOR: 2352 case ISD::ADD: 2353 case ISD::SUB: 2354 assert(VT.isInteger() && N1.getValueType() == N2.getValueType() && 2355 N1.getValueType() == VT && "Binary operator types must match!"); 2356 // (X ^|+- 0) -> X. This commonly occurs when legalizing i64 values, so 2357 // it's worth handling here. 2358 if (N2C && N2C->isNullValue()) 2359 return N1; 2360 break; 2361 case ISD::UDIV: 2362 case ISD::UREM: 2363 case ISD::MULHU: 2364 case ISD::MULHS: 2365 assert(VT.isInteger() && "This operator does not apply to FP types!"); 2366 // fall through 2367 case ISD::MUL: 2368 case ISD::SDIV: 2369 case ISD::SREM: 2370 case ISD::FADD: 2371 case ISD::FSUB: 2372 case ISD::FMUL: 2373 case ISD::FDIV: 2374 case ISD::FREM: 2375 assert(N1.getValueType() == N2.getValueType() && 2376 N1.getValueType() == VT && "Binary operator types must match!"); 2377 break; 2378 case ISD::FCOPYSIGN: // N1 and result must match. N1/N2 need not match. 2379 assert(N1.getValueType() == VT && 2380 N1.getValueType().isFloatingPoint() && 2381 N2.getValueType().isFloatingPoint() && 2382 "Invalid FCOPYSIGN!"); 2383 break; 2384 case ISD::SHL: 2385 case ISD::SRA: 2386 case ISD::SRL: 2387 case ISD::ROTL: 2388 case ISD::ROTR: 2389 assert(VT == N1.getValueType() && 2390 "Shift operators return type must be the same as their first arg"); 2391 assert(VT.isInteger() && N2.getValueType().isInteger() && 2392 "Shifts only work on integers"); 2393 assert(N2.getValueType() == TLI.getShiftAmountTy() && 2394 "Wrong type for shift amount"); 2395 2396 // Always fold shifts of i1 values so the code generator doesn't need to 2397 // handle them. Since we know the size of the shift has to be less than the 2398 // size of the value, the shift/rotate count is guaranteed to be zero. 2399 if (VT == MVT::i1) 2400 return N1; 2401 break; 2402 case ISD::FP_ROUND_INREG: { 2403 MVT EVT = cast<VTSDNode>(N2)->getVT(); 2404 assert(VT == N1.getValueType() && "Not an inreg round!"); 2405 assert(VT.isFloatingPoint() && EVT.isFloatingPoint() && 2406 "Cannot FP_ROUND_INREG integer types"); 2407 assert(EVT.bitsLE(VT) && "Not rounding down!"); 2408 if (cast<VTSDNode>(N2)->getVT() == VT) return N1; // Not actually rounding. 2409 break; 2410 } 2411 case ISD::FP_ROUND: 2412 assert(VT.isFloatingPoint() && 2413 N1.getValueType().isFloatingPoint() && 2414 VT.bitsLE(N1.getValueType()) && 2415 isa<ConstantSDNode>(N2) && "Invalid FP_ROUND!"); 2416 if (N1.getValueType() == VT) return N1; // noop conversion. 2417 break; 2418 case ISD::AssertSext: 2419 case ISD::AssertZext: { 2420 MVT EVT = cast<VTSDNode>(N2)->getVT(); 2421 assert(VT == N1.getValueType() && "Not an inreg extend!"); 2422 assert(VT.isInteger() && EVT.isInteger() && 2423 "Cannot *_EXTEND_INREG FP types"); 2424 assert(EVT.bitsLE(VT) && "Not extending!"); 2425 if (VT == EVT) return N1; // noop assertion. 2426 break; 2427 } 2428 case ISD::SIGN_EXTEND_INREG: { 2429 MVT EVT = cast<VTSDNode>(N2)->getVT(); 2430 assert(VT == N1.getValueType() && "Not an inreg extend!"); 2431 assert(VT.isInteger() && EVT.isInteger() && 2432 "Cannot *_EXTEND_INREG FP types"); 2433 assert(EVT.bitsLE(VT) && "Not extending!"); 2434 if (EVT == VT) return N1; // Not actually extending 2435 2436 if (N1C) { 2437 APInt Val = N1C->getAPIntValue(); 2438 unsigned FromBits = cast<VTSDNode>(N2)->getVT().getSizeInBits(); 2439 Val <<= Val.getBitWidth()-FromBits; 2440 Val = Val.ashr(Val.getBitWidth()-FromBits); 2441 return getConstant(Val, VT); 2442 } 2443 break; 2444 } 2445 case ISD::EXTRACT_VECTOR_ELT: 2446 // EXTRACT_VECTOR_ELT of an UNDEF is an UNDEF. 2447 if (N1.getOpcode() == ISD::UNDEF) 2448 return getNode(ISD::UNDEF, VT); 2449 2450 // EXTRACT_VECTOR_ELT of CONCAT_VECTORS is often formed while lowering is 2451 // expanding copies of large vectors from registers. 2452 if (N2C && 2453 N1.getOpcode() == ISD::CONCAT_VECTORS && 2454 N1.getNumOperands() > 0) { 2455 unsigned Factor = 2456 N1.getOperand(0).getValueType().getVectorNumElements(); 2457 return getNode(ISD::EXTRACT_VECTOR_ELT, VT, 2458 N1.getOperand(N2C->getZExtValue() / Factor), 2459 getConstant(N2C->getZExtValue() % Factor, 2460 N2.getValueType())); 2461 } 2462 2463 // EXTRACT_VECTOR_ELT of BUILD_VECTOR is often formed while lowering is 2464 // expanding large vector constants. 2465 if (N2C && N1.getOpcode() == ISD::BUILD_VECTOR) 2466 return N1.getOperand(N2C->getZExtValue()); 2467 2468 // EXTRACT_VECTOR_ELT of INSERT_VECTOR_ELT is often formed when vector 2469 // operations are lowered to scalars. 2470 if (N1.getOpcode() == ISD::INSERT_VECTOR_ELT) { 2471 if (N1.getOperand(2) == N2) 2472 return N1.getOperand(1); 2473 else 2474 return getNode(ISD::EXTRACT_VECTOR_ELT, VT, N1.getOperand(0), N2); 2475 } 2476 break; 2477 case ISD::EXTRACT_ELEMENT: 2478 assert(N2C && (unsigned)N2C->getZExtValue() < 2 && "Bad EXTRACT_ELEMENT!"); 2479 assert(!N1.getValueType().isVector() && !VT.isVector() && 2480 (N1.getValueType().isInteger() == VT.isInteger()) && 2481 "Wrong types for EXTRACT_ELEMENT!"); 2482 2483 // EXTRACT_ELEMENT of BUILD_PAIR is often formed while legalize is expanding 2484 // 64-bit integers into 32-bit parts. Instead of building the extract of 2485 // the BUILD_PAIR, only to have legalize rip it apart, just do it now. 2486 if (N1.getOpcode() == ISD::BUILD_PAIR) 2487 return N1.getOperand(N2C->getZExtValue()); 2488 2489 // EXTRACT_ELEMENT of a constant int is also very common. 2490 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) { 2491 unsigned ElementSize = VT.getSizeInBits(); 2492 unsigned Shift = ElementSize * N2C->getZExtValue(); 2493 APInt ShiftedVal = C->getAPIntValue().lshr(Shift); 2494 return getConstant(ShiftedVal.trunc(ElementSize), VT); 2495 } 2496 break; 2497 case ISD::EXTRACT_SUBVECTOR: 2498 if (N1.getValueType() == VT) // Trivial extraction. 2499 return N1; 2500 break; 2501 } 2502 2503 if (N1C) { 2504 if (N2C) { 2505 SDValue SV = FoldConstantArithmetic(Opcode, VT, N1C, N2C); 2506 if (SV.getNode()) return SV; 2507 } else { // Cannonicalize constant to RHS if commutative 2508 if (isCommutativeBinOp(Opcode)) { 2509 std::swap(N1C, N2C); 2510 std::swap(N1, N2); 2511 } 2512 } 2513 } 2514 2515 // Constant fold FP operations. 2516 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1.getNode()); 2517 ConstantFPSDNode *N2CFP = dyn_cast<ConstantFPSDNode>(N2.getNode()); 2518 if (N1CFP) { 2519 if (!N2CFP && isCommutativeBinOp(Opcode)) { 2520 // Cannonicalize constant to RHS if commutative 2521 std::swap(N1CFP, N2CFP); 2522 std::swap(N1, N2); 2523 } else if (N2CFP && VT != MVT::ppcf128) { 2524 APFloat V1 = N1CFP->getValueAPF(), V2 = N2CFP->getValueAPF(); 2525 APFloat::opStatus s; 2526 switch (Opcode) { 2527 case ISD::FADD: 2528 s = V1.add(V2, APFloat::rmNearestTiesToEven); 2529 if (s != APFloat::opInvalidOp) 2530 return getConstantFP(V1, VT); 2531 break; 2532 case ISD::FSUB: 2533 s = V1.subtract(V2, APFloat::rmNearestTiesToEven); 2534 if (s!=APFloat::opInvalidOp) 2535 return getConstantFP(V1, VT); 2536 break; 2537 case ISD::FMUL: 2538 s = V1.multiply(V2, APFloat::rmNearestTiesToEven); 2539 if (s!=APFloat::opInvalidOp) 2540 return getConstantFP(V1, VT); 2541 break; 2542 case ISD::FDIV: 2543 s = V1.divide(V2, APFloat::rmNearestTiesToEven); 2544 if (s!=APFloat::opInvalidOp && s!=APFloat::opDivByZero) 2545 return getConstantFP(V1, VT); 2546 break; 2547 case ISD::FREM : 2548 s = V1.mod(V2, APFloat::rmNearestTiesToEven); 2549 if (s!=APFloat::opInvalidOp && s!=APFloat::opDivByZero) 2550 return getConstantFP(V1, VT); 2551 break; 2552 case ISD::FCOPYSIGN: 2553 V1.copySign(V2); 2554 return getConstantFP(V1, VT); 2555 default: break; 2556 } 2557 } 2558 } 2559 2560 // Canonicalize an UNDEF to the RHS, even over a constant. 2561 if (N1.getOpcode() == ISD::UNDEF) { 2562 if (isCommutativeBinOp(Opcode)) { 2563 std::swap(N1, N2); 2564 } else { 2565 switch (Opcode) { 2566 case ISD::FP_ROUND_INREG: 2567 case ISD::SIGN_EXTEND_INREG: 2568 case ISD::SUB: 2569 case ISD::FSUB: 2570 case ISD::FDIV: 2571 case ISD::FREM: 2572 case ISD::SRA: 2573 return N1; // fold op(undef, arg2) -> undef 2574 case ISD::UDIV: 2575 case ISD::SDIV: 2576 case ISD::UREM: 2577 case ISD::SREM: 2578 case ISD::SRL: 2579 case ISD::SHL: 2580 if (!VT.isVector()) 2581 return getConstant(0, VT); // fold op(undef, arg2) -> 0 2582 // For vectors, we can't easily build an all zero vector, just return 2583 // the LHS. 2584 return N2; 2585 } 2586 } 2587 } 2588 2589 // Fold a bunch of operators when the RHS is undef. 2590 if (N2.getOpcode() == ISD::UNDEF) { 2591 switch (Opcode) { 2592 case ISD::XOR: 2593 if (N1.getOpcode() == ISD::UNDEF) 2594 // Handle undef ^ undef -> 0 special case. This is a common 2595 // idiom (misuse). 2596 return getConstant(0, VT); 2597 // fallthrough 2598 case ISD::ADD: 2599 case ISD::ADDC: 2600 case ISD::ADDE: 2601 case ISD::SUB: 2602 case ISD::FADD: 2603 case ISD::FSUB: 2604 case ISD::FMUL: 2605 case ISD::FDIV: 2606 case ISD::FREM: 2607 case ISD::UDIV: 2608 case ISD::SDIV: 2609 case ISD::UREM: 2610 case ISD::SREM: 2611 return N2; // fold op(arg1, undef) -> undef 2612 case ISD::MUL: 2613 case ISD::AND: 2614 case ISD::SRL: 2615 case ISD::SHL: 2616 if (!VT.isVector()) 2617 return getConstant(0, VT); // fold op(arg1, undef) -> 0 2618 // For vectors, we can't easily build an all zero vector, just return 2619 // the LHS. 2620 return N1; 2621 case ISD::OR: 2622 if (!VT.isVector()) 2623 return getConstant(VT.getIntegerVTBitMask(), VT); 2624 // For vectors, we can't easily build an all one vector, just return 2625 // the LHS. 2626 return N1; 2627 case ISD::SRA: 2628 return N1; 2629 } 2630 } 2631 2632 // Memoize this node if possible. 2633 SDNode *N; 2634 SDVTList VTs = getVTList(VT); 2635 if (VT != MVT::Flag) { 2636 SDValue Ops[] = { N1, N2 }; 2637 FoldingSetNodeID ID; 2638 AddNodeIDNode(ID, Opcode, VTs, Ops, 2); 2639 void *IP = 0; 2640 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2641 return SDValue(E, 0); 2642 N = NodeAllocator.Allocate<BinarySDNode>(); 2643 new (N) BinarySDNode(Opcode, VTs, N1, N2); 2644 CSEMap.InsertNode(N, IP); 2645 } else { 2646 N = NodeAllocator.Allocate<BinarySDNode>(); 2647 new (N) BinarySDNode(Opcode, VTs, N1, N2); 2648 } 2649 2650 AllNodes.push_back(N); 2651#ifndef NDEBUG 2652 VerifyNode(N); 2653#endif 2654 return SDValue(N, 0); 2655} 2656 2657SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, 2658 SDValue N1, SDValue N2, SDValue N3) { 2659 // Perform various simplifications. 2660 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 2661 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 2662 switch (Opcode) { 2663 case ISD::CONCAT_VECTORS: 2664 // A CONCAT_VECTOR with all operands BUILD_VECTOR can be simplified to 2665 // one big BUILD_VECTOR. 2666 if (N1.getOpcode() == ISD::BUILD_VECTOR && 2667 N2.getOpcode() == ISD::BUILD_VECTOR && 2668 N3.getOpcode() == ISD::BUILD_VECTOR) { 2669 SmallVector<SDValue, 16> Elts(N1.getNode()->op_begin(), N1.getNode()->op_end()); 2670 Elts.insert(Elts.end(), N2.getNode()->op_begin(), N2.getNode()->op_end()); 2671 Elts.insert(Elts.end(), N3.getNode()->op_begin(), N3.getNode()->op_end()); 2672 return getNode(ISD::BUILD_VECTOR, VT, &Elts[0], Elts.size()); 2673 } 2674 break; 2675 case ISD::SETCC: { 2676 // Use FoldSetCC to simplify SETCC's. 2677 SDValue Simp = FoldSetCC(VT, N1, N2, cast<CondCodeSDNode>(N3)->get()); 2678 if (Simp.getNode()) return Simp; 2679 break; 2680 } 2681 case ISD::SELECT: 2682 if (N1C) { 2683 if (N1C->getZExtValue()) 2684 return N2; // select true, X, Y -> X 2685 else 2686 return N3; // select false, X, Y -> Y 2687 } 2688 2689 if (N2 == N3) return N2; // select C, X, X -> X 2690 break; 2691 case ISD::BRCOND: 2692 if (N2C) { 2693 if (N2C->getZExtValue()) // Unconditional branch 2694 return getNode(ISD::BR, MVT::Other, N1, N3); 2695 else 2696 return N1; // Never-taken branch 2697 } 2698 break; 2699 case ISD::VECTOR_SHUFFLE: 2700 assert(N1.getValueType() == N2.getValueType() && 2701 N1.getValueType().isVector() && 2702 VT.isVector() && N3.getValueType().isVector() && 2703 N3.getOpcode() == ISD::BUILD_VECTOR && 2704 VT.getVectorNumElements() == N3.getNumOperands() && 2705 "Illegal VECTOR_SHUFFLE node!"); 2706 break; 2707 case ISD::BIT_CONVERT: 2708 // Fold bit_convert nodes from a type to themselves. 2709 if (N1.getValueType() == VT) 2710 return N1; 2711 break; 2712 } 2713 2714 // Memoize node if it doesn't produce a flag. 2715 SDNode *N; 2716 SDVTList VTs = getVTList(VT); 2717 if (VT != MVT::Flag) { 2718 SDValue Ops[] = { N1, N2, N3 }; 2719 FoldingSetNodeID ID; 2720 AddNodeIDNode(ID, Opcode, VTs, Ops, 3); 2721 void *IP = 0; 2722 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2723 return SDValue(E, 0); 2724 N = NodeAllocator.Allocate<TernarySDNode>(); 2725 new (N) TernarySDNode(Opcode, VTs, N1, N2, N3); 2726 CSEMap.InsertNode(N, IP); 2727 } else { 2728 N = NodeAllocator.Allocate<TernarySDNode>(); 2729 new (N) TernarySDNode(Opcode, VTs, N1, N2, N3); 2730 } 2731 AllNodes.push_back(N); 2732#ifndef NDEBUG 2733 VerifyNode(N); 2734#endif 2735 return SDValue(N, 0); 2736} 2737 2738SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, 2739 SDValue N1, SDValue N2, SDValue N3, 2740 SDValue N4) { 2741 SDValue Ops[] = { N1, N2, N3, N4 }; 2742 return getNode(Opcode, VT, Ops, 4); 2743} 2744 2745SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, 2746 SDValue N1, SDValue N2, SDValue N3, 2747 SDValue N4, SDValue N5) { 2748 SDValue Ops[] = { N1, N2, N3, N4, N5 }; 2749 return getNode(Opcode, VT, Ops, 5); 2750} 2751 2752/// getMemsetValue - Vectorized representation of the memset value 2753/// operand. 2754static SDValue getMemsetValue(SDValue Value, MVT VT, SelectionDAG &DAG) { 2755 unsigned NumBits = VT.isVector() ? 2756 VT.getVectorElementType().getSizeInBits() : VT.getSizeInBits(); 2757 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) { 2758 APInt Val = APInt(NumBits, C->getZExtValue() & 255); 2759 unsigned Shift = 8; 2760 for (unsigned i = NumBits; i > 8; i >>= 1) { 2761 Val = (Val << Shift) | Val; 2762 Shift <<= 1; 2763 } 2764 if (VT.isInteger()) 2765 return DAG.getConstant(Val, VT); 2766 return DAG.getConstantFP(APFloat(Val), VT); 2767 } 2768 2769 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 2770 Value = DAG.getNode(ISD::ZERO_EXTEND, VT, Value); 2771 unsigned Shift = 8; 2772 for (unsigned i = NumBits; i > 8; i >>= 1) { 2773 Value = DAG.getNode(ISD::OR, VT, 2774 DAG.getNode(ISD::SHL, VT, Value, 2775 DAG.getConstant(Shift, 2776 TLI.getShiftAmountTy())), 2777 Value); 2778 Shift <<= 1; 2779 } 2780 2781 return Value; 2782} 2783 2784/// getMemsetStringVal - Similar to getMemsetValue. Except this is only 2785/// used when a memcpy is turned into a memset when the source is a constant 2786/// string ptr. 2787static SDValue getMemsetStringVal(MVT VT, SelectionDAG &DAG, 2788 const TargetLowering &TLI, 2789 std::string &Str, unsigned Offset) { 2790 // Handle vector with all elements zero. 2791 if (Str.empty()) { 2792 if (VT.isInteger()) 2793 return DAG.getConstant(0, VT); 2794 unsigned NumElts = VT.getVectorNumElements(); 2795 MVT EltVT = (VT.getVectorElementType() == MVT::f32) ? MVT::i32 : MVT::i64; 2796 return DAG.getNode(ISD::BIT_CONVERT, VT, 2797 DAG.getConstant(0, MVT::getVectorVT(EltVT, NumElts))); 2798 } 2799 2800 assert(!VT.isVector() && "Can't handle vector type here!"); 2801 unsigned NumBits = VT.getSizeInBits(); 2802 unsigned MSB = NumBits / 8; 2803 uint64_t Val = 0; 2804 if (TLI.isLittleEndian()) 2805 Offset = Offset + MSB - 1; 2806 for (unsigned i = 0; i != MSB; ++i) { 2807 Val = (Val << 8) | (unsigned char)Str[Offset]; 2808 Offset += TLI.isLittleEndian() ? -1 : 1; 2809 } 2810 return DAG.getConstant(Val, VT); 2811} 2812 2813/// getMemBasePlusOffset - Returns base and offset node for the 2814/// 2815static SDValue getMemBasePlusOffset(SDValue Base, unsigned Offset, 2816 SelectionDAG &DAG) { 2817 MVT VT = Base.getValueType(); 2818 return DAG.getNode(ISD::ADD, VT, Base, DAG.getConstant(Offset, VT)); 2819} 2820 2821/// isMemSrcFromString - Returns true if memcpy source is a string constant. 2822/// 2823static bool isMemSrcFromString(SDValue Src, std::string &Str) { 2824 unsigned SrcDelta = 0; 2825 GlobalAddressSDNode *G = NULL; 2826 if (Src.getOpcode() == ISD::GlobalAddress) 2827 G = cast<GlobalAddressSDNode>(Src); 2828 else if (Src.getOpcode() == ISD::ADD && 2829 Src.getOperand(0).getOpcode() == ISD::GlobalAddress && 2830 Src.getOperand(1).getOpcode() == ISD::Constant) { 2831 G = cast<GlobalAddressSDNode>(Src.getOperand(0)); 2832 SrcDelta = cast<ConstantSDNode>(Src.getOperand(1))->getZExtValue(); 2833 } 2834 if (!G) 2835 return false; 2836 2837 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal()); 2838 if (GV && GetConstantStringInfo(GV, Str, SrcDelta, false)) 2839 return true; 2840 2841 return false; 2842} 2843 2844/// MeetsMaxMemopRequirement - Determines if the number of memory ops required 2845/// to replace the memset / memcpy is below the threshold. It also returns the 2846/// types of the sequence of memory ops to perform memset / memcpy. 2847static 2848bool MeetsMaxMemopRequirement(std::vector<MVT> &MemOps, 2849 SDValue Dst, SDValue Src, 2850 unsigned Limit, uint64_t Size, unsigned &Align, 2851 std::string &Str, bool &isSrcStr, 2852 SelectionDAG &DAG, 2853 const TargetLowering &TLI) { 2854 isSrcStr = isMemSrcFromString(Src, Str); 2855 bool isSrcConst = isa<ConstantSDNode>(Src); 2856 bool AllowUnalign = TLI.allowsUnalignedMemoryAccesses(); 2857 MVT VT = TLI.getOptimalMemOpType(Size, Align, isSrcConst, isSrcStr); 2858 if (VT != MVT::iAny) { 2859 unsigned NewAlign = (unsigned) 2860 TLI.getTargetData()->getABITypeAlignment(VT.getTypeForMVT()); 2861 // If source is a string constant, this will require an unaligned load. 2862 if (NewAlign > Align && (isSrcConst || AllowUnalign)) { 2863 if (Dst.getOpcode() != ISD::FrameIndex) { 2864 // Can't change destination alignment. It requires a unaligned store. 2865 if (AllowUnalign) 2866 VT = MVT::iAny; 2867 } else { 2868 int FI = cast<FrameIndexSDNode>(Dst)->getIndex(); 2869 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 2870 if (MFI->isFixedObjectIndex(FI)) { 2871 // Can't change destination alignment. It requires a unaligned store. 2872 if (AllowUnalign) 2873 VT = MVT::iAny; 2874 } else { 2875 // Give the stack frame object a larger alignment if needed. 2876 if (MFI->getObjectAlignment(FI) < NewAlign) 2877 MFI->setObjectAlignment(FI, NewAlign); 2878 Align = NewAlign; 2879 } 2880 } 2881 } 2882 } 2883 2884 if (VT == MVT::iAny) { 2885 if (AllowUnalign) { 2886 VT = MVT::i64; 2887 } else { 2888 switch (Align & 7) { 2889 case 0: VT = MVT::i64; break; 2890 case 4: VT = MVT::i32; break; 2891 case 2: VT = MVT::i16; break; 2892 default: VT = MVT::i8; break; 2893 } 2894 } 2895 2896 MVT LVT = MVT::i64; 2897 while (!TLI.isTypeLegal(LVT)) 2898 LVT = (MVT::SimpleValueType)(LVT.getSimpleVT() - 1); 2899 assert(LVT.isInteger()); 2900 2901 if (VT.bitsGT(LVT)) 2902 VT = LVT; 2903 } 2904 2905 unsigned NumMemOps = 0; 2906 while (Size != 0) { 2907 unsigned VTSize = VT.getSizeInBits() / 8; 2908 while (VTSize > Size) { 2909 // For now, only use non-vector load / store's for the left-over pieces. 2910 if (VT.isVector()) { 2911 VT = MVT::i64; 2912 while (!TLI.isTypeLegal(VT)) 2913 VT = (MVT::SimpleValueType)(VT.getSimpleVT() - 1); 2914 VTSize = VT.getSizeInBits() / 8; 2915 } else { 2916 VT = (MVT::SimpleValueType)(VT.getSimpleVT() - 1); 2917 VTSize >>= 1; 2918 } 2919 } 2920 2921 if (++NumMemOps > Limit) 2922 return false; 2923 MemOps.push_back(VT); 2924 Size -= VTSize; 2925 } 2926 2927 return true; 2928} 2929 2930static SDValue getMemcpyLoadsAndStores(SelectionDAG &DAG, 2931 SDValue Chain, SDValue Dst, 2932 SDValue Src, uint64_t Size, 2933 unsigned Align, bool AlwaysInline, 2934 const Value *DstSV, uint64_t DstSVOff, 2935 const Value *SrcSV, uint64_t SrcSVOff){ 2936 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 2937 2938 // Expand memcpy to a series of load and store ops if the size operand falls 2939 // below a certain threshold. 2940 std::vector<MVT> MemOps; 2941 uint64_t Limit = -1ULL; 2942 if (!AlwaysInline) 2943 Limit = TLI.getMaxStoresPerMemcpy(); 2944 unsigned DstAlign = Align; // Destination alignment can change. 2945 std::string Str; 2946 bool CopyFromStr; 2947 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, Limit, Size, DstAlign, 2948 Str, CopyFromStr, DAG, TLI)) 2949 return SDValue(); 2950 2951 2952 bool isZeroStr = CopyFromStr && Str.empty(); 2953 SmallVector<SDValue, 8> OutChains; 2954 unsigned NumMemOps = MemOps.size(); 2955 uint64_t SrcOff = 0, DstOff = 0; 2956 for (unsigned i = 0; i < NumMemOps; i++) { 2957 MVT VT = MemOps[i]; 2958 unsigned VTSize = VT.getSizeInBits() / 8; 2959 SDValue Value, Store; 2960 2961 if (CopyFromStr && (isZeroStr || !VT.isVector())) { 2962 // It's unlikely a store of a vector immediate can be done in a single 2963 // instruction. It would require a load from a constantpool first. 2964 // We also handle store a vector with all zero's. 2965 // FIXME: Handle other cases where store of vector immediate is done in 2966 // a single instruction. 2967 Value = getMemsetStringVal(VT, DAG, TLI, Str, SrcOff); 2968 Store = DAG.getStore(Chain, Value, 2969 getMemBasePlusOffset(Dst, DstOff, DAG), 2970 DstSV, DstSVOff + DstOff, false, DstAlign); 2971 } else { 2972 Value = DAG.getLoad(VT, Chain, 2973 getMemBasePlusOffset(Src, SrcOff, DAG), 2974 SrcSV, SrcSVOff + SrcOff, false, Align); 2975 Store = DAG.getStore(Chain, Value, 2976 getMemBasePlusOffset(Dst, DstOff, DAG), 2977 DstSV, DstSVOff + DstOff, false, DstAlign); 2978 } 2979 OutChains.push_back(Store); 2980 SrcOff += VTSize; 2981 DstOff += VTSize; 2982 } 2983 2984 return DAG.getNode(ISD::TokenFactor, MVT::Other, 2985 &OutChains[0], OutChains.size()); 2986} 2987 2988static SDValue getMemmoveLoadsAndStores(SelectionDAG &DAG, 2989 SDValue Chain, SDValue Dst, 2990 SDValue Src, uint64_t Size, 2991 unsigned Align, bool AlwaysInline, 2992 const Value *DstSV, uint64_t DstSVOff, 2993 const Value *SrcSV, uint64_t SrcSVOff){ 2994 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 2995 2996 // Expand memmove to a series of load and store ops if the size operand falls 2997 // below a certain threshold. 2998 std::vector<MVT> MemOps; 2999 uint64_t Limit = -1ULL; 3000 if (!AlwaysInline) 3001 Limit = TLI.getMaxStoresPerMemmove(); 3002 unsigned DstAlign = Align; // Destination alignment can change. 3003 std::string Str; 3004 bool CopyFromStr; 3005 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, Limit, Size, DstAlign, 3006 Str, CopyFromStr, DAG, TLI)) 3007 return SDValue(); 3008 3009 uint64_t SrcOff = 0, DstOff = 0; 3010 3011 SmallVector<SDValue, 8> LoadValues; 3012 SmallVector<SDValue, 8> LoadChains; 3013 SmallVector<SDValue, 8> OutChains; 3014 unsigned NumMemOps = MemOps.size(); 3015 for (unsigned i = 0; i < NumMemOps; i++) { 3016 MVT VT = MemOps[i]; 3017 unsigned VTSize = VT.getSizeInBits() / 8; 3018 SDValue Value, Store; 3019 3020 Value = DAG.getLoad(VT, Chain, 3021 getMemBasePlusOffset(Src, SrcOff, DAG), 3022 SrcSV, SrcSVOff + SrcOff, false, Align); 3023 LoadValues.push_back(Value); 3024 LoadChains.push_back(Value.getValue(1)); 3025 SrcOff += VTSize; 3026 } 3027 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 3028 &LoadChains[0], LoadChains.size()); 3029 OutChains.clear(); 3030 for (unsigned i = 0; i < NumMemOps; i++) { 3031 MVT VT = MemOps[i]; 3032 unsigned VTSize = VT.getSizeInBits() / 8; 3033 SDValue Value, Store; 3034 3035 Store = DAG.getStore(Chain, LoadValues[i], 3036 getMemBasePlusOffset(Dst, DstOff, DAG), 3037 DstSV, DstSVOff + DstOff, false, DstAlign); 3038 OutChains.push_back(Store); 3039 DstOff += VTSize; 3040 } 3041 3042 return DAG.getNode(ISD::TokenFactor, MVT::Other, 3043 &OutChains[0], OutChains.size()); 3044} 3045 3046static SDValue getMemsetStores(SelectionDAG &DAG, 3047 SDValue Chain, SDValue Dst, 3048 SDValue Src, uint64_t Size, 3049 unsigned Align, 3050 const Value *DstSV, uint64_t DstSVOff) { 3051 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 3052 3053 // Expand memset to a series of load/store ops if the size operand 3054 // falls below a certain threshold. 3055 std::vector<MVT> MemOps; 3056 std::string Str; 3057 bool CopyFromStr; 3058 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, TLI.getMaxStoresPerMemset(), 3059 Size, Align, Str, CopyFromStr, DAG, TLI)) 3060 return SDValue(); 3061 3062 SmallVector<SDValue, 8> OutChains; 3063 uint64_t DstOff = 0; 3064 3065 unsigned NumMemOps = MemOps.size(); 3066 for (unsigned i = 0; i < NumMemOps; i++) { 3067 MVT VT = MemOps[i]; 3068 unsigned VTSize = VT.getSizeInBits() / 8; 3069 SDValue Value = getMemsetValue(Src, VT, DAG); 3070 SDValue Store = DAG.getStore(Chain, Value, 3071 getMemBasePlusOffset(Dst, DstOff, DAG), 3072 DstSV, DstSVOff + DstOff); 3073 OutChains.push_back(Store); 3074 DstOff += VTSize; 3075 } 3076 3077 return DAG.getNode(ISD::TokenFactor, MVT::Other, 3078 &OutChains[0], OutChains.size()); 3079} 3080 3081SDValue SelectionDAG::getMemcpy(SDValue Chain, SDValue Dst, 3082 SDValue Src, SDValue Size, 3083 unsigned Align, bool AlwaysInline, 3084 const Value *DstSV, uint64_t DstSVOff, 3085 const Value *SrcSV, uint64_t SrcSVOff) { 3086 3087 // Check to see if we should lower the memcpy to loads and stores first. 3088 // For cases within the target-specified limits, this is the best choice. 3089 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 3090 if (ConstantSize) { 3091 // Memcpy with size zero? Just return the original chain. 3092 if (ConstantSize->isNullValue()) 3093 return Chain; 3094 3095 SDValue Result = 3096 getMemcpyLoadsAndStores(*this, Chain, Dst, Src, 3097 ConstantSize->getZExtValue(), 3098 Align, false, DstSV, DstSVOff, SrcSV, SrcSVOff); 3099 if (Result.getNode()) 3100 return Result; 3101 } 3102 3103 // Then check to see if we should lower the memcpy with target-specific 3104 // code. If the target chooses to do this, this is the next best. 3105 SDValue Result = 3106 TLI.EmitTargetCodeForMemcpy(*this, Chain, Dst, Src, Size, Align, 3107 AlwaysInline, 3108 DstSV, DstSVOff, SrcSV, SrcSVOff); 3109 if (Result.getNode()) 3110 return Result; 3111 3112 // If we really need inline code and the target declined to provide it, 3113 // use a (potentially long) sequence of loads and stores. 3114 if (AlwaysInline) { 3115 assert(ConstantSize && "AlwaysInline requires a constant size!"); 3116 return getMemcpyLoadsAndStores(*this, Chain, Dst, Src, 3117 ConstantSize->getZExtValue(), Align, true, 3118 DstSV, DstSVOff, SrcSV, SrcSVOff); 3119 } 3120 3121 // Emit a library call. 3122 TargetLowering::ArgListTy Args; 3123 TargetLowering::ArgListEntry Entry; 3124 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 3125 Entry.Node = Dst; Args.push_back(Entry); 3126 Entry.Node = Src; Args.push_back(Entry); 3127 Entry.Node = Size; Args.push_back(Entry); 3128 std::pair<SDValue,SDValue> CallResult = 3129 TLI.LowerCallTo(Chain, Type::VoidTy, 3130 false, false, false, false, CallingConv::C, false, 3131 getExternalSymbol("memcpy", TLI.getPointerTy()), 3132 Args, *this); 3133 return CallResult.second; 3134} 3135 3136SDValue SelectionDAG::getMemmove(SDValue Chain, SDValue Dst, 3137 SDValue Src, SDValue Size, 3138 unsigned Align, 3139 const Value *DstSV, uint64_t DstSVOff, 3140 const Value *SrcSV, uint64_t SrcSVOff) { 3141 3142 // Check to see if we should lower the memmove to loads and stores first. 3143 // For cases within the target-specified limits, this is the best choice. 3144 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 3145 if (ConstantSize) { 3146 // Memmove with size zero? Just return the original chain. 3147 if (ConstantSize->isNullValue()) 3148 return Chain; 3149 3150 SDValue Result = 3151 getMemmoveLoadsAndStores(*this, Chain, Dst, Src, 3152 ConstantSize->getZExtValue(), 3153 Align, false, DstSV, DstSVOff, SrcSV, SrcSVOff); 3154 if (Result.getNode()) 3155 return Result; 3156 } 3157 3158 // Then check to see if we should lower the memmove with target-specific 3159 // code. If the target chooses to do this, this is the next best. 3160 SDValue Result = 3161 TLI.EmitTargetCodeForMemmove(*this, Chain, Dst, Src, Size, Align, 3162 DstSV, DstSVOff, SrcSV, SrcSVOff); 3163 if (Result.getNode()) 3164 return Result; 3165 3166 // Emit a library call. 3167 TargetLowering::ArgListTy Args; 3168 TargetLowering::ArgListEntry Entry; 3169 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 3170 Entry.Node = Dst; Args.push_back(Entry); 3171 Entry.Node = Src; Args.push_back(Entry); 3172 Entry.Node = Size; Args.push_back(Entry); 3173 std::pair<SDValue,SDValue> CallResult = 3174 TLI.LowerCallTo(Chain, Type::VoidTy, 3175 false, false, false, false, CallingConv::C, false, 3176 getExternalSymbol("memmove", TLI.getPointerTy()), 3177 Args, *this); 3178 return CallResult.second; 3179} 3180 3181SDValue SelectionDAG::getMemset(SDValue Chain, SDValue Dst, 3182 SDValue Src, SDValue Size, 3183 unsigned Align, 3184 const Value *DstSV, uint64_t DstSVOff) { 3185 3186 // Check to see if we should lower the memset to stores first. 3187 // For cases within the target-specified limits, this is the best choice. 3188 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 3189 if (ConstantSize) { 3190 // Memset with size zero? Just return the original chain. 3191 if (ConstantSize->isNullValue()) 3192 return Chain; 3193 3194 SDValue Result = 3195 getMemsetStores(*this, Chain, Dst, Src, ConstantSize->getZExtValue(), 3196 Align, DstSV, DstSVOff); 3197 if (Result.getNode()) 3198 return Result; 3199 } 3200 3201 // Then check to see if we should lower the memset with target-specific 3202 // code. If the target chooses to do this, this is the next best. 3203 SDValue Result = 3204 TLI.EmitTargetCodeForMemset(*this, Chain, Dst, Src, Size, Align, 3205 DstSV, DstSVOff); 3206 if (Result.getNode()) 3207 return Result; 3208 3209 // Emit a library call. 3210 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType(); 3211 TargetLowering::ArgListTy Args; 3212 TargetLowering::ArgListEntry Entry; 3213 Entry.Node = Dst; Entry.Ty = IntPtrTy; 3214 Args.push_back(Entry); 3215 // Extend or truncate the argument to be an i32 value for the call. 3216 if (Src.getValueType().bitsGT(MVT::i32)) 3217 Src = getNode(ISD::TRUNCATE, MVT::i32, Src); 3218 else 3219 Src = getNode(ISD::ZERO_EXTEND, MVT::i32, Src); 3220 Entry.Node = Src; Entry.Ty = Type::Int32Ty; Entry.isSExt = true; 3221 Args.push_back(Entry); 3222 Entry.Node = Size; Entry.Ty = IntPtrTy; Entry.isSExt = false; 3223 Args.push_back(Entry); 3224 std::pair<SDValue,SDValue> CallResult = 3225 TLI.LowerCallTo(Chain, Type::VoidTy, 3226 false, false, false, false, CallingConv::C, false, 3227 getExternalSymbol("memset", TLI.getPointerTy()), 3228 Args, *this); 3229 return CallResult.second; 3230} 3231 3232SDValue SelectionDAG::getAtomic(unsigned Opcode, SDValue Chain, 3233 SDValue Ptr, SDValue Cmp, 3234 SDValue Swp, const Value* PtrVal, 3235 unsigned Alignment) { 3236 assert((Opcode == ISD::ATOMIC_CMP_SWAP_8 || 3237 Opcode == ISD::ATOMIC_CMP_SWAP_16 || 3238 Opcode == ISD::ATOMIC_CMP_SWAP_32 || 3239 Opcode == ISD::ATOMIC_CMP_SWAP_64) && "Invalid Atomic Op"); 3240 assert(Cmp.getValueType() == Swp.getValueType() && "Invalid Atomic Op Types"); 3241 3242 MVT VT = Cmp.getValueType(); 3243 3244 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3245 Alignment = getMVTAlignment(VT); 3246 3247 SDVTList VTs = getVTList(VT, MVT::Other); 3248 FoldingSetNodeID ID; 3249 SDValue Ops[] = {Chain, Ptr, Cmp, Swp}; 3250 AddNodeIDNode(ID, Opcode, VTs, Ops, 4); 3251 void* IP = 0; 3252 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3253 return SDValue(E, 0); 3254 SDNode* N = NodeAllocator.Allocate<AtomicSDNode>(); 3255 new (N) AtomicSDNode(Opcode, VTs, Chain, Ptr, Cmp, Swp, PtrVal, Alignment); 3256 CSEMap.InsertNode(N, IP); 3257 AllNodes.push_back(N); 3258 return SDValue(N, 0); 3259} 3260 3261SDValue SelectionDAG::getAtomic(unsigned Opcode, SDValue Chain, 3262 SDValue Ptr, SDValue Val, 3263 const Value* PtrVal, 3264 unsigned Alignment) { 3265 assert((Opcode == ISD::ATOMIC_LOAD_ADD_8 || 3266 Opcode == ISD::ATOMIC_LOAD_SUB_8 || 3267 Opcode == ISD::ATOMIC_LOAD_AND_8 || 3268 Opcode == ISD::ATOMIC_LOAD_OR_8 || 3269 Opcode == ISD::ATOMIC_LOAD_XOR_8 || 3270 Opcode == ISD::ATOMIC_LOAD_NAND_8 || 3271 Opcode == ISD::ATOMIC_LOAD_MIN_8 || 3272 Opcode == ISD::ATOMIC_LOAD_MAX_8 || 3273 Opcode == ISD::ATOMIC_LOAD_UMIN_8 || 3274 Opcode == ISD::ATOMIC_LOAD_UMAX_8 || 3275 Opcode == ISD::ATOMIC_SWAP_8 || 3276 Opcode == ISD::ATOMIC_LOAD_ADD_16 || 3277 Opcode == ISD::ATOMIC_LOAD_SUB_16 || 3278 Opcode == ISD::ATOMIC_LOAD_AND_16 || 3279 Opcode == ISD::ATOMIC_LOAD_OR_16 || 3280 Opcode == ISD::ATOMIC_LOAD_XOR_16 || 3281 Opcode == ISD::ATOMIC_LOAD_NAND_16 || 3282 Opcode == ISD::ATOMIC_LOAD_MIN_16 || 3283 Opcode == ISD::ATOMIC_LOAD_MAX_16 || 3284 Opcode == ISD::ATOMIC_LOAD_UMIN_16 || 3285 Opcode == ISD::ATOMIC_LOAD_UMAX_16 || 3286 Opcode == ISD::ATOMIC_SWAP_16 || 3287 Opcode == ISD::ATOMIC_LOAD_ADD_32 || 3288 Opcode == ISD::ATOMIC_LOAD_SUB_32 || 3289 Opcode == ISD::ATOMIC_LOAD_AND_32 || 3290 Opcode == ISD::ATOMIC_LOAD_OR_32 || 3291 Opcode == ISD::ATOMIC_LOAD_XOR_32 || 3292 Opcode == ISD::ATOMIC_LOAD_NAND_32 || 3293 Opcode == ISD::ATOMIC_LOAD_MIN_32 || 3294 Opcode == ISD::ATOMIC_LOAD_MAX_32 || 3295 Opcode == ISD::ATOMIC_LOAD_UMIN_32 || 3296 Opcode == ISD::ATOMIC_LOAD_UMAX_32 || 3297 Opcode == ISD::ATOMIC_SWAP_32 || 3298 Opcode == ISD::ATOMIC_LOAD_ADD_64 || 3299 Opcode == ISD::ATOMIC_LOAD_SUB_64 || 3300 Opcode == ISD::ATOMIC_LOAD_AND_64 || 3301 Opcode == ISD::ATOMIC_LOAD_OR_64 || 3302 Opcode == ISD::ATOMIC_LOAD_XOR_64 || 3303 Opcode == ISD::ATOMIC_LOAD_NAND_64 || 3304 Opcode == ISD::ATOMIC_LOAD_MIN_64 || 3305 Opcode == ISD::ATOMIC_LOAD_MAX_64 || 3306 Opcode == ISD::ATOMIC_LOAD_UMIN_64 || 3307 Opcode == ISD::ATOMIC_LOAD_UMAX_64 || 3308 Opcode == ISD::ATOMIC_SWAP_64) && "Invalid Atomic Op"); 3309 3310 MVT VT = Val.getValueType(); 3311 3312 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3313 Alignment = getMVTAlignment(VT); 3314 3315 SDVTList VTs = getVTList(VT, MVT::Other); 3316 FoldingSetNodeID ID; 3317 SDValue Ops[] = {Chain, Ptr, Val}; 3318 AddNodeIDNode(ID, Opcode, VTs, Ops, 3); 3319 void* IP = 0; 3320 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3321 return SDValue(E, 0); 3322 SDNode* N = NodeAllocator.Allocate<AtomicSDNode>(); 3323 new (N) AtomicSDNode(Opcode, VTs, Chain, Ptr, Val, PtrVal, Alignment); 3324 CSEMap.InsertNode(N, IP); 3325 AllNodes.push_back(N); 3326 return SDValue(N, 0); 3327} 3328 3329/// getMergeValues - Create a MERGE_VALUES node from the given operands. 3330/// Allowed to return something different (and simpler) if Simplify is true. 3331SDValue SelectionDAG::getMergeValues(const SDValue *Ops, unsigned NumOps, 3332 bool Simplify) { 3333 if (Simplify && NumOps == 1) 3334 return Ops[0]; 3335 3336 SmallVector<MVT, 4> VTs; 3337 VTs.reserve(NumOps); 3338 for (unsigned i = 0; i < NumOps; ++i) 3339 VTs.push_back(Ops[i].getValueType()); 3340 return getNode(ISD::MERGE_VALUES, getVTList(&VTs[0], NumOps), Ops, NumOps); 3341} 3342 3343SDValue 3344SelectionDAG::getMemIntrinsicNode(unsigned Opcode, 3345 const MVT *VTs, unsigned NumVTs, 3346 const SDValue *Ops, unsigned NumOps, 3347 MVT MemVT, const Value *srcValue, int SVOff, 3348 unsigned Align, bool Vol, 3349 bool ReadMem, bool WriteMem) { 3350 return getMemIntrinsicNode(Opcode, makeVTList(VTs, NumVTs), Ops, NumOps, 3351 MemVT, srcValue, SVOff, Align, Vol, 3352 ReadMem, WriteMem); 3353} 3354 3355SDValue 3356SelectionDAG::getMemIntrinsicNode(unsigned Opcode, SDVTList VTList, 3357 const SDValue *Ops, unsigned NumOps, 3358 MVT MemVT, const Value *srcValue, int SVOff, 3359 unsigned Align, bool Vol, 3360 bool ReadMem, bool WriteMem) { 3361 // Memoize the node unless it returns a flag. 3362 MemIntrinsicSDNode *N; 3363 if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) { 3364 FoldingSetNodeID ID; 3365 AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps); 3366 void *IP = 0; 3367 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3368 return SDValue(E, 0); 3369 3370 N = NodeAllocator.Allocate<MemIntrinsicSDNode>(); 3371 new (N) MemIntrinsicSDNode(Opcode, VTList, Ops, NumOps, MemVT, 3372 srcValue, SVOff, Align, Vol, ReadMem, WriteMem); 3373 CSEMap.InsertNode(N, IP); 3374 } else { 3375 N = NodeAllocator.Allocate<MemIntrinsicSDNode>(); 3376 new (N) MemIntrinsicSDNode(Opcode, VTList, Ops, NumOps, MemVT, 3377 srcValue, SVOff, Align, Vol, ReadMem, WriteMem); 3378 } 3379 AllNodes.push_back(N); 3380 return SDValue(N, 0); 3381} 3382 3383SDValue 3384SelectionDAG::getCall(unsigned CallingConv, bool IsVarArgs, bool IsTailCall, 3385 bool IsInreg, SDVTList VTs, 3386 const SDValue *Operands, unsigned NumOperands) { 3387 // Do not include isTailCall in the folding set profile. 3388 FoldingSetNodeID ID; 3389 AddNodeIDNode(ID, ISD::CALL, VTs, Operands, NumOperands); 3390 ID.AddInteger(CallingConv); 3391 ID.AddInteger(IsVarArgs); 3392 void *IP = 0; 3393 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) { 3394 // Instead of including isTailCall in the folding set, we just 3395 // set the flag of the existing node. 3396 if (!IsTailCall) 3397 cast<CallSDNode>(E)->setNotTailCall(); 3398 return SDValue(E, 0); 3399 } 3400 SDNode *N = NodeAllocator.Allocate<CallSDNode>(); 3401 new (N) CallSDNode(CallingConv, IsVarArgs, IsTailCall, IsInreg, 3402 VTs, Operands, NumOperands); 3403 CSEMap.InsertNode(N, IP); 3404 AllNodes.push_back(N); 3405 return SDValue(N, 0); 3406} 3407 3408SDValue 3409SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, 3410 MVT VT, SDValue Chain, 3411 SDValue Ptr, SDValue Offset, 3412 const Value *SV, int SVOffset, MVT EVT, 3413 bool isVolatile, unsigned Alignment) { 3414 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3415 Alignment = getMVTAlignment(VT); 3416 3417 if (VT == EVT) { 3418 ExtType = ISD::NON_EXTLOAD; 3419 } else if (ExtType == ISD::NON_EXTLOAD) { 3420 assert(VT == EVT && "Non-extending load from different memory type!"); 3421 } else { 3422 // Extending load. 3423 if (VT.isVector()) 3424 assert(EVT.getVectorNumElements() == VT.getVectorNumElements() && 3425 "Invalid vector extload!"); 3426 else 3427 assert(EVT.bitsLT(VT) && 3428 "Should only be an extending load, not truncating!"); 3429 assert((ExtType == ISD::EXTLOAD || VT.isInteger()) && 3430 "Cannot sign/zero extend a FP/Vector load!"); 3431 assert(VT.isInteger() == EVT.isInteger() && 3432 "Cannot convert from FP to Int or Int -> FP!"); 3433 } 3434 3435 bool Indexed = AM != ISD::UNINDEXED; 3436 assert((Indexed || Offset.getOpcode() == ISD::UNDEF) && 3437 "Unindexed load with an offset!"); 3438 3439 SDVTList VTs = Indexed ? 3440 getVTList(VT, Ptr.getValueType(), MVT::Other) : getVTList(VT, MVT::Other); 3441 SDValue Ops[] = { Chain, Ptr, Offset }; 3442 FoldingSetNodeID ID; 3443 AddNodeIDNode(ID, ISD::LOAD, VTs, Ops, 3); 3444 ID.AddInteger(AM); 3445 ID.AddInteger(ExtType); 3446 ID.AddInteger(EVT.getRawBits()); 3447 ID.AddInteger(encodeMemSDNodeFlags(isVolatile, Alignment)); 3448 void *IP = 0; 3449 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3450 return SDValue(E, 0); 3451 SDNode *N = NodeAllocator.Allocate<LoadSDNode>(); 3452 new (N) LoadSDNode(Ops, VTs, AM, ExtType, EVT, SV, SVOffset, 3453 Alignment, isVolatile); 3454 CSEMap.InsertNode(N, IP); 3455 AllNodes.push_back(N); 3456 return SDValue(N, 0); 3457} 3458 3459SDValue SelectionDAG::getLoad(MVT VT, 3460 SDValue Chain, SDValue Ptr, 3461 const Value *SV, int SVOffset, 3462 bool isVolatile, unsigned Alignment) { 3463 SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType()); 3464 return getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD, VT, Chain, Ptr, Undef, 3465 SV, SVOffset, VT, isVolatile, Alignment); 3466} 3467 3468SDValue SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, MVT VT, 3469 SDValue Chain, SDValue Ptr, 3470 const Value *SV, 3471 int SVOffset, MVT EVT, 3472 bool isVolatile, unsigned Alignment) { 3473 SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType()); 3474 return getLoad(ISD::UNINDEXED, ExtType, VT, Chain, Ptr, Undef, 3475 SV, SVOffset, EVT, isVolatile, Alignment); 3476} 3477 3478SDValue 3479SelectionDAG::getIndexedLoad(SDValue OrigLoad, SDValue Base, 3480 SDValue Offset, ISD::MemIndexedMode AM) { 3481 LoadSDNode *LD = cast<LoadSDNode>(OrigLoad); 3482 assert(LD->getOffset().getOpcode() == ISD::UNDEF && 3483 "Load is already a indexed load!"); 3484 return getLoad(AM, LD->getExtensionType(), OrigLoad.getValueType(), 3485 LD->getChain(), Base, Offset, LD->getSrcValue(), 3486 LD->getSrcValueOffset(), LD->getMemoryVT(), 3487 LD->isVolatile(), LD->getAlignment()); 3488} 3489 3490SDValue SelectionDAG::getStore(SDValue Chain, SDValue Val, 3491 SDValue Ptr, const Value *SV, int SVOffset, 3492 bool isVolatile, unsigned Alignment) { 3493 MVT VT = Val.getValueType(); 3494 3495 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3496 Alignment = getMVTAlignment(VT); 3497 3498 SDVTList VTs = getVTList(MVT::Other); 3499 SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType()); 3500 SDValue Ops[] = { Chain, Val, Ptr, Undef }; 3501 FoldingSetNodeID ID; 3502 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); 3503 ID.AddInteger(ISD::UNINDEXED); 3504 ID.AddInteger(false); 3505 ID.AddInteger(VT.getRawBits()); 3506 ID.AddInteger(encodeMemSDNodeFlags(isVolatile, Alignment)); 3507 void *IP = 0; 3508 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3509 return SDValue(E, 0); 3510 SDNode *N = NodeAllocator.Allocate<StoreSDNode>(); 3511 new (N) StoreSDNode(Ops, VTs, ISD::UNINDEXED, false, 3512 VT, SV, SVOffset, Alignment, isVolatile); 3513 CSEMap.InsertNode(N, IP); 3514 AllNodes.push_back(N); 3515 return SDValue(N, 0); 3516} 3517 3518SDValue SelectionDAG::getTruncStore(SDValue Chain, SDValue Val, 3519 SDValue Ptr, const Value *SV, 3520 int SVOffset, MVT SVT, 3521 bool isVolatile, unsigned Alignment) { 3522 MVT VT = Val.getValueType(); 3523 3524 if (VT == SVT) 3525 return getStore(Chain, Val, Ptr, SV, SVOffset, isVolatile, Alignment); 3526 3527 assert(VT.bitsGT(SVT) && "Not a truncation?"); 3528 assert(VT.isInteger() == SVT.isInteger() && 3529 "Can't do FP-INT conversion!"); 3530 3531 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3532 Alignment = getMVTAlignment(VT); 3533 3534 SDVTList VTs = getVTList(MVT::Other); 3535 SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType()); 3536 SDValue Ops[] = { Chain, Val, Ptr, Undef }; 3537 FoldingSetNodeID ID; 3538 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); 3539 ID.AddInteger(ISD::UNINDEXED); 3540 ID.AddInteger(1); 3541 ID.AddInteger(SVT.getRawBits()); 3542 ID.AddInteger(encodeMemSDNodeFlags(isVolatile, Alignment)); 3543 void *IP = 0; 3544 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3545 return SDValue(E, 0); 3546 SDNode *N = NodeAllocator.Allocate<StoreSDNode>(); 3547 new (N) StoreSDNode(Ops, VTs, ISD::UNINDEXED, true, 3548 SVT, SV, SVOffset, Alignment, isVolatile); 3549 CSEMap.InsertNode(N, IP); 3550 AllNodes.push_back(N); 3551 return SDValue(N, 0); 3552} 3553 3554SDValue 3555SelectionDAG::getIndexedStore(SDValue OrigStore, SDValue Base, 3556 SDValue Offset, ISD::MemIndexedMode AM) { 3557 StoreSDNode *ST = cast<StoreSDNode>(OrigStore); 3558 assert(ST->getOffset().getOpcode() == ISD::UNDEF && 3559 "Store is already a indexed store!"); 3560 SDVTList VTs = getVTList(Base.getValueType(), MVT::Other); 3561 SDValue Ops[] = { ST->getChain(), ST->getValue(), Base, Offset }; 3562 FoldingSetNodeID ID; 3563 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); 3564 ID.AddInteger(AM); 3565 ID.AddInteger(ST->isTruncatingStore()); 3566 ID.AddInteger(ST->getMemoryVT().getRawBits()); 3567 ID.AddInteger(ST->getRawFlags()); 3568 void *IP = 0; 3569 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3570 return SDValue(E, 0); 3571 SDNode *N = NodeAllocator.Allocate<StoreSDNode>(); 3572 new (N) StoreSDNode(Ops, VTs, AM, 3573 ST->isTruncatingStore(), ST->getMemoryVT(), 3574 ST->getSrcValue(), ST->getSrcValueOffset(), 3575 ST->getAlignment(), ST->isVolatile()); 3576 CSEMap.InsertNode(N, IP); 3577 AllNodes.push_back(N); 3578 return SDValue(N, 0); 3579} 3580 3581SDValue SelectionDAG::getVAArg(MVT VT, 3582 SDValue Chain, SDValue Ptr, 3583 SDValue SV) { 3584 SDValue Ops[] = { Chain, Ptr, SV }; 3585 return getNode(ISD::VAARG, getVTList(VT, MVT::Other), Ops, 3); 3586} 3587 3588SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, 3589 const SDUse *Ops, unsigned NumOps) { 3590 switch (NumOps) { 3591 case 0: return getNode(Opcode, VT); 3592 case 1: return getNode(Opcode, VT, Ops[0]); 3593 case 2: return getNode(Opcode, VT, Ops[0], Ops[1]); 3594 case 3: return getNode(Opcode, VT, Ops[0], Ops[1], Ops[2]); 3595 default: break; 3596 } 3597 3598 // Copy from an SDUse array into an SDValue array for use with 3599 // the regular getNode logic. 3600 SmallVector<SDValue, 8> NewOps(Ops, Ops + NumOps); 3601 return getNode(Opcode, VT, &NewOps[0], NumOps); 3602} 3603 3604SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, 3605 const SDValue *Ops, unsigned NumOps) { 3606 switch (NumOps) { 3607 case 0: return getNode(Opcode, VT); 3608 case 1: return getNode(Opcode, VT, Ops[0]); 3609 case 2: return getNode(Opcode, VT, Ops[0], Ops[1]); 3610 case 3: return getNode(Opcode, VT, Ops[0], Ops[1], Ops[2]); 3611 default: break; 3612 } 3613 3614 switch (Opcode) { 3615 default: break; 3616 case ISD::SELECT_CC: { 3617 assert(NumOps == 5 && "SELECT_CC takes 5 operands!"); 3618 assert(Ops[0].getValueType() == Ops[1].getValueType() && 3619 "LHS and RHS of condition must have same type!"); 3620 assert(Ops[2].getValueType() == Ops[3].getValueType() && 3621 "True and False arms of SelectCC must have same type!"); 3622 assert(Ops[2].getValueType() == VT && 3623 "select_cc node must be of same type as true and false value!"); 3624 break; 3625 } 3626 case ISD::BR_CC: { 3627 assert(NumOps == 5 && "BR_CC takes 5 operands!"); 3628 assert(Ops[2].getValueType() == Ops[3].getValueType() && 3629 "LHS/RHS of comparison should match types!"); 3630 break; 3631 } 3632 } 3633 3634 // Memoize nodes. 3635 SDNode *N; 3636 SDVTList VTs = getVTList(VT); 3637 if (VT != MVT::Flag) { 3638 FoldingSetNodeID ID; 3639 AddNodeIDNode(ID, Opcode, VTs, Ops, NumOps); 3640 void *IP = 0; 3641 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3642 return SDValue(E, 0); 3643 N = NodeAllocator.Allocate<SDNode>(); 3644 new (N) SDNode(Opcode, VTs, Ops, NumOps); 3645 CSEMap.InsertNode(N, IP); 3646 } else { 3647 N = NodeAllocator.Allocate<SDNode>(); 3648 new (N) SDNode(Opcode, VTs, Ops, NumOps); 3649 } 3650 AllNodes.push_back(N); 3651#ifndef NDEBUG 3652 VerifyNode(N); 3653#endif 3654 return SDValue(N, 0); 3655} 3656 3657SDValue SelectionDAG::getNode(unsigned Opcode, 3658 const std::vector<MVT> &ResultTys, 3659 const SDValue *Ops, unsigned NumOps) { 3660 return getNode(Opcode, getNodeValueTypes(ResultTys), ResultTys.size(), 3661 Ops, NumOps); 3662} 3663 3664SDValue SelectionDAG::getNode(unsigned Opcode, 3665 const MVT *VTs, unsigned NumVTs, 3666 const SDValue *Ops, unsigned NumOps) { 3667 if (NumVTs == 1) 3668 return getNode(Opcode, VTs[0], Ops, NumOps); 3669 return getNode(Opcode, makeVTList(VTs, NumVTs), Ops, NumOps); 3670} 3671 3672SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, 3673 const SDValue *Ops, unsigned NumOps) { 3674 if (VTList.NumVTs == 1) 3675 return getNode(Opcode, VTList.VTs[0], Ops, NumOps); 3676 3677 switch (Opcode) { 3678 // FIXME: figure out how to safely handle things like 3679 // int foo(int x) { return 1 << (x & 255); } 3680 // int bar() { return foo(256); } 3681#if 0 3682 case ISD::SRA_PARTS: 3683 case ISD::SRL_PARTS: 3684 case ISD::SHL_PARTS: 3685 if (N3.getOpcode() == ISD::SIGN_EXTEND_INREG && 3686 cast<VTSDNode>(N3.getOperand(1))->getVT() != MVT::i1) 3687 return getNode(Opcode, VT, N1, N2, N3.getOperand(0)); 3688 else if (N3.getOpcode() == ISD::AND) 3689 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(N3.getOperand(1))) { 3690 // If the and is only masking out bits that cannot effect the shift, 3691 // eliminate the and. 3692 unsigned NumBits = VT.getSizeInBits()*2; 3693 if ((AndRHS->getValue() & (NumBits-1)) == NumBits-1) 3694 return getNode(Opcode, VT, N1, N2, N3.getOperand(0)); 3695 } 3696 break; 3697#endif 3698 } 3699 3700 // Memoize the node unless it returns a flag. 3701 SDNode *N; 3702 if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) { 3703 FoldingSetNodeID ID; 3704 AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps); 3705 void *IP = 0; 3706 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3707 return SDValue(E, 0); 3708 if (NumOps == 1) { 3709 N = NodeAllocator.Allocate<UnarySDNode>(); 3710 new (N) UnarySDNode(Opcode, VTList, Ops[0]); 3711 } else if (NumOps == 2) { 3712 N = NodeAllocator.Allocate<BinarySDNode>(); 3713 new (N) BinarySDNode(Opcode, VTList, Ops[0], Ops[1]); 3714 } else if (NumOps == 3) { 3715 N = NodeAllocator.Allocate<TernarySDNode>(); 3716 new (N) TernarySDNode(Opcode, VTList, Ops[0], Ops[1], Ops[2]); 3717 } else { 3718 N = NodeAllocator.Allocate<SDNode>(); 3719 new (N) SDNode(Opcode, VTList, Ops, NumOps); 3720 } 3721 CSEMap.InsertNode(N, IP); 3722 } else { 3723 if (NumOps == 1) { 3724 N = NodeAllocator.Allocate<UnarySDNode>(); 3725 new (N) UnarySDNode(Opcode, VTList, Ops[0]); 3726 } else if (NumOps == 2) { 3727 N = NodeAllocator.Allocate<BinarySDNode>(); 3728 new (N) BinarySDNode(Opcode, VTList, Ops[0], Ops[1]); 3729 } else if (NumOps == 3) { 3730 N = NodeAllocator.Allocate<TernarySDNode>(); 3731 new (N) TernarySDNode(Opcode, VTList, Ops[0], Ops[1], Ops[2]); 3732 } else { 3733 N = NodeAllocator.Allocate<SDNode>(); 3734 new (N) SDNode(Opcode, VTList, Ops, NumOps); 3735 } 3736 } 3737 AllNodes.push_back(N); 3738#ifndef NDEBUG 3739 VerifyNode(N); 3740#endif 3741 return SDValue(N, 0); 3742} 3743 3744SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList) { 3745 return getNode(Opcode, VTList, 0, 0); 3746} 3747 3748SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, 3749 SDValue N1) { 3750 SDValue Ops[] = { N1 }; 3751 return getNode(Opcode, VTList, Ops, 1); 3752} 3753 3754SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, 3755 SDValue N1, SDValue N2) { 3756 SDValue Ops[] = { N1, N2 }; 3757 return getNode(Opcode, VTList, Ops, 2); 3758} 3759 3760SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, 3761 SDValue N1, SDValue N2, SDValue N3) { 3762 SDValue Ops[] = { N1, N2, N3 }; 3763 return getNode(Opcode, VTList, Ops, 3); 3764} 3765 3766SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, 3767 SDValue N1, SDValue N2, SDValue N3, 3768 SDValue N4) { 3769 SDValue Ops[] = { N1, N2, N3, N4 }; 3770 return getNode(Opcode, VTList, Ops, 4); 3771} 3772 3773SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, 3774 SDValue N1, SDValue N2, SDValue N3, 3775 SDValue N4, SDValue N5) { 3776 SDValue Ops[] = { N1, N2, N3, N4, N5 }; 3777 return getNode(Opcode, VTList, Ops, 5); 3778} 3779 3780SDVTList SelectionDAG::getVTList(MVT VT) { 3781 return makeVTList(SDNode::getValueTypeList(VT), 1); 3782} 3783 3784SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2) { 3785 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 3786 E = VTList.rend(); I != E; ++I) 3787 if (I->NumVTs == 2 && I->VTs[0] == VT1 && I->VTs[1] == VT2) 3788 return *I; 3789 3790 MVT *Array = Allocator.Allocate<MVT>(2); 3791 Array[0] = VT1; 3792 Array[1] = VT2; 3793 SDVTList Result = makeVTList(Array, 2); 3794 VTList.push_back(Result); 3795 return Result; 3796} 3797 3798SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2, MVT VT3) { 3799 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 3800 E = VTList.rend(); I != E; ++I) 3801 if (I->NumVTs == 3 && I->VTs[0] == VT1 && I->VTs[1] == VT2 && 3802 I->VTs[2] == VT3) 3803 return *I; 3804 3805 MVT *Array = Allocator.Allocate<MVT>(3); 3806 Array[0] = VT1; 3807 Array[1] = VT2; 3808 Array[2] = VT3; 3809 SDVTList Result = makeVTList(Array, 3); 3810 VTList.push_back(Result); 3811 return Result; 3812} 3813 3814SDVTList SelectionDAG::getVTList(const MVT *VTs, unsigned NumVTs) { 3815 switch (NumVTs) { 3816 case 0: assert(0 && "Cannot have nodes without results!"); 3817 case 1: return getVTList(VTs[0]); 3818 case 2: return getVTList(VTs[0], VTs[1]); 3819 case 3: return getVTList(VTs[0], VTs[1], VTs[2]); 3820 default: break; 3821 } 3822 3823 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 3824 E = VTList.rend(); I != E; ++I) { 3825 if (I->NumVTs != NumVTs || VTs[0] != I->VTs[0] || VTs[1] != I->VTs[1]) 3826 continue; 3827 3828 bool NoMatch = false; 3829 for (unsigned i = 2; i != NumVTs; ++i) 3830 if (VTs[i] != I->VTs[i]) { 3831 NoMatch = true; 3832 break; 3833 } 3834 if (!NoMatch) 3835 return *I; 3836 } 3837 3838 MVT *Array = Allocator.Allocate<MVT>(NumVTs); 3839 std::copy(VTs, VTs+NumVTs, Array); 3840 SDVTList Result = makeVTList(Array, NumVTs); 3841 VTList.push_back(Result); 3842 return Result; 3843} 3844 3845 3846/// UpdateNodeOperands - *Mutate* the specified node in-place to have the 3847/// specified operands. If the resultant node already exists in the DAG, 3848/// this does not modify the specified node, instead it returns the node that 3849/// already exists. If the resultant node does not exist in the DAG, the 3850/// input node is returned. As a degenerate case, if you specify the same 3851/// input operands as the node already has, the input node is returned. 3852SDValue SelectionDAG::UpdateNodeOperands(SDValue InN, SDValue Op) { 3853 SDNode *N = InN.getNode(); 3854 assert(N->getNumOperands() == 1 && "Update with wrong number of operands"); 3855 3856 // Check to see if there is no change. 3857 if (Op == N->getOperand(0)) return InN; 3858 3859 // See if the modified node already exists. 3860 void *InsertPos = 0; 3861 if (SDNode *Existing = FindModifiedNodeSlot(N, Op, InsertPos)) 3862 return SDValue(Existing, InN.getResNo()); 3863 3864 // Nope it doesn't. Remove the node from its current place in the maps. 3865 if (InsertPos) 3866 if (!RemoveNodeFromCSEMaps(N)) 3867 InsertPos = 0; 3868 3869 // Now we update the operands. 3870 N->OperandList[0].getVal()->removeUser(0, N); 3871 N->OperandList[0] = Op; 3872 N->OperandList[0].setUser(N); 3873 Op.getNode()->addUser(0, N); 3874 3875 // If this gets put into a CSE map, add it. 3876 if (InsertPos) CSEMap.InsertNode(N, InsertPos); 3877 return InN; 3878} 3879 3880SDValue SelectionDAG:: 3881UpdateNodeOperands(SDValue InN, SDValue Op1, SDValue Op2) { 3882 SDNode *N = InN.getNode(); 3883 assert(N->getNumOperands() == 2 && "Update with wrong number of operands"); 3884 3885 // Check to see if there is no change. 3886 if (Op1 == N->getOperand(0) && Op2 == N->getOperand(1)) 3887 return InN; // No operands changed, just return the input node. 3888 3889 // See if the modified node already exists. 3890 void *InsertPos = 0; 3891 if (SDNode *Existing = FindModifiedNodeSlot(N, Op1, Op2, InsertPos)) 3892 return SDValue(Existing, InN.getResNo()); 3893 3894 // Nope it doesn't. Remove the node from its current place in the maps. 3895 if (InsertPos) 3896 if (!RemoveNodeFromCSEMaps(N)) 3897 InsertPos = 0; 3898 3899 // Now we update the operands. 3900 if (N->OperandList[0] != Op1) { 3901 N->OperandList[0].getVal()->removeUser(0, N); 3902 N->OperandList[0] = Op1; 3903 N->OperandList[0].setUser(N); 3904 Op1.getNode()->addUser(0, N); 3905 } 3906 if (N->OperandList[1] != Op2) { 3907 N->OperandList[1].getVal()->removeUser(1, N); 3908 N->OperandList[1] = Op2; 3909 N->OperandList[1].setUser(N); 3910 Op2.getNode()->addUser(1, N); 3911 } 3912 3913 // If this gets put into a CSE map, add it. 3914 if (InsertPos) CSEMap.InsertNode(N, InsertPos); 3915 return InN; 3916} 3917 3918SDValue SelectionDAG:: 3919UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, SDValue Op3) { 3920 SDValue Ops[] = { Op1, Op2, Op3 }; 3921 return UpdateNodeOperands(N, Ops, 3); 3922} 3923 3924SDValue SelectionDAG:: 3925UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, 3926 SDValue Op3, SDValue Op4) { 3927 SDValue Ops[] = { Op1, Op2, Op3, Op4 }; 3928 return UpdateNodeOperands(N, Ops, 4); 3929} 3930 3931SDValue SelectionDAG:: 3932UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, 3933 SDValue Op3, SDValue Op4, SDValue Op5) { 3934 SDValue Ops[] = { Op1, Op2, Op3, Op4, Op5 }; 3935 return UpdateNodeOperands(N, Ops, 5); 3936} 3937 3938SDValue SelectionDAG:: 3939UpdateNodeOperands(SDValue InN, const SDValue *Ops, unsigned NumOps) { 3940 SDNode *N = InN.getNode(); 3941 assert(N->getNumOperands() == NumOps && 3942 "Update with wrong number of operands"); 3943 3944 // Check to see if there is no change. 3945 bool AnyChange = false; 3946 for (unsigned i = 0; i != NumOps; ++i) { 3947 if (Ops[i] != N->getOperand(i)) { 3948 AnyChange = true; 3949 break; 3950 } 3951 } 3952 3953 // No operands changed, just return the input node. 3954 if (!AnyChange) return InN; 3955 3956 // See if the modified node already exists. 3957 void *InsertPos = 0; 3958 if (SDNode *Existing = FindModifiedNodeSlot(N, Ops, NumOps, InsertPos)) 3959 return SDValue(Existing, InN.getResNo()); 3960 3961 // Nope it doesn't. Remove the node from its current place in the maps. 3962 if (InsertPos) 3963 if (!RemoveNodeFromCSEMaps(N)) 3964 InsertPos = 0; 3965 3966 // Now we update the operands. 3967 for (unsigned i = 0; i != NumOps; ++i) { 3968 if (N->OperandList[i] != Ops[i]) { 3969 N->OperandList[i].getVal()->removeUser(i, N); 3970 N->OperandList[i] = Ops[i]; 3971 N->OperandList[i].setUser(N); 3972 Ops[i].getNode()->addUser(i, N); 3973 } 3974 } 3975 3976 // If this gets put into a CSE map, add it. 3977 if (InsertPos) CSEMap.InsertNode(N, InsertPos); 3978 return InN; 3979} 3980 3981/// DropOperands - Release the operands and set this node to have 3982/// zero operands. 3983void SDNode::DropOperands() { 3984 // Unlike the code in MorphNodeTo that does this, we don't need to 3985 // watch for dead nodes here. 3986 for (op_iterator I = op_begin(), E = op_end(); I != E; ++I) 3987 I->getVal()->removeUser(std::distance(op_begin(), I), this); 3988 3989 NumOperands = 0; 3990} 3991 3992/// SelectNodeTo - These are wrappers around MorphNodeTo that accept a 3993/// machine opcode. 3994/// 3995SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 3996 MVT VT) { 3997 SDVTList VTs = getVTList(VT); 3998 return SelectNodeTo(N, MachineOpc, VTs, 0, 0); 3999} 4000 4001SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4002 MVT VT, SDValue Op1) { 4003 SDVTList VTs = getVTList(VT); 4004 SDValue Ops[] = { Op1 }; 4005 return SelectNodeTo(N, MachineOpc, VTs, Ops, 1); 4006} 4007 4008SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4009 MVT VT, SDValue Op1, 4010 SDValue Op2) { 4011 SDVTList VTs = getVTList(VT); 4012 SDValue Ops[] = { Op1, Op2 }; 4013 return SelectNodeTo(N, MachineOpc, VTs, Ops, 2); 4014} 4015 4016SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4017 MVT VT, SDValue Op1, 4018 SDValue Op2, SDValue Op3) { 4019 SDVTList VTs = getVTList(VT); 4020 SDValue Ops[] = { Op1, Op2, Op3 }; 4021 return SelectNodeTo(N, MachineOpc, VTs, Ops, 3); 4022} 4023 4024SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4025 MVT VT, const SDValue *Ops, 4026 unsigned NumOps) { 4027 SDVTList VTs = getVTList(VT); 4028 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 4029} 4030 4031SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4032 MVT VT1, MVT VT2, const SDValue *Ops, 4033 unsigned NumOps) { 4034 SDVTList VTs = getVTList(VT1, VT2); 4035 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 4036} 4037 4038SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4039 MVT VT1, MVT VT2) { 4040 SDVTList VTs = getVTList(VT1, VT2); 4041 return SelectNodeTo(N, MachineOpc, VTs, (SDValue *)0, 0); 4042} 4043 4044SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4045 MVT VT1, MVT VT2, MVT VT3, 4046 const SDValue *Ops, unsigned NumOps) { 4047 SDVTList VTs = getVTList(VT1, VT2, VT3); 4048 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 4049} 4050 4051SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4052 MVT VT1, MVT VT2, 4053 SDValue Op1) { 4054 SDVTList VTs = getVTList(VT1, VT2); 4055 SDValue Ops[] = { Op1 }; 4056 return SelectNodeTo(N, MachineOpc, VTs, Ops, 1); 4057} 4058 4059SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4060 MVT VT1, MVT VT2, 4061 SDValue Op1, SDValue Op2) { 4062 SDVTList VTs = getVTList(VT1, VT2); 4063 SDValue Ops[] = { Op1, Op2 }; 4064 return SelectNodeTo(N, MachineOpc, VTs, Ops, 2); 4065} 4066 4067SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4068 MVT VT1, MVT VT2, 4069 SDValue Op1, SDValue Op2, 4070 SDValue Op3) { 4071 SDVTList VTs = getVTList(VT1, VT2); 4072 SDValue Ops[] = { Op1, Op2, Op3 }; 4073 return SelectNodeTo(N, MachineOpc, VTs, Ops, 3); 4074} 4075 4076SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4077 SDVTList VTs, const SDValue *Ops, 4078 unsigned NumOps) { 4079 return MorphNodeTo(N, ~MachineOpc, VTs, Ops, NumOps); 4080} 4081 4082SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4083 MVT VT) { 4084 SDVTList VTs = getVTList(VT); 4085 return MorphNodeTo(N, Opc, VTs, 0, 0); 4086} 4087 4088SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4089 MVT VT, SDValue Op1) { 4090 SDVTList VTs = getVTList(VT); 4091 SDValue Ops[] = { Op1 }; 4092 return MorphNodeTo(N, Opc, VTs, Ops, 1); 4093} 4094 4095SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4096 MVT VT, SDValue Op1, 4097 SDValue Op2) { 4098 SDVTList VTs = getVTList(VT); 4099 SDValue Ops[] = { Op1, Op2 }; 4100 return MorphNodeTo(N, Opc, VTs, Ops, 2); 4101} 4102 4103SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4104 MVT VT, SDValue Op1, 4105 SDValue Op2, SDValue Op3) { 4106 SDVTList VTs = getVTList(VT); 4107 SDValue Ops[] = { Op1, Op2, Op3 }; 4108 return MorphNodeTo(N, Opc, VTs, Ops, 3); 4109} 4110 4111SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4112 MVT VT, const SDValue *Ops, 4113 unsigned NumOps) { 4114 SDVTList VTs = getVTList(VT); 4115 return MorphNodeTo(N, Opc, VTs, Ops, NumOps); 4116} 4117 4118SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4119 MVT VT1, MVT VT2, const SDValue *Ops, 4120 unsigned NumOps) { 4121 SDVTList VTs = getVTList(VT1, VT2); 4122 return MorphNodeTo(N, Opc, VTs, Ops, NumOps); 4123} 4124 4125SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4126 MVT VT1, MVT VT2) { 4127 SDVTList VTs = getVTList(VT1, VT2); 4128 return MorphNodeTo(N, Opc, VTs, (SDValue *)0, 0); 4129} 4130 4131SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4132 MVT VT1, MVT VT2, MVT VT3, 4133 const SDValue *Ops, unsigned NumOps) { 4134 SDVTList VTs = getVTList(VT1, VT2, VT3); 4135 return MorphNodeTo(N, Opc, VTs, Ops, NumOps); 4136} 4137 4138SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4139 MVT VT1, MVT VT2, 4140 SDValue Op1) { 4141 SDVTList VTs = getVTList(VT1, VT2); 4142 SDValue Ops[] = { Op1 }; 4143 return MorphNodeTo(N, Opc, VTs, Ops, 1); 4144} 4145 4146SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4147 MVT VT1, MVT VT2, 4148 SDValue Op1, SDValue Op2) { 4149 SDVTList VTs = getVTList(VT1, VT2); 4150 SDValue Ops[] = { Op1, Op2 }; 4151 return MorphNodeTo(N, Opc, VTs, Ops, 2); 4152} 4153 4154SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4155 MVT VT1, MVT VT2, 4156 SDValue Op1, SDValue Op2, 4157 SDValue Op3) { 4158 SDVTList VTs = getVTList(VT1, VT2); 4159 SDValue Ops[] = { Op1, Op2, Op3 }; 4160 return MorphNodeTo(N, Opc, VTs, Ops, 3); 4161} 4162 4163/// MorphNodeTo - These *mutate* the specified node to have the specified 4164/// return type, opcode, and operands. 4165/// 4166/// Note that MorphNodeTo returns the resultant node. If there is already a 4167/// node of the specified opcode and operands, it returns that node instead of 4168/// the current one. 4169/// 4170/// Using MorphNodeTo is faster than creating a new node and swapping it in 4171/// with ReplaceAllUsesWith both because it often avoids allocating a new 4172/// node, and because it doesn't require CSE recalculation for any of 4173/// the node's users. 4174/// 4175SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4176 SDVTList VTs, const SDValue *Ops, 4177 unsigned NumOps) { 4178 // If an identical node already exists, use it. 4179 void *IP = 0; 4180 if (VTs.VTs[VTs.NumVTs-1] != MVT::Flag) { 4181 FoldingSetNodeID ID; 4182 AddNodeIDNode(ID, Opc, VTs, Ops, NumOps); 4183 if (SDNode *ON = CSEMap.FindNodeOrInsertPos(ID, IP)) 4184 return ON; 4185 } 4186 4187 if (!RemoveNodeFromCSEMaps(N)) 4188 IP = 0; 4189 4190 // Start the morphing. 4191 N->NodeType = Opc; 4192 N->ValueList = VTs.VTs; 4193 N->NumValues = VTs.NumVTs; 4194 4195 // Clear the operands list, updating used nodes to remove this from their 4196 // use list. Keep track of any operands that become dead as a result. 4197 SmallPtrSet<SDNode*, 16> DeadNodeSet; 4198 for (SDNode::op_iterator B = N->op_begin(), I = B, E = N->op_end(); 4199 I != E; ++I) { 4200 SDNode *Used = I->getVal(); 4201 Used->removeUser(std::distance(B, I), N); 4202 if (Used->use_empty()) 4203 DeadNodeSet.insert(Used); 4204 } 4205 4206 // If NumOps is larger than the # of operands we currently have, reallocate 4207 // the operand list. 4208 if (NumOps > N->NumOperands) { 4209 if (N->OperandsNeedDelete) 4210 delete[] N->OperandList; 4211 4212 if (N->isMachineOpcode()) { 4213 // We're creating a final node that will live unmorphed for the 4214 // remainder of the current SelectionDAG iteration, so we can allocate 4215 // the operands directly out of a pool with no recycling metadata. 4216 N->OperandList = OperandAllocator.Allocate<SDUse>(NumOps); 4217 N->OperandsNeedDelete = false; 4218 } else { 4219 N->OperandList = new SDUse[NumOps]; 4220 N->OperandsNeedDelete = true; 4221 } 4222 } 4223 4224 // Assign the new operands. 4225 N->NumOperands = NumOps; 4226 for (unsigned i = 0, e = NumOps; i != e; ++i) { 4227 N->OperandList[i] = Ops[i]; 4228 N->OperandList[i].setUser(N); 4229 SDNode *ToUse = N->OperandList[i].getVal(); 4230 ToUse->addUser(i, N); 4231 } 4232 4233 // Delete any nodes that are still dead after adding the uses for the 4234 // new operands. 4235 SmallVector<SDNode *, 16> DeadNodes; 4236 for (SmallPtrSet<SDNode *, 16>::iterator I = DeadNodeSet.begin(), 4237 E = DeadNodeSet.end(); I != E; ++I) 4238 if ((*I)->use_empty()) 4239 DeadNodes.push_back(*I); 4240 RemoveDeadNodes(DeadNodes); 4241 4242 if (IP) 4243 CSEMap.InsertNode(N, IP); // Memoize the new node. 4244 return N; 4245} 4246 4247 4248/// getTargetNode - These are used for target selectors to create a new node 4249/// with specified return type(s), target opcode, and operands. 4250/// 4251/// Note that getTargetNode returns the resultant node. If there is already a 4252/// node of the specified opcode and operands, it returns that node instead of 4253/// the current one. 4254SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT) { 4255 return getNode(~Opcode, VT).getNode(); 4256} 4257SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT, SDValue Op1) { 4258 return getNode(~Opcode, VT, Op1).getNode(); 4259} 4260SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT, 4261 SDValue Op1, SDValue Op2) { 4262 return getNode(~Opcode, VT, Op1, Op2).getNode(); 4263} 4264SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT, 4265 SDValue Op1, SDValue Op2, 4266 SDValue Op3) { 4267 return getNode(~Opcode, VT, Op1, Op2, Op3).getNode(); 4268} 4269SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT, 4270 const SDValue *Ops, unsigned NumOps) { 4271 return getNode(~Opcode, VT, Ops, NumOps).getNode(); 4272} 4273SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2) { 4274 const MVT *VTs = getNodeValueTypes(VT1, VT2); 4275 SDValue Op; 4276 return getNode(~Opcode, VTs, 2, &Op, 0).getNode(); 4277} 4278SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, 4279 MVT VT2, SDValue Op1) { 4280 const MVT *VTs = getNodeValueTypes(VT1, VT2); 4281 return getNode(~Opcode, VTs, 2, &Op1, 1).getNode(); 4282} 4283SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, 4284 MVT VT2, SDValue Op1, 4285 SDValue Op2) { 4286 const MVT *VTs = getNodeValueTypes(VT1, VT2); 4287 SDValue Ops[] = { Op1, Op2 }; 4288 return getNode(~Opcode, VTs, 2, Ops, 2).getNode(); 4289} 4290SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, 4291 MVT VT2, SDValue Op1, 4292 SDValue Op2, SDValue Op3) { 4293 const MVT *VTs = getNodeValueTypes(VT1, VT2); 4294 SDValue Ops[] = { Op1, Op2, Op3 }; 4295 return getNode(~Opcode, VTs, 2, Ops, 3).getNode(); 4296} 4297SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, 4298 const SDValue *Ops, unsigned NumOps) { 4299 const MVT *VTs = getNodeValueTypes(VT1, VT2); 4300 return getNode(~Opcode, VTs, 2, Ops, NumOps).getNode(); 4301} 4302SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3, 4303 SDValue Op1, SDValue Op2) { 4304 const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3); 4305 SDValue Ops[] = { Op1, Op2 }; 4306 return getNode(~Opcode, VTs, 3, Ops, 2).getNode(); 4307} 4308SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3, 4309 SDValue Op1, SDValue Op2, 4310 SDValue Op3) { 4311 const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3); 4312 SDValue Ops[] = { Op1, Op2, Op3 }; 4313 return getNode(~Opcode, VTs, 3, Ops, 3).getNode(); 4314} 4315SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3, 4316 const SDValue *Ops, unsigned NumOps) { 4317 const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3); 4318 return getNode(~Opcode, VTs, 3, Ops, NumOps).getNode(); 4319} 4320SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, 4321 MVT VT2, MVT VT3, MVT VT4, 4322 const SDValue *Ops, unsigned NumOps) { 4323 std::vector<MVT> VTList; 4324 VTList.push_back(VT1); 4325 VTList.push_back(VT2); 4326 VTList.push_back(VT3); 4327 VTList.push_back(VT4); 4328 const MVT *VTs = getNodeValueTypes(VTList); 4329 return getNode(~Opcode, VTs, 4, Ops, NumOps).getNode(); 4330} 4331SDNode *SelectionDAG::getTargetNode(unsigned Opcode, 4332 const std::vector<MVT> &ResultTys, 4333 const SDValue *Ops, unsigned NumOps) { 4334 const MVT *VTs = getNodeValueTypes(ResultTys); 4335 return getNode(~Opcode, VTs, ResultTys.size(), 4336 Ops, NumOps).getNode(); 4337} 4338 4339/// getNodeIfExists - Get the specified node if it's already available, or 4340/// else return NULL. 4341SDNode *SelectionDAG::getNodeIfExists(unsigned Opcode, SDVTList VTList, 4342 const SDValue *Ops, unsigned NumOps) { 4343 if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) { 4344 FoldingSetNodeID ID; 4345 AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps); 4346 void *IP = 0; 4347 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 4348 return E; 4349 } 4350 return NULL; 4351} 4352 4353 4354/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. 4355/// This can cause recursive merging of nodes in the DAG. 4356/// 4357/// This version assumes From has a single result value. 4358/// 4359void SelectionDAG::ReplaceAllUsesWith(SDValue FromN, SDValue To, 4360 DAGUpdateListener *UpdateListener) { 4361 SDNode *From = FromN.getNode(); 4362 assert(From->getNumValues() == 1 && FromN.getResNo() == 0 && 4363 "Cannot replace with this method!"); 4364 assert(From != To.getNode() && "Cannot replace uses of with self"); 4365 4366 while (!From->use_empty()) { 4367 SDNode::use_iterator UI = From->use_begin(); 4368 SDNode *U = *UI; 4369 4370 // This node is about to morph, remove its old self from the CSE maps. 4371 RemoveNodeFromCSEMaps(U); 4372 int operandNum = 0; 4373 for (SDNode::op_iterator I = U->op_begin(), E = U->op_end(); 4374 I != E; ++I, ++operandNum) 4375 if (I->getVal() == From) { 4376 From->removeUser(operandNum, U); 4377 *I = To; 4378 I->setUser(U); 4379 To.getNode()->addUser(operandNum, U); 4380 } 4381 4382 // Now that we have modified U, add it back to the CSE maps. If it already 4383 // exists there, recursively merge the results together. 4384 if (SDNode *Existing = AddNonLeafNodeToCSEMaps(U)) { 4385 ReplaceAllUsesWith(U, Existing, UpdateListener); 4386 // U is now dead. Inform the listener if it exists and delete it. 4387 if (UpdateListener) 4388 UpdateListener->NodeDeleted(U, Existing); 4389 DeleteNodeNotInCSEMaps(U); 4390 } else { 4391 // If the node doesn't already exist, we updated it. Inform a listener if 4392 // it exists. 4393 if (UpdateListener) 4394 UpdateListener->NodeUpdated(U); 4395 } 4396 } 4397} 4398 4399/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. 4400/// This can cause recursive merging of nodes in the DAG. 4401/// 4402/// This version assumes From/To have matching types and numbers of result 4403/// values. 4404/// 4405void SelectionDAG::ReplaceAllUsesWith(SDNode *From, SDNode *To, 4406 DAGUpdateListener *UpdateListener) { 4407 assert(From->getVTList().VTs == To->getVTList().VTs && 4408 From->getNumValues() == To->getNumValues() && 4409 "Cannot use this version of ReplaceAllUsesWith!"); 4410 4411 // Handle the trivial case. 4412 if (From == To) 4413 return; 4414 4415 while (!From->use_empty()) { 4416 SDNode::use_iterator UI = From->use_begin(); 4417 SDNode *U = *UI; 4418 4419 // This node is about to morph, remove its old self from the CSE maps. 4420 RemoveNodeFromCSEMaps(U); 4421 int operandNum = 0; 4422 for (SDNode::op_iterator I = U->op_begin(), E = U->op_end(); 4423 I != E; ++I, ++operandNum) 4424 if (I->getVal() == From) { 4425 From->removeUser(operandNum, U); 4426 I->getSDValue().setNode(To); 4427 To->addUser(operandNum, U); 4428 } 4429 4430 // Now that we have modified U, add it back to the CSE maps. If it already 4431 // exists there, recursively merge the results together. 4432 if (SDNode *Existing = AddNonLeafNodeToCSEMaps(U)) { 4433 ReplaceAllUsesWith(U, Existing, UpdateListener); 4434 // U is now dead. Inform the listener if it exists and delete it. 4435 if (UpdateListener) 4436 UpdateListener->NodeDeleted(U, Existing); 4437 DeleteNodeNotInCSEMaps(U); 4438 } else { 4439 // If the node doesn't already exist, we updated it. Inform a listener if 4440 // it exists. 4441 if (UpdateListener) 4442 UpdateListener->NodeUpdated(U); 4443 } 4444 } 4445} 4446 4447/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. 4448/// This can cause recursive merging of nodes in the DAG. 4449/// 4450/// This version can replace From with any result values. To must match the 4451/// number and types of values returned by From. 4452void SelectionDAG::ReplaceAllUsesWith(SDNode *From, 4453 const SDValue *To, 4454 DAGUpdateListener *UpdateListener) { 4455 if (From->getNumValues() == 1) // Handle the simple case efficiently. 4456 return ReplaceAllUsesWith(SDValue(From, 0), To[0], UpdateListener); 4457 4458 while (!From->use_empty()) { 4459 SDNode::use_iterator UI = From->use_begin(); 4460 SDNode *U = *UI; 4461 4462 // This node is about to morph, remove its old self from the CSE maps. 4463 RemoveNodeFromCSEMaps(U); 4464 int operandNum = 0; 4465 for (SDNode::op_iterator I = U->op_begin(), E = U->op_end(); 4466 I != E; ++I, ++operandNum) 4467 if (I->getVal() == From) { 4468 const SDValue &ToOp = To[I->getSDValue().getResNo()]; 4469 From->removeUser(operandNum, U); 4470 *I = ToOp; 4471 I->setUser(U); 4472 ToOp.getNode()->addUser(operandNum, U); 4473 } 4474 4475 // Now that we have modified U, add it back to the CSE maps. If it already 4476 // exists there, recursively merge the results together. 4477 if (SDNode *Existing = AddNonLeafNodeToCSEMaps(U)) { 4478 ReplaceAllUsesWith(U, Existing, UpdateListener); 4479 // U is now dead. Inform the listener if it exists and delete it. 4480 if (UpdateListener) 4481 UpdateListener->NodeDeleted(U, Existing); 4482 DeleteNodeNotInCSEMaps(U); 4483 } else { 4484 // If the node doesn't already exist, we updated it. Inform a listener if 4485 // it exists. 4486 if (UpdateListener) 4487 UpdateListener->NodeUpdated(U); 4488 } 4489 } 4490} 4491 4492/// ReplaceAllUsesOfValueWith - Replace any uses of From with To, leaving 4493/// uses of other values produced by From.getVal() alone. The Deleted vector is 4494/// handled the same way as for ReplaceAllUsesWith. 4495void SelectionDAG::ReplaceAllUsesOfValueWith(SDValue From, SDValue To, 4496 DAGUpdateListener *UpdateListener){ 4497 // Handle the really simple, really trivial case efficiently. 4498 if (From == To) return; 4499 4500 // Handle the simple, trivial, case efficiently. 4501 if (From.getNode()->getNumValues() == 1) { 4502 ReplaceAllUsesWith(From, To, UpdateListener); 4503 return; 4504 } 4505 4506 // Get all of the users of From.getNode(). We want these in a nice, 4507 // deterministically ordered and uniqued set, so we use a SmallSetVector. 4508 SmallSetVector<SDNode*, 16> Users(From.getNode()->use_begin(), From.getNode()->use_end()); 4509 4510 while (!Users.empty()) { 4511 // We know that this user uses some value of From. If it is the right 4512 // value, update it. 4513 SDNode *User = Users.back(); 4514 Users.pop_back(); 4515 4516 // Scan for an operand that matches From. 4517 SDNode::op_iterator Op = User->op_begin(), E = User->op_end(); 4518 for (; Op != E; ++Op) 4519 if (*Op == From) break; 4520 4521 // If there are no matches, the user must use some other result of From. 4522 if (Op == E) continue; 4523 4524 // Okay, we know this user needs to be updated. Remove its old self 4525 // from the CSE maps. 4526 RemoveNodeFromCSEMaps(User); 4527 4528 // Update all operands that match "From" in case there are multiple uses. 4529 for (; Op != E; ++Op) { 4530 if (*Op == From) { 4531 From.getNode()->removeUser(Op-User->op_begin(), User); 4532 *Op = To; 4533 Op->setUser(User); 4534 To.getNode()->addUser(Op-User->op_begin(), User); 4535 } 4536 } 4537 4538 // Now that we have modified User, add it back to the CSE maps. If it 4539 // already exists there, recursively merge the results together. 4540 SDNode *Existing = AddNonLeafNodeToCSEMaps(User); 4541 if (!Existing) { 4542 if (UpdateListener) UpdateListener->NodeUpdated(User); 4543 continue; // Continue on to next user. 4544 } 4545 4546 // If there was already an existing matching node, use ReplaceAllUsesWith 4547 // to replace the dead one with the existing one. This can cause 4548 // recursive merging of other unrelated nodes down the line. 4549 ReplaceAllUsesWith(User, Existing, UpdateListener); 4550 4551 // User is now dead. Notify a listener if present. 4552 if (UpdateListener) UpdateListener->NodeDeleted(User, Existing); 4553 DeleteNodeNotInCSEMaps(User); 4554 } 4555} 4556 4557/// ReplaceAllUsesOfValuesWith - Replace any uses of From with To, leaving 4558/// uses of other values produced by From.getVal() alone. The same value may 4559/// appear in both the From and To list. The Deleted vector is 4560/// handled the same way as for ReplaceAllUsesWith. 4561void SelectionDAG::ReplaceAllUsesOfValuesWith(const SDValue *From, 4562 const SDValue *To, 4563 unsigned Num, 4564 DAGUpdateListener *UpdateListener){ 4565 // Handle the simple, trivial case efficiently. 4566 if (Num == 1) 4567 return ReplaceAllUsesOfValueWith(*From, *To, UpdateListener); 4568 4569 SmallVector<std::pair<SDNode *, unsigned>, 16> Users; 4570 for (unsigned i = 0; i != Num; ++i) 4571 for (SDNode::use_iterator UI = From[i].getNode()->use_begin(), 4572 E = From[i].getNode()->use_end(); UI != E; ++UI) 4573 Users.push_back(std::make_pair(*UI, i)); 4574 4575 while (!Users.empty()) { 4576 // We know that this user uses some value of From. If it is the right 4577 // value, update it. 4578 SDNode *User = Users.back().first; 4579 unsigned i = Users.back().second; 4580 Users.pop_back(); 4581 4582 // Scan for an operand that matches From. 4583 SDNode::op_iterator Op = User->op_begin(), E = User->op_end(); 4584 for (; Op != E; ++Op) 4585 if (*Op == From[i]) break; 4586 4587 // If there are no matches, the user must use some other result of From. 4588 if (Op == E) continue; 4589 4590 // Okay, we know this user needs to be updated. Remove its old self 4591 // from the CSE maps. 4592 RemoveNodeFromCSEMaps(User); 4593 4594 // Update all operands that match "From" in case there are multiple uses. 4595 for (; Op != E; ++Op) { 4596 if (*Op == From[i]) { 4597 From[i].getNode()->removeUser(Op-User->op_begin(), User); 4598 *Op = To[i]; 4599 Op->setUser(User); 4600 To[i].getNode()->addUser(Op-User->op_begin(), User); 4601 } 4602 } 4603 4604 // Now that we have modified User, add it back to the CSE maps. If it 4605 // already exists there, recursively merge the results together. 4606 SDNode *Existing = AddNonLeafNodeToCSEMaps(User); 4607 if (!Existing) { 4608 if (UpdateListener) UpdateListener->NodeUpdated(User); 4609 continue; // Continue on to next user. 4610 } 4611 4612 // If there was already an existing matching node, use ReplaceAllUsesWith 4613 // to replace the dead one with the existing one. This can cause 4614 // recursive merging of other unrelated nodes down the line. 4615 ReplaceAllUsesWith(User, Existing, UpdateListener); 4616 4617 // User is now dead. Notify a listener if present. 4618 if (UpdateListener) UpdateListener->NodeDeleted(User, Existing); 4619 DeleteNodeNotInCSEMaps(User); 4620 } 4621} 4622 4623/// AssignTopologicalOrder - Assign a unique node id for each node in the DAG 4624/// based on their topological order. It returns the maximum id and a vector 4625/// of the SDNodes* in assigned order by reference. 4626unsigned SelectionDAG::AssignTopologicalOrder() { 4627 4628 unsigned DAGSize = 0; 4629 4630 // SortedPos tracks the progress of the algorithm. Nodes before it are 4631 // sorted, nodes after it are unsorted. When the algorithm completes 4632 // it is at the end of the list. 4633 allnodes_iterator SortedPos = allnodes_begin(); 4634 4635 // Visit all the nodes. Add nodes with no operands to the TopOrder result 4636 // array immediately. Annotate nodes that do have operands with their 4637 // operand count. Before we do this, the Node Id fields of the nodes 4638 // may contain arbitrary values. After, the Node Id fields for nodes 4639 // before SortedPos will contain the topological sort index, and the 4640 // Node Id fields for nodes At SortedPos and after will contain the 4641 // count of outstanding operands. 4642 for (allnodes_iterator I = allnodes_begin(),E = allnodes_end(); I != E; ) { 4643 SDNode *N = I++; 4644 unsigned Degree = N->getNumOperands(); 4645 if (Degree == 0) { 4646 // A node with no uses, add it to the result array immediately. 4647 N->setNodeId(DAGSize++); 4648 allnodes_iterator Q = N; 4649 if (Q != SortedPos) 4650 SortedPos = AllNodes.insert(SortedPos, AllNodes.remove(Q)); 4651 ++SortedPos; 4652 } else { 4653 // Temporarily use the Node Id as scratch space for the degree count. 4654 N->setNodeId(Degree); 4655 } 4656 } 4657 4658 // Visit all the nodes. As we iterate, moves nodes into sorted order, 4659 // such that by the time the end is reached all nodes will be sorted. 4660 for (allnodes_iterator I = allnodes_begin(),E = allnodes_end(); I != E; ++I) { 4661 SDNode *N = I; 4662 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 4663 UI != UE; ++UI) { 4664 SDNode *P = *UI; 4665 unsigned Degree = P->getNodeId(); 4666 --Degree; 4667 if (Degree == 0) { 4668 // All of P's operands are sorted, so P may sorted now. 4669 P->setNodeId(DAGSize++); 4670 if (P != SortedPos) 4671 SortedPos = AllNodes.insert(SortedPos, AllNodes.remove(P)); 4672 ++SortedPos; 4673 } else { 4674 // Update P's outstanding operand count. 4675 P->setNodeId(Degree); 4676 } 4677 } 4678 } 4679 4680 assert(SortedPos == AllNodes.end() && 4681 "Topological sort incomplete!"); 4682 assert(AllNodes.front().getOpcode() == ISD::EntryToken && 4683 "First node in topological sort is not the entry token!"); 4684 assert(AllNodes.front().getNodeId() == 0 && 4685 "First node in topological sort has non-zero id!"); 4686 assert(AllNodes.front().getNumOperands() == 0 && 4687 "First node in topological sort has operands!"); 4688 assert(AllNodes.back().getNodeId() == (int)DAGSize-1 && 4689 "Last node in topologic sort has unexpected id!"); 4690 assert(AllNodes.back().use_empty() && 4691 "Last node in topologic sort has users!"); 4692 assert(DAGSize == allnodes_size() && "TopOrder result count mismatch!"); 4693 return DAGSize; 4694} 4695 4696 4697 4698//===----------------------------------------------------------------------===// 4699// SDNode Class 4700//===----------------------------------------------------------------------===// 4701 4702// Out-of-line virtual method to give class a home. 4703void SDNode::ANCHOR() {} 4704void UnarySDNode::ANCHOR() {} 4705void BinarySDNode::ANCHOR() {} 4706void TernarySDNode::ANCHOR() {} 4707void HandleSDNode::ANCHOR() {} 4708void ConstantSDNode::ANCHOR() {} 4709void ConstantFPSDNode::ANCHOR() {} 4710void GlobalAddressSDNode::ANCHOR() {} 4711void FrameIndexSDNode::ANCHOR() {} 4712void JumpTableSDNode::ANCHOR() {} 4713void ConstantPoolSDNode::ANCHOR() {} 4714void BasicBlockSDNode::ANCHOR() {} 4715void SrcValueSDNode::ANCHOR() {} 4716void MemOperandSDNode::ANCHOR() {} 4717void RegisterSDNode::ANCHOR() {} 4718void DbgStopPointSDNode::ANCHOR() {} 4719void LabelSDNode::ANCHOR() {} 4720void ExternalSymbolSDNode::ANCHOR() {} 4721void CondCodeSDNode::ANCHOR() {} 4722void ARG_FLAGSSDNode::ANCHOR() {} 4723void VTSDNode::ANCHOR() {} 4724void MemSDNode::ANCHOR() {} 4725void LoadSDNode::ANCHOR() {} 4726void StoreSDNode::ANCHOR() {} 4727void AtomicSDNode::ANCHOR() {} 4728void MemIntrinsicSDNode::ANCHOR() {} 4729void CallSDNode::ANCHOR() {} 4730 4731HandleSDNode::~HandleSDNode() { 4732 DropOperands(); 4733} 4734 4735GlobalAddressSDNode::GlobalAddressSDNode(bool isTarget, const GlobalValue *GA, 4736 MVT VT, int64_t o) 4737 : SDNode(isa<GlobalVariable>(GA) && 4738 cast<GlobalVariable>(GA)->isThreadLocal() ? 4739 // Thread Local 4740 (isTarget ? ISD::TargetGlobalTLSAddress : ISD::GlobalTLSAddress) : 4741 // Non Thread Local 4742 (isTarget ? ISD::TargetGlobalAddress : ISD::GlobalAddress), 4743 getSDVTList(VT)), Offset(o) { 4744 TheGlobal = const_cast<GlobalValue*>(GA); 4745} 4746 4747MemSDNode::MemSDNode(unsigned Opc, SDVTList VTs, MVT memvt, 4748 const Value *srcValue, int SVO, 4749 unsigned alignment, bool vol) 4750 : SDNode(Opc, VTs), MemoryVT(memvt), SrcValue(srcValue), SVOffset(SVO), 4751 Flags(encodeMemSDNodeFlags(vol, alignment)) { 4752 4753 assert(isPowerOf2_32(alignment) && "Alignment is not a power of 2!"); 4754 assert(getAlignment() == alignment && "Alignment representation error!"); 4755 assert(isVolatile() == vol && "Volatile representation error!"); 4756} 4757 4758MemSDNode::MemSDNode(unsigned Opc, SDVTList VTs, const SDValue *Ops, 4759 unsigned NumOps, MVT memvt, const Value *srcValue, 4760 int SVO, unsigned alignment, bool vol) 4761 : SDNode(Opc, VTs, Ops, NumOps), 4762 MemoryVT(memvt), SrcValue(srcValue), SVOffset(SVO), 4763 Flags(vol | ((Log2_32(alignment) + 1) << 1)) { 4764 assert(isPowerOf2_32(alignment) && "Alignment is not a power of 2!"); 4765 assert(getAlignment() == alignment && "Alignment representation error!"); 4766 assert(isVolatile() == vol && "Volatile representation error!"); 4767} 4768 4769/// getMemOperand - Return a MachineMemOperand object describing the memory 4770/// reference performed by this memory reference. 4771MachineMemOperand MemSDNode::getMemOperand() const { 4772 int Flags = 0; 4773 if (isa<LoadSDNode>(this)) 4774 Flags = MachineMemOperand::MOLoad; 4775 else if (isa<StoreSDNode>(this)) 4776 Flags = MachineMemOperand::MOStore; 4777 else if (isa<AtomicSDNode>(this)) { 4778 Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore; 4779 } 4780 else { 4781 const MemIntrinsicSDNode* MemIntrinNode = dyn_cast<MemIntrinsicSDNode>(this); 4782 assert(MemIntrinNode && "Unknown MemSDNode opcode!"); 4783 if (MemIntrinNode->readMem()) Flags |= MachineMemOperand::MOLoad; 4784 if (MemIntrinNode->writeMem()) Flags |= MachineMemOperand::MOStore; 4785 } 4786 4787 int Size = (getMemoryVT().getSizeInBits() + 7) >> 3; 4788 if (isVolatile()) Flags |= MachineMemOperand::MOVolatile; 4789 4790 // Check if the memory reference references a frame index 4791 const FrameIndexSDNode *FI = 4792 dyn_cast<const FrameIndexSDNode>(getBasePtr().getNode()); 4793 if (!getSrcValue() && FI) 4794 return MachineMemOperand(PseudoSourceValue::getFixedStack(FI->getIndex()), 4795 Flags, 0, Size, getAlignment()); 4796 else 4797 return MachineMemOperand(getSrcValue(), Flags, getSrcValueOffset(), 4798 Size, getAlignment()); 4799} 4800 4801/// Profile - Gather unique data for the node. 4802/// 4803void SDNode::Profile(FoldingSetNodeID &ID) const { 4804 AddNodeIDNode(ID, this); 4805} 4806 4807/// getValueTypeList - Return a pointer to the specified value type. 4808/// 4809const MVT *SDNode::getValueTypeList(MVT VT) { 4810 if (VT.isExtended()) { 4811 static std::set<MVT, MVT::compareRawBits> EVTs; 4812 return &(*EVTs.insert(VT).first); 4813 } else { 4814 static MVT VTs[MVT::LAST_VALUETYPE]; 4815 VTs[VT.getSimpleVT()] = VT; 4816 return &VTs[VT.getSimpleVT()]; 4817 } 4818} 4819 4820/// hasNUsesOfValue - Return true if there are exactly NUSES uses of the 4821/// indicated value. This method ignores uses of other values defined by this 4822/// operation. 4823bool SDNode::hasNUsesOfValue(unsigned NUses, unsigned Value) const { 4824 assert(Value < getNumValues() && "Bad value!"); 4825 4826 // TODO: Only iterate over uses of a given value of the node 4827 for (SDNode::use_iterator UI = use_begin(), E = use_end(); UI != E; ++UI) { 4828 if (UI.getUse().getSDValue().getResNo() == Value) { 4829 if (NUses == 0) 4830 return false; 4831 --NUses; 4832 } 4833 } 4834 4835 // Found exactly the right number of uses? 4836 return NUses == 0; 4837} 4838 4839 4840/// hasAnyUseOfValue - Return true if there are any use of the indicated 4841/// value. This method ignores uses of other values defined by this operation. 4842bool SDNode::hasAnyUseOfValue(unsigned Value) const { 4843 assert(Value < getNumValues() && "Bad value!"); 4844 4845 for (SDNode::use_iterator UI = use_begin(), E = use_end(); UI != E; ++UI) 4846 if (UI.getUse().getSDValue().getResNo() == Value) 4847 return true; 4848 4849 return false; 4850} 4851 4852 4853/// isOnlyUserOf - Return true if this node is the only use of N. 4854/// 4855bool SDNode::isOnlyUserOf(SDNode *N) const { 4856 bool Seen = false; 4857 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 4858 SDNode *User = *I; 4859 if (User == this) 4860 Seen = true; 4861 else 4862 return false; 4863 } 4864 4865 return Seen; 4866} 4867 4868/// isOperand - Return true if this node is an operand of N. 4869/// 4870bool SDValue::isOperandOf(SDNode *N) const { 4871 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 4872 if (*this == N->getOperand(i)) 4873 return true; 4874 return false; 4875} 4876 4877bool SDNode::isOperandOf(SDNode *N) const { 4878 for (unsigned i = 0, e = N->NumOperands; i != e; ++i) 4879 if (this == N->OperandList[i].getVal()) 4880 return true; 4881 return false; 4882} 4883 4884/// reachesChainWithoutSideEffects - Return true if this operand (which must 4885/// be a chain) reaches the specified operand without crossing any 4886/// side-effecting instructions. In practice, this looks through token 4887/// factors and non-volatile loads. In order to remain efficient, this only 4888/// looks a couple of nodes in, it does not do an exhaustive search. 4889bool SDValue::reachesChainWithoutSideEffects(SDValue Dest, 4890 unsigned Depth) const { 4891 if (*this == Dest) return true; 4892 4893 // Don't search too deeply, we just want to be able to see through 4894 // TokenFactor's etc. 4895 if (Depth == 0) return false; 4896 4897 // If this is a token factor, all inputs to the TF happen in parallel. If any 4898 // of the operands of the TF reach dest, then we can do the xform. 4899 if (getOpcode() == ISD::TokenFactor) { 4900 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) 4901 if (getOperand(i).reachesChainWithoutSideEffects(Dest, Depth-1)) 4902 return true; 4903 return false; 4904 } 4905 4906 // Loads don't have side effects, look through them. 4907 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(*this)) { 4908 if (!Ld->isVolatile()) 4909 return Ld->getChain().reachesChainWithoutSideEffects(Dest, Depth-1); 4910 } 4911 return false; 4912} 4913 4914 4915static void findPredecessor(SDNode *N, const SDNode *P, bool &found, 4916 SmallPtrSet<SDNode *, 32> &Visited) { 4917 if (found || !Visited.insert(N)) 4918 return; 4919 4920 for (unsigned i = 0, e = N->getNumOperands(); !found && i != e; ++i) { 4921 SDNode *Op = N->getOperand(i).getNode(); 4922 if (Op == P) { 4923 found = true; 4924 return; 4925 } 4926 findPredecessor(Op, P, found, Visited); 4927 } 4928} 4929 4930/// isPredecessorOf - Return true if this node is a predecessor of N. This node 4931/// is either an operand of N or it can be reached by recursively traversing 4932/// up the operands. 4933/// NOTE: this is an expensive method. Use it carefully. 4934bool SDNode::isPredecessorOf(SDNode *N) const { 4935 SmallPtrSet<SDNode *, 32> Visited; 4936 bool found = false; 4937 findPredecessor(N, this, found, Visited); 4938 return found; 4939} 4940 4941uint64_t SDNode::getConstantOperandVal(unsigned Num) const { 4942 assert(Num < NumOperands && "Invalid child # of SDNode!"); 4943 return cast<ConstantSDNode>(OperandList[Num])->getZExtValue(); 4944} 4945 4946std::string SDNode::getOperationName(const SelectionDAG *G) const { 4947 switch (getOpcode()) { 4948 default: 4949 if (getOpcode() < ISD::BUILTIN_OP_END) 4950 return "<<Unknown DAG Node>>"; 4951 if (isMachineOpcode()) { 4952 if (G) 4953 if (const TargetInstrInfo *TII = G->getTarget().getInstrInfo()) 4954 if (getMachineOpcode() < TII->getNumOpcodes()) 4955 return TII->get(getMachineOpcode()).getName(); 4956 return "<<Unknown Machine Node>>"; 4957 } 4958 if (G) { 4959 TargetLowering &TLI = G->getTargetLoweringInfo(); 4960 const char *Name = TLI.getTargetNodeName(getOpcode()); 4961 if (Name) return Name; 4962 return "<<Unknown Target Node>>"; 4963 } 4964 return "<<Unknown Node>>"; 4965 4966#ifndef NDEBUG 4967 case ISD::DELETED_NODE: 4968 return "<<Deleted Node!>>"; 4969#endif 4970 case ISD::PREFETCH: return "Prefetch"; 4971 case ISD::MEMBARRIER: return "MemBarrier"; 4972 case ISD::ATOMIC_CMP_SWAP_8: return "AtomicCmpSwap8"; 4973 case ISD::ATOMIC_SWAP_8: return "AtomicSwap8"; 4974 case ISD::ATOMIC_LOAD_ADD_8: return "AtomicLoadAdd8"; 4975 case ISD::ATOMIC_LOAD_SUB_8: return "AtomicLoadSub8"; 4976 case ISD::ATOMIC_LOAD_AND_8: return "AtomicLoadAnd8"; 4977 case ISD::ATOMIC_LOAD_OR_8: return "AtomicLoadOr8"; 4978 case ISD::ATOMIC_LOAD_XOR_8: return "AtomicLoadXor8"; 4979 case ISD::ATOMIC_LOAD_NAND_8: return "AtomicLoadNand8"; 4980 case ISD::ATOMIC_LOAD_MIN_8: return "AtomicLoadMin8"; 4981 case ISD::ATOMIC_LOAD_MAX_8: return "AtomicLoadMax8"; 4982 case ISD::ATOMIC_LOAD_UMIN_8: return "AtomicLoadUMin8"; 4983 case ISD::ATOMIC_LOAD_UMAX_8: return "AtomicLoadUMax8"; 4984 case ISD::ATOMIC_CMP_SWAP_16: return "AtomicCmpSwap16"; 4985 case ISD::ATOMIC_SWAP_16: return "AtomicSwap16"; 4986 case ISD::ATOMIC_LOAD_ADD_16: return "AtomicLoadAdd16"; 4987 case ISD::ATOMIC_LOAD_SUB_16: return "AtomicLoadSub16"; 4988 case ISD::ATOMIC_LOAD_AND_16: return "AtomicLoadAnd16"; 4989 case ISD::ATOMIC_LOAD_OR_16: return "AtomicLoadOr16"; 4990 case ISD::ATOMIC_LOAD_XOR_16: return "AtomicLoadXor16"; 4991 case ISD::ATOMIC_LOAD_NAND_16: return "AtomicLoadNand16"; 4992 case ISD::ATOMIC_LOAD_MIN_16: return "AtomicLoadMin16"; 4993 case ISD::ATOMIC_LOAD_MAX_16: return "AtomicLoadMax16"; 4994 case ISD::ATOMIC_LOAD_UMIN_16: return "AtomicLoadUMin16"; 4995 case ISD::ATOMIC_LOAD_UMAX_16: return "AtomicLoadUMax16"; 4996 case ISD::ATOMIC_CMP_SWAP_32: return "AtomicCmpSwap32"; 4997 case ISD::ATOMIC_SWAP_32: return "AtomicSwap32"; 4998 case ISD::ATOMIC_LOAD_ADD_32: return "AtomicLoadAdd32"; 4999 case ISD::ATOMIC_LOAD_SUB_32: return "AtomicLoadSub32"; 5000 case ISD::ATOMIC_LOAD_AND_32: return "AtomicLoadAnd32"; 5001 case ISD::ATOMIC_LOAD_OR_32: return "AtomicLoadOr32"; 5002 case ISD::ATOMIC_LOAD_XOR_32: return "AtomicLoadXor32"; 5003 case ISD::ATOMIC_LOAD_NAND_32: return "AtomicLoadNand32"; 5004 case ISD::ATOMIC_LOAD_MIN_32: return "AtomicLoadMin32"; 5005 case ISD::ATOMIC_LOAD_MAX_32: return "AtomicLoadMax32"; 5006 case ISD::ATOMIC_LOAD_UMIN_32: return "AtomicLoadUMin32"; 5007 case ISD::ATOMIC_LOAD_UMAX_32: return "AtomicLoadUMax32"; 5008 case ISD::ATOMIC_CMP_SWAP_64: return "AtomicCmpSwap64"; 5009 case ISD::ATOMIC_SWAP_64: return "AtomicSwap64"; 5010 case ISD::ATOMIC_LOAD_ADD_64: return "AtomicLoadAdd64"; 5011 case ISD::ATOMIC_LOAD_SUB_64: return "AtomicLoadSub64"; 5012 case ISD::ATOMIC_LOAD_AND_64: return "AtomicLoadAnd64"; 5013 case ISD::ATOMIC_LOAD_OR_64: return "AtomicLoadOr64"; 5014 case ISD::ATOMIC_LOAD_XOR_64: return "AtomicLoadXor64"; 5015 case ISD::ATOMIC_LOAD_NAND_64: return "AtomicLoadNand64"; 5016 case ISD::ATOMIC_LOAD_MIN_64: return "AtomicLoadMin64"; 5017 case ISD::ATOMIC_LOAD_MAX_64: return "AtomicLoadMax64"; 5018 case ISD::ATOMIC_LOAD_UMIN_64: return "AtomicLoadUMin64"; 5019 case ISD::ATOMIC_LOAD_UMAX_64: return "AtomicLoadUMax64"; 5020 case ISD::PCMARKER: return "PCMarker"; 5021 case ISD::READCYCLECOUNTER: return "ReadCycleCounter"; 5022 case ISD::SRCVALUE: return "SrcValue"; 5023 case ISD::MEMOPERAND: return "MemOperand"; 5024 case ISD::EntryToken: return "EntryToken"; 5025 case ISD::TokenFactor: return "TokenFactor"; 5026 case ISD::AssertSext: return "AssertSext"; 5027 case ISD::AssertZext: return "AssertZext"; 5028 5029 case ISD::BasicBlock: return "BasicBlock"; 5030 case ISD::ARG_FLAGS: return "ArgFlags"; 5031 case ISD::VALUETYPE: return "ValueType"; 5032 case ISD::Register: return "Register"; 5033 5034 case ISD::Constant: return "Constant"; 5035 case ISD::ConstantFP: return "ConstantFP"; 5036 case ISD::GlobalAddress: return "GlobalAddress"; 5037 case ISD::GlobalTLSAddress: return "GlobalTLSAddress"; 5038 case ISD::FrameIndex: return "FrameIndex"; 5039 case ISD::JumpTable: return "JumpTable"; 5040 case ISD::GLOBAL_OFFSET_TABLE: return "GLOBAL_OFFSET_TABLE"; 5041 case ISD::RETURNADDR: return "RETURNADDR"; 5042 case ISD::FRAMEADDR: return "FRAMEADDR"; 5043 case ISD::FRAME_TO_ARGS_OFFSET: return "FRAME_TO_ARGS_OFFSET"; 5044 case ISD::EXCEPTIONADDR: return "EXCEPTIONADDR"; 5045 case ISD::EHSELECTION: return "EHSELECTION"; 5046 case ISD::EH_RETURN: return "EH_RETURN"; 5047 case ISD::ConstantPool: return "ConstantPool"; 5048 case ISD::ExternalSymbol: return "ExternalSymbol"; 5049 case ISD::INTRINSIC_WO_CHAIN: { 5050 unsigned IID = cast<ConstantSDNode>(getOperand(0))->getZExtValue(); 5051 return Intrinsic::getName((Intrinsic::ID)IID); 5052 } 5053 case ISD::INTRINSIC_VOID: 5054 case ISD::INTRINSIC_W_CHAIN: { 5055 unsigned IID = cast<ConstantSDNode>(getOperand(1))->getZExtValue(); 5056 return Intrinsic::getName((Intrinsic::ID)IID); 5057 } 5058 5059 case ISD::BUILD_VECTOR: return "BUILD_VECTOR"; 5060 case ISD::TargetConstant: return "TargetConstant"; 5061 case ISD::TargetConstantFP:return "TargetConstantFP"; 5062 case ISD::TargetGlobalAddress: return "TargetGlobalAddress"; 5063 case ISD::TargetGlobalTLSAddress: return "TargetGlobalTLSAddress"; 5064 case ISD::TargetFrameIndex: return "TargetFrameIndex"; 5065 case ISD::TargetJumpTable: return "TargetJumpTable"; 5066 case ISD::TargetConstantPool: return "TargetConstantPool"; 5067 case ISD::TargetExternalSymbol: return "TargetExternalSymbol"; 5068 5069 case ISD::CopyToReg: return "CopyToReg"; 5070 case ISD::CopyFromReg: return "CopyFromReg"; 5071 case ISD::UNDEF: return "undef"; 5072 case ISD::MERGE_VALUES: return "merge_values"; 5073 case ISD::INLINEASM: return "inlineasm"; 5074 case ISD::DBG_LABEL: return "dbg_label"; 5075 case ISD::EH_LABEL: return "eh_label"; 5076 case ISD::DECLARE: return "declare"; 5077 case ISD::HANDLENODE: return "handlenode"; 5078 case ISD::FORMAL_ARGUMENTS: return "formal_arguments"; 5079 case ISD::CALL: return "call"; 5080 5081 // Unary operators 5082 case ISD::FABS: return "fabs"; 5083 case ISD::FNEG: return "fneg"; 5084 case ISD::FSQRT: return "fsqrt"; 5085 case ISD::FSIN: return "fsin"; 5086 case ISD::FCOS: return "fcos"; 5087 case ISD::FPOWI: return "fpowi"; 5088 case ISD::FPOW: return "fpow"; 5089 case ISD::FTRUNC: return "ftrunc"; 5090 case ISD::FFLOOR: return "ffloor"; 5091 case ISD::FCEIL: return "fceil"; 5092 case ISD::FRINT: return "frint"; 5093 case ISD::FNEARBYINT: return "fnearbyint"; 5094 5095 // Binary operators 5096 case ISD::ADD: return "add"; 5097 case ISD::SUB: return "sub"; 5098 case ISD::MUL: return "mul"; 5099 case ISD::MULHU: return "mulhu"; 5100 case ISD::MULHS: return "mulhs"; 5101 case ISD::SDIV: return "sdiv"; 5102 case ISD::UDIV: return "udiv"; 5103 case ISD::SREM: return "srem"; 5104 case ISD::UREM: return "urem"; 5105 case ISD::SMUL_LOHI: return "smul_lohi"; 5106 case ISD::UMUL_LOHI: return "umul_lohi"; 5107 case ISD::SDIVREM: return "sdivrem"; 5108 case ISD::UDIVREM: return "udivrem"; 5109 case ISD::AND: return "and"; 5110 case ISD::OR: return "or"; 5111 case ISD::XOR: return "xor"; 5112 case ISD::SHL: return "shl"; 5113 case ISD::SRA: return "sra"; 5114 case ISD::SRL: return "srl"; 5115 case ISD::ROTL: return "rotl"; 5116 case ISD::ROTR: return "rotr"; 5117 case ISD::FADD: return "fadd"; 5118 case ISD::FSUB: return "fsub"; 5119 case ISD::FMUL: return "fmul"; 5120 case ISD::FDIV: return "fdiv"; 5121 case ISD::FREM: return "frem"; 5122 case ISD::FCOPYSIGN: return "fcopysign"; 5123 case ISD::FGETSIGN: return "fgetsign"; 5124 5125 case ISD::SETCC: return "setcc"; 5126 case ISD::VSETCC: return "vsetcc"; 5127 case ISD::SELECT: return "select"; 5128 case ISD::SELECT_CC: return "select_cc"; 5129 case ISD::INSERT_VECTOR_ELT: return "insert_vector_elt"; 5130 case ISD::EXTRACT_VECTOR_ELT: return "extract_vector_elt"; 5131 case ISD::CONCAT_VECTORS: return "concat_vectors"; 5132 case ISD::EXTRACT_SUBVECTOR: return "extract_subvector"; 5133 case ISD::SCALAR_TO_VECTOR: return "scalar_to_vector"; 5134 case ISD::VECTOR_SHUFFLE: return "vector_shuffle"; 5135 case ISD::CARRY_FALSE: return "carry_false"; 5136 case ISD::ADDC: return "addc"; 5137 case ISD::ADDE: return "adde"; 5138 case ISD::SUBC: return "subc"; 5139 case ISD::SUBE: return "sube"; 5140 case ISD::SHL_PARTS: return "shl_parts"; 5141 case ISD::SRA_PARTS: return "sra_parts"; 5142 case ISD::SRL_PARTS: return "srl_parts"; 5143 5144 case ISD::EXTRACT_SUBREG: return "extract_subreg"; 5145 case ISD::INSERT_SUBREG: return "insert_subreg"; 5146 5147 // Conversion operators. 5148 case ISD::SIGN_EXTEND: return "sign_extend"; 5149 case ISD::ZERO_EXTEND: return "zero_extend"; 5150 case ISD::ANY_EXTEND: return "any_extend"; 5151 case ISD::SIGN_EXTEND_INREG: return "sign_extend_inreg"; 5152 case ISD::TRUNCATE: return "truncate"; 5153 case ISD::FP_ROUND: return "fp_round"; 5154 case ISD::FLT_ROUNDS_: return "flt_rounds"; 5155 case ISD::FP_ROUND_INREG: return "fp_round_inreg"; 5156 case ISD::FP_EXTEND: return "fp_extend"; 5157 5158 case ISD::SINT_TO_FP: return "sint_to_fp"; 5159 case ISD::UINT_TO_FP: return "uint_to_fp"; 5160 case ISD::FP_TO_SINT: return "fp_to_sint"; 5161 case ISD::FP_TO_UINT: return "fp_to_uint"; 5162 case ISD::BIT_CONVERT: return "bit_convert"; 5163 5164 // Control flow instructions 5165 case ISD::BR: return "br"; 5166 case ISD::BRIND: return "brind"; 5167 case ISD::BR_JT: return "br_jt"; 5168 case ISD::BRCOND: return "brcond"; 5169 case ISD::BR_CC: return "br_cc"; 5170 case ISD::RET: return "ret"; 5171 case ISD::CALLSEQ_START: return "callseq_start"; 5172 case ISD::CALLSEQ_END: return "callseq_end"; 5173 5174 // Other operators 5175 case ISD::LOAD: return "load"; 5176 case ISD::STORE: return "store"; 5177 case ISD::VAARG: return "vaarg"; 5178 case ISD::VACOPY: return "vacopy"; 5179 case ISD::VAEND: return "vaend"; 5180 case ISD::VASTART: return "vastart"; 5181 case ISD::DYNAMIC_STACKALLOC: return "dynamic_stackalloc"; 5182 case ISD::EXTRACT_ELEMENT: return "extract_element"; 5183 case ISD::BUILD_PAIR: return "build_pair"; 5184 case ISD::STACKSAVE: return "stacksave"; 5185 case ISD::STACKRESTORE: return "stackrestore"; 5186 case ISD::TRAP: return "trap"; 5187 5188 // Bit manipulation 5189 case ISD::BSWAP: return "bswap"; 5190 case ISD::CTPOP: return "ctpop"; 5191 case ISD::CTTZ: return "cttz"; 5192 case ISD::CTLZ: return "ctlz"; 5193 5194 // Debug info 5195 case ISD::DBG_STOPPOINT: return "dbg_stoppoint"; 5196 case ISD::DEBUG_LOC: return "debug_loc"; 5197 5198 // Trampolines 5199 case ISD::TRAMPOLINE: return "trampoline"; 5200 5201 case ISD::CONDCODE: 5202 switch (cast<CondCodeSDNode>(this)->get()) { 5203 default: assert(0 && "Unknown setcc condition!"); 5204 case ISD::SETOEQ: return "setoeq"; 5205 case ISD::SETOGT: return "setogt"; 5206 case ISD::SETOGE: return "setoge"; 5207 case ISD::SETOLT: return "setolt"; 5208 case ISD::SETOLE: return "setole"; 5209 case ISD::SETONE: return "setone"; 5210 5211 case ISD::SETO: return "seto"; 5212 case ISD::SETUO: return "setuo"; 5213 case ISD::SETUEQ: return "setue"; 5214 case ISD::SETUGT: return "setugt"; 5215 case ISD::SETUGE: return "setuge"; 5216 case ISD::SETULT: return "setult"; 5217 case ISD::SETULE: return "setule"; 5218 case ISD::SETUNE: return "setune"; 5219 5220 case ISD::SETEQ: return "seteq"; 5221 case ISD::SETGT: return "setgt"; 5222 case ISD::SETGE: return "setge"; 5223 case ISD::SETLT: return "setlt"; 5224 case ISD::SETLE: return "setle"; 5225 case ISD::SETNE: return "setne"; 5226 } 5227 } 5228} 5229 5230const char *SDNode::getIndexedModeName(ISD::MemIndexedMode AM) { 5231 switch (AM) { 5232 default: 5233 return ""; 5234 case ISD::PRE_INC: 5235 return "<pre-inc>"; 5236 case ISD::PRE_DEC: 5237 return "<pre-dec>"; 5238 case ISD::POST_INC: 5239 return "<post-inc>"; 5240 case ISD::POST_DEC: 5241 return "<post-dec>"; 5242 } 5243} 5244 5245std::string ISD::ArgFlagsTy::getArgFlagsString() { 5246 std::string S = "< "; 5247 5248 if (isZExt()) 5249 S += "zext "; 5250 if (isSExt()) 5251 S += "sext "; 5252 if (isInReg()) 5253 S += "inreg "; 5254 if (isSRet()) 5255 S += "sret "; 5256 if (isByVal()) 5257 S += "byval "; 5258 if (isNest()) 5259 S += "nest "; 5260 if (getByValAlign()) 5261 S += "byval-align:" + utostr(getByValAlign()) + " "; 5262 if (getOrigAlign()) 5263 S += "orig-align:" + utostr(getOrigAlign()) + " "; 5264 if (getByValSize()) 5265 S += "byval-size:" + utostr(getByValSize()) + " "; 5266 return S + ">"; 5267} 5268 5269void SDNode::dump() const { dump(0); } 5270void SDNode::dump(const SelectionDAG *G) const { 5271 print(errs(), G); 5272 errs().flush(); 5273} 5274 5275void SDNode::print(raw_ostream &OS, const SelectionDAG *G) const { 5276 OS << (void*)this << ": "; 5277 5278 for (unsigned i = 0, e = getNumValues(); i != e; ++i) { 5279 if (i) OS << ","; 5280 if (getValueType(i) == MVT::Other) 5281 OS << "ch"; 5282 else 5283 OS << getValueType(i).getMVTString(); 5284 } 5285 OS << " = " << getOperationName(G); 5286 5287 OS << " "; 5288 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 5289 if (i) OS << ", "; 5290 OS << (void*)getOperand(i).getNode(); 5291 if (unsigned RN = getOperand(i).getResNo()) 5292 OS << ":" << RN; 5293 } 5294 5295 if (!isTargetOpcode() && getOpcode() == ISD::VECTOR_SHUFFLE) { 5296 SDNode *Mask = getOperand(2).getNode(); 5297 OS << "<"; 5298 for (unsigned i = 0, e = Mask->getNumOperands(); i != e; ++i) { 5299 if (i) OS << ","; 5300 if (Mask->getOperand(i).getOpcode() == ISD::UNDEF) 5301 OS << "u"; 5302 else 5303 OS << cast<ConstantSDNode>(Mask->getOperand(i))->getZExtValue(); 5304 } 5305 OS << ">"; 5306 } 5307 5308 if (const ConstantSDNode *CSDN = dyn_cast<ConstantSDNode>(this)) { 5309 OS << '<' << CSDN->getAPIntValue() << '>'; 5310 } else if (const ConstantFPSDNode *CSDN = dyn_cast<ConstantFPSDNode>(this)) { 5311 if (&CSDN->getValueAPF().getSemantics()==&APFloat::IEEEsingle) 5312 OS << '<' << CSDN->getValueAPF().convertToFloat() << '>'; 5313 else if (&CSDN->getValueAPF().getSemantics()==&APFloat::IEEEdouble) 5314 OS << '<' << CSDN->getValueAPF().convertToDouble() << '>'; 5315 else { 5316 OS << "<APFloat("; 5317 CSDN->getValueAPF().bitcastToAPInt().dump(); 5318 OS << ")>"; 5319 } 5320 } else if (const GlobalAddressSDNode *GADN = 5321 dyn_cast<GlobalAddressSDNode>(this)) { 5322 int64_t offset = GADN->getOffset(); 5323 OS << '<'; 5324 WriteAsOperand(OS, GADN->getGlobal()); 5325 OS << '>'; 5326 if (offset > 0) 5327 OS << " + " << offset; 5328 else 5329 OS << " " << offset; 5330 } else if (const FrameIndexSDNode *FIDN = dyn_cast<FrameIndexSDNode>(this)) { 5331 OS << "<" << FIDN->getIndex() << ">"; 5332 } else if (const JumpTableSDNode *JTDN = dyn_cast<JumpTableSDNode>(this)) { 5333 OS << "<" << JTDN->getIndex() << ">"; 5334 } else if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(this)){ 5335 int offset = CP->getOffset(); 5336 if (CP->isMachineConstantPoolEntry()) 5337 OS << "<" << *CP->getMachineCPVal() << ">"; 5338 else 5339 OS << "<" << *CP->getConstVal() << ">"; 5340 if (offset > 0) 5341 OS << " + " << offset; 5342 else 5343 OS << " " << offset; 5344 } else if (const BasicBlockSDNode *BBDN = dyn_cast<BasicBlockSDNode>(this)) { 5345 OS << "<"; 5346 const Value *LBB = (const Value*)BBDN->getBasicBlock()->getBasicBlock(); 5347 if (LBB) 5348 OS << LBB->getName() << " "; 5349 OS << (const void*)BBDN->getBasicBlock() << ">"; 5350 } else if (const RegisterSDNode *R = dyn_cast<RegisterSDNode>(this)) { 5351 if (G && R->getReg() && 5352 TargetRegisterInfo::isPhysicalRegister(R->getReg())) { 5353 OS << " " << G->getTarget().getRegisterInfo()->getName(R->getReg()); 5354 } else { 5355 OS << " #" << R->getReg(); 5356 } 5357 } else if (const ExternalSymbolSDNode *ES = 5358 dyn_cast<ExternalSymbolSDNode>(this)) { 5359 OS << "'" << ES->getSymbol() << "'"; 5360 } else if (const SrcValueSDNode *M = dyn_cast<SrcValueSDNode>(this)) { 5361 if (M->getValue()) 5362 OS << "<" << M->getValue() << ">"; 5363 else 5364 OS << "<null>"; 5365 } else if (const MemOperandSDNode *M = dyn_cast<MemOperandSDNode>(this)) { 5366 if (M->MO.getValue()) 5367 OS << "<" << M->MO.getValue() << ":" << M->MO.getOffset() << ">"; 5368 else 5369 OS << "<null:" << M->MO.getOffset() << ">"; 5370 } else if (const ARG_FLAGSSDNode *N = dyn_cast<ARG_FLAGSSDNode>(this)) { 5371 OS << N->getArgFlags().getArgFlagsString(); 5372 } else if (const VTSDNode *N = dyn_cast<VTSDNode>(this)) { 5373 OS << ":" << N->getVT().getMVTString(); 5374 } 5375 else if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(this)) { 5376 const Value *SrcValue = LD->getSrcValue(); 5377 int SrcOffset = LD->getSrcValueOffset(); 5378 OS << " <"; 5379 if (SrcValue) 5380 OS << SrcValue; 5381 else 5382 OS << "null"; 5383 OS << ":" << SrcOffset << ">"; 5384 5385 bool doExt = true; 5386 switch (LD->getExtensionType()) { 5387 default: doExt = false; break; 5388 case ISD::EXTLOAD: OS << " <anyext "; break; 5389 case ISD::SEXTLOAD: OS << " <sext "; break; 5390 case ISD::ZEXTLOAD: OS << " <zext "; break; 5391 } 5392 if (doExt) 5393 OS << LD->getMemoryVT().getMVTString() << ">"; 5394 5395 const char *AM = getIndexedModeName(LD->getAddressingMode()); 5396 if (*AM) 5397 OS << " " << AM; 5398 if (LD->isVolatile()) 5399 OS << " <volatile>"; 5400 OS << " alignment=" << LD->getAlignment(); 5401 } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(this)) { 5402 const Value *SrcValue = ST->getSrcValue(); 5403 int SrcOffset = ST->getSrcValueOffset(); 5404 OS << " <"; 5405 if (SrcValue) 5406 OS << SrcValue; 5407 else 5408 OS << "null"; 5409 OS << ":" << SrcOffset << ">"; 5410 5411 if (ST->isTruncatingStore()) 5412 OS << " <trunc " << ST->getMemoryVT().getMVTString() << ">"; 5413 5414 const char *AM = getIndexedModeName(ST->getAddressingMode()); 5415 if (*AM) 5416 OS << " " << AM; 5417 if (ST->isVolatile()) 5418 OS << " <volatile>"; 5419 OS << " alignment=" << ST->getAlignment(); 5420 } else if (const AtomicSDNode* AT = dyn_cast<AtomicSDNode>(this)) { 5421 const Value *SrcValue = AT->getSrcValue(); 5422 int SrcOffset = AT->getSrcValueOffset(); 5423 OS << " <"; 5424 if (SrcValue) 5425 OS << SrcValue; 5426 else 5427 OS << "null"; 5428 OS << ":" << SrcOffset << ">"; 5429 if (AT->isVolatile()) 5430 OS << " <volatile>"; 5431 OS << " alignment=" << AT->getAlignment(); 5432 } 5433} 5434 5435static void DumpNodes(const SDNode *N, unsigned indent, const SelectionDAG *G) { 5436 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 5437 if (N->getOperand(i).getNode()->hasOneUse()) 5438 DumpNodes(N->getOperand(i).getNode(), indent+2, G); 5439 else 5440 cerr << "\n" << std::string(indent+2, ' ') 5441 << (void*)N->getOperand(i).getNode() << ": <multiple use>"; 5442 5443 5444 cerr << "\n" << std::string(indent, ' '); 5445 N->dump(G); 5446} 5447 5448void SelectionDAG::dump() const { 5449 cerr << "SelectionDAG has " << AllNodes.size() << " nodes:"; 5450 5451 for (allnodes_const_iterator I = allnodes_begin(), E = allnodes_end(); 5452 I != E; ++I) { 5453 const SDNode *N = I; 5454 if (!N->hasOneUse() && N != getRoot().getNode()) 5455 DumpNodes(N, 2, this); 5456 } 5457 5458 if (getRoot().getNode()) DumpNodes(getRoot().getNode(), 2, this); 5459 5460 cerr << "\n\n"; 5461} 5462 5463const Type *ConstantPoolSDNode::getType() const { 5464 if (isMachineConstantPoolEntry()) 5465 return Val.MachineCPVal->getType(); 5466 return Val.ConstVal->getType(); 5467} 5468