SelectionDAG.cpp revision b4459088d62670b0f0333eab1b260622955ec3e5
1//===-- SelectionDAG.cpp - Implement the SelectionDAG data structures -----===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAG class. 11// 12//===----------------------------------------------------------------------===// 13#include "llvm/CodeGen/SelectionDAG.h" 14#include "llvm/Constants.h" 15#include "llvm/Analysis/ValueTracking.h" 16#include "llvm/GlobalAlias.h" 17#include "llvm/GlobalVariable.h" 18#include "llvm/Intrinsics.h" 19#include "llvm/DerivedTypes.h" 20#include "llvm/Assembly/Writer.h" 21#include "llvm/CallingConv.h" 22#include "llvm/CodeGen/MachineBasicBlock.h" 23#include "llvm/CodeGen/MachineConstantPool.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/MachineModuleInfo.h" 26#include "llvm/CodeGen/PseudoSourceValue.h" 27#include "llvm/Target/TargetRegisterInfo.h" 28#include "llvm/Target/TargetData.h" 29#include "llvm/Target/TargetLowering.h" 30#include "llvm/Target/TargetOptions.h" 31#include "llvm/Target/TargetInstrInfo.h" 32#include "llvm/Target/TargetMachine.h" 33#include "llvm/Support/CommandLine.h" 34#include "llvm/Support/ManagedStatic.h" 35#include "llvm/Support/MathExtras.h" 36#include "llvm/Support/raw_ostream.h" 37#include "llvm/System/Mutex.h" 38#include "llvm/ADT/SetVector.h" 39#include "llvm/ADT/SmallPtrSet.h" 40#include "llvm/ADT/SmallSet.h" 41#include "llvm/ADT/SmallVector.h" 42#include "llvm/ADT/StringExtras.h" 43#include <algorithm> 44#include <cmath> 45using namespace llvm; 46 47/// makeVTList - Return an instance of the SDVTList struct initialized with the 48/// specified members. 49static SDVTList makeVTList(const MVT *VTs, unsigned NumVTs) { 50 SDVTList Res = {VTs, NumVTs}; 51 return Res; 52} 53 54static const fltSemantics *MVTToAPFloatSemantics(MVT VT) { 55 switch (VT.getSimpleVT()) { 56 default: assert(0 && "Unknown FP format"); 57 case MVT::f32: return &APFloat::IEEEsingle; 58 case MVT::f64: return &APFloat::IEEEdouble; 59 case MVT::f80: return &APFloat::x87DoubleExtended; 60 case MVT::f128: return &APFloat::IEEEquad; 61 case MVT::ppcf128: return &APFloat::PPCDoubleDouble; 62 } 63} 64 65SelectionDAG::DAGUpdateListener::~DAGUpdateListener() {} 66 67//===----------------------------------------------------------------------===// 68// ConstantFPSDNode Class 69//===----------------------------------------------------------------------===// 70 71/// isExactlyValue - We don't rely on operator== working on double values, as 72/// it returns true for things that are clearly not equal, like -0.0 and 0.0. 73/// As such, this method can be used to do an exact bit-for-bit comparison of 74/// two floating point values. 75bool ConstantFPSDNode::isExactlyValue(const APFloat& V) const { 76 return getValueAPF().bitwiseIsEqual(V); 77} 78 79bool ConstantFPSDNode::isValueValidForType(MVT VT, 80 const APFloat& Val) { 81 assert(VT.isFloatingPoint() && "Can only convert between FP types"); 82 83 // PPC long double cannot be converted to any other type. 84 if (VT == MVT::ppcf128 || 85 &Val.getSemantics() == &APFloat::PPCDoubleDouble) 86 return false; 87 88 // convert modifies in place, so make a copy. 89 APFloat Val2 = APFloat(Val); 90 bool losesInfo; 91 (void) Val2.convert(*MVTToAPFloatSemantics(VT), APFloat::rmNearestTiesToEven, 92 &losesInfo); 93 return !losesInfo; 94} 95 96//===----------------------------------------------------------------------===// 97// ISD Namespace 98//===----------------------------------------------------------------------===// 99 100/// isBuildVectorAllOnes - Return true if the specified node is a 101/// BUILD_VECTOR where all of the elements are ~0 or undef. 102bool ISD::isBuildVectorAllOnes(const SDNode *N) { 103 // Look through a bit convert. 104 if (N->getOpcode() == ISD::BIT_CONVERT) 105 N = N->getOperand(0).getNode(); 106 107 if (N->getOpcode() != ISD::BUILD_VECTOR) return false; 108 109 unsigned i = 0, e = N->getNumOperands(); 110 111 // Skip over all of the undef values. 112 while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF) 113 ++i; 114 115 // Do not accept an all-undef vector. 116 if (i == e) return false; 117 118 // Do not accept build_vectors that aren't all constants or which have non-~0 119 // elements. 120 SDValue NotZero = N->getOperand(i); 121 if (isa<ConstantSDNode>(NotZero)) { 122 if (!cast<ConstantSDNode>(NotZero)->isAllOnesValue()) 123 return false; 124 } else if (isa<ConstantFPSDNode>(NotZero)) { 125 if (!cast<ConstantFPSDNode>(NotZero)->getValueAPF(). 126 bitcastToAPInt().isAllOnesValue()) 127 return false; 128 } else 129 return false; 130 131 // Okay, we have at least one ~0 value, check to see if the rest match or are 132 // undefs. 133 for (++i; i != e; ++i) 134 if (N->getOperand(i) != NotZero && 135 N->getOperand(i).getOpcode() != ISD::UNDEF) 136 return false; 137 return true; 138} 139 140 141/// isBuildVectorAllZeros - Return true if the specified node is a 142/// BUILD_VECTOR where all of the elements are 0 or undef. 143bool ISD::isBuildVectorAllZeros(const SDNode *N) { 144 // Look through a bit convert. 145 if (N->getOpcode() == ISD::BIT_CONVERT) 146 N = N->getOperand(0).getNode(); 147 148 if (N->getOpcode() != ISD::BUILD_VECTOR) return false; 149 150 unsigned i = 0, e = N->getNumOperands(); 151 152 // Skip over all of the undef values. 153 while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF) 154 ++i; 155 156 // Do not accept an all-undef vector. 157 if (i == e) return false; 158 159 // Do not accept build_vectors that aren't all constants or which have non-0 160 // elements. 161 SDValue Zero = N->getOperand(i); 162 if (isa<ConstantSDNode>(Zero)) { 163 if (!cast<ConstantSDNode>(Zero)->isNullValue()) 164 return false; 165 } else if (isa<ConstantFPSDNode>(Zero)) { 166 if (!cast<ConstantFPSDNode>(Zero)->getValueAPF().isPosZero()) 167 return false; 168 } else 169 return false; 170 171 // Okay, we have at least one 0 value, check to see if the rest match or are 172 // undefs. 173 for (++i; i != e; ++i) 174 if (N->getOperand(i) != Zero && 175 N->getOperand(i).getOpcode() != ISD::UNDEF) 176 return false; 177 return true; 178} 179 180/// isScalarToVector - Return true if the specified node is a 181/// ISD::SCALAR_TO_VECTOR node or a BUILD_VECTOR node where only the low 182/// element is not an undef. 183bool ISD::isScalarToVector(const SDNode *N) { 184 if (N->getOpcode() == ISD::SCALAR_TO_VECTOR) 185 return true; 186 187 if (N->getOpcode() != ISD::BUILD_VECTOR) 188 return false; 189 if (N->getOperand(0).getOpcode() == ISD::UNDEF) 190 return false; 191 unsigned NumElems = N->getNumOperands(); 192 for (unsigned i = 1; i < NumElems; ++i) { 193 SDValue V = N->getOperand(i); 194 if (V.getOpcode() != ISD::UNDEF) 195 return false; 196 } 197 return true; 198} 199 200 201/// isDebugLabel - Return true if the specified node represents a debug 202/// label (i.e. ISD::DBG_LABEL or TargetInstrInfo::DBG_LABEL node). 203bool ISD::isDebugLabel(const SDNode *N) { 204 SDValue Zero; 205 if (N->getOpcode() == ISD::DBG_LABEL) 206 return true; 207 if (N->isMachineOpcode() && 208 N->getMachineOpcode() == TargetInstrInfo::DBG_LABEL) 209 return true; 210 return false; 211} 212 213/// getSetCCSwappedOperands - Return the operation corresponding to (Y op X) 214/// when given the operation for (X op Y). 215ISD::CondCode ISD::getSetCCSwappedOperands(ISD::CondCode Operation) { 216 // To perform this operation, we just need to swap the L and G bits of the 217 // operation. 218 unsigned OldL = (Operation >> 2) & 1; 219 unsigned OldG = (Operation >> 1) & 1; 220 return ISD::CondCode((Operation & ~6) | // Keep the N, U, E bits 221 (OldL << 1) | // New G bit 222 (OldG << 2)); // New L bit. 223} 224 225/// getSetCCInverse - Return the operation corresponding to !(X op Y), where 226/// 'op' is a valid SetCC operation. 227ISD::CondCode ISD::getSetCCInverse(ISD::CondCode Op, bool isInteger) { 228 unsigned Operation = Op; 229 if (isInteger) 230 Operation ^= 7; // Flip L, G, E bits, but not U. 231 else 232 Operation ^= 15; // Flip all of the condition bits. 233 234 if (Operation > ISD::SETTRUE2) 235 Operation &= ~8; // Don't let N and U bits get set. 236 237 return ISD::CondCode(Operation); 238} 239 240 241/// isSignedOp - For an integer comparison, return 1 if the comparison is a 242/// signed operation and 2 if the result is an unsigned comparison. Return zero 243/// if the operation does not depend on the sign of the input (setne and seteq). 244static int isSignedOp(ISD::CondCode Opcode) { 245 switch (Opcode) { 246 default: assert(0 && "Illegal integer setcc operation!"); 247 case ISD::SETEQ: 248 case ISD::SETNE: return 0; 249 case ISD::SETLT: 250 case ISD::SETLE: 251 case ISD::SETGT: 252 case ISD::SETGE: return 1; 253 case ISD::SETULT: 254 case ISD::SETULE: 255 case ISD::SETUGT: 256 case ISD::SETUGE: return 2; 257 } 258} 259 260/// getSetCCOrOperation - Return the result of a logical OR between different 261/// comparisons of identical values: ((X op1 Y) | (X op2 Y)). This function 262/// returns SETCC_INVALID if it is not possible to represent the resultant 263/// comparison. 264ISD::CondCode ISD::getSetCCOrOperation(ISD::CondCode Op1, ISD::CondCode Op2, 265 bool isInteger) { 266 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 267 // Cannot fold a signed integer setcc with an unsigned integer setcc. 268 return ISD::SETCC_INVALID; 269 270 unsigned Op = Op1 | Op2; // Combine all of the condition bits. 271 272 // If the N and U bits get set then the resultant comparison DOES suddenly 273 // care about orderedness, and is true when ordered. 274 if (Op > ISD::SETTRUE2) 275 Op &= ~16; // Clear the U bit if the N bit is set. 276 277 // Canonicalize illegal integer setcc's. 278 if (isInteger && Op == ISD::SETUNE) // e.g. SETUGT | SETULT 279 Op = ISD::SETNE; 280 281 return ISD::CondCode(Op); 282} 283 284/// getSetCCAndOperation - Return the result of a logical AND between different 285/// comparisons of identical values: ((X op1 Y) & (X op2 Y)). This 286/// function returns zero if it is not possible to represent the resultant 287/// comparison. 288ISD::CondCode ISD::getSetCCAndOperation(ISD::CondCode Op1, ISD::CondCode Op2, 289 bool isInteger) { 290 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 291 // Cannot fold a signed setcc with an unsigned setcc. 292 return ISD::SETCC_INVALID; 293 294 // Combine all of the condition bits. 295 ISD::CondCode Result = ISD::CondCode(Op1 & Op2); 296 297 // Canonicalize illegal integer setcc's. 298 if (isInteger) { 299 switch (Result) { 300 default: break; 301 case ISD::SETUO : Result = ISD::SETFALSE; break; // SETUGT & SETULT 302 case ISD::SETOEQ: // SETEQ & SETU[LG]E 303 case ISD::SETUEQ: Result = ISD::SETEQ ; break; // SETUGE & SETULE 304 case ISD::SETOLT: Result = ISD::SETULT ; break; // SETULT & SETNE 305 case ISD::SETOGT: Result = ISD::SETUGT ; break; // SETUGT & SETNE 306 } 307 } 308 309 return Result; 310} 311 312const TargetMachine &SelectionDAG::getTarget() const { 313 return MF->getTarget(); 314} 315 316//===----------------------------------------------------------------------===// 317// SDNode Profile Support 318//===----------------------------------------------------------------------===// 319 320/// AddNodeIDOpcode - Add the node opcode to the NodeID data. 321/// 322static void AddNodeIDOpcode(FoldingSetNodeID &ID, unsigned OpC) { 323 ID.AddInteger(OpC); 324} 325 326/// AddNodeIDValueTypes - Value type lists are intern'd so we can represent them 327/// solely with their pointer. 328static void AddNodeIDValueTypes(FoldingSetNodeID &ID, SDVTList VTList) { 329 ID.AddPointer(VTList.VTs); 330} 331 332/// AddNodeIDOperands - Various routines for adding operands to the NodeID data. 333/// 334static void AddNodeIDOperands(FoldingSetNodeID &ID, 335 const SDValue *Ops, unsigned NumOps) { 336 for (; NumOps; --NumOps, ++Ops) { 337 ID.AddPointer(Ops->getNode()); 338 ID.AddInteger(Ops->getResNo()); 339 } 340} 341 342/// AddNodeIDOperands - Various routines for adding operands to the NodeID data. 343/// 344static void AddNodeIDOperands(FoldingSetNodeID &ID, 345 const SDUse *Ops, unsigned NumOps) { 346 for (; NumOps; --NumOps, ++Ops) { 347 ID.AddPointer(Ops->getNode()); 348 ID.AddInteger(Ops->getResNo()); 349 } 350} 351 352static void AddNodeIDNode(FoldingSetNodeID &ID, 353 unsigned short OpC, SDVTList VTList, 354 const SDValue *OpList, unsigned N) { 355 AddNodeIDOpcode(ID, OpC); 356 AddNodeIDValueTypes(ID, VTList); 357 AddNodeIDOperands(ID, OpList, N); 358} 359 360/// AddNodeIDCustom - If this is an SDNode with special info, add this info to 361/// the NodeID data. 362static void AddNodeIDCustom(FoldingSetNodeID &ID, const SDNode *N) { 363 switch (N->getOpcode()) { 364 default: break; // Normal nodes don't need extra info. 365 case ISD::ARG_FLAGS: 366 ID.AddInteger(cast<ARG_FLAGSSDNode>(N)->getArgFlags().getRawBits()); 367 break; 368 case ISD::TargetConstant: 369 case ISD::Constant: 370 ID.AddPointer(cast<ConstantSDNode>(N)->getConstantIntValue()); 371 break; 372 case ISD::TargetConstantFP: 373 case ISD::ConstantFP: { 374 ID.AddPointer(cast<ConstantFPSDNode>(N)->getConstantFPValue()); 375 break; 376 } 377 case ISD::TargetGlobalAddress: 378 case ISD::GlobalAddress: 379 case ISD::TargetGlobalTLSAddress: 380 case ISD::GlobalTLSAddress: { 381 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(N); 382 ID.AddPointer(GA->getGlobal()); 383 ID.AddInteger(GA->getOffset()); 384 break; 385 } 386 case ISD::BasicBlock: 387 ID.AddPointer(cast<BasicBlockSDNode>(N)->getBasicBlock()); 388 break; 389 case ISD::Register: 390 ID.AddInteger(cast<RegisterSDNode>(N)->getReg()); 391 break; 392 case ISD::DBG_STOPPOINT: { 393 const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(N); 394 ID.AddInteger(DSP->getLine()); 395 ID.AddInteger(DSP->getColumn()); 396 ID.AddPointer(DSP->getCompileUnit()); 397 break; 398 } 399 case ISD::SRCVALUE: 400 ID.AddPointer(cast<SrcValueSDNode>(N)->getValue()); 401 break; 402 case ISD::MEMOPERAND: { 403 const MachineMemOperand &MO = cast<MemOperandSDNode>(N)->MO; 404 MO.Profile(ID); 405 break; 406 } 407 case ISD::FrameIndex: 408 case ISD::TargetFrameIndex: 409 ID.AddInteger(cast<FrameIndexSDNode>(N)->getIndex()); 410 break; 411 case ISD::JumpTable: 412 case ISD::TargetJumpTable: 413 ID.AddInteger(cast<JumpTableSDNode>(N)->getIndex()); 414 break; 415 case ISD::ConstantPool: 416 case ISD::TargetConstantPool: { 417 const ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(N); 418 ID.AddInteger(CP->getAlignment()); 419 ID.AddInteger(CP->getOffset()); 420 if (CP->isMachineConstantPoolEntry()) 421 CP->getMachineCPVal()->AddSelectionDAGCSEId(ID); 422 else 423 ID.AddPointer(CP->getConstVal()); 424 break; 425 } 426 case ISD::CALL: { 427 const CallSDNode *Call = cast<CallSDNode>(N); 428 ID.AddInteger(Call->getCallingConv()); 429 ID.AddInteger(Call->isVarArg()); 430 break; 431 } 432 case ISD::LOAD: { 433 const LoadSDNode *LD = cast<LoadSDNode>(N); 434 ID.AddInteger(LD->getMemoryVT().getRawBits()); 435 ID.AddInteger(LD->getRawSubclassData()); 436 break; 437 } 438 case ISD::STORE: { 439 const StoreSDNode *ST = cast<StoreSDNode>(N); 440 ID.AddInteger(ST->getMemoryVT().getRawBits()); 441 ID.AddInteger(ST->getRawSubclassData()); 442 break; 443 } 444 case ISD::ATOMIC_CMP_SWAP: 445 case ISD::ATOMIC_SWAP: 446 case ISD::ATOMIC_LOAD_ADD: 447 case ISD::ATOMIC_LOAD_SUB: 448 case ISD::ATOMIC_LOAD_AND: 449 case ISD::ATOMIC_LOAD_OR: 450 case ISD::ATOMIC_LOAD_XOR: 451 case ISD::ATOMIC_LOAD_NAND: 452 case ISD::ATOMIC_LOAD_MIN: 453 case ISD::ATOMIC_LOAD_MAX: 454 case ISD::ATOMIC_LOAD_UMIN: 455 case ISD::ATOMIC_LOAD_UMAX: { 456 const AtomicSDNode *AT = cast<AtomicSDNode>(N); 457 ID.AddInteger(AT->getMemoryVT().getRawBits()); 458 ID.AddInteger(AT->getRawSubclassData()); 459 break; 460 } 461 case ISD::VECTOR_SHUFFLE: { 462 const ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N); 463 for (unsigned i = 0, e = N->getValueType(0).getVectorNumElements(); 464 i != e; ++i) 465 ID.AddInteger(SVN->getMaskElt(i)); 466 break; 467 } 468 } // end switch (N->getOpcode()) 469} 470 471/// AddNodeIDNode - Generic routine for adding a nodes info to the NodeID 472/// data. 473static void AddNodeIDNode(FoldingSetNodeID &ID, const SDNode *N) { 474 AddNodeIDOpcode(ID, N->getOpcode()); 475 // Add the return value info. 476 AddNodeIDValueTypes(ID, N->getVTList()); 477 // Add the operand info. 478 AddNodeIDOperands(ID, N->op_begin(), N->getNumOperands()); 479 480 // Handle SDNode leafs with special info. 481 AddNodeIDCustom(ID, N); 482} 483 484/// encodeMemSDNodeFlags - Generic routine for computing a value for use in 485/// the CSE map that carries alignment, volatility, indexing mode, and 486/// extension/truncation information. 487/// 488static inline unsigned 489encodeMemSDNodeFlags(int ConvType, ISD::MemIndexedMode AM, 490 bool isVolatile, unsigned Alignment) { 491 assert((ConvType & 3) == ConvType && 492 "ConvType may not require more than 2 bits!"); 493 assert((AM & 7) == AM && 494 "AM may not require more than 3 bits!"); 495 return ConvType | 496 (AM << 2) | 497 (isVolatile << 5) | 498 ((Log2_32(Alignment) + 1) << 6); 499} 500 501//===----------------------------------------------------------------------===// 502// SelectionDAG Class 503//===----------------------------------------------------------------------===// 504 505/// doNotCSE - Return true if CSE should not be performed for this node. 506static bool doNotCSE(SDNode *N) { 507 if (N->getValueType(0) == MVT::Flag) 508 return true; // Never CSE anything that produces a flag. 509 510 switch (N->getOpcode()) { 511 default: break; 512 case ISD::HANDLENODE: 513 case ISD::DBG_LABEL: 514 case ISD::DBG_STOPPOINT: 515 case ISD::EH_LABEL: 516 case ISD::DECLARE: 517 return true; // Never CSE these nodes. 518 } 519 520 // Check that remaining values produced are not flags. 521 for (unsigned i = 1, e = N->getNumValues(); i != e; ++i) 522 if (N->getValueType(i) == MVT::Flag) 523 return true; // Never CSE anything that produces a flag. 524 525 return false; 526} 527 528/// RemoveDeadNodes - This method deletes all unreachable nodes in the 529/// SelectionDAG. 530void SelectionDAG::RemoveDeadNodes() { 531 // Create a dummy node (which is not added to allnodes), that adds a reference 532 // to the root node, preventing it from being deleted. 533 HandleSDNode Dummy(getRoot()); 534 535 SmallVector<SDNode*, 128> DeadNodes; 536 537 // Add all obviously-dead nodes to the DeadNodes worklist. 538 for (allnodes_iterator I = allnodes_begin(), E = allnodes_end(); I != E; ++I) 539 if (I->use_empty()) 540 DeadNodes.push_back(I); 541 542 RemoveDeadNodes(DeadNodes); 543 544 // If the root changed (e.g. it was a dead load, update the root). 545 setRoot(Dummy.getValue()); 546} 547 548/// RemoveDeadNodes - This method deletes the unreachable nodes in the 549/// given list, and any nodes that become unreachable as a result. 550void SelectionDAG::RemoveDeadNodes(SmallVectorImpl<SDNode *> &DeadNodes, 551 DAGUpdateListener *UpdateListener) { 552 553 // Process the worklist, deleting the nodes and adding their uses to the 554 // worklist. 555 while (!DeadNodes.empty()) { 556 SDNode *N = DeadNodes.pop_back_val(); 557 558 if (UpdateListener) 559 UpdateListener->NodeDeleted(N, 0); 560 561 // Take the node out of the appropriate CSE map. 562 RemoveNodeFromCSEMaps(N); 563 564 // Next, brutally remove the operand list. This is safe to do, as there are 565 // no cycles in the graph. 566 for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ) { 567 SDUse &Use = *I++; 568 SDNode *Operand = Use.getNode(); 569 Use.set(SDValue()); 570 571 // Now that we removed this operand, see if there are no uses of it left. 572 if (Operand->use_empty()) 573 DeadNodes.push_back(Operand); 574 } 575 576 DeallocateNode(N); 577 } 578} 579 580void SelectionDAG::RemoveDeadNode(SDNode *N, DAGUpdateListener *UpdateListener){ 581 SmallVector<SDNode*, 16> DeadNodes(1, N); 582 RemoveDeadNodes(DeadNodes, UpdateListener); 583} 584 585void SelectionDAG::DeleteNode(SDNode *N) { 586 // First take this out of the appropriate CSE map. 587 RemoveNodeFromCSEMaps(N); 588 589 // Finally, remove uses due to operands of this node, remove from the 590 // AllNodes list, and delete the node. 591 DeleteNodeNotInCSEMaps(N); 592} 593 594void SelectionDAG::DeleteNodeNotInCSEMaps(SDNode *N) { 595 assert(N != AllNodes.begin() && "Cannot delete the entry node!"); 596 assert(N->use_empty() && "Cannot delete a node that is not dead!"); 597 598 // Drop all of the operands and decrement used node's use counts. 599 N->DropOperands(); 600 601 DeallocateNode(N); 602} 603 604void SelectionDAG::DeallocateNode(SDNode *N) { 605 if (N->OperandsNeedDelete) 606 delete[] N->OperandList; 607 608 // Set the opcode to DELETED_NODE to help catch bugs when node 609 // memory is reallocated. 610 N->NodeType = ISD::DELETED_NODE; 611 612 NodeAllocator.Deallocate(AllNodes.remove(N)); 613} 614 615/// RemoveNodeFromCSEMaps - Take the specified node out of the CSE map that 616/// correspond to it. This is useful when we're about to delete or repurpose 617/// the node. We don't want future request for structurally identical nodes 618/// to return N anymore. 619bool SelectionDAG::RemoveNodeFromCSEMaps(SDNode *N) { 620 bool Erased = false; 621 switch (N->getOpcode()) { 622 case ISD::EntryToken: 623 assert(0 && "EntryToken should not be in CSEMaps!"); 624 return false; 625 case ISD::HANDLENODE: return false; // noop. 626 case ISD::CONDCODE: 627 assert(CondCodeNodes[cast<CondCodeSDNode>(N)->get()] && 628 "Cond code doesn't exist!"); 629 Erased = CondCodeNodes[cast<CondCodeSDNode>(N)->get()] != 0; 630 CondCodeNodes[cast<CondCodeSDNode>(N)->get()] = 0; 631 break; 632 case ISD::ExternalSymbol: 633 Erased = ExternalSymbols.erase(cast<ExternalSymbolSDNode>(N)->getSymbol()); 634 break; 635 case ISD::TargetExternalSymbol: 636 Erased = 637 TargetExternalSymbols.erase(cast<ExternalSymbolSDNode>(N)->getSymbol()); 638 break; 639 case ISD::VALUETYPE: { 640 MVT VT = cast<VTSDNode>(N)->getVT(); 641 if (VT.isExtended()) { 642 Erased = ExtendedValueTypeNodes.erase(VT); 643 } else { 644 Erased = ValueTypeNodes[VT.getSimpleVT()] != 0; 645 ValueTypeNodes[VT.getSimpleVT()] = 0; 646 } 647 break; 648 } 649 default: 650 // Remove it from the CSE Map. 651 Erased = CSEMap.RemoveNode(N); 652 break; 653 } 654#ifndef NDEBUG 655 // Verify that the node was actually in one of the CSE maps, unless it has a 656 // flag result (which cannot be CSE'd) or is one of the special cases that are 657 // not subject to CSE. 658 if (!Erased && N->getValueType(N->getNumValues()-1) != MVT::Flag && 659 !N->isMachineOpcode() && !doNotCSE(N)) { 660 N->dump(this); 661 cerr << "\n"; 662 assert(0 && "Node is not in map!"); 663 } 664#endif 665 return Erased; 666} 667 668/// AddModifiedNodeToCSEMaps - The specified node has been removed from the CSE 669/// maps and modified in place. Add it back to the CSE maps, unless an identical 670/// node already exists, in which case transfer all its users to the existing 671/// node. This transfer can potentially trigger recursive merging. 672/// 673void 674SelectionDAG::AddModifiedNodeToCSEMaps(SDNode *N, 675 DAGUpdateListener *UpdateListener) { 676 // For node types that aren't CSE'd, just act as if no identical node 677 // already exists. 678 if (!doNotCSE(N)) { 679 SDNode *Existing = CSEMap.GetOrInsertNode(N); 680 if (Existing != N) { 681 // If there was already an existing matching node, use ReplaceAllUsesWith 682 // to replace the dead one with the existing one. This can cause 683 // recursive merging of other unrelated nodes down the line. 684 ReplaceAllUsesWith(N, Existing, UpdateListener); 685 686 // N is now dead. Inform the listener if it exists and delete it. 687 if (UpdateListener) 688 UpdateListener->NodeDeleted(N, Existing); 689 DeleteNodeNotInCSEMaps(N); 690 return; 691 } 692 } 693 694 // If the node doesn't already exist, we updated it. Inform a listener if 695 // it exists. 696 if (UpdateListener) 697 UpdateListener->NodeUpdated(N); 698} 699 700/// FindModifiedNodeSlot - Find a slot for the specified node if its operands 701/// were replaced with those specified. If this node is never memoized, 702/// return null, otherwise return a pointer to the slot it would take. If a 703/// node already exists with these operands, the slot will be non-null. 704SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, SDValue Op, 705 void *&InsertPos) { 706 if (doNotCSE(N)) 707 return 0; 708 709 SDValue Ops[] = { Op }; 710 FoldingSetNodeID ID; 711 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, 1); 712 AddNodeIDCustom(ID, N); 713 return CSEMap.FindNodeOrInsertPos(ID, InsertPos); 714} 715 716/// FindModifiedNodeSlot - Find a slot for the specified node if its operands 717/// were replaced with those specified. If this node is never memoized, 718/// return null, otherwise return a pointer to the slot it would take. If a 719/// node already exists with these operands, the slot will be non-null. 720SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, 721 SDValue Op1, SDValue Op2, 722 void *&InsertPos) { 723 if (doNotCSE(N)) 724 return 0; 725 726 SDValue Ops[] = { Op1, Op2 }; 727 FoldingSetNodeID ID; 728 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, 2); 729 AddNodeIDCustom(ID, N); 730 return CSEMap.FindNodeOrInsertPos(ID, InsertPos); 731} 732 733 734/// FindModifiedNodeSlot - Find a slot for the specified node if its operands 735/// were replaced with those specified. If this node is never memoized, 736/// return null, otherwise return a pointer to the slot it would take. If a 737/// node already exists with these operands, the slot will be non-null. 738SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, 739 const SDValue *Ops,unsigned NumOps, 740 void *&InsertPos) { 741 if (doNotCSE(N)) 742 return 0; 743 744 FoldingSetNodeID ID; 745 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, NumOps); 746 AddNodeIDCustom(ID, N); 747 return CSEMap.FindNodeOrInsertPos(ID, InsertPos); 748} 749 750/// VerifyNode - Sanity check the given node. Aborts if it is invalid. 751void SelectionDAG::VerifyNode(SDNode *N) { 752 switch (N->getOpcode()) { 753 default: 754 break; 755 case ISD::BUILD_PAIR: { 756 MVT VT = N->getValueType(0); 757 assert(N->getNumValues() == 1 && "Too many results!"); 758 assert(!VT.isVector() && (VT.isInteger() || VT.isFloatingPoint()) && 759 "Wrong return type!"); 760 assert(N->getNumOperands() == 2 && "Wrong number of operands!"); 761 assert(N->getOperand(0).getValueType() == N->getOperand(1).getValueType() && 762 "Mismatched operand types!"); 763 assert(N->getOperand(0).getValueType().isInteger() == VT.isInteger() && 764 "Wrong operand type!"); 765 assert(VT.getSizeInBits() == 2 * N->getOperand(0).getValueSizeInBits() && 766 "Wrong return type size"); 767 break; 768 } 769 case ISD::BUILD_VECTOR: { 770 assert(N->getNumValues() == 1 && "Too many results!"); 771 assert(N->getValueType(0).isVector() && "Wrong return type!"); 772 assert(N->getNumOperands() == N->getValueType(0).getVectorNumElements() && 773 "Wrong number of operands!"); 774 MVT EltVT = N->getValueType(0).getVectorElementType(); 775 for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ++I) 776 assert((I->getValueType() == EltVT || 777 (EltVT.isInteger() && I->getValueType().isInteger() && 778 EltVT.bitsLE(I->getValueType()))) && 779 "Wrong operand type!"); 780 break; 781 } 782 } 783} 784 785/// getMVTAlignment - Compute the default alignment value for the 786/// given type. 787/// 788unsigned SelectionDAG::getMVTAlignment(MVT VT) const { 789 const Type *Ty = VT == MVT::iPTR ? 790 PointerType::get(Type::Int8Ty, 0) : 791 VT.getTypeForMVT(); 792 793 return TLI.getTargetData()->getABITypeAlignment(Ty); 794} 795 796// EntryNode could meaningfully have debug info if we can find it... 797SelectionDAG::SelectionDAG(TargetLowering &tli, FunctionLoweringInfo &fli) 798 : TLI(tli), FLI(fli), DW(0), 799 EntryNode(ISD::EntryToken, DebugLoc::getUnknownLoc(), 800 getVTList(MVT::Other)), Root(getEntryNode()) { 801 AllNodes.push_back(&EntryNode); 802} 803 804void SelectionDAG::init(MachineFunction &mf, MachineModuleInfo *mmi, 805 DwarfWriter *dw) { 806 MF = &mf; 807 MMI = mmi; 808 DW = dw; 809} 810 811SelectionDAG::~SelectionDAG() { 812 allnodes_clear(); 813} 814 815void SelectionDAG::allnodes_clear() { 816 assert(&*AllNodes.begin() == &EntryNode); 817 AllNodes.remove(AllNodes.begin()); 818 while (!AllNodes.empty()) 819 DeallocateNode(AllNodes.begin()); 820} 821 822void SelectionDAG::clear() { 823 allnodes_clear(); 824 OperandAllocator.Reset(); 825 CSEMap.clear(); 826 827 ExtendedValueTypeNodes.clear(); 828 ExternalSymbols.clear(); 829 TargetExternalSymbols.clear(); 830 std::fill(CondCodeNodes.begin(), CondCodeNodes.end(), 831 static_cast<CondCodeSDNode*>(0)); 832 std::fill(ValueTypeNodes.begin(), ValueTypeNodes.end(), 833 static_cast<SDNode*>(0)); 834 835 EntryNode.UseList = 0; 836 AllNodes.push_back(&EntryNode); 837 Root = getEntryNode(); 838} 839 840SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, DebugLoc DL, MVT VT) { 841 if (Op.getValueType() == VT) return Op; 842 APInt Imm = APInt::getLowBitsSet(Op.getValueSizeInBits(), 843 VT.getSizeInBits()); 844 return getNode(ISD::AND, DL, Op.getValueType(), Op, 845 getConstant(Imm, Op.getValueType())); 846} 847 848/// getNOT - Create a bitwise NOT operation as (XOR Val, -1). 849/// 850SDValue SelectionDAG::getNOT(DebugLoc DL, SDValue Val, MVT VT) { 851 MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 852 SDValue NegOne = 853 getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT); 854 return getNode(ISD::XOR, DL, VT, Val, NegOne); 855} 856 857SDValue SelectionDAG::getConstant(uint64_t Val, MVT VT, bool isT) { 858 MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 859 assert((EltVT.getSizeInBits() >= 64 || 860 (uint64_t)((int64_t)Val >> EltVT.getSizeInBits()) + 1 < 2) && 861 "getConstant with a uint64_t value that doesn't fit in the type!"); 862 return getConstant(APInt(EltVT.getSizeInBits(), Val), VT, isT); 863} 864 865SDValue SelectionDAG::getConstant(const APInt &Val, MVT VT, bool isT) { 866 return getConstant(*ConstantInt::get(Val), VT, isT); 867} 868 869SDValue SelectionDAG::getConstant(const ConstantInt &Val, MVT VT, bool isT) { 870 assert(VT.isInteger() && "Cannot create FP integer constant!"); 871 872 MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 873 assert(Val.getBitWidth() == EltVT.getSizeInBits() && 874 "APInt size does not match type size!"); 875 876 unsigned Opc = isT ? ISD::TargetConstant : ISD::Constant; 877 FoldingSetNodeID ID; 878 AddNodeIDNode(ID, Opc, getVTList(EltVT), 0, 0); 879 ID.AddPointer(&Val); 880 void *IP = 0; 881 SDNode *N = NULL; 882 if ((N = CSEMap.FindNodeOrInsertPos(ID, IP))) 883 if (!VT.isVector()) 884 return SDValue(N, 0); 885 if (!N) { 886 N = NodeAllocator.Allocate<ConstantSDNode>(); 887 new (N) ConstantSDNode(isT, &Val, EltVT); 888 CSEMap.InsertNode(N, IP); 889 AllNodes.push_back(N); 890 } 891 892 SDValue Result(N, 0); 893 if (VT.isVector()) { 894 SmallVector<SDValue, 8> Ops; 895 Ops.assign(VT.getVectorNumElements(), Result); 896 Result = getNode(ISD::BUILD_VECTOR, DebugLoc::getUnknownLoc(), 897 VT, &Ops[0], Ops.size()); 898 } 899 return Result; 900} 901 902SDValue SelectionDAG::getIntPtrConstant(uint64_t Val, bool isTarget) { 903 return getConstant(Val, TLI.getPointerTy(), isTarget); 904} 905 906 907SDValue SelectionDAG::getConstantFP(const APFloat& V, MVT VT, bool isTarget) { 908 return getConstantFP(*ConstantFP::get(V), VT, isTarget); 909} 910 911SDValue SelectionDAG::getConstantFP(const ConstantFP& V, MVT VT, bool isTarget){ 912 assert(VT.isFloatingPoint() && "Cannot create integer FP constant!"); 913 914 MVT EltVT = 915 VT.isVector() ? VT.getVectorElementType() : VT; 916 917 // Do the map lookup using the actual bit pattern for the floating point 918 // value, so that we don't have problems with 0.0 comparing equal to -0.0, and 919 // we don't have issues with SNANs. 920 unsigned Opc = isTarget ? ISD::TargetConstantFP : ISD::ConstantFP; 921 FoldingSetNodeID ID; 922 AddNodeIDNode(ID, Opc, getVTList(EltVT), 0, 0); 923 ID.AddPointer(&V); 924 void *IP = 0; 925 SDNode *N = NULL; 926 if ((N = CSEMap.FindNodeOrInsertPos(ID, IP))) 927 if (!VT.isVector()) 928 return SDValue(N, 0); 929 if (!N) { 930 N = NodeAllocator.Allocate<ConstantFPSDNode>(); 931 new (N) ConstantFPSDNode(isTarget, &V, EltVT); 932 CSEMap.InsertNode(N, IP); 933 AllNodes.push_back(N); 934 } 935 936 SDValue Result(N, 0); 937 if (VT.isVector()) { 938 SmallVector<SDValue, 8> Ops; 939 Ops.assign(VT.getVectorNumElements(), Result); 940 // FIXME DebugLoc info might be appropriate here 941 Result = getNode(ISD::BUILD_VECTOR, DebugLoc::getUnknownLoc(), 942 VT, &Ops[0], Ops.size()); 943 } 944 return Result; 945} 946 947SDValue SelectionDAG::getConstantFP(double Val, MVT VT, bool isTarget) { 948 MVT EltVT = 949 VT.isVector() ? VT.getVectorElementType() : VT; 950 if (EltVT==MVT::f32) 951 return getConstantFP(APFloat((float)Val), VT, isTarget); 952 else 953 return getConstantFP(APFloat(Val), VT, isTarget); 954} 955 956SDValue SelectionDAG::getGlobalAddress(const GlobalValue *GV, 957 MVT VT, int64_t Offset, 958 bool isTargetGA) { 959 unsigned Opc; 960 961 // Truncate (with sign-extension) the offset value to the pointer size. 962 unsigned BitWidth = TLI.getPointerTy().getSizeInBits(); 963 if (BitWidth < 64) 964 Offset = (Offset << (64 - BitWidth) >> (64 - BitWidth)); 965 966 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV); 967 if (!GVar) { 968 // If GV is an alias then use the aliasee for determining thread-localness. 969 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) 970 GVar = dyn_cast_or_null<GlobalVariable>(GA->resolveAliasedGlobal(false)); 971 } 972 973 if (GVar && GVar->isThreadLocal()) 974 Opc = isTargetGA ? ISD::TargetGlobalTLSAddress : ISD::GlobalTLSAddress; 975 else 976 Opc = isTargetGA ? ISD::TargetGlobalAddress : ISD::GlobalAddress; 977 978 FoldingSetNodeID ID; 979 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 980 ID.AddPointer(GV); 981 ID.AddInteger(Offset); 982 void *IP = 0; 983 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 984 return SDValue(E, 0); 985 SDNode *N = NodeAllocator.Allocate<GlobalAddressSDNode>(); 986 new (N) GlobalAddressSDNode(isTargetGA, GV, VT, Offset); 987 CSEMap.InsertNode(N, IP); 988 AllNodes.push_back(N); 989 return SDValue(N, 0); 990} 991 992SDValue SelectionDAG::getFrameIndex(int FI, MVT VT, bool isTarget) { 993 unsigned Opc = isTarget ? ISD::TargetFrameIndex : ISD::FrameIndex; 994 FoldingSetNodeID ID; 995 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 996 ID.AddInteger(FI); 997 void *IP = 0; 998 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 999 return SDValue(E, 0); 1000 SDNode *N = NodeAllocator.Allocate<FrameIndexSDNode>(); 1001 new (N) FrameIndexSDNode(FI, VT, isTarget); 1002 CSEMap.InsertNode(N, IP); 1003 AllNodes.push_back(N); 1004 return SDValue(N, 0); 1005} 1006 1007SDValue SelectionDAG::getJumpTable(int JTI, MVT VT, bool isTarget){ 1008 unsigned Opc = isTarget ? ISD::TargetJumpTable : ISD::JumpTable; 1009 FoldingSetNodeID ID; 1010 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 1011 ID.AddInteger(JTI); 1012 void *IP = 0; 1013 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1014 return SDValue(E, 0); 1015 SDNode *N = NodeAllocator.Allocate<JumpTableSDNode>(); 1016 new (N) JumpTableSDNode(JTI, VT, isTarget); 1017 CSEMap.InsertNode(N, IP); 1018 AllNodes.push_back(N); 1019 return SDValue(N, 0); 1020} 1021 1022SDValue SelectionDAG::getConstantPool(Constant *C, MVT VT, 1023 unsigned Alignment, int Offset, 1024 bool isTarget) { 1025 if (Alignment == 0) 1026 Alignment = TLI.getTargetData()->getPrefTypeAlignment(C->getType()); 1027 unsigned Opc = isTarget ? ISD::TargetConstantPool : ISD::ConstantPool; 1028 FoldingSetNodeID ID; 1029 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 1030 ID.AddInteger(Alignment); 1031 ID.AddInteger(Offset); 1032 ID.AddPointer(C); 1033 void *IP = 0; 1034 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1035 return SDValue(E, 0); 1036 SDNode *N = NodeAllocator.Allocate<ConstantPoolSDNode>(); 1037 new (N) ConstantPoolSDNode(isTarget, C, VT, Offset, Alignment); 1038 CSEMap.InsertNode(N, IP); 1039 AllNodes.push_back(N); 1040 return SDValue(N, 0); 1041} 1042 1043 1044SDValue SelectionDAG::getConstantPool(MachineConstantPoolValue *C, MVT VT, 1045 unsigned Alignment, int Offset, 1046 bool isTarget) { 1047 if (Alignment == 0) 1048 Alignment = TLI.getTargetData()->getPrefTypeAlignment(C->getType()); 1049 unsigned Opc = isTarget ? ISD::TargetConstantPool : ISD::ConstantPool; 1050 FoldingSetNodeID ID; 1051 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 1052 ID.AddInteger(Alignment); 1053 ID.AddInteger(Offset); 1054 C->AddSelectionDAGCSEId(ID); 1055 void *IP = 0; 1056 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1057 return SDValue(E, 0); 1058 SDNode *N = NodeAllocator.Allocate<ConstantPoolSDNode>(); 1059 new (N) ConstantPoolSDNode(isTarget, C, VT, Offset, Alignment); 1060 CSEMap.InsertNode(N, IP); 1061 AllNodes.push_back(N); 1062 return SDValue(N, 0); 1063} 1064 1065SDValue SelectionDAG::getBasicBlock(MachineBasicBlock *MBB) { 1066 FoldingSetNodeID ID; 1067 AddNodeIDNode(ID, ISD::BasicBlock, getVTList(MVT::Other), 0, 0); 1068 ID.AddPointer(MBB); 1069 void *IP = 0; 1070 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1071 return SDValue(E, 0); 1072 SDNode *N = NodeAllocator.Allocate<BasicBlockSDNode>(); 1073 new (N) BasicBlockSDNode(MBB); 1074 CSEMap.InsertNode(N, IP); 1075 AllNodes.push_back(N); 1076 return SDValue(N, 0); 1077} 1078 1079SDValue SelectionDAG::getArgFlags(ISD::ArgFlagsTy Flags) { 1080 FoldingSetNodeID ID; 1081 AddNodeIDNode(ID, ISD::ARG_FLAGS, getVTList(MVT::Other), 0, 0); 1082 ID.AddInteger(Flags.getRawBits()); 1083 void *IP = 0; 1084 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1085 return SDValue(E, 0); 1086 SDNode *N = NodeAllocator.Allocate<ARG_FLAGSSDNode>(); 1087 new (N) ARG_FLAGSSDNode(Flags); 1088 CSEMap.InsertNode(N, IP); 1089 AllNodes.push_back(N); 1090 return SDValue(N, 0); 1091} 1092 1093SDValue SelectionDAG::getValueType(MVT VT) { 1094 if (VT.isSimple() && (unsigned)VT.getSimpleVT() >= ValueTypeNodes.size()) 1095 ValueTypeNodes.resize(VT.getSimpleVT()+1); 1096 1097 SDNode *&N = VT.isExtended() ? 1098 ExtendedValueTypeNodes[VT] : ValueTypeNodes[VT.getSimpleVT()]; 1099 1100 if (N) return SDValue(N, 0); 1101 N = NodeAllocator.Allocate<VTSDNode>(); 1102 new (N) VTSDNode(VT); 1103 AllNodes.push_back(N); 1104 return SDValue(N, 0); 1105} 1106 1107SDValue SelectionDAG::getExternalSymbol(const char *Sym, MVT VT) { 1108 SDNode *&N = ExternalSymbols[Sym]; 1109 if (N) return SDValue(N, 0); 1110 N = NodeAllocator.Allocate<ExternalSymbolSDNode>(); 1111 new (N) ExternalSymbolSDNode(false, Sym, VT); 1112 AllNodes.push_back(N); 1113 return SDValue(N, 0); 1114} 1115 1116SDValue SelectionDAG::getTargetExternalSymbol(const char *Sym, MVT VT) { 1117 SDNode *&N = TargetExternalSymbols[Sym]; 1118 if (N) return SDValue(N, 0); 1119 N = NodeAllocator.Allocate<ExternalSymbolSDNode>(); 1120 new (N) ExternalSymbolSDNode(true, Sym, VT); 1121 AllNodes.push_back(N); 1122 return SDValue(N, 0); 1123} 1124 1125SDValue SelectionDAG::getCondCode(ISD::CondCode Cond) { 1126 if ((unsigned)Cond >= CondCodeNodes.size()) 1127 CondCodeNodes.resize(Cond+1); 1128 1129 if (CondCodeNodes[Cond] == 0) { 1130 CondCodeSDNode *N = NodeAllocator.Allocate<CondCodeSDNode>(); 1131 new (N) CondCodeSDNode(Cond); 1132 CondCodeNodes[Cond] = N; 1133 AllNodes.push_back(N); 1134 } 1135 return SDValue(CondCodeNodes[Cond], 0); 1136} 1137 1138// commuteShuffle - swaps the values of N1 and N2, and swaps all indices in 1139// the shuffle mask M that point at N1 to point at N2, and indices that point 1140// N2 to point at N1. 1141static void commuteShuffle(SDValue &N1, SDValue &N2, SmallVectorImpl<int> &M) { 1142 std::swap(N1, N2); 1143 int NElts = M.size(); 1144 for (int i = 0; i != NElts; ++i) { 1145 if (M[i] >= NElts) 1146 M[i] -= NElts; 1147 else if (M[i] >= 0) 1148 M[i] += NElts; 1149 } 1150} 1151 1152SDValue SelectionDAG::getVectorShuffle(MVT VT, DebugLoc dl, SDValue N1, 1153 SDValue N2, const int *Mask) { 1154 assert(N1.getValueType() == N2.getValueType() && "Invalid VECTOR_SHUFFLE"); 1155 assert(VT.isVector() && N1.getValueType().isVector() && 1156 "Vector Shuffle VTs must be a vectors"); 1157 assert(VT.getVectorElementType() == N1.getValueType().getVectorElementType() 1158 && "Vector Shuffle VTs must have same element type"); 1159 1160 // Canonicalize shuffle undef, undef -> undef 1161 if (N1.getOpcode() == ISD::UNDEF && N2.getOpcode() == ISD::UNDEF) 1162 return N1; 1163 1164 // Validate that all indices in Mask are within the range of the elements 1165 // input to the shuffle. 1166 unsigned NElts = VT.getVectorNumElements(); 1167 SmallVector<int, 8> MaskVec; 1168 for (unsigned i = 0; i != NElts; ++i) { 1169 assert(Mask[i] < (int)(NElts * 2) && "Index out of range"); 1170 MaskVec.push_back(Mask[i]); 1171 } 1172 1173 // Canonicalize shuffle v, v -> v, undef 1174 if (N1 == N2) { 1175 N2 = getUNDEF(VT); 1176 for (unsigned i = 0; i != NElts; ++i) 1177 if (MaskVec[i] >= (int)NElts) MaskVec[i] -= NElts; 1178 } 1179 1180 // Canonicalize shuffle undef, v -> v, undef. Commute the shuffle mask. 1181 if (N1.getOpcode() == ISD::UNDEF) 1182 commuteShuffle(N1, N2, MaskVec); 1183 1184 // Canonicalize all index into lhs, -> shuffle lhs, undef 1185 // Canonicalize all index into rhs, -> shuffle rhs, undef 1186 bool AllLHS = true, AllRHS = true; 1187 bool N2Undef = N2.getOpcode() == ISD::UNDEF; 1188 for (unsigned i = 0; i != NElts; ++i) { 1189 if (MaskVec[i] >= (int)NElts) { 1190 if (N2Undef) 1191 MaskVec[i] = -1; 1192 else 1193 AllLHS = false; 1194 } else if (MaskVec[i] >= 0) { 1195 AllRHS = false; 1196 } 1197 } 1198 if (AllLHS && AllRHS) 1199 return getUNDEF(VT); 1200 if (AllLHS && !N2Undef) 1201 N2 = getUNDEF(VT); 1202 if (AllRHS) { 1203 N1 = getUNDEF(VT); 1204 commuteShuffle(N1, N2, MaskVec); 1205 } 1206 1207 // If Identity shuffle, or all shuffle in to undef, return that node. 1208 bool AllUndef = true; 1209 bool Identity = true; 1210 for (unsigned i = 0; i != NElts; ++i) { 1211 if (MaskVec[i] >= 0 && MaskVec[i] != (int)i) Identity = false; 1212 if (MaskVec[i] >= 0) AllUndef = false; 1213 } 1214 if (Identity) 1215 return N1; 1216 if (AllUndef) 1217 return getUNDEF(VT); 1218 1219 FoldingSetNodeID ID; 1220 SDValue Ops[2] = { N1, N2 }; 1221 AddNodeIDNode(ID, ISD::VECTOR_SHUFFLE, getVTList(VT), Ops, 2); 1222 for (unsigned i = 0; i != NElts; ++i) 1223 ID.AddInteger(MaskVec[i]); 1224 1225 void* IP = 0; 1226 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1227 return SDValue(E, 0); 1228 1229 // Allocate the mask array for the node out of the BumpPtrAllocator, since 1230 // SDNode doesn't have access to it. This memory will be "leaked" when 1231 // the node is deallocated, but recovered when the NodeAllocator is released. 1232 int *MaskAlloc = OperandAllocator.Allocate<int>(NElts); 1233 memcpy(MaskAlloc, &MaskVec[0], NElts * sizeof(int)); 1234 1235 ShuffleVectorSDNode *N = NodeAllocator.Allocate<ShuffleVectorSDNode>(); 1236 new (N) ShuffleVectorSDNode(VT, dl, N1, N2, MaskAlloc); 1237 CSEMap.InsertNode(N, IP); 1238 AllNodes.push_back(N); 1239 return SDValue(N, 0); 1240} 1241 1242SDValue SelectionDAG::getConvertRndSat(MVT VT, DebugLoc dl, 1243 SDValue Val, SDValue DTy, 1244 SDValue STy, SDValue Rnd, SDValue Sat, 1245 ISD::CvtCode Code) { 1246 // If the src and dest types are the same and the conversion is between 1247 // integer types of the same sign or two floats, no conversion is necessary. 1248 if (DTy == STy && 1249 (Code == ISD::CVT_UU || Code == ISD::CVT_SS || Code == ISD::CVT_FF)) 1250 return Val; 1251 1252 FoldingSetNodeID ID; 1253 void* IP = 0; 1254 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1255 return SDValue(E, 0); 1256 CvtRndSatSDNode *N = NodeAllocator.Allocate<CvtRndSatSDNode>(); 1257 SDValue Ops[] = { Val, DTy, STy, Rnd, Sat }; 1258 new (N) CvtRndSatSDNode(VT, dl, Ops, 5, Code); 1259 CSEMap.InsertNode(N, IP); 1260 AllNodes.push_back(N); 1261 return SDValue(N, 0); 1262} 1263 1264SDValue SelectionDAG::getRegister(unsigned RegNo, MVT VT) { 1265 FoldingSetNodeID ID; 1266 AddNodeIDNode(ID, ISD::Register, getVTList(VT), 0, 0); 1267 ID.AddInteger(RegNo); 1268 void *IP = 0; 1269 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1270 return SDValue(E, 0); 1271 SDNode *N = NodeAllocator.Allocate<RegisterSDNode>(); 1272 new (N) RegisterSDNode(RegNo, VT); 1273 CSEMap.InsertNode(N, IP); 1274 AllNodes.push_back(N); 1275 return SDValue(N, 0); 1276} 1277 1278SDValue SelectionDAG::getDbgStopPoint(DebugLoc DL, SDValue Root, 1279 unsigned Line, unsigned Col, 1280 Value *CU) { 1281 SDNode *N = NodeAllocator.Allocate<DbgStopPointSDNode>(); 1282 new (N) DbgStopPointSDNode(Root, Line, Col, CU); 1283 N->setDebugLoc(DL); 1284 AllNodes.push_back(N); 1285 return SDValue(N, 0); 1286} 1287 1288SDValue SelectionDAG::getLabel(unsigned Opcode, DebugLoc dl, 1289 SDValue Root, 1290 unsigned LabelID) { 1291 FoldingSetNodeID ID; 1292 SDValue Ops[] = { Root }; 1293 AddNodeIDNode(ID, Opcode, getVTList(MVT::Other), &Ops[0], 1); 1294 ID.AddInteger(LabelID); 1295 void *IP = 0; 1296 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1297 return SDValue(E, 0); 1298 SDNode *N = NodeAllocator.Allocate<LabelSDNode>(); 1299 new (N) LabelSDNode(Opcode, dl, Root, LabelID); 1300 CSEMap.InsertNode(N, IP); 1301 AllNodes.push_back(N); 1302 return SDValue(N, 0); 1303} 1304 1305SDValue SelectionDAG::getSrcValue(const Value *V) { 1306 assert((!V || isa<PointerType>(V->getType())) && 1307 "SrcValue is not a pointer?"); 1308 1309 FoldingSetNodeID ID; 1310 AddNodeIDNode(ID, ISD::SRCVALUE, getVTList(MVT::Other), 0, 0); 1311 ID.AddPointer(V); 1312 1313 void *IP = 0; 1314 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1315 return SDValue(E, 0); 1316 1317 SDNode *N = NodeAllocator.Allocate<SrcValueSDNode>(); 1318 new (N) SrcValueSDNode(V); 1319 CSEMap.InsertNode(N, IP); 1320 AllNodes.push_back(N); 1321 return SDValue(N, 0); 1322} 1323 1324SDValue SelectionDAG::getMemOperand(const MachineMemOperand &MO) { 1325#ifndef NDEBUG 1326 const Value *v = MO.getValue(); 1327 assert((!v || isa<PointerType>(v->getType())) && 1328 "SrcValue is not a pointer?"); 1329#endif 1330 1331 FoldingSetNodeID ID; 1332 AddNodeIDNode(ID, ISD::MEMOPERAND, getVTList(MVT::Other), 0, 0); 1333 MO.Profile(ID); 1334 1335 void *IP = 0; 1336 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1337 return SDValue(E, 0); 1338 1339 SDNode *N = NodeAllocator.Allocate<MemOperandSDNode>(); 1340 new (N) MemOperandSDNode(MO); 1341 CSEMap.InsertNode(N, IP); 1342 AllNodes.push_back(N); 1343 return SDValue(N, 0); 1344} 1345 1346/// getShiftAmountOperand - Return the specified value casted to 1347/// the target's desired shift amount type. 1348SDValue SelectionDAG::getShiftAmountOperand(SDValue Op) { 1349 MVT OpTy = Op.getValueType(); 1350 MVT ShTy = TLI.getShiftAmountTy(); 1351 if (OpTy == ShTy || OpTy.isVector()) return Op; 1352 1353 ISD::NodeType Opcode = OpTy.bitsGT(ShTy) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; 1354 return getNode(Opcode, Op.getDebugLoc(), ShTy, Op); 1355} 1356 1357/// CreateStackTemporary - Create a stack temporary, suitable for holding the 1358/// specified value type. 1359SDValue SelectionDAG::CreateStackTemporary(MVT VT, unsigned minAlign) { 1360 MachineFrameInfo *FrameInfo = getMachineFunction().getFrameInfo(); 1361 unsigned ByteSize = VT.getStoreSizeInBits()/8; 1362 const Type *Ty = VT.getTypeForMVT(); 1363 unsigned StackAlign = 1364 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), minAlign); 1365 1366 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, StackAlign); 1367 return getFrameIndex(FrameIdx, TLI.getPointerTy()); 1368} 1369 1370/// CreateStackTemporary - Create a stack temporary suitable for holding 1371/// either of the specified value types. 1372SDValue SelectionDAG::CreateStackTemporary(MVT VT1, MVT VT2) { 1373 unsigned Bytes = std::max(VT1.getStoreSizeInBits(), 1374 VT2.getStoreSizeInBits())/8; 1375 const Type *Ty1 = VT1.getTypeForMVT(); 1376 const Type *Ty2 = VT2.getTypeForMVT(); 1377 const TargetData *TD = TLI.getTargetData(); 1378 unsigned Align = std::max(TD->getPrefTypeAlignment(Ty1), 1379 TD->getPrefTypeAlignment(Ty2)); 1380 1381 MachineFrameInfo *FrameInfo = getMachineFunction().getFrameInfo(); 1382 int FrameIdx = FrameInfo->CreateStackObject(Bytes, Align); 1383 return getFrameIndex(FrameIdx, TLI.getPointerTy()); 1384} 1385 1386SDValue SelectionDAG::FoldSetCC(MVT VT, SDValue N1, 1387 SDValue N2, ISD::CondCode Cond, DebugLoc dl) { 1388 // These setcc operations always fold. 1389 switch (Cond) { 1390 default: break; 1391 case ISD::SETFALSE: 1392 case ISD::SETFALSE2: return getConstant(0, VT); 1393 case ISD::SETTRUE: 1394 case ISD::SETTRUE2: return getConstant(1, VT); 1395 1396 case ISD::SETOEQ: 1397 case ISD::SETOGT: 1398 case ISD::SETOGE: 1399 case ISD::SETOLT: 1400 case ISD::SETOLE: 1401 case ISD::SETONE: 1402 case ISD::SETO: 1403 case ISD::SETUO: 1404 case ISD::SETUEQ: 1405 case ISD::SETUNE: 1406 assert(!N1.getValueType().isInteger() && "Illegal setcc for integer!"); 1407 break; 1408 } 1409 1410 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode())) { 1411 const APInt &C2 = N2C->getAPIntValue(); 1412 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) { 1413 const APInt &C1 = N1C->getAPIntValue(); 1414 1415 switch (Cond) { 1416 default: assert(0 && "Unknown integer setcc!"); 1417 case ISD::SETEQ: return getConstant(C1 == C2, VT); 1418 case ISD::SETNE: return getConstant(C1 != C2, VT); 1419 case ISD::SETULT: return getConstant(C1.ult(C2), VT); 1420 case ISD::SETUGT: return getConstant(C1.ugt(C2), VT); 1421 case ISD::SETULE: return getConstant(C1.ule(C2), VT); 1422 case ISD::SETUGE: return getConstant(C1.uge(C2), VT); 1423 case ISD::SETLT: return getConstant(C1.slt(C2), VT); 1424 case ISD::SETGT: return getConstant(C1.sgt(C2), VT); 1425 case ISD::SETLE: return getConstant(C1.sle(C2), VT); 1426 case ISD::SETGE: return getConstant(C1.sge(C2), VT); 1427 } 1428 } 1429 } 1430 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.getNode())) { 1431 if (ConstantFPSDNode *N2C = dyn_cast<ConstantFPSDNode>(N2.getNode())) { 1432 // No compile time operations on this type yet. 1433 if (N1C->getValueType(0) == MVT::ppcf128) 1434 return SDValue(); 1435 1436 APFloat::cmpResult R = N1C->getValueAPF().compare(N2C->getValueAPF()); 1437 switch (Cond) { 1438 default: break; 1439 case ISD::SETEQ: if (R==APFloat::cmpUnordered) 1440 return getUNDEF(VT); 1441 // fall through 1442 case ISD::SETOEQ: return getConstant(R==APFloat::cmpEqual, VT); 1443 case ISD::SETNE: if (R==APFloat::cmpUnordered) 1444 return getUNDEF(VT); 1445 // fall through 1446 case ISD::SETONE: return getConstant(R==APFloat::cmpGreaterThan || 1447 R==APFloat::cmpLessThan, VT); 1448 case ISD::SETLT: if (R==APFloat::cmpUnordered) 1449 return getUNDEF(VT); 1450 // fall through 1451 case ISD::SETOLT: return getConstant(R==APFloat::cmpLessThan, VT); 1452 case ISD::SETGT: if (R==APFloat::cmpUnordered) 1453 return getUNDEF(VT); 1454 // fall through 1455 case ISD::SETOGT: return getConstant(R==APFloat::cmpGreaterThan, VT); 1456 case ISD::SETLE: if (R==APFloat::cmpUnordered) 1457 return getUNDEF(VT); 1458 // fall through 1459 case ISD::SETOLE: return getConstant(R==APFloat::cmpLessThan || 1460 R==APFloat::cmpEqual, VT); 1461 case ISD::SETGE: if (R==APFloat::cmpUnordered) 1462 return getUNDEF(VT); 1463 // fall through 1464 case ISD::SETOGE: return getConstant(R==APFloat::cmpGreaterThan || 1465 R==APFloat::cmpEqual, VT); 1466 case ISD::SETO: return getConstant(R!=APFloat::cmpUnordered, VT); 1467 case ISD::SETUO: return getConstant(R==APFloat::cmpUnordered, VT); 1468 case ISD::SETUEQ: return getConstant(R==APFloat::cmpUnordered || 1469 R==APFloat::cmpEqual, VT); 1470 case ISD::SETUNE: return getConstant(R!=APFloat::cmpEqual, VT); 1471 case ISD::SETULT: return getConstant(R==APFloat::cmpUnordered || 1472 R==APFloat::cmpLessThan, VT); 1473 case ISD::SETUGT: return getConstant(R==APFloat::cmpGreaterThan || 1474 R==APFloat::cmpUnordered, VT); 1475 case ISD::SETULE: return getConstant(R!=APFloat::cmpGreaterThan, VT); 1476 case ISD::SETUGE: return getConstant(R!=APFloat::cmpLessThan, VT); 1477 } 1478 } else { 1479 // Ensure that the constant occurs on the RHS. 1480 return getSetCC(dl, VT, N2, N1, ISD::getSetCCSwappedOperands(Cond)); 1481 } 1482 } 1483 1484 // Could not fold it. 1485 return SDValue(); 1486} 1487 1488/// SignBitIsZero - Return true if the sign bit of Op is known to be zero. We 1489/// use this predicate to simplify operations downstream. 1490bool SelectionDAG::SignBitIsZero(SDValue Op, unsigned Depth) const { 1491 unsigned BitWidth = Op.getValueSizeInBits(); 1492 return MaskedValueIsZero(Op, APInt::getSignBit(BitWidth), Depth); 1493} 1494 1495/// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero. We use 1496/// this predicate to simplify operations downstream. Mask is known to be zero 1497/// for bits that V cannot have. 1498bool SelectionDAG::MaskedValueIsZero(SDValue Op, const APInt &Mask, 1499 unsigned Depth) const { 1500 APInt KnownZero, KnownOne; 1501 ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth); 1502 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1503 return (KnownZero & Mask) == Mask; 1504} 1505 1506/// ComputeMaskedBits - Determine which of the bits specified in Mask are 1507/// known to be either zero or one and return them in the KnownZero/KnownOne 1508/// bitsets. This code only analyzes bits in Mask, in order to short-circuit 1509/// processing. 1510void SelectionDAG::ComputeMaskedBits(SDValue Op, const APInt &Mask, 1511 APInt &KnownZero, APInt &KnownOne, 1512 unsigned Depth) const { 1513 unsigned BitWidth = Mask.getBitWidth(); 1514 assert(BitWidth == Op.getValueType().getSizeInBits() && 1515 "Mask size mismatches value type size!"); 1516 1517 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything. 1518 if (Depth == 6 || Mask == 0) 1519 return; // Limit search depth. 1520 1521 APInt KnownZero2, KnownOne2; 1522 1523 switch (Op.getOpcode()) { 1524 case ISD::Constant: 1525 // We know all of the bits for a constant! 1526 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & Mask; 1527 KnownZero = ~KnownOne & Mask; 1528 return; 1529 case ISD::AND: 1530 // If either the LHS or the RHS are Zero, the result is zero. 1531 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1532 ComputeMaskedBits(Op.getOperand(0), Mask & ~KnownZero, 1533 KnownZero2, KnownOne2, Depth+1); 1534 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1535 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1536 1537 // Output known-1 bits are only known if set in both the LHS & RHS. 1538 KnownOne &= KnownOne2; 1539 // Output known-0 are known to be clear if zero in either the LHS | RHS. 1540 KnownZero |= KnownZero2; 1541 return; 1542 case ISD::OR: 1543 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1544 ComputeMaskedBits(Op.getOperand(0), Mask & ~KnownOne, 1545 KnownZero2, KnownOne2, Depth+1); 1546 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1547 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1548 1549 // Output known-0 bits are only known if clear in both the LHS & RHS. 1550 KnownZero &= KnownZero2; 1551 // Output known-1 are known to be set if set in either the LHS | RHS. 1552 KnownOne |= KnownOne2; 1553 return; 1554 case ISD::XOR: { 1555 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1556 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1); 1557 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1558 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1559 1560 // Output known-0 bits are known if clear or set in both the LHS & RHS. 1561 APInt KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 1562 // Output known-1 are known to be set if set in only one of the LHS, RHS. 1563 KnownOne = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 1564 KnownZero = KnownZeroOut; 1565 return; 1566 } 1567 case ISD::MUL: { 1568 APInt Mask2 = APInt::getAllOnesValue(BitWidth); 1569 ComputeMaskedBits(Op.getOperand(1), Mask2, KnownZero, KnownOne, Depth+1); 1570 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero2, KnownOne2, Depth+1); 1571 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1572 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1573 1574 // If low bits are zero in either operand, output low known-0 bits. 1575 // Also compute a conserative estimate for high known-0 bits. 1576 // More trickiness is possible, but this is sufficient for the 1577 // interesting case of alignment computation. 1578 KnownOne.clear(); 1579 unsigned TrailZ = KnownZero.countTrailingOnes() + 1580 KnownZero2.countTrailingOnes(); 1581 unsigned LeadZ = std::max(KnownZero.countLeadingOnes() + 1582 KnownZero2.countLeadingOnes(), 1583 BitWidth) - BitWidth; 1584 1585 TrailZ = std::min(TrailZ, BitWidth); 1586 LeadZ = std::min(LeadZ, BitWidth); 1587 KnownZero = APInt::getLowBitsSet(BitWidth, TrailZ) | 1588 APInt::getHighBitsSet(BitWidth, LeadZ); 1589 KnownZero &= Mask; 1590 return; 1591 } 1592 case ISD::UDIV: { 1593 // For the purposes of computing leading zeros we can conservatively 1594 // treat a udiv as a logical right shift by the power of 2 known to 1595 // be less than the denominator. 1596 APInt AllOnes = APInt::getAllOnesValue(BitWidth); 1597 ComputeMaskedBits(Op.getOperand(0), 1598 AllOnes, KnownZero2, KnownOne2, Depth+1); 1599 unsigned LeadZ = KnownZero2.countLeadingOnes(); 1600 1601 KnownOne2.clear(); 1602 KnownZero2.clear(); 1603 ComputeMaskedBits(Op.getOperand(1), 1604 AllOnes, KnownZero2, KnownOne2, Depth+1); 1605 unsigned RHSUnknownLeadingOnes = KnownOne2.countLeadingZeros(); 1606 if (RHSUnknownLeadingOnes != BitWidth) 1607 LeadZ = std::min(BitWidth, 1608 LeadZ + BitWidth - RHSUnknownLeadingOnes - 1); 1609 1610 KnownZero = APInt::getHighBitsSet(BitWidth, LeadZ) & Mask; 1611 return; 1612 } 1613 case ISD::SELECT: 1614 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero, KnownOne, Depth+1); 1615 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero2, KnownOne2, Depth+1); 1616 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1617 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1618 1619 // Only known if known in both the LHS and RHS. 1620 KnownOne &= KnownOne2; 1621 KnownZero &= KnownZero2; 1622 return; 1623 case ISD::SELECT_CC: 1624 ComputeMaskedBits(Op.getOperand(3), Mask, KnownZero, KnownOne, Depth+1); 1625 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero2, KnownOne2, Depth+1); 1626 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1627 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1628 1629 // Only known if known in both the LHS and RHS. 1630 KnownOne &= KnownOne2; 1631 KnownZero &= KnownZero2; 1632 return; 1633 case ISD::SADDO: 1634 case ISD::UADDO: 1635 case ISD::SSUBO: 1636 case ISD::USUBO: 1637 case ISD::SMULO: 1638 case ISD::UMULO: 1639 if (Op.getResNo() != 1) 1640 return; 1641 // The boolean result conforms to getBooleanContents. Fall through. 1642 case ISD::SETCC: 1643 // If we know the result of a setcc has the top bits zero, use this info. 1644 if (TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent && 1645 BitWidth > 1) 1646 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1); 1647 return; 1648 case ISD::SHL: 1649 // (shl X, C1) & C2 == 0 iff (X & C2 >>u C1) == 0 1650 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1651 unsigned ShAmt = SA->getZExtValue(); 1652 1653 // If the shift count is an invalid immediate, don't do anything. 1654 if (ShAmt >= BitWidth) 1655 return; 1656 1657 ComputeMaskedBits(Op.getOperand(0), Mask.lshr(ShAmt), 1658 KnownZero, KnownOne, Depth+1); 1659 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1660 KnownZero <<= ShAmt; 1661 KnownOne <<= ShAmt; 1662 // low bits known zero. 1663 KnownZero |= APInt::getLowBitsSet(BitWidth, ShAmt); 1664 } 1665 return; 1666 case ISD::SRL: 1667 // (ushr X, C1) & C2 == 0 iff (-1 >> C1) & C2 == 0 1668 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1669 unsigned ShAmt = SA->getZExtValue(); 1670 1671 // If the shift count is an invalid immediate, don't do anything. 1672 if (ShAmt >= BitWidth) 1673 return; 1674 1675 ComputeMaskedBits(Op.getOperand(0), (Mask << ShAmt), 1676 KnownZero, KnownOne, Depth+1); 1677 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1678 KnownZero = KnownZero.lshr(ShAmt); 1679 KnownOne = KnownOne.lshr(ShAmt); 1680 1681 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt) & Mask; 1682 KnownZero |= HighBits; // High bits known zero. 1683 } 1684 return; 1685 case ISD::SRA: 1686 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1687 unsigned ShAmt = SA->getZExtValue(); 1688 1689 // If the shift count is an invalid immediate, don't do anything. 1690 if (ShAmt >= BitWidth) 1691 return; 1692 1693 APInt InDemandedMask = (Mask << ShAmt); 1694 // If any of the demanded bits are produced by the sign extension, we also 1695 // demand the input sign bit. 1696 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt) & Mask; 1697 if (HighBits.getBoolValue()) 1698 InDemandedMask |= APInt::getSignBit(BitWidth); 1699 1700 ComputeMaskedBits(Op.getOperand(0), InDemandedMask, KnownZero, KnownOne, 1701 Depth+1); 1702 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1703 KnownZero = KnownZero.lshr(ShAmt); 1704 KnownOne = KnownOne.lshr(ShAmt); 1705 1706 // Handle the sign bits. 1707 APInt SignBit = APInt::getSignBit(BitWidth); 1708 SignBit = SignBit.lshr(ShAmt); // Adjust to where it is now in the mask. 1709 1710 if (KnownZero.intersects(SignBit)) { 1711 KnownZero |= HighBits; // New bits are known zero. 1712 } else if (KnownOne.intersects(SignBit)) { 1713 KnownOne |= HighBits; // New bits are known one. 1714 } 1715 } 1716 return; 1717 case ISD::SIGN_EXTEND_INREG: { 1718 MVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1719 unsigned EBits = EVT.getSizeInBits(); 1720 1721 // Sign extension. Compute the demanded bits in the result that are not 1722 // present in the input. 1723 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - EBits) & Mask; 1724 1725 APInt InSignBit = APInt::getSignBit(EBits); 1726 APInt InputDemandedBits = Mask & APInt::getLowBitsSet(BitWidth, EBits); 1727 1728 // If the sign extended bits are demanded, we know that the sign 1729 // bit is demanded. 1730 InSignBit.zext(BitWidth); 1731 if (NewBits.getBoolValue()) 1732 InputDemandedBits |= InSignBit; 1733 1734 ComputeMaskedBits(Op.getOperand(0), InputDemandedBits, 1735 KnownZero, KnownOne, Depth+1); 1736 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1737 1738 // If the sign bit of the input is known set or clear, then we know the 1739 // top bits of the result. 1740 if (KnownZero.intersects(InSignBit)) { // Input sign bit known clear 1741 KnownZero |= NewBits; 1742 KnownOne &= ~NewBits; 1743 } else if (KnownOne.intersects(InSignBit)) { // Input sign bit known set 1744 KnownOne |= NewBits; 1745 KnownZero &= ~NewBits; 1746 } else { // Input sign bit unknown 1747 KnownZero &= ~NewBits; 1748 KnownOne &= ~NewBits; 1749 } 1750 return; 1751 } 1752 case ISD::CTTZ: 1753 case ISD::CTLZ: 1754 case ISD::CTPOP: { 1755 unsigned LowBits = Log2_32(BitWidth)+1; 1756 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - LowBits); 1757 KnownOne.clear(); 1758 return; 1759 } 1760 case ISD::LOAD: { 1761 if (ISD::isZEXTLoad(Op.getNode())) { 1762 LoadSDNode *LD = cast<LoadSDNode>(Op); 1763 MVT VT = LD->getMemoryVT(); 1764 unsigned MemBits = VT.getSizeInBits(); 1765 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits) & Mask; 1766 } 1767 return; 1768 } 1769 case ISD::ZERO_EXTEND: { 1770 MVT InVT = Op.getOperand(0).getValueType(); 1771 unsigned InBits = InVT.getSizeInBits(); 1772 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - InBits) & Mask; 1773 APInt InMask = Mask; 1774 InMask.trunc(InBits); 1775 KnownZero.trunc(InBits); 1776 KnownOne.trunc(InBits); 1777 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1778 KnownZero.zext(BitWidth); 1779 KnownOne.zext(BitWidth); 1780 KnownZero |= NewBits; 1781 return; 1782 } 1783 case ISD::SIGN_EXTEND: { 1784 MVT InVT = Op.getOperand(0).getValueType(); 1785 unsigned InBits = InVT.getSizeInBits(); 1786 APInt InSignBit = APInt::getSignBit(InBits); 1787 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - InBits) & Mask; 1788 APInt InMask = Mask; 1789 InMask.trunc(InBits); 1790 1791 // If any of the sign extended bits are demanded, we know that the sign 1792 // bit is demanded. Temporarily set this bit in the mask for our callee. 1793 if (NewBits.getBoolValue()) 1794 InMask |= InSignBit; 1795 1796 KnownZero.trunc(InBits); 1797 KnownOne.trunc(InBits); 1798 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1799 1800 // Note if the sign bit is known to be zero or one. 1801 bool SignBitKnownZero = KnownZero.isNegative(); 1802 bool SignBitKnownOne = KnownOne.isNegative(); 1803 assert(!(SignBitKnownZero && SignBitKnownOne) && 1804 "Sign bit can't be known to be both zero and one!"); 1805 1806 // If the sign bit wasn't actually demanded by our caller, we don't 1807 // want it set in the KnownZero and KnownOne result values. Reset the 1808 // mask and reapply it to the result values. 1809 InMask = Mask; 1810 InMask.trunc(InBits); 1811 KnownZero &= InMask; 1812 KnownOne &= InMask; 1813 1814 KnownZero.zext(BitWidth); 1815 KnownOne.zext(BitWidth); 1816 1817 // If the sign bit is known zero or one, the top bits match. 1818 if (SignBitKnownZero) 1819 KnownZero |= NewBits; 1820 else if (SignBitKnownOne) 1821 KnownOne |= NewBits; 1822 return; 1823 } 1824 case ISD::ANY_EXTEND: { 1825 MVT InVT = Op.getOperand(0).getValueType(); 1826 unsigned InBits = InVT.getSizeInBits(); 1827 APInt InMask = Mask; 1828 InMask.trunc(InBits); 1829 KnownZero.trunc(InBits); 1830 KnownOne.trunc(InBits); 1831 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1832 KnownZero.zext(BitWidth); 1833 KnownOne.zext(BitWidth); 1834 return; 1835 } 1836 case ISD::TRUNCATE: { 1837 MVT InVT = Op.getOperand(0).getValueType(); 1838 unsigned InBits = InVT.getSizeInBits(); 1839 APInt InMask = Mask; 1840 InMask.zext(InBits); 1841 KnownZero.zext(InBits); 1842 KnownOne.zext(InBits); 1843 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1844 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1845 KnownZero.trunc(BitWidth); 1846 KnownOne.trunc(BitWidth); 1847 break; 1848 } 1849 case ISD::AssertZext: { 1850 MVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1851 APInt InMask = APInt::getLowBitsSet(BitWidth, VT.getSizeInBits()); 1852 ComputeMaskedBits(Op.getOperand(0), Mask & InMask, KnownZero, 1853 KnownOne, Depth+1); 1854 KnownZero |= (~InMask) & Mask; 1855 return; 1856 } 1857 case ISD::FGETSIGN: 1858 // All bits are zero except the low bit. 1859 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - 1); 1860 return; 1861 1862 case ISD::SUB: { 1863 if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) { 1864 // We know that the top bits of C-X are clear if X contains less bits 1865 // than C (i.e. no wrap-around can happen). For example, 20-X is 1866 // positive if we can prove that X is >= 0 and < 16. 1867 if (CLHS->getAPIntValue().isNonNegative()) { 1868 unsigned NLZ = (CLHS->getAPIntValue()+1).countLeadingZeros(); 1869 // NLZ can't be BitWidth with no sign bit 1870 APInt MaskV = APInt::getHighBitsSet(BitWidth, NLZ+1); 1871 ComputeMaskedBits(Op.getOperand(1), MaskV, KnownZero2, KnownOne2, 1872 Depth+1); 1873 1874 // If all of the MaskV bits are known to be zero, then we know the 1875 // output top bits are zero, because we now know that the output is 1876 // from [0-C]. 1877 if ((KnownZero2 & MaskV) == MaskV) { 1878 unsigned NLZ2 = CLHS->getAPIntValue().countLeadingZeros(); 1879 // Top bits known zero. 1880 KnownZero = APInt::getHighBitsSet(BitWidth, NLZ2) & Mask; 1881 } 1882 } 1883 } 1884 } 1885 // fall through 1886 case ISD::ADD: { 1887 // Output known-0 bits are known if clear or set in both the low clear bits 1888 // common to both LHS & RHS. For example, 8+(X<<3) is known to have the 1889 // low 3 bits clear. 1890 APInt Mask2 = APInt::getLowBitsSet(BitWidth, Mask.countTrailingOnes()); 1891 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero2, KnownOne2, Depth+1); 1892 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1893 unsigned KnownZeroOut = KnownZero2.countTrailingOnes(); 1894 1895 ComputeMaskedBits(Op.getOperand(1), Mask2, KnownZero2, KnownOne2, Depth+1); 1896 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1897 KnownZeroOut = std::min(KnownZeroOut, 1898 KnownZero2.countTrailingOnes()); 1899 1900 KnownZero |= APInt::getLowBitsSet(BitWidth, KnownZeroOut); 1901 return; 1902 } 1903 case ISD::SREM: 1904 if (ConstantSDNode *Rem = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1905 const APInt &RA = Rem->getAPIntValue(); 1906 if (RA.isPowerOf2() || (-RA).isPowerOf2()) { 1907 APInt LowBits = RA.isStrictlyPositive() ? (RA - 1) : ~RA; 1908 APInt Mask2 = LowBits | APInt::getSignBit(BitWidth); 1909 ComputeMaskedBits(Op.getOperand(0), Mask2,KnownZero2,KnownOne2,Depth+1); 1910 1911 // If the sign bit of the first operand is zero, the sign bit of 1912 // the result is zero. If the first operand has no one bits below 1913 // the second operand's single 1 bit, its sign will be zero. 1914 if (KnownZero2[BitWidth-1] || ((KnownZero2 & LowBits) == LowBits)) 1915 KnownZero2 |= ~LowBits; 1916 1917 KnownZero |= KnownZero2 & Mask; 1918 1919 assert((KnownZero & KnownOne) == 0&&"Bits known to be one AND zero?"); 1920 } 1921 } 1922 return; 1923 case ISD::UREM: { 1924 if (ConstantSDNode *Rem = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1925 const APInt &RA = Rem->getAPIntValue(); 1926 if (RA.isPowerOf2()) { 1927 APInt LowBits = (RA - 1); 1928 APInt Mask2 = LowBits & Mask; 1929 KnownZero |= ~LowBits & Mask; 1930 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero, KnownOne,Depth+1); 1931 assert((KnownZero & KnownOne) == 0&&"Bits known to be one AND zero?"); 1932 break; 1933 } 1934 } 1935 1936 // Since the result is less than or equal to either operand, any leading 1937 // zero bits in either operand must also exist in the result. 1938 APInt AllOnes = APInt::getAllOnesValue(BitWidth); 1939 ComputeMaskedBits(Op.getOperand(0), AllOnes, KnownZero, KnownOne, 1940 Depth+1); 1941 ComputeMaskedBits(Op.getOperand(1), AllOnes, KnownZero2, KnownOne2, 1942 Depth+1); 1943 1944 uint32_t Leaders = std::max(KnownZero.countLeadingOnes(), 1945 KnownZero2.countLeadingOnes()); 1946 KnownOne.clear(); 1947 KnownZero = APInt::getHighBitsSet(BitWidth, Leaders) & Mask; 1948 return; 1949 } 1950 default: 1951 // Allow the target to implement this method for its nodes. 1952 if (Op.getOpcode() >= ISD::BUILTIN_OP_END) { 1953 case ISD::INTRINSIC_WO_CHAIN: 1954 case ISD::INTRINSIC_W_CHAIN: 1955 case ISD::INTRINSIC_VOID: 1956 TLI.computeMaskedBitsForTargetNode(Op, Mask, KnownZero, KnownOne, *this); 1957 } 1958 return; 1959 } 1960} 1961 1962/// ComputeNumSignBits - Return the number of times the sign bit of the 1963/// register is replicated into the other bits. We know that at least 1 bit 1964/// is always equal to the sign bit (itself), but other cases can give us 1965/// information. For example, immediately after an "SRA X, 2", we know that 1966/// the top 3 bits are all equal to each other, so we return 3. 1967unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, unsigned Depth) const{ 1968 MVT VT = Op.getValueType(); 1969 assert(VT.isInteger() && "Invalid VT!"); 1970 unsigned VTBits = VT.getSizeInBits(); 1971 unsigned Tmp, Tmp2; 1972 unsigned FirstAnswer = 1; 1973 1974 if (Depth == 6) 1975 return 1; // Limit search depth. 1976 1977 switch (Op.getOpcode()) { 1978 default: break; 1979 case ISD::AssertSext: 1980 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); 1981 return VTBits-Tmp+1; 1982 case ISD::AssertZext: 1983 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); 1984 return VTBits-Tmp; 1985 1986 case ISD::Constant: { 1987 const APInt &Val = cast<ConstantSDNode>(Op)->getAPIntValue(); 1988 // If negative, return # leading ones. 1989 if (Val.isNegative()) 1990 return Val.countLeadingOnes(); 1991 1992 // Return # leading zeros. 1993 return Val.countLeadingZeros(); 1994 } 1995 1996 case ISD::SIGN_EXTEND: 1997 Tmp = VTBits-Op.getOperand(0).getValueType().getSizeInBits(); 1998 return ComputeNumSignBits(Op.getOperand(0), Depth+1) + Tmp; 1999 2000 case ISD::SIGN_EXTEND_INREG: 2001 // Max of the input and what this extends. 2002 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); 2003 Tmp = VTBits-Tmp+1; 2004 2005 Tmp2 = ComputeNumSignBits(Op.getOperand(0), Depth+1); 2006 return std::max(Tmp, Tmp2); 2007 2008 case ISD::SRA: 2009 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 2010 // SRA X, C -> adds C sign bits. 2011 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 2012 Tmp += C->getZExtValue(); 2013 if (Tmp > VTBits) Tmp = VTBits; 2014 } 2015 return Tmp; 2016 case ISD::SHL: 2017 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 2018 // shl destroys sign bits. 2019 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 2020 if (C->getZExtValue() >= VTBits || // Bad shift. 2021 C->getZExtValue() >= Tmp) break; // Shifted all sign bits out. 2022 return Tmp - C->getZExtValue(); 2023 } 2024 break; 2025 case ISD::AND: 2026 case ISD::OR: 2027 case ISD::XOR: // NOT is handled here. 2028 // Logical binary ops preserve the number of sign bits at the worst. 2029 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 2030 if (Tmp != 1) { 2031 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 2032 FirstAnswer = std::min(Tmp, Tmp2); 2033 // We computed what we know about the sign bits as our first 2034 // answer. Now proceed to the generic code that uses 2035 // ComputeMaskedBits, and pick whichever answer is better. 2036 } 2037 break; 2038 2039 case ISD::SELECT: 2040 Tmp = ComputeNumSignBits(Op.getOperand(1), Depth+1); 2041 if (Tmp == 1) return 1; // Early out. 2042 Tmp2 = ComputeNumSignBits(Op.getOperand(2), Depth+1); 2043 return std::min(Tmp, Tmp2); 2044 2045 case ISD::SADDO: 2046 case ISD::UADDO: 2047 case ISD::SSUBO: 2048 case ISD::USUBO: 2049 case ISD::SMULO: 2050 case ISD::UMULO: 2051 if (Op.getResNo() != 1) 2052 break; 2053 // The boolean result conforms to getBooleanContents. Fall through. 2054 case ISD::SETCC: 2055 // If setcc returns 0/-1, all bits are sign bits. 2056 if (TLI.getBooleanContents() == 2057 TargetLowering::ZeroOrNegativeOneBooleanContent) 2058 return VTBits; 2059 break; 2060 case ISD::ROTL: 2061 case ISD::ROTR: 2062 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 2063 unsigned RotAmt = C->getZExtValue() & (VTBits-1); 2064 2065 // Handle rotate right by N like a rotate left by 32-N. 2066 if (Op.getOpcode() == ISD::ROTR) 2067 RotAmt = (VTBits-RotAmt) & (VTBits-1); 2068 2069 // If we aren't rotating out all of the known-in sign bits, return the 2070 // number that are left. This handles rotl(sext(x), 1) for example. 2071 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 2072 if (Tmp > RotAmt+1) return Tmp-RotAmt; 2073 } 2074 break; 2075 case ISD::ADD: 2076 // Add can have at most one carry bit. Thus we know that the output 2077 // is, at worst, one more bit than the inputs. 2078 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 2079 if (Tmp == 1) return 1; // Early out. 2080 2081 // Special case decrementing a value (ADD X, -1): 2082 if (ConstantSDNode *CRHS = dyn_cast<ConstantSDNode>(Op.getOperand(1))) 2083 if (CRHS->isAllOnesValue()) { 2084 APInt KnownZero, KnownOne; 2085 APInt Mask = APInt::getAllOnesValue(VTBits); 2086 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1); 2087 2088 // If the input is known to be 0 or 1, the output is 0/-1, which is all 2089 // sign bits set. 2090 if ((KnownZero | APInt(VTBits, 1)) == Mask) 2091 return VTBits; 2092 2093 // If we are subtracting one from a positive number, there is no carry 2094 // out of the result. 2095 if (KnownZero.isNegative()) 2096 return Tmp; 2097 } 2098 2099 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 2100 if (Tmp2 == 1) return 1; 2101 return std::min(Tmp, Tmp2)-1; 2102 break; 2103 2104 case ISD::SUB: 2105 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 2106 if (Tmp2 == 1) return 1; 2107 2108 // Handle NEG. 2109 if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) 2110 if (CLHS->isNullValue()) { 2111 APInt KnownZero, KnownOne; 2112 APInt Mask = APInt::getAllOnesValue(VTBits); 2113 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 2114 // If the input is known to be 0 or 1, the output is 0/-1, which is all 2115 // sign bits set. 2116 if ((KnownZero | APInt(VTBits, 1)) == Mask) 2117 return VTBits; 2118 2119 // If the input is known to be positive (the sign bit is known clear), 2120 // the output of the NEG has the same number of sign bits as the input. 2121 if (KnownZero.isNegative()) 2122 return Tmp2; 2123 2124 // Otherwise, we treat this like a SUB. 2125 } 2126 2127 // Sub can have at most one carry bit. Thus we know that the output 2128 // is, at worst, one more bit than the inputs. 2129 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 2130 if (Tmp == 1) return 1; // Early out. 2131 return std::min(Tmp, Tmp2)-1; 2132 break; 2133 case ISD::TRUNCATE: 2134 // FIXME: it's tricky to do anything useful for this, but it is an important 2135 // case for targets like X86. 2136 break; 2137 } 2138 2139 // Handle LOADX separately here. EXTLOAD case will fallthrough. 2140 if (Op.getOpcode() == ISD::LOAD) { 2141 LoadSDNode *LD = cast<LoadSDNode>(Op); 2142 unsigned ExtType = LD->getExtensionType(); 2143 switch (ExtType) { 2144 default: break; 2145 case ISD::SEXTLOAD: // '17' bits known 2146 Tmp = LD->getMemoryVT().getSizeInBits(); 2147 return VTBits-Tmp+1; 2148 case ISD::ZEXTLOAD: // '16' bits known 2149 Tmp = LD->getMemoryVT().getSizeInBits(); 2150 return VTBits-Tmp; 2151 } 2152 } 2153 2154 // Allow the target to implement this method for its nodes. 2155 if (Op.getOpcode() >= ISD::BUILTIN_OP_END || 2156 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 2157 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 2158 Op.getOpcode() == ISD::INTRINSIC_VOID) { 2159 unsigned NumBits = TLI.ComputeNumSignBitsForTargetNode(Op, Depth); 2160 if (NumBits > 1) FirstAnswer = std::max(FirstAnswer, NumBits); 2161 } 2162 2163 // Finally, if we can prove that the top bits of the result are 0's or 1's, 2164 // use this information. 2165 APInt KnownZero, KnownOne; 2166 APInt Mask = APInt::getAllOnesValue(VTBits); 2167 ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth); 2168 2169 if (KnownZero.isNegative()) { // sign bit is 0 2170 Mask = KnownZero; 2171 } else if (KnownOne.isNegative()) { // sign bit is 1; 2172 Mask = KnownOne; 2173 } else { 2174 // Nothing known. 2175 return FirstAnswer; 2176 } 2177 2178 // Okay, we know that the sign bit in Mask is set. Use CLZ to determine 2179 // the number of identical bits in the top of the input value. 2180 Mask = ~Mask; 2181 Mask <<= Mask.getBitWidth()-VTBits; 2182 // Return # leading zeros. We use 'min' here in case Val was zero before 2183 // shifting. We don't want to return '64' as for an i32 "0". 2184 return std::max(FirstAnswer, std::min(VTBits, Mask.countLeadingZeros())); 2185} 2186 2187 2188bool SelectionDAG::isVerifiedDebugInfoDesc(SDValue Op) const { 2189 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op); 2190 if (!GA) return false; 2191 if (GA->getOffset() != 0) return false; 2192 GlobalVariable *GV = dyn_cast<GlobalVariable>(GA->getGlobal()); 2193 if (!GV) return false; 2194 MachineModuleInfo *MMI = getMachineModuleInfo(); 2195 return MMI && MMI->hasDebugInfo(); 2196} 2197 2198 2199/// getShuffleScalarElt - Returns the scalar element that will make up the ith 2200/// element of the result of the vector shuffle. 2201SDValue SelectionDAG::getShuffleScalarElt(const ShuffleVectorSDNode *N, 2202 unsigned i) { 2203 MVT VT = N->getValueType(0); 2204 DebugLoc dl = N->getDebugLoc(); 2205 if (N->getMaskElt(i) < 0) 2206 return getUNDEF(VT.getVectorElementType()); 2207 unsigned Index = N->getMaskElt(i); 2208 unsigned NumElems = VT.getVectorNumElements(); 2209 SDValue V = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1); 2210 Index %= NumElems; 2211 2212 if (V.getOpcode() == ISD::BIT_CONVERT) { 2213 V = V.getOperand(0); 2214 MVT VVT = V.getValueType(); 2215 if (!VVT.isVector() || VVT.getVectorNumElements() != (unsigned)NumElems) 2216 return SDValue(); 2217 } 2218 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) 2219 return (Index == 0) ? V.getOperand(0) 2220 : getUNDEF(VT.getVectorElementType()); 2221 if (V.getOpcode() == ISD::BUILD_VECTOR) 2222 return V.getOperand(Index); 2223 if (const ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(V)) 2224 return getShuffleScalarElt(SVN, Index); 2225 return SDValue(); 2226} 2227 2228 2229/// getNode - Gets or creates the specified node. 2230/// 2231SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT) { 2232 FoldingSetNodeID ID; 2233 AddNodeIDNode(ID, Opcode, getVTList(VT), 0, 0); 2234 void *IP = 0; 2235 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2236 return SDValue(E, 0); 2237 SDNode *N = NodeAllocator.Allocate<SDNode>(); 2238 new (N) SDNode(Opcode, DL, getVTList(VT)); 2239 CSEMap.InsertNode(N, IP); 2240 2241 AllNodes.push_back(N); 2242#ifndef NDEBUG 2243 VerifyNode(N); 2244#endif 2245 return SDValue(N, 0); 2246} 2247 2248SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, 2249 MVT VT, SDValue Operand) { 2250 // Constant fold unary operations with an integer constant operand. 2251 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Operand.getNode())) { 2252 const APInt &Val = C->getAPIntValue(); 2253 unsigned BitWidth = VT.getSizeInBits(); 2254 switch (Opcode) { 2255 default: break; 2256 case ISD::SIGN_EXTEND: 2257 return getConstant(APInt(Val).sextOrTrunc(BitWidth), VT); 2258 case ISD::ANY_EXTEND: 2259 case ISD::ZERO_EXTEND: 2260 case ISD::TRUNCATE: 2261 return getConstant(APInt(Val).zextOrTrunc(BitWidth), VT); 2262 case ISD::UINT_TO_FP: 2263 case ISD::SINT_TO_FP: { 2264 const uint64_t zero[] = {0, 0}; 2265 // No compile time operations on this type. 2266 if (VT==MVT::ppcf128) 2267 break; 2268 APFloat apf = APFloat(APInt(BitWidth, 2, zero)); 2269 (void)apf.convertFromAPInt(Val, 2270 Opcode==ISD::SINT_TO_FP, 2271 APFloat::rmNearestTiesToEven); 2272 return getConstantFP(apf, VT); 2273 } 2274 case ISD::BIT_CONVERT: 2275 if (VT == MVT::f32 && C->getValueType(0) == MVT::i32) 2276 return getConstantFP(Val.bitsToFloat(), VT); 2277 else if (VT == MVT::f64 && C->getValueType(0) == MVT::i64) 2278 return getConstantFP(Val.bitsToDouble(), VT); 2279 break; 2280 case ISD::BSWAP: 2281 return getConstant(Val.byteSwap(), VT); 2282 case ISD::CTPOP: 2283 return getConstant(Val.countPopulation(), VT); 2284 case ISD::CTLZ: 2285 return getConstant(Val.countLeadingZeros(), VT); 2286 case ISD::CTTZ: 2287 return getConstant(Val.countTrailingZeros(), VT); 2288 } 2289 } 2290 2291 // Constant fold unary operations with a floating point constant operand. 2292 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Operand.getNode())) { 2293 APFloat V = C->getValueAPF(); // make copy 2294 if (VT != MVT::ppcf128 && Operand.getValueType() != MVT::ppcf128) { 2295 switch (Opcode) { 2296 case ISD::FNEG: 2297 V.changeSign(); 2298 return getConstantFP(V, VT); 2299 case ISD::FABS: 2300 V.clearSign(); 2301 return getConstantFP(V, VT); 2302 case ISD::FP_ROUND: 2303 case ISD::FP_EXTEND: { 2304 bool ignored; 2305 // This can return overflow, underflow, or inexact; we don't care. 2306 // FIXME need to be more flexible about rounding mode. 2307 (void)V.convert(*MVTToAPFloatSemantics(VT), 2308 APFloat::rmNearestTiesToEven, &ignored); 2309 return getConstantFP(V, VT); 2310 } 2311 case ISD::FP_TO_SINT: 2312 case ISD::FP_TO_UINT: { 2313 integerPart x[2]; 2314 bool ignored; 2315 assert(integerPartWidth >= 64); 2316 // FIXME need to be more flexible about rounding mode. 2317 APFloat::opStatus s = V.convertToInteger(x, VT.getSizeInBits(), 2318 Opcode==ISD::FP_TO_SINT, 2319 APFloat::rmTowardZero, &ignored); 2320 if (s==APFloat::opInvalidOp) // inexact is OK, in fact usual 2321 break; 2322 APInt api(VT.getSizeInBits(), 2, x); 2323 return getConstant(api, VT); 2324 } 2325 case ISD::BIT_CONVERT: 2326 if (VT == MVT::i32 && C->getValueType(0) == MVT::f32) 2327 return getConstant((uint32_t)V.bitcastToAPInt().getZExtValue(), VT); 2328 else if (VT == MVT::i64 && C->getValueType(0) == MVT::f64) 2329 return getConstant(V.bitcastToAPInt().getZExtValue(), VT); 2330 break; 2331 } 2332 } 2333 } 2334 2335 unsigned OpOpcode = Operand.getNode()->getOpcode(); 2336 switch (Opcode) { 2337 case ISD::TokenFactor: 2338 case ISD::MERGE_VALUES: 2339 case ISD::CONCAT_VECTORS: 2340 return Operand; // Factor, merge or concat of one node? No need. 2341 case ISD::FP_ROUND: assert(0 && "Invalid method to make FP_ROUND node"); 2342 case ISD::FP_EXTEND: 2343 assert(VT.isFloatingPoint() && 2344 Operand.getValueType().isFloatingPoint() && "Invalid FP cast!"); 2345 if (Operand.getValueType() == VT) return Operand; // noop conversion. 2346 if (Operand.getOpcode() == ISD::UNDEF) 2347 return getUNDEF(VT); 2348 break; 2349 case ISD::SIGN_EXTEND: 2350 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2351 "Invalid SIGN_EXTEND!"); 2352 if (Operand.getValueType() == VT) return Operand; // noop extension 2353 assert(Operand.getValueType().bitsLT(VT) 2354 && "Invalid sext node, dst < src!"); 2355 if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND) 2356 return getNode(OpOpcode, DL, VT, Operand.getNode()->getOperand(0)); 2357 break; 2358 case ISD::ZERO_EXTEND: 2359 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2360 "Invalid ZERO_EXTEND!"); 2361 if (Operand.getValueType() == VT) return Operand; // noop extension 2362 assert(Operand.getValueType().bitsLT(VT) 2363 && "Invalid zext node, dst < src!"); 2364 if (OpOpcode == ISD::ZERO_EXTEND) // (zext (zext x)) -> (zext x) 2365 return getNode(ISD::ZERO_EXTEND, DL, VT, 2366 Operand.getNode()->getOperand(0)); 2367 break; 2368 case ISD::ANY_EXTEND: 2369 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2370 "Invalid ANY_EXTEND!"); 2371 if (Operand.getValueType() == VT) return Operand; // noop extension 2372 assert(Operand.getValueType().bitsLT(VT) 2373 && "Invalid anyext node, dst < src!"); 2374 if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND) 2375 // (ext (zext x)) -> (zext x) and (ext (sext x)) -> (sext x) 2376 return getNode(OpOpcode, DL, VT, Operand.getNode()->getOperand(0)); 2377 break; 2378 case ISD::TRUNCATE: 2379 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2380 "Invalid TRUNCATE!"); 2381 if (Operand.getValueType() == VT) return Operand; // noop truncate 2382 assert(Operand.getValueType().bitsGT(VT) 2383 && "Invalid truncate node, src < dst!"); 2384 if (OpOpcode == ISD::TRUNCATE) 2385 return getNode(ISD::TRUNCATE, DL, VT, Operand.getNode()->getOperand(0)); 2386 else if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND || 2387 OpOpcode == ISD::ANY_EXTEND) { 2388 // If the source is smaller than the dest, we still need an extend. 2389 if (Operand.getNode()->getOperand(0).getValueType().bitsLT(VT)) 2390 return getNode(OpOpcode, DL, VT, Operand.getNode()->getOperand(0)); 2391 else if (Operand.getNode()->getOperand(0).getValueType().bitsGT(VT)) 2392 return getNode(ISD::TRUNCATE, DL, VT, Operand.getNode()->getOperand(0)); 2393 else 2394 return Operand.getNode()->getOperand(0); 2395 } 2396 break; 2397 case ISD::BIT_CONVERT: 2398 // Basic sanity checking. 2399 assert(VT.getSizeInBits() == Operand.getValueType().getSizeInBits() 2400 && "Cannot BIT_CONVERT between types of different sizes!"); 2401 if (VT == Operand.getValueType()) return Operand; // noop conversion. 2402 if (OpOpcode == ISD::BIT_CONVERT) // bitconv(bitconv(x)) -> bitconv(x) 2403 return getNode(ISD::BIT_CONVERT, DL, VT, Operand.getOperand(0)); 2404 if (OpOpcode == ISD::UNDEF) 2405 return getUNDEF(VT); 2406 break; 2407 case ISD::SCALAR_TO_VECTOR: 2408 assert(VT.isVector() && !Operand.getValueType().isVector() && 2409 (VT.getVectorElementType() == Operand.getValueType() || 2410 (VT.getVectorElementType().isInteger() && 2411 Operand.getValueType().isInteger() && 2412 VT.getVectorElementType().bitsLE(Operand.getValueType()))) && 2413 "Illegal SCALAR_TO_VECTOR node!"); 2414 if (OpOpcode == ISD::UNDEF) 2415 return getUNDEF(VT); 2416 // scalar_to_vector(extract_vector_elt V, 0) -> V, top bits are undefined. 2417 if (OpOpcode == ISD::EXTRACT_VECTOR_ELT && 2418 isa<ConstantSDNode>(Operand.getOperand(1)) && 2419 Operand.getConstantOperandVal(1) == 0 && 2420 Operand.getOperand(0).getValueType() == VT) 2421 return Operand.getOperand(0); 2422 break; 2423 case ISD::FNEG: 2424 // -(X-Y) -> (Y-X) is unsafe because when X==Y, -0.0 != +0.0 2425 if (UnsafeFPMath && OpOpcode == ISD::FSUB) 2426 return getNode(ISD::FSUB, DL, VT, Operand.getNode()->getOperand(1), 2427 Operand.getNode()->getOperand(0)); 2428 if (OpOpcode == ISD::FNEG) // --X -> X 2429 return Operand.getNode()->getOperand(0); 2430 break; 2431 case ISD::FABS: 2432 if (OpOpcode == ISD::FNEG) // abs(-X) -> abs(X) 2433 return getNode(ISD::FABS, DL, VT, Operand.getNode()->getOperand(0)); 2434 break; 2435 } 2436 2437 SDNode *N; 2438 SDVTList VTs = getVTList(VT); 2439 if (VT != MVT::Flag) { // Don't CSE flag producing nodes 2440 FoldingSetNodeID ID; 2441 SDValue Ops[1] = { Operand }; 2442 AddNodeIDNode(ID, Opcode, VTs, Ops, 1); 2443 void *IP = 0; 2444 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2445 return SDValue(E, 0); 2446 N = NodeAllocator.Allocate<UnarySDNode>(); 2447 new (N) UnarySDNode(Opcode, DL, VTs, Operand); 2448 CSEMap.InsertNode(N, IP); 2449 } else { 2450 N = NodeAllocator.Allocate<UnarySDNode>(); 2451 new (N) UnarySDNode(Opcode, DL, VTs, Operand); 2452 } 2453 2454 AllNodes.push_back(N); 2455#ifndef NDEBUG 2456 VerifyNode(N); 2457#endif 2458 return SDValue(N, 0); 2459} 2460 2461SDValue SelectionDAG::FoldConstantArithmetic(unsigned Opcode, 2462 MVT VT, 2463 ConstantSDNode *Cst1, 2464 ConstantSDNode *Cst2) { 2465 const APInt &C1 = Cst1->getAPIntValue(), &C2 = Cst2->getAPIntValue(); 2466 2467 switch (Opcode) { 2468 case ISD::ADD: return getConstant(C1 + C2, VT); 2469 case ISD::SUB: return getConstant(C1 - C2, VT); 2470 case ISD::MUL: return getConstant(C1 * C2, VT); 2471 case ISD::UDIV: 2472 if (C2.getBoolValue()) return getConstant(C1.udiv(C2), VT); 2473 break; 2474 case ISD::UREM: 2475 if (C2.getBoolValue()) return getConstant(C1.urem(C2), VT); 2476 break; 2477 case ISD::SDIV: 2478 if (C2.getBoolValue()) return getConstant(C1.sdiv(C2), VT); 2479 break; 2480 case ISD::SREM: 2481 if (C2.getBoolValue()) return getConstant(C1.srem(C2), VT); 2482 break; 2483 case ISD::AND: return getConstant(C1 & C2, VT); 2484 case ISD::OR: return getConstant(C1 | C2, VT); 2485 case ISD::XOR: return getConstant(C1 ^ C2, VT); 2486 case ISD::SHL: return getConstant(C1 << C2, VT); 2487 case ISD::SRL: return getConstant(C1.lshr(C2), VT); 2488 case ISD::SRA: return getConstant(C1.ashr(C2), VT); 2489 case ISD::ROTL: return getConstant(C1.rotl(C2), VT); 2490 case ISD::ROTR: return getConstant(C1.rotr(C2), VT); 2491 default: break; 2492 } 2493 2494 return SDValue(); 2495} 2496 2497SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, 2498 SDValue N1, SDValue N2) { 2499 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 2500 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 2501 switch (Opcode) { 2502 default: break; 2503 case ISD::TokenFactor: 2504 assert(VT == MVT::Other && N1.getValueType() == MVT::Other && 2505 N2.getValueType() == MVT::Other && "Invalid token factor!"); 2506 // Fold trivial token factors. 2507 if (N1.getOpcode() == ISD::EntryToken) return N2; 2508 if (N2.getOpcode() == ISD::EntryToken) return N1; 2509 if (N1 == N2) return N1; 2510 break; 2511 case ISD::CONCAT_VECTORS: 2512 // A CONCAT_VECTOR with all operands BUILD_VECTOR can be simplified to 2513 // one big BUILD_VECTOR. 2514 if (N1.getOpcode() == ISD::BUILD_VECTOR && 2515 N2.getOpcode() == ISD::BUILD_VECTOR) { 2516 SmallVector<SDValue, 16> Elts(N1.getNode()->op_begin(), N1.getNode()->op_end()); 2517 Elts.insert(Elts.end(), N2.getNode()->op_begin(), N2.getNode()->op_end()); 2518 return getNode(ISD::BUILD_VECTOR, DL, VT, &Elts[0], Elts.size()); 2519 } 2520 break; 2521 case ISD::AND: 2522 assert(VT.isInteger() && N1.getValueType() == N2.getValueType() && 2523 N1.getValueType() == VT && "Binary operator types must match!"); 2524 // (X & 0) -> 0. This commonly occurs when legalizing i64 values, so it's 2525 // worth handling here. 2526 if (N2C && N2C->isNullValue()) 2527 return N2; 2528 if (N2C && N2C->isAllOnesValue()) // X & -1 -> X 2529 return N1; 2530 break; 2531 case ISD::OR: 2532 case ISD::XOR: 2533 case ISD::ADD: 2534 case ISD::SUB: 2535 assert(VT.isInteger() && N1.getValueType() == N2.getValueType() && 2536 N1.getValueType() == VT && "Binary operator types must match!"); 2537 // (X ^|+- 0) -> X. This commonly occurs when legalizing i64 values, so 2538 // it's worth handling here. 2539 if (N2C && N2C->isNullValue()) 2540 return N1; 2541 break; 2542 case ISD::UDIV: 2543 case ISD::UREM: 2544 case ISD::MULHU: 2545 case ISD::MULHS: 2546 case ISD::MUL: 2547 case ISD::SDIV: 2548 case ISD::SREM: 2549 assert(VT.isInteger() && "This operator does not apply to FP types!"); 2550 // fall through 2551 case ISD::FADD: 2552 case ISD::FSUB: 2553 case ISD::FMUL: 2554 case ISD::FDIV: 2555 case ISD::FREM: 2556 if (UnsafeFPMath) { 2557 if (Opcode == ISD::FADD) { 2558 // 0+x --> x 2559 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) 2560 if (CFP->getValueAPF().isZero()) 2561 return N2; 2562 // x+0 --> x 2563 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N2)) 2564 if (CFP->getValueAPF().isZero()) 2565 return N1; 2566 } else if (Opcode == ISD::FSUB) { 2567 // x-0 --> x 2568 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N2)) 2569 if (CFP->getValueAPF().isZero()) 2570 return N1; 2571 } 2572 } 2573 assert(N1.getValueType() == N2.getValueType() && 2574 N1.getValueType() == VT && "Binary operator types must match!"); 2575 break; 2576 case ISD::FCOPYSIGN: // N1 and result must match. N1/N2 need not match. 2577 assert(N1.getValueType() == VT && 2578 N1.getValueType().isFloatingPoint() && 2579 N2.getValueType().isFloatingPoint() && 2580 "Invalid FCOPYSIGN!"); 2581 break; 2582 case ISD::SHL: 2583 case ISD::SRA: 2584 case ISD::SRL: 2585 case ISD::ROTL: 2586 case ISD::ROTR: 2587 assert(VT == N1.getValueType() && 2588 "Shift operators return type must be the same as their first arg"); 2589 assert(VT.isInteger() && N2.getValueType().isInteger() && 2590 "Shifts only work on integers"); 2591 2592 // Always fold shifts of i1 values so the code generator doesn't need to 2593 // handle them. Since we know the size of the shift has to be less than the 2594 // size of the value, the shift/rotate count is guaranteed to be zero. 2595 if (VT == MVT::i1) 2596 return N1; 2597 break; 2598 case ISD::FP_ROUND_INREG: { 2599 MVT EVT = cast<VTSDNode>(N2)->getVT(); 2600 assert(VT == N1.getValueType() && "Not an inreg round!"); 2601 assert(VT.isFloatingPoint() && EVT.isFloatingPoint() && 2602 "Cannot FP_ROUND_INREG integer types"); 2603 assert(EVT.bitsLE(VT) && "Not rounding down!"); 2604 if (cast<VTSDNode>(N2)->getVT() == VT) return N1; // Not actually rounding. 2605 break; 2606 } 2607 case ISD::FP_ROUND: 2608 assert(VT.isFloatingPoint() && 2609 N1.getValueType().isFloatingPoint() && 2610 VT.bitsLE(N1.getValueType()) && 2611 isa<ConstantSDNode>(N2) && "Invalid FP_ROUND!"); 2612 if (N1.getValueType() == VT) return N1; // noop conversion. 2613 break; 2614 case ISD::AssertSext: 2615 case ISD::AssertZext: { 2616 MVT EVT = cast<VTSDNode>(N2)->getVT(); 2617 assert(VT == N1.getValueType() && "Not an inreg extend!"); 2618 assert(VT.isInteger() && EVT.isInteger() && 2619 "Cannot *_EXTEND_INREG FP types"); 2620 assert(EVT.bitsLE(VT) && "Not extending!"); 2621 if (VT == EVT) return N1; // noop assertion. 2622 break; 2623 } 2624 case ISD::SIGN_EXTEND_INREG: { 2625 MVT EVT = cast<VTSDNode>(N2)->getVT(); 2626 assert(VT == N1.getValueType() && "Not an inreg extend!"); 2627 assert(VT.isInteger() && EVT.isInteger() && 2628 "Cannot *_EXTEND_INREG FP types"); 2629 assert(EVT.bitsLE(VT) && "Not extending!"); 2630 if (EVT == VT) return N1; // Not actually extending 2631 2632 if (N1C) { 2633 APInt Val = N1C->getAPIntValue(); 2634 unsigned FromBits = cast<VTSDNode>(N2)->getVT().getSizeInBits(); 2635 Val <<= Val.getBitWidth()-FromBits; 2636 Val = Val.ashr(Val.getBitWidth()-FromBits); 2637 return getConstant(Val, VT); 2638 } 2639 break; 2640 } 2641 case ISD::EXTRACT_VECTOR_ELT: 2642 // EXTRACT_VECTOR_ELT of an UNDEF is an UNDEF. 2643 if (N1.getOpcode() == ISD::UNDEF) 2644 return getUNDEF(VT); 2645 2646 // EXTRACT_VECTOR_ELT of CONCAT_VECTORS is often formed while lowering is 2647 // expanding copies of large vectors from registers. 2648 if (N2C && 2649 N1.getOpcode() == ISD::CONCAT_VECTORS && 2650 N1.getNumOperands() > 0) { 2651 unsigned Factor = 2652 N1.getOperand(0).getValueType().getVectorNumElements(); 2653 return getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, 2654 N1.getOperand(N2C->getZExtValue() / Factor), 2655 getConstant(N2C->getZExtValue() % Factor, 2656 N2.getValueType())); 2657 } 2658 2659 // EXTRACT_VECTOR_ELT of BUILD_VECTOR is often formed while lowering is 2660 // expanding large vector constants. 2661 if (N2C && N1.getOpcode() == ISD::BUILD_VECTOR) { 2662 SDValue Elt = N1.getOperand(N2C->getZExtValue()); 2663 if (Elt.getValueType() != VT) { 2664 // If the vector element type is not legal, the BUILD_VECTOR operands 2665 // are promoted and implicitly truncated. Make that explicit here. 2666 assert(VT.isInteger() && Elt.getValueType().isInteger() && 2667 VT.bitsLE(Elt.getValueType()) && 2668 "Bad type for BUILD_VECTOR operand"); 2669 Elt = getNode(ISD::TRUNCATE, DL, VT, Elt); 2670 } 2671 return Elt; 2672 } 2673 2674 // EXTRACT_VECTOR_ELT of INSERT_VECTOR_ELT is often formed when vector 2675 // operations are lowered to scalars. 2676 if (N1.getOpcode() == ISD::INSERT_VECTOR_ELT) { 2677 // If the indices are the same, return the inserted element. 2678 if (N1.getOperand(2) == N2) 2679 return N1.getOperand(1); 2680 // If the indices are known different, extract the element from 2681 // the original vector. 2682 else if (isa<ConstantSDNode>(N1.getOperand(2)) && 2683 isa<ConstantSDNode>(N2)) 2684 return getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, N1.getOperand(0), N2); 2685 } 2686 break; 2687 case ISD::EXTRACT_ELEMENT: 2688 assert(N2C && (unsigned)N2C->getZExtValue() < 2 && "Bad EXTRACT_ELEMENT!"); 2689 assert(!N1.getValueType().isVector() && !VT.isVector() && 2690 (N1.getValueType().isInteger() == VT.isInteger()) && 2691 "Wrong types for EXTRACT_ELEMENT!"); 2692 2693 // EXTRACT_ELEMENT of BUILD_PAIR is often formed while legalize is expanding 2694 // 64-bit integers into 32-bit parts. Instead of building the extract of 2695 // the BUILD_PAIR, only to have legalize rip it apart, just do it now. 2696 if (N1.getOpcode() == ISD::BUILD_PAIR) 2697 return N1.getOperand(N2C->getZExtValue()); 2698 2699 // EXTRACT_ELEMENT of a constant int is also very common. 2700 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) { 2701 unsigned ElementSize = VT.getSizeInBits(); 2702 unsigned Shift = ElementSize * N2C->getZExtValue(); 2703 APInt ShiftedVal = C->getAPIntValue().lshr(Shift); 2704 return getConstant(ShiftedVal.trunc(ElementSize), VT); 2705 } 2706 break; 2707 case ISD::EXTRACT_SUBVECTOR: 2708 if (N1.getValueType() == VT) // Trivial extraction. 2709 return N1; 2710 break; 2711 } 2712 2713 if (N1C) { 2714 if (N2C) { 2715 SDValue SV = FoldConstantArithmetic(Opcode, VT, N1C, N2C); 2716 if (SV.getNode()) return SV; 2717 } else { // Cannonicalize constant to RHS if commutative 2718 if (isCommutativeBinOp(Opcode)) { 2719 std::swap(N1C, N2C); 2720 std::swap(N1, N2); 2721 } 2722 } 2723 } 2724 2725 // Constant fold FP operations. 2726 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1.getNode()); 2727 ConstantFPSDNode *N2CFP = dyn_cast<ConstantFPSDNode>(N2.getNode()); 2728 if (N1CFP) { 2729 if (!N2CFP && isCommutativeBinOp(Opcode)) { 2730 // Cannonicalize constant to RHS if commutative 2731 std::swap(N1CFP, N2CFP); 2732 std::swap(N1, N2); 2733 } else if (N2CFP && VT != MVT::ppcf128) { 2734 APFloat V1 = N1CFP->getValueAPF(), V2 = N2CFP->getValueAPF(); 2735 APFloat::opStatus s; 2736 switch (Opcode) { 2737 case ISD::FADD: 2738 s = V1.add(V2, APFloat::rmNearestTiesToEven); 2739 if (s != APFloat::opInvalidOp) 2740 return getConstantFP(V1, VT); 2741 break; 2742 case ISD::FSUB: 2743 s = V1.subtract(V2, APFloat::rmNearestTiesToEven); 2744 if (s!=APFloat::opInvalidOp) 2745 return getConstantFP(V1, VT); 2746 break; 2747 case ISD::FMUL: 2748 s = V1.multiply(V2, APFloat::rmNearestTiesToEven); 2749 if (s!=APFloat::opInvalidOp) 2750 return getConstantFP(V1, VT); 2751 break; 2752 case ISD::FDIV: 2753 s = V1.divide(V2, APFloat::rmNearestTiesToEven); 2754 if (s!=APFloat::opInvalidOp && s!=APFloat::opDivByZero) 2755 return getConstantFP(V1, VT); 2756 break; 2757 case ISD::FREM : 2758 s = V1.mod(V2, APFloat::rmNearestTiesToEven); 2759 if (s!=APFloat::opInvalidOp && s!=APFloat::opDivByZero) 2760 return getConstantFP(V1, VT); 2761 break; 2762 case ISD::FCOPYSIGN: 2763 V1.copySign(V2); 2764 return getConstantFP(V1, VT); 2765 default: break; 2766 } 2767 } 2768 } 2769 2770 // Canonicalize an UNDEF to the RHS, even over a constant. 2771 if (N1.getOpcode() == ISD::UNDEF) { 2772 if (isCommutativeBinOp(Opcode)) { 2773 std::swap(N1, N2); 2774 } else { 2775 switch (Opcode) { 2776 case ISD::FP_ROUND_INREG: 2777 case ISD::SIGN_EXTEND_INREG: 2778 case ISD::SUB: 2779 case ISD::FSUB: 2780 case ISD::FDIV: 2781 case ISD::FREM: 2782 case ISD::SRA: 2783 return N1; // fold op(undef, arg2) -> undef 2784 case ISD::UDIV: 2785 case ISD::SDIV: 2786 case ISD::UREM: 2787 case ISD::SREM: 2788 case ISD::SRL: 2789 case ISD::SHL: 2790 if (!VT.isVector()) 2791 return getConstant(0, VT); // fold op(undef, arg2) -> 0 2792 // For vectors, we can't easily build an all zero vector, just return 2793 // the LHS. 2794 return N2; 2795 } 2796 } 2797 } 2798 2799 // Fold a bunch of operators when the RHS is undef. 2800 if (N2.getOpcode() == ISD::UNDEF) { 2801 switch (Opcode) { 2802 case ISD::XOR: 2803 if (N1.getOpcode() == ISD::UNDEF) 2804 // Handle undef ^ undef -> 0 special case. This is a common 2805 // idiom (misuse). 2806 return getConstant(0, VT); 2807 // fallthrough 2808 case ISD::ADD: 2809 case ISD::ADDC: 2810 case ISD::ADDE: 2811 case ISD::SUB: 2812 case ISD::UDIV: 2813 case ISD::SDIV: 2814 case ISD::UREM: 2815 case ISD::SREM: 2816 return N2; // fold op(arg1, undef) -> undef 2817 case ISD::FADD: 2818 case ISD::FSUB: 2819 case ISD::FMUL: 2820 case ISD::FDIV: 2821 case ISD::FREM: 2822 if (UnsafeFPMath) 2823 return N2; 2824 break; 2825 case ISD::MUL: 2826 case ISD::AND: 2827 case ISD::SRL: 2828 case ISD::SHL: 2829 if (!VT.isVector()) 2830 return getConstant(0, VT); // fold op(arg1, undef) -> 0 2831 // For vectors, we can't easily build an all zero vector, just return 2832 // the LHS. 2833 return N1; 2834 case ISD::OR: 2835 if (!VT.isVector()) 2836 return getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT); 2837 // For vectors, we can't easily build an all one vector, just return 2838 // the LHS. 2839 return N1; 2840 case ISD::SRA: 2841 return N1; 2842 } 2843 } 2844 2845 // Memoize this node if possible. 2846 SDNode *N; 2847 SDVTList VTs = getVTList(VT); 2848 if (VT != MVT::Flag) { 2849 SDValue Ops[] = { N1, N2 }; 2850 FoldingSetNodeID ID; 2851 AddNodeIDNode(ID, Opcode, VTs, Ops, 2); 2852 void *IP = 0; 2853 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2854 return SDValue(E, 0); 2855 N = NodeAllocator.Allocate<BinarySDNode>(); 2856 new (N) BinarySDNode(Opcode, DL, VTs, N1, N2); 2857 CSEMap.InsertNode(N, IP); 2858 } else { 2859 N = NodeAllocator.Allocate<BinarySDNode>(); 2860 new (N) BinarySDNode(Opcode, DL, VTs, N1, N2); 2861 } 2862 2863 AllNodes.push_back(N); 2864#ifndef NDEBUG 2865 VerifyNode(N); 2866#endif 2867 return SDValue(N, 0); 2868} 2869 2870SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, 2871 SDValue N1, SDValue N2, SDValue N3) { 2872 // Perform various simplifications. 2873 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 2874 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 2875 switch (Opcode) { 2876 case ISD::CONCAT_VECTORS: 2877 // A CONCAT_VECTOR with all operands BUILD_VECTOR can be simplified to 2878 // one big BUILD_VECTOR. 2879 if (N1.getOpcode() == ISD::BUILD_VECTOR && 2880 N2.getOpcode() == ISD::BUILD_VECTOR && 2881 N3.getOpcode() == ISD::BUILD_VECTOR) { 2882 SmallVector<SDValue, 16> Elts(N1.getNode()->op_begin(), N1.getNode()->op_end()); 2883 Elts.insert(Elts.end(), N2.getNode()->op_begin(), N2.getNode()->op_end()); 2884 Elts.insert(Elts.end(), N3.getNode()->op_begin(), N3.getNode()->op_end()); 2885 return getNode(ISD::BUILD_VECTOR, DL, VT, &Elts[0], Elts.size()); 2886 } 2887 break; 2888 case ISD::SETCC: { 2889 // Use FoldSetCC to simplify SETCC's. 2890 SDValue Simp = FoldSetCC(VT, N1, N2, cast<CondCodeSDNode>(N3)->get(), DL); 2891 if (Simp.getNode()) return Simp; 2892 break; 2893 } 2894 case ISD::SELECT: 2895 if (N1C) { 2896 if (N1C->getZExtValue()) 2897 return N2; // select true, X, Y -> X 2898 else 2899 return N3; // select false, X, Y -> Y 2900 } 2901 2902 if (N2 == N3) return N2; // select C, X, X -> X 2903 break; 2904 case ISD::BRCOND: 2905 if (N2C) { 2906 if (N2C->getZExtValue()) // Unconditional branch 2907 return getNode(ISD::BR, DL, MVT::Other, N1, N3); 2908 else 2909 return N1; // Never-taken branch 2910 } 2911 break; 2912 case ISD::VECTOR_SHUFFLE: 2913 assert(0 && "should use getVectorShuffle constructor!"); 2914 break; 2915 case ISD::BIT_CONVERT: 2916 // Fold bit_convert nodes from a type to themselves. 2917 if (N1.getValueType() == VT) 2918 return N1; 2919 break; 2920 } 2921 2922 // Memoize node if it doesn't produce a flag. 2923 SDNode *N; 2924 SDVTList VTs = getVTList(VT); 2925 if (VT != MVT::Flag) { 2926 SDValue Ops[] = { N1, N2, N3 }; 2927 FoldingSetNodeID ID; 2928 AddNodeIDNode(ID, Opcode, VTs, Ops, 3); 2929 void *IP = 0; 2930 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2931 return SDValue(E, 0); 2932 N = NodeAllocator.Allocate<TernarySDNode>(); 2933 new (N) TernarySDNode(Opcode, DL, VTs, N1, N2, N3); 2934 CSEMap.InsertNode(N, IP); 2935 } else { 2936 N = NodeAllocator.Allocate<TernarySDNode>(); 2937 new (N) TernarySDNode(Opcode, DL, VTs, N1, N2, N3); 2938 } 2939 AllNodes.push_back(N); 2940#ifndef NDEBUG 2941 VerifyNode(N); 2942#endif 2943 return SDValue(N, 0); 2944} 2945 2946SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, 2947 SDValue N1, SDValue N2, SDValue N3, 2948 SDValue N4) { 2949 SDValue Ops[] = { N1, N2, N3, N4 }; 2950 return getNode(Opcode, DL, VT, Ops, 4); 2951} 2952 2953SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, 2954 SDValue N1, SDValue N2, SDValue N3, 2955 SDValue N4, SDValue N5) { 2956 SDValue Ops[] = { N1, N2, N3, N4, N5 }; 2957 return getNode(Opcode, DL, VT, Ops, 5); 2958} 2959 2960/// getMemsetValue - Vectorized representation of the memset value 2961/// operand. 2962static SDValue getMemsetValue(SDValue Value, MVT VT, SelectionDAG &DAG, 2963 DebugLoc dl) { 2964 unsigned NumBits = VT.isVector() ? 2965 VT.getVectorElementType().getSizeInBits() : VT.getSizeInBits(); 2966 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) { 2967 APInt Val = APInt(NumBits, C->getZExtValue() & 255); 2968 unsigned Shift = 8; 2969 for (unsigned i = NumBits; i > 8; i >>= 1) { 2970 Val = (Val << Shift) | Val; 2971 Shift <<= 1; 2972 } 2973 if (VT.isInteger()) 2974 return DAG.getConstant(Val, VT); 2975 return DAG.getConstantFP(APFloat(Val), VT); 2976 } 2977 2978 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 2979 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Value); 2980 unsigned Shift = 8; 2981 for (unsigned i = NumBits; i > 8; i >>= 1) { 2982 Value = DAG.getNode(ISD::OR, dl, VT, 2983 DAG.getNode(ISD::SHL, dl, VT, Value, 2984 DAG.getConstant(Shift, 2985 TLI.getShiftAmountTy())), 2986 Value); 2987 Shift <<= 1; 2988 } 2989 2990 return Value; 2991} 2992 2993/// getMemsetStringVal - Similar to getMemsetValue. Except this is only 2994/// used when a memcpy is turned into a memset when the source is a constant 2995/// string ptr. 2996static SDValue getMemsetStringVal(MVT VT, DebugLoc dl, SelectionDAG &DAG, 2997 const TargetLowering &TLI, 2998 std::string &Str, unsigned Offset) { 2999 // Handle vector with all elements zero. 3000 if (Str.empty()) { 3001 if (VT.isInteger()) 3002 return DAG.getConstant(0, VT); 3003 unsigned NumElts = VT.getVectorNumElements(); 3004 MVT EltVT = (VT.getVectorElementType() == MVT::f32) ? MVT::i32 : MVT::i64; 3005 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 3006 DAG.getConstant(0, MVT::getVectorVT(EltVT, NumElts))); 3007 } 3008 3009 assert(!VT.isVector() && "Can't handle vector type here!"); 3010 unsigned NumBits = VT.getSizeInBits(); 3011 unsigned MSB = NumBits / 8; 3012 uint64_t Val = 0; 3013 if (TLI.isLittleEndian()) 3014 Offset = Offset + MSB - 1; 3015 for (unsigned i = 0; i != MSB; ++i) { 3016 Val = (Val << 8) | (unsigned char)Str[Offset]; 3017 Offset += TLI.isLittleEndian() ? -1 : 1; 3018 } 3019 return DAG.getConstant(Val, VT); 3020} 3021 3022/// getMemBasePlusOffset - Returns base and offset node for the 3023/// 3024static SDValue getMemBasePlusOffset(SDValue Base, unsigned Offset, 3025 SelectionDAG &DAG) { 3026 MVT VT = Base.getValueType(); 3027 return DAG.getNode(ISD::ADD, Base.getDebugLoc(), 3028 VT, Base, DAG.getConstant(Offset, VT)); 3029} 3030 3031/// isMemSrcFromString - Returns true if memcpy source is a string constant. 3032/// 3033static bool isMemSrcFromString(SDValue Src, std::string &Str) { 3034 unsigned SrcDelta = 0; 3035 GlobalAddressSDNode *G = NULL; 3036 if (Src.getOpcode() == ISD::GlobalAddress) 3037 G = cast<GlobalAddressSDNode>(Src); 3038 else if (Src.getOpcode() == ISD::ADD && 3039 Src.getOperand(0).getOpcode() == ISD::GlobalAddress && 3040 Src.getOperand(1).getOpcode() == ISD::Constant) { 3041 G = cast<GlobalAddressSDNode>(Src.getOperand(0)); 3042 SrcDelta = cast<ConstantSDNode>(Src.getOperand(1))->getZExtValue(); 3043 } 3044 if (!G) 3045 return false; 3046 3047 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal()); 3048 if (GV && GetConstantStringInfo(GV, Str, SrcDelta, false)) 3049 return true; 3050 3051 return false; 3052} 3053 3054/// MeetsMaxMemopRequirement - Determines if the number of memory ops required 3055/// to replace the memset / memcpy is below the threshold. It also returns the 3056/// types of the sequence of memory ops to perform memset / memcpy. 3057static 3058bool MeetsMaxMemopRequirement(std::vector<MVT> &MemOps, 3059 SDValue Dst, SDValue Src, 3060 unsigned Limit, uint64_t Size, unsigned &Align, 3061 std::string &Str, bool &isSrcStr, 3062 SelectionDAG &DAG, 3063 const TargetLowering &TLI) { 3064 isSrcStr = isMemSrcFromString(Src, Str); 3065 bool isSrcConst = isa<ConstantSDNode>(Src); 3066 bool AllowUnalign = TLI.allowsUnalignedMemoryAccesses(); 3067 MVT VT = TLI.getOptimalMemOpType(Size, Align, isSrcConst, isSrcStr, DAG); 3068 if (VT != MVT::iAny) { 3069 unsigned NewAlign = (unsigned) 3070 TLI.getTargetData()->getABITypeAlignment(VT.getTypeForMVT()); 3071 // If source is a string constant, this will require an unaligned load. 3072 if (NewAlign > Align && (isSrcConst || AllowUnalign)) { 3073 if (Dst.getOpcode() != ISD::FrameIndex) { 3074 // Can't change destination alignment. It requires a unaligned store. 3075 if (AllowUnalign) 3076 VT = MVT::iAny; 3077 } else { 3078 int FI = cast<FrameIndexSDNode>(Dst)->getIndex(); 3079 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 3080 if (MFI->isFixedObjectIndex(FI)) { 3081 // Can't change destination alignment. It requires a unaligned store. 3082 if (AllowUnalign) 3083 VT = MVT::iAny; 3084 } else { 3085 // Give the stack frame object a larger alignment if needed. 3086 if (MFI->getObjectAlignment(FI) < NewAlign) 3087 MFI->setObjectAlignment(FI, NewAlign); 3088 Align = NewAlign; 3089 } 3090 } 3091 } 3092 } 3093 3094 if (VT == MVT::iAny) { 3095 if (AllowUnalign) { 3096 VT = MVT::i64; 3097 } else { 3098 switch (Align & 7) { 3099 case 0: VT = MVT::i64; break; 3100 case 4: VT = MVT::i32; break; 3101 case 2: VT = MVT::i16; break; 3102 default: VT = MVT::i8; break; 3103 } 3104 } 3105 3106 MVT LVT = MVT::i64; 3107 while (!TLI.isTypeLegal(LVT)) 3108 LVT = (MVT::SimpleValueType)(LVT.getSimpleVT() - 1); 3109 assert(LVT.isInteger()); 3110 3111 if (VT.bitsGT(LVT)) 3112 VT = LVT; 3113 } 3114 3115 unsigned NumMemOps = 0; 3116 while (Size != 0) { 3117 unsigned VTSize = VT.getSizeInBits() / 8; 3118 while (VTSize > Size) { 3119 // For now, only use non-vector load / store's for the left-over pieces. 3120 if (VT.isVector()) { 3121 VT = MVT::i64; 3122 while (!TLI.isTypeLegal(VT)) 3123 VT = (MVT::SimpleValueType)(VT.getSimpleVT() - 1); 3124 VTSize = VT.getSizeInBits() / 8; 3125 } else { 3126 // This can result in a type that is not legal on the target, e.g. 3127 // 1 or 2 bytes on PPC. 3128 VT = (MVT::SimpleValueType)(VT.getSimpleVT() - 1); 3129 VTSize >>= 1; 3130 } 3131 } 3132 3133 if (++NumMemOps > Limit) 3134 return false; 3135 MemOps.push_back(VT); 3136 Size -= VTSize; 3137 } 3138 3139 return true; 3140} 3141 3142static SDValue getMemcpyLoadsAndStores(SelectionDAG &DAG, DebugLoc dl, 3143 SDValue Chain, SDValue Dst, 3144 SDValue Src, uint64_t Size, 3145 unsigned Align, bool AlwaysInline, 3146 const Value *DstSV, uint64_t DstSVOff, 3147 const Value *SrcSV, uint64_t SrcSVOff){ 3148 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 3149 3150 // Expand memcpy to a series of load and store ops if the size operand falls 3151 // below a certain threshold. 3152 std::vector<MVT> MemOps; 3153 uint64_t Limit = -1ULL; 3154 if (!AlwaysInline) 3155 Limit = TLI.getMaxStoresPerMemcpy(); 3156 unsigned DstAlign = Align; // Destination alignment can change. 3157 std::string Str; 3158 bool CopyFromStr; 3159 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, Limit, Size, DstAlign, 3160 Str, CopyFromStr, DAG, TLI)) 3161 return SDValue(); 3162 3163 3164 bool isZeroStr = CopyFromStr && Str.empty(); 3165 SmallVector<SDValue, 8> OutChains; 3166 unsigned NumMemOps = MemOps.size(); 3167 uint64_t SrcOff = 0, DstOff = 0; 3168 for (unsigned i = 0; i < NumMemOps; i++) { 3169 MVT VT = MemOps[i]; 3170 unsigned VTSize = VT.getSizeInBits() / 8; 3171 SDValue Value, Store; 3172 3173 if (CopyFromStr && (isZeroStr || !VT.isVector())) { 3174 // It's unlikely a store of a vector immediate can be done in a single 3175 // instruction. It would require a load from a constantpool first. 3176 // We also handle store a vector with all zero's. 3177 // FIXME: Handle other cases where store of vector immediate is done in 3178 // a single instruction. 3179 Value = getMemsetStringVal(VT, dl, DAG, TLI, Str, SrcOff); 3180 Store = DAG.getStore(Chain, dl, Value, 3181 getMemBasePlusOffset(Dst, DstOff, DAG), 3182 DstSV, DstSVOff + DstOff, false, DstAlign); 3183 } else { 3184 // The type might not be legal for the target. This should only happen 3185 // if the type is smaller than a legal type, as on PPC, so the right 3186 // thing to do is generate a LoadExt/StoreTrunc pair. These simplify 3187 // to Load/Store if NVT==VT. 3188 // FIXME does the case above also need this? 3189 MVT NVT = TLI.getTypeToTransformTo(VT); 3190 assert(NVT.bitsGE(VT)); 3191 Value = DAG.getExtLoad(ISD::EXTLOAD, dl, NVT, Chain, 3192 getMemBasePlusOffset(Src, SrcOff, DAG), 3193 SrcSV, SrcSVOff + SrcOff, VT, false, Align); 3194 Store = DAG.getTruncStore(Chain, dl, Value, 3195 getMemBasePlusOffset(Dst, DstOff, DAG), 3196 DstSV, DstSVOff + DstOff, VT, false, DstAlign); 3197 } 3198 OutChains.push_back(Store); 3199 SrcOff += VTSize; 3200 DstOff += VTSize; 3201 } 3202 3203 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3204 &OutChains[0], OutChains.size()); 3205} 3206 3207static SDValue getMemmoveLoadsAndStores(SelectionDAG &DAG, DebugLoc dl, 3208 SDValue Chain, SDValue Dst, 3209 SDValue Src, uint64_t Size, 3210 unsigned Align, bool AlwaysInline, 3211 const Value *DstSV, uint64_t DstSVOff, 3212 const Value *SrcSV, uint64_t SrcSVOff){ 3213 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 3214 3215 // Expand memmove to a series of load and store ops if the size operand falls 3216 // below a certain threshold. 3217 std::vector<MVT> MemOps; 3218 uint64_t Limit = -1ULL; 3219 if (!AlwaysInline) 3220 Limit = TLI.getMaxStoresPerMemmove(); 3221 unsigned DstAlign = Align; // Destination alignment can change. 3222 std::string Str; 3223 bool CopyFromStr; 3224 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, Limit, Size, DstAlign, 3225 Str, CopyFromStr, DAG, TLI)) 3226 return SDValue(); 3227 3228 uint64_t SrcOff = 0, DstOff = 0; 3229 3230 SmallVector<SDValue, 8> LoadValues; 3231 SmallVector<SDValue, 8> LoadChains; 3232 SmallVector<SDValue, 8> OutChains; 3233 unsigned NumMemOps = MemOps.size(); 3234 for (unsigned i = 0; i < NumMemOps; i++) { 3235 MVT VT = MemOps[i]; 3236 unsigned VTSize = VT.getSizeInBits() / 8; 3237 SDValue Value, Store; 3238 3239 Value = DAG.getLoad(VT, dl, Chain, 3240 getMemBasePlusOffset(Src, SrcOff, DAG), 3241 SrcSV, SrcSVOff + SrcOff, false, Align); 3242 LoadValues.push_back(Value); 3243 LoadChains.push_back(Value.getValue(1)); 3244 SrcOff += VTSize; 3245 } 3246 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3247 &LoadChains[0], LoadChains.size()); 3248 OutChains.clear(); 3249 for (unsigned i = 0; i < NumMemOps; i++) { 3250 MVT VT = MemOps[i]; 3251 unsigned VTSize = VT.getSizeInBits() / 8; 3252 SDValue Value, Store; 3253 3254 Store = DAG.getStore(Chain, dl, LoadValues[i], 3255 getMemBasePlusOffset(Dst, DstOff, DAG), 3256 DstSV, DstSVOff + DstOff, false, DstAlign); 3257 OutChains.push_back(Store); 3258 DstOff += VTSize; 3259 } 3260 3261 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3262 &OutChains[0], OutChains.size()); 3263} 3264 3265static SDValue getMemsetStores(SelectionDAG &DAG, DebugLoc dl, 3266 SDValue Chain, SDValue Dst, 3267 SDValue Src, uint64_t Size, 3268 unsigned Align, 3269 const Value *DstSV, uint64_t DstSVOff) { 3270 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 3271 3272 // Expand memset to a series of load/store ops if the size operand 3273 // falls below a certain threshold. 3274 std::vector<MVT> MemOps; 3275 std::string Str; 3276 bool CopyFromStr; 3277 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, TLI.getMaxStoresPerMemset(), 3278 Size, Align, Str, CopyFromStr, DAG, TLI)) 3279 return SDValue(); 3280 3281 SmallVector<SDValue, 8> OutChains; 3282 uint64_t DstOff = 0; 3283 3284 unsigned NumMemOps = MemOps.size(); 3285 for (unsigned i = 0; i < NumMemOps; i++) { 3286 MVT VT = MemOps[i]; 3287 unsigned VTSize = VT.getSizeInBits() / 8; 3288 SDValue Value = getMemsetValue(Src, VT, DAG, dl); 3289 SDValue Store = DAG.getStore(Chain, dl, Value, 3290 getMemBasePlusOffset(Dst, DstOff, DAG), 3291 DstSV, DstSVOff + DstOff); 3292 OutChains.push_back(Store); 3293 DstOff += VTSize; 3294 } 3295 3296 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3297 &OutChains[0], OutChains.size()); 3298} 3299 3300SDValue SelectionDAG::getMemcpy(SDValue Chain, DebugLoc dl, SDValue Dst, 3301 SDValue Src, SDValue Size, 3302 unsigned Align, bool AlwaysInline, 3303 const Value *DstSV, uint64_t DstSVOff, 3304 const Value *SrcSV, uint64_t SrcSVOff) { 3305 3306 // Check to see if we should lower the memcpy to loads and stores first. 3307 // For cases within the target-specified limits, this is the best choice. 3308 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 3309 if (ConstantSize) { 3310 // Memcpy with size zero? Just return the original chain. 3311 if (ConstantSize->isNullValue()) 3312 return Chain; 3313 3314 SDValue Result = 3315 getMemcpyLoadsAndStores(*this, dl, Chain, Dst, Src, 3316 ConstantSize->getZExtValue(), 3317 Align, false, DstSV, DstSVOff, SrcSV, SrcSVOff); 3318 if (Result.getNode()) 3319 return Result; 3320 } 3321 3322 // Then check to see if we should lower the memcpy with target-specific 3323 // code. If the target chooses to do this, this is the next best. 3324 SDValue Result = 3325 TLI.EmitTargetCodeForMemcpy(*this, dl, Chain, Dst, Src, Size, Align, 3326 AlwaysInline, 3327 DstSV, DstSVOff, SrcSV, SrcSVOff); 3328 if (Result.getNode()) 3329 return Result; 3330 3331 // If we really need inline code and the target declined to provide it, 3332 // use a (potentially long) sequence of loads and stores. 3333 if (AlwaysInline) { 3334 assert(ConstantSize && "AlwaysInline requires a constant size!"); 3335 return getMemcpyLoadsAndStores(*this, dl, Chain, Dst, Src, 3336 ConstantSize->getZExtValue(), Align, true, 3337 DstSV, DstSVOff, SrcSV, SrcSVOff); 3338 } 3339 3340 // Emit a library call. 3341 TargetLowering::ArgListTy Args; 3342 TargetLowering::ArgListEntry Entry; 3343 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 3344 Entry.Node = Dst; Args.push_back(Entry); 3345 Entry.Node = Src; Args.push_back(Entry); 3346 Entry.Node = Size; Args.push_back(Entry); 3347 // FIXME: pass in DebugLoc 3348 std::pair<SDValue,SDValue> CallResult = 3349 TLI.LowerCallTo(Chain, Type::VoidTy, 3350 false, false, false, false, CallingConv::C, false, 3351 getExternalSymbol("memcpy", TLI.getPointerTy()), 3352 Args, *this, dl); 3353 return CallResult.second; 3354} 3355 3356SDValue SelectionDAG::getMemmove(SDValue Chain, DebugLoc dl, SDValue Dst, 3357 SDValue Src, SDValue Size, 3358 unsigned Align, 3359 const Value *DstSV, uint64_t DstSVOff, 3360 const Value *SrcSV, uint64_t SrcSVOff) { 3361 3362 // Check to see if we should lower the memmove to loads and stores first. 3363 // For cases within the target-specified limits, this is the best choice. 3364 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 3365 if (ConstantSize) { 3366 // Memmove with size zero? Just return the original chain. 3367 if (ConstantSize->isNullValue()) 3368 return Chain; 3369 3370 SDValue Result = 3371 getMemmoveLoadsAndStores(*this, dl, Chain, Dst, Src, 3372 ConstantSize->getZExtValue(), 3373 Align, false, DstSV, DstSVOff, SrcSV, SrcSVOff); 3374 if (Result.getNode()) 3375 return Result; 3376 } 3377 3378 // Then check to see if we should lower the memmove with target-specific 3379 // code. If the target chooses to do this, this is the next best. 3380 SDValue Result = 3381 TLI.EmitTargetCodeForMemmove(*this, dl, Chain, Dst, Src, Size, Align, 3382 DstSV, DstSVOff, SrcSV, SrcSVOff); 3383 if (Result.getNode()) 3384 return Result; 3385 3386 // Emit a library call. 3387 TargetLowering::ArgListTy Args; 3388 TargetLowering::ArgListEntry Entry; 3389 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 3390 Entry.Node = Dst; Args.push_back(Entry); 3391 Entry.Node = Src; Args.push_back(Entry); 3392 Entry.Node = Size; Args.push_back(Entry); 3393 // FIXME: pass in DebugLoc 3394 std::pair<SDValue,SDValue> CallResult = 3395 TLI.LowerCallTo(Chain, Type::VoidTy, 3396 false, false, false, false, CallingConv::C, false, 3397 getExternalSymbol("memmove", TLI.getPointerTy()), 3398 Args, *this, dl); 3399 return CallResult.second; 3400} 3401 3402SDValue SelectionDAG::getMemset(SDValue Chain, DebugLoc dl, SDValue Dst, 3403 SDValue Src, SDValue Size, 3404 unsigned Align, 3405 const Value *DstSV, uint64_t DstSVOff) { 3406 3407 // Check to see if we should lower the memset to stores first. 3408 // For cases within the target-specified limits, this is the best choice. 3409 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 3410 if (ConstantSize) { 3411 // Memset with size zero? Just return the original chain. 3412 if (ConstantSize->isNullValue()) 3413 return Chain; 3414 3415 SDValue Result = 3416 getMemsetStores(*this, dl, Chain, Dst, Src, ConstantSize->getZExtValue(), 3417 Align, DstSV, DstSVOff); 3418 if (Result.getNode()) 3419 return Result; 3420 } 3421 3422 // Then check to see if we should lower the memset with target-specific 3423 // code. If the target chooses to do this, this is the next best. 3424 SDValue Result = 3425 TLI.EmitTargetCodeForMemset(*this, dl, Chain, Dst, Src, Size, Align, 3426 DstSV, DstSVOff); 3427 if (Result.getNode()) 3428 return Result; 3429 3430 // Emit a library call. 3431 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType(); 3432 TargetLowering::ArgListTy Args; 3433 TargetLowering::ArgListEntry Entry; 3434 Entry.Node = Dst; Entry.Ty = IntPtrTy; 3435 Args.push_back(Entry); 3436 // Extend or truncate the argument to be an i32 value for the call. 3437 if (Src.getValueType().bitsGT(MVT::i32)) 3438 Src = getNode(ISD::TRUNCATE, dl, MVT::i32, Src); 3439 else 3440 Src = getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Src); 3441 Entry.Node = Src; Entry.Ty = Type::Int32Ty; Entry.isSExt = true; 3442 Args.push_back(Entry); 3443 Entry.Node = Size; Entry.Ty = IntPtrTy; Entry.isSExt = false; 3444 Args.push_back(Entry); 3445 // FIXME: pass in DebugLoc 3446 std::pair<SDValue,SDValue> CallResult = 3447 TLI.LowerCallTo(Chain, Type::VoidTy, 3448 false, false, false, false, CallingConv::C, false, 3449 getExternalSymbol("memset", TLI.getPointerTy()), 3450 Args, *this, dl); 3451 return CallResult.second; 3452} 3453 3454SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, MVT MemVT, 3455 SDValue Chain, 3456 SDValue Ptr, SDValue Cmp, 3457 SDValue Swp, const Value* PtrVal, 3458 unsigned Alignment) { 3459 assert(Opcode == ISD::ATOMIC_CMP_SWAP && "Invalid Atomic Op"); 3460 assert(Cmp.getValueType() == Swp.getValueType() && "Invalid Atomic Op Types"); 3461 3462 MVT VT = Cmp.getValueType(); 3463 3464 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3465 Alignment = getMVTAlignment(MemVT); 3466 3467 SDVTList VTs = getVTList(VT, MVT::Other); 3468 FoldingSetNodeID ID; 3469 ID.AddInteger(MemVT.getRawBits()); 3470 SDValue Ops[] = {Chain, Ptr, Cmp, Swp}; 3471 AddNodeIDNode(ID, Opcode, VTs, Ops, 4); 3472 void* IP = 0; 3473 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3474 return SDValue(E, 0); 3475 SDNode* N = NodeAllocator.Allocate<AtomicSDNode>(); 3476 new (N) AtomicSDNode(Opcode, dl, VTs, MemVT, 3477 Chain, Ptr, Cmp, Swp, PtrVal, Alignment); 3478 CSEMap.InsertNode(N, IP); 3479 AllNodes.push_back(N); 3480 return SDValue(N, 0); 3481} 3482 3483SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, MVT MemVT, 3484 SDValue Chain, 3485 SDValue Ptr, SDValue Val, 3486 const Value* PtrVal, 3487 unsigned Alignment) { 3488 assert((Opcode == ISD::ATOMIC_LOAD_ADD || 3489 Opcode == ISD::ATOMIC_LOAD_SUB || 3490 Opcode == ISD::ATOMIC_LOAD_AND || 3491 Opcode == ISD::ATOMIC_LOAD_OR || 3492 Opcode == ISD::ATOMIC_LOAD_XOR || 3493 Opcode == ISD::ATOMIC_LOAD_NAND || 3494 Opcode == ISD::ATOMIC_LOAD_MIN || 3495 Opcode == ISD::ATOMIC_LOAD_MAX || 3496 Opcode == ISD::ATOMIC_LOAD_UMIN || 3497 Opcode == ISD::ATOMIC_LOAD_UMAX || 3498 Opcode == ISD::ATOMIC_SWAP) && 3499 "Invalid Atomic Op"); 3500 3501 MVT VT = Val.getValueType(); 3502 3503 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3504 Alignment = getMVTAlignment(MemVT); 3505 3506 SDVTList VTs = getVTList(VT, MVT::Other); 3507 FoldingSetNodeID ID; 3508 ID.AddInteger(MemVT.getRawBits()); 3509 SDValue Ops[] = {Chain, Ptr, Val}; 3510 AddNodeIDNode(ID, Opcode, VTs, Ops, 3); 3511 void* IP = 0; 3512 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3513 return SDValue(E, 0); 3514 SDNode* N = NodeAllocator.Allocate<AtomicSDNode>(); 3515 new (N) AtomicSDNode(Opcode, dl, VTs, MemVT, 3516 Chain, Ptr, Val, PtrVal, Alignment); 3517 CSEMap.InsertNode(N, IP); 3518 AllNodes.push_back(N); 3519 return SDValue(N, 0); 3520} 3521 3522/// getMergeValues - Create a MERGE_VALUES node from the given operands. 3523/// Allowed to return something different (and simpler) if Simplify is true. 3524SDValue SelectionDAG::getMergeValues(const SDValue *Ops, unsigned NumOps, 3525 DebugLoc dl) { 3526 if (NumOps == 1) 3527 return Ops[0]; 3528 3529 SmallVector<MVT, 4> VTs; 3530 VTs.reserve(NumOps); 3531 for (unsigned i = 0; i < NumOps; ++i) 3532 VTs.push_back(Ops[i].getValueType()); 3533 return getNode(ISD::MERGE_VALUES, dl, getVTList(&VTs[0], NumOps), 3534 Ops, NumOps); 3535} 3536 3537SDValue 3538SelectionDAG::getMemIntrinsicNode(unsigned Opcode, DebugLoc dl, 3539 const MVT *VTs, unsigned NumVTs, 3540 const SDValue *Ops, unsigned NumOps, 3541 MVT MemVT, const Value *srcValue, int SVOff, 3542 unsigned Align, bool Vol, 3543 bool ReadMem, bool WriteMem) { 3544 return getMemIntrinsicNode(Opcode, dl, makeVTList(VTs, NumVTs), Ops, NumOps, 3545 MemVT, srcValue, SVOff, Align, Vol, 3546 ReadMem, WriteMem); 3547} 3548 3549SDValue 3550SelectionDAG::getMemIntrinsicNode(unsigned Opcode, DebugLoc dl, SDVTList VTList, 3551 const SDValue *Ops, unsigned NumOps, 3552 MVT MemVT, const Value *srcValue, int SVOff, 3553 unsigned Align, bool Vol, 3554 bool ReadMem, bool WriteMem) { 3555 // Memoize the node unless it returns a flag. 3556 MemIntrinsicSDNode *N; 3557 if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) { 3558 FoldingSetNodeID ID; 3559 AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps); 3560 void *IP = 0; 3561 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3562 return SDValue(E, 0); 3563 3564 N = NodeAllocator.Allocate<MemIntrinsicSDNode>(); 3565 new (N) MemIntrinsicSDNode(Opcode, dl, VTList, Ops, NumOps, MemVT, 3566 srcValue, SVOff, Align, Vol, ReadMem, WriteMem); 3567 CSEMap.InsertNode(N, IP); 3568 } else { 3569 N = NodeAllocator.Allocate<MemIntrinsicSDNode>(); 3570 new (N) MemIntrinsicSDNode(Opcode, dl, VTList, Ops, NumOps, MemVT, 3571 srcValue, SVOff, Align, Vol, ReadMem, WriteMem); 3572 } 3573 AllNodes.push_back(N); 3574 return SDValue(N, 0); 3575} 3576 3577SDValue 3578SelectionDAG::getCall(unsigned CallingConv, DebugLoc dl, bool IsVarArgs, 3579 bool IsTailCall, bool IsInreg, SDVTList VTs, 3580 const SDValue *Operands, unsigned NumOperands) { 3581 // Do not include isTailCall in the folding set profile. 3582 FoldingSetNodeID ID; 3583 AddNodeIDNode(ID, ISD::CALL, VTs, Operands, NumOperands); 3584 ID.AddInteger(CallingConv); 3585 ID.AddInteger(IsVarArgs); 3586 void *IP = 0; 3587 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) { 3588 // Instead of including isTailCall in the folding set, we just 3589 // set the flag of the existing node. 3590 if (!IsTailCall) 3591 cast<CallSDNode>(E)->setNotTailCall(); 3592 return SDValue(E, 0); 3593 } 3594 SDNode *N = NodeAllocator.Allocate<CallSDNode>(); 3595 new (N) CallSDNode(CallingConv, dl, IsVarArgs, IsTailCall, IsInreg, 3596 VTs, Operands, NumOperands); 3597 CSEMap.InsertNode(N, IP); 3598 AllNodes.push_back(N); 3599 return SDValue(N, 0); 3600} 3601 3602SDValue 3603SelectionDAG::getLoad(ISD::MemIndexedMode AM, DebugLoc dl, 3604 ISD::LoadExtType ExtType, MVT VT, SDValue Chain, 3605 SDValue Ptr, SDValue Offset, 3606 const Value *SV, int SVOffset, MVT EVT, 3607 bool isVolatile, unsigned Alignment) { 3608 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3609 Alignment = getMVTAlignment(VT); 3610 3611 if (VT == EVT) { 3612 ExtType = ISD::NON_EXTLOAD; 3613 } else if (ExtType == ISD::NON_EXTLOAD) { 3614 assert(VT == EVT && "Non-extending load from different memory type!"); 3615 } else { 3616 // Extending load. 3617 if (VT.isVector()) 3618 assert(EVT.getVectorNumElements() == VT.getVectorNumElements() && 3619 "Invalid vector extload!"); 3620 else 3621 assert(EVT.bitsLT(VT) && 3622 "Should only be an extending load, not truncating!"); 3623 assert((ExtType == ISD::EXTLOAD || VT.isInteger()) && 3624 "Cannot sign/zero extend a FP/Vector load!"); 3625 assert(VT.isInteger() == EVT.isInteger() && 3626 "Cannot convert from FP to Int or Int -> FP!"); 3627 } 3628 3629 bool Indexed = AM != ISD::UNINDEXED; 3630 assert((Indexed || Offset.getOpcode() == ISD::UNDEF) && 3631 "Unindexed load with an offset!"); 3632 3633 SDVTList VTs = Indexed ? 3634 getVTList(VT, Ptr.getValueType(), MVT::Other) : getVTList(VT, MVT::Other); 3635 SDValue Ops[] = { Chain, Ptr, Offset }; 3636 FoldingSetNodeID ID; 3637 AddNodeIDNode(ID, ISD::LOAD, VTs, Ops, 3); 3638 ID.AddInteger(EVT.getRawBits()); 3639 ID.AddInteger(encodeMemSDNodeFlags(ExtType, AM, isVolatile, Alignment)); 3640 void *IP = 0; 3641 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3642 return SDValue(E, 0); 3643 SDNode *N = NodeAllocator.Allocate<LoadSDNode>(); 3644 new (N) LoadSDNode(Ops, dl, VTs, AM, ExtType, EVT, SV, SVOffset, 3645 Alignment, isVolatile); 3646 CSEMap.InsertNode(N, IP); 3647 AllNodes.push_back(N); 3648 return SDValue(N, 0); 3649} 3650 3651SDValue SelectionDAG::getLoad(MVT VT, DebugLoc dl, 3652 SDValue Chain, SDValue Ptr, 3653 const Value *SV, int SVOffset, 3654 bool isVolatile, unsigned Alignment) { 3655 SDValue Undef = getUNDEF(Ptr.getValueType()); 3656 return getLoad(ISD::UNINDEXED, dl, ISD::NON_EXTLOAD, VT, Chain, Ptr, Undef, 3657 SV, SVOffset, VT, isVolatile, Alignment); 3658} 3659 3660SDValue SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, DebugLoc dl, MVT VT, 3661 SDValue Chain, SDValue Ptr, 3662 const Value *SV, 3663 int SVOffset, MVT EVT, 3664 bool isVolatile, unsigned Alignment) { 3665 SDValue Undef = getUNDEF(Ptr.getValueType()); 3666 return getLoad(ISD::UNINDEXED, dl, ExtType, VT, Chain, Ptr, Undef, 3667 SV, SVOffset, EVT, isVolatile, Alignment); 3668} 3669 3670SDValue 3671SelectionDAG::getIndexedLoad(SDValue OrigLoad, DebugLoc dl, SDValue Base, 3672 SDValue Offset, ISD::MemIndexedMode AM) { 3673 LoadSDNode *LD = cast<LoadSDNode>(OrigLoad); 3674 assert(LD->getOffset().getOpcode() == ISD::UNDEF && 3675 "Load is already a indexed load!"); 3676 return getLoad(AM, dl, LD->getExtensionType(), OrigLoad.getValueType(), 3677 LD->getChain(), Base, Offset, LD->getSrcValue(), 3678 LD->getSrcValueOffset(), LD->getMemoryVT(), 3679 LD->isVolatile(), LD->getAlignment()); 3680} 3681 3682SDValue SelectionDAG::getStore(SDValue Chain, DebugLoc dl, SDValue Val, 3683 SDValue Ptr, const Value *SV, int SVOffset, 3684 bool isVolatile, unsigned Alignment) { 3685 MVT VT = Val.getValueType(); 3686 3687 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3688 Alignment = getMVTAlignment(VT); 3689 3690 SDVTList VTs = getVTList(MVT::Other); 3691 SDValue Undef = getUNDEF(Ptr.getValueType()); 3692 SDValue Ops[] = { Chain, Val, Ptr, Undef }; 3693 FoldingSetNodeID ID; 3694 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); 3695 ID.AddInteger(VT.getRawBits()); 3696 ID.AddInteger(encodeMemSDNodeFlags(false, ISD::UNINDEXED, 3697 isVolatile, Alignment)); 3698 void *IP = 0; 3699 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3700 return SDValue(E, 0); 3701 SDNode *N = NodeAllocator.Allocate<StoreSDNode>(); 3702 new (N) StoreSDNode(Ops, dl, VTs, ISD::UNINDEXED, false, 3703 VT, SV, SVOffset, Alignment, isVolatile); 3704 CSEMap.InsertNode(N, IP); 3705 AllNodes.push_back(N); 3706 return SDValue(N, 0); 3707} 3708 3709SDValue SelectionDAG::getTruncStore(SDValue Chain, DebugLoc dl, SDValue Val, 3710 SDValue Ptr, const Value *SV, 3711 int SVOffset, MVT SVT, 3712 bool isVolatile, unsigned Alignment) { 3713 MVT VT = Val.getValueType(); 3714 3715 if (VT == SVT) 3716 return getStore(Chain, dl, Val, Ptr, SV, SVOffset, isVolatile, Alignment); 3717 3718 assert(VT.bitsGT(SVT) && "Not a truncation?"); 3719 assert(VT.isInteger() == SVT.isInteger() && 3720 "Can't do FP-INT conversion!"); 3721 3722 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3723 Alignment = getMVTAlignment(VT); 3724 3725 SDVTList VTs = getVTList(MVT::Other); 3726 SDValue Undef = getUNDEF(Ptr.getValueType()); 3727 SDValue Ops[] = { Chain, Val, Ptr, Undef }; 3728 FoldingSetNodeID ID; 3729 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); 3730 ID.AddInteger(SVT.getRawBits()); 3731 ID.AddInteger(encodeMemSDNodeFlags(true, ISD::UNINDEXED, 3732 isVolatile, Alignment)); 3733 void *IP = 0; 3734 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3735 return SDValue(E, 0); 3736 SDNode *N = NodeAllocator.Allocate<StoreSDNode>(); 3737 new (N) StoreSDNode(Ops, dl, VTs, ISD::UNINDEXED, true, 3738 SVT, SV, SVOffset, Alignment, isVolatile); 3739 CSEMap.InsertNode(N, IP); 3740 AllNodes.push_back(N); 3741 return SDValue(N, 0); 3742} 3743 3744SDValue 3745SelectionDAG::getIndexedStore(SDValue OrigStore, DebugLoc dl, SDValue Base, 3746 SDValue Offset, ISD::MemIndexedMode AM) { 3747 StoreSDNode *ST = cast<StoreSDNode>(OrigStore); 3748 assert(ST->getOffset().getOpcode() == ISD::UNDEF && 3749 "Store is already a indexed store!"); 3750 SDVTList VTs = getVTList(Base.getValueType(), MVT::Other); 3751 SDValue Ops[] = { ST->getChain(), ST->getValue(), Base, Offset }; 3752 FoldingSetNodeID ID; 3753 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); 3754 ID.AddInteger(ST->getMemoryVT().getRawBits()); 3755 ID.AddInteger(ST->getRawSubclassData()); 3756 void *IP = 0; 3757 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3758 return SDValue(E, 0); 3759 SDNode *N = NodeAllocator.Allocate<StoreSDNode>(); 3760 new (N) StoreSDNode(Ops, dl, VTs, AM, 3761 ST->isTruncatingStore(), ST->getMemoryVT(), 3762 ST->getSrcValue(), ST->getSrcValueOffset(), 3763 ST->getAlignment(), ST->isVolatile()); 3764 CSEMap.InsertNode(N, IP); 3765 AllNodes.push_back(N); 3766 return SDValue(N, 0); 3767} 3768 3769SDValue SelectionDAG::getVAArg(MVT VT, DebugLoc dl, 3770 SDValue Chain, SDValue Ptr, 3771 SDValue SV) { 3772 SDValue Ops[] = { Chain, Ptr, SV }; 3773 return getNode(ISD::VAARG, dl, getVTList(VT, MVT::Other), Ops, 3); 3774} 3775 3776SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, 3777 const SDUse *Ops, unsigned NumOps) { 3778 switch (NumOps) { 3779 case 0: return getNode(Opcode, DL, VT); 3780 case 1: return getNode(Opcode, DL, VT, Ops[0]); 3781 case 2: return getNode(Opcode, DL, VT, Ops[0], Ops[1]); 3782 case 3: return getNode(Opcode, DL, VT, Ops[0], Ops[1], Ops[2]); 3783 default: break; 3784 } 3785 3786 // Copy from an SDUse array into an SDValue array for use with 3787 // the regular getNode logic. 3788 SmallVector<SDValue, 8> NewOps(Ops, Ops + NumOps); 3789 return getNode(Opcode, DL, VT, &NewOps[0], NumOps); 3790} 3791 3792SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, 3793 const SDValue *Ops, unsigned NumOps) { 3794 switch (NumOps) { 3795 case 0: return getNode(Opcode, DL, VT); 3796 case 1: return getNode(Opcode, DL, VT, Ops[0]); 3797 case 2: return getNode(Opcode, DL, VT, Ops[0], Ops[1]); 3798 case 3: return getNode(Opcode, DL, VT, Ops[0], Ops[1], Ops[2]); 3799 default: break; 3800 } 3801 3802 switch (Opcode) { 3803 default: break; 3804 case ISD::SELECT_CC: { 3805 assert(NumOps == 5 && "SELECT_CC takes 5 operands!"); 3806 assert(Ops[0].getValueType() == Ops[1].getValueType() && 3807 "LHS and RHS of condition must have same type!"); 3808 assert(Ops[2].getValueType() == Ops[3].getValueType() && 3809 "True and False arms of SelectCC must have same type!"); 3810 assert(Ops[2].getValueType() == VT && 3811 "select_cc node must be of same type as true and false value!"); 3812 break; 3813 } 3814 case ISD::BR_CC: { 3815 assert(NumOps == 5 && "BR_CC takes 5 operands!"); 3816 assert(Ops[2].getValueType() == Ops[3].getValueType() && 3817 "LHS/RHS of comparison should match types!"); 3818 break; 3819 } 3820 } 3821 3822 // Memoize nodes. 3823 SDNode *N; 3824 SDVTList VTs = getVTList(VT); 3825 3826 if (VT != MVT::Flag) { 3827 FoldingSetNodeID ID; 3828 AddNodeIDNode(ID, Opcode, VTs, Ops, NumOps); 3829 void *IP = 0; 3830 3831 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3832 return SDValue(E, 0); 3833 3834 N = NodeAllocator.Allocate<SDNode>(); 3835 new (N) SDNode(Opcode, DL, VTs, Ops, NumOps); 3836 CSEMap.InsertNode(N, IP); 3837 } else { 3838 N = NodeAllocator.Allocate<SDNode>(); 3839 new (N) SDNode(Opcode, DL, VTs, Ops, NumOps); 3840 } 3841 3842 AllNodes.push_back(N); 3843#ifndef NDEBUG 3844 VerifyNode(N); 3845#endif 3846 return SDValue(N, 0); 3847} 3848 3849SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, 3850 const std::vector<MVT> &ResultTys, 3851 const SDValue *Ops, unsigned NumOps) { 3852 return getNode(Opcode, DL, getVTList(&ResultTys[0], ResultTys.size()), 3853 Ops, NumOps); 3854} 3855 3856SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, 3857 const MVT *VTs, unsigned NumVTs, 3858 const SDValue *Ops, unsigned NumOps) { 3859 if (NumVTs == 1) 3860 return getNode(Opcode, DL, VTs[0], Ops, NumOps); 3861 return getNode(Opcode, DL, makeVTList(VTs, NumVTs), Ops, NumOps); 3862} 3863 3864SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, 3865 const SDValue *Ops, unsigned NumOps) { 3866 if (VTList.NumVTs == 1) 3867 return getNode(Opcode, DL, VTList.VTs[0], Ops, NumOps); 3868 3869 switch (Opcode) { 3870 // FIXME: figure out how to safely handle things like 3871 // int foo(int x) { return 1 << (x & 255); } 3872 // int bar() { return foo(256); } 3873#if 0 3874 case ISD::SRA_PARTS: 3875 case ISD::SRL_PARTS: 3876 case ISD::SHL_PARTS: 3877 if (N3.getOpcode() == ISD::SIGN_EXTEND_INREG && 3878 cast<VTSDNode>(N3.getOperand(1))->getVT() != MVT::i1) 3879 return getNode(Opcode, DL, VT, N1, N2, N3.getOperand(0)); 3880 else if (N3.getOpcode() == ISD::AND) 3881 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(N3.getOperand(1))) { 3882 // If the and is only masking out bits that cannot effect the shift, 3883 // eliminate the and. 3884 unsigned NumBits = VT.getSizeInBits()*2; 3885 if ((AndRHS->getValue() & (NumBits-1)) == NumBits-1) 3886 return getNode(Opcode, DL, VT, N1, N2, N3.getOperand(0)); 3887 } 3888 break; 3889#endif 3890 } 3891 3892 // Memoize the node unless it returns a flag. 3893 SDNode *N; 3894 if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) { 3895 FoldingSetNodeID ID; 3896 AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps); 3897 void *IP = 0; 3898 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3899 return SDValue(E, 0); 3900 if (NumOps == 1) { 3901 N = NodeAllocator.Allocate<UnarySDNode>(); 3902 new (N) UnarySDNode(Opcode, DL, VTList, Ops[0]); 3903 } else if (NumOps == 2) { 3904 N = NodeAllocator.Allocate<BinarySDNode>(); 3905 new (N) BinarySDNode(Opcode, DL, VTList, Ops[0], Ops[1]); 3906 } else if (NumOps == 3) { 3907 N = NodeAllocator.Allocate<TernarySDNode>(); 3908 new (N) TernarySDNode(Opcode, DL, VTList, Ops[0], Ops[1], Ops[2]); 3909 } else { 3910 N = NodeAllocator.Allocate<SDNode>(); 3911 new (N) SDNode(Opcode, DL, VTList, Ops, NumOps); 3912 } 3913 CSEMap.InsertNode(N, IP); 3914 } else { 3915 if (NumOps == 1) { 3916 N = NodeAllocator.Allocate<UnarySDNode>(); 3917 new (N) UnarySDNode(Opcode, DL, VTList, Ops[0]); 3918 } else if (NumOps == 2) { 3919 N = NodeAllocator.Allocate<BinarySDNode>(); 3920 new (N) BinarySDNode(Opcode, DL, VTList, Ops[0], Ops[1]); 3921 } else if (NumOps == 3) { 3922 N = NodeAllocator.Allocate<TernarySDNode>(); 3923 new (N) TernarySDNode(Opcode, DL, VTList, Ops[0], Ops[1], Ops[2]); 3924 } else { 3925 N = NodeAllocator.Allocate<SDNode>(); 3926 new (N) SDNode(Opcode, DL, VTList, Ops, NumOps); 3927 } 3928 } 3929 AllNodes.push_back(N); 3930#ifndef NDEBUG 3931 VerifyNode(N); 3932#endif 3933 return SDValue(N, 0); 3934} 3935 3936SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList) { 3937 return getNode(Opcode, DL, VTList, 0, 0); 3938} 3939 3940SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, 3941 SDValue N1) { 3942 SDValue Ops[] = { N1 }; 3943 return getNode(Opcode, DL, VTList, Ops, 1); 3944} 3945 3946SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, 3947 SDValue N1, SDValue N2) { 3948 SDValue Ops[] = { N1, N2 }; 3949 return getNode(Opcode, DL, VTList, Ops, 2); 3950} 3951 3952SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, 3953 SDValue N1, SDValue N2, SDValue N3) { 3954 SDValue Ops[] = { N1, N2, N3 }; 3955 return getNode(Opcode, DL, VTList, Ops, 3); 3956} 3957 3958SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, 3959 SDValue N1, SDValue N2, SDValue N3, 3960 SDValue N4) { 3961 SDValue Ops[] = { N1, N2, N3, N4 }; 3962 return getNode(Opcode, DL, VTList, Ops, 4); 3963} 3964 3965SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, 3966 SDValue N1, SDValue N2, SDValue N3, 3967 SDValue N4, SDValue N5) { 3968 SDValue Ops[] = { N1, N2, N3, N4, N5 }; 3969 return getNode(Opcode, DL, VTList, Ops, 5); 3970} 3971 3972SDVTList SelectionDAG::getVTList(MVT VT) { 3973 return makeVTList(SDNode::getValueTypeList(VT), 1); 3974} 3975 3976SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2) { 3977 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 3978 E = VTList.rend(); I != E; ++I) 3979 if (I->NumVTs == 2 && I->VTs[0] == VT1 && I->VTs[1] == VT2) 3980 return *I; 3981 3982 MVT *Array = Allocator.Allocate<MVT>(2); 3983 Array[0] = VT1; 3984 Array[1] = VT2; 3985 SDVTList Result = makeVTList(Array, 2); 3986 VTList.push_back(Result); 3987 return Result; 3988} 3989 3990SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2, MVT VT3) { 3991 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 3992 E = VTList.rend(); I != E; ++I) 3993 if (I->NumVTs == 3 && I->VTs[0] == VT1 && I->VTs[1] == VT2 && 3994 I->VTs[2] == VT3) 3995 return *I; 3996 3997 MVT *Array = Allocator.Allocate<MVT>(3); 3998 Array[0] = VT1; 3999 Array[1] = VT2; 4000 Array[2] = VT3; 4001 SDVTList Result = makeVTList(Array, 3); 4002 VTList.push_back(Result); 4003 return Result; 4004} 4005 4006SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2, MVT VT3, MVT VT4) { 4007 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 4008 E = VTList.rend(); I != E; ++I) 4009 if (I->NumVTs == 4 && I->VTs[0] == VT1 && I->VTs[1] == VT2 && 4010 I->VTs[2] == VT3 && I->VTs[3] == VT4) 4011 return *I; 4012 4013 MVT *Array = Allocator.Allocate<MVT>(3); 4014 Array[0] = VT1; 4015 Array[1] = VT2; 4016 Array[2] = VT3; 4017 Array[3] = VT4; 4018 SDVTList Result = makeVTList(Array, 4); 4019 VTList.push_back(Result); 4020 return Result; 4021} 4022 4023SDVTList SelectionDAG::getVTList(const MVT *VTs, unsigned NumVTs) { 4024 switch (NumVTs) { 4025 case 0: assert(0 && "Cannot have nodes without results!"); 4026 case 1: return getVTList(VTs[0]); 4027 case 2: return getVTList(VTs[0], VTs[1]); 4028 case 3: return getVTList(VTs[0], VTs[1], VTs[2]); 4029 default: break; 4030 } 4031 4032 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 4033 E = VTList.rend(); I != E; ++I) { 4034 if (I->NumVTs != NumVTs || VTs[0] != I->VTs[0] || VTs[1] != I->VTs[1]) 4035 continue; 4036 4037 bool NoMatch = false; 4038 for (unsigned i = 2; i != NumVTs; ++i) 4039 if (VTs[i] != I->VTs[i]) { 4040 NoMatch = true; 4041 break; 4042 } 4043 if (!NoMatch) 4044 return *I; 4045 } 4046 4047 MVT *Array = Allocator.Allocate<MVT>(NumVTs); 4048 std::copy(VTs, VTs+NumVTs, Array); 4049 SDVTList Result = makeVTList(Array, NumVTs); 4050 VTList.push_back(Result); 4051 return Result; 4052} 4053 4054 4055/// UpdateNodeOperands - *Mutate* the specified node in-place to have the 4056/// specified operands. If the resultant node already exists in the DAG, 4057/// this does not modify the specified node, instead it returns the node that 4058/// already exists. If the resultant node does not exist in the DAG, the 4059/// input node is returned. As a degenerate case, if you specify the same 4060/// input operands as the node already has, the input node is returned. 4061SDValue SelectionDAG::UpdateNodeOperands(SDValue InN, SDValue Op) { 4062 SDNode *N = InN.getNode(); 4063 assert(N->getNumOperands() == 1 && "Update with wrong number of operands"); 4064 4065 // Check to see if there is no change. 4066 if (Op == N->getOperand(0)) return InN; 4067 4068 // See if the modified node already exists. 4069 void *InsertPos = 0; 4070 if (SDNode *Existing = FindModifiedNodeSlot(N, Op, InsertPos)) 4071 return SDValue(Existing, InN.getResNo()); 4072 4073 // Nope it doesn't. Remove the node from its current place in the maps. 4074 if (InsertPos) 4075 if (!RemoveNodeFromCSEMaps(N)) 4076 InsertPos = 0; 4077 4078 // Now we update the operands. 4079 N->OperandList[0].set(Op); 4080 4081 // If this gets put into a CSE map, add it. 4082 if (InsertPos) CSEMap.InsertNode(N, InsertPos); 4083 return InN; 4084} 4085 4086SDValue SelectionDAG:: 4087UpdateNodeOperands(SDValue InN, SDValue Op1, SDValue Op2) { 4088 SDNode *N = InN.getNode(); 4089 assert(N->getNumOperands() == 2 && "Update with wrong number of operands"); 4090 4091 // Check to see if there is no change. 4092 if (Op1 == N->getOperand(0) && Op2 == N->getOperand(1)) 4093 return InN; // No operands changed, just return the input node. 4094 4095 // See if the modified node already exists. 4096 void *InsertPos = 0; 4097 if (SDNode *Existing = FindModifiedNodeSlot(N, Op1, Op2, InsertPos)) 4098 return SDValue(Existing, InN.getResNo()); 4099 4100 // Nope it doesn't. Remove the node from its current place in the maps. 4101 if (InsertPos) 4102 if (!RemoveNodeFromCSEMaps(N)) 4103 InsertPos = 0; 4104 4105 // Now we update the operands. 4106 if (N->OperandList[0] != Op1) 4107 N->OperandList[0].set(Op1); 4108 if (N->OperandList[1] != Op2) 4109 N->OperandList[1].set(Op2); 4110 4111 // If this gets put into a CSE map, add it. 4112 if (InsertPos) CSEMap.InsertNode(N, InsertPos); 4113 return InN; 4114} 4115 4116SDValue SelectionDAG:: 4117UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, SDValue Op3) { 4118 SDValue Ops[] = { Op1, Op2, Op3 }; 4119 return UpdateNodeOperands(N, Ops, 3); 4120} 4121 4122SDValue SelectionDAG:: 4123UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, 4124 SDValue Op3, SDValue Op4) { 4125 SDValue Ops[] = { Op1, Op2, Op3, Op4 }; 4126 return UpdateNodeOperands(N, Ops, 4); 4127} 4128 4129SDValue SelectionDAG:: 4130UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, 4131 SDValue Op3, SDValue Op4, SDValue Op5) { 4132 SDValue Ops[] = { Op1, Op2, Op3, Op4, Op5 }; 4133 return UpdateNodeOperands(N, Ops, 5); 4134} 4135 4136SDValue SelectionDAG:: 4137UpdateNodeOperands(SDValue InN, const SDValue *Ops, unsigned NumOps) { 4138 SDNode *N = InN.getNode(); 4139 assert(N->getNumOperands() == NumOps && 4140 "Update with wrong number of operands"); 4141 4142 // Check to see if there is no change. 4143 bool AnyChange = false; 4144 for (unsigned i = 0; i != NumOps; ++i) { 4145 if (Ops[i] != N->getOperand(i)) { 4146 AnyChange = true; 4147 break; 4148 } 4149 } 4150 4151 // No operands changed, just return the input node. 4152 if (!AnyChange) return InN; 4153 4154 // See if the modified node already exists. 4155 void *InsertPos = 0; 4156 if (SDNode *Existing = FindModifiedNodeSlot(N, Ops, NumOps, InsertPos)) 4157 return SDValue(Existing, InN.getResNo()); 4158 4159 // Nope it doesn't. Remove the node from its current place in the maps. 4160 if (InsertPos) 4161 if (!RemoveNodeFromCSEMaps(N)) 4162 InsertPos = 0; 4163 4164 // Now we update the operands. 4165 for (unsigned i = 0; i != NumOps; ++i) 4166 if (N->OperandList[i] != Ops[i]) 4167 N->OperandList[i].set(Ops[i]); 4168 4169 // If this gets put into a CSE map, add it. 4170 if (InsertPos) CSEMap.InsertNode(N, InsertPos); 4171 return InN; 4172} 4173 4174/// DropOperands - Release the operands and set this node to have 4175/// zero operands. 4176void SDNode::DropOperands() { 4177 // Unlike the code in MorphNodeTo that does this, we don't need to 4178 // watch for dead nodes here. 4179 for (op_iterator I = op_begin(), E = op_end(); I != E; ) { 4180 SDUse &Use = *I++; 4181 Use.set(SDValue()); 4182 } 4183} 4184 4185/// SelectNodeTo - These are wrappers around MorphNodeTo that accept a 4186/// machine opcode. 4187/// 4188SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4189 MVT VT) { 4190 SDVTList VTs = getVTList(VT); 4191 return SelectNodeTo(N, MachineOpc, VTs, 0, 0); 4192} 4193 4194SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4195 MVT VT, SDValue Op1) { 4196 SDVTList VTs = getVTList(VT); 4197 SDValue Ops[] = { Op1 }; 4198 return SelectNodeTo(N, MachineOpc, VTs, Ops, 1); 4199} 4200 4201SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4202 MVT VT, SDValue Op1, 4203 SDValue Op2) { 4204 SDVTList VTs = getVTList(VT); 4205 SDValue Ops[] = { Op1, Op2 }; 4206 return SelectNodeTo(N, MachineOpc, VTs, Ops, 2); 4207} 4208 4209SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4210 MVT VT, SDValue Op1, 4211 SDValue Op2, SDValue Op3) { 4212 SDVTList VTs = getVTList(VT); 4213 SDValue Ops[] = { Op1, Op2, Op3 }; 4214 return SelectNodeTo(N, MachineOpc, VTs, Ops, 3); 4215} 4216 4217SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4218 MVT VT, const SDValue *Ops, 4219 unsigned NumOps) { 4220 SDVTList VTs = getVTList(VT); 4221 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 4222} 4223 4224SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4225 MVT VT1, MVT VT2, const SDValue *Ops, 4226 unsigned NumOps) { 4227 SDVTList VTs = getVTList(VT1, VT2); 4228 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 4229} 4230 4231SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4232 MVT VT1, MVT VT2) { 4233 SDVTList VTs = getVTList(VT1, VT2); 4234 return SelectNodeTo(N, MachineOpc, VTs, (SDValue *)0, 0); 4235} 4236 4237SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4238 MVT VT1, MVT VT2, MVT VT3, 4239 const SDValue *Ops, unsigned NumOps) { 4240 SDVTList VTs = getVTList(VT1, VT2, VT3); 4241 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 4242} 4243 4244SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4245 MVT VT1, MVT VT2, MVT VT3, MVT VT4, 4246 const SDValue *Ops, unsigned NumOps) { 4247 SDVTList VTs = getVTList(VT1, VT2, VT3, VT4); 4248 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 4249} 4250 4251SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4252 MVT VT1, MVT VT2, 4253 SDValue Op1) { 4254 SDVTList VTs = getVTList(VT1, VT2); 4255 SDValue Ops[] = { Op1 }; 4256 return SelectNodeTo(N, MachineOpc, VTs, Ops, 1); 4257} 4258 4259SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4260 MVT VT1, MVT VT2, 4261 SDValue Op1, SDValue Op2) { 4262 SDVTList VTs = getVTList(VT1, VT2); 4263 SDValue Ops[] = { Op1, Op2 }; 4264 return SelectNodeTo(N, MachineOpc, VTs, Ops, 2); 4265} 4266 4267SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4268 MVT VT1, MVT VT2, 4269 SDValue Op1, SDValue Op2, 4270 SDValue Op3) { 4271 SDVTList VTs = getVTList(VT1, VT2); 4272 SDValue Ops[] = { Op1, Op2, Op3 }; 4273 return SelectNodeTo(N, MachineOpc, VTs, Ops, 3); 4274} 4275 4276SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4277 MVT VT1, MVT VT2, MVT VT3, 4278 SDValue Op1, SDValue Op2, 4279 SDValue Op3) { 4280 SDVTList VTs = getVTList(VT1, VT2, VT3); 4281 SDValue Ops[] = { Op1, Op2, Op3 }; 4282 return SelectNodeTo(N, MachineOpc, VTs, Ops, 3); 4283} 4284 4285SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4286 SDVTList VTs, const SDValue *Ops, 4287 unsigned NumOps) { 4288 return MorphNodeTo(N, ~MachineOpc, VTs, Ops, NumOps); 4289} 4290 4291SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4292 MVT VT) { 4293 SDVTList VTs = getVTList(VT); 4294 return MorphNodeTo(N, Opc, VTs, 0, 0); 4295} 4296 4297SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4298 MVT VT, SDValue Op1) { 4299 SDVTList VTs = getVTList(VT); 4300 SDValue Ops[] = { Op1 }; 4301 return MorphNodeTo(N, Opc, VTs, Ops, 1); 4302} 4303 4304SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4305 MVT VT, SDValue Op1, 4306 SDValue Op2) { 4307 SDVTList VTs = getVTList(VT); 4308 SDValue Ops[] = { Op1, Op2 }; 4309 return MorphNodeTo(N, Opc, VTs, Ops, 2); 4310} 4311 4312SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4313 MVT VT, SDValue Op1, 4314 SDValue Op2, SDValue Op3) { 4315 SDVTList VTs = getVTList(VT); 4316 SDValue Ops[] = { Op1, Op2, Op3 }; 4317 return MorphNodeTo(N, Opc, VTs, Ops, 3); 4318} 4319 4320SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4321 MVT VT, const SDValue *Ops, 4322 unsigned NumOps) { 4323 SDVTList VTs = getVTList(VT); 4324 return MorphNodeTo(N, Opc, VTs, Ops, NumOps); 4325} 4326 4327SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4328 MVT VT1, MVT VT2, const SDValue *Ops, 4329 unsigned NumOps) { 4330 SDVTList VTs = getVTList(VT1, VT2); 4331 return MorphNodeTo(N, Opc, VTs, Ops, NumOps); 4332} 4333 4334SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4335 MVT VT1, MVT VT2) { 4336 SDVTList VTs = getVTList(VT1, VT2); 4337 return MorphNodeTo(N, Opc, VTs, (SDValue *)0, 0); 4338} 4339 4340SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4341 MVT VT1, MVT VT2, MVT VT3, 4342 const SDValue *Ops, unsigned NumOps) { 4343 SDVTList VTs = getVTList(VT1, VT2, VT3); 4344 return MorphNodeTo(N, Opc, VTs, Ops, NumOps); 4345} 4346 4347SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4348 MVT VT1, MVT VT2, 4349 SDValue Op1) { 4350 SDVTList VTs = getVTList(VT1, VT2); 4351 SDValue Ops[] = { Op1 }; 4352 return MorphNodeTo(N, Opc, VTs, Ops, 1); 4353} 4354 4355SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4356 MVT VT1, MVT VT2, 4357 SDValue Op1, SDValue Op2) { 4358 SDVTList VTs = getVTList(VT1, VT2); 4359 SDValue Ops[] = { Op1, Op2 }; 4360 return MorphNodeTo(N, Opc, VTs, Ops, 2); 4361} 4362 4363SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4364 MVT VT1, MVT VT2, 4365 SDValue Op1, SDValue Op2, 4366 SDValue Op3) { 4367 SDVTList VTs = getVTList(VT1, VT2); 4368 SDValue Ops[] = { Op1, Op2, Op3 }; 4369 return MorphNodeTo(N, Opc, VTs, Ops, 3); 4370} 4371 4372/// MorphNodeTo - These *mutate* the specified node to have the specified 4373/// return type, opcode, and operands. 4374/// 4375/// Note that MorphNodeTo returns the resultant node. If there is already a 4376/// node of the specified opcode and operands, it returns that node instead of 4377/// the current one. Note that the DebugLoc need not be the same. 4378/// 4379/// Using MorphNodeTo is faster than creating a new node and swapping it in 4380/// with ReplaceAllUsesWith both because it often avoids allocating a new 4381/// node, and because it doesn't require CSE recalculation for any of 4382/// the node's users. 4383/// 4384SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4385 SDVTList VTs, const SDValue *Ops, 4386 unsigned NumOps) { 4387 // If an identical node already exists, use it. 4388 void *IP = 0; 4389 if (VTs.VTs[VTs.NumVTs-1] != MVT::Flag) { 4390 FoldingSetNodeID ID; 4391 AddNodeIDNode(ID, Opc, VTs, Ops, NumOps); 4392 if (SDNode *ON = CSEMap.FindNodeOrInsertPos(ID, IP)) 4393 return ON; 4394 } 4395 4396 if (!RemoveNodeFromCSEMaps(N)) 4397 IP = 0; 4398 4399 // Start the morphing. 4400 N->NodeType = Opc; 4401 N->ValueList = VTs.VTs; 4402 N->NumValues = VTs.NumVTs; 4403 4404 // Clear the operands list, updating used nodes to remove this from their 4405 // use list. Keep track of any operands that become dead as a result. 4406 SmallPtrSet<SDNode*, 16> DeadNodeSet; 4407 for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ) { 4408 SDUse &Use = *I++; 4409 SDNode *Used = Use.getNode(); 4410 Use.set(SDValue()); 4411 if (Used->use_empty()) 4412 DeadNodeSet.insert(Used); 4413 } 4414 4415 // If NumOps is larger than the # of operands we currently have, reallocate 4416 // the operand list. 4417 if (NumOps > N->NumOperands) { 4418 if (N->OperandsNeedDelete) 4419 delete[] N->OperandList; 4420 4421 if (N->isMachineOpcode()) { 4422 // We're creating a final node that will live unmorphed for the 4423 // remainder of the current SelectionDAG iteration, so we can allocate 4424 // the operands directly out of a pool with no recycling metadata. 4425 N->OperandList = OperandAllocator.Allocate<SDUse>(NumOps); 4426 N->OperandsNeedDelete = false; 4427 } else { 4428 N->OperandList = new SDUse[NumOps]; 4429 N->OperandsNeedDelete = true; 4430 } 4431 } 4432 4433 // Assign the new operands. 4434 N->NumOperands = NumOps; 4435 for (unsigned i = 0, e = NumOps; i != e; ++i) { 4436 N->OperandList[i].setUser(N); 4437 N->OperandList[i].setInitial(Ops[i]); 4438 } 4439 4440 // Delete any nodes that are still dead after adding the uses for the 4441 // new operands. 4442 SmallVector<SDNode *, 16> DeadNodes; 4443 for (SmallPtrSet<SDNode *, 16>::iterator I = DeadNodeSet.begin(), 4444 E = DeadNodeSet.end(); I != E; ++I) 4445 if ((*I)->use_empty()) 4446 DeadNodes.push_back(*I); 4447 RemoveDeadNodes(DeadNodes); 4448 4449 if (IP) 4450 CSEMap.InsertNode(N, IP); // Memoize the new node. 4451 return N; 4452} 4453 4454 4455/// getTargetNode - These are used for target selectors to create a new node 4456/// with specified return type(s), target opcode, and operands. 4457/// 4458/// Note that getTargetNode returns the resultant node. If there is already a 4459/// node of the specified opcode and operands, it returns that node instead of 4460/// the current one. 4461SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT) { 4462 return getNode(~Opcode, dl, VT).getNode(); 4463} 4464 4465SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, 4466 SDValue Op1) { 4467 return getNode(~Opcode, dl, VT, Op1).getNode(); 4468} 4469 4470SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, 4471 SDValue Op1, SDValue Op2) { 4472 return getNode(~Opcode, dl, VT, Op1, Op2).getNode(); 4473} 4474 4475SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, 4476 SDValue Op1, SDValue Op2, 4477 SDValue Op3) { 4478 return getNode(~Opcode, dl, VT, Op1, Op2, Op3).getNode(); 4479} 4480 4481SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, 4482 const SDValue *Ops, unsigned NumOps) { 4483 return getNode(~Opcode, dl, VT, Ops, NumOps).getNode(); 4484} 4485 4486SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, 4487 MVT VT1, MVT VT2) { 4488 SDVTList VTs = getVTList(VT1, VT2); 4489 SDValue Op; 4490 return getNode(~Opcode, dl, VTs, &Op, 0).getNode(); 4491} 4492 4493SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, 4494 MVT VT2, SDValue Op1) { 4495 SDVTList VTs = getVTList(VT1, VT2); 4496 return getNode(~Opcode, dl, VTs, &Op1, 1).getNode(); 4497} 4498 4499SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, 4500 MVT VT2, SDValue Op1, 4501 SDValue Op2) { 4502 SDVTList VTs = getVTList(VT1, VT2); 4503 SDValue Ops[] = { Op1, Op2 }; 4504 return getNode(~Opcode, dl, VTs, Ops, 2).getNode(); 4505} 4506 4507SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, 4508 MVT VT2, SDValue Op1, 4509 SDValue Op2, SDValue Op3) { 4510 SDVTList VTs = getVTList(VT1, VT2); 4511 SDValue Ops[] = { Op1, Op2, Op3 }; 4512 return getNode(~Opcode, dl, VTs, Ops, 3).getNode(); 4513} 4514 4515SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, 4516 MVT VT1, MVT VT2, 4517 const SDValue *Ops, unsigned NumOps) { 4518 SDVTList VTs = getVTList(VT1, VT2); 4519 return getNode(~Opcode, dl, VTs, Ops, NumOps).getNode(); 4520} 4521 4522SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, 4523 MVT VT1, MVT VT2, MVT VT3, 4524 SDValue Op1, SDValue Op2) { 4525 SDVTList VTs = getVTList(VT1, VT2, VT3); 4526 SDValue Ops[] = { Op1, Op2 }; 4527 return getNode(~Opcode, dl, VTs, Ops, 2).getNode(); 4528} 4529 4530SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, 4531 MVT VT1, MVT VT2, MVT VT3, 4532 SDValue Op1, SDValue Op2, 4533 SDValue Op3) { 4534 SDVTList VTs = getVTList(VT1, VT2, VT3); 4535 SDValue Ops[] = { Op1, Op2, Op3 }; 4536 return getNode(~Opcode, dl, VTs, Ops, 3).getNode(); 4537} 4538 4539SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, 4540 MVT VT1, MVT VT2, MVT VT3, 4541 const SDValue *Ops, unsigned NumOps) { 4542 SDVTList VTs = getVTList(VT1, VT2, VT3); 4543 return getNode(~Opcode, dl, VTs, Ops, NumOps).getNode(); 4544} 4545 4546SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, 4547 MVT VT2, MVT VT3, MVT VT4, 4548 const SDValue *Ops, unsigned NumOps) { 4549 SDVTList VTs = getVTList(VT1, VT2, VT3, VT4); 4550 return getNode(~Opcode, dl, VTs, Ops, NumOps).getNode(); 4551} 4552 4553SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, 4554 const std::vector<MVT> &ResultTys, 4555 const SDValue *Ops, unsigned NumOps) { 4556 return getNode(~Opcode, dl, ResultTys, Ops, NumOps).getNode(); 4557} 4558 4559/// getNodeIfExists - Get the specified node if it's already available, or 4560/// else return NULL. 4561SDNode *SelectionDAG::getNodeIfExists(unsigned Opcode, SDVTList VTList, 4562 const SDValue *Ops, unsigned NumOps) { 4563 if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) { 4564 FoldingSetNodeID ID; 4565 AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps); 4566 void *IP = 0; 4567 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 4568 return E; 4569 } 4570 return NULL; 4571} 4572 4573/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. 4574/// This can cause recursive merging of nodes in the DAG. 4575/// 4576/// This version assumes From has a single result value. 4577/// 4578void SelectionDAG::ReplaceAllUsesWith(SDValue FromN, SDValue To, 4579 DAGUpdateListener *UpdateListener) { 4580 SDNode *From = FromN.getNode(); 4581 assert(From->getNumValues() == 1 && FromN.getResNo() == 0 && 4582 "Cannot replace with this method!"); 4583 assert(From != To.getNode() && "Cannot replace uses of with self"); 4584 4585 // Iterate over all the existing uses of From. New uses will be added 4586 // to the beginning of the use list, which we avoid visiting. 4587 // This specifically avoids visiting uses of From that arise while the 4588 // replacement is happening, because any such uses would be the result 4589 // of CSE: If an existing node looks like From after one of its operands 4590 // is replaced by To, we don't want to replace of all its users with To 4591 // too. See PR3018 for more info. 4592 SDNode::use_iterator UI = From->use_begin(), UE = From->use_end(); 4593 while (UI != UE) { 4594 SDNode *User = *UI; 4595 4596 // This node is about to morph, remove its old self from the CSE maps. 4597 RemoveNodeFromCSEMaps(User); 4598 4599 // A user can appear in a use list multiple times, and when this 4600 // happens the uses are usually next to each other in the list. 4601 // To help reduce the number of CSE recomputations, process all 4602 // the uses of this user that we can find this way. 4603 do { 4604 SDUse &Use = UI.getUse(); 4605 ++UI; 4606 Use.set(To); 4607 } while (UI != UE && *UI == User); 4608 4609 // Now that we have modified User, add it back to the CSE maps. If it 4610 // already exists there, recursively merge the results together. 4611 AddModifiedNodeToCSEMaps(User, UpdateListener); 4612 } 4613} 4614 4615/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. 4616/// This can cause recursive merging of nodes in the DAG. 4617/// 4618/// This version assumes that for each value of From, there is a 4619/// corresponding value in To in the same position with the same type. 4620/// 4621void SelectionDAG::ReplaceAllUsesWith(SDNode *From, SDNode *To, 4622 DAGUpdateListener *UpdateListener) { 4623#ifndef NDEBUG 4624 for (unsigned i = 0, e = From->getNumValues(); i != e; ++i) 4625 assert((!From->hasAnyUseOfValue(i) || 4626 From->getValueType(i) == To->getValueType(i)) && 4627 "Cannot use this version of ReplaceAllUsesWith!"); 4628#endif 4629 4630 // Handle the trivial case. 4631 if (From == To) 4632 return; 4633 4634 // Iterate over just the existing users of From. See the comments in 4635 // the ReplaceAllUsesWith above. 4636 SDNode::use_iterator UI = From->use_begin(), UE = From->use_end(); 4637 while (UI != UE) { 4638 SDNode *User = *UI; 4639 4640 // This node is about to morph, remove its old self from the CSE maps. 4641 RemoveNodeFromCSEMaps(User); 4642 4643 // A user can appear in a use list multiple times, and when this 4644 // happens the uses are usually next to each other in the list. 4645 // To help reduce the number of CSE recomputations, process all 4646 // the uses of this user that we can find this way. 4647 do { 4648 SDUse &Use = UI.getUse(); 4649 ++UI; 4650 Use.setNode(To); 4651 } while (UI != UE && *UI == User); 4652 4653 // Now that we have modified User, add it back to the CSE maps. If it 4654 // already exists there, recursively merge the results together. 4655 AddModifiedNodeToCSEMaps(User, UpdateListener); 4656 } 4657} 4658 4659/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. 4660/// This can cause recursive merging of nodes in the DAG. 4661/// 4662/// This version can replace From with any result values. To must match the 4663/// number and types of values returned by From. 4664void SelectionDAG::ReplaceAllUsesWith(SDNode *From, 4665 const SDValue *To, 4666 DAGUpdateListener *UpdateListener) { 4667 if (From->getNumValues() == 1) // Handle the simple case efficiently. 4668 return ReplaceAllUsesWith(SDValue(From, 0), To[0], UpdateListener); 4669 4670 // Iterate over just the existing users of From. See the comments in 4671 // the ReplaceAllUsesWith above. 4672 SDNode::use_iterator UI = From->use_begin(), UE = From->use_end(); 4673 while (UI != UE) { 4674 SDNode *User = *UI; 4675 4676 // This node is about to morph, remove its old self from the CSE maps. 4677 RemoveNodeFromCSEMaps(User); 4678 4679 // A user can appear in a use list multiple times, and when this 4680 // happens the uses are usually next to each other in the list. 4681 // To help reduce the number of CSE recomputations, process all 4682 // the uses of this user that we can find this way. 4683 do { 4684 SDUse &Use = UI.getUse(); 4685 const SDValue &ToOp = To[Use.getResNo()]; 4686 ++UI; 4687 Use.set(ToOp); 4688 } while (UI != UE && *UI == User); 4689 4690 // Now that we have modified User, add it back to the CSE maps. If it 4691 // already exists there, recursively merge the results together. 4692 AddModifiedNodeToCSEMaps(User, UpdateListener); 4693 } 4694} 4695 4696/// ReplaceAllUsesOfValueWith - Replace any uses of From with To, leaving 4697/// uses of other values produced by From.getNode() alone. The Deleted 4698/// vector is handled the same way as for ReplaceAllUsesWith. 4699void SelectionDAG::ReplaceAllUsesOfValueWith(SDValue From, SDValue To, 4700 DAGUpdateListener *UpdateListener){ 4701 // Handle the really simple, really trivial case efficiently. 4702 if (From == To) return; 4703 4704 // Handle the simple, trivial, case efficiently. 4705 if (From.getNode()->getNumValues() == 1) { 4706 ReplaceAllUsesWith(From, To, UpdateListener); 4707 return; 4708 } 4709 4710 // Iterate over just the existing users of From. See the comments in 4711 // the ReplaceAllUsesWith above. 4712 SDNode::use_iterator UI = From.getNode()->use_begin(), 4713 UE = From.getNode()->use_end(); 4714 while (UI != UE) { 4715 SDNode *User = *UI; 4716 bool UserRemovedFromCSEMaps = false; 4717 4718 // A user can appear in a use list multiple times, and when this 4719 // happens the uses are usually next to each other in the list. 4720 // To help reduce the number of CSE recomputations, process all 4721 // the uses of this user that we can find this way. 4722 do { 4723 SDUse &Use = UI.getUse(); 4724 4725 // Skip uses of different values from the same node. 4726 if (Use.getResNo() != From.getResNo()) { 4727 ++UI; 4728 continue; 4729 } 4730 4731 // If this node hasn't been modified yet, it's still in the CSE maps, 4732 // so remove its old self from the CSE maps. 4733 if (!UserRemovedFromCSEMaps) { 4734 RemoveNodeFromCSEMaps(User); 4735 UserRemovedFromCSEMaps = true; 4736 } 4737 4738 ++UI; 4739 Use.set(To); 4740 } while (UI != UE && *UI == User); 4741 4742 // We are iterating over all uses of the From node, so if a use 4743 // doesn't use the specific value, no changes are made. 4744 if (!UserRemovedFromCSEMaps) 4745 continue; 4746 4747 // Now that we have modified User, add it back to the CSE maps. If it 4748 // already exists there, recursively merge the results together. 4749 AddModifiedNodeToCSEMaps(User, UpdateListener); 4750 } 4751} 4752 4753namespace { 4754 /// UseMemo - This class is used by SelectionDAG::ReplaceAllUsesOfValuesWith 4755 /// to record information about a use. 4756 struct UseMemo { 4757 SDNode *User; 4758 unsigned Index; 4759 SDUse *Use; 4760 }; 4761 4762 /// operator< - Sort Memos by User. 4763 bool operator<(const UseMemo &L, const UseMemo &R) { 4764 return (intptr_t)L.User < (intptr_t)R.User; 4765 } 4766} 4767 4768/// ReplaceAllUsesOfValuesWith - Replace any uses of From with To, leaving 4769/// uses of other values produced by From.getNode() alone. The same value 4770/// may appear in both the From and To list. The Deleted vector is 4771/// handled the same way as for ReplaceAllUsesWith. 4772void SelectionDAG::ReplaceAllUsesOfValuesWith(const SDValue *From, 4773 const SDValue *To, 4774 unsigned Num, 4775 DAGUpdateListener *UpdateListener){ 4776 // Handle the simple, trivial case efficiently. 4777 if (Num == 1) 4778 return ReplaceAllUsesOfValueWith(*From, *To, UpdateListener); 4779 4780 // Read up all the uses and make records of them. This helps 4781 // processing new uses that are introduced during the 4782 // replacement process. 4783 SmallVector<UseMemo, 4> Uses; 4784 for (unsigned i = 0; i != Num; ++i) { 4785 unsigned FromResNo = From[i].getResNo(); 4786 SDNode *FromNode = From[i].getNode(); 4787 for (SDNode::use_iterator UI = FromNode->use_begin(), 4788 E = FromNode->use_end(); UI != E; ++UI) { 4789 SDUse &Use = UI.getUse(); 4790 if (Use.getResNo() == FromResNo) { 4791 UseMemo Memo = { *UI, i, &Use }; 4792 Uses.push_back(Memo); 4793 } 4794 } 4795 } 4796 4797 // Sort the uses, so that all the uses from a given User are together. 4798 std::sort(Uses.begin(), Uses.end()); 4799 4800 for (unsigned UseIndex = 0, UseIndexEnd = Uses.size(); 4801 UseIndex != UseIndexEnd; ) { 4802 // We know that this user uses some value of From. If it is the right 4803 // value, update it. 4804 SDNode *User = Uses[UseIndex].User; 4805 4806 // This node is about to morph, remove its old self from the CSE maps. 4807 RemoveNodeFromCSEMaps(User); 4808 4809 // The Uses array is sorted, so all the uses for a given User 4810 // are next to each other in the list. 4811 // To help reduce the number of CSE recomputations, process all 4812 // the uses of this user that we can find this way. 4813 do { 4814 unsigned i = Uses[UseIndex].Index; 4815 SDUse &Use = *Uses[UseIndex].Use; 4816 ++UseIndex; 4817 4818 Use.set(To[i]); 4819 } while (UseIndex != UseIndexEnd && Uses[UseIndex].User == User); 4820 4821 // Now that we have modified User, add it back to the CSE maps. If it 4822 // already exists there, recursively merge the results together. 4823 AddModifiedNodeToCSEMaps(User, UpdateListener); 4824 } 4825} 4826 4827/// AssignTopologicalOrder - Assign a unique node id for each node in the DAG 4828/// based on their topological order. It returns the maximum id and a vector 4829/// of the SDNodes* in assigned order by reference. 4830unsigned SelectionDAG::AssignTopologicalOrder() { 4831 4832 unsigned DAGSize = 0; 4833 4834 // SortedPos tracks the progress of the algorithm. Nodes before it are 4835 // sorted, nodes after it are unsorted. When the algorithm completes 4836 // it is at the end of the list. 4837 allnodes_iterator SortedPos = allnodes_begin(); 4838 4839 // Visit all the nodes. Move nodes with no operands to the front of 4840 // the list immediately. Annotate nodes that do have operands with their 4841 // operand count. Before we do this, the Node Id fields of the nodes 4842 // may contain arbitrary values. After, the Node Id fields for nodes 4843 // before SortedPos will contain the topological sort index, and the 4844 // Node Id fields for nodes At SortedPos and after will contain the 4845 // count of outstanding operands. 4846 for (allnodes_iterator I = allnodes_begin(),E = allnodes_end(); I != E; ) { 4847 SDNode *N = I++; 4848 unsigned Degree = N->getNumOperands(); 4849 if (Degree == 0) { 4850 // A node with no uses, add it to the result array immediately. 4851 N->setNodeId(DAGSize++); 4852 allnodes_iterator Q = N; 4853 if (Q != SortedPos) 4854 SortedPos = AllNodes.insert(SortedPos, AllNodes.remove(Q)); 4855 ++SortedPos; 4856 } else { 4857 // Temporarily use the Node Id as scratch space for the degree count. 4858 N->setNodeId(Degree); 4859 } 4860 } 4861 4862 // Visit all the nodes. As we iterate, moves nodes into sorted order, 4863 // such that by the time the end is reached all nodes will be sorted. 4864 for (allnodes_iterator I = allnodes_begin(),E = allnodes_end(); I != E; ++I) { 4865 SDNode *N = I; 4866 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 4867 UI != UE; ++UI) { 4868 SDNode *P = *UI; 4869 unsigned Degree = P->getNodeId(); 4870 --Degree; 4871 if (Degree == 0) { 4872 // All of P's operands are sorted, so P may sorted now. 4873 P->setNodeId(DAGSize++); 4874 if (P != SortedPos) 4875 SortedPos = AllNodes.insert(SortedPos, AllNodes.remove(P)); 4876 ++SortedPos; 4877 } else { 4878 // Update P's outstanding operand count. 4879 P->setNodeId(Degree); 4880 } 4881 } 4882 } 4883 4884 assert(SortedPos == AllNodes.end() && 4885 "Topological sort incomplete!"); 4886 assert(AllNodes.front().getOpcode() == ISD::EntryToken && 4887 "First node in topological sort is not the entry token!"); 4888 assert(AllNodes.front().getNodeId() == 0 && 4889 "First node in topological sort has non-zero id!"); 4890 assert(AllNodes.front().getNumOperands() == 0 && 4891 "First node in topological sort has operands!"); 4892 assert(AllNodes.back().getNodeId() == (int)DAGSize-1 && 4893 "Last node in topologic sort has unexpected id!"); 4894 assert(AllNodes.back().use_empty() && 4895 "Last node in topologic sort has users!"); 4896 assert(DAGSize == allnodes_size() && "Node count mismatch!"); 4897 return DAGSize; 4898} 4899 4900 4901 4902//===----------------------------------------------------------------------===// 4903// SDNode Class 4904//===----------------------------------------------------------------------===// 4905 4906HandleSDNode::~HandleSDNode() { 4907 DropOperands(); 4908} 4909 4910GlobalAddressSDNode::GlobalAddressSDNode(bool isTarget, const GlobalValue *GA, 4911 MVT VT, int64_t o) 4912 : SDNode(isa<GlobalVariable>(GA) && 4913 cast<GlobalVariable>(GA)->isThreadLocal() ? 4914 // Thread Local 4915 (isTarget ? ISD::TargetGlobalTLSAddress : ISD::GlobalTLSAddress) : 4916 // Non Thread Local 4917 (isTarget ? ISD::TargetGlobalAddress : ISD::GlobalAddress), 4918 DebugLoc::getUnknownLoc(), getSDVTList(VT)), Offset(o) { 4919 TheGlobal = const_cast<GlobalValue*>(GA); 4920} 4921 4922MemSDNode::MemSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, MVT memvt, 4923 const Value *srcValue, int SVO, 4924 unsigned alignment, bool vol) 4925 : SDNode(Opc, dl, VTs), MemoryVT(memvt), SrcValue(srcValue), SVOffset(SVO) { 4926 SubclassData = encodeMemSDNodeFlags(0, ISD::UNINDEXED, vol, alignment); 4927 assert(isPowerOf2_32(alignment) && "Alignment is not a power of 2!"); 4928 assert(getAlignment() == alignment && "Alignment representation error!"); 4929 assert(isVolatile() == vol && "Volatile representation error!"); 4930} 4931 4932MemSDNode::MemSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, 4933 const SDValue *Ops, 4934 unsigned NumOps, MVT memvt, const Value *srcValue, 4935 int SVO, unsigned alignment, bool vol) 4936 : SDNode(Opc, dl, VTs, Ops, NumOps), 4937 MemoryVT(memvt), SrcValue(srcValue), SVOffset(SVO) { 4938 SubclassData = encodeMemSDNodeFlags(0, ISD::UNINDEXED, vol, alignment); 4939 assert(isPowerOf2_32(alignment) && "Alignment is not a power of 2!"); 4940 assert(getAlignment() == alignment && "Alignment representation error!"); 4941 assert(isVolatile() == vol && "Volatile representation error!"); 4942} 4943 4944/// getMemOperand - Return a MachineMemOperand object describing the memory 4945/// reference performed by this memory reference. 4946MachineMemOperand MemSDNode::getMemOperand() const { 4947 int Flags = 0; 4948 if (isa<LoadSDNode>(this)) 4949 Flags = MachineMemOperand::MOLoad; 4950 else if (isa<StoreSDNode>(this)) 4951 Flags = MachineMemOperand::MOStore; 4952 else if (isa<AtomicSDNode>(this)) { 4953 Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore; 4954 } 4955 else { 4956 const MemIntrinsicSDNode* MemIntrinNode = dyn_cast<MemIntrinsicSDNode>(this); 4957 assert(MemIntrinNode && "Unknown MemSDNode opcode!"); 4958 if (MemIntrinNode->readMem()) Flags |= MachineMemOperand::MOLoad; 4959 if (MemIntrinNode->writeMem()) Flags |= MachineMemOperand::MOStore; 4960 } 4961 4962 int Size = (getMemoryVT().getSizeInBits() + 7) >> 3; 4963 if (isVolatile()) Flags |= MachineMemOperand::MOVolatile; 4964 4965 // Check if the memory reference references a frame index 4966 const FrameIndexSDNode *FI = 4967 dyn_cast<const FrameIndexSDNode>(getBasePtr().getNode()); 4968 if (!getSrcValue() && FI) 4969 return MachineMemOperand(PseudoSourceValue::getFixedStack(FI->getIndex()), 4970 Flags, 0, Size, getAlignment()); 4971 else 4972 return MachineMemOperand(getSrcValue(), Flags, getSrcValueOffset(), 4973 Size, getAlignment()); 4974} 4975 4976/// Profile - Gather unique data for the node. 4977/// 4978void SDNode::Profile(FoldingSetNodeID &ID) const { 4979 AddNodeIDNode(ID, this); 4980} 4981 4982static ManagedStatic<std::set<MVT, MVT::compareRawBits> > EVTs; 4983static MVT VTs[MVT::LAST_VALUETYPE]; 4984static ManagedStatic<sys::SmartMutex<true> > VTMutex; 4985 4986/// getValueTypeList - Return a pointer to the specified value type. 4987/// 4988const MVT *SDNode::getValueTypeList(MVT VT) { 4989 sys::SmartScopedLock<true> Lock(&*VTMutex); 4990 if (VT.isExtended()) { 4991 return &(*EVTs->insert(VT).first); 4992 } else { 4993 VTs[VT.getSimpleVT()] = VT; 4994 return &VTs[VT.getSimpleVT()]; 4995 } 4996} 4997 4998/// hasNUsesOfValue - Return true if there are exactly NUSES uses of the 4999/// indicated value. This method ignores uses of other values defined by this 5000/// operation. 5001bool SDNode::hasNUsesOfValue(unsigned NUses, unsigned Value) const { 5002 assert(Value < getNumValues() && "Bad value!"); 5003 5004 // TODO: Only iterate over uses of a given value of the node 5005 for (SDNode::use_iterator UI = use_begin(), E = use_end(); UI != E; ++UI) { 5006 if (UI.getUse().getResNo() == Value) { 5007 if (NUses == 0) 5008 return false; 5009 --NUses; 5010 } 5011 } 5012 5013 // Found exactly the right number of uses? 5014 return NUses == 0; 5015} 5016 5017 5018/// hasAnyUseOfValue - Return true if there are any use of the indicated 5019/// value. This method ignores uses of other values defined by this operation. 5020bool SDNode::hasAnyUseOfValue(unsigned Value) const { 5021 assert(Value < getNumValues() && "Bad value!"); 5022 5023 for (SDNode::use_iterator UI = use_begin(), E = use_end(); UI != E; ++UI) 5024 if (UI.getUse().getResNo() == Value) 5025 return true; 5026 5027 return false; 5028} 5029 5030 5031/// isOnlyUserOf - Return true if this node is the only use of N. 5032/// 5033bool SDNode::isOnlyUserOf(SDNode *N) const { 5034 bool Seen = false; 5035 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 5036 SDNode *User = *I; 5037 if (User == this) 5038 Seen = true; 5039 else 5040 return false; 5041 } 5042 5043 return Seen; 5044} 5045 5046/// isOperand - Return true if this node is an operand of N. 5047/// 5048bool SDValue::isOperandOf(SDNode *N) const { 5049 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 5050 if (*this == N->getOperand(i)) 5051 return true; 5052 return false; 5053} 5054 5055bool SDNode::isOperandOf(SDNode *N) const { 5056 for (unsigned i = 0, e = N->NumOperands; i != e; ++i) 5057 if (this == N->OperandList[i].getNode()) 5058 return true; 5059 return false; 5060} 5061 5062/// reachesChainWithoutSideEffects - Return true if this operand (which must 5063/// be a chain) reaches the specified operand without crossing any 5064/// side-effecting instructions. In practice, this looks through token 5065/// factors and non-volatile loads. In order to remain efficient, this only 5066/// looks a couple of nodes in, it does not do an exhaustive search. 5067bool SDValue::reachesChainWithoutSideEffects(SDValue Dest, 5068 unsigned Depth) const { 5069 if (*this == Dest) return true; 5070 5071 // Don't search too deeply, we just want to be able to see through 5072 // TokenFactor's etc. 5073 if (Depth == 0) return false; 5074 5075 // If this is a token factor, all inputs to the TF happen in parallel. If any 5076 // of the operands of the TF reach dest, then we can do the xform. 5077 if (getOpcode() == ISD::TokenFactor) { 5078 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) 5079 if (getOperand(i).reachesChainWithoutSideEffects(Dest, Depth-1)) 5080 return true; 5081 return false; 5082 } 5083 5084 // Loads don't have side effects, look through them. 5085 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(*this)) { 5086 if (!Ld->isVolatile()) 5087 return Ld->getChain().reachesChainWithoutSideEffects(Dest, Depth-1); 5088 } 5089 return false; 5090} 5091 5092 5093static void findPredecessor(SDNode *N, const SDNode *P, bool &found, 5094 SmallPtrSet<SDNode *, 32> &Visited) { 5095 if (found || !Visited.insert(N)) 5096 return; 5097 5098 for (unsigned i = 0, e = N->getNumOperands(); !found && i != e; ++i) { 5099 SDNode *Op = N->getOperand(i).getNode(); 5100 if (Op == P) { 5101 found = true; 5102 return; 5103 } 5104 findPredecessor(Op, P, found, Visited); 5105 } 5106} 5107 5108/// isPredecessorOf - Return true if this node is a predecessor of N. This node 5109/// is either an operand of N or it can be reached by recursively traversing 5110/// up the operands. 5111/// NOTE: this is an expensive method. Use it carefully. 5112bool SDNode::isPredecessorOf(SDNode *N) const { 5113 SmallPtrSet<SDNode *, 32> Visited; 5114 bool found = false; 5115 findPredecessor(N, this, found, Visited); 5116 return found; 5117} 5118 5119uint64_t SDNode::getConstantOperandVal(unsigned Num) const { 5120 assert(Num < NumOperands && "Invalid child # of SDNode!"); 5121 return cast<ConstantSDNode>(OperandList[Num])->getZExtValue(); 5122} 5123 5124std::string SDNode::getOperationName(const SelectionDAG *G) const { 5125 switch (getOpcode()) { 5126 default: 5127 if (getOpcode() < ISD::BUILTIN_OP_END) 5128 return "<<Unknown DAG Node>>"; 5129 if (isMachineOpcode()) { 5130 if (G) 5131 if (const TargetInstrInfo *TII = G->getTarget().getInstrInfo()) 5132 if (getMachineOpcode() < TII->getNumOpcodes()) 5133 return TII->get(getMachineOpcode()).getName(); 5134 return "<<Unknown Machine Node>>"; 5135 } 5136 if (G) { 5137 const TargetLowering &TLI = G->getTargetLoweringInfo(); 5138 const char *Name = TLI.getTargetNodeName(getOpcode()); 5139 if (Name) return Name; 5140 return "<<Unknown Target Node>>"; 5141 } 5142 return "<<Unknown Node>>"; 5143 5144#ifndef NDEBUG 5145 case ISD::DELETED_NODE: 5146 return "<<Deleted Node!>>"; 5147#endif 5148 case ISD::PREFETCH: return "Prefetch"; 5149 case ISD::MEMBARRIER: return "MemBarrier"; 5150 case ISD::ATOMIC_CMP_SWAP: return "AtomicCmpSwap"; 5151 case ISD::ATOMIC_SWAP: return "AtomicSwap"; 5152 case ISD::ATOMIC_LOAD_ADD: return "AtomicLoadAdd"; 5153 case ISD::ATOMIC_LOAD_SUB: return "AtomicLoadSub"; 5154 case ISD::ATOMIC_LOAD_AND: return "AtomicLoadAnd"; 5155 case ISD::ATOMIC_LOAD_OR: return "AtomicLoadOr"; 5156 case ISD::ATOMIC_LOAD_XOR: return "AtomicLoadXor"; 5157 case ISD::ATOMIC_LOAD_NAND: return "AtomicLoadNand"; 5158 case ISD::ATOMIC_LOAD_MIN: return "AtomicLoadMin"; 5159 case ISD::ATOMIC_LOAD_MAX: return "AtomicLoadMax"; 5160 case ISD::ATOMIC_LOAD_UMIN: return "AtomicLoadUMin"; 5161 case ISD::ATOMIC_LOAD_UMAX: return "AtomicLoadUMax"; 5162 case ISD::PCMARKER: return "PCMarker"; 5163 case ISD::READCYCLECOUNTER: return "ReadCycleCounter"; 5164 case ISD::SRCVALUE: return "SrcValue"; 5165 case ISD::MEMOPERAND: return "MemOperand"; 5166 case ISD::EntryToken: return "EntryToken"; 5167 case ISD::TokenFactor: return "TokenFactor"; 5168 case ISD::AssertSext: return "AssertSext"; 5169 case ISD::AssertZext: return "AssertZext"; 5170 5171 case ISD::BasicBlock: return "BasicBlock"; 5172 case ISD::ARG_FLAGS: return "ArgFlags"; 5173 case ISD::VALUETYPE: return "ValueType"; 5174 case ISD::Register: return "Register"; 5175 5176 case ISD::Constant: return "Constant"; 5177 case ISD::ConstantFP: return "ConstantFP"; 5178 case ISD::GlobalAddress: return "GlobalAddress"; 5179 case ISD::GlobalTLSAddress: return "GlobalTLSAddress"; 5180 case ISD::FrameIndex: return "FrameIndex"; 5181 case ISD::JumpTable: return "JumpTable"; 5182 case ISD::GLOBAL_OFFSET_TABLE: return "GLOBAL_OFFSET_TABLE"; 5183 case ISD::RETURNADDR: return "RETURNADDR"; 5184 case ISD::FRAMEADDR: return "FRAMEADDR"; 5185 case ISD::FRAME_TO_ARGS_OFFSET: return "FRAME_TO_ARGS_OFFSET"; 5186 case ISD::EXCEPTIONADDR: return "EXCEPTIONADDR"; 5187 case ISD::EHSELECTION: return "EHSELECTION"; 5188 case ISD::EH_RETURN: return "EH_RETURN"; 5189 case ISD::ConstantPool: return "ConstantPool"; 5190 case ISD::ExternalSymbol: return "ExternalSymbol"; 5191 case ISD::INTRINSIC_WO_CHAIN: { 5192 unsigned IID = cast<ConstantSDNode>(getOperand(0))->getZExtValue(); 5193 return Intrinsic::getName((Intrinsic::ID)IID); 5194 } 5195 case ISD::INTRINSIC_VOID: 5196 case ISD::INTRINSIC_W_CHAIN: { 5197 unsigned IID = cast<ConstantSDNode>(getOperand(1))->getZExtValue(); 5198 return Intrinsic::getName((Intrinsic::ID)IID); 5199 } 5200 5201 case ISD::BUILD_VECTOR: return "BUILD_VECTOR"; 5202 case ISD::TargetConstant: return "TargetConstant"; 5203 case ISD::TargetConstantFP:return "TargetConstantFP"; 5204 case ISD::TargetGlobalAddress: return "TargetGlobalAddress"; 5205 case ISD::TargetGlobalTLSAddress: return "TargetGlobalTLSAddress"; 5206 case ISD::TargetFrameIndex: return "TargetFrameIndex"; 5207 case ISD::TargetJumpTable: return "TargetJumpTable"; 5208 case ISD::TargetConstantPool: return "TargetConstantPool"; 5209 case ISD::TargetExternalSymbol: return "TargetExternalSymbol"; 5210 5211 case ISD::CopyToReg: return "CopyToReg"; 5212 case ISD::CopyFromReg: return "CopyFromReg"; 5213 case ISD::UNDEF: return "undef"; 5214 case ISD::MERGE_VALUES: return "merge_values"; 5215 case ISD::INLINEASM: return "inlineasm"; 5216 case ISD::DBG_LABEL: return "dbg_label"; 5217 case ISD::EH_LABEL: return "eh_label"; 5218 case ISD::DECLARE: return "declare"; 5219 case ISD::HANDLENODE: return "handlenode"; 5220 case ISD::FORMAL_ARGUMENTS: return "formal_arguments"; 5221 case ISD::CALL: return "call"; 5222 5223 // Unary operators 5224 case ISD::FABS: return "fabs"; 5225 case ISD::FNEG: return "fneg"; 5226 case ISD::FSQRT: return "fsqrt"; 5227 case ISD::FSIN: return "fsin"; 5228 case ISD::FCOS: return "fcos"; 5229 case ISD::FPOWI: return "fpowi"; 5230 case ISD::FPOW: return "fpow"; 5231 case ISD::FTRUNC: return "ftrunc"; 5232 case ISD::FFLOOR: return "ffloor"; 5233 case ISD::FCEIL: return "fceil"; 5234 case ISD::FRINT: return "frint"; 5235 case ISD::FNEARBYINT: return "fnearbyint"; 5236 5237 // Binary operators 5238 case ISD::ADD: return "add"; 5239 case ISD::SUB: return "sub"; 5240 case ISD::MUL: return "mul"; 5241 case ISD::MULHU: return "mulhu"; 5242 case ISD::MULHS: return "mulhs"; 5243 case ISD::SDIV: return "sdiv"; 5244 case ISD::UDIV: return "udiv"; 5245 case ISD::SREM: return "srem"; 5246 case ISD::UREM: return "urem"; 5247 case ISD::SMUL_LOHI: return "smul_lohi"; 5248 case ISD::UMUL_LOHI: return "umul_lohi"; 5249 case ISD::SDIVREM: return "sdivrem"; 5250 case ISD::UDIVREM: return "udivrem"; 5251 case ISD::AND: return "and"; 5252 case ISD::OR: return "or"; 5253 case ISD::XOR: return "xor"; 5254 case ISD::SHL: return "shl"; 5255 case ISD::SRA: return "sra"; 5256 case ISD::SRL: return "srl"; 5257 case ISD::ROTL: return "rotl"; 5258 case ISD::ROTR: return "rotr"; 5259 case ISD::FADD: return "fadd"; 5260 case ISD::FSUB: return "fsub"; 5261 case ISD::FMUL: return "fmul"; 5262 case ISD::FDIV: return "fdiv"; 5263 case ISD::FREM: return "frem"; 5264 case ISD::FCOPYSIGN: return "fcopysign"; 5265 case ISD::FGETSIGN: return "fgetsign"; 5266 5267 case ISD::SETCC: return "setcc"; 5268 case ISD::VSETCC: return "vsetcc"; 5269 case ISD::SELECT: return "select"; 5270 case ISD::SELECT_CC: return "select_cc"; 5271 case ISD::INSERT_VECTOR_ELT: return "insert_vector_elt"; 5272 case ISD::EXTRACT_VECTOR_ELT: return "extract_vector_elt"; 5273 case ISD::CONCAT_VECTORS: return "concat_vectors"; 5274 case ISD::EXTRACT_SUBVECTOR: return "extract_subvector"; 5275 case ISD::SCALAR_TO_VECTOR: return "scalar_to_vector"; 5276 case ISD::VECTOR_SHUFFLE: return "vector_shuffle"; 5277 case ISD::CARRY_FALSE: return "carry_false"; 5278 case ISD::ADDC: return "addc"; 5279 case ISD::ADDE: return "adde"; 5280 case ISD::SADDO: return "saddo"; 5281 case ISD::UADDO: return "uaddo"; 5282 case ISD::SSUBO: return "ssubo"; 5283 case ISD::USUBO: return "usubo"; 5284 case ISD::SMULO: return "smulo"; 5285 case ISD::UMULO: return "umulo"; 5286 case ISD::SUBC: return "subc"; 5287 case ISD::SUBE: return "sube"; 5288 case ISD::SHL_PARTS: return "shl_parts"; 5289 case ISD::SRA_PARTS: return "sra_parts"; 5290 case ISD::SRL_PARTS: return "srl_parts"; 5291 5292 // Conversion operators. 5293 case ISD::SIGN_EXTEND: return "sign_extend"; 5294 case ISD::ZERO_EXTEND: return "zero_extend"; 5295 case ISD::ANY_EXTEND: return "any_extend"; 5296 case ISD::SIGN_EXTEND_INREG: return "sign_extend_inreg"; 5297 case ISD::TRUNCATE: return "truncate"; 5298 case ISD::FP_ROUND: return "fp_round"; 5299 case ISD::FLT_ROUNDS_: return "flt_rounds"; 5300 case ISD::FP_ROUND_INREG: return "fp_round_inreg"; 5301 case ISD::FP_EXTEND: return "fp_extend"; 5302 5303 case ISD::SINT_TO_FP: return "sint_to_fp"; 5304 case ISD::UINT_TO_FP: return "uint_to_fp"; 5305 case ISD::FP_TO_SINT: return "fp_to_sint"; 5306 case ISD::FP_TO_UINT: return "fp_to_uint"; 5307 case ISD::BIT_CONVERT: return "bit_convert"; 5308 5309 case ISD::CONVERT_RNDSAT: { 5310 switch (cast<CvtRndSatSDNode>(this)->getCvtCode()) { 5311 default: assert(0 && "Unknown cvt code!"); 5312 case ISD::CVT_FF: return "cvt_ff"; 5313 case ISD::CVT_FS: return "cvt_fs"; 5314 case ISD::CVT_FU: return "cvt_fu"; 5315 case ISD::CVT_SF: return "cvt_sf"; 5316 case ISD::CVT_UF: return "cvt_uf"; 5317 case ISD::CVT_SS: return "cvt_ss"; 5318 case ISD::CVT_SU: return "cvt_su"; 5319 case ISD::CVT_US: return "cvt_us"; 5320 case ISD::CVT_UU: return "cvt_uu"; 5321 } 5322 } 5323 5324 // Control flow instructions 5325 case ISD::BR: return "br"; 5326 case ISD::BRIND: return "brind"; 5327 case ISD::BR_JT: return "br_jt"; 5328 case ISD::BRCOND: return "brcond"; 5329 case ISD::BR_CC: return "br_cc"; 5330 case ISD::RET: return "ret"; 5331 case ISD::CALLSEQ_START: return "callseq_start"; 5332 case ISD::CALLSEQ_END: return "callseq_end"; 5333 5334 // Other operators 5335 case ISD::LOAD: return "load"; 5336 case ISD::STORE: return "store"; 5337 case ISD::VAARG: return "vaarg"; 5338 case ISD::VACOPY: return "vacopy"; 5339 case ISD::VAEND: return "vaend"; 5340 case ISD::VASTART: return "vastart"; 5341 case ISD::DYNAMIC_STACKALLOC: return "dynamic_stackalloc"; 5342 case ISD::EXTRACT_ELEMENT: return "extract_element"; 5343 case ISD::BUILD_PAIR: return "build_pair"; 5344 case ISD::STACKSAVE: return "stacksave"; 5345 case ISD::STACKRESTORE: return "stackrestore"; 5346 case ISD::TRAP: return "trap"; 5347 5348 // Bit manipulation 5349 case ISD::BSWAP: return "bswap"; 5350 case ISD::CTPOP: return "ctpop"; 5351 case ISD::CTTZ: return "cttz"; 5352 case ISD::CTLZ: return "ctlz"; 5353 5354 // Debug info 5355 case ISD::DBG_STOPPOINT: return "dbg_stoppoint"; 5356 case ISD::DEBUG_LOC: return "debug_loc"; 5357 5358 // Trampolines 5359 case ISD::TRAMPOLINE: return "trampoline"; 5360 5361 case ISD::CONDCODE: 5362 switch (cast<CondCodeSDNode>(this)->get()) { 5363 default: assert(0 && "Unknown setcc condition!"); 5364 case ISD::SETOEQ: return "setoeq"; 5365 case ISD::SETOGT: return "setogt"; 5366 case ISD::SETOGE: return "setoge"; 5367 case ISD::SETOLT: return "setolt"; 5368 case ISD::SETOLE: return "setole"; 5369 case ISD::SETONE: return "setone"; 5370 5371 case ISD::SETO: return "seto"; 5372 case ISD::SETUO: return "setuo"; 5373 case ISD::SETUEQ: return "setue"; 5374 case ISD::SETUGT: return "setugt"; 5375 case ISD::SETUGE: return "setuge"; 5376 case ISD::SETULT: return "setult"; 5377 case ISD::SETULE: return "setule"; 5378 case ISD::SETUNE: return "setune"; 5379 5380 case ISD::SETEQ: return "seteq"; 5381 case ISD::SETGT: return "setgt"; 5382 case ISD::SETGE: return "setge"; 5383 case ISD::SETLT: return "setlt"; 5384 case ISD::SETLE: return "setle"; 5385 case ISD::SETNE: return "setne"; 5386 } 5387 } 5388} 5389 5390const char *SDNode::getIndexedModeName(ISD::MemIndexedMode AM) { 5391 switch (AM) { 5392 default: 5393 return ""; 5394 case ISD::PRE_INC: 5395 return "<pre-inc>"; 5396 case ISD::PRE_DEC: 5397 return "<pre-dec>"; 5398 case ISD::POST_INC: 5399 return "<post-inc>"; 5400 case ISD::POST_DEC: 5401 return "<post-dec>"; 5402 } 5403} 5404 5405std::string ISD::ArgFlagsTy::getArgFlagsString() { 5406 std::string S = "< "; 5407 5408 if (isZExt()) 5409 S += "zext "; 5410 if (isSExt()) 5411 S += "sext "; 5412 if (isInReg()) 5413 S += "inreg "; 5414 if (isSRet()) 5415 S += "sret "; 5416 if (isByVal()) 5417 S += "byval "; 5418 if (isNest()) 5419 S += "nest "; 5420 if (getByValAlign()) 5421 S += "byval-align:" + utostr(getByValAlign()) + " "; 5422 if (getOrigAlign()) 5423 S += "orig-align:" + utostr(getOrigAlign()) + " "; 5424 if (getByValSize()) 5425 S += "byval-size:" + utostr(getByValSize()) + " "; 5426 return S + ">"; 5427} 5428 5429void SDNode::dump() const { dump(0); } 5430void SDNode::dump(const SelectionDAG *G) const { 5431 print(errs(), G); 5432} 5433 5434void SDNode::print_types(raw_ostream &OS, const SelectionDAG *G) const { 5435 OS << (void*)this << ": "; 5436 5437 for (unsigned i = 0, e = getNumValues(); i != e; ++i) { 5438 if (i) OS << ","; 5439 if (getValueType(i) == MVT::Other) 5440 OS << "ch"; 5441 else 5442 OS << getValueType(i).getMVTString(); 5443 } 5444 OS << " = " << getOperationName(G); 5445} 5446 5447void SDNode::print_details(raw_ostream &OS, const SelectionDAG *G) const { 5448 if (!isTargetOpcode() && getOpcode() == ISD::VECTOR_SHUFFLE) { 5449 const ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(this); 5450 OS << "<"; 5451 for (unsigned i = 0, e = ValueList[0].getVectorNumElements(); i != e; ++i) { 5452 int Idx = SVN->getMaskElt(i); 5453 if (i) OS << ","; 5454 if (Idx < 0) 5455 OS << "u"; 5456 else 5457 OS << Idx; 5458 } 5459 OS << ">"; 5460 } 5461 5462 if (const ConstantSDNode *CSDN = dyn_cast<ConstantSDNode>(this)) { 5463 OS << '<' << CSDN->getAPIntValue() << '>'; 5464 } else if (const ConstantFPSDNode *CSDN = dyn_cast<ConstantFPSDNode>(this)) { 5465 if (&CSDN->getValueAPF().getSemantics()==&APFloat::IEEEsingle) 5466 OS << '<' << CSDN->getValueAPF().convertToFloat() << '>'; 5467 else if (&CSDN->getValueAPF().getSemantics()==&APFloat::IEEEdouble) 5468 OS << '<' << CSDN->getValueAPF().convertToDouble() << '>'; 5469 else { 5470 OS << "<APFloat("; 5471 CSDN->getValueAPF().bitcastToAPInt().dump(); 5472 OS << ")>"; 5473 } 5474 } else if (const GlobalAddressSDNode *GADN = 5475 dyn_cast<GlobalAddressSDNode>(this)) { 5476 int64_t offset = GADN->getOffset(); 5477 OS << '<'; 5478 WriteAsOperand(OS, GADN->getGlobal()); 5479 OS << '>'; 5480 if (offset > 0) 5481 OS << " + " << offset; 5482 else 5483 OS << " " << offset; 5484 } else if (const FrameIndexSDNode *FIDN = dyn_cast<FrameIndexSDNode>(this)) { 5485 OS << "<" << FIDN->getIndex() << ">"; 5486 } else if (const JumpTableSDNode *JTDN = dyn_cast<JumpTableSDNode>(this)) { 5487 OS << "<" << JTDN->getIndex() << ">"; 5488 } else if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(this)){ 5489 int offset = CP->getOffset(); 5490 if (CP->isMachineConstantPoolEntry()) 5491 OS << "<" << *CP->getMachineCPVal() << ">"; 5492 else 5493 OS << "<" << *CP->getConstVal() << ">"; 5494 if (offset > 0) 5495 OS << " + " << offset; 5496 else 5497 OS << " " << offset; 5498 } else if (const BasicBlockSDNode *BBDN = dyn_cast<BasicBlockSDNode>(this)) { 5499 OS << "<"; 5500 const Value *LBB = (const Value*)BBDN->getBasicBlock()->getBasicBlock(); 5501 if (LBB) 5502 OS << LBB->getName() << " "; 5503 OS << (const void*)BBDN->getBasicBlock() << ">"; 5504 } else if (const RegisterSDNode *R = dyn_cast<RegisterSDNode>(this)) { 5505 if (G && R->getReg() && 5506 TargetRegisterInfo::isPhysicalRegister(R->getReg())) { 5507 OS << " " << G->getTarget().getRegisterInfo()->getName(R->getReg()); 5508 } else { 5509 OS << " #" << R->getReg(); 5510 } 5511 } else if (const ExternalSymbolSDNode *ES = 5512 dyn_cast<ExternalSymbolSDNode>(this)) { 5513 OS << "'" << ES->getSymbol() << "'"; 5514 } else if (const SrcValueSDNode *M = dyn_cast<SrcValueSDNode>(this)) { 5515 if (M->getValue()) 5516 OS << "<" << M->getValue() << ">"; 5517 else 5518 OS << "<null>"; 5519 } else if (const MemOperandSDNode *M = dyn_cast<MemOperandSDNode>(this)) { 5520 if (M->MO.getValue()) 5521 OS << "<" << M->MO.getValue() << ":" << M->MO.getOffset() << ">"; 5522 else 5523 OS << "<null:" << M->MO.getOffset() << ">"; 5524 } else if (const ARG_FLAGSSDNode *N = dyn_cast<ARG_FLAGSSDNode>(this)) { 5525 OS << N->getArgFlags().getArgFlagsString(); 5526 } else if (const VTSDNode *N = dyn_cast<VTSDNode>(this)) { 5527 OS << ":" << N->getVT().getMVTString(); 5528 } 5529 else if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(this)) { 5530 const Value *SrcValue = LD->getSrcValue(); 5531 int SrcOffset = LD->getSrcValueOffset(); 5532 OS << " <"; 5533 if (SrcValue) 5534 OS << SrcValue; 5535 else 5536 OS << "null"; 5537 OS << ":" << SrcOffset << ">"; 5538 5539 bool doExt = true; 5540 switch (LD->getExtensionType()) { 5541 default: doExt = false; break; 5542 case ISD::EXTLOAD: OS << " <anyext "; break; 5543 case ISD::SEXTLOAD: OS << " <sext "; break; 5544 case ISD::ZEXTLOAD: OS << " <zext "; break; 5545 } 5546 if (doExt) 5547 OS << LD->getMemoryVT().getMVTString() << ">"; 5548 5549 const char *AM = getIndexedModeName(LD->getAddressingMode()); 5550 if (*AM) 5551 OS << " " << AM; 5552 if (LD->isVolatile()) 5553 OS << " <volatile>"; 5554 OS << " alignment=" << LD->getAlignment(); 5555 } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(this)) { 5556 const Value *SrcValue = ST->getSrcValue(); 5557 int SrcOffset = ST->getSrcValueOffset(); 5558 OS << " <"; 5559 if (SrcValue) 5560 OS << SrcValue; 5561 else 5562 OS << "null"; 5563 OS << ":" << SrcOffset << ">"; 5564 5565 if (ST->isTruncatingStore()) 5566 OS << " <trunc " << ST->getMemoryVT().getMVTString() << ">"; 5567 5568 const char *AM = getIndexedModeName(ST->getAddressingMode()); 5569 if (*AM) 5570 OS << " " << AM; 5571 if (ST->isVolatile()) 5572 OS << " <volatile>"; 5573 OS << " alignment=" << ST->getAlignment(); 5574 } else if (const AtomicSDNode* AT = dyn_cast<AtomicSDNode>(this)) { 5575 const Value *SrcValue = AT->getSrcValue(); 5576 int SrcOffset = AT->getSrcValueOffset(); 5577 OS << " <"; 5578 if (SrcValue) 5579 OS << SrcValue; 5580 else 5581 OS << "null"; 5582 OS << ":" << SrcOffset << ">"; 5583 if (AT->isVolatile()) 5584 OS << " <volatile>"; 5585 OS << " alignment=" << AT->getAlignment(); 5586 } 5587} 5588 5589void SDNode::print(raw_ostream &OS, const SelectionDAG *G) const { 5590 print_types(OS, G); 5591 OS << " "; 5592 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 5593 if (i) OS << ", "; 5594 OS << (void*)getOperand(i).getNode(); 5595 if (unsigned RN = getOperand(i).getResNo()) 5596 OS << ":" << RN; 5597 } 5598 print_details(OS, G); 5599} 5600 5601static void DumpNodes(const SDNode *N, unsigned indent, const SelectionDAG *G) { 5602 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 5603 if (N->getOperand(i).getNode()->hasOneUse()) 5604 DumpNodes(N->getOperand(i).getNode(), indent+2, G); 5605 else 5606 cerr << "\n" << std::string(indent+2, ' ') 5607 << (void*)N->getOperand(i).getNode() << ": <multiple use>"; 5608 5609 5610 cerr << "\n" << std::string(indent, ' '); 5611 N->dump(G); 5612} 5613 5614void SelectionDAG::dump() const { 5615 cerr << "SelectionDAG has " << AllNodes.size() << " nodes:"; 5616 5617 for (allnodes_const_iterator I = allnodes_begin(), E = allnodes_end(); 5618 I != E; ++I) { 5619 const SDNode *N = I; 5620 if (!N->hasOneUse() && N != getRoot().getNode()) 5621 DumpNodes(N, 2, this); 5622 } 5623 5624 if (getRoot().getNode()) DumpNodes(getRoot().getNode(), 2, this); 5625 5626 cerr << "\n\n"; 5627} 5628 5629void SDNode::printr(raw_ostream &OS, const SelectionDAG *G) const { 5630 print_types(OS, G); 5631 print_details(OS, G); 5632} 5633 5634typedef SmallPtrSet<const SDNode *, 128> VisitedSDNodeSet; 5635static void DumpNodesr(raw_ostream &OS, const SDNode *N, unsigned indent, 5636 const SelectionDAG *G, VisitedSDNodeSet &once) { 5637 if (!once.insert(N)) // If we've been here before, return now. 5638 return; 5639 // Dump the current SDNode, but don't end the line yet. 5640 OS << std::string(indent, ' '); 5641 N->printr(OS, G); 5642 // Having printed this SDNode, walk the children: 5643 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 5644 const SDNode *child = N->getOperand(i).getNode(); 5645 if (i) OS << ","; 5646 OS << " "; 5647 if (child->getNumOperands() == 0) { 5648 // This child has no grandchildren; print it inline right here. 5649 child->printr(OS, G); 5650 once.insert(child); 5651 } else { // Just the address. FIXME: also print the child's opcode 5652 OS << (void*)child; 5653 if (unsigned RN = N->getOperand(i).getResNo()) 5654 OS << ":" << RN; 5655 } 5656 } 5657 OS << "\n"; 5658 // Dump children that have grandchildren on their own line(s). 5659 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 5660 const SDNode *child = N->getOperand(i).getNode(); 5661 DumpNodesr(OS, child, indent+2, G, once); 5662 } 5663} 5664 5665void SDNode::dumpr() const { 5666 VisitedSDNodeSet once; 5667 DumpNodesr(errs(), this, 0, 0, once); 5668} 5669 5670 5671// getAddressSpace - Return the address space this GlobalAddress belongs to. 5672unsigned GlobalAddressSDNode::getAddressSpace() const { 5673 return getGlobal()->getType()->getAddressSpace(); 5674} 5675 5676 5677const Type *ConstantPoolSDNode::getType() const { 5678 if (isMachineConstantPoolEntry()) 5679 return Val.MachineCPVal->getType(); 5680 return Val.ConstVal->getType(); 5681} 5682 5683bool BuildVectorSDNode::isConstantSplat(APInt &SplatValue, 5684 APInt &SplatUndef, 5685 unsigned &SplatBitSize, 5686 bool &HasAnyUndefs, 5687 unsigned MinSplatBits) { 5688 MVT VT = getValueType(0); 5689 assert(VT.isVector() && "Expected a vector type"); 5690 unsigned sz = VT.getSizeInBits(); 5691 if (MinSplatBits > sz) 5692 return false; 5693 5694 SplatValue = APInt(sz, 0); 5695 SplatUndef = APInt(sz, 0); 5696 5697 // Get the bits. Bits with undefined values (when the corresponding element 5698 // of the vector is an ISD::UNDEF value) are set in SplatUndef and cleared 5699 // in SplatValue. If any of the values are not constant, give up and return 5700 // false. 5701 unsigned int nOps = getNumOperands(); 5702 assert(nOps > 0 && "isConstantSplat has 0-size build vector"); 5703 unsigned EltBitSize = VT.getVectorElementType().getSizeInBits(); 5704 for (unsigned i = 0; i < nOps; ++i) { 5705 SDValue OpVal = getOperand(i); 5706 unsigned BitPos = i * EltBitSize; 5707 5708 if (OpVal.getOpcode() == ISD::UNDEF) 5709 SplatUndef |= APInt::getBitsSet(sz, BitPos, BitPos +EltBitSize); 5710 else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) 5711 SplatValue |= (APInt(CN->getAPIntValue()).zextOrTrunc(EltBitSize). 5712 zextOrTrunc(sz) << BitPos); 5713 else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) 5714 SplatValue |= CN->getValueAPF().bitcastToAPInt().zextOrTrunc(sz) <<BitPos; 5715 else 5716 return false; 5717 } 5718 5719 // The build_vector is all constants or undefs. Find the smallest element 5720 // size that splats the vector. 5721 5722 HasAnyUndefs = (SplatUndef != 0); 5723 while (sz > 8) { 5724 5725 unsigned HalfSize = sz / 2; 5726 APInt HighValue = APInt(SplatValue).lshr(HalfSize).trunc(HalfSize); 5727 APInt LowValue = APInt(SplatValue).trunc(HalfSize); 5728 APInt HighUndef = APInt(SplatUndef).lshr(HalfSize).trunc(HalfSize); 5729 APInt LowUndef = APInt(SplatUndef).trunc(HalfSize); 5730 5731 // If the two halves do not match (ignoring undef bits), stop here. 5732 if ((HighValue & ~LowUndef) != (LowValue & ~HighUndef) || 5733 MinSplatBits > HalfSize) 5734 break; 5735 5736 SplatValue = HighValue | LowValue; 5737 SplatUndef = HighUndef & LowUndef; 5738 5739 sz = HalfSize; 5740 } 5741 5742 SplatBitSize = sz; 5743 return true; 5744} 5745 5746bool ShuffleVectorSDNode::isSplatMask(const int *Mask, MVT VT) { 5747 // Find the first non-undef value in the shuffle mask. 5748 unsigned i, e; 5749 for (i = 0, e = VT.getVectorNumElements(); i != e && Mask[i] < 0; ++i) 5750 /* search */; 5751 5752 assert(i != e && "VECTOR_SHUFFLE node with all undef indices!"); 5753 5754 // Make sure all remaining elements are either undef or the same as the first 5755 // non-undef value. 5756 for (int Idx = Mask[i]; i != e; ++i) 5757 if (Mask[i] >= 0 && Mask[i] != Idx) 5758 return false; 5759 return true; 5760} 5761