SelectionDAG.cpp revision bd209ab9bc0f6ad667c15df4453955c2ed4c2434
1//===-- SelectionDAG.cpp - Implement the SelectionDAG data structures -----===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAG class. 11// 12//===----------------------------------------------------------------------===// 13#include "llvm/CodeGen/SelectionDAG.h" 14#include "llvm/Constants.h" 15#include "llvm/Analysis/ValueTracking.h" 16#include "llvm/GlobalAlias.h" 17#include "llvm/GlobalVariable.h" 18#include "llvm/Intrinsics.h" 19#include "llvm/DerivedTypes.h" 20#include "llvm/Assembly/Writer.h" 21#include "llvm/CallingConv.h" 22#include "llvm/CodeGen/MachineBasicBlock.h" 23#include "llvm/CodeGen/MachineConstantPool.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/MachineModuleInfo.h" 26#include "llvm/CodeGen/PseudoSourceValue.h" 27#include "llvm/Target/TargetRegisterInfo.h" 28#include "llvm/Target/TargetData.h" 29#include "llvm/Target/TargetLowering.h" 30#include "llvm/Target/TargetOptions.h" 31#include "llvm/Target/TargetInstrInfo.h" 32#include "llvm/Target/TargetMachine.h" 33#include "llvm/Support/CommandLine.h" 34#include "llvm/Support/MathExtras.h" 35#include "llvm/Support/raw_ostream.h" 36#include "llvm/ADT/SetVector.h" 37#include "llvm/ADT/SmallPtrSet.h" 38#include "llvm/ADT/SmallSet.h" 39#include "llvm/ADT/SmallVector.h" 40#include "llvm/ADT/StringExtras.h" 41#include <algorithm> 42#include <cmath> 43using namespace llvm; 44 45/// makeVTList - Return an instance of the SDVTList struct initialized with the 46/// specified members. 47static SDVTList makeVTList(const MVT *VTs, unsigned NumVTs) { 48 SDVTList Res = {VTs, NumVTs}; 49 return Res; 50} 51 52static const fltSemantics *MVTToAPFloatSemantics(MVT VT) { 53 switch (VT.getSimpleVT()) { 54 default: assert(0 && "Unknown FP format"); 55 case MVT::f32: return &APFloat::IEEEsingle; 56 case MVT::f64: return &APFloat::IEEEdouble; 57 case MVT::f80: return &APFloat::x87DoubleExtended; 58 case MVT::f128: return &APFloat::IEEEquad; 59 case MVT::ppcf128: return &APFloat::PPCDoubleDouble; 60 } 61} 62 63SelectionDAG::DAGUpdateListener::~DAGUpdateListener() {} 64 65//===----------------------------------------------------------------------===// 66// ConstantFPSDNode Class 67//===----------------------------------------------------------------------===// 68 69/// isExactlyValue - We don't rely on operator== working on double values, as 70/// it returns true for things that are clearly not equal, like -0.0 and 0.0. 71/// As such, this method can be used to do an exact bit-for-bit comparison of 72/// two floating point values. 73bool ConstantFPSDNode::isExactlyValue(const APFloat& V) const { 74 return getValueAPF().bitwiseIsEqual(V); 75} 76 77bool ConstantFPSDNode::isValueValidForType(MVT VT, 78 const APFloat& Val) { 79 assert(VT.isFloatingPoint() && "Can only convert between FP types"); 80 81 // PPC long double cannot be converted to any other type. 82 if (VT == MVT::ppcf128 || 83 &Val.getSemantics() == &APFloat::PPCDoubleDouble) 84 return false; 85 86 // convert modifies in place, so make a copy. 87 APFloat Val2 = APFloat(Val); 88 bool losesInfo; 89 (void) Val2.convert(*MVTToAPFloatSemantics(VT), APFloat::rmNearestTiesToEven, 90 &losesInfo); 91 return !losesInfo; 92} 93 94//===----------------------------------------------------------------------===// 95// ISD Namespace 96//===----------------------------------------------------------------------===// 97 98/// isBuildVectorAllOnes - Return true if the specified node is a 99/// BUILD_VECTOR where all of the elements are ~0 or undef. 100bool ISD::isBuildVectorAllOnes(const SDNode *N) { 101 // Look through a bit convert. 102 if (N->getOpcode() == ISD::BIT_CONVERT) 103 N = N->getOperand(0).getNode(); 104 105 if (N->getOpcode() != ISD::BUILD_VECTOR) return false; 106 107 unsigned i = 0, e = N->getNumOperands(); 108 109 // Skip over all of the undef values. 110 while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF) 111 ++i; 112 113 // Do not accept an all-undef vector. 114 if (i == e) return false; 115 116 // Do not accept build_vectors that aren't all constants or which have non-~0 117 // elements. 118 SDValue NotZero = N->getOperand(i); 119 if (isa<ConstantSDNode>(NotZero)) { 120 if (!cast<ConstantSDNode>(NotZero)->isAllOnesValue()) 121 return false; 122 } else if (isa<ConstantFPSDNode>(NotZero)) { 123 if (!cast<ConstantFPSDNode>(NotZero)->getValueAPF(). 124 bitcastToAPInt().isAllOnesValue()) 125 return false; 126 } else 127 return false; 128 129 // Okay, we have at least one ~0 value, check to see if the rest match or are 130 // undefs. 131 for (++i; i != e; ++i) 132 if (N->getOperand(i) != NotZero && 133 N->getOperand(i).getOpcode() != ISD::UNDEF) 134 return false; 135 return true; 136} 137 138 139/// isBuildVectorAllZeros - Return true if the specified node is a 140/// BUILD_VECTOR where all of the elements are 0 or undef. 141bool ISD::isBuildVectorAllZeros(const SDNode *N) { 142 // Look through a bit convert. 143 if (N->getOpcode() == ISD::BIT_CONVERT) 144 N = N->getOperand(0).getNode(); 145 146 if (N->getOpcode() != ISD::BUILD_VECTOR) return false; 147 148 unsigned i = 0, e = N->getNumOperands(); 149 150 // Skip over all of the undef values. 151 while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF) 152 ++i; 153 154 // Do not accept an all-undef vector. 155 if (i == e) return false; 156 157 // Do not accept build_vectors that aren't all constants or which have non-~0 158 // elements. 159 SDValue Zero = N->getOperand(i); 160 if (isa<ConstantSDNode>(Zero)) { 161 if (!cast<ConstantSDNode>(Zero)->isNullValue()) 162 return false; 163 } else if (isa<ConstantFPSDNode>(Zero)) { 164 if (!cast<ConstantFPSDNode>(Zero)->getValueAPF().isPosZero()) 165 return false; 166 } else 167 return false; 168 169 // Okay, we have at least one ~0 value, check to see if the rest match or are 170 // undefs. 171 for (++i; i != e; ++i) 172 if (N->getOperand(i) != Zero && 173 N->getOperand(i).getOpcode() != ISD::UNDEF) 174 return false; 175 return true; 176} 177 178/// isScalarToVector - Return true if the specified node is a 179/// ISD::SCALAR_TO_VECTOR node or a BUILD_VECTOR node where only the low 180/// element is not an undef. 181bool ISD::isScalarToVector(const SDNode *N) { 182 if (N->getOpcode() == ISD::SCALAR_TO_VECTOR) 183 return true; 184 185 if (N->getOpcode() != ISD::BUILD_VECTOR) 186 return false; 187 if (N->getOperand(0).getOpcode() == ISD::UNDEF) 188 return false; 189 unsigned NumElems = N->getNumOperands(); 190 for (unsigned i = 1; i < NumElems; ++i) { 191 SDValue V = N->getOperand(i); 192 if (V.getOpcode() != ISD::UNDEF) 193 return false; 194 } 195 return true; 196} 197 198 199/// isDebugLabel - Return true if the specified node represents a debug 200/// label (i.e. ISD::DBG_LABEL or TargetInstrInfo::DBG_LABEL node). 201bool ISD::isDebugLabel(const SDNode *N) { 202 SDValue Zero; 203 if (N->getOpcode() == ISD::DBG_LABEL) 204 return true; 205 if (N->isMachineOpcode() && 206 N->getMachineOpcode() == TargetInstrInfo::DBG_LABEL) 207 return true; 208 return false; 209} 210 211/// getSetCCSwappedOperands - Return the operation corresponding to (Y op X) 212/// when given the operation for (X op Y). 213ISD::CondCode ISD::getSetCCSwappedOperands(ISD::CondCode Operation) { 214 // To perform this operation, we just need to swap the L and G bits of the 215 // operation. 216 unsigned OldL = (Operation >> 2) & 1; 217 unsigned OldG = (Operation >> 1) & 1; 218 return ISD::CondCode((Operation & ~6) | // Keep the N, U, E bits 219 (OldL << 1) | // New G bit 220 (OldG << 2)); // New L bit. 221} 222 223/// getSetCCInverse - Return the operation corresponding to !(X op Y), where 224/// 'op' is a valid SetCC operation. 225ISD::CondCode ISD::getSetCCInverse(ISD::CondCode Op, bool isInteger) { 226 unsigned Operation = Op; 227 if (isInteger) 228 Operation ^= 7; // Flip L, G, E bits, but not U. 229 else 230 Operation ^= 15; // Flip all of the condition bits. 231 232 if (Operation > ISD::SETTRUE2) 233 Operation &= ~8; // Don't let N and U bits get set. 234 235 return ISD::CondCode(Operation); 236} 237 238 239/// isSignedOp - For an integer comparison, return 1 if the comparison is a 240/// signed operation and 2 if the result is an unsigned comparison. Return zero 241/// if the operation does not depend on the sign of the input (setne and seteq). 242static int isSignedOp(ISD::CondCode Opcode) { 243 switch (Opcode) { 244 default: assert(0 && "Illegal integer setcc operation!"); 245 case ISD::SETEQ: 246 case ISD::SETNE: return 0; 247 case ISD::SETLT: 248 case ISD::SETLE: 249 case ISD::SETGT: 250 case ISD::SETGE: return 1; 251 case ISD::SETULT: 252 case ISD::SETULE: 253 case ISD::SETUGT: 254 case ISD::SETUGE: return 2; 255 } 256} 257 258/// getSetCCOrOperation - Return the result of a logical OR between different 259/// comparisons of identical values: ((X op1 Y) | (X op2 Y)). This function 260/// returns SETCC_INVALID if it is not possible to represent the resultant 261/// comparison. 262ISD::CondCode ISD::getSetCCOrOperation(ISD::CondCode Op1, ISD::CondCode Op2, 263 bool isInteger) { 264 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 265 // Cannot fold a signed integer setcc with an unsigned integer setcc. 266 return ISD::SETCC_INVALID; 267 268 unsigned Op = Op1 | Op2; // Combine all of the condition bits. 269 270 // If the N and U bits get set then the resultant comparison DOES suddenly 271 // care about orderedness, and is true when ordered. 272 if (Op > ISD::SETTRUE2) 273 Op &= ~16; // Clear the U bit if the N bit is set. 274 275 // Canonicalize illegal integer setcc's. 276 if (isInteger && Op == ISD::SETUNE) // e.g. SETUGT | SETULT 277 Op = ISD::SETNE; 278 279 return ISD::CondCode(Op); 280} 281 282/// getSetCCAndOperation - Return the result of a logical AND between different 283/// comparisons of identical values: ((X op1 Y) & (X op2 Y)). This 284/// function returns zero if it is not possible to represent the resultant 285/// comparison. 286ISD::CondCode ISD::getSetCCAndOperation(ISD::CondCode Op1, ISD::CondCode Op2, 287 bool isInteger) { 288 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 289 // Cannot fold a signed setcc with an unsigned setcc. 290 return ISD::SETCC_INVALID; 291 292 // Combine all of the condition bits. 293 ISD::CondCode Result = ISD::CondCode(Op1 & Op2); 294 295 // Canonicalize illegal integer setcc's. 296 if (isInteger) { 297 switch (Result) { 298 default: break; 299 case ISD::SETUO : Result = ISD::SETFALSE; break; // SETUGT & SETULT 300 case ISD::SETOEQ: // SETEQ & SETU[LG]E 301 case ISD::SETUEQ: Result = ISD::SETEQ ; break; // SETUGE & SETULE 302 case ISD::SETOLT: Result = ISD::SETULT ; break; // SETULT & SETNE 303 case ISD::SETOGT: Result = ISD::SETUGT ; break; // SETUGT & SETNE 304 } 305 } 306 307 return Result; 308} 309 310const TargetMachine &SelectionDAG::getTarget() const { 311 return MF->getTarget(); 312} 313 314//===----------------------------------------------------------------------===// 315// SDNode Profile Support 316//===----------------------------------------------------------------------===// 317 318/// AddNodeIDOpcode - Add the node opcode to the NodeID data. 319/// 320static void AddNodeIDOpcode(FoldingSetNodeID &ID, unsigned OpC) { 321 ID.AddInteger(OpC); 322} 323 324/// AddNodeIDValueTypes - Value type lists are intern'd so we can represent them 325/// solely with their pointer. 326static void AddNodeIDValueTypes(FoldingSetNodeID &ID, SDVTList VTList) { 327 ID.AddPointer(VTList.VTs); 328} 329 330/// AddNodeIDOperands - Various routines for adding operands to the NodeID data. 331/// 332static void AddNodeIDOperands(FoldingSetNodeID &ID, 333 const SDValue *Ops, unsigned NumOps) { 334 for (; NumOps; --NumOps, ++Ops) { 335 ID.AddPointer(Ops->getNode()); 336 ID.AddInteger(Ops->getResNo()); 337 } 338} 339 340/// AddNodeIDOperands - Various routines for adding operands to the NodeID data. 341/// 342static void AddNodeIDOperands(FoldingSetNodeID &ID, 343 const SDUse *Ops, unsigned NumOps) { 344 for (; NumOps; --NumOps, ++Ops) { 345 ID.AddPointer(Ops->getNode()); 346 ID.AddInteger(Ops->getResNo()); 347 } 348} 349 350static void AddNodeIDNode(FoldingSetNodeID &ID, 351 unsigned short OpC, SDVTList VTList, 352 const SDValue *OpList, unsigned N) { 353 AddNodeIDOpcode(ID, OpC); 354 AddNodeIDValueTypes(ID, VTList); 355 AddNodeIDOperands(ID, OpList, N); 356} 357 358/// AddNodeIDCustom - If this is an SDNode with special info, add this info to 359/// the NodeID data. 360static void AddNodeIDCustom(FoldingSetNodeID &ID, const SDNode *N) { 361 switch (N->getOpcode()) { 362 default: break; // Normal nodes don't need extra info. 363 case ISD::ARG_FLAGS: 364 ID.AddInteger(cast<ARG_FLAGSSDNode>(N)->getArgFlags().getRawBits()); 365 break; 366 case ISD::TargetConstant: 367 case ISD::Constant: 368 ID.AddPointer(cast<ConstantSDNode>(N)->getConstantIntValue()); 369 break; 370 case ISD::TargetConstantFP: 371 case ISD::ConstantFP: { 372 ID.AddPointer(cast<ConstantFPSDNode>(N)->getConstantFPValue()); 373 break; 374 } 375 case ISD::TargetGlobalAddress: 376 case ISD::GlobalAddress: 377 case ISD::TargetGlobalTLSAddress: 378 case ISD::GlobalTLSAddress: { 379 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(N); 380 ID.AddPointer(GA->getGlobal()); 381 ID.AddInteger(GA->getOffset()); 382 break; 383 } 384 case ISD::BasicBlock: 385 ID.AddPointer(cast<BasicBlockSDNode>(N)->getBasicBlock()); 386 break; 387 case ISD::Register: 388 ID.AddInteger(cast<RegisterSDNode>(N)->getReg()); 389 break; 390 case ISD::DBG_STOPPOINT: { 391 const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(N); 392 ID.AddInteger(DSP->getLine()); 393 ID.AddInteger(DSP->getColumn()); 394 ID.AddPointer(DSP->getCompileUnit()); 395 break; 396 } 397 case ISD::SRCVALUE: 398 ID.AddPointer(cast<SrcValueSDNode>(N)->getValue()); 399 break; 400 case ISD::MEMOPERAND: { 401 const MachineMemOperand &MO = cast<MemOperandSDNode>(N)->MO; 402 MO.Profile(ID); 403 break; 404 } 405 case ISD::FrameIndex: 406 case ISD::TargetFrameIndex: 407 ID.AddInteger(cast<FrameIndexSDNode>(N)->getIndex()); 408 break; 409 case ISD::JumpTable: 410 case ISD::TargetJumpTable: 411 ID.AddInteger(cast<JumpTableSDNode>(N)->getIndex()); 412 break; 413 case ISD::ConstantPool: 414 case ISD::TargetConstantPool: { 415 const ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(N); 416 ID.AddInteger(CP->getAlignment()); 417 ID.AddInteger(CP->getOffset()); 418 if (CP->isMachineConstantPoolEntry()) 419 CP->getMachineCPVal()->AddSelectionDAGCSEId(ID); 420 else 421 ID.AddPointer(CP->getConstVal()); 422 break; 423 } 424 case ISD::CALL: { 425 const CallSDNode *Call = cast<CallSDNode>(N); 426 ID.AddInteger(Call->getCallingConv()); 427 ID.AddInteger(Call->isVarArg()); 428 break; 429 } 430 case ISD::LOAD: { 431 const LoadSDNode *LD = cast<LoadSDNode>(N); 432 ID.AddInteger(LD->getMemoryVT().getRawBits()); 433 ID.AddInteger(LD->getRawSubclassData()); 434 break; 435 } 436 case ISD::STORE: { 437 const StoreSDNode *ST = cast<StoreSDNode>(N); 438 ID.AddInteger(ST->getMemoryVT().getRawBits()); 439 ID.AddInteger(ST->getRawSubclassData()); 440 break; 441 } 442 case ISD::ATOMIC_CMP_SWAP: 443 case ISD::ATOMIC_SWAP: 444 case ISD::ATOMIC_LOAD_ADD: 445 case ISD::ATOMIC_LOAD_SUB: 446 case ISD::ATOMIC_LOAD_AND: 447 case ISD::ATOMIC_LOAD_OR: 448 case ISD::ATOMIC_LOAD_XOR: 449 case ISD::ATOMIC_LOAD_NAND: 450 case ISD::ATOMIC_LOAD_MIN: 451 case ISD::ATOMIC_LOAD_MAX: 452 case ISD::ATOMIC_LOAD_UMIN: 453 case ISD::ATOMIC_LOAD_UMAX: { 454 const AtomicSDNode *AT = cast<AtomicSDNode>(N); 455 ID.AddInteger(AT->getMemoryVT().getRawBits()); 456 ID.AddInteger(AT->getRawSubclassData()); 457 break; 458 } 459 } // end switch (N->getOpcode()) 460} 461 462/// AddNodeIDNode - Generic routine for adding a nodes info to the NodeID 463/// data. 464static void AddNodeIDNode(FoldingSetNodeID &ID, const SDNode *N) { 465 AddNodeIDOpcode(ID, N->getOpcode()); 466 // Add the return value info. 467 AddNodeIDValueTypes(ID, N->getVTList()); 468 // Add the operand info. 469 AddNodeIDOperands(ID, N->op_begin(), N->getNumOperands()); 470 471 // Handle SDNode leafs with special info. 472 AddNodeIDCustom(ID, N); 473} 474 475/// encodeMemSDNodeFlags - Generic routine for computing a value for use in 476/// the CSE map that carries alignment, volatility, indexing mode, and 477/// extension/truncation information. 478/// 479static inline unsigned 480encodeMemSDNodeFlags(int ConvType, ISD::MemIndexedMode AM, 481 bool isVolatile, unsigned Alignment) { 482 assert((ConvType & 3) == ConvType && 483 "ConvType may not require more than 2 bits!"); 484 assert((AM & 7) == AM && 485 "AM may not require more than 3 bits!"); 486 return ConvType | 487 (AM << 2) | 488 (isVolatile << 5) | 489 ((Log2_32(Alignment) + 1) << 6); 490} 491 492//===----------------------------------------------------------------------===// 493// SelectionDAG Class 494//===----------------------------------------------------------------------===// 495 496/// doNotCSE - Return true if CSE should not be performed for this node. 497static bool doNotCSE(SDNode *N) { 498 if (N->getValueType(0) == MVT::Flag) 499 return true; // Never CSE anything that produces a flag. 500 501 switch (N->getOpcode()) { 502 default: break; 503 case ISD::HANDLENODE: 504 case ISD::DBG_LABEL: 505 case ISD::DBG_STOPPOINT: 506 case ISD::EH_LABEL: 507 case ISD::DECLARE: 508 return true; // Never CSE these nodes. 509 } 510 511 // Check that remaining values produced are not flags. 512 for (unsigned i = 1, e = N->getNumValues(); i != e; ++i) 513 if (N->getValueType(i) == MVT::Flag) 514 return true; // Never CSE anything that produces a flag. 515 516 return false; 517} 518 519/// RemoveDeadNodes - This method deletes all unreachable nodes in the 520/// SelectionDAG. 521void SelectionDAG::RemoveDeadNodes() { 522 // Create a dummy node (which is not added to allnodes), that adds a reference 523 // to the root node, preventing it from being deleted. 524 HandleSDNode Dummy(getRoot()); 525 526 SmallVector<SDNode*, 128> DeadNodes; 527 528 // Add all obviously-dead nodes to the DeadNodes worklist. 529 for (allnodes_iterator I = allnodes_begin(), E = allnodes_end(); I != E; ++I) 530 if (I->use_empty()) 531 DeadNodes.push_back(I); 532 533 RemoveDeadNodes(DeadNodes); 534 535 // If the root changed (e.g. it was a dead load, update the root). 536 setRoot(Dummy.getValue()); 537} 538 539/// RemoveDeadNodes - This method deletes the unreachable nodes in the 540/// given list, and any nodes that become unreachable as a result. 541void SelectionDAG::RemoveDeadNodes(SmallVectorImpl<SDNode *> &DeadNodes, 542 DAGUpdateListener *UpdateListener) { 543 544 // Process the worklist, deleting the nodes and adding their uses to the 545 // worklist. 546 while (!DeadNodes.empty()) { 547 SDNode *N = DeadNodes.pop_back_val(); 548 549 if (UpdateListener) 550 UpdateListener->NodeDeleted(N, 0); 551 552 // Take the node out of the appropriate CSE map. 553 RemoveNodeFromCSEMaps(N); 554 555 // Next, brutally remove the operand list. This is safe to do, as there are 556 // no cycles in the graph. 557 for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ) { 558 SDUse &Use = *I++; 559 SDNode *Operand = Use.getNode(); 560 Use.set(SDValue()); 561 562 // Now that we removed this operand, see if there are no uses of it left. 563 if (Operand->use_empty()) 564 DeadNodes.push_back(Operand); 565 } 566 567 DeallocateNode(N); 568 } 569} 570 571void SelectionDAG::RemoveDeadNode(SDNode *N, DAGUpdateListener *UpdateListener){ 572 SmallVector<SDNode*, 16> DeadNodes(1, N); 573 RemoveDeadNodes(DeadNodes, UpdateListener); 574} 575 576void SelectionDAG::DeleteNode(SDNode *N) { 577 // First take this out of the appropriate CSE map. 578 RemoveNodeFromCSEMaps(N); 579 580 // Finally, remove uses due to operands of this node, remove from the 581 // AllNodes list, and delete the node. 582 DeleteNodeNotInCSEMaps(N); 583} 584 585void SelectionDAG::DeleteNodeNotInCSEMaps(SDNode *N) { 586 assert(N != AllNodes.begin() && "Cannot delete the entry node!"); 587 assert(N->use_empty() && "Cannot delete a node that is not dead!"); 588 589 // Drop all of the operands and decrement used node's use counts. 590 N->DropOperands(); 591 592 DeallocateNode(N); 593} 594 595void SelectionDAG::DeallocateNode(SDNode *N) { 596 if (N->OperandsNeedDelete) 597 delete[] N->OperandList; 598 599 // Set the opcode to DELETED_NODE to help catch bugs when node 600 // memory is reallocated. 601 N->NodeType = ISD::DELETED_NODE; 602 603 NodeAllocator.Deallocate(AllNodes.remove(N)); 604} 605 606/// RemoveNodeFromCSEMaps - Take the specified node out of the CSE map that 607/// correspond to it. This is useful when we're about to delete or repurpose 608/// the node. We don't want future request for structurally identical nodes 609/// to return N anymore. 610bool SelectionDAG::RemoveNodeFromCSEMaps(SDNode *N) { 611 bool Erased = false; 612 switch (N->getOpcode()) { 613 case ISD::EntryToken: 614 assert(0 && "EntryToken should not be in CSEMaps!"); 615 return false; 616 case ISD::HANDLENODE: return false; // noop. 617 case ISD::CONDCODE: 618 assert(CondCodeNodes[cast<CondCodeSDNode>(N)->get()] && 619 "Cond code doesn't exist!"); 620 Erased = CondCodeNodes[cast<CondCodeSDNode>(N)->get()] != 0; 621 CondCodeNodes[cast<CondCodeSDNode>(N)->get()] = 0; 622 break; 623 case ISD::ExternalSymbol: 624 Erased = ExternalSymbols.erase(cast<ExternalSymbolSDNode>(N)->getSymbol()); 625 break; 626 case ISD::TargetExternalSymbol: 627 Erased = 628 TargetExternalSymbols.erase(cast<ExternalSymbolSDNode>(N)->getSymbol()); 629 break; 630 case ISD::VALUETYPE: { 631 MVT VT = cast<VTSDNode>(N)->getVT(); 632 if (VT.isExtended()) { 633 Erased = ExtendedValueTypeNodes.erase(VT); 634 } else { 635 Erased = ValueTypeNodes[VT.getSimpleVT()] != 0; 636 ValueTypeNodes[VT.getSimpleVT()] = 0; 637 } 638 break; 639 } 640 default: 641 // Remove it from the CSE Map. 642 Erased = CSEMap.RemoveNode(N); 643 break; 644 } 645#ifndef NDEBUG 646 // Verify that the node was actually in one of the CSE maps, unless it has a 647 // flag result (which cannot be CSE'd) or is one of the special cases that are 648 // not subject to CSE. 649 if (!Erased && N->getValueType(N->getNumValues()-1) != MVT::Flag && 650 !N->isMachineOpcode() && !doNotCSE(N)) { 651 N->dump(this); 652 cerr << "\n"; 653 assert(0 && "Node is not in map!"); 654 } 655#endif 656 return Erased; 657} 658 659/// AddModifiedNodeToCSEMaps - The specified node has been removed from the CSE 660/// maps and modified in place. Add it back to the CSE maps, unless an identical 661/// node already exists, in which case transfer all its users to the existing 662/// node. This transfer can potentially trigger recursive merging. 663/// 664void 665SelectionDAG::AddModifiedNodeToCSEMaps(SDNode *N, 666 DAGUpdateListener *UpdateListener) { 667 // For node types that aren't CSE'd, just act as if no identical node 668 // already exists. 669 if (!doNotCSE(N)) { 670 SDNode *Existing = CSEMap.GetOrInsertNode(N); 671 if (Existing != N) { 672 // If there was already an existing matching node, use ReplaceAllUsesWith 673 // to replace the dead one with the existing one. This can cause 674 // recursive merging of other unrelated nodes down the line. 675 ReplaceAllUsesWith(N, Existing, UpdateListener); 676 677 // N is now dead. Inform the listener if it exists and delete it. 678 if (UpdateListener) 679 UpdateListener->NodeDeleted(N, Existing); 680 DeleteNodeNotInCSEMaps(N); 681 return; 682 } 683 } 684 685 // If the node doesn't already exist, we updated it. Inform a listener if 686 // it exists. 687 if (UpdateListener) 688 UpdateListener->NodeUpdated(N); 689} 690 691/// FindModifiedNodeSlot - Find a slot for the specified node if its operands 692/// were replaced with those specified. If this node is never memoized, 693/// return null, otherwise return a pointer to the slot it would take. If a 694/// node already exists with these operands, the slot will be non-null. 695SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, SDValue Op, 696 void *&InsertPos) { 697 if (doNotCSE(N)) 698 return 0; 699 700 SDValue Ops[] = { Op }; 701 FoldingSetNodeID ID; 702 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, 1); 703 AddNodeIDCustom(ID, N); 704 return CSEMap.FindNodeOrInsertPos(ID, InsertPos); 705} 706 707/// FindModifiedNodeSlot - Find a slot for the specified node if its operands 708/// were replaced with those specified. If this node is never memoized, 709/// return null, otherwise return a pointer to the slot it would take. If a 710/// node already exists with these operands, the slot will be non-null. 711SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, 712 SDValue Op1, SDValue Op2, 713 void *&InsertPos) { 714 if (doNotCSE(N)) 715 return 0; 716 717 SDValue Ops[] = { Op1, Op2 }; 718 FoldingSetNodeID ID; 719 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, 2); 720 AddNodeIDCustom(ID, N); 721 return CSEMap.FindNodeOrInsertPos(ID, InsertPos); 722} 723 724 725/// FindModifiedNodeSlot - Find a slot for the specified node if its operands 726/// were replaced with those specified. If this node is never memoized, 727/// return null, otherwise return a pointer to the slot it would take. If a 728/// node already exists with these operands, the slot will be non-null. 729SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, 730 const SDValue *Ops,unsigned NumOps, 731 void *&InsertPos) { 732 if (doNotCSE(N)) 733 return 0; 734 735 FoldingSetNodeID ID; 736 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, NumOps); 737 AddNodeIDCustom(ID, N); 738 return CSEMap.FindNodeOrInsertPos(ID, InsertPos); 739} 740 741/// VerifyNode - Sanity check the given node. Aborts if it is invalid. 742void SelectionDAG::VerifyNode(SDNode *N) { 743 switch (N->getOpcode()) { 744 default: 745 break; 746 case ISD::BUILD_PAIR: { 747 MVT VT = N->getValueType(0); 748 assert(N->getNumValues() == 1 && "Too many results!"); 749 assert(!VT.isVector() && (VT.isInteger() || VT.isFloatingPoint()) && 750 "Wrong return type!"); 751 assert(N->getNumOperands() == 2 && "Wrong number of operands!"); 752 assert(N->getOperand(0).getValueType() == N->getOperand(1).getValueType() && 753 "Mismatched operand types!"); 754 assert(N->getOperand(0).getValueType().isInteger() == VT.isInteger() && 755 "Wrong operand type!"); 756 assert(VT.getSizeInBits() == 2 * N->getOperand(0).getValueSizeInBits() && 757 "Wrong return type size"); 758 break; 759 } 760 case ISD::BUILD_VECTOR: { 761 assert(N->getNumValues() == 1 && "Too many results!"); 762 assert(N->getValueType(0).isVector() && "Wrong return type!"); 763 assert(N->getNumOperands() == N->getValueType(0).getVectorNumElements() && 764 "Wrong number of operands!"); 765 MVT EltVT = N->getValueType(0).getVectorElementType(); 766 for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ++I) 767 assert((I->getValueType() == EltVT || 768 (EltVT.isInteger() && I->getValueType().isInteger() && 769 EltVT.bitsLE(I->getValueType()))) && 770 "Wrong operand type!"); 771 break; 772 } 773 } 774} 775 776/// getMVTAlignment - Compute the default alignment value for the 777/// given type. 778/// 779unsigned SelectionDAG::getMVTAlignment(MVT VT) const { 780 const Type *Ty = VT == MVT::iPTR ? 781 PointerType::get(Type::Int8Ty, 0) : 782 VT.getTypeForMVT(); 783 784 return TLI.getTargetData()->getABITypeAlignment(Ty); 785} 786 787// EntryNode could meaningfully have debug info if we can find it... 788SelectionDAG::SelectionDAG(TargetLowering &tli, FunctionLoweringInfo &fli) 789 : TLI(tli), FLI(fli), DW(0), 790 EntryNode(ISD::EntryToken, DebugLoc::getUnknownLoc(), 791 getVTList(MVT::Other)), Root(getEntryNode()) { 792 AllNodes.push_back(&EntryNode); 793} 794 795void SelectionDAG::init(MachineFunction &mf, MachineModuleInfo *mmi, 796 DwarfWriter *dw) { 797 MF = &mf; 798 MMI = mmi; 799 DW = dw; 800} 801 802SelectionDAG::~SelectionDAG() { 803 allnodes_clear(); 804} 805 806void SelectionDAG::allnodes_clear() { 807 assert(&*AllNodes.begin() == &EntryNode); 808 AllNodes.remove(AllNodes.begin()); 809 while (!AllNodes.empty()) 810 DeallocateNode(AllNodes.begin()); 811} 812 813void SelectionDAG::clear() { 814 allnodes_clear(); 815 OperandAllocator.Reset(); 816 CSEMap.clear(); 817 818 ExtendedValueTypeNodes.clear(); 819 ExternalSymbols.clear(); 820 TargetExternalSymbols.clear(); 821 std::fill(CondCodeNodes.begin(), CondCodeNodes.end(), 822 static_cast<CondCodeSDNode*>(0)); 823 std::fill(ValueTypeNodes.begin(), ValueTypeNodes.end(), 824 static_cast<SDNode*>(0)); 825 826 EntryNode.UseList = 0; 827 AllNodes.push_back(&EntryNode); 828 Root = getEntryNode(); 829} 830 831SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, DebugLoc DL, MVT VT) { 832 if (Op.getValueType() == VT) return Op; 833 APInt Imm = APInt::getLowBitsSet(Op.getValueSizeInBits(), 834 VT.getSizeInBits()); 835 return getNode(ISD::AND, DL, Op.getValueType(), Op, 836 getConstant(Imm, Op.getValueType())); 837} 838 839/// getNOT - Create a bitwise NOT operation as (XOR Val, -1). 840/// 841SDValue SelectionDAG::getNOT(DebugLoc DL, SDValue Val, MVT VT) { 842 MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 843 SDValue NegOne = 844 getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT); 845 return getNode(ISD::XOR, DL, VT, Val, NegOne); 846} 847 848SDValue SelectionDAG::getConstant(uint64_t Val, MVT VT, bool isT) { 849 MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 850 assert((EltVT.getSizeInBits() >= 64 || 851 (uint64_t)((int64_t)Val >> EltVT.getSizeInBits()) + 1 < 2) && 852 "getConstant with a uint64_t value that doesn't fit in the type!"); 853 return getConstant(APInt(EltVT.getSizeInBits(), Val), VT, isT); 854} 855 856SDValue SelectionDAG::getConstant(const APInt &Val, MVT VT, bool isT) { 857 return getConstant(*ConstantInt::get(Val), VT, isT); 858} 859 860SDValue SelectionDAG::getConstant(const ConstantInt &Val, MVT VT, bool isT) { 861 assert(VT.isInteger() && "Cannot create FP integer constant!"); 862 863 MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 864 assert(Val.getBitWidth() == EltVT.getSizeInBits() && 865 "APInt size does not match type size!"); 866 867 unsigned Opc = isT ? ISD::TargetConstant : ISD::Constant; 868 FoldingSetNodeID ID; 869 AddNodeIDNode(ID, Opc, getVTList(EltVT), 0, 0); 870 ID.AddPointer(&Val); 871 void *IP = 0; 872 SDNode *N = NULL; 873 if ((N = CSEMap.FindNodeOrInsertPos(ID, IP))) 874 if (!VT.isVector()) 875 return SDValue(N, 0); 876 if (!N) { 877 N = NodeAllocator.Allocate<ConstantSDNode>(); 878 new (N) ConstantSDNode(isT, &Val, EltVT); 879 CSEMap.InsertNode(N, IP); 880 AllNodes.push_back(N); 881 } 882 883 SDValue Result(N, 0); 884 if (VT.isVector()) { 885 SmallVector<SDValue, 8> Ops; 886 Ops.assign(VT.getVectorNumElements(), Result); 887 Result = getNode(ISD::BUILD_VECTOR, DebugLoc::getUnknownLoc(), 888 VT, &Ops[0], Ops.size()); 889 } 890 return Result; 891} 892 893SDValue SelectionDAG::getIntPtrConstant(uint64_t Val, bool isTarget) { 894 return getConstant(Val, TLI.getPointerTy(), isTarget); 895} 896 897 898SDValue SelectionDAG::getConstantFP(const APFloat& V, MVT VT, bool isTarget) { 899 return getConstantFP(*ConstantFP::get(V), VT, isTarget); 900} 901 902SDValue SelectionDAG::getConstantFP(const ConstantFP& V, MVT VT, bool isTarget){ 903 assert(VT.isFloatingPoint() && "Cannot create integer FP constant!"); 904 905 MVT EltVT = 906 VT.isVector() ? VT.getVectorElementType() : VT; 907 908 // Do the map lookup using the actual bit pattern for the floating point 909 // value, so that we don't have problems with 0.0 comparing equal to -0.0, and 910 // we don't have issues with SNANs. 911 unsigned Opc = isTarget ? ISD::TargetConstantFP : ISD::ConstantFP; 912 FoldingSetNodeID ID; 913 AddNodeIDNode(ID, Opc, getVTList(EltVT), 0, 0); 914 ID.AddPointer(&V); 915 void *IP = 0; 916 SDNode *N = NULL; 917 if ((N = CSEMap.FindNodeOrInsertPos(ID, IP))) 918 if (!VT.isVector()) 919 return SDValue(N, 0); 920 if (!N) { 921 N = NodeAllocator.Allocate<ConstantFPSDNode>(); 922 new (N) ConstantFPSDNode(isTarget, &V, EltVT); 923 CSEMap.InsertNode(N, IP); 924 AllNodes.push_back(N); 925 } 926 927 SDValue Result(N, 0); 928 if (VT.isVector()) { 929 SmallVector<SDValue, 8> Ops; 930 Ops.assign(VT.getVectorNumElements(), Result); 931 // FIXME DebugLoc info might be appropriate here 932 Result = getNode(ISD::BUILD_VECTOR, DebugLoc::getUnknownLoc(), 933 VT, &Ops[0], Ops.size()); 934 } 935 return Result; 936} 937 938SDValue SelectionDAG::getConstantFP(double Val, MVT VT, bool isTarget) { 939 MVT EltVT = 940 VT.isVector() ? VT.getVectorElementType() : VT; 941 if (EltVT==MVT::f32) 942 return getConstantFP(APFloat((float)Val), VT, isTarget); 943 else 944 return getConstantFP(APFloat(Val), VT, isTarget); 945} 946 947SDValue SelectionDAG::getGlobalAddress(const GlobalValue *GV, 948 MVT VT, int64_t Offset, 949 bool isTargetGA) { 950 unsigned Opc; 951 952 // Truncate (with sign-extension) the offset value to the pointer size. 953 unsigned BitWidth = TLI.getPointerTy().getSizeInBits(); 954 if (BitWidth < 64) 955 Offset = (Offset << (64 - BitWidth) >> (64 - BitWidth)); 956 957 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV); 958 if (!GVar) { 959 // If GV is an alias then use the aliasee for determining thread-localness. 960 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) 961 GVar = dyn_cast_or_null<GlobalVariable>(GA->resolveAliasedGlobal(false)); 962 } 963 964 if (GVar && GVar->isThreadLocal()) 965 Opc = isTargetGA ? ISD::TargetGlobalTLSAddress : ISD::GlobalTLSAddress; 966 else 967 Opc = isTargetGA ? ISD::TargetGlobalAddress : ISD::GlobalAddress; 968 969 FoldingSetNodeID ID; 970 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 971 ID.AddPointer(GV); 972 ID.AddInteger(Offset); 973 void *IP = 0; 974 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 975 return SDValue(E, 0); 976 SDNode *N = NodeAllocator.Allocate<GlobalAddressSDNode>(); 977 new (N) GlobalAddressSDNode(isTargetGA, GV, VT, Offset); 978 CSEMap.InsertNode(N, IP); 979 AllNodes.push_back(N); 980 return SDValue(N, 0); 981} 982 983SDValue SelectionDAG::getFrameIndex(int FI, MVT VT, bool isTarget) { 984 unsigned Opc = isTarget ? ISD::TargetFrameIndex : ISD::FrameIndex; 985 FoldingSetNodeID ID; 986 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 987 ID.AddInteger(FI); 988 void *IP = 0; 989 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 990 return SDValue(E, 0); 991 SDNode *N = NodeAllocator.Allocate<FrameIndexSDNode>(); 992 new (N) FrameIndexSDNode(FI, VT, isTarget); 993 CSEMap.InsertNode(N, IP); 994 AllNodes.push_back(N); 995 return SDValue(N, 0); 996} 997 998SDValue SelectionDAG::getJumpTable(int JTI, MVT VT, bool isTarget){ 999 unsigned Opc = isTarget ? ISD::TargetJumpTable : ISD::JumpTable; 1000 FoldingSetNodeID ID; 1001 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 1002 ID.AddInteger(JTI); 1003 void *IP = 0; 1004 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1005 return SDValue(E, 0); 1006 SDNode *N = NodeAllocator.Allocate<JumpTableSDNode>(); 1007 new (N) JumpTableSDNode(JTI, VT, isTarget); 1008 CSEMap.InsertNode(N, IP); 1009 AllNodes.push_back(N); 1010 return SDValue(N, 0); 1011} 1012 1013SDValue SelectionDAG::getConstantPool(Constant *C, MVT VT, 1014 unsigned Alignment, int Offset, 1015 bool isTarget) { 1016 if (Alignment == 0) 1017 Alignment = TLI.getTargetData()->getPrefTypeAlignment(C->getType()); 1018 unsigned Opc = isTarget ? ISD::TargetConstantPool : ISD::ConstantPool; 1019 FoldingSetNodeID ID; 1020 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 1021 ID.AddInteger(Alignment); 1022 ID.AddInteger(Offset); 1023 ID.AddPointer(C); 1024 void *IP = 0; 1025 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1026 return SDValue(E, 0); 1027 SDNode *N = NodeAllocator.Allocate<ConstantPoolSDNode>(); 1028 new (N) ConstantPoolSDNode(isTarget, C, VT, Offset, Alignment); 1029 CSEMap.InsertNode(N, IP); 1030 AllNodes.push_back(N); 1031 return SDValue(N, 0); 1032} 1033 1034 1035SDValue SelectionDAG::getConstantPool(MachineConstantPoolValue *C, MVT VT, 1036 unsigned Alignment, int Offset, 1037 bool isTarget) { 1038 if (Alignment == 0) 1039 Alignment = TLI.getTargetData()->getPrefTypeAlignment(C->getType()); 1040 unsigned Opc = isTarget ? ISD::TargetConstantPool : ISD::ConstantPool; 1041 FoldingSetNodeID ID; 1042 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 1043 ID.AddInteger(Alignment); 1044 ID.AddInteger(Offset); 1045 C->AddSelectionDAGCSEId(ID); 1046 void *IP = 0; 1047 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1048 return SDValue(E, 0); 1049 SDNode *N = NodeAllocator.Allocate<ConstantPoolSDNode>(); 1050 new (N) ConstantPoolSDNode(isTarget, C, VT, Offset, Alignment); 1051 CSEMap.InsertNode(N, IP); 1052 AllNodes.push_back(N); 1053 return SDValue(N, 0); 1054} 1055 1056SDValue SelectionDAG::getBasicBlock(MachineBasicBlock *MBB) { 1057 FoldingSetNodeID ID; 1058 AddNodeIDNode(ID, ISD::BasicBlock, getVTList(MVT::Other), 0, 0); 1059 ID.AddPointer(MBB); 1060 void *IP = 0; 1061 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1062 return SDValue(E, 0); 1063 SDNode *N = NodeAllocator.Allocate<BasicBlockSDNode>(); 1064 new (N) BasicBlockSDNode(MBB); 1065 CSEMap.InsertNode(N, IP); 1066 AllNodes.push_back(N); 1067 return SDValue(N, 0); 1068} 1069 1070SDValue SelectionDAG::getArgFlags(ISD::ArgFlagsTy Flags) { 1071 FoldingSetNodeID ID; 1072 AddNodeIDNode(ID, ISD::ARG_FLAGS, getVTList(MVT::Other), 0, 0); 1073 ID.AddInteger(Flags.getRawBits()); 1074 void *IP = 0; 1075 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1076 return SDValue(E, 0); 1077 SDNode *N = NodeAllocator.Allocate<ARG_FLAGSSDNode>(); 1078 new (N) ARG_FLAGSSDNode(Flags); 1079 CSEMap.InsertNode(N, IP); 1080 AllNodes.push_back(N); 1081 return SDValue(N, 0); 1082} 1083 1084SDValue SelectionDAG::getValueType(MVT VT) { 1085 if (VT.isSimple() && (unsigned)VT.getSimpleVT() >= ValueTypeNodes.size()) 1086 ValueTypeNodes.resize(VT.getSimpleVT()+1); 1087 1088 SDNode *&N = VT.isExtended() ? 1089 ExtendedValueTypeNodes[VT] : ValueTypeNodes[VT.getSimpleVT()]; 1090 1091 if (N) return SDValue(N, 0); 1092 N = NodeAllocator.Allocate<VTSDNode>(); 1093 new (N) VTSDNode(VT); 1094 AllNodes.push_back(N); 1095 return SDValue(N, 0); 1096} 1097 1098SDValue SelectionDAG::getExternalSymbol(const char *Sym, MVT VT) { 1099 SDNode *&N = ExternalSymbols[Sym]; 1100 if (N) return SDValue(N, 0); 1101 N = NodeAllocator.Allocate<ExternalSymbolSDNode>(); 1102 new (N) ExternalSymbolSDNode(false, Sym, VT); 1103 AllNodes.push_back(N); 1104 return SDValue(N, 0); 1105} 1106 1107SDValue SelectionDAG::getTargetExternalSymbol(const char *Sym, MVT VT) { 1108 SDNode *&N = TargetExternalSymbols[Sym]; 1109 if (N) return SDValue(N, 0); 1110 N = NodeAllocator.Allocate<ExternalSymbolSDNode>(); 1111 new (N) ExternalSymbolSDNode(true, Sym, VT); 1112 AllNodes.push_back(N); 1113 return SDValue(N, 0); 1114} 1115 1116SDValue SelectionDAG::getCondCode(ISD::CondCode Cond) { 1117 if ((unsigned)Cond >= CondCodeNodes.size()) 1118 CondCodeNodes.resize(Cond+1); 1119 1120 if (CondCodeNodes[Cond] == 0) { 1121 CondCodeSDNode *N = NodeAllocator.Allocate<CondCodeSDNode>(); 1122 new (N) CondCodeSDNode(Cond); 1123 CondCodeNodes[Cond] = N; 1124 AllNodes.push_back(N); 1125 } 1126 return SDValue(CondCodeNodes[Cond], 0); 1127} 1128 1129SDValue SelectionDAG::getConvertRndSat(MVT VT, DebugLoc dl, 1130 SDValue Val, SDValue DTy, 1131 SDValue STy, SDValue Rnd, SDValue Sat, 1132 ISD::CvtCode Code) { 1133 // If the src and dest types are the same and the conversion is between 1134 // integer types of the same sign or two floats, no conversion is necessary. 1135 if (DTy == STy && 1136 (Code == ISD::CVT_UU || Code == ISD::CVT_SS || Code == ISD::CVT_FF)) 1137 return Val; 1138 1139 FoldingSetNodeID ID; 1140 void* IP = 0; 1141 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1142 return SDValue(E, 0); 1143 CvtRndSatSDNode *N = NodeAllocator.Allocate<CvtRndSatSDNode>(); 1144 SDValue Ops[] = { Val, DTy, STy, Rnd, Sat }; 1145 new (N) CvtRndSatSDNode(VT, dl, Ops, 5, Code); 1146 CSEMap.InsertNode(N, IP); 1147 AllNodes.push_back(N); 1148 return SDValue(N, 0); 1149} 1150 1151SDValue SelectionDAG::getRegister(unsigned RegNo, MVT VT) { 1152 FoldingSetNodeID ID; 1153 AddNodeIDNode(ID, ISD::Register, getVTList(VT), 0, 0); 1154 ID.AddInteger(RegNo); 1155 void *IP = 0; 1156 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1157 return SDValue(E, 0); 1158 SDNode *N = NodeAllocator.Allocate<RegisterSDNode>(); 1159 new (N) RegisterSDNode(RegNo, VT); 1160 CSEMap.InsertNode(N, IP); 1161 AllNodes.push_back(N); 1162 return SDValue(N, 0); 1163} 1164 1165SDValue SelectionDAG::getDbgStopPoint(SDValue Root, 1166 unsigned Line, unsigned Col, 1167 Value *CU) { 1168 SDNode *N = NodeAllocator.Allocate<DbgStopPointSDNode>(); 1169 new (N) DbgStopPointSDNode(Root, Line, Col, CU); 1170 AllNodes.push_back(N); 1171 return SDValue(N, 0); 1172} 1173 1174SDValue SelectionDAG::getLabel(unsigned Opcode, DebugLoc dl, 1175 SDValue Root, 1176 unsigned LabelID) { 1177 FoldingSetNodeID ID; 1178 SDValue Ops[] = { Root }; 1179 AddNodeIDNode(ID, Opcode, getVTList(MVT::Other), &Ops[0], 1); 1180 ID.AddInteger(LabelID); 1181 void *IP = 0; 1182 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1183 return SDValue(E, 0); 1184 SDNode *N = NodeAllocator.Allocate<LabelSDNode>(); 1185 new (N) LabelSDNode(Opcode, dl, Root, LabelID); 1186 CSEMap.InsertNode(N, IP); 1187 AllNodes.push_back(N); 1188 return SDValue(N, 0); 1189} 1190 1191SDValue SelectionDAG::getSrcValue(const Value *V) { 1192 assert((!V || isa<PointerType>(V->getType())) && 1193 "SrcValue is not a pointer?"); 1194 1195 FoldingSetNodeID ID; 1196 AddNodeIDNode(ID, ISD::SRCVALUE, getVTList(MVT::Other), 0, 0); 1197 ID.AddPointer(V); 1198 1199 void *IP = 0; 1200 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1201 return SDValue(E, 0); 1202 1203 SDNode *N = NodeAllocator.Allocate<SrcValueSDNode>(); 1204 new (N) SrcValueSDNode(V); 1205 CSEMap.InsertNode(N, IP); 1206 AllNodes.push_back(N); 1207 return SDValue(N, 0); 1208} 1209 1210SDValue SelectionDAG::getMemOperand(const MachineMemOperand &MO) { 1211#ifndef NDEBUG 1212 const Value *v = MO.getValue(); 1213 assert((!v || isa<PointerType>(v->getType())) && 1214 "SrcValue is not a pointer?"); 1215#endif 1216 1217 FoldingSetNodeID ID; 1218 AddNodeIDNode(ID, ISD::MEMOPERAND, getVTList(MVT::Other), 0, 0); 1219 MO.Profile(ID); 1220 1221 void *IP = 0; 1222 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1223 return SDValue(E, 0); 1224 1225 SDNode *N = NodeAllocator.Allocate<MemOperandSDNode>(); 1226 new (N) MemOperandSDNode(MO); 1227 CSEMap.InsertNode(N, IP); 1228 AllNodes.push_back(N); 1229 return SDValue(N, 0); 1230} 1231 1232/// getShiftAmountOperand - Return the specified value casted to 1233/// the target's desired shift amount type. 1234SDValue SelectionDAG::getShiftAmountOperand(SDValue Op) { 1235 MVT OpTy = Op.getValueType(); 1236 MVT ShTy = TLI.getShiftAmountTy(); 1237 if (OpTy == ShTy || OpTy.isVector()) return Op; 1238 1239 ISD::NodeType Opcode = OpTy.bitsGT(ShTy) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; 1240 return getNode(Opcode, Op.getDebugLoc(), ShTy, Op); 1241} 1242 1243/// CreateStackTemporary - Create a stack temporary, suitable for holding the 1244/// specified value type. 1245SDValue SelectionDAG::CreateStackTemporary(MVT VT, unsigned minAlign) { 1246 MachineFrameInfo *FrameInfo = getMachineFunction().getFrameInfo(); 1247 unsigned ByteSize = VT.getStoreSizeInBits()/8; 1248 const Type *Ty = VT.getTypeForMVT(); 1249 unsigned StackAlign = 1250 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), minAlign); 1251 1252 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, StackAlign); 1253 return getFrameIndex(FrameIdx, TLI.getPointerTy()); 1254} 1255 1256/// CreateStackTemporary - Create a stack temporary suitable for holding 1257/// either of the specified value types. 1258SDValue SelectionDAG::CreateStackTemporary(MVT VT1, MVT VT2) { 1259 unsigned Bytes = std::max(VT1.getStoreSizeInBits(), 1260 VT2.getStoreSizeInBits())/8; 1261 const Type *Ty1 = VT1.getTypeForMVT(); 1262 const Type *Ty2 = VT2.getTypeForMVT(); 1263 const TargetData *TD = TLI.getTargetData(); 1264 unsigned Align = std::max(TD->getPrefTypeAlignment(Ty1), 1265 TD->getPrefTypeAlignment(Ty2)); 1266 1267 MachineFrameInfo *FrameInfo = getMachineFunction().getFrameInfo(); 1268 int FrameIdx = FrameInfo->CreateStackObject(Bytes, Align); 1269 return getFrameIndex(FrameIdx, TLI.getPointerTy()); 1270} 1271 1272SDValue SelectionDAG::FoldSetCC(MVT VT, SDValue N1, 1273 SDValue N2, ISD::CondCode Cond, DebugLoc dl) { 1274 // These setcc operations always fold. 1275 switch (Cond) { 1276 default: break; 1277 case ISD::SETFALSE: 1278 case ISD::SETFALSE2: return getConstant(0, VT); 1279 case ISD::SETTRUE: 1280 case ISD::SETTRUE2: return getConstant(1, VT); 1281 1282 case ISD::SETOEQ: 1283 case ISD::SETOGT: 1284 case ISD::SETOGE: 1285 case ISD::SETOLT: 1286 case ISD::SETOLE: 1287 case ISD::SETONE: 1288 case ISD::SETO: 1289 case ISD::SETUO: 1290 case ISD::SETUEQ: 1291 case ISD::SETUNE: 1292 assert(!N1.getValueType().isInteger() && "Illegal setcc for integer!"); 1293 break; 1294 } 1295 1296 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode())) { 1297 const APInt &C2 = N2C->getAPIntValue(); 1298 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) { 1299 const APInt &C1 = N1C->getAPIntValue(); 1300 1301 switch (Cond) { 1302 default: assert(0 && "Unknown integer setcc!"); 1303 case ISD::SETEQ: return getConstant(C1 == C2, VT); 1304 case ISD::SETNE: return getConstant(C1 != C2, VT); 1305 case ISD::SETULT: return getConstant(C1.ult(C2), VT); 1306 case ISD::SETUGT: return getConstant(C1.ugt(C2), VT); 1307 case ISD::SETULE: return getConstant(C1.ule(C2), VT); 1308 case ISD::SETUGE: return getConstant(C1.uge(C2), VT); 1309 case ISD::SETLT: return getConstant(C1.slt(C2), VT); 1310 case ISD::SETGT: return getConstant(C1.sgt(C2), VT); 1311 case ISD::SETLE: return getConstant(C1.sle(C2), VT); 1312 case ISD::SETGE: return getConstant(C1.sge(C2), VT); 1313 } 1314 } 1315 } 1316 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.getNode())) { 1317 if (ConstantFPSDNode *N2C = dyn_cast<ConstantFPSDNode>(N2.getNode())) { 1318 // No compile time operations on this type yet. 1319 if (N1C->getValueType(0) == MVT::ppcf128) 1320 return SDValue(); 1321 1322 APFloat::cmpResult R = N1C->getValueAPF().compare(N2C->getValueAPF()); 1323 switch (Cond) { 1324 default: break; 1325 case ISD::SETEQ: if (R==APFloat::cmpUnordered) 1326 return getUNDEF(VT); 1327 // fall through 1328 case ISD::SETOEQ: return getConstant(R==APFloat::cmpEqual, VT); 1329 case ISD::SETNE: if (R==APFloat::cmpUnordered) 1330 return getUNDEF(VT); 1331 // fall through 1332 case ISD::SETONE: return getConstant(R==APFloat::cmpGreaterThan || 1333 R==APFloat::cmpLessThan, VT); 1334 case ISD::SETLT: if (R==APFloat::cmpUnordered) 1335 return getUNDEF(VT); 1336 // fall through 1337 case ISD::SETOLT: return getConstant(R==APFloat::cmpLessThan, VT); 1338 case ISD::SETGT: if (R==APFloat::cmpUnordered) 1339 return getUNDEF(VT); 1340 // fall through 1341 case ISD::SETOGT: return getConstant(R==APFloat::cmpGreaterThan, VT); 1342 case ISD::SETLE: if (R==APFloat::cmpUnordered) 1343 return getUNDEF(VT); 1344 // fall through 1345 case ISD::SETOLE: return getConstant(R==APFloat::cmpLessThan || 1346 R==APFloat::cmpEqual, VT); 1347 case ISD::SETGE: if (R==APFloat::cmpUnordered) 1348 return getUNDEF(VT); 1349 // fall through 1350 case ISD::SETOGE: return getConstant(R==APFloat::cmpGreaterThan || 1351 R==APFloat::cmpEqual, VT); 1352 case ISD::SETO: return getConstant(R!=APFloat::cmpUnordered, VT); 1353 case ISD::SETUO: return getConstant(R==APFloat::cmpUnordered, VT); 1354 case ISD::SETUEQ: return getConstant(R==APFloat::cmpUnordered || 1355 R==APFloat::cmpEqual, VT); 1356 case ISD::SETUNE: return getConstant(R!=APFloat::cmpEqual, VT); 1357 case ISD::SETULT: return getConstant(R==APFloat::cmpUnordered || 1358 R==APFloat::cmpLessThan, VT); 1359 case ISD::SETUGT: return getConstant(R==APFloat::cmpGreaterThan || 1360 R==APFloat::cmpUnordered, VT); 1361 case ISD::SETULE: return getConstant(R!=APFloat::cmpGreaterThan, VT); 1362 case ISD::SETUGE: return getConstant(R!=APFloat::cmpLessThan, VT); 1363 } 1364 } else { 1365 // Ensure that the constant occurs on the RHS. 1366 return getSetCC(dl, VT, N2, N1, ISD::getSetCCSwappedOperands(Cond)); 1367 } 1368 } 1369 1370 // Could not fold it. 1371 return SDValue(); 1372} 1373 1374/// SignBitIsZero - Return true if the sign bit of Op is known to be zero. We 1375/// use this predicate to simplify operations downstream. 1376bool SelectionDAG::SignBitIsZero(SDValue Op, unsigned Depth) const { 1377 unsigned BitWidth = Op.getValueSizeInBits(); 1378 return MaskedValueIsZero(Op, APInt::getSignBit(BitWidth), Depth); 1379} 1380 1381/// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero. We use 1382/// this predicate to simplify operations downstream. Mask is known to be zero 1383/// for bits that V cannot have. 1384bool SelectionDAG::MaskedValueIsZero(SDValue Op, const APInt &Mask, 1385 unsigned Depth) const { 1386 APInt KnownZero, KnownOne; 1387 ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth); 1388 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1389 return (KnownZero & Mask) == Mask; 1390} 1391 1392/// ComputeMaskedBits - Determine which of the bits specified in Mask are 1393/// known to be either zero or one and return them in the KnownZero/KnownOne 1394/// bitsets. This code only analyzes bits in Mask, in order to short-circuit 1395/// processing. 1396void SelectionDAG::ComputeMaskedBits(SDValue Op, const APInt &Mask, 1397 APInt &KnownZero, APInt &KnownOne, 1398 unsigned Depth) const { 1399 unsigned BitWidth = Mask.getBitWidth(); 1400 assert(BitWidth == Op.getValueType().getSizeInBits() && 1401 "Mask size mismatches value type size!"); 1402 1403 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything. 1404 if (Depth == 6 || Mask == 0) 1405 return; // Limit search depth. 1406 1407 APInt KnownZero2, KnownOne2; 1408 1409 switch (Op.getOpcode()) { 1410 case ISD::Constant: 1411 // We know all of the bits for a constant! 1412 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & Mask; 1413 KnownZero = ~KnownOne & Mask; 1414 return; 1415 case ISD::AND: 1416 // If either the LHS or the RHS are Zero, the result is zero. 1417 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1418 ComputeMaskedBits(Op.getOperand(0), Mask & ~KnownZero, 1419 KnownZero2, KnownOne2, Depth+1); 1420 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1421 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1422 1423 // Output known-1 bits are only known if set in both the LHS & RHS. 1424 KnownOne &= KnownOne2; 1425 // Output known-0 are known to be clear if zero in either the LHS | RHS. 1426 KnownZero |= KnownZero2; 1427 return; 1428 case ISD::OR: 1429 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1430 ComputeMaskedBits(Op.getOperand(0), Mask & ~KnownOne, 1431 KnownZero2, KnownOne2, Depth+1); 1432 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1433 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1434 1435 // Output known-0 bits are only known if clear in both the LHS & RHS. 1436 KnownZero &= KnownZero2; 1437 // Output known-1 are known to be set if set in either the LHS | RHS. 1438 KnownOne |= KnownOne2; 1439 return; 1440 case ISD::XOR: { 1441 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1442 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1); 1443 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1444 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1445 1446 // Output known-0 bits are known if clear or set in both the LHS & RHS. 1447 APInt KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 1448 // Output known-1 are known to be set if set in only one of the LHS, RHS. 1449 KnownOne = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 1450 KnownZero = KnownZeroOut; 1451 return; 1452 } 1453 case ISD::MUL: { 1454 APInt Mask2 = APInt::getAllOnesValue(BitWidth); 1455 ComputeMaskedBits(Op.getOperand(1), Mask2, KnownZero, KnownOne, Depth+1); 1456 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero2, KnownOne2, Depth+1); 1457 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1458 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1459 1460 // If low bits are zero in either operand, output low known-0 bits. 1461 // Also compute a conserative estimate for high known-0 bits. 1462 // More trickiness is possible, but this is sufficient for the 1463 // interesting case of alignment computation. 1464 KnownOne.clear(); 1465 unsigned TrailZ = KnownZero.countTrailingOnes() + 1466 KnownZero2.countTrailingOnes(); 1467 unsigned LeadZ = std::max(KnownZero.countLeadingOnes() + 1468 KnownZero2.countLeadingOnes(), 1469 BitWidth) - BitWidth; 1470 1471 TrailZ = std::min(TrailZ, BitWidth); 1472 LeadZ = std::min(LeadZ, BitWidth); 1473 KnownZero = APInt::getLowBitsSet(BitWidth, TrailZ) | 1474 APInt::getHighBitsSet(BitWidth, LeadZ); 1475 KnownZero &= Mask; 1476 return; 1477 } 1478 case ISD::UDIV: { 1479 // For the purposes of computing leading zeros we can conservatively 1480 // treat a udiv as a logical right shift by the power of 2 known to 1481 // be less than the denominator. 1482 APInt AllOnes = APInt::getAllOnesValue(BitWidth); 1483 ComputeMaskedBits(Op.getOperand(0), 1484 AllOnes, KnownZero2, KnownOne2, Depth+1); 1485 unsigned LeadZ = KnownZero2.countLeadingOnes(); 1486 1487 KnownOne2.clear(); 1488 KnownZero2.clear(); 1489 ComputeMaskedBits(Op.getOperand(1), 1490 AllOnes, KnownZero2, KnownOne2, Depth+1); 1491 unsigned RHSUnknownLeadingOnes = KnownOne2.countLeadingZeros(); 1492 if (RHSUnknownLeadingOnes != BitWidth) 1493 LeadZ = std::min(BitWidth, 1494 LeadZ + BitWidth - RHSUnknownLeadingOnes - 1); 1495 1496 KnownZero = APInt::getHighBitsSet(BitWidth, LeadZ) & Mask; 1497 return; 1498 } 1499 case ISD::SELECT: 1500 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero, KnownOne, Depth+1); 1501 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero2, KnownOne2, Depth+1); 1502 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1503 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1504 1505 // Only known if known in both the LHS and RHS. 1506 KnownOne &= KnownOne2; 1507 KnownZero &= KnownZero2; 1508 return; 1509 case ISD::SELECT_CC: 1510 ComputeMaskedBits(Op.getOperand(3), Mask, KnownZero, KnownOne, Depth+1); 1511 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero2, KnownOne2, Depth+1); 1512 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1513 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1514 1515 // Only known if known in both the LHS and RHS. 1516 KnownOne &= KnownOne2; 1517 KnownZero &= KnownZero2; 1518 return; 1519 case ISD::SADDO: 1520 case ISD::UADDO: 1521 case ISD::SSUBO: 1522 case ISD::USUBO: 1523 case ISD::SMULO: 1524 case ISD::UMULO: 1525 if (Op.getResNo() != 1) 1526 return; 1527 // The boolean result conforms to getBooleanContents. Fall through. 1528 case ISD::SETCC: 1529 // If we know the result of a setcc has the top bits zero, use this info. 1530 if (TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent && 1531 BitWidth > 1) 1532 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1); 1533 return; 1534 case ISD::SHL: 1535 // (shl X, C1) & C2 == 0 iff (X & C2 >>u C1) == 0 1536 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1537 unsigned ShAmt = SA->getZExtValue(); 1538 1539 // If the shift count is an invalid immediate, don't do anything. 1540 if (ShAmt >= BitWidth) 1541 return; 1542 1543 ComputeMaskedBits(Op.getOperand(0), Mask.lshr(ShAmt), 1544 KnownZero, KnownOne, Depth+1); 1545 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1546 KnownZero <<= ShAmt; 1547 KnownOne <<= ShAmt; 1548 // low bits known zero. 1549 KnownZero |= APInt::getLowBitsSet(BitWidth, ShAmt); 1550 } 1551 return; 1552 case ISD::SRL: 1553 // (ushr X, C1) & C2 == 0 iff (-1 >> C1) & C2 == 0 1554 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1555 unsigned ShAmt = SA->getZExtValue(); 1556 1557 // If the shift count is an invalid immediate, don't do anything. 1558 if (ShAmt >= BitWidth) 1559 return; 1560 1561 ComputeMaskedBits(Op.getOperand(0), (Mask << ShAmt), 1562 KnownZero, KnownOne, Depth+1); 1563 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1564 KnownZero = KnownZero.lshr(ShAmt); 1565 KnownOne = KnownOne.lshr(ShAmt); 1566 1567 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt) & Mask; 1568 KnownZero |= HighBits; // High bits known zero. 1569 } 1570 return; 1571 case ISD::SRA: 1572 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1573 unsigned ShAmt = SA->getZExtValue(); 1574 1575 // If the shift count is an invalid immediate, don't do anything. 1576 if (ShAmt >= BitWidth) 1577 return; 1578 1579 APInt InDemandedMask = (Mask << ShAmt); 1580 // If any of the demanded bits are produced by the sign extension, we also 1581 // demand the input sign bit. 1582 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt) & Mask; 1583 if (HighBits.getBoolValue()) 1584 InDemandedMask |= APInt::getSignBit(BitWidth); 1585 1586 ComputeMaskedBits(Op.getOperand(0), InDemandedMask, KnownZero, KnownOne, 1587 Depth+1); 1588 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1589 KnownZero = KnownZero.lshr(ShAmt); 1590 KnownOne = KnownOne.lshr(ShAmt); 1591 1592 // Handle the sign bits. 1593 APInt SignBit = APInt::getSignBit(BitWidth); 1594 SignBit = SignBit.lshr(ShAmt); // Adjust to where it is now in the mask. 1595 1596 if (KnownZero.intersects(SignBit)) { 1597 KnownZero |= HighBits; // New bits are known zero. 1598 } else if (KnownOne.intersects(SignBit)) { 1599 KnownOne |= HighBits; // New bits are known one. 1600 } 1601 } 1602 return; 1603 case ISD::SIGN_EXTEND_INREG: { 1604 MVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1605 unsigned EBits = EVT.getSizeInBits(); 1606 1607 // Sign extension. Compute the demanded bits in the result that are not 1608 // present in the input. 1609 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - EBits) & Mask; 1610 1611 APInt InSignBit = APInt::getSignBit(EBits); 1612 APInt InputDemandedBits = Mask & APInt::getLowBitsSet(BitWidth, EBits); 1613 1614 // If the sign extended bits are demanded, we know that the sign 1615 // bit is demanded. 1616 InSignBit.zext(BitWidth); 1617 if (NewBits.getBoolValue()) 1618 InputDemandedBits |= InSignBit; 1619 1620 ComputeMaskedBits(Op.getOperand(0), InputDemandedBits, 1621 KnownZero, KnownOne, Depth+1); 1622 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1623 1624 // If the sign bit of the input is known set or clear, then we know the 1625 // top bits of the result. 1626 if (KnownZero.intersects(InSignBit)) { // Input sign bit known clear 1627 KnownZero |= NewBits; 1628 KnownOne &= ~NewBits; 1629 } else if (KnownOne.intersects(InSignBit)) { // Input sign bit known set 1630 KnownOne |= NewBits; 1631 KnownZero &= ~NewBits; 1632 } else { // Input sign bit unknown 1633 KnownZero &= ~NewBits; 1634 KnownOne &= ~NewBits; 1635 } 1636 return; 1637 } 1638 case ISD::CTTZ: 1639 case ISD::CTLZ: 1640 case ISD::CTPOP: { 1641 unsigned LowBits = Log2_32(BitWidth)+1; 1642 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - LowBits); 1643 KnownOne.clear(); 1644 return; 1645 } 1646 case ISD::LOAD: { 1647 if (ISD::isZEXTLoad(Op.getNode())) { 1648 LoadSDNode *LD = cast<LoadSDNode>(Op); 1649 MVT VT = LD->getMemoryVT(); 1650 unsigned MemBits = VT.getSizeInBits(); 1651 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits) & Mask; 1652 } 1653 return; 1654 } 1655 case ISD::ZERO_EXTEND: { 1656 MVT InVT = Op.getOperand(0).getValueType(); 1657 unsigned InBits = InVT.getSizeInBits(); 1658 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - InBits) & Mask; 1659 APInt InMask = Mask; 1660 InMask.trunc(InBits); 1661 KnownZero.trunc(InBits); 1662 KnownOne.trunc(InBits); 1663 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1664 KnownZero.zext(BitWidth); 1665 KnownOne.zext(BitWidth); 1666 KnownZero |= NewBits; 1667 return; 1668 } 1669 case ISD::SIGN_EXTEND: { 1670 MVT InVT = Op.getOperand(0).getValueType(); 1671 unsigned InBits = InVT.getSizeInBits(); 1672 APInt InSignBit = APInt::getSignBit(InBits); 1673 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - InBits) & Mask; 1674 APInt InMask = Mask; 1675 InMask.trunc(InBits); 1676 1677 // If any of the sign extended bits are demanded, we know that the sign 1678 // bit is demanded. Temporarily set this bit in the mask for our callee. 1679 if (NewBits.getBoolValue()) 1680 InMask |= InSignBit; 1681 1682 KnownZero.trunc(InBits); 1683 KnownOne.trunc(InBits); 1684 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1685 1686 // Note if the sign bit is known to be zero or one. 1687 bool SignBitKnownZero = KnownZero.isNegative(); 1688 bool SignBitKnownOne = KnownOne.isNegative(); 1689 assert(!(SignBitKnownZero && SignBitKnownOne) && 1690 "Sign bit can't be known to be both zero and one!"); 1691 1692 // If the sign bit wasn't actually demanded by our caller, we don't 1693 // want it set in the KnownZero and KnownOne result values. Reset the 1694 // mask and reapply it to the result values. 1695 InMask = Mask; 1696 InMask.trunc(InBits); 1697 KnownZero &= InMask; 1698 KnownOne &= InMask; 1699 1700 KnownZero.zext(BitWidth); 1701 KnownOne.zext(BitWidth); 1702 1703 // If the sign bit is known zero or one, the top bits match. 1704 if (SignBitKnownZero) 1705 KnownZero |= NewBits; 1706 else if (SignBitKnownOne) 1707 KnownOne |= NewBits; 1708 return; 1709 } 1710 case ISD::ANY_EXTEND: { 1711 MVT InVT = Op.getOperand(0).getValueType(); 1712 unsigned InBits = InVT.getSizeInBits(); 1713 APInt InMask = Mask; 1714 InMask.trunc(InBits); 1715 KnownZero.trunc(InBits); 1716 KnownOne.trunc(InBits); 1717 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1718 KnownZero.zext(BitWidth); 1719 KnownOne.zext(BitWidth); 1720 return; 1721 } 1722 case ISD::TRUNCATE: { 1723 MVT InVT = Op.getOperand(0).getValueType(); 1724 unsigned InBits = InVT.getSizeInBits(); 1725 APInt InMask = Mask; 1726 InMask.zext(InBits); 1727 KnownZero.zext(InBits); 1728 KnownOne.zext(InBits); 1729 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1730 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1731 KnownZero.trunc(BitWidth); 1732 KnownOne.trunc(BitWidth); 1733 break; 1734 } 1735 case ISD::AssertZext: { 1736 MVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1737 APInt InMask = APInt::getLowBitsSet(BitWidth, VT.getSizeInBits()); 1738 ComputeMaskedBits(Op.getOperand(0), Mask & InMask, KnownZero, 1739 KnownOne, Depth+1); 1740 KnownZero |= (~InMask) & Mask; 1741 return; 1742 } 1743 case ISD::FGETSIGN: 1744 // All bits are zero except the low bit. 1745 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - 1); 1746 return; 1747 1748 case ISD::SUB: { 1749 if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) { 1750 // We know that the top bits of C-X are clear if X contains less bits 1751 // than C (i.e. no wrap-around can happen). For example, 20-X is 1752 // positive if we can prove that X is >= 0 and < 16. 1753 if (CLHS->getAPIntValue().isNonNegative()) { 1754 unsigned NLZ = (CLHS->getAPIntValue()+1).countLeadingZeros(); 1755 // NLZ can't be BitWidth with no sign bit 1756 APInt MaskV = APInt::getHighBitsSet(BitWidth, NLZ+1); 1757 ComputeMaskedBits(Op.getOperand(1), MaskV, KnownZero2, KnownOne2, 1758 Depth+1); 1759 1760 // If all of the MaskV bits are known to be zero, then we know the 1761 // output top bits are zero, because we now know that the output is 1762 // from [0-C]. 1763 if ((KnownZero2 & MaskV) == MaskV) { 1764 unsigned NLZ2 = CLHS->getAPIntValue().countLeadingZeros(); 1765 // Top bits known zero. 1766 KnownZero = APInt::getHighBitsSet(BitWidth, NLZ2) & Mask; 1767 } 1768 } 1769 } 1770 } 1771 // fall through 1772 case ISD::ADD: { 1773 // Output known-0 bits are known if clear or set in both the low clear bits 1774 // common to both LHS & RHS. For example, 8+(X<<3) is known to have the 1775 // low 3 bits clear. 1776 APInt Mask2 = APInt::getLowBitsSet(BitWidth, Mask.countTrailingOnes()); 1777 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero2, KnownOne2, Depth+1); 1778 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1779 unsigned KnownZeroOut = KnownZero2.countTrailingOnes(); 1780 1781 ComputeMaskedBits(Op.getOperand(1), Mask2, KnownZero2, KnownOne2, Depth+1); 1782 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1783 KnownZeroOut = std::min(KnownZeroOut, 1784 KnownZero2.countTrailingOnes()); 1785 1786 KnownZero |= APInt::getLowBitsSet(BitWidth, KnownZeroOut); 1787 return; 1788 } 1789 case ISD::SREM: 1790 if (ConstantSDNode *Rem = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1791 const APInt &RA = Rem->getAPIntValue(); 1792 if (RA.isPowerOf2() || (-RA).isPowerOf2()) { 1793 APInt LowBits = RA.isStrictlyPositive() ? (RA - 1) : ~RA; 1794 APInt Mask2 = LowBits | APInt::getSignBit(BitWidth); 1795 ComputeMaskedBits(Op.getOperand(0), Mask2,KnownZero2,KnownOne2,Depth+1); 1796 1797 // If the sign bit of the first operand is zero, the sign bit of 1798 // the result is zero. If the first operand has no one bits below 1799 // the second operand's single 1 bit, its sign will be zero. 1800 if (KnownZero2[BitWidth-1] || ((KnownZero2 & LowBits) == LowBits)) 1801 KnownZero2 |= ~LowBits; 1802 1803 KnownZero |= KnownZero2 & Mask; 1804 1805 assert((KnownZero & KnownOne) == 0&&"Bits known to be one AND zero?"); 1806 } 1807 } 1808 return; 1809 case ISD::UREM: { 1810 if (ConstantSDNode *Rem = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1811 const APInt &RA = Rem->getAPIntValue(); 1812 if (RA.isPowerOf2()) { 1813 APInt LowBits = (RA - 1); 1814 APInt Mask2 = LowBits & Mask; 1815 KnownZero |= ~LowBits & Mask; 1816 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero, KnownOne,Depth+1); 1817 assert((KnownZero & KnownOne) == 0&&"Bits known to be one AND zero?"); 1818 break; 1819 } 1820 } 1821 1822 // Since the result is less than or equal to either operand, any leading 1823 // zero bits in either operand must also exist in the result. 1824 APInt AllOnes = APInt::getAllOnesValue(BitWidth); 1825 ComputeMaskedBits(Op.getOperand(0), AllOnes, KnownZero, KnownOne, 1826 Depth+1); 1827 ComputeMaskedBits(Op.getOperand(1), AllOnes, KnownZero2, KnownOne2, 1828 Depth+1); 1829 1830 uint32_t Leaders = std::max(KnownZero.countLeadingOnes(), 1831 KnownZero2.countLeadingOnes()); 1832 KnownOne.clear(); 1833 KnownZero = APInt::getHighBitsSet(BitWidth, Leaders) & Mask; 1834 return; 1835 } 1836 default: 1837 // Allow the target to implement this method for its nodes. 1838 if (Op.getOpcode() >= ISD::BUILTIN_OP_END) { 1839 case ISD::INTRINSIC_WO_CHAIN: 1840 case ISD::INTRINSIC_W_CHAIN: 1841 case ISD::INTRINSIC_VOID: 1842 TLI.computeMaskedBitsForTargetNode(Op, Mask, KnownZero, KnownOne, *this); 1843 } 1844 return; 1845 } 1846} 1847 1848/// ComputeNumSignBits - Return the number of times the sign bit of the 1849/// register is replicated into the other bits. We know that at least 1 bit 1850/// is always equal to the sign bit (itself), but other cases can give us 1851/// information. For example, immediately after an "SRA X, 2", we know that 1852/// the top 3 bits are all equal to each other, so we return 3. 1853unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, unsigned Depth) const{ 1854 MVT VT = Op.getValueType(); 1855 assert(VT.isInteger() && "Invalid VT!"); 1856 unsigned VTBits = VT.getSizeInBits(); 1857 unsigned Tmp, Tmp2; 1858 unsigned FirstAnswer = 1; 1859 1860 if (Depth == 6) 1861 return 1; // Limit search depth. 1862 1863 switch (Op.getOpcode()) { 1864 default: break; 1865 case ISD::AssertSext: 1866 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); 1867 return VTBits-Tmp+1; 1868 case ISD::AssertZext: 1869 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); 1870 return VTBits-Tmp; 1871 1872 case ISD::Constant: { 1873 const APInt &Val = cast<ConstantSDNode>(Op)->getAPIntValue(); 1874 // If negative, return # leading ones. 1875 if (Val.isNegative()) 1876 return Val.countLeadingOnes(); 1877 1878 // Return # leading zeros. 1879 return Val.countLeadingZeros(); 1880 } 1881 1882 case ISD::SIGN_EXTEND: 1883 Tmp = VTBits-Op.getOperand(0).getValueType().getSizeInBits(); 1884 return ComputeNumSignBits(Op.getOperand(0), Depth+1) + Tmp; 1885 1886 case ISD::SIGN_EXTEND_INREG: 1887 // Max of the input and what this extends. 1888 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); 1889 Tmp = VTBits-Tmp+1; 1890 1891 Tmp2 = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1892 return std::max(Tmp, Tmp2); 1893 1894 case ISD::SRA: 1895 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1896 // SRA X, C -> adds C sign bits. 1897 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1898 Tmp += C->getZExtValue(); 1899 if (Tmp > VTBits) Tmp = VTBits; 1900 } 1901 return Tmp; 1902 case ISD::SHL: 1903 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1904 // shl destroys sign bits. 1905 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1906 if (C->getZExtValue() >= VTBits || // Bad shift. 1907 C->getZExtValue() >= Tmp) break; // Shifted all sign bits out. 1908 return Tmp - C->getZExtValue(); 1909 } 1910 break; 1911 case ISD::AND: 1912 case ISD::OR: 1913 case ISD::XOR: // NOT is handled here. 1914 // Logical binary ops preserve the number of sign bits at the worst. 1915 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1916 if (Tmp != 1) { 1917 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 1918 FirstAnswer = std::min(Tmp, Tmp2); 1919 // We computed what we know about the sign bits as our first 1920 // answer. Now proceed to the generic code that uses 1921 // ComputeMaskedBits, and pick whichever answer is better. 1922 } 1923 break; 1924 1925 case ISD::SELECT: 1926 Tmp = ComputeNumSignBits(Op.getOperand(1), Depth+1); 1927 if (Tmp == 1) return 1; // Early out. 1928 Tmp2 = ComputeNumSignBits(Op.getOperand(2), Depth+1); 1929 return std::min(Tmp, Tmp2); 1930 1931 case ISD::SADDO: 1932 case ISD::UADDO: 1933 case ISD::SSUBO: 1934 case ISD::USUBO: 1935 case ISD::SMULO: 1936 case ISD::UMULO: 1937 if (Op.getResNo() != 1) 1938 break; 1939 // The boolean result conforms to getBooleanContents. Fall through. 1940 case ISD::SETCC: 1941 // If setcc returns 0/-1, all bits are sign bits. 1942 if (TLI.getBooleanContents() == 1943 TargetLowering::ZeroOrNegativeOneBooleanContent) 1944 return VTBits; 1945 break; 1946 case ISD::ROTL: 1947 case ISD::ROTR: 1948 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1949 unsigned RotAmt = C->getZExtValue() & (VTBits-1); 1950 1951 // Handle rotate right by N like a rotate left by 32-N. 1952 if (Op.getOpcode() == ISD::ROTR) 1953 RotAmt = (VTBits-RotAmt) & (VTBits-1); 1954 1955 // If we aren't rotating out all of the known-in sign bits, return the 1956 // number that are left. This handles rotl(sext(x), 1) for example. 1957 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1958 if (Tmp > RotAmt+1) return Tmp-RotAmt; 1959 } 1960 break; 1961 case ISD::ADD: 1962 // Add can have at most one carry bit. Thus we know that the output 1963 // is, at worst, one more bit than the inputs. 1964 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1965 if (Tmp == 1) return 1; // Early out. 1966 1967 // Special case decrementing a value (ADD X, -1): 1968 if (ConstantSDNode *CRHS = dyn_cast<ConstantSDNode>(Op.getOperand(1))) 1969 if (CRHS->isAllOnesValue()) { 1970 APInt KnownZero, KnownOne; 1971 APInt Mask = APInt::getAllOnesValue(VTBits); 1972 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1); 1973 1974 // If the input is known to be 0 or 1, the output is 0/-1, which is all 1975 // sign bits set. 1976 if ((KnownZero | APInt(VTBits, 1)) == Mask) 1977 return VTBits; 1978 1979 // If we are subtracting one from a positive number, there is no carry 1980 // out of the result. 1981 if (KnownZero.isNegative()) 1982 return Tmp; 1983 } 1984 1985 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 1986 if (Tmp2 == 1) return 1; 1987 return std::min(Tmp, Tmp2)-1; 1988 break; 1989 1990 case ISD::SUB: 1991 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 1992 if (Tmp2 == 1) return 1; 1993 1994 // Handle NEG. 1995 if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) 1996 if (CLHS->isNullValue()) { 1997 APInt KnownZero, KnownOne; 1998 APInt Mask = APInt::getAllOnesValue(VTBits); 1999 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 2000 // If the input is known to be 0 or 1, the output is 0/-1, which is all 2001 // sign bits set. 2002 if ((KnownZero | APInt(VTBits, 1)) == Mask) 2003 return VTBits; 2004 2005 // If the input is known to be positive (the sign bit is known clear), 2006 // the output of the NEG has the same number of sign bits as the input. 2007 if (KnownZero.isNegative()) 2008 return Tmp2; 2009 2010 // Otherwise, we treat this like a SUB. 2011 } 2012 2013 // Sub can have at most one carry bit. Thus we know that the output 2014 // is, at worst, one more bit than the inputs. 2015 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 2016 if (Tmp == 1) return 1; // Early out. 2017 return std::min(Tmp, Tmp2)-1; 2018 break; 2019 case ISD::TRUNCATE: 2020 // FIXME: it's tricky to do anything useful for this, but it is an important 2021 // case for targets like X86. 2022 break; 2023 } 2024 2025 // Handle LOADX separately here. EXTLOAD case will fallthrough. 2026 if (Op.getOpcode() == ISD::LOAD) { 2027 LoadSDNode *LD = cast<LoadSDNode>(Op); 2028 unsigned ExtType = LD->getExtensionType(); 2029 switch (ExtType) { 2030 default: break; 2031 case ISD::SEXTLOAD: // '17' bits known 2032 Tmp = LD->getMemoryVT().getSizeInBits(); 2033 return VTBits-Tmp+1; 2034 case ISD::ZEXTLOAD: // '16' bits known 2035 Tmp = LD->getMemoryVT().getSizeInBits(); 2036 return VTBits-Tmp; 2037 } 2038 } 2039 2040 // Allow the target to implement this method for its nodes. 2041 if (Op.getOpcode() >= ISD::BUILTIN_OP_END || 2042 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 2043 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 2044 Op.getOpcode() == ISD::INTRINSIC_VOID) { 2045 unsigned NumBits = TLI.ComputeNumSignBitsForTargetNode(Op, Depth); 2046 if (NumBits > 1) FirstAnswer = std::max(FirstAnswer, NumBits); 2047 } 2048 2049 // Finally, if we can prove that the top bits of the result are 0's or 1's, 2050 // use this information. 2051 APInt KnownZero, KnownOne; 2052 APInt Mask = APInt::getAllOnesValue(VTBits); 2053 ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth); 2054 2055 if (KnownZero.isNegative()) { // sign bit is 0 2056 Mask = KnownZero; 2057 } else if (KnownOne.isNegative()) { // sign bit is 1; 2058 Mask = KnownOne; 2059 } else { 2060 // Nothing known. 2061 return FirstAnswer; 2062 } 2063 2064 // Okay, we know that the sign bit in Mask is set. Use CLZ to determine 2065 // the number of identical bits in the top of the input value. 2066 Mask = ~Mask; 2067 Mask <<= Mask.getBitWidth()-VTBits; 2068 // Return # leading zeros. We use 'min' here in case Val was zero before 2069 // shifting. We don't want to return '64' as for an i32 "0". 2070 return std::max(FirstAnswer, std::min(VTBits, Mask.countLeadingZeros())); 2071} 2072 2073 2074bool SelectionDAG::isVerifiedDebugInfoDesc(SDValue Op) const { 2075 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op); 2076 if (!GA) return false; 2077 if (GA->getOffset() != 0) return false; 2078 GlobalVariable *GV = dyn_cast<GlobalVariable>(GA->getGlobal()); 2079 if (!GV) return false; 2080 MachineModuleInfo *MMI = getMachineModuleInfo(); 2081 return MMI && MMI->hasDebugInfo(); 2082} 2083 2084 2085/// getShuffleScalarElt - Returns the scalar element that will make up the ith 2086/// element of the result of the vector shuffle. 2087SDValue SelectionDAG::getShuffleScalarElt(const SDNode *N, unsigned i) { 2088 MVT VT = N->getValueType(0); 2089 DebugLoc dl = N->getDebugLoc(); 2090 SDValue PermMask = N->getOperand(2); 2091 SDValue Idx = PermMask.getOperand(i); 2092 if (Idx.getOpcode() == ISD::UNDEF) 2093 return getUNDEF(VT.getVectorElementType()); 2094 unsigned Index = cast<ConstantSDNode>(Idx)->getZExtValue(); 2095 unsigned NumElems = PermMask.getNumOperands(); 2096 SDValue V = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1); 2097 Index %= NumElems; 2098 2099 if (V.getOpcode() == ISD::BIT_CONVERT) { 2100 V = V.getOperand(0); 2101 MVT VVT = V.getValueType(); 2102 if (!VVT.isVector() || VVT.getVectorNumElements() != NumElems) 2103 return SDValue(); 2104 } 2105 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) 2106 return (Index == 0) ? V.getOperand(0) 2107 : getUNDEF(VT.getVectorElementType()); 2108 if (V.getOpcode() == ISD::BUILD_VECTOR) 2109 return V.getOperand(Index); 2110 if (V.getOpcode() == ISD::VECTOR_SHUFFLE) 2111 return getShuffleScalarElt(V.getNode(), Index); 2112 return SDValue(); 2113} 2114 2115 2116/// getNode - Gets or creates the specified node. 2117/// 2118SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT) { 2119 FoldingSetNodeID ID; 2120 AddNodeIDNode(ID, Opcode, getVTList(VT), 0, 0); 2121 void *IP = 0; 2122 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2123 return SDValue(E, 0); 2124 SDNode *N = NodeAllocator.Allocate<SDNode>(); 2125 new (N) SDNode(Opcode, DL, getVTList(VT)); 2126 CSEMap.InsertNode(N, IP); 2127 2128 AllNodes.push_back(N); 2129#ifndef NDEBUG 2130 VerifyNode(N); 2131#endif 2132 return SDValue(N, 0); 2133} 2134 2135SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, 2136 MVT VT, SDValue Operand) { 2137 // Constant fold unary operations with an integer constant operand. 2138 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Operand.getNode())) { 2139 const APInt &Val = C->getAPIntValue(); 2140 unsigned BitWidth = VT.getSizeInBits(); 2141 switch (Opcode) { 2142 default: break; 2143 case ISD::SIGN_EXTEND: 2144 return getConstant(APInt(Val).sextOrTrunc(BitWidth), VT); 2145 case ISD::ANY_EXTEND: 2146 case ISD::ZERO_EXTEND: 2147 case ISD::TRUNCATE: 2148 return getConstant(APInt(Val).zextOrTrunc(BitWidth), VT); 2149 case ISD::UINT_TO_FP: 2150 case ISD::SINT_TO_FP: { 2151 const uint64_t zero[] = {0, 0}; 2152 // No compile time operations on this type. 2153 if (VT==MVT::ppcf128) 2154 break; 2155 APFloat apf = APFloat(APInt(BitWidth, 2, zero)); 2156 (void)apf.convertFromAPInt(Val, 2157 Opcode==ISD::SINT_TO_FP, 2158 APFloat::rmNearestTiesToEven); 2159 return getConstantFP(apf, VT); 2160 } 2161 case ISD::BIT_CONVERT: 2162 if (VT == MVT::f32 && C->getValueType(0) == MVT::i32) 2163 return getConstantFP(Val.bitsToFloat(), VT); 2164 else if (VT == MVT::f64 && C->getValueType(0) == MVT::i64) 2165 return getConstantFP(Val.bitsToDouble(), VT); 2166 break; 2167 case ISD::BSWAP: 2168 return getConstant(Val.byteSwap(), VT); 2169 case ISD::CTPOP: 2170 return getConstant(Val.countPopulation(), VT); 2171 case ISD::CTLZ: 2172 return getConstant(Val.countLeadingZeros(), VT); 2173 case ISD::CTTZ: 2174 return getConstant(Val.countTrailingZeros(), VT); 2175 } 2176 } 2177 2178 // Constant fold unary operations with a floating point constant operand. 2179 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Operand.getNode())) { 2180 APFloat V = C->getValueAPF(); // make copy 2181 if (VT != MVT::ppcf128 && Operand.getValueType() != MVT::ppcf128) { 2182 switch (Opcode) { 2183 case ISD::FNEG: 2184 V.changeSign(); 2185 return getConstantFP(V, VT); 2186 case ISD::FABS: 2187 V.clearSign(); 2188 return getConstantFP(V, VT); 2189 case ISD::FP_ROUND: 2190 case ISD::FP_EXTEND: { 2191 bool ignored; 2192 // This can return overflow, underflow, or inexact; we don't care. 2193 // FIXME need to be more flexible about rounding mode. 2194 (void)V.convert(*MVTToAPFloatSemantics(VT), 2195 APFloat::rmNearestTiesToEven, &ignored); 2196 return getConstantFP(V, VT); 2197 } 2198 case ISD::FP_TO_SINT: 2199 case ISD::FP_TO_UINT: { 2200 integerPart x; 2201 bool ignored; 2202 assert(integerPartWidth >= 64); 2203 // FIXME need to be more flexible about rounding mode. 2204 APFloat::opStatus s = V.convertToInteger(&x, 64U, 2205 Opcode==ISD::FP_TO_SINT, 2206 APFloat::rmTowardZero, &ignored); 2207 if (s==APFloat::opInvalidOp) // inexact is OK, in fact usual 2208 break; 2209 return getConstant(x, VT); 2210 } 2211 case ISD::BIT_CONVERT: 2212 if (VT == MVT::i32 && C->getValueType(0) == MVT::f32) 2213 return getConstant((uint32_t)V.bitcastToAPInt().getZExtValue(), VT); 2214 else if (VT == MVT::i64 && C->getValueType(0) == MVT::f64) 2215 return getConstant(V.bitcastToAPInt().getZExtValue(), VT); 2216 break; 2217 } 2218 } 2219 } 2220 2221 unsigned OpOpcode = Operand.getNode()->getOpcode(); 2222 switch (Opcode) { 2223 case ISD::TokenFactor: 2224 case ISD::MERGE_VALUES: 2225 case ISD::CONCAT_VECTORS: 2226 return Operand; // Factor, merge or concat of one node? No need. 2227 case ISD::FP_ROUND: assert(0 && "Invalid method to make FP_ROUND node"); 2228 case ISD::FP_EXTEND: 2229 assert(VT.isFloatingPoint() && 2230 Operand.getValueType().isFloatingPoint() && "Invalid FP cast!"); 2231 if (Operand.getValueType() == VT) return Operand; // noop conversion. 2232 if (Operand.getOpcode() == ISD::UNDEF) 2233 return getUNDEF(VT); 2234 break; 2235 case ISD::SIGN_EXTEND: 2236 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2237 "Invalid SIGN_EXTEND!"); 2238 if (Operand.getValueType() == VT) return Operand; // noop extension 2239 assert(Operand.getValueType().bitsLT(VT) 2240 && "Invalid sext node, dst < src!"); 2241 if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND) 2242 return getNode(OpOpcode, DL, VT, Operand.getNode()->getOperand(0)); 2243 break; 2244 case ISD::ZERO_EXTEND: 2245 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2246 "Invalid ZERO_EXTEND!"); 2247 if (Operand.getValueType() == VT) return Operand; // noop extension 2248 assert(Operand.getValueType().bitsLT(VT) 2249 && "Invalid zext node, dst < src!"); 2250 if (OpOpcode == ISD::ZERO_EXTEND) // (zext (zext x)) -> (zext x) 2251 return getNode(ISD::ZERO_EXTEND, DL, VT, 2252 Operand.getNode()->getOperand(0)); 2253 break; 2254 case ISD::ANY_EXTEND: 2255 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2256 "Invalid ANY_EXTEND!"); 2257 if (Operand.getValueType() == VT) return Operand; // noop extension 2258 assert(Operand.getValueType().bitsLT(VT) 2259 && "Invalid anyext node, dst < src!"); 2260 if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND) 2261 // (ext (zext x)) -> (zext x) and (ext (sext x)) -> (sext x) 2262 return getNode(OpOpcode, DL, VT, Operand.getNode()->getOperand(0)); 2263 break; 2264 case ISD::TRUNCATE: 2265 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2266 "Invalid TRUNCATE!"); 2267 if (Operand.getValueType() == VT) return Operand; // noop truncate 2268 assert(Operand.getValueType().bitsGT(VT) 2269 && "Invalid truncate node, src < dst!"); 2270 if (OpOpcode == ISD::TRUNCATE) 2271 return getNode(ISD::TRUNCATE, DL, VT, Operand.getNode()->getOperand(0)); 2272 else if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND || 2273 OpOpcode == ISD::ANY_EXTEND) { 2274 // If the source is smaller than the dest, we still need an extend. 2275 if (Operand.getNode()->getOperand(0).getValueType().bitsLT(VT)) 2276 return getNode(OpOpcode, DL, VT, Operand.getNode()->getOperand(0)); 2277 else if (Operand.getNode()->getOperand(0).getValueType().bitsGT(VT)) 2278 return getNode(ISD::TRUNCATE, DL, VT, Operand.getNode()->getOperand(0)); 2279 else 2280 return Operand.getNode()->getOperand(0); 2281 } 2282 break; 2283 case ISD::BIT_CONVERT: 2284 // Basic sanity checking. 2285 assert(VT.getSizeInBits() == Operand.getValueType().getSizeInBits() 2286 && "Cannot BIT_CONVERT between types of different sizes!"); 2287 if (VT == Operand.getValueType()) return Operand; // noop conversion. 2288 if (OpOpcode == ISD::BIT_CONVERT) // bitconv(bitconv(x)) -> bitconv(x) 2289 return getNode(ISD::BIT_CONVERT, DL, VT, Operand.getOperand(0)); 2290 if (OpOpcode == ISD::UNDEF) 2291 return getUNDEF(VT); 2292 break; 2293 case ISD::SCALAR_TO_VECTOR: 2294 assert(VT.isVector() && !Operand.getValueType().isVector() && 2295 (VT.getVectorElementType() == Operand.getValueType() || 2296 (VT.getVectorElementType().isInteger() && 2297 Operand.getValueType().isInteger() && 2298 VT.getVectorElementType().bitsLE(Operand.getValueType()))) && 2299 "Illegal SCALAR_TO_VECTOR node!"); 2300 if (OpOpcode == ISD::UNDEF) 2301 return getUNDEF(VT); 2302 // scalar_to_vector(extract_vector_elt V, 0) -> V, top bits are undefined. 2303 if (OpOpcode == ISD::EXTRACT_VECTOR_ELT && 2304 isa<ConstantSDNode>(Operand.getOperand(1)) && 2305 Operand.getConstantOperandVal(1) == 0 && 2306 Operand.getOperand(0).getValueType() == VT) 2307 return Operand.getOperand(0); 2308 break; 2309 case ISD::FNEG: 2310 // -(X-Y) -> (Y-X) is unsafe because when X==Y, -0.0 != +0.0 2311 if (UnsafeFPMath && OpOpcode == ISD::FSUB) 2312 return getNode(ISD::FSUB, DL, VT, Operand.getNode()->getOperand(1), 2313 Operand.getNode()->getOperand(0)); 2314 if (OpOpcode == ISD::FNEG) // --X -> X 2315 return Operand.getNode()->getOperand(0); 2316 break; 2317 case ISD::FABS: 2318 if (OpOpcode == ISD::FNEG) // abs(-X) -> abs(X) 2319 return getNode(ISD::FABS, DL, VT, Operand.getNode()->getOperand(0)); 2320 break; 2321 } 2322 2323 SDNode *N; 2324 SDVTList VTs = getVTList(VT); 2325 if (VT != MVT::Flag) { // Don't CSE flag producing nodes 2326 FoldingSetNodeID ID; 2327 SDValue Ops[1] = { Operand }; 2328 AddNodeIDNode(ID, Opcode, VTs, Ops, 1); 2329 void *IP = 0; 2330 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2331 return SDValue(E, 0); 2332 N = NodeAllocator.Allocate<UnarySDNode>(); 2333 new (N) UnarySDNode(Opcode, DL, VTs, Operand); 2334 CSEMap.InsertNode(N, IP); 2335 } else { 2336 N = NodeAllocator.Allocate<UnarySDNode>(); 2337 new (N) UnarySDNode(Opcode, DL, VTs, Operand); 2338 } 2339 2340 AllNodes.push_back(N); 2341#ifndef NDEBUG 2342 VerifyNode(N); 2343#endif 2344 return SDValue(N, 0); 2345} 2346 2347SDValue SelectionDAG::FoldConstantArithmetic(unsigned Opcode, 2348 MVT VT, 2349 ConstantSDNode *Cst1, 2350 ConstantSDNode *Cst2) { 2351 const APInt &C1 = Cst1->getAPIntValue(), &C2 = Cst2->getAPIntValue(); 2352 2353 switch (Opcode) { 2354 case ISD::ADD: return getConstant(C1 + C2, VT); 2355 case ISD::SUB: return getConstant(C1 - C2, VT); 2356 case ISD::MUL: return getConstant(C1 * C2, VT); 2357 case ISD::UDIV: 2358 if (C2.getBoolValue()) return getConstant(C1.udiv(C2), VT); 2359 break; 2360 case ISD::UREM: 2361 if (C2.getBoolValue()) return getConstant(C1.urem(C2), VT); 2362 break; 2363 case ISD::SDIV: 2364 if (C2.getBoolValue()) return getConstant(C1.sdiv(C2), VT); 2365 break; 2366 case ISD::SREM: 2367 if (C2.getBoolValue()) return getConstant(C1.srem(C2), VT); 2368 break; 2369 case ISD::AND: return getConstant(C1 & C2, VT); 2370 case ISD::OR: return getConstant(C1 | C2, VT); 2371 case ISD::XOR: return getConstant(C1 ^ C2, VT); 2372 case ISD::SHL: return getConstant(C1 << C2, VT); 2373 case ISD::SRL: return getConstant(C1.lshr(C2), VT); 2374 case ISD::SRA: return getConstant(C1.ashr(C2), VT); 2375 case ISD::ROTL: return getConstant(C1.rotl(C2), VT); 2376 case ISD::ROTR: return getConstant(C1.rotr(C2), VT); 2377 default: break; 2378 } 2379 2380 return SDValue(); 2381} 2382 2383SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, 2384 SDValue N1, SDValue N2) { 2385 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 2386 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 2387 switch (Opcode) { 2388 default: break; 2389 case ISD::TokenFactor: 2390 assert(VT == MVT::Other && N1.getValueType() == MVT::Other && 2391 N2.getValueType() == MVT::Other && "Invalid token factor!"); 2392 // Fold trivial token factors. 2393 if (N1.getOpcode() == ISD::EntryToken) return N2; 2394 if (N2.getOpcode() == ISD::EntryToken) return N1; 2395 if (N1 == N2) return N1; 2396 break; 2397 case ISD::CONCAT_VECTORS: 2398 // A CONCAT_VECTOR with all operands BUILD_VECTOR can be simplified to 2399 // one big BUILD_VECTOR. 2400 if (N1.getOpcode() == ISD::BUILD_VECTOR && 2401 N2.getOpcode() == ISD::BUILD_VECTOR) { 2402 SmallVector<SDValue, 16> Elts(N1.getNode()->op_begin(), N1.getNode()->op_end()); 2403 Elts.insert(Elts.end(), N2.getNode()->op_begin(), N2.getNode()->op_end()); 2404 return getNode(ISD::BUILD_VECTOR, DL, VT, &Elts[0], Elts.size()); 2405 } 2406 break; 2407 case ISD::AND: 2408 assert(VT.isInteger() && N1.getValueType() == N2.getValueType() && 2409 N1.getValueType() == VT && "Binary operator types must match!"); 2410 // (X & 0) -> 0. This commonly occurs when legalizing i64 values, so it's 2411 // worth handling here. 2412 if (N2C && N2C->isNullValue()) 2413 return N2; 2414 if (N2C && N2C->isAllOnesValue()) // X & -1 -> X 2415 return N1; 2416 break; 2417 case ISD::OR: 2418 case ISD::XOR: 2419 case ISD::ADD: 2420 case ISD::SUB: 2421 assert(VT.isInteger() && N1.getValueType() == N2.getValueType() && 2422 N1.getValueType() == VT && "Binary operator types must match!"); 2423 // (X ^|+- 0) -> X. This commonly occurs when legalizing i64 values, so 2424 // it's worth handling here. 2425 if (N2C && N2C->isNullValue()) 2426 return N1; 2427 break; 2428 case ISD::UDIV: 2429 case ISD::UREM: 2430 case ISD::MULHU: 2431 case ISD::MULHS: 2432 case ISD::MUL: 2433 case ISD::SDIV: 2434 case ISD::SREM: 2435 assert(VT.isInteger() && "This operator does not apply to FP types!"); 2436 // fall through 2437 case ISD::FADD: 2438 case ISD::FSUB: 2439 case ISD::FMUL: 2440 case ISD::FDIV: 2441 case ISD::FREM: 2442 if (UnsafeFPMath) { 2443 if (Opcode == ISD::FADD) { 2444 // 0+x --> x 2445 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) 2446 if (CFP->getValueAPF().isZero()) 2447 return N2; 2448 // x+0 --> x 2449 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N2)) 2450 if (CFP->getValueAPF().isZero()) 2451 return N1; 2452 } else if (Opcode == ISD::FSUB) { 2453 // x-0 --> x 2454 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N2)) 2455 if (CFP->getValueAPF().isZero()) 2456 return N1; 2457 } 2458 } 2459 assert(N1.getValueType() == N2.getValueType() && 2460 N1.getValueType() == VT && "Binary operator types must match!"); 2461 break; 2462 case ISD::FCOPYSIGN: // N1 and result must match. N1/N2 need not match. 2463 assert(N1.getValueType() == VT && 2464 N1.getValueType().isFloatingPoint() && 2465 N2.getValueType().isFloatingPoint() && 2466 "Invalid FCOPYSIGN!"); 2467 break; 2468 case ISD::SHL: 2469 case ISD::SRA: 2470 case ISD::SRL: 2471 case ISD::ROTL: 2472 case ISD::ROTR: 2473 assert(VT == N1.getValueType() && 2474 "Shift operators return type must be the same as their first arg"); 2475 assert(VT.isInteger() && N2.getValueType().isInteger() && 2476 "Shifts only work on integers"); 2477 2478 // Always fold shifts of i1 values so the code generator doesn't need to 2479 // handle them. Since we know the size of the shift has to be less than the 2480 // size of the value, the shift/rotate count is guaranteed to be zero. 2481 if (VT == MVT::i1) 2482 return N1; 2483 break; 2484 case ISD::FP_ROUND_INREG: { 2485 MVT EVT = cast<VTSDNode>(N2)->getVT(); 2486 assert(VT == N1.getValueType() && "Not an inreg round!"); 2487 assert(VT.isFloatingPoint() && EVT.isFloatingPoint() && 2488 "Cannot FP_ROUND_INREG integer types"); 2489 assert(EVT.bitsLE(VT) && "Not rounding down!"); 2490 if (cast<VTSDNode>(N2)->getVT() == VT) return N1; // Not actually rounding. 2491 break; 2492 } 2493 case ISD::FP_ROUND: 2494 assert(VT.isFloatingPoint() && 2495 N1.getValueType().isFloatingPoint() && 2496 VT.bitsLE(N1.getValueType()) && 2497 isa<ConstantSDNode>(N2) && "Invalid FP_ROUND!"); 2498 if (N1.getValueType() == VT) return N1; // noop conversion. 2499 break; 2500 case ISD::AssertSext: 2501 case ISD::AssertZext: { 2502 MVT EVT = cast<VTSDNode>(N2)->getVT(); 2503 assert(VT == N1.getValueType() && "Not an inreg extend!"); 2504 assert(VT.isInteger() && EVT.isInteger() && 2505 "Cannot *_EXTEND_INREG FP types"); 2506 assert(EVT.bitsLE(VT) && "Not extending!"); 2507 if (VT == EVT) return N1; // noop assertion. 2508 break; 2509 } 2510 case ISD::SIGN_EXTEND_INREG: { 2511 MVT EVT = cast<VTSDNode>(N2)->getVT(); 2512 assert(VT == N1.getValueType() && "Not an inreg extend!"); 2513 assert(VT.isInteger() && EVT.isInteger() && 2514 "Cannot *_EXTEND_INREG FP types"); 2515 assert(EVT.bitsLE(VT) && "Not extending!"); 2516 if (EVT == VT) return N1; // Not actually extending 2517 2518 if (N1C) { 2519 APInt Val = N1C->getAPIntValue(); 2520 unsigned FromBits = cast<VTSDNode>(N2)->getVT().getSizeInBits(); 2521 Val <<= Val.getBitWidth()-FromBits; 2522 Val = Val.ashr(Val.getBitWidth()-FromBits); 2523 return getConstant(Val, VT); 2524 } 2525 break; 2526 } 2527 case ISD::EXTRACT_VECTOR_ELT: 2528 // EXTRACT_VECTOR_ELT of an UNDEF is an UNDEF. 2529 if (N1.getOpcode() == ISD::UNDEF) 2530 return getUNDEF(VT); 2531 2532 // EXTRACT_VECTOR_ELT of CONCAT_VECTORS is often formed while lowering is 2533 // expanding copies of large vectors from registers. 2534 if (N2C && 2535 N1.getOpcode() == ISD::CONCAT_VECTORS && 2536 N1.getNumOperands() > 0) { 2537 unsigned Factor = 2538 N1.getOperand(0).getValueType().getVectorNumElements(); 2539 return getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, 2540 N1.getOperand(N2C->getZExtValue() / Factor), 2541 getConstant(N2C->getZExtValue() % Factor, 2542 N2.getValueType())); 2543 } 2544 2545 // EXTRACT_VECTOR_ELT of BUILD_VECTOR is often formed while lowering is 2546 // expanding large vector constants. 2547 if (N2C && N1.getOpcode() == ISD::BUILD_VECTOR) { 2548 SDValue Elt = N1.getOperand(N2C->getZExtValue()); 2549 if (Elt.getValueType() != VT) { 2550 // If the vector element type is not legal, the BUILD_VECTOR operands 2551 // are promoted and implicitly truncated. Make that explicit here. 2552 assert(VT.isInteger() && Elt.getValueType().isInteger() && 2553 VT.bitsLE(Elt.getValueType()) && 2554 "Bad type for BUILD_VECTOR operand"); 2555 Elt = getNode(ISD::TRUNCATE, DL, VT, Elt); 2556 } 2557 return Elt; 2558 } 2559 2560 // EXTRACT_VECTOR_ELT of INSERT_VECTOR_ELT is often formed when vector 2561 // operations are lowered to scalars. 2562 if (N1.getOpcode() == ISD::INSERT_VECTOR_ELT) { 2563 // If the indices are the same, return the inserted element. 2564 if (N1.getOperand(2) == N2) 2565 return N1.getOperand(1); 2566 // If the indices are known different, extract the element from 2567 // the original vector. 2568 else if (isa<ConstantSDNode>(N1.getOperand(2)) && 2569 isa<ConstantSDNode>(N2)) 2570 return getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, N1.getOperand(0), N2); 2571 } 2572 break; 2573 case ISD::EXTRACT_ELEMENT: 2574 assert(N2C && (unsigned)N2C->getZExtValue() < 2 && "Bad EXTRACT_ELEMENT!"); 2575 assert(!N1.getValueType().isVector() && !VT.isVector() && 2576 (N1.getValueType().isInteger() == VT.isInteger()) && 2577 "Wrong types for EXTRACT_ELEMENT!"); 2578 2579 // EXTRACT_ELEMENT of BUILD_PAIR is often formed while legalize is expanding 2580 // 64-bit integers into 32-bit parts. Instead of building the extract of 2581 // the BUILD_PAIR, only to have legalize rip it apart, just do it now. 2582 if (N1.getOpcode() == ISD::BUILD_PAIR) 2583 return N1.getOperand(N2C->getZExtValue()); 2584 2585 // EXTRACT_ELEMENT of a constant int is also very common. 2586 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) { 2587 unsigned ElementSize = VT.getSizeInBits(); 2588 unsigned Shift = ElementSize * N2C->getZExtValue(); 2589 APInt ShiftedVal = C->getAPIntValue().lshr(Shift); 2590 return getConstant(ShiftedVal.trunc(ElementSize), VT); 2591 } 2592 break; 2593 case ISD::EXTRACT_SUBVECTOR: 2594 if (N1.getValueType() == VT) // Trivial extraction. 2595 return N1; 2596 break; 2597 } 2598 2599 if (N1C) { 2600 if (N2C) { 2601 SDValue SV = FoldConstantArithmetic(Opcode, VT, N1C, N2C); 2602 if (SV.getNode()) return SV; 2603 } else { // Cannonicalize constant to RHS if commutative 2604 if (isCommutativeBinOp(Opcode)) { 2605 std::swap(N1C, N2C); 2606 std::swap(N1, N2); 2607 } 2608 } 2609 } 2610 2611 // Constant fold FP operations. 2612 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1.getNode()); 2613 ConstantFPSDNode *N2CFP = dyn_cast<ConstantFPSDNode>(N2.getNode()); 2614 if (N1CFP) { 2615 if (!N2CFP && isCommutativeBinOp(Opcode)) { 2616 // Cannonicalize constant to RHS if commutative 2617 std::swap(N1CFP, N2CFP); 2618 std::swap(N1, N2); 2619 } else if (N2CFP && VT != MVT::ppcf128) { 2620 APFloat V1 = N1CFP->getValueAPF(), V2 = N2CFP->getValueAPF(); 2621 APFloat::opStatus s; 2622 switch (Opcode) { 2623 case ISD::FADD: 2624 s = V1.add(V2, APFloat::rmNearestTiesToEven); 2625 if (s != APFloat::opInvalidOp) 2626 return getConstantFP(V1, VT); 2627 break; 2628 case ISD::FSUB: 2629 s = V1.subtract(V2, APFloat::rmNearestTiesToEven); 2630 if (s!=APFloat::opInvalidOp) 2631 return getConstantFP(V1, VT); 2632 break; 2633 case ISD::FMUL: 2634 s = V1.multiply(V2, APFloat::rmNearestTiesToEven); 2635 if (s!=APFloat::opInvalidOp) 2636 return getConstantFP(V1, VT); 2637 break; 2638 case ISD::FDIV: 2639 s = V1.divide(V2, APFloat::rmNearestTiesToEven); 2640 if (s!=APFloat::opInvalidOp && s!=APFloat::opDivByZero) 2641 return getConstantFP(V1, VT); 2642 break; 2643 case ISD::FREM : 2644 s = V1.mod(V2, APFloat::rmNearestTiesToEven); 2645 if (s!=APFloat::opInvalidOp && s!=APFloat::opDivByZero) 2646 return getConstantFP(V1, VT); 2647 break; 2648 case ISD::FCOPYSIGN: 2649 V1.copySign(V2); 2650 return getConstantFP(V1, VT); 2651 default: break; 2652 } 2653 } 2654 } 2655 2656 // Canonicalize an UNDEF to the RHS, even over a constant. 2657 if (N1.getOpcode() == ISD::UNDEF) { 2658 if (isCommutativeBinOp(Opcode)) { 2659 std::swap(N1, N2); 2660 } else { 2661 switch (Opcode) { 2662 case ISD::FP_ROUND_INREG: 2663 case ISD::SIGN_EXTEND_INREG: 2664 case ISD::SUB: 2665 case ISD::FSUB: 2666 case ISD::FDIV: 2667 case ISD::FREM: 2668 case ISD::SRA: 2669 return N1; // fold op(undef, arg2) -> undef 2670 case ISD::UDIV: 2671 case ISD::SDIV: 2672 case ISD::UREM: 2673 case ISD::SREM: 2674 case ISD::SRL: 2675 case ISD::SHL: 2676 if (!VT.isVector()) 2677 return getConstant(0, VT); // fold op(undef, arg2) -> 0 2678 // For vectors, we can't easily build an all zero vector, just return 2679 // the LHS. 2680 return N2; 2681 } 2682 } 2683 } 2684 2685 // Fold a bunch of operators when the RHS is undef. 2686 if (N2.getOpcode() == ISD::UNDEF) { 2687 switch (Opcode) { 2688 case ISD::XOR: 2689 if (N1.getOpcode() == ISD::UNDEF) 2690 // Handle undef ^ undef -> 0 special case. This is a common 2691 // idiom (misuse). 2692 return getConstant(0, VT); 2693 // fallthrough 2694 case ISD::ADD: 2695 case ISD::ADDC: 2696 case ISD::ADDE: 2697 case ISD::SUB: 2698 case ISD::FADD: 2699 case ISD::FSUB: 2700 case ISD::FMUL: 2701 case ISD::FDIV: 2702 case ISD::FREM: 2703 case ISD::UDIV: 2704 case ISD::SDIV: 2705 case ISD::UREM: 2706 case ISD::SREM: 2707 return N2; // fold op(arg1, undef) -> undef 2708 case ISD::MUL: 2709 case ISD::AND: 2710 case ISD::SRL: 2711 case ISD::SHL: 2712 if (!VT.isVector()) 2713 return getConstant(0, VT); // fold op(arg1, undef) -> 0 2714 // For vectors, we can't easily build an all zero vector, just return 2715 // the LHS. 2716 return N1; 2717 case ISD::OR: 2718 if (!VT.isVector()) 2719 return getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT); 2720 // For vectors, we can't easily build an all one vector, just return 2721 // the LHS. 2722 return N1; 2723 case ISD::SRA: 2724 return N1; 2725 } 2726 } 2727 2728 // Memoize this node if possible. 2729 SDNode *N; 2730 SDVTList VTs = getVTList(VT); 2731 if (VT != MVT::Flag) { 2732 SDValue Ops[] = { N1, N2 }; 2733 FoldingSetNodeID ID; 2734 AddNodeIDNode(ID, Opcode, VTs, Ops, 2); 2735 void *IP = 0; 2736 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2737 return SDValue(E, 0); 2738 N = NodeAllocator.Allocate<BinarySDNode>(); 2739 new (N) BinarySDNode(Opcode, DL, VTs, N1, N2); 2740 CSEMap.InsertNode(N, IP); 2741 } else { 2742 N = NodeAllocator.Allocate<BinarySDNode>(); 2743 new (N) BinarySDNode(Opcode, DL, VTs, N1, N2); 2744 } 2745 2746 AllNodes.push_back(N); 2747#ifndef NDEBUG 2748 VerifyNode(N); 2749#endif 2750 return SDValue(N, 0); 2751} 2752 2753SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, 2754 SDValue N1, SDValue N2, SDValue N3) { 2755 // Perform various simplifications. 2756 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 2757 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 2758 switch (Opcode) { 2759 case ISD::CONCAT_VECTORS: 2760 // A CONCAT_VECTOR with all operands BUILD_VECTOR can be simplified to 2761 // one big BUILD_VECTOR. 2762 if (N1.getOpcode() == ISD::BUILD_VECTOR && 2763 N2.getOpcode() == ISD::BUILD_VECTOR && 2764 N3.getOpcode() == ISD::BUILD_VECTOR) { 2765 SmallVector<SDValue, 16> Elts(N1.getNode()->op_begin(), N1.getNode()->op_end()); 2766 Elts.insert(Elts.end(), N2.getNode()->op_begin(), N2.getNode()->op_end()); 2767 Elts.insert(Elts.end(), N3.getNode()->op_begin(), N3.getNode()->op_end()); 2768 return getNode(ISD::BUILD_VECTOR, DL, VT, &Elts[0], Elts.size()); 2769 } 2770 break; 2771 case ISD::SETCC: { 2772 // Use FoldSetCC to simplify SETCC's. 2773 SDValue Simp = FoldSetCC(VT, N1, N2, cast<CondCodeSDNode>(N3)->get(), DL); 2774 if (Simp.getNode()) return Simp; 2775 break; 2776 } 2777 case ISD::SELECT: 2778 if (N1C) { 2779 if (N1C->getZExtValue()) 2780 return N2; // select true, X, Y -> X 2781 else 2782 return N3; // select false, X, Y -> Y 2783 } 2784 2785 if (N2 == N3) return N2; // select C, X, X -> X 2786 break; 2787 case ISD::BRCOND: 2788 if (N2C) { 2789 if (N2C->getZExtValue()) // Unconditional branch 2790 return getNode(ISD::BR, DL, MVT::Other, N1, N3); 2791 else 2792 return N1; // Never-taken branch 2793 } 2794 break; 2795 case ISD::VECTOR_SHUFFLE: 2796 assert(N1.getValueType() == N2.getValueType() && 2797 N1.getValueType().isVector() && 2798 VT.isVector() && N3.getValueType().isVector() && 2799 N3.getOpcode() == ISD::BUILD_VECTOR && 2800 VT.getVectorNumElements() == N3.getNumOperands() && 2801 "Illegal VECTOR_SHUFFLE node!"); 2802 break; 2803 case ISD::BIT_CONVERT: 2804 // Fold bit_convert nodes from a type to themselves. 2805 if (N1.getValueType() == VT) 2806 return N1; 2807 break; 2808 } 2809 2810 // Memoize node if it doesn't produce a flag. 2811 SDNode *N; 2812 SDVTList VTs = getVTList(VT); 2813 if (VT != MVT::Flag) { 2814 SDValue Ops[] = { N1, N2, N3 }; 2815 FoldingSetNodeID ID; 2816 AddNodeIDNode(ID, Opcode, VTs, Ops, 3); 2817 void *IP = 0; 2818 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2819 return SDValue(E, 0); 2820 N = NodeAllocator.Allocate<TernarySDNode>(); 2821 new (N) TernarySDNode(Opcode, DL, VTs, N1, N2, N3); 2822 CSEMap.InsertNode(N, IP); 2823 } else { 2824 N = NodeAllocator.Allocate<TernarySDNode>(); 2825 new (N) TernarySDNode(Opcode, DL, VTs, N1, N2, N3); 2826 } 2827 AllNodes.push_back(N); 2828#ifndef NDEBUG 2829 VerifyNode(N); 2830#endif 2831 return SDValue(N, 0); 2832} 2833 2834SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, 2835 SDValue N1, SDValue N2, SDValue N3, 2836 SDValue N4) { 2837 SDValue Ops[] = { N1, N2, N3, N4 }; 2838 return getNode(Opcode, DL, VT, Ops, 4); 2839} 2840 2841SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, 2842 SDValue N1, SDValue N2, SDValue N3, 2843 SDValue N4, SDValue N5) { 2844 SDValue Ops[] = { N1, N2, N3, N4, N5 }; 2845 return getNode(Opcode, DL, VT, Ops, 5); 2846} 2847 2848/// getMemsetValue - Vectorized representation of the memset value 2849/// operand. 2850static SDValue getMemsetValue(SDValue Value, MVT VT, SelectionDAG &DAG, 2851 DebugLoc dl) { 2852 unsigned NumBits = VT.isVector() ? 2853 VT.getVectorElementType().getSizeInBits() : VT.getSizeInBits(); 2854 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) { 2855 APInt Val = APInt(NumBits, C->getZExtValue() & 255); 2856 unsigned Shift = 8; 2857 for (unsigned i = NumBits; i > 8; i >>= 1) { 2858 Val = (Val << Shift) | Val; 2859 Shift <<= 1; 2860 } 2861 if (VT.isInteger()) 2862 return DAG.getConstant(Val, VT); 2863 return DAG.getConstantFP(APFloat(Val), VT); 2864 } 2865 2866 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 2867 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Value); 2868 unsigned Shift = 8; 2869 for (unsigned i = NumBits; i > 8; i >>= 1) { 2870 Value = DAG.getNode(ISD::OR, dl, VT, 2871 DAG.getNode(ISD::SHL, dl, VT, Value, 2872 DAG.getConstant(Shift, 2873 TLI.getShiftAmountTy())), 2874 Value); 2875 Shift <<= 1; 2876 } 2877 2878 return Value; 2879} 2880 2881/// getMemsetStringVal - Similar to getMemsetValue. Except this is only 2882/// used when a memcpy is turned into a memset when the source is a constant 2883/// string ptr. 2884static SDValue getMemsetStringVal(MVT VT, DebugLoc dl, SelectionDAG &DAG, 2885 const TargetLowering &TLI, 2886 std::string &Str, unsigned Offset) { 2887 // Handle vector with all elements zero. 2888 if (Str.empty()) { 2889 if (VT.isInteger()) 2890 return DAG.getConstant(0, VT); 2891 unsigned NumElts = VT.getVectorNumElements(); 2892 MVT EltVT = (VT.getVectorElementType() == MVT::f32) ? MVT::i32 : MVT::i64; 2893 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 2894 DAG.getConstant(0, MVT::getVectorVT(EltVT, NumElts))); 2895 } 2896 2897 assert(!VT.isVector() && "Can't handle vector type here!"); 2898 unsigned NumBits = VT.getSizeInBits(); 2899 unsigned MSB = NumBits / 8; 2900 uint64_t Val = 0; 2901 if (TLI.isLittleEndian()) 2902 Offset = Offset + MSB - 1; 2903 for (unsigned i = 0; i != MSB; ++i) { 2904 Val = (Val << 8) | (unsigned char)Str[Offset]; 2905 Offset += TLI.isLittleEndian() ? -1 : 1; 2906 } 2907 return DAG.getConstant(Val, VT); 2908} 2909 2910/// getMemBasePlusOffset - Returns base and offset node for the 2911/// 2912static SDValue getMemBasePlusOffset(SDValue Base, unsigned Offset, 2913 SelectionDAG &DAG) { 2914 MVT VT = Base.getValueType(); 2915 return DAG.getNode(ISD::ADD, Base.getDebugLoc(), 2916 VT, Base, DAG.getConstant(Offset, VT)); 2917} 2918 2919/// isMemSrcFromString - Returns true if memcpy source is a string constant. 2920/// 2921static bool isMemSrcFromString(SDValue Src, std::string &Str) { 2922 unsigned SrcDelta = 0; 2923 GlobalAddressSDNode *G = NULL; 2924 if (Src.getOpcode() == ISD::GlobalAddress) 2925 G = cast<GlobalAddressSDNode>(Src); 2926 else if (Src.getOpcode() == ISD::ADD && 2927 Src.getOperand(0).getOpcode() == ISD::GlobalAddress && 2928 Src.getOperand(1).getOpcode() == ISD::Constant) { 2929 G = cast<GlobalAddressSDNode>(Src.getOperand(0)); 2930 SrcDelta = cast<ConstantSDNode>(Src.getOperand(1))->getZExtValue(); 2931 } 2932 if (!G) 2933 return false; 2934 2935 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal()); 2936 if (GV && GetConstantStringInfo(GV, Str, SrcDelta, false)) 2937 return true; 2938 2939 return false; 2940} 2941 2942/// MeetsMaxMemopRequirement - Determines if the number of memory ops required 2943/// to replace the memset / memcpy is below the threshold. It also returns the 2944/// types of the sequence of memory ops to perform memset / memcpy. 2945static 2946bool MeetsMaxMemopRequirement(std::vector<MVT> &MemOps, 2947 SDValue Dst, SDValue Src, 2948 unsigned Limit, uint64_t Size, unsigned &Align, 2949 std::string &Str, bool &isSrcStr, 2950 SelectionDAG &DAG, 2951 const TargetLowering &TLI) { 2952 isSrcStr = isMemSrcFromString(Src, Str); 2953 bool isSrcConst = isa<ConstantSDNode>(Src); 2954 bool AllowUnalign = TLI.allowsUnalignedMemoryAccesses(); 2955 MVT VT = TLI.getOptimalMemOpType(Size, Align, isSrcConst, isSrcStr); 2956 if (VT != MVT::iAny) { 2957 unsigned NewAlign = (unsigned) 2958 TLI.getTargetData()->getABITypeAlignment(VT.getTypeForMVT()); 2959 // If source is a string constant, this will require an unaligned load. 2960 if (NewAlign > Align && (isSrcConst || AllowUnalign)) { 2961 if (Dst.getOpcode() != ISD::FrameIndex) { 2962 // Can't change destination alignment. It requires a unaligned store. 2963 if (AllowUnalign) 2964 VT = MVT::iAny; 2965 } else { 2966 int FI = cast<FrameIndexSDNode>(Dst)->getIndex(); 2967 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 2968 if (MFI->isFixedObjectIndex(FI)) { 2969 // Can't change destination alignment. It requires a unaligned store. 2970 if (AllowUnalign) 2971 VT = MVT::iAny; 2972 } else { 2973 // Give the stack frame object a larger alignment if needed. 2974 if (MFI->getObjectAlignment(FI) < NewAlign) 2975 MFI->setObjectAlignment(FI, NewAlign); 2976 Align = NewAlign; 2977 } 2978 } 2979 } 2980 } 2981 2982 if (VT == MVT::iAny) { 2983 if (AllowUnalign) { 2984 VT = MVT::i64; 2985 } else { 2986 switch (Align & 7) { 2987 case 0: VT = MVT::i64; break; 2988 case 4: VT = MVT::i32; break; 2989 case 2: VT = MVT::i16; break; 2990 default: VT = MVT::i8; break; 2991 } 2992 } 2993 2994 MVT LVT = MVT::i64; 2995 while (!TLI.isTypeLegal(LVT)) 2996 LVT = (MVT::SimpleValueType)(LVT.getSimpleVT() - 1); 2997 assert(LVT.isInteger()); 2998 2999 if (VT.bitsGT(LVT)) 3000 VT = LVT; 3001 } 3002 3003 unsigned NumMemOps = 0; 3004 while (Size != 0) { 3005 unsigned VTSize = VT.getSizeInBits() / 8; 3006 while (VTSize > Size) { 3007 // For now, only use non-vector load / store's for the left-over pieces. 3008 if (VT.isVector()) { 3009 VT = MVT::i64; 3010 while (!TLI.isTypeLegal(VT)) 3011 VT = (MVT::SimpleValueType)(VT.getSimpleVT() - 1); 3012 VTSize = VT.getSizeInBits() / 8; 3013 } else { 3014 VT = (MVT::SimpleValueType)(VT.getSimpleVT() - 1); 3015 VTSize >>= 1; 3016 } 3017 } 3018 3019 if (++NumMemOps > Limit) 3020 return false; 3021 MemOps.push_back(VT); 3022 Size -= VTSize; 3023 } 3024 3025 return true; 3026} 3027 3028static SDValue getMemcpyLoadsAndStores(SelectionDAG &DAG, DebugLoc dl, 3029 SDValue Chain, SDValue Dst, 3030 SDValue Src, uint64_t Size, 3031 unsigned Align, bool AlwaysInline, 3032 const Value *DstSV, uint64_t DstSVOff, 3033 const Value *SrcSV, uint64_t SrcSVOff){ 3034 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 3035 3036 // Expand memcpy to a series of load and store ops if the size operand falls 3037 // below a certain threshold. 3038 std::vector<MVT> MemOps; 3039 uint64_t Limit = -1ULL; 3040 if (!AlwaysInline) 3041 Limit = TLI.getMaxStoresPerMemcpy(); 3042 unsigned DstAlign = Align; // Destination alignment can change. 3043 std::string Str; 3044 bool CopyFromStr; 3045 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, Limit, Size, DstAlign, 3046 Str, CopyFromStr, DAG, TLI)) 3047 return SDValue(); 3048 3049 3050 bool isZeroStr = CopyFromStr && Str.empty(); 3051 SmallVector<SDValue, 8> OutChains; 3052 unsigned NumMemOps = MemOps.size(); 3053 uint64_t SrcOff = 0, DstOff = 0; 3054 for (unsigned i = 0; i < NumMemOps; i++) { 3055 MVT VT = MemOps[i]; 3056 unsigned VTSize = VT.getSizeInBits() / 8; 3057 SDValue Value, Store; 3058 3059 if (CopyFromStr && (isZeroStr || !VT.isVector())) { 3060 // It's unlikely a store of a vector immediate can be done in a single 3061 // instruction. It would require a load from a constantpool first. 3062 // We also handle store a vector with all zero's. 3063 // FIXME: Handle other cases where store of vector immediate is done in 3064 // a single instruction. 3065 Value = getMemsetStringVal(VT, dl, DAG, TLI, Str, SrcOff); 3066 Store = DAG.getStore(Chain, dl, Value, 3067 getMemBasePlusOffset(Dst, DstOff, DAG), 3068 DstSV, DstSVOff + DstOff, false, DstAlign); 3069 } else { 3070 Value = DAG.getLoad(VT, dl, Chain, 3071 getMemBasePlusOffset(Src, SrcOff, DAG), 3072 SrcSV, SrcSVOff + SrcOff, false, Align); 3073 Store = DAG.getStore(Chain, dl, Value, 3074 getMemBasePlusOffset(Dst, DstOff, DAG), 3075 DstSV, DstSVOff + DstOff, false, DstAlign); 3076 } 3077 OutChains.push_back(Store); 3078 SrcOff += VTSize; 3079 DstOff += VTSize; 3080 } 3081 3082 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3083 &OutChains[0], OutChains.size()); 3084} 3085 3086static SDValue getMemmoveLoadsAndStores(SelectionDAG &DAG, DebugLoc dl, 3087 SDValue Chain, SDValue Dst, 3088 SDValue Src, uint64_t Size, 3089 unsigned Align, bool AlwaysInline, 3090 const Value *DstSV, uint64_t DstSVOff, 3091 const Value *SrcSV, uint64_t SrcSVOff){ 3092 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 3093 3094 // Expand memmove to a series of load and store ops if the size operand falls 3095 // below a certain threshold. 3096 std::vector<MVT> MemOps; 3097 uint64_t Limit = -1ULL; 3098 if (!AlwaysInline) 3099 Limit = TLI.getMaxStoresPerMemmove(); 3100 unsigned DstAlign = Align; // Destination alignment can change. 3101 std::string Str; 3102 bool CopyFromStr; 3103 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, Limit, Size, DstAlign, 3104 Str, CopyFromStr, DAG, TLI)) 3105 return SDValue(); 3106 3107 uint64_t SrcOff = 0, DstOff = 0; 3108 3109 SmallVector<SDValue, 8> LoadValues; 3110 SmallVector<SDValue, 8> LoadChains; 3111 SmallVector<SDValue, 8> OutChains; 3112 unsigned NumMemOps = MemOps.size(); 3113 for (unsigned i = 0; i < NumMemOps; i++) { 3114 MVT VT = MemOps[i]; 3115 unsigned VTSize = VT.getSizeInBits() / 8; 3116 SDValue Value, Store; 3117 3118 Value = DAG.getLoad(VT, dl, Chain, 3119 getMemBasePlusOffset(Src, SrcOff, DAG), 3120 SrcSV, SrcSVOff + SrcOff, false, Align); 3121 LoadValues.push_back(Value); 3122 LoadChains.push_back(Value.getValue(1)); 3123 SrcOff += VTSize; 3124 } 3125 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3126 &LoadChains[0], LoadChains.size()); 3127 OutChains.clear(); 3128 for (unsigned i = 0; i < NumMemOps; i++) { 3129 MVT VT = MemOps[i]; 3130 unsigned VTSize = VT.getSizeInBits() / 8; 3131 SDValue Value, Store; 3132 3133 Store = DAG.getStore(Chain, dl, LoadValues[i], 3134 getMemBasePlusOffset(Dst, DstOff, DAG), 3135 DstSV, DstSVOff + DstOff, false, DstAlign); 3136 OutChains.push_back(Store); 3137 DstOff += VTSize; 3138 } 3139 3140 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3141 &OutChains[0], OutChains.size()); 3142} 3143 3144static SDValue getMemsetStores(SelectionDAG &DAG, DebugLoc dl, 3145 SDValue Chain, SDValue Dst, 3146 SDValue Src, uint64_t Size, 3147 unsigned Align, 3148 const Value *DstSV, uint64_t DstSVOff) { 3149 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 3150 3151 // Expand memset to a series of load/store ops if the size operand 3152 // falls below a certain threshold. 3153 std::vector<MVT> MemOps; 3154 std::string Str; 3155 bool CopyFromStr; 3156 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, TLI.getMaxStoresPerMemset(), 3157 Size, Align, Str, CopyFromStr, DAG, TLI)) 3158 return SDValue(); 3159 3160 SmallVector<SDValue, 8> OutChains; 3161 uint64_t DstOff = 0; 3162 3163 unsigned NumMemOps = MemOps.size(); 3164 for (unsigned i = 0; i < NumMemOps; i++) { 3165 MVT VT = MemOps[i]; 3166 unsigned VTSize = VT.getSizeInBits() / 8; 3167 SDValue Value = getMemsetValue(Src, VT, DAG, dl); 3168 SDValue Store = DAG.getStore(Chain, dl, Value, 3169 getMemBasePlusOffset(Dst, DstOff, DAG), 3170 DstSV, DstSVOff + DstOff); 3171 OutChains.push_back(Store); 3172 DstOff += VTSize; 3173 } 3174 3175 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3176 &OutChains[0], OutChains.size()); 3177} 3178 3179SDValue SelectionDAG::getMemcpy(SDValue Chain, DebugLoc dl, SDValue Dst, 3180 SDValue Src, SDValue Size, 3181 unsigned Align, bool AlwaysInline, 3182 const Value *DstSV, uint64_t DstSVOff, 3183 const Value *SrcSV, uint64_t SrcSVOff) { 3184 3185 // Check to see if we should lower the memcpy to loads and stores first. 3186 // For cases within the target-specified limits, this is the best choice. 3187 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 3188 if (ConstantSize) { 3189 // Memcpy with size zero? Just return the original chain. 3190 if (ConstantSize->isNullValue()) 3191 return Chain; 3192 3193 SDValue Result = 3194 getMemcpyLoadsAndStores(*this, dl, Chain, Dst, Src, 3195 ConstantSize->getZExtValue(), 3196 Align, false, DstSV, DstSVOff, SrcSV, SrcSVOff); 3197 if (Result.getNode()) 3198 return Result; 3199 } 3200 3201 // Then check to see if we should lower the memcpy with target-specific 3202 // code. If the target chooses to do this, this is the next best. 3203 SDValue Result = 3204 TLI.EmitTargetCodeForMemcpy(*this, dl, Chain, Dst, Src, Size, Align, 3205 AlwaysInline, 3206 DstSV, DstSVOff, SrcSV, SrcSVOff); 3207 if (Result.getNode()) 3208 return Result; 3209 3210 // If we really need inline code and the target declined to provide it, 3211 // use a (potentially long) sequence of loads and stores. 3212 if (AlwaysInline) { 3213 assert(ConstantSize && "AlwaysInline requires a constant size!"); 3214 return getMemcpyLoadsAndStores(*this, dl, Chain, Dst, Src, 3215 ConstantSize->getZExtValue(), Align, true, 3216 DstSV, DstSVOff, SrcSV, SrcSVOff); 3217 } 3218 3219 // Emit a library call. 3220 TargetLowering::ArgListTy Args; 3221 TargetLowering::ArgListEntry Entry; 3222 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 3223 Entry.Node = Dst; Args.push_back(Entry); 3224 Entry.Node = Src; Args.push_back(Entry); 3225 Entry.Node = Size; Args.push_back(Entry); 3226 // FIXME: pass in DebugLoc 3227 std::pair<SDValue,SDValue> CallResult = 3228 TLI.LowerCallTo(Chain, Type::VoidTy, 3229 false, false, false, false, CallingConv::C, false, 3230 getExternalSymbol("memcpy", TLI.getPointerTy()), 3231 Args, *this, dl); 3232 return CallResult.second; 3233} 3234 3235SDValue SelectionDAG::getMemmove(SDValue Chain, DebugLoc dl, SDValue Dst, 3236 SDValue Src, SDValue Size, 3237 unsigned Align, 3238 const Value *DstSV, uint64_t DstSVOff, 3239 const Value *SrcSV, uint64_t SrcSVOff) { 3240 3241 // Check to see if we should lower the memmove to loads and stores first. 3242 // For cases within the target-specified limits, this is the best choice. 3243 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 3244 if (ConstantSize) { 3245 // Memmove with size zero? Just return the original chain. 3246 if (ConstantSize->isNullValue()) 3247 return Chain; 3248 3249 SDValue Result = 3250 getMemmoveLoadsAndStores(*this, dl, Chain, Dst, Src, 3251 ConstantSize->getZExtValue(), 3252 Align, false, DstSV, DstSVOff, SrcSV, SrcSVOff); 3253 if (Result.getNode()) 3254 return Result; 3255 } 3256 3257 // Then check to see if we should lower the memmove with target-specific 3258 // code. If the target chooses to do this, this is the next best. 3259 SDValue Result = 3260 TLI.EmitTargetCodeForMemmove(*this, dl, Chain, Dst, Src, Size, Align, 3261 DstSV, DstSVOff, SrcSV, SrcSVOff); 3262 if (Result.getNode()) 3263 return Result; 3264 3265 // Emit a library call. 3266 TargetLowering::ArgListTy Args; 3267 TargetLowering::ArgListEntry Entry; 3268 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 3269 Entry.Node = Dst; Args.push_back(Entry); 3270 Entry.Node = Src; Args.push_back(Entry); 3271 Entry.Node = Size; Args.push_back(Entry); 3272 // FIXME: pass in DebugLoc 3273 std::pair<SDValue,SDValue> CallResult = 3274 TLI.LowerCallTo(Chain, Type::VoidTy, 3275 false, false, false, false, CallingConv::C, false, 3276 getExternalSymbol("memmove", TLI.getPointerTy()), 3277 Args, *this, dl); 3278 return CallResult.second; 3279} 3280 3281SDValue SelectionDAG::getMemset(SDValue Chain, DebugLoc dl, SDValue Dst, 3282 SDValue Src, SDValue Size, 3283 unsigned Align, 3284 const Value *DstSV, uint64_t DstSVOff) { 3285 3286 // Check to see if we should lower the memset to stores first. 3287 // For cases within the target-specified limits, this is the best choice. 3288 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 3289 if (ConstantSize) { 3290 // Memset with size zero? Just return the original chain. 3291 if (ConstantSize->isNullValue()) 3292 return Chain; 3293 3294 SDValue Result = 3295 getMemsetStores(*this, dl, Chain, Dst, Src, ConstantSize->getZExtValue(), 3296 Align, DstSV, DstSVOff); 3297 if (Result.getNode()) 3298 return Result; 3299 } 3300 3301 // Then check to see if we should lower the memset with target-specific 3302 // code. If the target chooses to do this, this is the next best. 3303 SDValue Result = 3304 TLI.EmitTargetCodeForMemset(*this, dl, Chain, Dst, Src, Size, Align, 3305 DstSV, DstSVOff); 3306 if (Result.getNode()) 3307 return Result; 3308 3309 // Emit a library call. 3310 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType(); 3311 TargetLowering::ArgListTy Args; 3312 TargetLowering::ArgListEntry Entry; 3313 Entry.Node = Dst; Entry.Ty = IntPtrTy; 3314 Args.push_back(Entry); 3315 // Extend or truncate the argument to be an i32 value for the call. 3316 if (Src.getValueType().bitsGT(MVT::i32)) 3317 Src = getNode(ISD::TRUNCATE, dl, MVT::i32, Src); 3318 else 3319 Src = getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Src); 3320 Entry.Node = Src; Entry.Ty = Type::Int32Ty; Entry.isSExt = true; 3321 Args.push_back(Entry); 3322 Entry.Node = Size; Entry.Ty = IntPtrTy; Entry.isSExt = false; 3323 Args.push_back(Entry); 3324 // FIXME: pass in DebugLoc 3325 std::pair<SDValue,SDValue> CallResult = 3326 TLI.LowerCallTo(Chain, Type::VoidTy, 3327 false, false, false, false, CallingConv::C, false, 3328 getExternalSymbol("memset", TLI.getPointerTy()), 3329 Args, *this, dl); 3330 return CallResult.second; 3331} 3332 3333SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, MVT MemVT, 3334 SDValue Chain, 3335 SDValue Ptr, SDValue Cmp, 3336 SDValue Swp, const Value* PtrVal, 3337 unsigned Alignment) { 3338 assert(Opcode == ISD::ATOMIC_CMP_SWAP && "Invalid Atomic Op"); 3339 assert(Cmp.getValueType() == Swp.getValueType() && "Invalid Atomic Op Types"); 3340 3341 MVT VT = Cmp.getValueType(); 3342 3343 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3344 Alignment = getMVTAlignment(MemVT); 3345 3346 SDVTList VTs = getVTList(VT, MVT::Other); 3347 FoldingSetNodeID ID; 3348 ID.AddInteger(MemVT.getRawBits()); 3349 SDValue Ops[] = {Chain, Ptr, Cmp, Swp}; 3350 AddNodeIDNode(ID, Opcode, VTs, Ops, 4); 3351 void* IP = 0; 3352 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3353 return SDValue(E, 0); 3354 SDNode* N = NodeAllocator.Allocate<AtomicSDNode>(); 3355 new (N) AtomicSDNode(Opcode, dl, VTs, MemVT, 3356 Chain, Ptr, Cmp, Swp, PtrVal, Alignment); 3357 CSEMap.InsertNode(N, IP); 3358 AllNodes.push_back(N); 3359 return SDValue(N, 0); 3360} 3361 3362SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, MVT MemVT, 3363 SDValue Chain, 3364 SDValue Ptr, SDValue Val, 3365 const Value* PtrVal, 3366 unsigned Alignment) { 3367 assert((Opcode == ISD::ATOMIC_LOAD_ADD || 3368 Opcode == ISD::ATOMIC_LOAD_SUB || 3369 Opcode == ISD::ATOMIC_LOAD_AND || 3370 Opcode == ISD::ATOMIC_LOAD_OR || 3371 Opcode == ISD::ATOMIC_LOAD_XOR || 3372 Opcode == ISD::ATOMIC_LOAD_NAND || 3373 Opcode == ISD::ATOMIC_LOAD_MIN || 3374 Opcode == ISD::ATOMIC_LOAD_MAX || 3375 Opcode == ISD::ATOMIC_LOAD_UMIN || 3376 Opcode == ISD::ATOMIC_LOAD_UMAX || 3377 Opcode == ISD::ATOMIC_SWAP) && 3378 "Invalid Atomic Op"); 3379 3380 MVT VT = Val.getValueType(); 3381 3382 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3383 Alignment = getMVTAlignment(MemVT); 3384 3385 SDVTList VTs = getVTList(VT, MVT::Other); 3386 FoldingSetNodeID ID; 3387 ID.AddInteger(MemVT.getRawBits()); 3388 SDValue Ops[] = {Chain, Ptr, Val}; 3389 AddNodeIDNode(ID, Opcode, VTs, Ops, 3); 3390 void* IP = 0; 3391 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3392 return SDValue(E, 0); 3393 SDNode* N = NodeAllocator.Allocate<AtomicSDNode>(); 3394 new (N) AtomicSDNode(Opcode, dl, VTs, MemVT, 3395 Chain, Ptr, Val, PtrVal, Alignment); 3396 CSEMap.InsertNode(N, IP); 3397 AllNodes.push_back(N); 3398 return SDValue(N, 0); 3399} 3400 3401/// getMergeValues - Create a MERGE_VALUES node from the given operands. 3402/// Allowed to return something different (and simpler) if Simplify is true. 3403SDValue SelectionDAG::getMergeValues(const SDValue *Ops, unsigned NumOps, 3404 DebugLoc dl) { 3405 if (NumOps == 1) 3406 return Ops[0]; 3407 3408 SmallVector<MVT, 4> VTs; 3409 VTs.reserve(NumOps); 3410 for (unsigned i = 0; i < NumOps; ++i) 3411 VTs.push_back(Ops[i].getValueType()); 3412 return getNode(ISD::MERGE_VALUES, dl, getVTList(&VTs[0], NumOps), 3413 Ops, NumOps); 3414} 3415 3416SDValue 3417SelectionDAG::getMemIntrinsicNode(unsigned Opcode, DebugLoc dl, 3418 const MVT *VTs, unsigned NumVTs, 3419 const SDValue *Ops, unsigned NumOps, 3420 MVT MemVT, const Value *srcValue, int SVOff, 3421 unsigned Align, bool Vol, 3422 bool ReadMem, bool WriteMem) { 3423 return getMemIntrinsicNode(Opcode, dl, makeVTList(VTs, NumVTs), Ops, NumOps, 3424 MemVT, srcValue, SVOff, Align, Vol, 3425 ReadMem, WriteMem); 3426} 3427 3428SDValue 3429SelectionDAG::getMemIntrinsicNode(unsigned Opcode, DebugLoc dl, SDVTList VTList, 3430 const SDValue *Ops, unsigned NumOps, 3431 MVT MemVT, const Value *srcValue, int SVOff, 3432 unsigned Align, bool Vol, 3433 bool ReadMem, bool WriteMem) { 3434 // Memoize the node unless it returns a flag. 3435 MemIntrinsicSDNode *N; 3436 if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) { 3437 FoldingSetNodeID ID; 3438 AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps); 3439 void *IP = 0; 3440 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3441 return SDValue(E, 0); 3442 3443 N = NodeAllocator.Allocate<MemIntrinsicSDNode>(); 3444 new (N) MemIntrinsicSDNode(Opcode, dl, VTList, Ops, NumOps, MemVT, 3445 srcValue, SVOff, Align, Vol, ReadMem, WriteMem); 3446 CSEMap.InsertNode(N, IP); 3447 } else { 3448 N = NodeAllocator.Allocate<MemIntrinsicSDNode>(); 3449 new (N) MemIntrinsicSDNode(Opcode, dl, VTList, Ops, NumOps, MemVT, 3450 srcValue, SVOff, Align, Vol, ReadMem, WriteMem); 3451 } 3452 AllNodes.push_back(N); 3453 return SDValue(N, 0); 3454} 3455 3456SDValue 3457SelectionDAG::getCall(unsigned CallingConv, DebugLoc dl, bool IsVarArgs, 3458 bool IsTailCall, bool IsInreg, SDVTList VTs, 3459 const SDValue *Operands, unsigned NumOperands) { 3460 // Do not include isTailCall in the folding set profile. 3461 FoldingSetNodeID ID; 3462 AddNodeIDNode(ID, ISD::CALL, VTs, Operands, NumOperands); 3463 ID.AddInteger(CallingConv); 3464 ID.AddInteger(IsVarArgs); 3465 void *IP = 0; 3466 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) { 3467 // Instead of including isTailCall in the folding set, we just 3468 // set the flag of the existing node. 3469 if (!IsTailCall) 3470 cast<CallSDNode>(E)->setNotTailCall(); 3471 return SDValue(E, 0); 3472 } 3473 SDNode *N = NodeAllocator.Allocate<CallSDNode>(); 3474 new (N) CallSDNode(CallingConv, dl, IsVarArgs, IsTailCall, IsInreg, 3475 VTs, Operands, NumOperands); 3476 CSEMap.InsertNode(N, IP); 3477 AllNodes.push_back(N); 3478 return SDValue(N, 0); 3479} 3480 3481SDValue 3482SelectionDAG::getLoad(ISD::MemIndexedMode AM, DebugLoc dl, 3483 ISD::LoadExtType ExtType, MVT VT, SDValue Chain, 3484 SDValue Ptr, SDValue Offset, 3485 const Value *SV, int SVOffset, MVT EVT, 3486 bool isVolatile, unsigned Alignment) { 3487 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3488 Alignment = getMVTAlignment(VT); 3489 3490 if (VT == EVT) { 3491 ExtType = ISD::NON_EXTLOAD; 3492 } else if (ExtType == ISD::NON_EXTLOAD) { 3493 assert(VT == EVT && "Non-extending load from different memory type!"); 3494 } else { 3495 // Extending load. 3496 if (VT.isVector()) 3497 assert(EVT.getVectorNumElements() == VT.getVectorNumElements() && 3498 "Invalid vector extload!"); 3499 else 3500 assert(EVT.bitsLT(VT) && 3501 "Should only be an extending load, not truncating!"); 3502 assert((ExtType == ISD::EXTLOAD || VT.isInteger()) && 3503 "Cannot sign/zero extend a FP/Vector load!"); 3504 assert(VT.isInteger() == EVT.isInteger() && 3505 "Cannot convert from FP to Int or Int -> FP!"); 3506 } 3507 3508 bool Indexed = AM != ISD::UNINDEXED; 3509 assert((Indexed || Offset.getOpcode() == ISD::UNDEF) && 3510 "Unindexed load with an offset!"); 3511 3512 SDVTList VTs = Indexed ? 3513 getVTList(VT, Ptr.getValueType(), MVT::Other) : getVTList(VT, MVT::Other); 3514 SDValue Ops[] = { Chain, Ptr, Offset }; 3515 FoldingSetNodeID ID; 3516 AddNodeIDNode(ID, ISD::LOAD, VTs, Ops, 3); 3517 ID.AddInteger(EVT.getRawBits()); 3518 ID.AddInteger(encodeMemSDNodeFlags(ExtType, AM, isVolatile, Alignment)); 3519 void *IP = 0; 3520 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3521 return SDValue(E, 0); 3522 SDNode *N = NodeAllocator.Allocate<LoadSDNode>(); 3523 new (N) LoadSDNode(Ops, dl, VTs, AM, ExtType, EVT, SV, SVOffset, 3524 Alignment, isVolatile); 3525 CSEMap.InsertNode(N, IP); 3526 AllNodes.push_back(N); 3527 return SDValue(N, 0); 3528} 3529 3530SDValue SelectionDAG::getLoad(MVT VT, DebugLoc dl, 3531 SDValue Chain, SDValue Ptr, 3532 const Value *SV, int SVOffset, 3533 bool isVolatile, unsigned Alignment) { 3534 SDValue Undef = getUNDEF(Ptr.getValueType()); 3535 return getLoad(ISD::UNINDEXED, dl, ISD::NON_EXTLOAD, VT, Chain, Ptr, Undef, 3536 SV, SVOffset, VT, isVolatile, Alignment); 3537} 3538 3539SDValue SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, DebugLoc dl, MVT VT, 3540 SDValue Chain, SDValue Ptr, 3541 const Value *SV, 3542 int SVOffset, MVT EVT, 3543 bool isVolatile, unsigned Alignment) { 3544 SDValue Undef = getUNDEF(Ptr.getValueType()); 3545 return getLoad(ISD::UNINDEXED, dl, ExtType, VT, Chain, Ptr, Undef, 3546 SV, SVOffset, EVT, isVolatile, Alignment); 3547} 3548 3549SDValue 3550SelectionDAG::getIndexedLoad(SDValue OrigLoad, DebugLoc dl, SDValue Base, 3551 SDValue Offset, ISD::MemIndexedMode AM) { 3552 LoadSDNode *LD = cast<LoadSDNode>(OrigLoad); 3553 assert(LD->getOffset().getOpcode() == ISD::UNDEF && 3554 "Load is already a indexed load!"); 3555 return getLoad(AM, dl, LD->getExtensionType(), OrigLoad.getValueType(), 3556 LD->getChain(), Base, Offset, LD->getSrcValue(), 3557 LD->getSrcValueOffset(), LD->getMemoryVT(), 3558 LD->isVolatile(), LD->getAlignment()); 3559} 3560 3561SDValue SelectionDAG::getStore(SDValue Chain, DebugLoc dl, SDValue Val, 3562 SDValue Ptr, const Value *SV, int SVOffset, 3563 bool isVolatile, unsigned Alignment) { 3564 MVT VT = Val.getValueType(); 3565 3566 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3567 Alignment = getMVTAlignment(VT); 3568 3569 SDVTList VTs = getVTList(MVT::Other); 3570 SDValue Undef = getUNDEF(Ptr.getValueType()); 3571 SDValue Ops[] = { Chain, Val, Ptr, Undef }; 3572 FoldingSetNodeID ID; 3573 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); 3574 ID.AddInteger(VT.getRawBits()); 3575 ID.AddInteger(encodeMemSDNodeFlags(false, ISD::UNINDEXED, 3576 isVolatile, Alignment)); 3577 void *IP = 0; 3578 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3579 return SDValue(E, 0); 3580 SDNode *N = NodeAllocator.Allocate<StoreSDNode>(); 3581 new (N) StoreSDNode(Ops, dl, VTs, ISD::UNINDEXED, false, 3582 VT, SV, SVOffset, Alignment, isVolatile); 3583 CSEMap.InsertNode(N, IP); 3584 AllNodes.push_back(N); 3585 return SDValue(N, 0); 3586} 3587 3588SDValue SelectionDAG::getTruncStore(SDValue Chain, DebugLoc dl, SDValue Val, 3589 SDValue Ptr, const Value *SV, 3590 int SVOffset, MVT SVT, 3591 bool isVolatile, unsigned Alignment) { 3592 MVT VT = Val.getValueType(); 3593 3594 if (VT == SVT) 3595 return getStore(Chain, dl, Val, Ptr, SV, SVOffset, isVolatile, Alignment); 3596 3597 assert(VT.bitsGT(SVT) && "Not a truncation?"); 3598 assert(VT.isInteger() == SVT.isInteger() && 3599 "Can't do FP-INT conversion!"); 3600 3601 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3602 Alignment = getMVTAlignment(VT); 3603 3604 SDVTList VTs = getVTList(MVT::Other); 3605 SDValue Undef = getUNDEF(Ptr.getValueType()); 3606 SDValue Ops[] = { Chain, Val, Ptr, Undef }; 3607 FoldingSetNodeID ID; 3608 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); 3609 ID.AddInteger(SVT.getRawBits()); 3610 ID.AddInteger(encodeMemSDNodeFlags(true, ISD::UNINDEXED, 3611 isVolatile, Alignment)); 3612 void *IP = 0; 3613 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3614 return SDValue(E, 0); 3615 SDNode *N = NodeAllocator.Allocate<StoreSDNode>(); 3616 new (N) StoreSDNode(Ops, dl, VTs, ISD::UNINDEXED, true, 3617 SVT, SV, SVOffset, Alignment, isVolatile); 3618 CSEMap.InsertNode(N, IP); 3619 AllNodes.push_back(N); 3620 return SDValue(N, 0); 3621} 3622 3623SDValue 3624SelectionDAG::getIndexedStore(SDValue OrigStore, DebugLoc dl, SDValue Base, 3625 SDValue Offset, ISD::MemIndexedMode AM) { 3626 StoreSDNode *ST = cast<StoreSDNode>(OrigStore); 3627 assert(ST->getOffset().getOpcode() == ISD::UNDEF && 3628 "Store is already a indexed store!"); 3629 SDVTList VTs = getVTList(Base.getValueType(), MVT::Other); 3630 SDValue Ops[] = { ST->getChain(), ST->getValue(), Base, Offset }; 3631 FoldingSetNodeID ID; 3632 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); 3633 ID.AddInteger(ST->getMemoryVT().getRawBits()); 3634 ID.AddInteger(ST->getRawSubclassData()); 3635 void *IP = 0; 3636 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3637 return SDValue(E, 0); 3638 SDNode *N = NodeAllocator.Allocate<StoreSDNode>(); 3639 new (N) StoreSDNode(Ops, dl, VTs, AM, 3640 ST->isTruncatingStore(), ST->getMemoryVT(), 3641 ST->getSrcValue(), ST->getSrcValueOffset(), 3642 ST->getAlignment(), ST->isVolatile()); 3643 CSEMap.InsertNode(N, IP); 3644 AllNodes.push_back(N); 3645 return SDValue(N, 0); 3646} 3647 3648SDValue SelectionDAG::getVAArg(MVT VT, DebugLoc dl, 3649 SDValue Chain, SDValue Ptr, 3650 SDValue SV) { 3651 SDValue Ops[] = { Chain, Ptr, SV }; 3652 return getNode(ISD::VAARG, dl, getVTList(VT, MVT::Other), Ops, 3); 3653} 3654 3655SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, 3656 const SDUse *Ops, unsigned NumOps) { 3657 switch (NumOps) { 3658 case 0: return getNode(Opcode, DL, VT); 3659 case 1: return getNode(Opcode, DL, VT, Ops[0]); 3660 case 2: return getNode(Opcode, DL, VT, Ops[0], Ops[1]); 3661 case 3: return getNode(Opcode, DL, VT, Ops[0], Ops[1], Ops[2]); 3662 default: break; 3663 } 3664 3665 // Copy from an SDUse array into an SDValue array for use with 3666 // the regular getNode logic. 3667 SmallVector<SDValue, 8> NewOps(Ops, Ops + NumOps); 3668 return getNode(Opcode, DL, VT, &NewOps[0], NumOps); 3669} 3670 3671SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, 3672 const SDValue *Ops, unsigned NumOps) { 3673 switch (NumOps) { 3674 case 0: return getNode(Opcode, DL, VT); 3675 case 1: return getNode(Opcode, DL, VT, Ops[0]); 3676 case 2: return getNode(Opcode, DL, VT, Ops[0], Ops[1]); 3677 case 3: return getNode(Opcode, DL, VT, Ops[0], Ops[1], Ops[2]); 3678 default: break; 3679 } 3680 3681 switch (Opcode) { 3682 default: break; 3683 case ISD::SELECT_CC: { 3684 assert(NumOps == 5 && "SELECT_CC takes 5 operands!"); 3685 assert(Ops[0].getValueType() == Ops[1].getValueType() && 3686 "LHS and RHS of condition must have same type!"); 3687 assert(Ops[2].getValueType() == Ops[3].getValueType() && 3688 "True and False arms of SelectCC must have same type!"); 3689 assert(Ops[2].getValueType() == VT && 3690 "select_cc node must be of same type as true and false value!"); 3691 break; 3692 } 3693 case ISD::BR_CC: { 3694 assert(NumOps == 5 && "BR_CC takes 5 operands!"); 3695 assert(Ops[2].getValueType() == Ops[3].getValueType() && 3696 "LHS/RHS of comparison should match types!"); 3697 break; 3698 } 3699 } 3700 3701 // Memoize nodes. 3702 SDNode *N; 3703 SDVTList VTs = getVTList(VT); 3704 3705 if (VT != MVT::Flag) { 3706 FoldingSetNodeID ID; 3707 AddNodeIDNode(ID, Opcode, VTs, Ops, NumOps); 3708 void *IP = 0; 3709 3710 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3711 return SDValue(E, 0); 3712 3713 N = NodeAllocator.Allocate<SDNode>(); 3714 new (N) SDNode(Opcode, DL, VTs, Ops, NumOps); 3715 CSEMap.InsertNode(N, IP); 3716 } else { 3717 N = NodeAllocator.Allocate<SDNode>(); 3718 new (N) SDNode(Opcode, DL, VTs, Ops, NumOps); 3719 } 3720 3721 AllNodes.push_back(N); 3722#ifndef NDEBUG 3723 VerifyNode(N); 3724#endif 3725 return SDValue(N, 0); 3726} 3727 3728SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, 3729 const std::vector<MVT> &ResultTys, 3730 const SDValue *Ops, unsigned NumOps) { 3731 return getNode(Opcode, DL, getVTList(&ResultTys[0], ResultTys.size()), 3732 Ops, NumOps); 3733} 3734 3735SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, 3736 const MVT *VTs, unsigned NumVTs, 3737 const SDValue *Ops, unsigned NumOps) { 3738 if (NumVTs == 1) 3739 return getNode(Opcode, DL, VTs[0], Ops, NumOps); 3740 return getNode(Opcode, DL, makeVTList(VTs, NumVTs), Ops, NumOps); 3741} 3742 3743SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, 3744 const SDValue *Ops, unsigned NumOps) { 3745 if (VTList.NumVTs == 1) 3746 return getNode(Opcode, DL, VTList.VTs[0], Ops, NumOps); 3747 3748 switch (Opcode) { 3749 // FIXME: figure out how to safely handle things like 3750 // int foo(int x) { return 1 << (x & 255); } 3751 // int bar() { return foo(256); } 3752#if 0 3753 case ISD::SRA_PARTS: 3754 case ISD::SRL_PARTS: 3755 case ISD::SHL_PARTS: 3756 if (N3.getOpcode() == ISD::SIGN_EXTEND_INREG && 3757 cast<VTSDNode>(N3.getOperand(1))->getVT() != MVT::i1) 3758 return getNode(Opcode, DL, VT, N1, N2, N3.getOperand(0)); 3759 else if (N3.getOpcode() == ISD::AND) 3760 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(N3.getOperand(1))) { 3761 // If the and is only masking out bits that cannot effect the shift, 3762 // eliminate the and. 3763 unsigned NumBits = VT.getSizeInBits()*2; 3764 if ((AndRHS->getValue() & (NumBits-1)) == NumBits-1) 3765 return getNode(Opcode, DL, VT, N1, N2, N3.getOperand(0)); 3766 } 3767 break; 3768#endif 3769 } 3770 3771 // Memoize the node unless it returns a flag. 3772 SDNode *N; 3773 if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) { 3774 FoldingSetNodeID ID; 3775 AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps); 3776 void *IP = 0; 3777 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3778 return SDValue(E, 0); 3779 if (NumOps == 1) { 3780 N = NodeAllocator.Allocate<UnarySDNode>(); 3781 new (N) UnarySDNode(Opcode, DL, VTList, Ops[0]); 3782 } else if (NumOps == 2) { 3783 N = NodeAllocator.Allocate<BinarySDNode>(); 3784 new (N) BinarySDNode(Opcode, DL, VTList, Ops[0], Ops[1]); 3785 } else if (NumOps == 3) { 3786 N = NodeAllocator.Allocate<TernarySDNode>(); 3787 new (N) TernarySDNode(Opcode, DL, VTList, Ops[0], Ops[1], Ops[2]); 3788 } else { 3789 N = NodeAllocator.Allocate<SDNode>(); 3790 new (N) SDNode(Opcode, DL, VTList, Ops, NumOps); 3791 } 3792 CSEMap.InsertNode(N, IP); 3793 } else { 3794 if (NumOps == 1) { 3795 N = NodeAllocator.Allocate<UnarySDNode>(); 3796 new (N) UnarySDNode(Opcode, DL, VTList, Ops[0]); 3797 } else if (NumOps == 2) { 3798 N = NodeAllocator.Allocate<BinarySDNode>(); 3799 new (N) BinarySDNode(Opcode, DL, VTList, Ops[0], Ops[1]); 3800 } else if (NumOps == 3) { 3801 N = NodeAllocator.Allocate<TernarySDNode>(); 3802 new (N) TernarySDNode(Opcode, DL, VTList, Ops[0], Ops[1], Ops[2]); 3803 } else { 3804 N = NodeAllocator.Allocate<SDNode>(); 3805 new (N) SDNode(Opcode, DL, VTList, Ops, NumOps); 3806 } 3807 } 3808 AllNodes.push_back(N); 3809#ifndef NDEBUG 3810 VerifyNode(N); 3811#endif 3812 return SDValue(N, 0); 3813} 3814 3815SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList) { 3816 return getNode(Opcode, DL, VTList, 0, 0); 3817} 3818 3819SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, 3820 SDValue N1) { 3821 SDValue Ops[] = { N1 }; 3822 return getNode(Opcode, DL, VTList, Ops, 1); 3823} 3824 3825SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, 3826 SDValue N1, SDValue N2) { 3827 SDValue Ops[] = { N1, N2 }; 3828 return getNode(Opcode, DL, VTList, Ops, 2); 3829} 3830 3831SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, 3832 SDValue N1, SDValue N2, SDValue N3) { 3833 SDValue Ops[] = { N1, N2, N3 }; 3834 return getNode(Opcode, DL, VTList, Ops, 3); 3835} 3836 3837SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, 3838 SDValue N1, SDValue N2, SDValue N3, 3839 SDValue N4) { 3840 SDValue Ops[] = { N1, N2, N3, N4 }; 3841 return getNode(Opcode, DL, VTList, Ops, 4); 3842} 3843 3844SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, 3845 SDValue N1, SDValue N2, SDValue N3, 3846 SDValue N4, SDValue N5) { 3847 SDValue Ops[] = { N1, N2, N3, N4, N5 }; 3848 return getNode(Opcode, DL, VTList, Ops, 5); 3849} 3850 3851SDVTList SelectionDAG::getVTList(MVT VT) { 3852 return makeVTList(SDNode::getValueTypeList(VT), 1); 3853} 3854 3855SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2) { 3856 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 3857 E = VTList.rend(); I != E; ++I) 3858 if (I->NumVTs == 2 && I->VTs[0] == VT1 && I->VTs[1] == VT2) 3859 return *I; 3860 3861 MVT *Array = Allocator.Allocate<MVT>(2); 3862 Array[0] = VT1; 3863 Array[1] = VT2; 3864 SDVTList Result = makeVTList(Array, 2); 3865 VTList.push_back(Result); 3866 return Result; 3867} 3868 3869SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2, MVT VT3) { 3870 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 3871 E = VTList.rend(); I != E; ++I) 3872 if (I->NumVTs == 3 && I->VTs[0] == VT1 && I->VTs[1] == VT2 && 3873 I->VTs[2] == VT3) 3874 return *I; 3875 3876 MVT *Array = Allocator.Allocate<MVT>(3); 3877 Array[0] = VT1; 3878 Array[1] = VT2; 3879 Array[2] = VT3; 3880 SDVTList Result = makeVTList(Array, 3); 3881 VTList.push_back(Result); 3882 return Result; 3883} 3884 3885SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2, MVT VT3, MVT VT4) { 3886 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 3887 E = VTList.rend(); I != E; ++I) 3888 if (I->NumVTs == 4 && I->VTs[0] == VT1 && I->VTs[1] == VT2 && 3889 I->VTs[2] == VT3 && I->VTs[3] == VT4) 3890 return *I; 3891 3892 MVT *Array = Allocator.Allocate<MVT>(3); 3893 Array[0] = VT1; 3894 Array[1] = VT2; 3895 Array[2] = VT3; 3896 Array[3] = VT4; 3897 SDVTList Result = makeVTList(Array, 4); 3898 VTList.push_back(Result); 3899 return Result; 3900} 3901 3902SDVTList SelectionDAG::getVTList(const MVT *VTs, unsigned NumVTs) { 3903 switch (NumVTs) { 3904 case 0: assert(0 && "Cannot have nodes without results!"); 3905 case 1: return getVTList(VTs[0]); 3906 case 2: return getVTList(VTs[0], VTs[1]); 3907 case 3: return getVTList(VTs[0], VTs[1], VTs[2]); 3908 default: break; 3909 } 3910 3911 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 3912 E = VTList.rend(); I != E; ++I) { 3913 if (I->NumVTs != NumVTs || VTs[0] != I->VTs[0] || VTs[1] != I->VTs[1]) 3914 continue; 3915 3916 bool NoMatch = false; 3917 for (unsigned i = 2; i != NumVTs; ++i) 3918 if (VTs[i] != I->VTs[i]) { 3919 NoMatch = true; 3920 break; 3921 } 3922 if (!NoMatch) 3923 return *I; 3924 } 3925 3926 MVT *Array = Allocator.Allocate<MVT>(NumVTs); 3927 std::copy(VTs, VTs+NumVTs, Array); 3928 SDVTList Result = makeVTList(Array, NumVTs); 3929 VTList.push_back(Result); 3930 return Result; 3931} 3932 3933 3934/// UpdateNodeOperands - *Mutate* the specified node in-place to have the 3935/// specified operands. If the resultant node already exists in the DAG, 3936/// this does not modify the specified node, instead it returns the node that 3937/// already exists. If the resultant node does not exist in the DAG, the 3938/// input node is returned. As a degenerate case, if you specify the same 3939/// input operands as the node already has, the input node is returned. 3940SDValue SelectionDAG::UpdateNodeOperands(SDValue InN, SDValue Op) { 3941 SDNode *N = InN.getNode(); 3942 assert(N->getNumOperands() == 1 && "Update with wrong number of operands"); 3943 3944 // Check to see if there is no change. 3945 if (Op == N->getOperand(0)) return InN; 3946 3947 // See if the modified node already exists. 3948 void *InsertPos = 0; 3949 if (SDNode *Existing = FindModifiedNodeSlot(N, Op, InsertPos)) 3950 return SDValue(Existing, InN.getResNo()); 3951 3952 // Nope it doesn't. Remove the node from its current place in the maps. 3953 if (InsertPos) 3954 if (!RemoveNodeFromCSEMaps(N)) 3955 InsertPos = 0; 3956 3957 // Now we update the operands. 3958 N->OperandList[0].set(Op); 3959 3960 // If this gets put into a CSE map, add it. 3961 if (InsertPos) CSEMap.InsertNode(N, InsertPos); 3962 return InN; 3963} 3964 3965SDValue SelectionDAG:: 3966UpdateNodeOperands(SDValue InN, SDValue Op1, SDValue Op2) { 3967 SDNode *N = InN.getNode(); 3968 assert(N->getNumOperands() == 2 && "Update with wrong number of operands"); 3969 3970 // Check to see if there is no change. 3971 if (Op1 == N->getOperand(0) && Op2 == N->getOperand(1)) 3972 return InN; // No operands changed, just return the input node. 3973 3974 // See if the modified node already exists. 3975 void *InsertPos = 0; 3976 if (SDNode *Existing = FindModifiedNodeSlot(N, Op1, Op2, InsertPos)) 3977 return SDValue(Existing, InN.getResNo()); 3978 3979 // Nope it doesn't. Remove the node from its current place in the maps. 3980 if (InsertPos) 3981 if (!RemoveNodeFromCSEMaps(N)) 3982 InsertPos = 0; 3983 3984 // Now we update the operands. 3985 if (N->OperandList[0] != Op1) 3986 N->OperandList[0].set(Op1); 3987 if (N->OperandList[1] != Op2) 3988 N->OperandList[1].set(Op2); 3989 3990 // If this gets put into a CSE map, add it. 3991 if (InsertPos) CSEMap.InsertNode(N, InsertPos); 3992 return InN; 3993} 3994 3995SDValue SelectionDAG:: 3996UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, SDValue Op3) { 3997 SDValue Ops[] = { Op1, Op2, Op3 }; 3998 return UpdateNodeOperands(N, Ops, 3); 3999} 4000 4001SDValue SelectionDAG:: 4002UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, 4003 SDValue Op3, SDValue Op4) { 4004 SDValue Ops[] = { Op1, Op2, Op3, Op4 }; 4005 return UpdateNodeOperands(N, Ops, 4); 4006} 4007 4008SDValue SelectionDAG:: 4009UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, 4010 SDValue Op3, SDValue Op4, SDValue Op5) { 4011 SDValue Ops[] = { Op1, Op2, Op3, Op4, Op5 }; 4012 return UpdateNodeOperands(N, Ops, 5); 4013} 4014 4015SDValue SelectionDAG:: 4016UpdateNodeOperands(SDValue InN, const SDValue *Ops, unsigned NumOps) { 4017 SDNode *N = InN.getNode(); 4018 assert(N->getNumOperands() == NumOps && 4019 "Update with wrong number of operands"); 4020 4021 // Check to see if there is no change. 4022 bool AnyChange = false; 4023 for (unsigned i = 0; i != NumOps; ++i) { 4024 if (Ops[i] != N->getOperand(i)) { 4025 AnyChange = true; 4026 break; 4027 } 4028 } 4029 4030 // No operands changed, just return the input node. 4031 if (!AnyChange) return InN; 4032 4033 // See if the modified node already exists. 4034 void *InsertPos = 0; 4035 if (SDNode *Existing = FindModifiedNodeSlot(N, Ops, NumOps, InsertPos)) 4036 return SDValue(Existing, InN.getResNo()); 4037 4038 // Nope it doesn't. Remove the node from its current place in the maps. 4039 if (InsertPos) 4040 if (!RemoveNodeFromCSEMaps(N)) 4041 InsertPos = 0; 4042 4043 // Now we update the operands. 4044 for (unsigned i = 0; i != NumOps; ++i) 4045 if (N->OperandList[i] != Ops[i]) 4046 N->OperandList[i].set(Ops[i]); 4047 4048 // If this gets put into a CSE map, add it. 4049 if (InsertPos) CSEMap.InsertNode(N, InsertPos); 4050 return InN; 4051} 4052 4053/// DropOperands - Release the operands and set this node to have 4054/// zero operands. 4055void SDNode::DropOperands() { 4056 // Unlike the code in MorphNodeTo that does this, we don't need to 4057 // watch for dead nodes here. 4058 for (op_iterator I = op_begin(), E = op_end(); I != E; ) { 4059 SDUse &Use = *I++; 4060 Use.set(SDValue()); 4061 } 4062} 4063 4064/// SelectNodeTo - These are wrappers around MorphNodeTo that accept a 4065/// machine opcode. 4066/// 4067SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4068 MVT VT) { 4069 SDVTList VTs = getVTList(VT); 4070 return SelectNodeTo(N, MachineOpc, VTs, 0, 0); 4071} 4072 4073SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4074 MVT VT, SDValue Op1) { 4075 SDVTList VTs = getVTList(VT); 4076 SDValue Ops[] = { Op1 }; 4077 return SelectNodeTo(N, MachineOpc, VTs, Ops, 1); 4078} 4079 4080SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4081 MVT VT, SDValue Op1, 4082 SDValue Op2) { 4083 SDVTList VTs = getVTList(VT); 4084 SDValue Ops[] = { Op1, Op2 }; 4085 return SelectNodeTo(N, MachineOpc, VTs, Ops, 2); 4086} 4087 4088SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4089 MVT VT, SDValue Op1, 4090 SDValue Op2, SDValue Op3) { 4091 SDVTList VTs = getVTList(VT); 4092 SDValue Ops[] = { Op1, Op2, Op3 }; 4093 return SelectNodeTo(N, MachineOpc, VTs, Ops, 3); 4094} 4095 4096SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4097 MVT VT, const SDValue *Ops, 4098 unsigned NumOps) { 4099 SDVTList VTs = getVTList(VT); 4100 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 4101} 4102 4103SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4104 MVT VT1, MVT VT2, const SDValue *Ops, 4105 unsigned NumOps) { 4106 SDVTList VTs = getVTList(VT1, VT2); 4107 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 4108} 4109 4110SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4111 MVT VT1, MVT VT2) { 4112 SDVTList VTs = getVTList(VT1, VT2); 4113 return SelectNodeTo(N, MachineOpc, VTs, (SDValue *)0, 0); 4114} 4115 4116SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4117 MVT VT1, MVT VT2, MVT VT3, 4118 const SDValue *Ops, unsigned NumOps) { 4119 SDVTList VTs = getVTList(VT1, VT2, VT3); 4120 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 4121} 4122 4123SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4124 MVT VT1, MVT VT2, MVT VT3, MVT VT4, 4125 const SDValue *Ops, unsigned NumOps) { 4126 SDVTList VTs = getVTList(VT1, VT2, VT3, VT4); 4127 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 4128} 4129 4130SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4131 MVT VT1, MVT VT2, 4132 SDValue Op1) { 4133 SDVTList VTs = getVTList(VT1, VT2); 4134 SDValue Ops[] = { Op1 }; 4135 return SelectNodeTo(N, MachineOpc, VTs, Ops, 1); 4136} 4137 4138SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4139 MVT VT1, MVT VT2, 4140 SDValue Op1, SDValue Op2) { 4141 SDVTList VTs = getVTList(VT1, VT2); 4142 SDValue Ops[] = { Op1, Op2 }; 4143 return SelectNodeTo(N, MachineOpc, VTs, Ops, 2); 4144} 4145 4146SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4147 MVT VT1, MVT VT2, 4148 SDValue Op1, SDValue Op2, 4149 SDValue Op3) { 4150 SDVTList VTs = getVTList(VT1, VT2); 4151 SDValue Ops[] = { Op1, Op2, Op3 }; 4152 return SelectNodeTo(N, MachineOpc, VTs, Ops, 3); 4153} 4154 4155SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4156 MVT VT1, MVT VT2, MVT VT3, 4157 SDValue Op1, SDValue Op2, 4158 SDValue Op3) { 4159 SDVTList VTs = getVTList(VT1, VT2, VT3); 4160 SDValue Ops[] = { Op1, Op2, Op3 }; 4161 return SelectNodeTo(N, MachineOpc, VTs, Ops, 3); 4162} 4163 4164SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4165 SDVTList VTs, const SDValue *Ops, 4166 unsigned NumOps) { 4167 return MorphNodeTo(N, ~MachineOpc, VTs, Ops, NumOps); 4168} 4169 4170SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4171 MVT VT) { 4172 SDVTList VTs = getVTList(VT); 4173 return MorphNodeTo(N, Opc, VTs, 0, 0); 4174} 4175 4176SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4177 MVT VT, SDValue Op1) { 4178 SDVTList VTs = getVTList(VT); 4179 SDValue Ops[] = { Op1 }; 4180 return MorphNodeTo(N, Opc, VTs, Ops, 1); 4181} 4182 4183SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4184 MVT VT, SDValue Op1, 4185 SDValue Op2) { 4186 SDVTList VTs = getVTList(VT); 4187 SDValue Ops[] = { Op1, Op2 }; 4188 return MorphNodeTo(N, Opc, VTs, Ops, 2); 4189} 4190 4191SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4192 MVT VT, SDValue Op1, 4193 SDValue Op2, SDValue Op3) { 4194 SDVTList VTs = getVTList(VT); 4195 SDValue Ops[] = { Op1, Op2, Op3 }; 4196 return MorphNodeTo(N, Opc, VTs, Ops, 3); 4197} 4198 4199SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4200 MVT VT, const SDValue *Ops, 4201 unsigned NumOps) { 4202 SDVTList VTs = getVTList(VT); 4203 return MorphNodeTo(N, Opc, VTs, Ops, NumOps); 4204} 4205 4206SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4207 MVT VT1, MVT VT2, const SDValue *Ops, 4208 unsigned NumOps) { 4209 SDVTList VTs = getVTList(VT1, VT2); 4210 return MorphNodeTo(N, Opc, VTs, Ops, NumOps); 4211} 4212 4213SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4214 MVT VT1, MVT VT2) { 4215 SDVTList VTs = getVTList(VT1, VT2); 4216 return MorphNodeTo(N, Opc, VTs, (SDValue *)0, 0); 4217} 4218 4219SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4220 MVT VT1, MVT VT2, MVT VT3, 4221 const SDValue *Ops, unsigned NumOps) { 4222 SDVTList VTs = getVTList(VT1, VT2, VT3); 4223 return MorphNodeTo(N, Opc, VTs, Ops, NumOps); 4224} 4225 4226SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4227 MVT VT1, MVT VT2, 4228 SDValue Op1) { 4229 SDVTList VTs = getVTList(VT1, VT2); 4230 SDValue Ops[] = { Op1 }; 4231 return MorphNodeTo(N, Opc, VTs, Ops, 1); 4232} 4233 4234SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4235 MVT VT1, MVT VT2, 4236 SDValue Op1, SDValue Op2) { 4237 SDVTList VTs = getVTList(VT1, VT2); 4238 SDValue Ops[] = { Op1, Op2 }; 4239 return MorphNodeTo(N, Opc, VTs, Ops, 2); 4240} 4241 4242SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4243 MVT VT1, MVT VT2, 4244 SDValue Op1, SDValue Op2, 4245 SDValue Op3) { 4246 SDVTList VTs = getVTList(VT1, VT2); 4247 SDValue Ops[] = { Op1, Op2, Op3 }; 4248 return MorphNodeTo(N, Opc, VTs, Ops, 3); 4249} 4250 4251/// MorphNodeTo - These *mutate* the specified node to have the specified 4252/// return type, opcode, and operands. 4253/// 4254/// Note that MorphNodeTo returns the resultant node. If there is already a 4255/// node of the specified opcode and operands, it returns that node instead of 4256/// the current one. Note that the DebugLoc need not be the same. 4257/// 4258/// Using MorphNodeTo is faster than creating a new node and swapping it in 4259/// with ReplaceAllUsesWith both because it often avoids allocating a new 4260/// node, and because it doesn't require CSE recalculation for any of 4261/// the node's users. 4262/// 4263SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4264 SDVTList VTs, const SDValue *Ops, 4265 unsigned NumOps) { 4266 // If an identical node already exists, use it. 4267 void *IP = 0; 4268 if (VTs.VTs[VTs.NumVTs-1] != MVT::Flag) { 4269 FoldingSetNodeID ID; 4270 AddNodeIDNode(ID, Opc, VTs, Ops, NumOps); 4271 if (SDNode *ON = CSEMap.FindNodeOrInsertPos(ID, IP)) 4272 return ON; 4273 } 4274 4275 if (!RemoveNodeFromCSEMaps(N)) 4276 IP = 0; 4277 4278 // Start the morphing. 4279 N->NodeType = Opc; 4280 N->ValueList = VTs.VTs; 4281 N->NumValues = VTs.NumVTs; 4282 4283 // Clear the operands list, updating used nodes to remove this from their 4284 // use list. Keep track of any operands that become dead as a result. 4285 SmallPtrSet<SDNode*, 16> DeadNodeSet; 4286 for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ) { 4287 SDUse &Use = *I++; 4288 SDNode *Used = Use.getNode(); 4289 Use.set(SDValue()); 4290 if (Used->use_empty()) 4291 DeadNodeSet.insert(Used); 4292 } 4293 4294 // If NumOps is larger than the # of operands we currently have, reallocate 4295 // the operand list. 4296 if (NumOps > N->NumOperands) { 4297 if (N->OperandsNeedDelete) 4298 delete[] N->OperandList; 4299 4300 if (N->isMachineOpcode()) { 4301 // We're creating a final node that will live unmorphed for the 4302 // remainder of the current SelectionDAG iteration, so we can allocate 4303 // the operands directly out of a pool with no recycling metadata. 4304 N->OperandList = OperandAllocator.Allocate<SDUse>(NumOps); 4305 N->OperandsNeedDelete = false; 4306 } else { 4307 N->OperandList = new SDUse[NumOps]; 4308 N->OperandsNeedDelete = true; 4309 } 4310 } 4311 4312 // Assign the new operands. 4313 N->NumOperands = NumOps; 4314 for (unsigned i = 0, e = NumOps; i != e; ++i) { 4315 N->OperandList[i].setUser(N); 4316 N->OperandList[i].setInitial(Ops[i]); 4317 } 4318 4319 // Delete any nodes that are still dead after adding the uses for the 4320 // new operands. 4321 SmallVector<SDNode *, 16> DeadNodes; 4322 for (SmallPtrSet<SDNode *, 16>::iterator I = DeadNodeSet.begin(), 4323 E = DeadNodeSet.end(); I != E; ++I) 4324 if ((*I)->use_empty()) 4325 DeadNodes.push_back(*I); 4326 RemoveDeadNodes(DeadNodes); 4327 4328 if (IP) 4329 CSEMap.InsertNode(N, IP); // Memoize the new node. 4330 return N; 4331} 4332 4333 4334/// getTargetNode - These are used for target selectors to create a new node 4335/// with specified return type(s), target opcode, and operands. 4336/// 4337/// Note that getTargetNode returns the resultant node. If there is already a 4338/// node of the specified opcode and operands, it returns that node instead of 4339/// the current one. 4340SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT) { 4341 return getNode(~Opcode, dl, VT).getNode(); 4342} 4343 4344SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, 4345 SDValue Op1) { 4346 return getNode(~Opcode, dl, VT, Op1).getNode(); 4347} 4348 4349SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, 4350 SDValue Op1, SDValue Op2) { 4351 return getNode(~Opcode, dl, VT, Op1, Op2).getNode(); 4352} 4353 4354SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, 4355 SDValue Op1, SDValue Op2, 4356 SDValue Op3) { 4357 return getNode(~Opcode, dl, VT, Op1, Op2, Op3).getNode(); 4358} 4359 4360SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, 4361 const SDValue *Ops, unsigned NumOps) { 4362 return getNode(~Opcode, dl, VT, Ops, NumOps).getNode(); 4363} 4364 4365SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, 4366 MVT VT1, MVT VT2) { 4367 SDVTList VTs = getVTList(VT1, VT2); 4368 SDValue Op; 4369 return getNode(~Opcode, dl, VTs, &Op, 0).getNode(); 4370} 4371 4372SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, 4373 MVT VT2, SDValue Op1) { 4374 SDVTList VTs = getVTList(VT1, VT2); 4375 return getNode(~Opcode, dl, VTs, &Op1, 1).getNode(); 4376} 4377 4378SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, 4379 MVT VT2, SDValue Op1, 4380 SDValue Op2) { 4381 SDVTList VTs = getVTList(VT1, VT2); 4382 SDValue Ops[] = { Op1, Op2 }; 4383 return getNode(~Opcode, dl, VTs, Ops, 2).getNode(); 4384} 4385 4386SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, 4387 MVT VT2, SDValue Op1, 4388 SDValue Op2, SDValue Op3) { 4389 SDVTList VTs = getVTList(VT1, VT2); 4390 SDValue Ops[] = { Op1, Op2, Op3 }; 4391 return getNode(~Opcode, dl, VTs, Ops, 3).getNode(); 4392} 4393 4394SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, 4395 MVT VT1, MVT VT2, 4396 const SDValue *Ops, unsigned NumOps) { 4397 SDVTList VTs = getVTList(VT1, VT2); 4398 return getNode(~Opcode, dl, VTs, Ops, NumOps).getNode(); 4399} 4400 4401SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, 4402 MVT VT1, MVT VT2, MVT VT3, 4403 SDValue Op1, SDValue Op2) { 4404 SDVTList VTs = getVTList(VT1, VT2, VT3); 4405 SDValue Ops[] = { Op1, Op2 }; 4406 return getNode(~Opcode, dl, VTs, Ops, 2).getNode(); 4407} 4408 4409SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, 4410 MVT VT1, MVT VT2, MVT VT3, 4411 SDValue Op1, SDValue Op2, 4412 SDValue Op3) { 4413 SDVTList VTs = getVTList(VT1, VT2, VT3); 4414 SDValue Ops[] = { Op1, Op2, Op3 }; 4415 return getNode(~Opcode, dl, VTs, Ops, 3).getNode(); 4416} 4417 4418SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, 4419 MVT VT1, MVT VT2, MVT VT3, 4420 const SDValue *Ops, unsigned NumOps) { 4421 SDVTList VTs = getVTList(VT1, VT2, VT3); 4422 return getNode(~Opcode, dl, VTs, Ops, NumOps).getNode(); 4423} 4424 4425SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, 4426 MVT VT2, MVT VT3, MVT VT4, 4427 const SDValue *Ops, unsigned NumOps) { 4428 SDVTList VTs = getVTList(VT1, VT2, VT3, VT4); 4429 return getNode(~Opcode, dl, VTs, Ops, NumOps).getNode(); 4430} 4431 4432SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, 4433 const std::vector<MVT> &ResultTys, 4434 const SDValue *Ops, unsigned NumOps) { 4435 return getNode(~Opcode, dl, ResultTys, Ops, NumOps).getNode(); 4436} 4437 4438/// getNodeIfExists - Get the specified node if it's already available, or 4439/// else return NULL. 4440SDNode *SelectionDAG::getNodeIfExists(unsigned Opcode, SDVTList VTList, 4441 const SDValue *Ops, unsigned NumOps) { 4442 if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) { 4443 FoldingSetNodeID ID; 4444 AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps); 4445 void *IP = 0; 4446 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 4447 return E; 4448 } 4449 return NULL; 4450} 4451 4452/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. 4453/// This can cause recursive merging of nodes in the DAG. 4454/// 4455/// This version assumes From has a single result value. 4456/// 4457void SelectionDAG::ReplaceAllUsesWith(SDValue FromN, SDValue To, 4458 DAGUpdateListener *UpdateListener) { 4459 SDNode *From = FromN.getNode(); 4460 assert(From->getNumValues() == 1 && FromN.getResNo() == 0 && 4461 "Cannot replace with this method!"); 4462 assert(From != To.getNode() && "Cannot replace uses of with self"); 4463 4464 // Iterate over all the existing uses of From. New uses will be added 4465 // to the beginning of the use list, which we avoid visiting. 4466 // This specifically avoids visiting uses of From that arise while the 4467 // replacement is happening, because any such uses would be the result 4468 // of CSE: If an existing node looks like From after one of its operands 4469 // is replaced by To, we don't want to replace of all its users with To 4470 // too. See PR3018 for more info. 4471 SDNode::use_iterator UI = From->use_begin(), UE = From->use_end(); 4472 while (UI != UE) { 4473 SDNode *User = *UI; 4474 4475 // This node is about to morph, remove its old self from the CSE maps. 4476 RemoveNodeFromCSEMaps(User); 4477 4478 // A user can appear in a use list multiple times, and when this 4479 // happens the uses are usually next to each other in the list. 4480 // To help reduce the number of CSE recomputations, process all 4481 // the uses of this user that we can find this way. 4482 do { 4483 SDUse &Use = UI.getUse(); 4484 ++UI; 4485 Use.set(To); 4486 } while (UI != UE && *UI == User); 4487 4488 // Now that we have modified User, add it back to the CSE maps. If it 4489 // already exists there, recursively merge the results together. 4490 AddModifiedNodeToCSEMaps(User, UpdateListener); 4491 } 4492} 4493 4494/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. 4495/// This can cause recursive merging of nodes in the DAG. 4496/// 4497/// This version assumes that for each value of From, there is a 4498/// corresponding value in To in the same position with the same type. 4499/// 4500void SelectionDAG::ReplaceAllUsesWith(SDNode *From, SDNode *To, 4501 DAGUpdateListener *UpdateListener) { 4502#ifndef NDEBUG 4503 for (unsigned i = 0, e = From->getNumValues(); i != e; ++i) 4504 assert((!From->hasAnyUseOfValue(i) || 4505 From->getValueType(i) == To->getValueType(i)) && 4506 "Cannot use this version of ReplaceAllUsesWith!"); 4507#endif 4508 4509 // Handle the trivial case. 4510 if (From == To) 4511 return; 4512 4513 // Iterate over just the existing users of From. See the comments in 4514 // the ReplaceAllUsesWith above. 4515 SDNode::use_iterator UI = From->use_begin(), UE = From->use_end(); 4516 while (UI != UE) { 4517 SDNode *User = *UI; 4518 4519 // This node is about to morph, remove its old self from the CSE maps. 4520 RemoveNodeFromCSEMaps(User); 4521 4522 // A user can appear in a use list multiple times, and when this 4523 // happens the uses are usually next to each other in the list. 4524 // To help reduce the number of CSE recomputations, process all 4525 // the uses of this user that we can find this way. 4526 do { 4527 SDUse &Use = UI.getUse(); 4528 ++UI; 4529 Use.setNode(To); 4530 } while (UI != UE && *UI == User); 4531 4532 // Now that we have modified User, add it back to the CSE maps. If it 4533 // already exists there, recursively merge the results together. 4534 AddModifiedNodeToCSEMaps(User, UpdateListener); 4535 } 4536} 4537 4538/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. 4539/// This can cause recursive merging of nodes in the DAG. 4540/// 4541/// This version can replace From with any result values. To must match the 4542/// number and types of values returned by From. 4543void SelectionDAG::ReplaceAllUsesWith(SDNode *From, 4544 const SDValue *To, 4545 DAGUpdateListener *UpdateListener) { 4546 if (From->getNumValues() == 1) // Handle the simple case efficiently. 4547 return ReplaceAllUsesWith(SDValue(From, 0), To[0], UpdateListener); 4548 4549 // Iterate over just the existing users of From. See the comments in 4550 // the ReplaceAllUsesWith above. 4551 SDNode::use_iterator UI = From->use_begin(), UE = From->use_end(); 4552 while (UI != UE) { 4553 SDNode *User = *UI; 4554 4555 // This node is about to morph, remove its old self from the CSE maps. 4556 RemoveNodeFromCSEMaps(User); 4557 4558 // A user can appear in a use list multiple times, and when this 4559 // happens the uses are usually next to each other in the list. 4560 // To help reduce the number of CSE recomputations, process all 4561 // the uses of this user that we can find this way. 4562 do { 4563 SDUse &Use = UI.getUse(); 4564 const SDValue &ToOp = To[Use.getResNo()]; 4565 ++UI; 4566 Use.set(ToOp); 4567 } while (UI != UE && *UI == User); 4568 4569 // Now that we have modified User, add it back to the CSE maps. If it 4570 // already exists there, recursively merge the results together. 4571 AddModifiedNodeToCSEMaps(User, UpdateListener); 4572 } 4573} 4574 4575/// ReplaceAllUsesOfValueWith - Replace any uses of From with To, leaving 4576/// uses of other values produced by From.getNode() alone. The Deleted 4577/// vector is handled the same way as for ReplaceAllUsesWith. 4578void SelectionDAG::ReplaceAllUsesOfValueWith(SDValue From, SDValue To, 4579 DAGUpdateListener *UpdateListener){ 4580 // Handle the really simple, really trivial case efficiently. 4581 if (From == To) return; 4582 4583 // Handle the simple, trivial, case efficiently. 4584 if (From.getNode()->getNumValues() == 1) { 4585 ReplaceAllUsesWith(From, To, UpdateListener); 4586 return; 4587 } 4588 4589 // Iterate over just the existing users of From. See the comments in 4590 // the ReplaceAllUsesWith above. 4591 SDNode::use_iterator UI = From.getNode()->use_begin(), 4592 UE = From.getNode()->use_end(); 4593 while (UI != UE) { 4594 SDNode *User = *UI; 4595 bool UserRemovedFromCSEMaps = false; 4596 4597 // A user can appear in a use list multiple times, and when this 4598 // happens the uses are usually next to each other in the list. 4599 // To help reduce the number of CSE recomputations, process all 4600 // the uses of this user that we can find this way. 4601 do { 4602 SDUse &Use = UI.getUse(); 4603 4604 // Skip uses of different values from the same node. 4605 if (Use.getResNo() != From.getResNo()) { 4606 ++UI; 4607 continue; 4608 } 4609 4610 // If this node hasn't been modified yet, it's still in the CSE maps, 4611 // so remove its old self from the CSE maps. 4612 if (!UserRemovedFromCSEMaps) { 4613 RemoveNodeFromCSEMaps(User); 4614 UserRemovedFromCSEMaps = true; 4615 } 4616 4617 ++UI; 4618 Use.set(To); 4619 } while (UI != UE && *UI == User); 4620 4621 // We are iterating over all uses of the From node, so if a use 4622 // doesn't use the specific value, no changes are made. 4623 if (!UserRemovedFromCSEMaps) 4624 continue; 4625 4626 // Now that we have modified User, add it back to the CSE maps. If it 4627 // already exists there, recursively merge the results together. 4628 AddModifiedNodeToCSEMaps(User, UpdateListener); 4629 } 4630} 4631 4632namespace { 4633 /// UseMemo - This class is used by SelectionDAG::ReplaceAllUsesOfValuesWith 4634 /// to record information about a use. 4635 struct UseMemo { 4636 SDNode *User; 4637 unsigned Index; 4638 SDUse *Use; 4639 }; 4640 4641 /// operator< - Sort Memos by User. 4642 bool operator<(const UseMemo &L, const UseMemo &R) { 4643 return (intptr_t)L.User < (intptr_t)R.User; 4644 } 4645} 4646 4647/// ReplaceAllUsesOfValuesWith - Replace any uses of From with To, leaving 4648/// uses of other values produced by From.getNode() alone. The same value 4649/// may appear in both the From and To list. The Deleted vector is 4650/// handled the same way as for ReplaceAllUsesWith. 4651void SelectionDAG::ReplaceAllUsesOfValuesWith(const SDValue *From, 4652 const SDValue *To, 4653 unsigned Num, 4654 DAGUpdateListener *UpdateListener){ 4655 // Handle the simple, trivial case efficiently. 4656 if (Num == 1) 4657 return ReplaceAllUsesOfValueWith(*From, *To, UpdateListener); 4658 4659 // Read up all the uses and make records of them. This helps 4660 // processing new uses that are introduced during the 4661 // replacement process. 4662 SmallVector<UseMemo, 4> Uses; 4663 for (unsigned i = 0; i != Num; ++i) { 4664 unsigned FromResNo = From[i].getResNo(); 4665 SDNode *FromNode = From[i].getNode(); 4666 for (SDNode::use_iterator UI = FromNode->use_begin(), 4667 E = FromNode->use_end(); UI != E; ++UI) { 4668 SDUse &Use = UI.getUse(); 4669 if (Use.getResNo() == FromResNo) { 4670 UseMemo Memo = { *UI, i, &Use }; 4671 Uses.push_back(Memo); 4672 } 4673 } 4674 } 4675 4676 // Sort the uses, so that all the uses from a given User are together. 4677 std::sort(Uses.begin(), Uses.end()); 4678 4679 for (unsigned UseIndex = 0, UseIndexEnd = Uses.size(); 4680 UseIndex != UseIndexEnd; ) { 4681 // We know that this user uses some value of From. If it is the right 4682 // value, update it. 4683 SDNode *User = Uses[UseIndex].User; 4684 4685 // This node is about to morph, remove its old self from the CSE maps. 4686 RemoveNodeFromCSEMaps(User); 4687 4688 // The Uses array is sorted, so all the uses for a given User 4689 // are next to each other in the list. 4690 // To help reduce the number of CSE recomputations, process all 4691 // the uses of this user that we can find this way. 4692 do { 4693 unsigned i = Uses[UseIndex].Index; 4694 SDUse &Use = *Uses[UseIndex].Use; 4695 ++UseIndex; 4696 4697 Use.set(To[i]); 4698 } while (UseIndex != UseIndexEnd && Uses[UseIndex].User == User); 4699 4700 // Now that we have modified User, add it back to the CSE maps. If it 4701 // already exists there, recursively merge the results together. 4702 AddModifiedNodeToCSEMaps(User, UpdateListener); 4703 } 4704} 4705 4706/// AssignTopologicalOrder - Assign a unique node id for each node in the DAG 4707/// based on their topological order. It returns the maximum id and a vector 4708/// of the SDNodes* in assigned order by reference. 4709unsigned SelectionDAG::AssignTopologicalOrder() { 4710 4711 unsigned DAGSize = 0; 4712 4713 // SortedPos tracks the progress of the algorithm. Nodes before it are 4714 // sorted, nodes after it are unsorted. When the algorithm completes 4715 // it is at the end of the list. 4716 allnodes_iterator SortedPos = allnodes_begin(); 4717 4718 // Visit all the nodes. Move nodes with no operands to the front of 4719 // the list immediately. Annotate nodes that do have operands with their 4720 // operand count. Before we do this, the Node Id fields of the nodes 4721 // may contain arbitrary values. After, the Node Id fields for nodes 4722 // before SortedPos will contain the topological sort index, and the 4723 // Node Id fields for nodes At SortedPos and after will contain the 4724 // count of outstanding operands. 4725 for (allnodes_iterator I = allnodes_begin(),E = allnodes_end(); I != E; ) { 4726 SDNode *N = I++; 4727 unsigned Degree = N->getNumOperands(); 4728 if (Degree == 0) { 4729 // A node with no uses, add it to the result array immediately. 4730 N->setNodeId(DAGSize++); 4731 allnodes_iterator Q = N; 4732 if (Q != SortedPos) 4733 SortedPos = AllNodes.insert(SortedPos, AllNodes.remove(Q)); 4734 ++SortedPos; 4735 } else { 4736 // Temporarily use the Node Id as scratch space for the degree count. 4737 N->setNodeId(Degree); 4738 } 4739 } 4740 4741 // Visit all the nodes. As we iterate, moves nodes into sorted order, 4742 // such that by the time the end is reached all nodes will be sorted. 4743 for (allnodes_iterator I = allnodes_begin(),E = allnodes_end(); I != E; ++I) { 4744 SDNode *N = I; 4745 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 4746 UI != UE; ++UI) { 4747 SDNode *P = *UI; 4748 unsigned Degree = P->getNodeId(); 4749 --Degree; 4750 if (Degree == 0) { 4751 // All of P's operands are sorted, so P may sorted now. 4752 P->setNodeId(DAGSize++); 4753 if (P != SortedPos) 4754 SortedPos = AllNodes.insert(SortedPos, AllNodes.remove(P)); 4755 ++SortedPos; 4756 } else { 4757 // Update P's outstanding operand count. 4758 P->setNodeId(Degree); 4759 } 4760 } 4761 } 4762 4763 assert(SortedPos == AllNodes.end() && 4764 "Topological sort incomplete!"); 4765 assert(AllNodes.front().getOpcode() == ISD::EntryToken && 4766 "First node in topological sort is not the entry token!"); 4767 assert(AllNodes.front().getNodeId() == 0 && 4768 "First node in topological sort has non-zero id!"); 4769 assert(AllNodes.front().getNumOperands() == 0 && 4770 "First node in topological sort has operands!"); 4771 assert(AllNodes.back().getNodeId() == (int)DAGSize-1 && 4772 "Last node in topologic sort has unexpected id!"); 4773 assert(AllNodes.back().use_empty() && 4774 "Last node in topologic sort has users!"); 4775 assert(DAGSize == allnodes_size() && "Node count mismatch!"); 4776 return DAGSize; 4777} 4778 4779 4780 4781//===----------------------------------------------------------------------===// 4782// SDNode Class 4783//===----------------------------------------------------------------------===// 4784 4785HandleSDNode::~HandleSDNode() { 4786 DropOperands(); 4787} 4788 4789GlobalAddressSDNode::GlobalAddressSDNode(bool isTarget, const GlobalValue *GA, 4790 MVT VT, int64_t o) 4791 : SDNode(isa<GlobalVariable>(GA) && 4792 cast<GlobalVariable>(GA)->isThreadLocal() ? 4793 // Thread Local 4794 (isTarget ? ISD::TargetGlobalTLSAddress : ISD::GlobalTLSAddress) : 4795 // Non Thread Local 4796 (isTarget ? ISD::TargetGlobalAddress : ISD::GlobalAddress), 4797 DebugLoc::getUnknownLoc(), getSDVTList(VT)), Offset(o) { 4798 TheGlobal = const_cast<GlobalValue*>(GA); 4799} 4800 4801MemSDNode::MemSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, MVT memvt, 4802 const Value *srcValue, int SVO, 4803 unsigned alignment, bool vol) 4804 : SDNode(Opc, dl, VTs), MemoryVT(memvt), SrcValue(srcValue), SVOffset(SVO) { 4805 SubclassData = encodeMemSDNodeFlags(0, ISD::UNINDEXED, vol, alignment); 4806 assert(isPowerOf2_32(alignment) && "Alignment is not a power of 2!"); 4807 assert(getAlignment() == alignment && "Alignment representation error!"); 4808 assert(isVolatile() == vol && "Volatile representation error!"); 4809} 4810 4811MemSDNode::MemSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, 4812 const SDValue *Ops, 4813 unsigned NumOps, MVT memvt, const Value *srcValue, 4814 int SVO, unsigned alignment, bool vol) 4815 : SDNode(Opc, dl, VTs, Ops, NumOps), 4816 MemoryVT(memvt), SrcValue(srcValue), SVOffset(SVO) { 4817 SubclassData = encodeMemSDNodeFlags(0, ISD::UNINDEXED, vol, alignment); 4818 assert(isPowerOf2_32(alignment) && "Alignment is not a power of 2!"); 4819 assert(getAlignment() == alignment && "Alignment representation error!"); 4820 assert(isVolatile() == vol && "Volatile representation error!"); 4821} 4822 4823/// getMemOperand - Return a MachineMemOperand object describing the memory 4824/// reference performed by this memory reference. 4825MachineMemOperand MemSDNode::getMemOperand() const { 4826 int Flags = 0; 4827 if (isa<LoadSDNode>(this)) 4828 Flags = MachineMemOperand::MOLoad; 4829 else if (isa<StoreSDNode>(this)) 4830 Flags = MachineMemOperand::MOStore; 4831 else if (isa<AtomicSDNode>(this)) { 4832 Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore; 4833 } 4834 else { 4835 const MemIntrinsicSDNode* MemIntrinNode = dyn_cast<MemIntrinsicSDNode>(this); 4836 assert(MemIntrinNode && "Unknown MemSDNode opcode!"); 4837 if (MemIntrinNode->readMem()) Flags |= MachineMemOperand::MOLoad; 4838 if (MemIntrinNode->writeMem()) Flags |= MachineMemOperand::MOStore; 4839 } 4840 4841 int Size = (getMemoryVT().getSizeInBits() + 7) >> 3; 4842 if (isVolatile()) Flags |= MachineMemOperand::MOVolatile; 4843 4844 // Check if the memory reference references a frame index 4845 const FrameIndexSDNode *FI = 4846 dyn_cast<const FrameIndexSDNode>(getBasePtr().getNode()); 4847 if (!getSrcValue() && FI) 4848 return MachineMemOperand(PseudoSourceValue::getFixedStack(FI->getIndex()), 4849 Flags, 0, Size, getAlignment()); 4850 else 4851 return MachineMemOperand(getSrcValue(), Flags, getSrcValueOffset(), 4852 Size, getAlignment()); 4853} 4854 4855/// Profile - Gather unique data for the node. 4856/// 4857void SDNode::Profile(FoldingSetNodeID &ID) const { 4858 AddNodeIDNode(ID, this); 4859} 4860 4861/// getValueTypeList - Return a pointer to the specified value type. 4862/// 4863const MVT *SDNode::getValueTypeList(MVT VT) { 4864 if (VT.isExtended()) { 4865 static std::set<MVT, MVT::compareRawBits> EVTs; 4866 return &(*EVTs.insert(VT).first); 4867 } else { 4868 static MVT VTs[MVT::LAST_VALUETYPE]; 4869 VTs[VT.getSimpleVT()] = VT; 4870 return &VTs[VT.getSimpleVT()]; 4871 } 4872} 4873 4874/// hasNUsesOfValue - Return true if there are exactly NUSES uses of the 4875/// indicated value. This method ignores uses of other values defined by this 4876/// operation. 4877bool SDNode::hasNUsesOfValue(unsigned NUses, unsigned Value) const { 4878 assert(Value < getNumValues() && "Bad value!"); 4879 4880 // TODO: Only iterate over uses of a given value of the node 4881 for (SDNode::use_iterator UI = use_begin(), E = use_end(); UI != E; ++UI) { 4882 if (UI.getUse().getResNo() == Value) { 4883 if (NUses == 0) 4884 return false; 4885 --NUses; 4886 } 4887 } 4888 4889 // Found exactly the right number of uses? 4890 return NUses == 0; 4891} 4892 4893 4894/// hasAnyUseOfValue - Return true if there are any use of the indicated 4895/// value. This method ignores uses of other values defined by this operation. 4896bool SDNode::hasAnyUseOfValue(unsigned Value) const { 4897 assert(Value < getNumValues() && "Bad value!"); 4898 4899 for (SDNode::use_iterator UI = use_begin(), E = use_end(); UI != E; ++UI) 4900 if (UI.getUse().getResNo() == Value) 4901 return true; 4902 4903 return false; 4904} 4905 4906 4907/// isOnlyUserOf - Return true if this node is the only use of N. 4908/// 4909bool SDNode::isOnlyUserOf(SDNode *N) const { 4910 bool Seen = false; 4911 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 4912 SDNode *User = *I; 4913 if (User == this) 4914 Seen = true; 4915 else 4916 return false; 4917 } 4918 4919 return Seen; 4920} 4921 4922/// isOperand - Return true if this node is an operand of N. 4923/// 4924bool SDValue::isOperandOf(SDNode *N) const { 4925 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 4926 if (*this == N->getOperand(i)) 4927 return true; 4928 return false; 4929} 4930 4931bool SDNode::isOperandOf(SDNode *N) const { 4932 for (unsigned i = 0, e = N->NumOperands; i != e; ++i) 4933 if (this == N->OperandList[i].getNode()) 4934 return true; 4935 return false; 4936} 4937 4938/// reachesChainWithoutSideEffects - Return true if this operand (which must 4939/// be a chain) reaches the specified operand without crossing any 4940/// side-effecting instructions. In practice, this looks through token 4941/// factors and non-volatile loads. In order to remain efficient, this only 4942/// looks a couple of nodes in, it does not do an exhaustive search. 4943bool SDValue::reachesChainWithoutSideEffects(SDValue Dest, 4944 unsigned Depth) const { 4945 if (*this == Dest) return true; 4946 4947 // Don't search too deeply, we just want to be able to see through 4948 // TokenFactor's etc. 4949 if (Depth == 0) return false; 4950 4951 // If this is a token factor, all inputs to the TF happen in parallel. If any 4952 // of the operands of the TF reach dest, then we can do the xform. 4953 if (getOpcode() == ISD::TokenFactor) { 4954 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) 4955 if (getOperand(i).reachesChainWithoutSideEffects(Dest, Depth-1)) 4956 return true; 4957 return false; 4958 } 4959 4960 // Loads don't have side effects, look through them. 4961 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(*this)) { 4962 if (!Ld->isVolatile()) 4963 return Ld->getChain().reachesChainWithoutSideEffects(Dest, Depth-1); 4964 } 4965 return false; 4966} 4967 4968 4969static void findPredecessor(SDNode *N, const SDNode *P, bool &found, 4970 SmallPtrSet<SDNode *, 32> &Visited) { 4971 if (found || !Visited.insert(N)) 4972 return; 4973 4974 for (unsigned i = 0, e = N->getNumOperands(); !found && i != e; ++i) { 4975 SDNode *Op = N->getOperand(i).getNode(); 4976 if (Op == P) { 4977 found = true; 4978 return; 4979 } 4980 findPredecessor(Op, P, found, Visited); 4981 } 4982} 4983 4984/// isPredecessorOf - Return true if this node is a predecessor of N. This node 4985/// is either an operand of N or it can be reached by recursively traversing 4986/// up the operands. 4987/// NOTE: this is an expensive method. Use it carefully. 4988bool SDNode::isPredecessorOf(SDNode *N) const { 4989 SmallPtrSet<SDNode *, 32> Visited; 4990 bool found = false; 4991 findPredecessor(N, this, found, Visited); 4992 return found; 4993} 4994 4995uint64_t SDNode::getConstantOperandVal(unsigned Num) const { 4996 assert(Num < NumOperands && "Invalid child # of SDNode!"); 4997 return cast<ConstantSDNode>(OperandList[Num])->getZExtValue(); 4998} 4999 5000std::string SDNode::getOperationName(const SelectionDAG *G) const { 5001 switch (getOpcode()) { 5002 default: 5003 if (getOpcode() < ISD::BUILTIN_OP_END) 5004 return "<<Unknown DAG Node>>"; 5005 if (isMachineOpcode()) { 5006 if (G) 5007 if (const TargetInstrInfo *TII = G->getTarget().getInstrInfo()) 5008 if (getMachineOpcode() < TII->getNumOpcodes()) 5009 return TII->get(getMachineOpcode()).getName(); 5010 return "<<Unknown Machine Node>>"; 5011 } 5012 if (G) { 5013 const TargetLowering &TLI = G->getTargetLoweringInfo(); 5014 const char *Name = TLI.getTargetNodeName(getOpcode()); 5015 if (Name) return Name; 5016 return "<<Unknown Target Node>>"; 5017 } 5018 return "<<Unknown Node>>"; 5019 5020#ifndef NDEBUG 5021 case ISD::DELETED_NODE: 5022 return "<<Deleted Node!>>"; 5023#endif 5024 case ISD::PREFETCH: return "Prefetch"; 5025 case ISD::MEMBARRIER: return "MemBarrier"; 5026 case ISD::ATOMIC_CMP_SWAP: return "AtomicCmpSwap"; 5027 case ISD::ATOMIC_SWAP: return "AtomicSwap"; 5028 case ISD::ATOMIC_LOAD_ADD: return "AtomicLoadAdd"; 5029 case ISD::ATOMIC_LOAD_SUB: return "AtomicLoadSub"; 5030 case ISD::ATOMIC_LOAD_AND: return "AtomicLoadAnd"; 5031 case ISD::ATOMIC_LOAD_OR: return "AtomicLoadOr"; 5032 case ISD::ATOMIC_LOAD_XOR: return "AtomicLoadXor"; 5033 case ISD::ATOMIC_LOAD_NAND: return "AtomicLoadNand"; 5034 case ISD::ATOMIC_LOAD_MIN: return "AtomicLoadMin"; 5035 case ISD::ATOMIC_LOAD_MAX: return "AtomicLoadMax"; 5036 case ISD::ATOMIC_LOAD_UMIN: return "AtomicLoadUMin"; 5037 case ISD::ATOMIC_LOAD_UMAX: return "AtomicLoadUMax"; 5038 case ISD::PCMARKER: return "PCMarker"; 5039 case ISD::READCYCLECOUNTER: return "ReadCycleCounter"; 5040 case ISD::SRCVALUE: return "SrcValue"; 5041 case ISD::MEMOPERAND: return "MemOperand"; 5042 case ISD::EntryToken: return "EntryToken"; 5043 case ISD::TokenFactor: return "TokenFactor"; 5044 case ISD::AssertSext: return "AssertSext"; 5045 case ISD::AssertZext: return "AssertZext"; 5046 5047 case ISD::BasicBlock: return "BasicBlock"; 5048 case ISD::ARG_FLAGS: return "ArgFlags"; 5049 case ISD::VALUETYPE: return "ValueType"; 5050 case ISD::Register: return "Register"; 5051 5052 case ISD::Constant: return "Constant"; 5053 case ISD::ConstantFP: return "ConstantFP"; 5054 case ISD::GlobalAddress: return "GlobalAddress"; 5055 case ISD::GlobalTLSAddress: return "GlobalTLSAddress"; 5056 case ISD::FrameIndex: return "FrameIndex"; 5057 case ISD::JumpTable: return "JumpTable"; 5058 case ISD::GLOBAL_OFFSET_TABLE: return "GLOBAL_OFFSET_TABLE"; 5059 case ISD::RETURNADDR: return "RETURNADDR"; 5060 case ISD::FRAMEADDR: return "FRAMEADDR"; 5061 case ISD::FRAME_TO_ARGS_OFFSET: return "FRAME_TO_ARGS_OFFSET"; 5062 case ISD::EXCEPTIONADDR: return "EXCEPTIONADDR"; 5063 case ISD::EHSELECTION: return "EHSELECTION"; 5064 case ISD::EH_RETURN: return "EH_RETURN"; 5065 case ISD::ConstantPool: return "ConstantPool"; 5066 case ISD::ExternalSymbol: return "ExternalSymbol"; 5067 case ISD::INTRINSIC_WO_CHAIN: { 5068 unsigned IID = cast<ConstantSDNode>(getOperand(0))->getZExtValue(); 5069 return Intrinsic::getName((Intrinsic::ID)IID); 5070 } 5071 case ISD::INTRINSIC_VOID: 5072 case ISD::INTRINSIC_W_CHAIN: { 5073 unsigned IID = cast<ConstantSDNode>(getOperand(1))->getZExtValue(); 5074 return Intrinsic::getName((Intrinsic::ID)IID); 5075 } 5076 5077 case ISD::BUILD_VECTOR: return "BUILD_VECTOR"; 5078 case ISD::TargetConstant: return "TargetConstant"; 5079 case ISD::TargetConstantFP:return "TargetConstantFP"; 5080 case ISD::TargetGlobalAddress: return "TargetGlobalAddress"; 5081 case ISD::TargetGlobalTLSAddress: return "TargetGlobalTLSAddress"; 5082 case ISD::TargetFrameIndex: return "TargetFrameIndex"; 5083 case ISD::TargetJumpTable: return "TargetJumpTable"; 5084 case ISD::TargetConstantPool: return "TargetConstantPool"; 5085 case ISD::TargetExternalSymbol: return "TargetExternalSymbol"; 5086 5087 case ISD::CopyToReg: return "CopyToReg"; 5088 case ISD::CopyFromReg: return "CopyFromReg"; 5089 case ISD::UNDEF: return "undef"; 5090 case ISD::MERGE_VALUES: return "merge_values"; 5091 case ISD::INLINEASM: return "inlineasm"; 5092 case ISD::DBG_LABEL: return "dbg_label"; 5093 case ISD::EH_LABEL: return "eh_label"; 5094 case ISD::DECLARE: return "declare"; 5095 case ISD::HANDLENODE: return "handlenode"; 5096 case ISD::FORMAL_ARGUMENTS: return "formal_arguments"; 5097 case ISD::CALL: return "call"; 5098 5099 // Unary operators 5100 case ISD::FABS: return "fabs"; 5101 case ISD::FNEG: return "fneg"; 5102 case ISD::FSQRT: return "fsqrt"; 5103 case ISD::FSIN: return "fsin"; 5104 case ISD::FCOS: return "fcos"; 5105 case ISD::FPOWI: return "fpowi"; 5106 case ISD::FPOW: return "fpow"; 5107 case ISD::FTRUNC: return "ftrunc"; 5108 case ISD::FFLOOR: return "ffloor"; 5109 case ISD::FCEIL: return "fceil"; 5110 case ISD::FRINT: return "frint"; 5111 case ISD::FNEARBYINT: return "fnearbyint"; 5112 5113 // Binary operators 5114 case ISD::ADD: return "add"; 5115 case ISD::SUB: return "sub"; 5116 case ISD::MUL: return "mul"; 5117 case ISD::MULHU: return "mulhu"; 5118 case ISD::MULHS: return "mulhs"; 5119 case ISD::SDIV: return "sdiv"; 5120 case ISD::UDIV: return "udiv"; 5121 case ISD::SREM: return "srem"; 5122 case ISD::UREM: return "urem"; 5123 case ISD::SMUL_LOHI: return "smul_lohi"; 5124 case ISD::UMUL_LOHI: return "umul_lohi"; 5125 case ISD::SDIVREM: return "sdivrem"; 5126 case ISD::UDIVREM: return "udivrem"; 5127 case ISD::AND: return "and"; 5128 case ISD::OR: return "or"; 5129 case ISD::XOR: return "xor"; 5130 case ISD::SHL: return "shl"; 5131 case ISD::SRA: return "sra"; 5132 case ISD::SRL: return "srl"; 5133 case ISD::ROTL: return "rotl"; 5134 case ISD::ROTR: return "rotr"; 5135 case ISD::FADD: return "fadd"; 5136 case ISD::FSUB: return "fsub"; 5137 case ISD::FMUL: return "fmul"; 5138 case ISD::FDIV: return "fdiv"; 5139 case ISD::FREM: return "frem"; 5140 case ISD::FCOPYSIGN: return "fcopysign"; 5141 case ISD::FGETSIGN: return "fgetsign"; 5142 5143 case ISD::SETCC: return "setcc"; 5144 case ISD::VSETCC: return "vsetcc"; 5145 case ISD::SELECT: return "select"; 5146 case ISD::SELECT_CC: return "select_cc"; 5147 case ISD::INSERT_VECTOR_ELT: return "insert_vector_elt"; 5148 case ISD::EXTRACT_VECTOR_ELT: return "extract_vector_elt"; 5149 case ISD::CONCAT_VECTORS: return "concat_vectors"; 5150 case ISD::EXTRACT_SUBVECTOR: return "extract_subvector"; 5151 case ISD::SCALAR_TO_VECTOR: return "scalar_to_vector"; 5152 case ISD::VECTOR_SHUFFLE: return "vector_shuffle"; 5153 case ISD::CARRY_FALSE: return "carry_false"; 5154 case ISD::ADDC: return "addc"; 5155 case ISD::ADDE: return "adde"; 5156 case ISD::SADDO: return "saddo"; 5157 case ISD::UADDO: return "uaddo"; 5158 case ISD::SSUBO: return "ssubo"; 5159 case ISD::USUBO: return "usubo"; 5160 case ISD::SMULO: return "smulo"; 5161 case ISD::UMULO: return "umulo"; 5162 case ISD::SUBC: return "subc"; 5163 case ISD::SUBE: return "sube"; 5164 case ISD::SHL_PARTS: return "shl_parts"; 5165 case ISD::SRA_PARTS: return "sra_parts"; 5166 case ISD::SRL_PARTS: return "srl_parts"; 5167 5168 // Conversion operators. 5169 case ISD::SIGN_EXTEND: return "sign_extend"; 5170 case ISD::ZERO_EXTEND: return "zero_extend"; 5171 case ISD::ANY_EXTEND: return "any_extend"; 5172 case ISD::SIGN_EXTEND_INREG: return "sign_extend_inreg"; 5173 case ISD::TRUNCATE: return "truncate"; 5174 case ISD::FP_ROUND: return "fp_round"; 5175 case ISD::FLT_ROUNDS_: return "flt_rounds"; 5176 case ISD::FP_ROUND_INREG: return "fp_round_inreg"; 5177 case ISD::FP_EXTEND: return "fp_extend"; 5178 5179 case ISD::SINT_TO_FP: return "sint_to_fp"; 5180 case ISD::UINT_TO_FP: return "uint_to_fp"; 5181 case ISD::FP_TO_SINT: return "fp_to_sint"; 5182 case ISD::FP_TO_UINT: return "fp_to_uint"; 5183 case ISD::BIT_CONVERT: return "bit_convert"; 5184 5185 case ISD::CONVERT_RNDSAT: { 5186 switch (cast<CvtRndSatSDNode>(this)->getCvtCode()) { 5187 default: assert(0 && "Unknown cvt code!"); 5188 case ISD::CVT_FF: return "cvt_ff"; 5189 case ISD::CVT_FS: return "cvt_fs"; 5190 case ISD::CVT_FU: return "cvt_fu"; 5191 case ISD::CVT_SF: return "cvt_sf"; 5192 case ISD::CVT_UF: return "cvt_uf"; 5193 case ISD::CVT_SS: return "cvt_ss"; 5194 case ISD::CVT_SU: return "cvt_su"; 5195 case ISD::CVT_US: return "cvt_us"; 5196 case ISD::CVT_UU: return "cvt_uu"; 5197 } 5198 } 5199 5200 // Control flow instructions 5201 case ISD::BR: return "br"; 5202 case ISD::BRIND: return "brind"; 5203 case ISD::BR_JT: return "br_jt"; 5204 case ISD::BRCOND: return "brcond"; 5205 case ISD::BR_CC: return "br_cc"; 5206 case ISD::RET: return "ret"; 5207 case ISD::CALLSEQ_START: return "callseq_start"; 5208 case ISD::CALLSEQ_END: return "callseq_end"; 5209 5210 // Other operators 5211 case ISD::LOAD: return "load"; 5212 case ISD::STORE: return "store"; 5213 case ISD::VAARG: return "vaarg"; 5214 case ISD::VACOPY: return "vacopy"; 5215 case ISD::VAEND: return "vaend"; 5216 case ISD::VASTART: return "vastart"; 5217 case ISD::DYNAMIC_STACKALLOC: return "dynamic_stackalloc"; 5218 case ISD::EXTRACT_ELEMENT: return "extract_element"; 5219 case ISD::BUILD_PAIR: return "build_pair"; 5220 case ISD::STACKSAVE: return "stacksave"; 5221 case ISD::STACKRESTORE: return "stackrestore"; 5222 case ISD::TRAP: return "trap"; 5223 5224 // Bit manipulation 5225 case ISD::BSWAP: return "bswap"; 5226 case ISD::CTPOP: return "ctpop"; 5227 case ISD::CTTZ: return "cttz"; 5228 case ISD::CTLZ: return "ctlz"; 5229 5230 // Debug info 5231 case ISD::DBG_STOPPOINT: return "dbg_stoppoint"; 5232 case ISD::DEBUG_LOC: return "debug_loc"; 5233 5234 // Trampolines 5235 case ISD::TRAMPOLINE: return "trampoline"; 5236 5237 case ISD::CONDCODE: 5238 switch (cast<CondCodeSDNode>(this)->get()) { 5239 default: assert(0 && "Unknown setcc condition!"); 5240 case ISD::SETOEQ: return "setoeq"; 5241 case ISD::SETOGT: return "setogt"; 5242 case ISD::SETOGE: return "setoge"; 5243 case ISD::SETOLT: return "setolt"; 5244 case ISD::SETOLE: return "setole"; 5245 case ISD::SETONE: return "setone"; 5246 5247 case ISD::SETO: return "seto"; 5248 case ISD::SETUO: return "setuo"; 5249 case ISD::SETUEQ: return "setue"; 5250 case ISD::SETUGT: return "setugt"; 5251 case ISD::SETUGE: return "setuge"; 5252 case ISD::SETULT: return "setult"; 5253 case ISD::SETULE: return "setule"; 5254 case ISD::SETUNE: return "setune"; 5255 5256 case ISD::SETEQ: return "seteq"; 5257 case ISD::SETGT: return "setgt"; 5258 case ISD::SETGE: return "setge"; 5259 case ISD::SETLT: return "setlt"; 5260 case ISD::SETLE: return "setle"; 5261 case ISD::SETNE: return "setne"; 5262 } 5263 } 5264} 5265 5266const char *SDNode::getIndexedModeName(ISD::MemIndexedMode AM) { 5267 switch (AM) { 5268 default: 5269 return ""; 5270 case ISD::PRE_INC: 5271 return "<pre-inc>"; 5272 case ISD::PRE_DEC: 5273 return "<pre-dec>"; 5274 case ISD::POST_INC: 5275 return "<post-inc>"; 5276 case ISD::POST_DEC: 5277 return "<post-dec>"; 5278 } 5279} 5280 5281std::string ISD::ArgFlagsTy::getArgFlagsString() { 5282 std::string S = "< "; 5283 5284 if (isZExt()) 5285 S += "zext "; 5286 if (isSExt()) 5287 S += "sext "; 5288 if (isInReg()) 5289 S += "inreg "; 5290 if (isSRet()) 5291 S += "sret "; 5292 if (isByVal()) 5293 S += "byval "; 5294 if (isNest()) 5295 S += "nest "; 5296 if (getByValAlign()) 5297 S += "byval-align:" + utostr(getByValAlign()) + " "; 5298 if (getOrigAlign()) 5299 S += "orig-align:" + utostr(getOrigAlign()) + " "; 5300 if (getByValSize()) 5301 S += "byval-size:" + utostr(getByValSize()) + " "; 5302 return S + ">"; 5303} 5304 5305void SDNode::dump() const { dump(0); } 5306void SDNode::dump(const SelectionDAG *G) const { 5307 print(errs(), G); 5308} 5309 5310void SDNode::print_types(raw_ostream &OS, const SelectionDAG *G) const { 5311 OS << (void*)this << ": "; 5312 5313 for (unsigned i = 0, e = getNumValues(); i != e; ++i) { 5314 if (i) OS << ","; 5315 if (getValueType(i) == MVT::Other) 5316 OS << "ch"; 5317 else 5318 OS << getValueType(i).getMVTString(); 5319 } 5320 OS << " = " << getOperationName(G); 5321} 5322 5323void SDNode::print_details(raw_ostream &OS, const SelectionDAG *G) const { 5324 if (!isTargetOpcode() && getOpcode() == ISD::VECTOR_SHUFFLE) { 5325 SDNode *Mask = getOperand(2).getNode(); 5326 OS << "<"; 5327 for (unsigned i = 0, e = Mask->getNumOperands(); i != e; ++i) { 5328 if (i) OS << ","; 5329 if (Mask->getOperand(i).getOpcode() == ISD::UNDEF) 5330 OS << "u"; 5331 else 5332 OS << cast<ConstantSDNode>(Mask->getOperand(i))->getZExtValue(); 5333 } 5334 OS << ">"; 5335 } 5336 5337 if (const ConstantSDNode *CSDN = dyn_cast<ConstantSDNode>(this)) { 5338 OS << '<' << CSDN->getAPIntValue() << '>'; 5339 } else if (const ConstantFPSDNode *CSDN = dyn_cast<ConstantFPSDNode>(this)) { 5340 if (&CSDN->getValueAPF().getSemantics()==&APFloat::IEEEsingle) 5341 OS << '<' << CSDN->getValueAPF().convertToFloat() << '>'; 5342 else if (&CSDN->getValueAPF().getSemantics()==&APFloat::IEEEdouble) 5343 OS << '<' << CSDN->getValueAPF().convertToDouble() << '>'; 5344 else { 5345 OS << "<APFloat("; 5346 CSDN->getValueAPF().bitcastToAPInt().dump(); 5347 OS << ")>"; 5348 } 5349 } else if (const GlobalAddressSDNode *GADN = 5350 dyn_cast<GlobalAddressSDNode>(this)) { 5351 int64_t offset = GADN->getOffset(); 5352 OS << '<'; 5353 WriteAsOperand(OS, GADN->getGlobal()); 5354 OS << '>'; 5355 if (offset > 0) 5356 OS << " + " << offset; 5357 else 5358 OS << " " << offset; 5359 } else if (const FrameIndexSDNode *FIDN = dyn_cast<FrameIndexSDNode>(this)) { 5360 OS << "<" << FIDN->getIndex() << ">"; 5361 } else if (const JumpTableSDNode *JTDN = dyn_cast<JumpTableSDNode>(this)) { 5362 OS << "<" << JTDN->getIndex() << ">"; 5363 } else if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(this)){ 5364 int offset = CP->getOffset(); 5365 if (CP->isMachineConstantPoolEntry()) 5366 OS << "<" << *CP->getMachineCPVal() << ">"; 5367 else 5368 OS << "<" << *CP->getConstVal() << ">"; 5369 if (offset > 0) 5370 OS << " + " << offset; 5371 else 5372 OS << " " << offset; 5373 } else if (const BasicBlockSDNode *BBDN = dyn_cast<BasicBlockSDNode>(this)) { 5374 OS << "<"; 5375 const Value *LBB = (const Value*)BBDN->getBasicBlock()->getBasicBlock(); 5376 if (LBB) 5377 OS << LBB->getName() << " "; 5378 OS << (const void*)BBDN->getBasicBlock() << ">"; 5379 } else if (const RegisterSDNode *R = dyn_cast<RegisterSDNode>(this)) { 5380 if (G && R->getReg() && 5381 TargetRegisterInfo::isPhysicalRegister(R->getReg())) { 5382 OS << " " << G->getTarget().getRegisterInfo()->getName(R->getReg()); 5383 } else { 5384 OS << " #" << R->getReg(); 5385 } 5386 } else if (const ExternalSymbolSDNode *ES = 5387 dyn_cast<ExternalSymbolSDNode>(this)) { 5388 OS << "'" << ES->getSymbol() << "'"; 5389 } else if (const SrcValueSDNode *M = dyn_cast<SrcValueSDNode>(this)) { 5390 if (M->getValue()) 5391 OS << "<" << M->getValue() << ">"; 5392 else 5393 OS << "<null>"; 5394 } else if (const MemOperandSDNode *M = dyn_cast<MemOperandSDNode>(this)) { 5395 if (M->MO.getValue()) 5396 OS << "<" << M->MO.getValue() << ":" << M->MO.getOffset() << ">"; 5397 else 5398 OS << "<null:" << M->MO.getOffset() << ">"; 5399 } else if (const ARG_FLAGSSDNode *N = dyn_cast<ARG_FLAGSSDNode>(this)) { 5400 OS << N->getArgFlags().getArgFlagsString(); 5401 } else if (const VTSDNode *N = dyn_cast<VTSDNode>(this)) { 5402 OS << ":" << N->getVT().getMVTString(); 5403 } 5404 else if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(this)) { 5405 const Value *SrcValue = LD->getSrcValue(); 5406 int SrcOffset = LD->getSrcValueOffset(); 5407 OS << " <"; 5408 if (SrcValue) 5409 OS << SrcValue; 5410 else 5411 OS << "null"; 5412 OS << ":" << SrcOffset << ">"; 5413 5414 bool doExt = true; 5415 switch (LD->getExtensionType()) { 5416 default: doExt = false; break; 5417 case ISD::EXTLOAD: OS << " <anyext "; break; 5418 case ISD::SEXTLOAD: OS << " <sext "; break; 5419 case ISD::ZEXTLOAD: OS << " <zext "; break; 5420 } 5421 if (doExt) 5422 OS << LD->getMemoryVT().getMVTString() << ">"; 5423 5424 const char *AM = getIndexedModeName(LD->getAddressingMode()); 5425 if (*AM) 5426 OS << " " << AM; 5427 if (LD->isVolatile()) 5428 OS << " <volatile>"; 5429 OS << " alignment=" << LD->getAlignment(); 5430 } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(this)) { 5431 const Value *SrcValue = ST->getSrcValue(); 5432 int SrcOffset = ST->getSrcValueOffset(); 5433 OS << " <"; 5434 if (SrcValue) 5435 OS << SrcValue; 5436 else 5437 OS << "null"; 5438 OS << ":" << SrcOffset << ">"; 5439 5440 if (ST->isTruncatingStore()) 5441 OS << " <trunc " << ST->getMemoryVT().getMVTString() << ">"; 5442 5443 const char *AM = getIndexedModeName(ST->getAddressingMode()); 5444 if (*AM) 5445 OS << " " << AM; 5446 if (ST->isVolatile()) 5447 OS << " <volatile>"; 5448 OS << " alignment=" << ST->getAlignment(); 5449 } else if (const AtomicSDNode* AT = dyn_cast<AtomicSDNode>(this)) { 5450 const Value *SrcValue = AT->getSrcValue(); 5451 int SrcOffset = AT->getSrcValueOffset(); 5452 OS << " <"; 5453 if (SrcValue) 5454 OS << SrcValue; 5455 else 5456 OS << "null"; 5457 OS << ":" << SrcOffset << ">"; 5458 if (AT->isVolatile()) 5459 OS << " <volatile>"; 5460 OS << " alignment=" << AT->getAlignment(); 5461 } 5462} 5463 5464void SDNode::print(raw_ostream &OS, const SelectionDAG *G) const { 5465 print_types(OS, G); 5466 OS << " "; 5467 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 5468 if (i) OS << ", "; 5469 OS << (void*)getOperand(i).getNode(); 5470 if (unsigned RN = getOperand(i).getResNo()) 5471 OS << ":" << RN; 5472 } 5473 print_details(OS, G); 5474} 5475 5476static void DumpNodes(const SDNode *N, unsigned indent, const SelectionDAG *G) { 5477 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 5478 if (N->getOperand(i).getNode()->hasOneUse()) 5479 DumpNodes(N->getOperand(i).getNode(), indent+2, G); 5480 else 5481 cerr << "\n" << std::string(indent+2, ' ') 5482 << (void*)N->getOperand(i).getNode() << ": <multiple use>"; 5483 5484 5485 cerr << "\n" << std::string(indent, ' '); 5486 N->dump(G); 5487} 5488 5489void SelectionDAG::dump() const { 5490 cerr << "SelectionDAG has " << AllNodes.size() << " nodes:"; 5491 5492 for (allnodes_const_iterator I = allnodes_begin(), E = allnodes_end(); 5493 I != E; ++I) { 5494 const SDNode *N = I; 5495 if (!N->hasOneUse() && N != getRoot().getNode()) 5496 DumpNodes(N, 2, this); 5497 } 5498 5499 if (getRoot().getNode()) DumpNodes(getRoot().getNode(), 2, this); 5500 5501 cerr << "\n\n"; 5502} 5503 5504void SDNode::printr(raw_ostream &OS, const SelectionDAG *G) const { 5505 print_types(OS, G); 5506 print_details(OS, G); 5507} 5508 5509typedef SmallPtrSet<const SDNode *, 128> VisitedSDNodeSet; 5510static void DumpNodesr(raw_ostream &OS, const SDNode *N, unsigned indent, 5511 const SelectionDAG *G, VisitedSDNodeSet &once) { 5512 if (!once.insert(N)) // If we've been here before, return now. 5513 return; 5514 // Dump the current SDNode, but don't end the line yet. 5515 OS << std::string(indent, ' '); 5516 N->printr(OS, G); 5517 // Having printed this SDNode, walk the children: 5518 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 5519 const SDNode *child = N->getOperand(i).getNode(); 5520 if (i) OS << ","; 5521 OS << " "; 5522 if (child->getNumOperands() == 0) { 5523 // This child has no grandchildren; print it inline right here. 5524 child->printr(OS, G); 5525 once.insert(child); 5526 } else { // Just the address. FIXME: also print the child's opcode 5527 OS << (void*)child; 5528 if (unsigned RN = N->getOperand(i).getResNo()) 5529 OS << ":" << RN; 5530 } 5531 } 5532 OS << "\n"; 5533 // Dump children that have grandchildren on their own line(s). 5534 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 5535 const SDNode *child = N->getOperand(i).getNode(); 5536 DumpNodesr(OS, child, indent+2, G, once); 5537 } 5538} 5539 5540void SDNode::dumpr() const { 5541 VisitedSDNodeSet once; 5542 DumpNodesr(errs(), this, 0, 0, once); 5543} 5544 5545const Type *ConstantPoolSDNode::getType() const { 5546 if (isMachineConstantPoolEntry()) 5547 return Val.MachineCPVal->getType(); 5548 return Val.ConstVal->getType(); 5549} 5550 5551bool BuildVectorSDNode::isConstantSplat(APInt &SplatValue, 5552 APInt &SplatUndef, 5553 unsigned &SplatBitSize, 5554 bool &HasAnyUndefs, 5555 unsigned MinSplatBits) { 5556 MVT VT = getValueType(0); 5557 assert(VT.isVector() && "Expected a vector type"); 5558 unsigned sz = VT.getSizeInBits(); 5559 if (MinSplatBits > sz) 5560 return false; 5561 5562 SplatValue = APInt(sz, 0); 5563 SplatUndef = APInt(sz, 0); 5564 5565 // Get the bits. Bits with undefined values (when the corresponding element 5566 // of the vector is an ISD::UNDEF value) are set in SplatUndef and cleared 5567 // in SplatValue. If any of the values are not constant, give up and return 5568 // false. 5569 unsigned int nOps = getNumOperands(); 5570 assert(nOps > 0 && "isConstantSplat has 0-size build vector"); 5571 unsigned EltBitSize = VT.getVectorElementType().getSizeInBits(); 5572 for (unsigned i = 0; i < nOps; ++i) { 5573 SDValue OpVal = getOperand(i); 5574 unsigned BitPos = i * EltBitSize; 5575 5576 if (OpVal.getOpcode() == ISD::UNDEF) 5577 SplatUndef |= APInt::getBitsSet(sz, BitPos, BitPos +EltBitSize); 5578 else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) 5579 SplatValue |= (APInt(CN->getAPIntValue()).zextOrTrunc(EltBitSize). 5580 zextOrTrunc(sz) << BitPos); 5581 else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) 5582 SplatValue |= CN->getValueAPF().bitcastToAPInt().zextOrTrunc(sz) <<BitPos; 5583 else 5584 return false; 5585 } 5586 5587 // The build_vector is all constants or undefs. Find the smallest element 5588 // size that splats the vector. 5589 5590 HasAnyUndefs = (SplatUndef != 0); 5591 while (sz > 8) { 5592 5593 unsigned HalfSize = sz / 2; 5594 APInt HighValue = APInt(SplatValue).lshr(HalfSize).trunc(HalfSize); 5595 APInt LowValue = APInt(SplatValue).trunc(HalfSize); 5596 APInt HighUndef = APInt(SplatUndef).lshr(HalfSize).trunc(HalfSize); 5597 APInt LowUndef = APInt(SplatUndef).trunc(HalfSize); 5598 5599 // If the two halves do not match (ignoring undef bits), stop here. 5600 if ((HighValue & ~LowUndef) != (LowValue & ~HighUndef) || 5601 MinSplatBits > HalfSize) 5602 break; 5603 5604 SplatValue = HighValue | LowValue; 5605 SplatUndef = HighUndef & LowUndef; 5606 5607 sz = HalfSize; 5608 } 5609 5610 SplatBitSize = sz; 5611 return true; 5612} 5613