SelectionDAG.cpp revision d1996360399ad6dbe75ee185b661b16c83146373
1//===-- SelectionDAG.cpp - Implement the SelectionDAG data structures -----===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAG class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "SDNodeOrdering.h" 16#include "llvm/Constants.h" 17#include "llvm/Analysis/ValueTracking.h" 18#include "llvm/Function.h" 19#include "llvm/GlobalAlias.h" 20#include "llvm/GlobalVariable.h" 21#include "llvm/Intrinsics.h" 22#include "llvm/DerivedTypes.h" 23#include "llvm/Assembly/Writer.h" 24#include "llvm/CallingConv.h" 25#include "llvm/CodeGen/MachineBasicBlock.h" 26#include "llvm/CodeGen/MachineConstantPool.h" 27#include "llvm/CodeGen/MachineFrameInfo.h" 28#include "llvm/CodeGen/MachineModuleInfo.h" 29#include "llvm/CodeGen/PseudoSourceValue.h" 30#include "llvm/Target/TargetRegisterInfo.h" 31#include "llvm/Target/TargetData.h" 32#include "llvm/Target/TargetFrameInfo.h" 33#include "llvm/Target/TargetLowering.h" 34#include "llvm/Target/TargetOptions.h" 35#include "llvm/Target/TargetInstrInfo.h" 36#include "llvm/Target/TargetIntrinsicInfo.h" 37#include "llvm/Target/TargetMachine.h" 38#include "llvm/Support/CommandLine.h" 39#include "llvm/Support/Debug.h" 40#include "llvm/Support/ErrorHandling.h" 41#include "llvm/Support/ManagedStatic.h" 42#include "llvm/Support/MathExtras.h" 43#include "llvm/Support/raw_ostream.h" 44#include "llvm/System/Mutex.h" 45#include "llvm/ADT/SetVector.h" 46#include "llvm/ADT/SmallPtrSet.h" 47#include "llvm/ADT/SmallSet.h" 48#include "llvm/ADT/SmallVector.h" 49#include "llvm/ADT/StringExtras.h" 50#include <algorithm> 51#include <cmath> 52using namespace llvm; 53 54/// makeVTList - Return an instance of the SDVTList struct initialized with the 55/// specified members. 56static SDVTList makeVTList(const EVT *VTs, unsigned NumVTs) { 57 SDVTList Res = {VTs, NumVTs}; 58 return Res; 59} 60 61static const fltSemantics *EVTToAPFloatSemantics(EVT VT) { 62 switch (VT.getSimpleVT().SimpleTy) { 63 default: llvm_unreachable("Unknown FP format"); 64 case MVT::f32: return &APFloat::IEEEsingle; 65 case MVT::f64: return &APFloat::IEEEdouble; 66 case MVT::f80: return &APFloat::x87DoubleExtended; 67 case MVT::f128: return &APFloat::IEEEquad; 68 case MVT::ppcf128: return &APFloat::PPCDoubleDouble; 69 } 70} 71 72SelectionDAG::DAGUpdateListener::~DAGUpdateListener() {} 73 74//===----------------------------------------------------------------------===// 75// ConstantFPSDNode Class 76//===----------------------------------------------------------------------===// 77 78/// isExactlyValue - We don't rely on operator== working on double values, as 79/// it returns true for things that are clearly not equal, like -0.0 and 0.0. 80/// As such, this method can be used to do an exact bit-for-bit comparison of 81/// two floating point values. 82bool ConstantFPSDNode::isExactlyValue(const APFloat& V) const { 83 return getValueAPF().bitwiseIsEqual(V); 84} 85 86bool ConstantFPSDNode::isValueValidForType(EVT VT, 87 const APFloat& Val) { 88 assert(VT.isFloatingPoint() && "Can only convert between FP types"); 89 90 // PPC long double cannot be converted to any other type. 91 if (VT == MVT::ppcf128 || 92 &Val.getSemantics() == &APFloat::PPCDoubleDouble) 93 return false; 94 95 // convert modifies in place, so make a copy. 96 APFloat Val2 = APFloat(Val); 97 bool losesInfo; 98 (void) Val2.convert(*EVTToAPFloatSemantics(VT), APFloat::rmNearestTiesToEven, 99 &losesInfo); 100 return !losesInfo; 101} 102 103//===----------------------------------------------------------------------===// 104// ISD Namespace 105//===----------------------------------------------------------------------===// 106 107/// isBuildVectorAllOnes - Return true if the specified node is a 108/// BUILD_VECTOR where all of the elements are ~0 or undef. 109bool ISD::isBuildVectorAllOnes(const SDNode *N) { 110 // Look through a bit convert. 111 if (N->getOpcode() == ISD::BIT_CONVERT) 112 N = N->getOperand(0).getNode(); 113 114 if (N->getOpcode() != ISD::BUILD_VECTOR) return false; 115 116 unsigned i = 0, e = N->getNumOperands(); 117 118 // Skip over all of the undef values. 119 while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF) 120 ++i; 121 122 // Do not accept an all-undef vector. 123 if (i == e) return false; 124 125 // Do not accept build_vectors that aren't all constants or which have non-~0 126 // elements. 127 SDValue NotZero = N->getOperand(i); 128 if (isa<ConstantSDNode>(NotZero)) { 129 if (!cast<ConstantSDNode>(NotZero)->isAllOnesValue()) 130 return false; 131 } else if (isa<ConstantFPSDNode>(NotZero)) { 132 if (!cast<ConstantFPSDNode>(NotZero)->getValueAPF(). 133 bitcastToAPInt().isAllOnesValue()) 134 return false; 135 } else 136 return false; 137 138 // Okay, we have at least one ~0 value, check to see if the rest match or are 139 // undefs. 140 for (++i; i != e; ++i) 141 if (N->getOperand(i) != NotZero && 142 N->getOperand(i).getOpcode() != ISD::UNDEF) 143 return false; 144 return true; 145} 146 147 148/// isBuildVectorAllZeros - Return true if the specified node is a 149/// BUILD_VECTOR where all of the elements are 0 or undef. 150bool ISD::isBuildVectorAllZeros(const SDNode *N) { 151 // Look through a bit convert. 152 if (N->getOpcode() == ISD::BIT_CONVERT) 153 N = N->getOperand(0).getNode(); 154 155 if (N->getOpcode() != ISD::BUILD_VECTOR) return false; 156 157 unsigned i = 0, e = N->getNumOperands(); 158 159 // Skip over all of the undef values. 160 while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF) 161 ++i; 162 163 // Do not accept an all-undef vector. 164 if (i == e) return false; 165 166 // Do not accept build_vectors that aren't all constants or which have non-0 167 // elements. 168 SDValue Zero = N->getOperand(i); 169 if (isa<ConstantSDNode>(Zero)) { 170 if (!cast<ConstantSDNode>(Zero)->isNullValue()) 171 return false; 172 } else if (isa<ConstantFPSDNode>(Zero)) { 173 if (!cast<ConstantFPSDNode>(Zero)->getValueAPF().isPosZero()) 174 return false; 175 } else 176 return false; 177 178 // Okay, we have at least one 0 value, check to see if the rest match or are 179 // undefs. 180 for (++i; i != e; ++i) 181 if (N->getOperand(i) != Zero && 182 N->getOperand(i).getOpcode() != ISD::UNDEF) 183 return false; 184 return true; 185} 186 187/// isScalarToVector - Return true if the specified node is a 188/// ISD::SCALAR_TO_VECTOR node or a BUILD_VECTOR node where only the low 189/// element is not an undef. 190bool ISD::isScalarToVector(const SDNode *N) { 191 if (N->getOpcode() == ISD::SCALAR_TO_VECTOR) 192 return true; 193 194 if (N->getOpcode() != ISD::BUILD_VECTOR) 195 return false; 196 if (N->getOperand(0).getOpcode() == ISD::UNDEF) 197 return false; 198 unsigned NumElems = N->getNumOperands(); 199 for (unsigned i = 1; i < NumElems; ++i) { 200 SDValue V = N->getOperand(i); 201 if (V.getOpcode() != ISD::UNDEF) 202 return false; 203 } 204 return true; 205} 206 207/// getSetCCSwappedOperands - Return the operation corresponding to (Y op X) 208/// when given the operation for (X op Y). 209ISD::CondCode ISD::getSetCCSwappedOperands(ISD::CondCode Operation) { 210 // To perform this operation, we just need to swap the L and G bits of the 211 // operation. 212 unsigned OldL = (Operation >> 2) & 1; 213 unsigned OldG = (Operation >> 1) & 1; 214 return ISD::CondCode((Operation & ~6) | // Keep the N, U, E bits 215 (OldL << 1) | // New G bit 216 (OldG << 2)); // New L bit. 217} 218 219/// getSetCCInverse - Return the operation corresponding to !(X op Y), where 220/// 'op' is a valid SetCC operation. 221ISD::CondCode ISD::getSetCCInverse(ISD::CondCode Op, bool isInteger) { 222 unsigned Operation = Op; 223 if (isInteger) 224 Operation ^= 7; // Flip L, G, E bits, but not U. 225 else 226 Operation ^= 15; // Flip all of the condition bits. 227 228 if (Operation > ISD::SETTRUE2) 229 Operation &= ~8; // Don't let N and U bits get set. 230 231 return ISD::CondCode(Operation); 232} 233 234 235/// isSignedOp - For an integer comparison, return 1 if the comparison is a 236/// signed operation and 2 if the result is an unsigned comparison. Return zero 237/// if the operation does not depend on the sign of the input (setne and seteq). 238static int isSignedOp(ISD::CondCode Opcode) { 239 switch (Opcode) { 240 default: llvm_unreachable("Illegal integer setcc operation!"); 241 case ISD::SETEQ: 242 case ISD::SETNE: return 0; 243 case ISD::SETLT: 244 case ISD::SETLE: 245 case ISD::SETGT: 246 case ISD::SETGE: return 1; 247 case ISD::SETULT: 248 case ISD::SETULE: 249 case ISD::SETUGT: 250 case ISD::SETUGE: return 2; 251 } 252} 253 254/// getSetCCOrOperation - Return the result of a logical OR between different 255/// comparisons of identical values: ((X op1 Y) | (X op2 Y)). This function 256/// returns SETCC_INVALID if it is not possible to represent the resultant 257/// comparison. 258ISD::CondCode ISD::getSetCCOrOperation(ISD::CondCode Op1, ISD::CondCode Op2, 259 bool isInteger) { 260 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 261 // Cannot fold a signed integer setcc with an unsigned integer setcc. 262 return ISD::SETCC_INVALID; 263 264 unsigned Op = Op1 | Op2; // Combine all of the condition bits. 265 266 // If the N and U bits get set then the resultant comparison DOES suddenly 267 // care about orderedness, and is true when ordered. 268 if (Op > ISD::SETTRUE2) 269 Op &= ~16; // Clear the U bit if the N bit is set. 270 271 // Canonicalize illegal integer setcc's. 272 if (isInteger && Op == ISD::SETUNE) // e.g. SETUGT | SETULT 273 Op = ISD::SETNE; 274 275 return ISD::CondCode(Op); 276} 277 278/// getSetCCAndOperation - Return the result of a logical AND between different 279/// comparisons of identical values: ((X op1 Y) & (X op2 Y)). This 280/// function returns zero if it is not possible to represent the resultant 281/// comparison. 282ISD::CondCode ISD::getSetCCAndOperation(ISD::CondCode Op1, ISD::CondCode Op2, 283 bool isInteger) { 284 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 285 // Cannot fold a signed setcc with an unsigned setcc. 286 return ISD::SETCC_INVALID; 287 288 // Combine all of the condition bits. 289 ISD::CondCode Result = ISD::CondCode(Op1 & Op2); 290 291 // Canonicalize illegal integer setcc's. 292 if (isInteger) { 293 switch (Result) { 294 default: break; 295 case ISD::SETUO : Result = ISD::SETFALSE; break; // SETUGT & SETULT 296 case ISD::SETOEQ: // SETEQ & SETU[LG]E 297 case ISD::SETUEQ: Result = ISD::SETEQ ; break; // SETUGE & SETULE 298 case ISD::SETOLT: Result = ISD::SETULT ; break; // SETULT & SETNE 299 case ISD::SETOGT: Result = ISD::SETUGT ; break; // SETUGT & SETNE 300 } 301 } 302 303 return Result; 304} 305 306const TargetMachine &SelectionDAG::getTarget() const { 307 return MF->getTarget(); 308} 309 310//===----------------------------------------------------------------------===// 311// SDNode Profile Support 312//===----------------------------------------------------------------------===// 313 314/// AddNodeIDOpcode - Add the node opcode to the NodeID data. 315/// 316static void AddNodeIDOpcode(FoldingSetNodeID &ID, unsigned OpC) { 317 ID.AddInteger(OpC); 318} 319 320/// AddNodeIDValueTypes - Value type lists are intern'd so we can represent them 321/// solely with their pointer. 322static void AddNodeIDValueTypes(FoldingSetNodeID &ID, SDVTList VTList) { 323 ID.AddPointer(VTList.VTs); 324} 325 326/// AddNodeIDOperands - Various routines for adding operands to the NodeID data. 327/// 328static void AddNodeIDOperands(FoldingSetNodeID &ID, 329 const SDValue *Ops, unsigned NumOps) { 330 for (; NumOps; --NumOps, ++Ops) { 331 ID.AddPointer(Ops->getNode()); 332 ID.AddInteger(Ops->getResNo()); 333 } 334} 335 336/// AddNodeIDOperands - Various routines for adding operands to the NodeID data. 337/// 338static void AddNodeIDOperands(FoldingSetNodeID &ID, 339 const SDUse *Ops, unsigned NumOps) { 340 for (; NumOps; --NumOps, ++Ops) { 341 ID.AddPointer(Ops->getNode()); 342 ID.AddInteger(Ops->getResNo()); 343 } 344} 345 346static void AddNodeIDNode(FoldingSetNodeID &ID, 347 unsigned short OpC, SDVTList VTList, 348 const SDValue *OpList, unsigned N) { 349 AddNodeIDOpcode(ID, OpC); 350 AddNodeIDValueTypes(ID, VTList); 351 AddNodeIDOperands(ID, OpList, N); 352} 353 354/// AddNodeIDCustom - If this is an SDNode with special info, add this info to 355/// the NodeID data. 356static void AddNodeIDCustom(FoldingSetNodeID &ID, const SDNode *N) { 357 switch (N->getOpcode()) { 358 case ISD::TargetExternalSymbol: 359 case ISD::ExternalSymbol: 360 llvm_unreachable("Should only be used on nodes with operands"); 361 default: break; // Normal nodes don't need extra info. 362 case ISD::TargetConstant: 363 case ISD::Constant: 364 ID.AddPointer(cast<ConstantSDNode>(N)->getConstantIntValue()); 365 break; 366 case ISD::TargetConstantFP: 367 case ISD::ConstantFP: { 368 ID.AddPointer(cast<ConstantFPSDNode>(N)->getConstantFPValue()); 369 break; 370 } 371 case ISD::TargetGlobalAddress: 372 case ISD::GlobalAddress: 373 case ISD::TargetGlobalTLSAddress: 374 case ISD::GlobalTLSAddress: { 375 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(N); 376 ID.AddPointer(GA->getGlobal()); 377 ID.AddInteger(GA->getOffset()); 378 ID.AddInteger(GA->getTargetFlags()); 379 break; 380 } 381 case ISD::BasicBlock: 382 ID.AddPointer(cast<BasicBlockSDNode>(N)->getBasicBlock()); 383 break; 384 case ISD::Register: 385 ID.AddInteger(cast<RegisterSDNode>(N)->getReg()); 386 break; 387 388 case ISD::SRCVALUE: 389 ID.AddPointer(cast<SrcValueSDNode>(N)->getValue()); 390 break; 391 case ISD::FrameIndex: 392 case ISD::TargetFrameIndex: 393 ID.AddInteger(cast<FrameIndexSDNode>(N)->getIndex()); 394 break; 395 case ISD::JumpTable: 396 case ISD::TargetJumpTable: 397 ID.AddInteger(cast<JumpTableSDNode>(N)->getIndex()); 398 ID.AddInteger(cast<JumpTableSDNode>(N)->getTargetFlags()); 399 break; 400 case ISD::ConstantPool: 401 case ISD::TargetConstantPool: { 402 const ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(N); 403 ID.AddInteger(CP->getAlignment()); 404 ID.AddInteger(CP->getOffset()); 405 if (CP->isMachineConstantPoolEntry()) 406 CP->getMachineCPVal()->AddSelectionDAGCSEId(ID); 407 else 408 ID.AddPointer(CP->getConstVal()); 409 ID.AddInteger(CP->getTargetFlags()); 410 break; 411 } 412 case ISD::LOAD: { 413 const LoadSDNode *LD = cast<LoadSDNode>(N); 414 ID.AddInteger(LD->getMemoryVT().getRawBits()); 415 ID.AddInteger(LD->getRawSubclassData()); 416 break; 417 } 418 case ISD::STORE: { 419 const StoreSDNode *ST = cast<StoreSDNode>(N); 420 ID.AddInteger(ST->getMemoryVT().getRawBits()); 421 ID.AddInteger(ST->getRawSubclassData()); 422 break; 423 } 424 case ISD::ATOMIC_CMP_SWAP: 425 case ISD::ATOMIC_SWAP: 426 case ISD::ATOMIC_LOAD_ADD: 427 case ISD::ATOMIC_LOAD_SUB: 428 case ISD::ATOMIC_LOAD_AND: 429 case ISD::ATOMIC_LOAD_OR: 430 case ISD::ATOMIC_LOAD_XOR: 431 case ISD::ATOMIC_LOAD_NAND: 432 case ISD::ATOMIC_LOAD_MIN: 433 case ISD::ATOMIC_LOAD_MAX: 434 case ISD::ATOMIC_LOAD_UMIN: 435 case ISD::ATOMIC_LOAD_UMAX: { 436 const AtomicSDNode *AT = cast<AtomicSDNode>(N); 437 ID.AddInteger(AT->getMemoryVT().getRawBits()); 438 ID.AddInteger(AT->getRawSubclassData()); 439 break; 440 } 441 case ISD::VECTOR_SHUFFLE: { 442 const ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N); 443 for (unsigned i = 0, e = N->getValueType(0).getVectorNumElements(); 444 i != e; ++i) 445 ID.AddInteger(SVN->getMaskElt(i)); 446 break; 447 } 448 case ISD::TargetBlockAddress: 449 case ISD::BlockAddress: { 450 ID.AddPointer(cast<BlockAddressSDNode>(N)->getBlockAddress()); 451 ID.AddInteger(cast<BlockAddressSDNode>(N)->getTargetFlags()); 452 break; 453 } 454 } // end switch (N->getOpcode()) 455} 456 457/// AddNodeIDNode - Generic routine for adding a nodes info to the NodeID 458/// data. 459static void AddNodeIDNode(FoldingSetNodeID &ID, const SDNode *N) { 460 AddNodeIDOpcode(ID, N->getOpcode()); 461 // Add the return value info. 462 AddNodeIDValueTypes(ID, N->getVTList()); 463 // Add the operand info. 464 AddNodeIDOperands(ID, N->op_begin(), N->getNumOperands()); 465 466 // Handle SDNode leafs with special info. 467 AddNodeIDCustom(ID, N); 468} 469 470/// encodeMemSDNodeFlags - Generic routine for computing a value for use in 471/// the CSE map that carries volatility, indexing mode, and 472/// extension/truncation information. 473/// 474static inline unsigned 475encodeMemSDNodeFlags(int ConvType, ISD::MemIndexedMode AM, bool isVolatile) { 476 assert((ConvType & 3) == ConvType && 477 "ConvType may not require more than 2 bits!"); 478 assert((AM & 7) == AM && 479 "AM may not require more than 3 bits!"); 480 return ConvType | 481 (AM << 2) | 482 (isVolatile << 5); 483} 484 485//===----------------------------------------------------------------------===// 486// SelectionDAG Class 487//===----------------------------------------------------------------------===// 488 489/// doNotCSE - Return true if CSE should not be performed for this node. 490static bool doNotCSE(SDNode *N) { 491 if (N->getValueType(0) == MVT::Flag) 492 return true; // Never CSE anything that produces a flag. 493 494 switch (N->getOpcode()) { 495 default: break; 496 case ISD::HANDLENODE: 497 case ISD::EH_LABEL: 498 return true; // Never CSE these nodes. 499 } 500 501 // Check that remaining values produced are not flags. 502 for (unsigned i = 1, e = N->getNumValues(); i != e; ++i) 503 if (N->getValueType(i) == MVT::Flag) 504 return true; // Never CSE anything that produces a flag. 505 506 return false; 507} 508 509/// RemoveDeadNodes - This method deletes all unreachable nodes in the 510/// SelectionDAG. 511void SelectionDAG::RemoveDeadNodes() { 512 // Create a dummy node (which is not added to allnodes), that adds a reference 513 // to the root node, preventing it from being deleted. 514 HandleSDNode Dummy(getRoot()); 515 516 SmallVector<SDNode*, 128> DeadNodes; 517 518 // Add all obviously-dead nodes to the DeadNodes worklist. 519 for (allnodes_iterator I = allnodes_begin(), E = allnodes_end(); I != E; ++I) 520 if (I->use_empty()) 521 DeadNodes.push_back(I); 522 523 RemoveDeadNodes(DeadNodes); 524 525 // If the root changed (e.g. it was a dead load, update the root). 526 setRoot(Dummy.getValue()); 527} 528 529/// RemoveDeadNodes - This method deletes the unreachable nodes in the 530/// given list, and any nodes that become unreachable as a result. 531void SelectionDAG::RemoveDeadNodes(SmallVectorImpl<SDNode *> &DeadNodes, 532 DAGUpdateListener *UpdateListener) { 533 534 // Process the worklist, deleting the nodes and adding their uses to the 535 // worklist. 536 while (!DeadNodes.empty()) { 537 SDNode *N = DeadNodes.pop_back_val(); 538 539 if (UpdateListener) 540 UpdateListener->NodeDeleted(N, 0); 541 542 // Take the node out of the appropriate CSE map. 543 RemoveNodeFromCSEMaps(N); 544 545 // Next, brutally remove the operand list. This is safe to do, as there are 546 // no cycles in the graph. 547 for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ) { 548 SDUse &Use = *I++; 549 SDNode *Operand = Use.getNode(); 550 Use.set(SDValue()); 551 552 // Now that we removed this operand, see if there are no uses of it left. 553 if (Operand->use_empty()) 554 DeadNodes.push_back(Operand); 555 } 556 557 DeallocateNode(N); 558 } 559} 560 561void SelectionDAG::RemoveDeadNode(SDNode *N, DAGUpdateListener *UpdateListener){ 562 SmallVector<SDNode*, 16> DeadNodes(1, N); 563 RemoveDeadNodes(DeadNodes, UpdateListener); 564} 565 566void SelectionDAG::DeleteNode(SDNode *N) { 567 // First take this out of the appropriate CSE map. 568 RemoveNodeFromCSEMaps(N); 569 570 // Finally, remove uses due to operands of this node, remove from the 571 // AllNodes list, and delete the node. 572 DeleteNodeNotInCSEMaps(N); 573} 574 575void SelectionDAG::DeleteNodeNotInCSEMaps(SDNode *N) { 576 assert(N != AllNodes.begin() && "Cannot delete the entry node!"); 577 assert(N->use_empty() && "Cannot delete a node that is not dead!"); 578 579 // Drop all of the operands and decrement used node's use counts. 580 N->DropOperands(); 581 582 DeallocateNode(N); 583} 584 585void SelectionDAG::DeallocateNode(SDNode *N) { 586 if (N->OperandsNeedDelete) 587 delete[] N->OperandList; 588 589 // Set the opcode to DELETED_NODE to help catch bugs when node 590 // memory is reallocated. 591 N->NodeType = ISD::DELETED_NODE; 592 593 NodeAllocator.Deallocate(AllNodes.remove(N)); 594 595 // Remove the ordering of this node. 596 if (Ordering) Ordering->remove(N); 597} 598 599/// RemoveNodeFromCSEMaps - Take the specified node out of the CSE map that 600/// correspond to it. This is useful when we're about to delete or repurpose 601/// the node. We don't want future request for structurally identical nodes 602/// to return N anymore. 603bool SelectionDAG::RemoveNodeFromCSEMaps(SDNode *N) { 604 bool Erased = false; 605 switch (N->getOpcode()) { 606 case ISD::EntryToken: 607 llvm_unreachable("EntryToken should not be in CSEMaps!"); 608 return false; 609 case ISD::HANDLENODE: return false; // noop. 610 case ISD::CONDCODE: 611 assert(CondCodeNodes[cast<CondCodeSDNode>(N)->get()] && 612 "Cond code doesn't exist!"); 613 Erased = CondCodeNodes[cast<CondCodeSDNode>(N)->get()] != 0; 614 CondCodeNodes[cast<CondCodeSDNode>(N)->get()] = 0; 615 break; 616 case ISD::ExternalSymbol: 617 Erased = ExternalSymbols.erase(cast<ExternalSymbolSDNode>(N)->getSymbol()); 618 break; 619 case ISD::TargetExternalSymbol: { 620 ExternalSymbolSDNode *ESN = cast<ExternalSymbolSDNode>(N); 621 Erased = TargetExternalSymbols.erase( 622 std::pair<std::string,unsigned char>(ESN->getSymbol(), 623 ESN->getTargetFlags())); 624 break; 625 } 626 case ISD::VALUETYPE: { 627 EVT VT = cast<VTSDNode>(N)->getVT(); 628 if (VT.isExtended()) { 629 Erased = ExtendedValueTypeNodes.erase(VT); 630 } else { 631 Erased = ValueTypeNodes[VT.getSimpleVT().SimpleTy] != 0; 632 ValueTypeNodes[VT.getSimpleVT().SimpleTy] = 0; 633 } 634 break; 635 } 636 default: 637 // Remove it from the CSE Map. 638 Erased = CSEMap.RemoveNode(N); 639 break; 640 } 641#ifndef NDEBUG 642 // Verify that the node was actually in one of the CSE maps, unless it has a 643 // flag result (which cannot be CSE'd) or is one of the special cases that are 644 // not subject to CSE. 645 if (!Erased && N->getValueType(N->getNumValues()-1) != MVT::Flag && 646 !N->isMachineOpcode() && !doNotCSE(N)) { 647 N->dump(this); 648 dbgs() << "\n"; 649 llvm_unreachable("Node is not in map!"); 650 } 651#endif 652 return Erased; 653} 654 655/// AddModifiedNodeToCSEMaps - The specified node has been removed from the CSE 656/// maps and modified in place. Add it back to the CSE maps, unless an identical 657/// node already exists, in which case transfer all its users to the existing 658/// node. This transfer can potentially trigger recursive merging. 659/// 660void 661SelectionDAG::AddModifiedNodeToCSEMaps(SDNode *N, 662 DAGUpdateListener *UpdateListener) { 663 // For node types that aren't CSE'd, just act as if no identical node 664 // already exists. 665 if (!doNotCSE(N)) { 666 SDNode *Existing = CSEMap.GetOrInsertNode(N); 667 if (Existing != N) { 668 // If there was already an existing matching node, use ReplaceAllUsesWith 669 // to replace the dead one with the existing one. This can cause 670 // recursive merging of other unrelated nodes down the line. 671 ReplaceAllUsesWith(N, Existing, UpdateListener); 672 673 // N is now dead. Inform the listener if it exists and delete it. 674 if (UpdateListener) 675 UpdateListener->NodeDeleted(N, Existing); 676 DeleteNodeNotInCSEMaps(N); 677 return; 678 } 679 } 680 681 // If the node doesn't already exist, we updated it. Inform a listener if 682 // it exists. 683 if (UpdateListener) 684 UpdateListener->NodeUpdated(N); 685} 686 687/// FindModifiedNodeSlot - Find a slot for the specified node if its operands 688/// were replaced with those specified. If this node is never memoized, 689/// return null, otherwise return a pointer to the slot it would take. If a 690/// node already exists with these operands, the slot will be non-null. 691SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, SDValue Op, 692 void *&InsertPos) { 693 if (doNotCSE(N)) 694 return 0; 695 696 SDValue Ops[] = { Op }; 697 FoldingSetNodeID ID; 698 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, 1); 699 AddNodeIDCustom(ID, N); 700 SDNode *Node = CSEMap.FindNodeOrInsertPos(ID, InsertPos); 701 return Node; 702} 703 704/// FindModifiedNodeSlot - Find a slot for the specified node if its operands 705/// were replaced with those specified. If this node is never memoized, 706/// return null, otherwise return a pointer to the slot it would take. If a 707/// node already exists with these operands, the slot will be non-null. 708SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, 709 SDValue Op1, SDValue Op2, 710 void *&InsertPos) { 711 if (doNotCSE(N)) 712 return 0; 713 714 SDValue Ops[] = { Op1, Op2 }; 715 FoldingSetNodeID ID; 716 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, 2); 717 AddNodeIDCustom(ID, N); 718 SDNode *Node = CSEMap.FindNodeOrInsertPos(ID, InsertPos); 719 return Node; 720} 721 722 723/// FindModifiedNodeSlot - Find a slot for the specified node if its operands 724/// were replaced with those specified. If this node is never memoized, 725/// return null, otherwise return a pointer to the slot it would take. If a 726/// node already exists with these operands, the slot will be non-null. 727SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, 728 const SDValue *Ops,unsigned NumOps, 729 void *&InsertPos) { 730 if (doNotCSE(N)) 731 return 0; 732 733 FoldingSetNodeID ID; 734 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, NumOps); 735 AddNodeIDCustom(ID, N); 736 SDNode *Node = CSEMap.FindNodeOrInsertPos(ID, InsertPos); 737 return Node; 738} 739 740/// VerifyNode - Sanity check the given node. Aborts if it is invalid. 741void SelectionDAG::VerifyNode(SDNode *N) { 742 switch (N->getOpcode()) { 743 default: 744 break; 745 case ISD::BUILD_PAIR: { 746 EVT VT = N->getValueType(0); 747 assert(N->getNumValues() == 1 && "Too many results!"); 748 assert(!VT.isVector() && (VT.isInteger() || VT.isFloatingPoint()) && 749 "Wrong return type!"); 750 assert(N->getNumOperands() == 2 && "Wrong number of operands!"); 751 assert(N->getOperand(0).getValueType() == N->getOperand(1).getValueType() && 752 "Mismatched operand types!"); 753 assert(N->getOperand(0).getValueType().isInteger() == VT.isInteger() && 754 "Wrong operand type!"); 755 assert(VT.getSizeInBits() == 2 * N->getOperand(0).getValueSizeInBits() && 756 "Wrong return type size"); 757 break; 758 } 759 case ISD::BUILD_VECTOR: { 760 assert(N->getNumValues() == 1 && "Too many results!"); 761 assert(N->getValueType(0).isVector() && "Wrong return type!"); 762 assert(N->getNumOperands() == N->getValueType(0).getVectorNumElements() && 763 "Wrong number of operands!"); 764 EVT EltVT = N->getValueType(0).getVectorElementType(); 765 for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ++I) 766 assert((I->getValueType() == EltVT || 767 (EltVT.isInteger() && I->getValueType().isInteger() && 768 EltVT.bitsLE(I->getValueType()))) && 769 "Wrong operand type!"); 770 break; 771 } 772 } 773} 774 775/// getEVTAlignment - Compute the default alignment value for the 776/// given type. 777/// 778unsigned SelectionDAG::getEVTAlignment(EVT VT) const { 779 const Type *Ty = VT == MVT::iPTR ? 780 PointerType::get(Type::getInt8Ty(*getContext()), 0) : 781 VT.getTypeForEVT(*getContext()); 782 783 return TLI.getTargetData()->getABITypeAlignment(Ty); 784} 785 786// EntryNode could meaningfully have debug info if we can find it... 787SelectionDAG::SelectionDAG(TargetLowering &tli, FunctionLoweringInfo &fli) 788 : TLI(tli), FLI(fli), DW(0), 789 EntryNode(ISD::EntryToken, DebugLoc::getUnknownLoc(), 790 getVTList(MVT::Other)), 791 Root(getEntryNode()), Ordering(0) { 792 AllNodes.push_back(&EntryNode); 793 if (DisableScheduling) 794 Ordering = new SDNodeOrdering(); 795} 796 797void SelectionDAG::init(MachineFunction &mf, MachineModuleInfo *mmi, 798 DwarfWriter *dw) { 799 MF = &mf; 800 MMI = mmi; 801 DW = dw; 802 Context = &mf.getFunction()->getContext(); 803} 804 805SelectionDAG::~SelectionDAG() { 806 allnodes_clear(); 807 delete Ordering; 808} 809 810void SelectionDAG::allnodes_clear() { 811 assert(&*AllNodes.begin() == &EntryNode); 812 AllNodes.remove(AllNodes.begin()); 813 while (!AllNodes.empty()) 814 DeallocateNode(AllNodes.begin()); 815} 816 817void SelectionDAG::clear() { 818 allnodes_clear(); 819 OperandAllocator.Reset(); 820 CSEMap.clear(); 821 822 ExtendedValueTypeNodes.clear(); 823 ExternalSymbols.clear(); 824 TargetExternalSymbols.clear(); 825 std::fill(CondCodeNodes.begin(), CondCodeNodes.end(), 826 static_cast<CondCodeSDNode*>(0)); 827 std::fill(ValueTypeNodes.begin(), ValueTypeNodes.end(), 828 static_cast<SDNode*>(0)); 829 830 EntryNode.UseList = 0; 831 AllNodes.push_back(&EntryNode); 832 Root = getEntryNode(); 833 if (DisableScheduling) 834 Ordering = new SDNodeOrdering(); 835} 836 837SDValue SelectionDAG::getSExtOrTrunc(SDValue Op, DebugLoc DL, EVT VT) { 838 return VT.bitsGT(Op.getValueType()) ? 839 getNode(ISD::SIGN_EXTEND, DL, VT, Op) : 840 getNode(ISD::TRUNCATE, DL, VT, Op); 841} 842 843SDValue SelectionDAG::getZExtOrTrunc(SDValue Op, DebugLoc DL, EVT VT) { 844 return VT.bitsGT(Op.getValueType()) ? 845 getNode(ISD::ZERO_EXTEND, DL, VT, Op) : 846 getNode(ISD::TRUNCATE, DL, VT, Op); 847} 848 849SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, DebugLoc DL, EVT VT) { 850 assert(!VT.isVector() && 851 "getZeroExtendInReg should use the vector element type instead of " 852 "the vector type!"); 853 if (Op.getValueType() == VT) return Op; 854 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits(); 855 APInt Imm = APInt::getLowBitsSet(BitWidth, 856 VT.getSizeInBits()); 857 return getNode(ISD::AND, DL, Op.getValueType(), Op, 858 getConstant(Imm, Op.getValueType())); 859} 860 861/// getNOT - Create a bitwise NOT operation as (XOR Val, -1). 862/// 863SDValue SelectionDAG::getNOT(DebugLoc DL, SDValue Val, EVT VT) { 864 EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 865 SDValue NegOne = 866 getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT); 867 return getNode(ISD::XOR, DL, VT, Val, NegOne); 868} 869 870SDValue SelectionDAG::getConstant(uint64_t Val, EVT VT, bool isT) { 871 EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 872 assert((EltVT.getSizeInBits() >= 64 || 873 (uint64_t)((int64_t)Val >> EltVT.getSizeInBits()) + 1 < 2) && 874 "getConstant with a uint64_t value that doesn't fit in the type!"); 875 return getConstant(APInt(EltVT.getSizeInBits(), Val), VT, isT); 876} 877 878SDValue SelectionDAG::getConstant(const APInt &Val, EVT VT, bool isT) { 879 return getConstant(*ConstantInt::get(*Context, Val), VT, isT); 880} 881 882SDValue SelectionDAG::getConstant(const ConstantInt &Val, EVT VT, bool isT) { 883 assert(VT.isInteger() && "Cannot create FP integer constant!"); 884 885 EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 886 assert(Val.getBitWidth() == EltVT.getSizeInBits() && 887 "APInt size does not match type size!"); 888 889 unsigned Opc = isT ? ISD::TargetConstant : ISD::Constant; 890 FoldingSetNodeID ID; 891 AddNodeIDNode(ID, Opc, getVTList(EltVT), 0, 0); 892 ID.AddPointer(&Val); 893 void *IP = 0; 894 SDNode *N = NULL; 895 if ((N = CSEMap.FindNodeOrInsertPos(ID, IP))) 896 if (!VT.isVector()) 897 return SDValue(N, 0); 898 899 if (!N) { 900 N = NodeAllocator.Allocate<ConstantSDNode>(); 901 new (N) ConstantSDNode(isT, &Val, EltVT); 902 CSEMap.InsertNode(N, IP); 903 AllNodes.push_back(N); 904 } 905 906 SDValue Result(N, 0); 907 if (VT.isVector()) { 908 SmallVector<SDValue, 8> Ops; 909 Ops.assign(VT.getVectorNumElements(), Result); 910 Result = getNode(ISD::BUILD_VECTOR, DebugLoc::getUnknownLoc(), 911 VT, &Ops[0], Ops.size()); 912 } 913 return Result; 914} 915 916SDValue SelectionDAG::getIntPtrConstant(uint64_t Val, bool isTarget) { 917 return getConstant(Val, TLI.getPointerTy(), isTarget); 918} 919 920 921SDValue SelectionDAG::getConstantFP(const APFloat& V, EVT VT, bool isTarget) { 922 return getConstantFP(*ConstantFP::get(*getContext(), V), VT, isTarget); 923} 924 925SDValue SelectionDAG::getConstantFP(const ConstantFP& V, EVT VT, bool isTarget){ 926 assert(VT.isFloatingPoint() && "Cannot create integer FP constant!"); 927 928 EVT EltVT = 929 VT.isVector() ? VT.getVectorElementType() : VT; 930 931 // Do the map lookup using the actual bit pattern for the floating point 932 // value, so that we don't have problems with 0.0 comparing equal to -0.0, and 933 // we don't have issues with SNANs. 934 unsigned Opc = isTarget ? ISD::TargetConstantFP : ISD::ConstantFP; 935 FoldingSetNodeID ID; 936 AddNodeIDNode(ID, Opc, getVTList(EltVT), 0, 0); 937 ID.AddPointer(&V); 938 void *IP = 0; 939 SDNode *N = NULL; 940 if ((N = CSEMap.FindNodeOrInsertPos(ID, IP))) 941 if (!VT.isVector()) 942 return SDValue(N, 0); 943 944 if (!N) { 945 N = NodeAllocator.Allocate<ConstantFPSDNode>(); 946 new (N) ConstantFPSDNode(isTarget, &V, EltVT); 947 CSEMap.InsertNode(N, IP); 948 AllNodes.push_back(N); 949 } 950 951 SDValue Result(N, 0); 952 if (VT.isVector()) { 953 SmallVector<SDValue, 8> Ops; 954 Ops.assign(VT.getVectorNumElements(), Result); 955 // FIXME DebugLoc info might be appropriate here 956 Result = getNode(ISD::BUILD_VECTOR, DebugLoc::getUnknownLoc(), 957 VT, &Ops[0], Ops.size()); 958 } 959 return Result; 960} 961 962SDValue SelectionDAG::getConstantFP(double Val, EVT VT, bool isTarget) { 963 EVT EltVT = 964 VT.isVector() ? VT.getVectorElementType() : VT; 965 if (EltVT==MVT::f32) 966 return getConstantFP(APFloat((float)Val), VT, isTarget); 967 else 968 return getConstantFP(APFloat(Val), VT, isTarget); 969} 970 971SDValue SelectionDAG::getGlobalAddress(const GlobalValue *GV, 972 EVT VT, int64_t Offset, 973 bool isTargetGA, 974 unsigned char TargetFlags) { 975 assert((TargetFlags == 0 || isTargetGA) && 976 "Cannot set target flags on target-independent globals"); 977 978 // Truncate (with sign-extension) the offset value to the pointer size. 979 EVT PTy = TLI.getPointerTy(); 980 unsigned BitWidth = PTy.getSizeInBits(); 981 if (BitWidth < 64) 982 Offset = (Offset << (64 - BitWidth) >> (64 - BitWidth)); 983 984 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV); 985 if (!GVar) { 986 // If GV is an alias then use the aliasee for determining thread-localness. 987 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) 988 GVar = dyn_cast_or_null<GlobalVariable>(GA->resolveAliasedGlobal(false)); 989 } 990 991 unsigned Opc; 992 if (GVar && GVar->isThreadLocal()) 993 Opc = isTargetGA ? ISD::TargetGlobalTLSAddress : ISD::GlobalTLSAddress; 994 else 995 Opc = isTargetGA ? ISD::TargetGlobalAddress : ISD::GlobalAddress; 996 997 FoldingSetNodeID ID; 998 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 999 ID.AddPointer(GV); 1000 ID.AddInteger(Offset); 1001 ID.AddInteger(TargetFlags); 1002 void *IP = 0; 1003 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1004 return SDValue(E, 0); 1005 1006 SDNode *N = NodeAllocator.Allocate<GlobalAddressSDNode>(); 1007 new (N) GlobalAddressSDNode(Opc, GV, VT, Offset, TargetFlags); 1008 CSEMap.InsertNode(N, IP); 1009 AllNodes.push_back(N); 1010 return SDValue(N, 0); 1011} 1012 1013SDValue SelectionDAG::getFrameIndex(int FI, EVT VT, bool isTarget) { 1014 unsigned Opc = isTarget ? ISD::TargetFrameIndex : ISD::FrameIndex; 1015 FoldingSetNodeID ID; 1016 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 1017 ID.AddInteger(FI); 1018 void *IP = 0; 1019 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1020 return SDValue(E, 0); 1021 1022 SDNode *N = NodeAllocator.Allocate<FrameIndexSDNode>(); 1023 new (N) FrameIndexSDNode(FI, VT, isTarget); 1024 CSEMap.InsertNode(N, IP); 1025 AllNodes.push_back(N); 1026 return SDValue(N, 0); 1027} 1028 1029SDValue SelectionDAG::getJumpTable(int JTI, EVT VT, bool isTarget, 1030 unsigned char TargetFlags) { 1031 assert((TargetFlags == 0 || isTarget) && 1032 "Cannot set target flags on target-independent jump tables"); 1033 unsigned Opc = isTarget ? ISD::TargetJumpTable : ISD::JumpTable; 1034 FoldingSetNodeID ID; 1035 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 1036 ID.AddInteger(JTI); 1037 ID.AddInteger(TargetFlags); 1038 void *IP = 0; 1039 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1040 return SDValue(E, 0); 1041 1042 SDNode *N = NodeAllocator.Allocate<JumpTableSDNode>(); 1043 new (N) JumpTableSDNode(JTI, VT, isTarget, TargetFlags); 1044 CSEMap.InsertNode(N, IP); 1045 AllNodes.push_back(N); 1046 return SDValue(N, 0); 1047} 1048 1049SDValue SelectionDAG::getConstantPool(Constant *C, EVT VT, 1050 unsigned Alignment, int Offset, 1051 bool isTarget, 1052 unsigned char TargetFlags) { 1053 assert((TargetFlags == 0 || isTarget) && 1054 "Cannot set target flags on target-independent globals"); 1055 if (Alignment == 0) 1056 Alignment = TLI.getTargetData()->getPrefTypeAlignment(C->getType()); 1057 unsigned Opc = isTarget ? ISD::TargetConstantPool : ISD::ConstantPool; 1058 FoldingSetNodeID ID; 1059 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 1060 ID.AddInteger(Alignment); 1061 ID.AddInteger(Offset); 1062 ID.AddPointer(C); 1063 ID.AddInteger(TargetFlags); 1064 void *IP = 0; 1065 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1066 return SDValue(E, 0); 1067 1068 SDNode *N = NodeAllocator.Allocate<ConstantPoolSDNode>(); 1069 new (N) ConstantPoolSDNode(isTarget, C, VT, Offset, Alignment, TargetFlags); 1070 CSEMap.InsertNode(N, IP); 1071 AllNodes.push_back(N); 1072 return SDValue(N, 0); 1073} 1074 1075 1076SDValue SelectionDAG::getConstantPool(MachineConstantPoolValue *C, EVT VT, 1077 unsigned Alignment, int Offset, 1078 bool isTarget, 1079 unsigned char TargetFlags) { 1080 assert((TargetFlags == 0 || isTarget) && 1081 "Cannot set target flags on target-independent globals"); 1082 if (Alignment == 0) 1083 Alignment = TLI.getTargetData()->getPrefTypeAlignment(C->getType()); 1084 unsigned Opc = isTarget ? ISD::TargetConstantPool : ISD::ConstantPool; 1085 FoldingSetNodeID ID; 1086 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 1087 ID.AddInteger(Alignment); 1088 ID.AddInteger(Offset); 1089 C->AddSelectionDAGCSEId(ID); 1090 ID.AddInteger(TargetFlags); 1091 void *IP = 0; 1092 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1093 return SDValue(E, 0); 1094 1095 SDNode *N = NodeAllocator.Allocate<ConstantPoolSDNode>(); 1096 new (N) ConstantPoolSDNode(isTarget, C, VT, Offset, Alignment, TargetFlags); 1097 CSEMap.InsertNode(N, IP); 1098 AllNodes.push_back(N); 1099 return SDValue(N, 0); 1100} 1101 1102SDValue SelectionDAG::getBasicBlock(MachineBasicBlock *MBB) { 1103 FoldingSetNodeID ID; 1104 AddNodeIDNode(ID, ISD::BasicBlock, getVTList(MVT::Other), 0, 0); 1105 ID.AddPointer(MBB); 1106 void *IP = 0; 1107 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1108 return SDValue(E, 0); 1109 1110 SDNode *N = NodeAllocator.Allocate<BasicBlockSDNode>(); 1111 new (N) BasicBlockSDNode(MBB); 1112 CSEMap.InsertNode(N, IP); 1113 AllNodes.push_back(N); 1114 return SDValue(N, 0); 1115} 1116 1117SDValue SelectionDAG::getValueType(EVT VT) { 1118 if (VT.isSimple() && (unsigned)VT.getSimpleVT().SimpleTy >= 1119 ValueTypeNodes.size()) 1120 ValueTypeNodes.resize(VT.getSimpleVT().SimpleTy+1); 1121 1122 SDNode *&N = VT.isExtended() ? 1123 ExtendedValueTypeNodes[VT] : ValueTypeNodes[VT.getSimpleVT().SimpleTy]; 1124 1125 if (N) return SDValue(N, 0); 1126 N = NodeAllocator.Allocate<VTSDNode>(); 1127 new (N) VTSDNode(VT); 1128 AllNodes.push_back(N); 1129 return SDValue(N, 0); 1130} 1131 1132SDValue SelectionDAG::getExternalSymbol(const char *Sym, EVT VT) { 1133 SDNode *&N = ExternalSymbols[Sym]; 1134 if (N) return SDValue(N, 0); 1135 N = NodeAllocator.Allocate<ExternalSymbolSDNode>(); 1136 new (N) ExternalSymbolSDNode(false, Sym, 0, VT); 1137 AllNodes.push_back(N); 1138 return SDValue(N, 0); 1139} 1140 1141SDValue SelectionDAG::getTargetExternalSymbol(const char *Sym, EVT VT, 1142 unsigned char TargetFlags) { 1143 SDNode *&N = 1144 TargetExternalSymbols[std::pair<std::string,unsigned char>(Sym, 1145 TargetFlags)]; 1146 if (N) return SDValue(N, 0); 1147 N = NodeAllocator.Allocate<ExternalSymbolSDNode>(); 1148 new (N) ExternalSymbolSDNode(true, Sym, TargetFlags, VT); 1149 AllNodes.push_back(N); 1150 return SDValue(N, 0); 1151} 1152 1153SDValue SelectionDAG::getCondCode(ISD::CondCode Cond) { 1154 if ((unsigned)Cond >= CondCodeNodes.size()) 1155 CondCodeNodes.resize(Cond+1); 1156 1157 if (CondCodeNodes[Cond] == 0) { 1158 CondCodeSDNode *N = NodeAllocator.Allocate<CondCodeSDNode>(); 1159 new (N) CondCodeSDNode(Cond); 1160 CondCodeNodes[Cond] = N; 1161 AllNodes.push_back(N); 1162 } 1163 1164 return SDValue(CondCodeNodes[Cond], 0); 1165} 1166 1167// commuteShuffle - swaps the values of N1 and N2, and swaps all indices in 1168// the shuffle mask M that point at N1 to point at N2, and indices that point 1169// N2 to point at N1. 1170static void commuteShuffle(SDValue &N1, SDValue &N2, SmallVectorImpl<int> &M) { 1171 std::swap(N1, N2); 1172 int NElts = M.size(); 1173 for (int i = 0; i != NElts; ++i) { 1174 if (M[i] >= NElts) 1175 M[i] -= NElts; 1176 else if (M[i] >= 0) 1177 M[i] += NElts; 1178 } 1179} 1180 1181SDValue SelectionDAG::getVectorShuffle(EVT VT, DebugLoc dl, SDValue N1, 1182 SDValue N2, const int *Mask) { 1183 assert(N1.getValueType() == N2.getValueType() && "Invalid VECTOR_SHUFFLE"); 1184 assert(VT.isVector() && N1.getValueType().isVector() && 1185 "Vector Shuffle VTs must be a vectors"); 1186 assert(VT.getVectorElementType() == N1.getValueType().getVectorElementType() 1187 && "Vector Shuffle VTs must have same element type"); 1188 1189 // Canonicalize shuffle undef, undef -> undef 1190 if (N1.getOpcode() == ISD::UNDEF && N2.getOpcode() == ISD::UNDEF) 1191 return getUNDEF(VT); 1192 1193 // Validate that all indices in Mask are within the range of the elements 1194 // input to the shuffle. 1195 unsigned NElts = VT.getVectorNumElements(); 1196 SmallVector<int, 8> MaskVec; 1197 for (unsigned i = 0; i != NElts; ++i) { 1198 assert(Mask[i] < (int)(NElts * 2) && "Index out of range"); 1199 MaskVec.push_back(Mask[i]); 1200 } 1201 1202 // Canonicalize shuffle v, v -> v, undef 1203 if (N1 == N2) { 1204 N2 = getUNDEF(VT); 1205 for (unsigned i = 0; i != NElts; ++i) 1206 if (MaskVec[i] >= (int)NElts) MaskVec[i] -= NElts; 1207 } 1208 1209 // Canonicalize shuffle undef, v -> v, undef. Commute the shuffle mask. 1210 if (N1.getOpcode() == ISD::UNDEF) 1211 commuteShuffle(N1, N2, MaskVec); 1212 1213 // Canonicalize all index into lhs, -> shuffle lhs, undef 1214 // Canonicalize all index into rhs, -> shuffle rhs, undef 1215 bool AllLHS = true, AllRHS = true; 1216 bool N2Undef = N2.getOpcode() == ISD::UNDEF; 1217 for (unsigned i = 0; i != NElts; ++i) { 1218 if (MaskVec[i] >= (int)NElts) { 1219 if (N2Undef) 1220 MaskVec[i] = -1; 1221 else 1222 AllLHS = false; 1223 } else if (MaskVec[i] >= 0) { 1224 AllRHS = false; 1225 } 1226 } 1227 if (AllLHS && AllRHS) 1228 return getUNDEF(VT); 1229 if (AllLHS && !N2Undef) 1230 N2 = getUNDEF(VT); 1231 if (AllRHS) { 1232 N1 = getUNDEF(VT); 1233 commuteShuffle(N1, N2, MaskVec); 1234 } 1235 1236 // If Identity shuffle, or all shuffle in to undef, return that node. 1237 bool AllUndef = true; 1238 bool Identity = true; 1239 for (unsigned i = 0; i != NElts; ++i) { 1240 if (MaskVec[i] >= 0 && MaskVec[i] != (int)i) Identity = false; 1241 if (MaskVec[i] >= 0) AllUndef = false; 1242 } 1243 if (Identity && NElts == N1.getValueType().getVectorNumElements()) 1244 return N1; 1245 if (AllUndef) 1246 return getUNDEF(VT); 1247 1248 FoldingSetNodeID ID; 1249 SDValue Ops[2] = { N1, N2 }; 1250 AddNodeIDNode(ID, ISD::VECTOR_SHUFFLE, getVTList(VT), Ops, 2); 1251 for (unsigned i = 0; i != NElts; ++i) 1252 ID.AddInteger(MaskVec[i]); 1253 1254 void* IP = 0; 1255 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1256 return SDValue(E, 0); 1257 1258 // Allocate the mask array for the node out of the BumpPtrAllocator, since 1259 // SDNode doesn't have access to it. This memory will be "leaked" when 1260 // the node is deallocated, but recovered when the NodeAllocator is released. 1261 int *MaskAlloc = OperandAllocator.Allocate<int>(NElts); 1262 memcpy(MaskAlloc, &MaskVec[0], NElts * sizeof(int)); 1263 1264 ShuffleVectorSDNode *N = NodeAllocator.Allocate<ShuffleVectorSDNode>(); 1265 new (N) ShuffleVectorSDNode(VT, dl, N1, N2, MaskAlloc); 1266 CSEMap.InsertNode(N, IP); 1267 AllNodes.push_back(N); 1268 return SDValue(N, 0); 1269} 1270 1271SDValue SelectionDAG::getConvertRndSat(EVT VT, DebugLoc dl, 1272 SDValue Val, SDValue DTy, 1273 SDValue STy, SDValue Rnd, SDValue Sat, 1274 ISD::CvtCode Code) { 1275 // If the src and dest types are the same and the conversion is between 1276 // integer types of the same sign or two floats, no conversion is necessary. 1277 if (DTy == STy && 1278 (Code == ISD::CVT_UU || Code == ISD::CVT_SS || Code == ISD::CVT_FF)) 1279 return Val; 1280 1281 FoldingSetNodeID ID; 1282 SDValue Ops[] = { Val, DTy, STy, Rnd, Sat }; 1283 AddNodeIDNode(ID, ISD::CONVERT_RNDSAT, getVTList(VT), &Ops[0], 5); 1284 void* IP = 0; 1285 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1286 return SDValue(E, 0); 1287 1288 CvtRndSatSDNode *N = NodeAllocator.Allocate<CvtRndSatSDNode>(); 1289 new (N) CvtRndSatSDNode(VT, dl, Ops, 5, Code); 1290 CSEMap.InsertNode(N, IP); 1291 AllNodes.push_back(N); 1292 return SDValue(N, 0); 1293} 1294 1295SDValue SelectionDAG::getRegister(unsigned RegNo, EVT VT) { 1296 FoldingSetNodeID ID; 1297 AddNodeIDNode(ID, ISD::Register, getVTList(VT), 0, 0); 1298 ID.AddInteger(RegNo); 1299 void *IP = 0; 1300 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1301 return SDValue(E, 0); 1302 1303 SDNode *N = NodeAllocator.Allocate<RegisterSDNode>(); 1304 new (N) RegisterSDNode(RegNo, VT); 1305 CSEMap.InsertNode(N, IP); 1306 AllNodes.push_back(N); 1307 return SDValue(N, 0); 1308} 1309 1310SDValue SelectionDAG::getLabel(unsigned Opcode, DebugLoc dl, 1311 SDValue Root, 1312 unsigned LabelID) { 1313 FoldingSetNodeID ID; 1314 SDValue Ops[] = { Root }; 1315 AddNodeIDNode(ID, Opcode, getVTList(MVT::Other), &Ops[0], 1); 1316 ID.AddInteger(LabelID); 1317 void *IP = 0; 1318 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1319 return SDValue(E, 0); 1320 1321 SDNode *N = NodeAllocator.Allocate<LabelSDNode>(); 1322 new (N) LabelSDNode(Opcode, dl, Root, LabelID); 1323 CSEMap.InsertNode(N, IP); 1324 AllNodes.push_back(N); 1325 return SDValue(N, 0); 1326} 1327 1328SDValue SelectionDAG::getBlockAddress(BlockAddress *BA, EVT VT, 1329 bool isTarget, 1330 unsigned char TargetFlags) { 1331 unsigned Opc = isTarget ? ISD::TargetBlockAddress : ISD::BlockAddress; 1332 1333 FoldingSetNodeID ID; 1334 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 1335 ID.AddPointer(BA); 1336 ID.AddInteger(TargetFlags); 1337 void *IP = 0; 1338 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1339 return SDValue(E, 0); 1340 1341 SDNode *N = NodeAllocator.Allocate<BlockAddressSDNode>(); 1342 new (N) BlockAddressSDNode(Opc, VT, BA, TargetFlags); 1343 CSEMap.InsertNode(N, IP); 1344 AllNodes.push_back(N); 1345 return SDValue(N, 0); 1346} 1347 1348SDValue SelectionDAG::getSrcValue(const Value *V) { 1349 assert((!V || isa<PointerType>(V->getType())) && 1350 "SrcValue is not a pointer?"); 1351 1352 FoldingSetNodeID ID; 1353 AddNodeIDNode(ID, ISD::SRCVALUE, getVTList(MVT::Other), 0, 0); 1354 ID.AddPointer(V); 1355 1356 void *IP = 0; 1357 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1358 return SDValue(E, 0); 1359 1360 SDNode *N = NodeAllocator.Allocate<SrcValueSDNode>(); 1361 new (N) SrcValueSDNode(V); 1362 CSEMap.InsertNode(N, IP); 1363 AllNodes.push_back(N); 1364 return SDValue(N, 0); 1365} 1366 1367/// getShiftAmountOperand - Return the specified value casted to 1368/// the target's desired shift amount type. 1369SDValue SelectionDAG::getShiftAmountOperand(SDValue Op) { 1370 EVT OpTy = Op.getValueType(); 1371 MVT ShTy = TLI.getShiftAmountTy(); 1372 if (OpTy == ShTy || OpTy.isVector()) return Op; 1373 1374 ISD::NodeType Opcode = OpTy.bitsGT(ShTy) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; 1375 return getNode(Opcode, Op.getDebugLoc(), ShTy, Op); 1376} 1377 1378/// CreateStackTemporary - Create a stack temporary, suitable for holding the 1379/// specified value type. 1380SDValue SelectionDAG::CreateStackTemporary(EVT VT, unsigned minAlign) { 1381 MachineFrameInfo *FrameInfo = getMachineFunction().getFrameInfo(); 1382 unsigned ByteSize = VT.getStoreSize(); 1383 const Type *Ty = VT.getTypeForEVT(*getContext()); 1384 unsigned StackAlign = 1385 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), minAlign); 1386 1387 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, StackAlign, false); 1388 return getFrameIndex(FrameIdx, TLI.getPointerTy()); 1389} 1390 1391/// CreateStackTemporary - Create a stack temporary suitable for holding 1392/// either of the specified value types. 1393SDValue SelectionDAG::CreateStackTemporary(EVT VT1, EVT VT2) { 1394 unsigned Bytes = std::max(VT1.getStoreSizeInBits(), 1395 VT2.getStoreSizeInBits())/8; 1396 const Type *Ty1 = VT1.getTypeForEVT(*getContext()); 1397 const Type *Ty2 = VT2.getTypeForEVT(*getContext()); 1398 const TargetData *TD = TLI.getTargetData(); 1399 unsigned Align = std::max(TD->getPrefTypeAlignment(Ty1), 1400 TD->getPrefTypeAlignment(Ty2)); 1401 1402 MachineFrameInfo *FrameInfo = getMachineFunction().getFrameInfo(); 1403 int FrameIdx = FrameInfo->CreateStackObject(Bytes, Align, false); 1404 return getFrameIndex(FrameIdx, TLI.getPointerTy()); 1405} 1406 1407SDValue SelectionDAG::FoldSetCC(EVT VT, SDValue N1, 1408 SDValue N2, ISD::CondCode Cond, DebugLoc dl) { 1409 // These setcc operations always fold. 1410 switch (Cond) { 1411 default: break; 1412 case ISD::SETFALSE: 1413 case ISD::SETFALSE2: return getConstant(0, VT); 1414 case ISD::SETTRUE: 1415 case ISD::SETTRUE2: return getConstant(1, VT); 1416 1417 case ISD::SETOEQ: 1418 case ISD::SETOGT: 1419 case ISD::SETOGE: 1420 case ISD::SETOLT: 1421 case ISD::SETOLE: 1422 case ISD::SETONE: 1423 case ISD::SETO: 1424 case ISD::SETUO: 1425 case ISD::SETUEQ: 1426 case ISD::SETUNE: 1427 assert(!N1.getValueType().isInteger() && "Illegal setcc for integer!"); 1428 break; 1429 } 1430 1431 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode())) { 1432 const APInt &C2 = N2C->getAPIntValue(); 1433 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) { 1434 const APInt &C1 = N1C->getAPIntValue(); 1435 1436 switch (Cond) { 1437 default: llvm_unreachable("Unknown integer setcc!"); 1438 case ISD::SETEQ: return getConstant(C1 == C2, VT); 1439 case ISD::SETNE: return getConstant(C1 != C2, VT); 1440 case ISD::SETULT: return getConstant(C1.ult(C2), VT); 1441 case ISD::SETUGT: return getConstant(C1.ugt(C2), VT); 1442 case ISD::SETULE: return getConstant(C1.ule(C2), VT); 1443 case ISD::SETUGE: return getConstant(C1.uge(C2), VT); 1444 case ISD::SETLT: return getConstant(C1.slt(C2), VT); 1445 case ISD::SETGT: return getConstant(C1.sgt(C2), VT); 1446 case ISD::SETLE: return getConstant(C1.sle(C2), VT); 1447 case ISD::SETGE: return getConstant(C1.sge(C2), VT); 1448 } 1449 } 1450 } 1451 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.getNode())) { 1452 if (ConstantFPSDNode *N2C = dyn_cast<ConstantFPSDNode>(N2.getNode())) { 1453 // No compile time operations on this type yet. 1454 if (N1C->getValueType(0) == MVT::ppcf128) 1455 return SDValue(); 1456 1457 APFloat::cmpResult R = N1C->getValueAPF().compare(N2C->getValueAPF()); 1458 switch (Cond) { 1459 default: break; 1460 case ISD::SETEQ: if (R==APFloat::cmpUnordered) 1461 return getUNDEF(VT); 1462 // fall through 1463 case ISD::SETOEQ: return getConstant(R==APFloat::cmpEqual, VT); 1464 case ISD::SETNE: if (R==APFloat::cmpUnordered) 1465 return getUNDEF(VT); 1466 // fall through 1467 case ISD::SETONE: return getConstant(R==APFloat::cmpGreaterThan || 1468 R==APFloat::cmpLessThan, VT); 1469 case ISD::SETLT: if (R==APFloat::cmpUnordered) 1470 return getUNDEF(VT); 1471 // fall through 1472 case ISD::SETOLT: return getConstant(R==APFloat::cmpLessThan, VT); 1473 case ISD::SETGT: if (R==APFloat::cmpUnordered) 1474 return getUNDEF(VT); 1475 // fall through 1476 case ISD::SETOGT: return getConstant(R==APFloat::cmpGreaterThan, VT); 1477 case ISD::SETLE: if (R==APFloat::cmpUnordered) 1478 return getUNDEF(VT); 1479 // fall through 1480 case ISD::SETOLE: return getConstant(R==APFloat::cmpLessThan || 1481 R==APFloat::cmpEqual, VT); 1482 case ISD::SETGE: if (R==APFloat::cmpUnordered) 1483 return getUNDEF(VT); 1484 // fall through 1485 case ISD::SETOGE: return getConstant(R==APFloat::cmpGreaterThan || 1486 R==APFloat::cmpEqual, VT); 1487 case ISD::SETO: return getConstant(R!=APFloat::cmpUnordered, VT); 1488 case ISD::SETUO: return getConstant(R==APFloat::cmpUnordered, VT); 1489 case ISD::SETUEQ: return getConstant(R==APFloat::cmpUnordered || 1490 R==APFloat::cmpEqual, VT); 1491 case ISD::SETUNE: return getConstant(R!=APFloat::cmpEqual, VT); 1492 case ISD::SETULT: return getConstant(R==APFloat::cmpUnordered || 1493 R==APFloat::cmpLessThan, VT); 1494 case ISD::SETUGT: return getConstant(R==APFloat::cmpGreaterThan || 1495 R==APFloat::cmpUnordered, VT); 1496 case ISD::SETULE: return getConstant(R!=APFloat::cmpGreaterThan, VT); 1497 case ISD::SETUGE: return getConstant(R!=APFloat::cmpLessThan, VT); 1498 } 1499 } else { 1500 // Ensure that the constant occurs on the RHS. 1501 return getSetCC(dl, VT, N2, N1, ISD::getSetCCSwappedOperands(Cond)); 1502 } 1503 } 1504 1505 // Could not fold it. 1506 return SDValue(); 1507} 1508 1509/// SignBitIsZero - Return true if the sign bit of Op is known to be zero. We 1510/// use this predicate to simplify operations downstream. 1511bool SelectionDAG::SignBitIsZero(SDValue Op, unsigned Depth) const { 1512 // This predicate is not safe for vector operations. 1513 if (Op.getValueType().isVector()) 1514 return false; 1515 1516 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits(); 1517 return MaskedValueIsZero(Op, APInt::getSignBit(BitWidth), Depth); 1518} 1519 1520/// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero. We use 1521/// this predicate to simplify operations downstream. Mask is known to be zero 1522/// for bits that V cannot have. 1523bool SelectionDAG::MaskedValueIsZero(SDValue Op, const APInt &Mask, 1524 unsigned Depth) const { 1525 APInt KnownZero, KnownOne; 1526 ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth); 1527 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1528 return (KnownZero & Mask) == Mask; 1529} 1530 1531/// ComputeMaskedBits - Determine which of the bits specified in Mask are 1532/// known to be either zero or one and return them in the KnownZero/KnownOne 1533/// bitsets. This code only analyzes bits in Mask, in order to short-circuit 1534/// processing. 1535void SelectionDAG::ComputeMaskedBits(SDValue Op, const APInt &Mask, 1536 APInt &KnownZero, APInt &KnownOne, 1537 unsigned Depth) const { 1538 unsigned BitWidth = Mask.getBitWidth(); 1539 assert(BitWidth == Op.getValueType().getScalarType().getSizeInBits() && 1540 "Mask size mismatches value type size!"); 1541 1542 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything. 1543 if (Depth == 6 || Mask == 0) 1544 return; // Limit search depth. 1545 1546 APInt KnownZero2, KnownOne2; 1547 1548 switch (Op.getOpcode()) { 1549 case ISD::Constant: 1550 // We know all of the bits for a constant! 1551 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & Mask; 1552 KnownZero = ~KnownOne & Mask; 1553 return; 1554 case ISD::AND: 1555 // If either the LHS or the RHS are Zero, the result is zero. 1556 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1557 ComputeMaskedBits(Op.getOperand(0), Mask & ~KnownZero, 1558 KnownZero2, KnownOne2, Depth+1); 1559 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1560 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1561 1562 // Output known-1 bits are only known if set in both the LHS & RHS. 1563 KnownOne &= KnownOne2; 1564 // Output known-0 are known to be clear if zero in either the LHS | RHS. 1565 KnownZero |= KnownZero2; 1566 return; 1567 case ISD::OR: 1568 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1569 ComputeMaskedBits(Op.getOperand(0), Mask & ~KnownOne, 1570 KnownZero2, KnownOne2, Depth+1); 1571 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1572 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1573 1574 // Output known-0 bits are only known if clear in both the LHS & RHS. 1575 KnownZero &= KnownZero2; 1576 // Output known-1 are known to be set if set in either the LHS | RHS. 1577 KnownOne |= KnownOne2; 1578 return; 1579 case ISD::XOR: { 1580 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1581 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1); 1582 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1583 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1584 1585 // Output known-0 bits are known if clear or set in both the LHS & RHS. 1586 APInt KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 1587 // Output known-1 are known to be set if set in only one of the LHS, RHS. 1588 KnownOne = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 1589 KnownZero = KnownZeroOut; 1590 return; 1591 } 1592 case ISD::MUL: { 1593 APInt Mask2 = APInt::getAllOnesValue(BitWidth); 1594 ComputeMaskedBits(Op.getOperand(1), Mask2, KnownZero, KnownOne, Depth+1); 1595 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero2, KnownOne2, Depth+1); 1596 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1597 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1598 1599 // If low bits are zero in either operand, output low known-0 bits. 1600 // Also compute a conserative estimate for high known-0 bits. 1601 // More trickiness is possible, but this is sufficient for the 1602 // interesting case of alignment computation. 1603 KnownOne.clear(); 1604 unsigned TrailZ = KnownZero.countTrailingOnes() + 1605 KnownZero2.countTrailingOnes(); 1606 unsigned LeadZ = std::max(KnownZero.countLeadingOnes() + 1607 KnownZero2.countLeadingOnes(), 1608 BitWidth) - BitWidth; 1609 1610 TrailZ = std::min(TrailZ, BitWidth); 1611 LeadZ = std::min(LeadZ, BitWidth); 1612 KnownZero = APInt::getLowBitsSet(BitWidth, TrailZ) | 1613 APInt::getHighBitsSet(BitWidth, LeadZ); 1614 KnownZero &= Mask; 1615 return; 1616 } 1617 case ISD::UDIV: { 1618 // For the purposes of computing leading zeros we can conservatively 1619 // treat a udiv as a logical right shift by the power of 2 known to 1620 // be less than the denominator. 1621 APInt AllOnes = APInt::getAllOnesValue(BitWidth); 1622 ComputeMaskedBits(Op.getOperand(0), 1623 AllOnes, KnownZero2, KnownOne2, Depth+1); 1624 unsigned LeadZ = KnownZero2.countLeadingOnes(); 1625 1626 KnownOne2.clear(); 1627 KnownZero2.clear(); 1628 ComputeMaskedBits(Op.getOperand(1), 1629 AllOnes, KnownZero2, KnownOne2, Depth+1); 1630 unsigned RHSUnknownLeadingOnes = KnownOne2.countLeadingZeros(); 1631 if (RHSUnknownLeadingOnes != BitWidth) 1632 LeadZ = std::min(BitWidth, 1633 LeadZ + BitWidth - RHSUnknownLeadingOnes - 1); 1634 1635 KnownZero = APInt::getHighBitsSet(BitWidth, LeadZ) & Mask; 1636 return; 1637 } 1638 case ISD::SELECT: 1639 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero, KnownOne, Depth+1); 1640 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero2, KnownOne2, Depth+1); 1641 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1642 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1643 1644 // Only known if known in both the LHS and RHS. 1645 KnownOne &= KnownOne2; 1646 KnownZero &= KnownZero2; 1647 return; 1648 case ISD::SELECT_CC: 1649 ComputeMaskedBits(Op.getOperand(3), Mask, KnownZero, KnownOne, Depth+1); 1650 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero2, KnownOne2, Depth+1); 1651 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1652 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1653 1654 // Only known if known in both the LHS and RHS. 1655 KnownOne &= KnownOne2; 1656 KnownZero &= KnownZero2; 1657 return; 1658 case ISD::SADDO: 1659 case ISD::UADDO: 1660 case ISD::SSUBO: 1661 case ISD::USUBO: 1662 case ISD::SMULO: 1663 case ISD::UMULO: 1664 if (Op.getResNo() != 1) 1665 return; 1666 // The boolean result conforms to getBooleanContents. Fall through. 1667 case ISD::SETCC: 1668 // If we know the result of a setcc has the top bits zero, use this info. 1669 if (TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent && 1670 BitWidth > 1) 1671 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1); 1672 return; 1673 case ISD::SHL: 1674 // (shl X, C1) & C2 == 0 iff (X & C2 >>u C1) == 0 1675 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1676 unsigned ShAmt = SA->getZExtValue(); 1677 1678 // If the shift count is an invalid immediate, don't do anything. 1679 if (ShAmt >= BitWidth) 1680 return; 1681 1682 ComputeMaskedBits(Op.getOperand(0), Mask.lshr(ShAmt), 1683 KnownZero, KnownOne, Depth+1); 1684 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1685 KnownZero <<= ShAmt; 1686 KnownOne <<= ShAmt; 1687 // low bits known zero. 1688 KnownZero |= APInt::getLowBitsSet(BitWidth, ShAmt); 1689 } 1690 return; 1691 case ISD::SRL: 1692 // (ushr X, C1) & C2 == 0 iff (-1 >> C1) & C2 == 0 1693 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1694 unsigned ShAmt = SA->getZExtValue(); 1695 1696 // If the shift count is an invalid immediate, don't do anything. 1697 if (ShAmt >= BitWidth) 1698 return; 1699 1700 ComputeMaskedBits(Op.getOperand(0), (Mask << ShAmt), 1701 KnownZero, KnownOne, Depth+1); 1702 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1703 KnownZero = KnownZero.lshr(ShAmt); 1704 KnownOne = KnownOne.lshr(ShAmt); 1705 1706 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt) & Mask; 1707 KnownZero |= HighBits; // High bits known zero. 1708 } 1709 return; 1710 case ISD::SRA: 1711 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1712 unsigned ShAmt = SA->getZExtValue(); 1713 1714 // If the shift count is an invalid immediate, don't do anything. 1715 if (ShAmt >= BitWidth) 1716 return; 1717 1718 APInt InDemandedMask = (Mask << ShAmt); 1719 // If any of the demanded bits are produced by the sign extension, we also 1720 // demand the input sign bit. 1721 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt) & Mask; 1722 if (HighBits.getBoolValue()) 1723 InDemandedMask |= APInt::getSignBit(BitWidth); 1724 1725 ComputeMaskedBits(Op.getOperand(0), InDemandedMask, KnownZero, KnownOne, 1726 Depth+1); 1727 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1728 KnownZero = KnownZero.lshr(ShAmt); 1729 KnownOne = KnownOne.lshr(ShAmt); 1730 1731 // Handle the sign bits. 1732 APInt SignBit = APInt::getSignBit(BitWidth); 1733 SignBit = SignBit.lshr(ShAmt); // Adjust to where it is now in the mask. 1734 1735 if (KnownZero.intersects(SignBit)) { 1736 KnownZero |= HighBits; // New bits are known zero. 1737 } else if (KnownOne.intersects(SignBit)) { 1738 KnownOne |= HighBits; // New bits are known one. 1739 } 1740 } 1741 return; 1742 case ISD::SIGN_EXTEND_INREG: { 1743 EVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1744 unsigned EBits = EVT.getScalarType().getSizeInBits(); 1745 1746 // Sign extension. Compute the demanded bits in the result that are not 1747 // present in the input. 1748 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - EBits) & Mask; 1749 1750 APInt InSignBit = APInt::getSignBit(EBits); 1751 APInt InputDemandedBits = Mask & APInt::getLowBitsSet(BitWidth, EBits); 1752 1753 // If the sign extended bits are demanded, we know that the sign 1754 // bit is demanded. 1755 InSignBit.zext(BitWidth); 1756 if (NewBits.getBoolValue()) 1757 InputDemandedBits |= InSignBit; 1758 1759 ComputeMaskedBits(Op.getOperand(0), InputDemandedBits, 1760 KnownZero, KnownOne, Depth+1); 1761 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1762 1763 // If the sign bit of the input is known set or clear, then we know the 1764 // top bits of the result. 1765 if (KnownZero.intersects(InSignBit)) { // Input sign bit known clear 1766 KnownZero |= NewBits; 1767 KnownOne &= ~NewBits; 1768 } else if (KnownOne.intersects(InSignBit)) { // Input sign bit known set 1769 KnownOne |= NewBits; 1770 KnownZero &= ~NewBits; 1771 } else { // Input sign bit unknown 1772 KnownZero &= ~NewBits; 1773 KnownOne &= ~NewBits; 1774 } 1775 return; 1776 } 1777 case ISD::CTTZ: 1778 case ISD::CTLZ: 1779 case ISD::CTPOP: { 1780 unsigned LowBits = Log2_32(BitWidth)+1; 1781 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - LowBits); 1782 KnownOne.clear(); 1783 return; 1784 } 1785 case ISD::LOAD: { 1786 if (ISD::isZEXTLoad(Op.getNode())) { 1787 LoadSDNode *LD = cast<LoadSDNode>(Op); 1788 EVT VT = LD->getMemoryVT(); 1789 unsigned MemBits = VT.getScalarType().getSizeInBits(); 1790 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits) & Mask; 1791 } 1792 return; 1793 } 1794 case ISD::ZERO_EXTEND: { 1795 EVT InVT = Op.getOperand(0).getValueType(); 1796 unsigned InBits = InVT.getScalarType().getSizeInBits(); 1797 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - InBits) & Mask; 1798 APInt InMask = Mask; 1799 InMask.trunc(InBits); 1800 KnownZero.trunc(InBits); 1801 KnownOne.trunc(InBits); 1802 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1803 KnownZero.zext(BitWidth); 1804 KnownOne.zext(BitWidth); 1805 KnownZero |= NewBits; 1806 return; 1807 } 1808 case ISD::SIGN_EXTEND: { 1809 EVT InVT = Op.getOperand(0).getValueType(); 1810 unsigned InBits = InVT.getScalarType().getSizeInBits(); 1811 APInt InSignBit = APInt::getSignBit(InBits); 1812 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - InBits) & Mask; 1813 APInt InMask = Mask; 1814 InMask.trunc(InBits); 1815 1816 // If any of the sign extended bits are demanded, we know that the sign 1817 // bit is demanded. Temporarily set this bit in the mask for our callee. 1818 if (NewBits.getBoolValue()) 1819 InMask |= InSignBit; 1820 1821 KnownZero.trunc(InBits); 1822 KnownOne.trunc(InBits); 1823 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1824 1825 // Note if the sign bit is known to be zero or one. 1826 bool SignBitKnownZero = KnownZero.isNegative(); 1827 bool SignBitKnownOne = KnownOne.isNegative(); 1828 assert(!(SignBitKnownZero && SignBitKnownOne) && 1829 "Sign bit can't be known to be both zero and one!"); 1830 1831 // If the sign bit wasn't actually demanded by our caller, we don't 1832 // want it set in the KnownZero and KnownOne result values. Reset the 1833 // mask and reapply it to the result values. 1834 InMask = Mask; 1835 InMask.trunc(InBits); 1836 KnownZero &= InMask; 1837 KnownOne &= InMask; 1838 1839 KnownZero.zext(BitWidth); 1840 KnownOne.zext(BitWidth); 1841 1842 // If the sign bit is known zero or one, the top bits match. 1843 if (SignBitKnownZero) 1844 KnownZero |= NewBits; 1845 else if (SignBitKnownOne) 1846 KnownOne |= NewBits; 1847 return; 1848 } 1849 case ISD::ANY_EXTEND: { 1850 EVT InVT = Op.getOperand(0).getValueType(); 1851 unsigned InBits = InVT.getScalarType().getSizeInBits(); 1852 APInt InMask = Mask; 1853 InMask.trunc(InBits); 1854 KnownZero.trunc(InBits); 1855 KnownOne.trunc(InBits); 1856 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1857 KnownZero.zext(BitWidth); 1858 KnownOne.zext(BitWidth); 1859 return; 1860 } 1861 case ISD::TRUNCATE: { 1862 EVT InVT = Op.getOperand(0).getValueType(); 1863 unsigned InBits = InVT.getScalarType().getSizeInBits(); 1864 APInt InMask = Mask; 1865 InMask.zext(InBits); 1866 KnownZero.zext(InBits); 1867 KnownOne.zext(InBits); 1868 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1869 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1870 KnownZero.trunc(BitWidth); 1871 KnownOne.trunc(BitWidth); 1872 break; 1873 } 1874 case ISD::AssertZext: { 1875 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1876 APInt InMask = APInt::getLowBitsSet(BitWidth, VT.getSizeInBits()); 1877 ComputeMaskedBits(Op.getOperand(0), Mask & InMask, KnownZero, 1878 KnownOne, Depth+1); 1879 KnownZero |= (~InMask) & Mask; 1880 return; 1881 } 1882 case ISD::FGETSIGN: 1883 // All bits are zero except the low bit. 1884 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - 1); 1885 return; 1886 1887 case ISD::SUB: { 1888 if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) { 1889 // We know that the top bits of C-X are clear if X contains less bits 1890 // than C (i.e. no wrap-around can happen). For example, 20-X is 1891 // positive if we can prove that X is >= 0 and < 16. 1892 if (CLHS->getAPIntValue().isNonNegative()) { 1893 unsigned NLZ = (CLHS->getAPIntValue()+1).countLeadingZeros(); 1894 // NLZ can't be BitWidth with no sign bit 1895 APInt MaskV = APInt::getHighBitsSet(BitWidth, NLZ+1); 1896 ComputeMaskedBits(Op.getOperand(1), MaskV, KnownZero2, KnownOne2, 1897 Depth+1); 1898 1899 // If all of the MaskV bits are known to be zero, then we know the 1900 // output top bits are zero, because we now know that the output is 1901 // from [0-C]. 1902 if ((KnownZero2 & MaskV) == MaskV) { 1903 unsigned NLZ2 = CLHS->getAPIntValue().countLeadingZeros(); 1904 // Top bits known zero. 1905 KnownZero = APInt::getHighBitsSet(BitWidth, NLZ2) & Mask; 1906 } 1907 } 1908 } 1909 } 1910 // fall through 1911 case ISD::ADD: { 1912 // Output known-0 bits are known if clear or set in both the low clear bits 1913 // common to both LHS & RHS. For example, 8+(X<<3) is known to have the 1914 // low 3 bits clear. 1915 APInt Mask2 = APInt::getLowBitsSet(BitWidth, Mask.countTrailingOnes()); 1916 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero2, KnownOne2, Depth+1); 1917 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1918 unsigned KnownZeroOut = KnownZero2.countTrailingOnes(); 1919 1920 ComputeMaskedBits(Op.getOperand(1), Mask2, KnownZero2, KnownOne2, Depth+1); 1921 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1922 KnownZeroOut = std::min(KnownZeroOut, 1923 KnownZero2.countTrailingOnes()); 1924 1925 KnownZero |= APInt::getLowBitsSet(BitWidth, KnownZeroOut); 1926 return; 1927 } 1928 case ISD::SREM: 1929 if (ConstantSDNode *Rem = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1930 const APInt &RA = Rem->getAPIntValue(); 1931 if (RA.isPowerOf2() || (-RA).isPowerOf2()) { 1932 APInt LowBits = RA.isStrictlyPositive() ? (RA - 1) : ~RA; 1933 APInt Mask2 = LowBits | APInt::getSignBit(BitWidth); 1934 ComputeMaskedBits(Op.getOperand(0), Mask2,KnownZero2,KnownOne2,Depth+1); 1935 1936 // If the sign bit of the first operand is zero, the sign bit of 1937 // the result is zero. If the first operand has no one bits below 1938 // the second operand's single 1 bit, its sign will be zero. 1939 if (KnownZero2[BitWidth-1] || ((KnownZero2 & LowBits) == LowBits)) 1940 KnownZero2 |= ~LowBits; 1941 1942 KnownZero |= KnownZero2 & Mask; 1943 1944 assert((KnownZero & KnownOne) == 0&&"Bits known to be one AND zero?"); 1945 } 1946 } 1947 return; 1948 case ISD::UREM: { 1949 if (ConstantSDNode *Rem = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1950 const APInt &RA = Rem->getAPIntValue(); 1951 if (RA.isPowerOf2()) { 1952 APInt LowBits = (RA - 1); 1953 APInt Mask2 = LowBits & Mask; 1954 KnownZero |= ~LowBits & Mask; 1955 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero, KnownOne,Depth+1); 1956 assert((KnownZero & KnownOne) == 0&&"Bits known to be one AND zero?"); 1957 break; 1958 } 1959 } 1960 1961 // Since the result is less than or equal to either operand, any leading 1962 // zero bits in either operand must also exist in the result. 1963 APInt AllOnes = APInt::getAllOnesValue(BitWidth); 1964 ComputeMaskedBits(Op.getOperand(0), AllOnes, KnownZero, KnownOne, 1965 Depth+1); 1966 ComputeMaskedBits(Op.getOperand(1), AllOnes, KnownZero2, KnownOne2, 1967 Depth+1); 1968 1969 uint32_t Leaders = std::max(KnownZero.countLeadingOnes(), 1970 KnownZero2.countLeadingOnes()); 1971 KnownOne.clear(); 1972 KnownZero = APInt::getHighBitsSet(BitWidth, Leaders) & Mask; 1973 return; 1974 } 1975 default: 1976 // Allow the target to implement this method for its nodes. 1977 if (Op.getOpcode() >= ISD::BUILTIN_OP_END) { 1978 case ISD::INTRINSIC_WO_CHAIN: 1979 case ISD::INTRINSIC_W_CHAIN: 1980 case ISD::INTRINSIC_VOID: 1981 TLI.computeMaskedBitsForTargetNode(Op, Mask, KnownZero, KnownOne, *this, 1982 Depth); 1983 } 1984 return; 1985 } 1986} 1987 1988/// ComputeNumSignBits - Return the number of times the sign bit of the 1989/// register is replicated into the other bits. We know that at least 1 bit 1990/// is always equal to the sign bit (itself), but other cases can give us 1991/// information. For example, immediately after an "SRA X, 2", we know that 1992/// the top 3 bits are all equal to each other, so we return 3. 1993unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, unsigned Depth) const{ 1994 EVT VT = Op.getValueType(); 1995 assert(VT.isInteger() && "Invalid VT!"); 1996 unsigned VTBits = VT.getScalarType().getSizeInBits(); 1997 unsigned Tmp, Tmp2; 1998 unsigned FirstAnswer = 1; 1999 2000 if (Depth == 6) 2001 return 1; // Limit search depth. 2002 2003 switch (Op.getOpcode()) { 2004 default: break; 2005 case ISD::AssertSext: 2006 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); 2007 return VTBits-Tmp+1; 2008 case ISD::AssertZext: 2009 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); 2010 return VTBits-Tmp; 2011 2012 case ISD::Constant: { 2013 const APInt &Val = cast<ConstantSDNode>(Op)->getAPIntValue(); 2014 // If negative, return # leading ones. 2015 if (Val.isNegative()) 2016 return Val.countLeadingOnes(); 2017 2018 // Return # leading zeros. 2019 return Val.countLeadingZeros(); 2020 } 2021 2022 case ISD::SIGN_EXTEND: 2023 Tmp = VTBits-Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 2024 return ComputeNumSignBits(Op.getOperand(0), Depth+1) + Tmp; 2025 2026 case ISD::SIGN_EXTEND_INREG: 2027 // Max of the input and what this extends. 2028 Tmp = 2029 cast<VTSDNode>(Op.getOperand(1))->getVT().getScalarType().getSizeInBits(); 2030 Tmp = VTBits-Tmp+1; 2031 2032 Tmp2 = ComputeNumSignBits(Op.getOperand(0), Depth+1); 2033 return std::max(Tmp, Tmp2); 2034 2035 case ISD::SRA: 2036 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 2037 // SRA X, C -> adds C sign bits. 2038 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 2039 Tmp += C->getZExtValue(); 2040 if (Tmp > VTBits) Tmp = VTBits; 2041 } 2042 return Tmp; 2043 case ISD::SHL: 2044 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 2045 // shl destroys sign bits. 2046 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 2047 if (C->getZExtValue() >= VTBits || // Bad shift. 2048 C->getZExtValue() >= Tmp) break; // Shifted all sign bits out. 2049 return Tmp - C->getZExtValue(); 2050 } 2051 break; 2052 case ISD::AND: 2053 case ISD::OR: 2054 case ISD::XOR: // NOT is handled here. 2055 // Logical binary ops preserve the number of sign bits at the worst. 2056 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 2057 if (Tmp != 1) { 2058 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 2059 FirstAnswer = std::min(Tmp, Tmp2); 2060 // We computed what we know about the sign bits as our first 2061 // answer. Now proceed to the generic code that uses 2062 // ComputeMaskedBits, and pick whichever answer is better. 2063 } 2064 break; 2065 2066 case ISD::SELECT: 2067 Tmp = ComputeNumSignBits(Op.getOperand(1), Depth+1); 2068 if (Tmp == 1) return 1; // Early out. 2069 Tmp2 = ComputeNumSignBits(Op.getOperand(2), Depth+1); 2070 return std::min(Tmp, Tmp2); 2071 2072 case ISD::SADDO: 2073 case ISD::UADDO: 2074 case ISD::SSUBO: 2075 case ISD::USUBO: 2076 case ISD::SMULO: 2077 case ISD::UMULO: 2078 if (Op.getResNo() != 1) 2079 break; 2080 // The boolean result conforms to getBooleanContents. Fall through. 2081 case ISD::SETCC: 2082 // If setcc returns 0/-1, all bits are sign bits. 2083 if (TLI.getBooleanContents() == 2084 TargetLowering::ZeroOrNegativeOneBooleanContent) 2085 return VTBits; 2086 break; 2087 case ISD::ROTL: 2088 case ISD::ROTR: 2089 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 2090 unsigned RotAmt = C->getZExtValue() & (VTBits-1); 2091 2092 // Handle rotate right by N like a rotate left by 32-N. 2093 if (Op.getOpcode() == ISD::ROTR) 2094 RotAmt = (VTBits-RotAmt) & (VTBits-1); 2095 2096 // If we aren't rotating out all of the known-in sign bits, return the 2097 // number that are left. This handles rotl(sext(x), 1) for example. 2098 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 2099 if (Tmp > RotAmt+1) return Tmp-RotAmt; 2100 } 2101 break; 2102 case ISD::ADD: 2103 // Add can have at most one carry bit. Thus we know that the output 2104 // is, at worst, one more bit than the inputs. 2105 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 2106 if (Tmp == 1) return 1; // Early out. 2107 2108 // Special case decrementing a value (ADD X, -1): 2109 if (ConstantSDNode *CRHS = dyn_cast<ConstantSDNode>(Op.getOperand(1))) 2110 if (CRHS->isAllOnesValue()) { 2111 APInt KnownZero, KnownOne; 2112 APInt Mask = APInt::getAllOnesValue(VTBits); 2113 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1); 2114 2115 // If the input is known to be 0 or 1, the output is 0/-1, which is all 2116 // sign bits set. 2117 if ((KnownZero | APInt(VTBits, 1)) == Mask) 2118 return VTBits; 2119 2120 // If we are subtracting one from a positive number, there is no carry 2121 // out of the result. 2122 if (KnownZero.isNegative()) 2123 return Tmp; 2124 } 2125 2126 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 2127 if (Tmp2 == 1) return 1; 2128 return std::min(Tmp, Tmp2)-1; 2129 break; 2130 2131 case ISD::SUB: 2132 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 2133 if (Tmp2 == 1) return 1; 2134 2135 // Handle NEG. 2136 if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) 2137 if (CLHS->isNullValue()) { 2138 APInt KnownZero, KnownOne; 2139 APInt Mask = APInt::getAllOnesValue(VTBits); 2140 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 2141 // If the input is known to be 0 or 1, the output is 0/-1, which is all 2142 // sign bits set. 2143 if ((KnownZero | APInt(VTBits, 1)) == Mask) 2144 return VTBits; 2145 2146 // If the input is known to be positive (the sign bit is known clear), 2147 // the output of the NEG has the same number of sign bits as the input. 2148 if (KnownZero.isNegative()) 2149 return Tmp2; 2150 2151 // Otherwise, we treat this like a SUB. 2152 } 2153 2154 // Sub can have at most one carry bit. Thus we know that the output 2155 // is, at worst, one more bit than the inputs. 2156 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 2157 if (Tmp == 1) return 1; // Early out. 2158 return std::min(Tmp, Tmp2)-1; 2159 break; 2160 case ISD::TRUNCATE: 2161 // FIXME: it's tricky to do anything useful for this, but it is an important 2162 // case for targets like X86. 2163 break; 2164 } 2165 2166 // Handle LOADX separately here. EXTLOAD case will fallthrough. 2167 if (Op.getOpcode() == ISD::LOAD) { 2168 LoadSDNode *LD = cast<LoadSDNode>(Op); 2169 unsigned ExtType = LD->getExtensionType(); 2170 switch (ExtType) { 2171 default: break; 2172 case ISD::SEXTLOAD: // '17' bits known 2173 Tmp = LD->getMemoryVT().getScalarType().getSizeInBits(); 2174 return VTBits-Tmp+1; 2175 case ISD::ZEXTLOAD: // '16' bits known 2176 Tmp = LD->getMemoryVT().getScalarType().getSizeInBits(); 2177 return VTBits-Tmp; 2178 } 2179 } 2180 2181 // Allow the target to implement this method for its nodes. 2182 if (Op.getOpcode() >= ISD::BUILTIN_OP_END || 2183 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 2184 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 2185 Op.getOpcode() == ISD::INTRINSIC_VOID) { 2186 unsigned NumBits = TLI.ComputeNumSignBitsForTargetNode(Op, Depth); 2187 if (NumBits > 1) FirstAnswer = std::max(FirstAnswer, NumBits); 2188 } 2189 2190 // Finally, if we can prove that the top bits of the result are 0's or 1's, 2191 // use this information. 2192 APInt KnownZero, KnownOne; 2193 APInt Mask = APInt::getAllOnesValue(VTBits); 2194 ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth); 2195 2196 if (KnownZero.isNegative()) { // sign bit is 0 2197 Mask = KnownZero; 2198 } else if (KnownOne.isNegative()) { // sign bit is 1; 2199 Mask = KnownOne; 2200 } else { 2201 // Nothing known. 2202 return FirstAnswer; 2203 } 2204 2205 // Okay, we know that the sign bit in Mask is set. Use CLZ to determine 2206 // the number of identical bits in the top of the input value. 2207 Mask = ~Mask; 2208 Mask <<= Mask.getBitWidth()-VTBits; 2209 // Return # leading zeros. We use 'min' here in case Val was zero before 2210 // shifting. We don't want to return '64' as for an i32 "0". 2211 return std::max(FirstAnswer, std::min(VTBits, Mask.countLeadingZeros())); 2212} 2213 2214bool SelectionDAG::isKnownNeverNaN(SDValue Op) const { 2215 // If we're told that NaNs won't happen, assume they won't. 2216 if (FiniteOnlyFPMath()) 2217 return true; 2218 2219 // If the value is a constant, we can obviously see if it is a NaN or not. 2220 if (const ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Op)) 2221 return !C->getValueAPF().isNaN(); 2222 2223 // TODO: Recognize more cases here. 2224 2225 return false; 2226} 2227 2228bool SelectionDAG::isVerifiedDebugInfoDesc(SDValue Op) const { 2229 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op); 2230 if (!GA) return false; 2231 if (GA->getOffset() != 0) return false; 2232 GlobalVariable *GV = dyn_cast<GlobalVariable>(GA->getGlobal()); 2233 if (!GV) return false; 2234 MachineModuleInfo *MMI = getMachineModuleInfo(); 2235 return MMI && MMI->hasDebugInfo(); 2236} 2237 2238 2239/// getShuffleScalarElt - Returns the scalar element that will make up the ith 2240/// element of the result of the vector shuffle. 2241SDValue SelectionDAG::getShuffleScalarElt(const ShuffleVectorSDNode *N, 2242 unsigned i) { 2243 EVT VT = N->getValueType(0); 2244 DebugLoc dl = N->getDebugLoc(); 2245 if (N->getMaskElt(i) < 0) 2246 return getUNDEF(VT.getVectorElementType()); 2247 unsigned Index = N->getMaskElt(i); 2248 unsigned NumElems = VT.getVectorNumElements(); 2249 SDValue V = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1); 2250 Index %= NumElems; 2251 2252 if (V.getOpcode() == ISD::BIT_CONVERT) { 2253 V = V.getOperand(0); 2254 EVT VVT = V.getValueType(); 2255 if (!VVT.isVector() || VVT.getVectorNumElements() != (unsigned)NumElems) 2256 return SDValue(); 2257 } 2258 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) 2259 return (Index == 0) ? V.getOperand(0) 2260 : getUNDEF(VT.getVectorElementType()); 2261 if (V.getOpcode() == ISD::BUILD_VECTOR) 2262 return V.getOperand(Index); 2263 if (const ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(V)) 2264 return getShuffleScalarElt(SVN, Index); 2265 return SDValue(); 2266} 2267 2268 2269/// getNode - Gets or creates the specified node. 2270/// 2271SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, EVT VT) { 2272 FoldingSetNodeID ID; 2273 AddNodeIDNode(ID, Opcode, getVTList(VT), 0, 0); 2274 void *IP = 0; 2275 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2276 return SDValue(E, 0); 2277 2278 SDNode *N = NodeAllocator.Allocate<SDNode>(); 2279 new (N) SDNode(Opcode, DL, getVTList(VT)); 2280 CSEMap.InsertNode(N, IP); 2281 2282 AllNodes.push_back(N); 2283#ifndef NDEBUG 2284 VerifyNode(N); 2285#endif 2286 return SDValue(N, 0); 2287} 2288 2289SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, 2290 EVT VT, SDValue Operand) { 2291 // Constant fold unary operations with an integer constant operand. 2292 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Operand.getNode())) { 2293 const APInt &Val = C->getAPIntValue(); 2294 unsigned BitWidth = VT.getSizeInBits(); 2295 switch (Opcode) { 2296 default: break; 2297 case ISD::SIGN_EXTEND: 2298 return getConstant(APInt(Val).sextOrTrunc(BitWidth), VT); 2299 case ISD::ANY_EXTEND: 2300 case ISD::ZERO_EXTEND: 2301 case ISD::TRUNCATE: 2302 return getConstant(APInt(Val).zextOrTrunc(BitWidth), VT); 2303 case ISD::UINT_TO_FP: 2304 case ISD::SINT_TO_FP: { 2305 const uint64_t zero[] = {0, 0}; 2306 // No compile time operations on this type. 2307 if (VT==MVT::ppcf128) 2308 break; 2309 APFloat apf = APFloat(APInt(BitWidth, 2, zero)); 2310 (void)apf.convertFromAPInt(Val, 2311 Opcode==ISD::SINT_TO_FP, 2312 APFloat::rmNearestTiesToEven); 2313 return getConstantFP(apf, VT); 2314 } 2315 case ISD::BIT_CONVERT: 2316 if (VT == MVT::f32 && C->getValueType(0) == MVT::i32) 2317 return getConstantFP(Val.bitsToFloat(), VT); 2318 else if (VT == MVT::f64 && C->getValueType(0) == MVT::i64) 2319 return getConstantFP(Val.bitsToDouble(), VT); 2320 break; 2321 case ISD::BSWAP: 2322 return getConstant(Val.byteSwap(), VT); 2323 case ISD::CTPOP: 2324 return getConstant(Val.countPopulation(), VT); 2325 case ISD::CTLZ: 2326 return getConstant(Val.countLeadingZeros(), VT); 2327 case ISD::CTTZ: 2328 return getConstant(Val.countTrailingZeros(), VT); 2329 } 2330 } 2331 2332 // Constant fold unary operations with a floating point constant operand. 2333 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Operand.getNode())) { 2334 APFloat V = C->getValueAPF(); // make copy 2335 if (VT != MVT::ppcf128 && Operand.getValueType() != MVT::ppcf128) { 2336 switch (Opcode) { 2337 case ISD::FNEG: 2338 V.changeSign(); 2339 return getConstantFP(V, VT); 2340 case ISD::FABS: 2341 V.clearSign(); 2342 return getConstantFP(V, VT); 2343 case ISD::FP_ROUND: 2344 case ISD::FP_EXTEND: { 2345 bool ignored; 2346 // This can return overflow, underflow, or inexact; we don't care. 2347 // FIXME need to be more flexible about rounding mode. 2348 (void)V.convert(*EVTToAPFloatSemantics(VT), 2349 APFloat::rmNearestTiesToEven, &ignored); 2350 return getConstantFP(V, VT); 2351 } 2352 case ISD::FP_TO_SINT: 2353 case ISD::FP_TO_UINT: { 2354 integerPart x[2]; 2355 bool ignored; 2356 assert(integerPartWidth >= 64); 2357 // FIXME need to be more flexible about rounding mode. 2358 APFloat::opStatus s = V.convertToInteger(x, VT.getSizeInBits(), 2359 Opcode==ISD::FP_TO_SINT, 2360 APFloat::rmTowardZero, &ignored); 2361 if (s==APFloat::opInvalidOp) // inexact is OK, in fact usual 2362 break; 2363 APInt api(VT.getSizeInBits(), 2, x); 2364 return getConstant(api, VT); 2365 } 2366 case ISD::BIT_CONVERT: 2367 if (VT == MVT::i32 && C->getValueType(0) == MVT::f32) 2368 return getConstant((uint32_t)V.bitcastToAPInt().getZExtValue(), VT); 2369 else if (VT == MVT::i64 && C->getValueType(0) == MVT::f64) 2370 return getConstant(V.bitcastToAPInt().getZExtValue(), VT); 2371 break; 2372 } 2373 } 2374 } 2375 2376 unsigned OpOpcode = Operand.getNode()->getOpcode(); 2377 switch (Opcode) { 2378 case ISD::TokenFactor: 2379 case ISD::MERGE_VALUES: 2380 case ISD::CONCAT_VECTORS: 2381 return Operand; // Factor, merge or concat of one node? No need. 2382 case ISD::FP_ROUND: llvm_unreachable("Invalid method to make FP_ROUND node"); 2383 case ISD::FP_EXTEND: 2384 assert(VT.isFloatingPoint() && 2385 Operand.getValueType().isFloatingPoint() && "Invalid FP cast!"); 2386 if (Operand.getValueType() == VT) return Operand; // noop conversion. 2387 assert((!VT.isVector() || 2388 VT.getVectorNumElements() == 2389 Operand.getValueType().getVectorNumElements()) && 2390 "Vector element count mismatch!"); 2391 if (Operand.getOpcode() == ISD::UNDEF) 2392 return getUNDEF(VT); 2393 break; 2394 case ISD::SIGN_EXTEND: 2395 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2396 "Invalid SIGN_EXTEND!"); 2397 if (Operand.getValueType() == VT) return Operand; // noop extension 2398 assert(Operand.getValueType().getScalarType().bitsLT(VT.getScalarType()) && 2399 "Invalid sext node, dst < src!"); 2400 assert((!VT.isVector() || 2401 VT.getVectorNumElements() == 2402 Operand.getValueType().getVectorNumElements()) && 2403 "Vector element count mismatch!"); 2404 if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND) 2405 return getNode(OpOpcode, DL, VT, Operand.getNode()->getOperand(0)); 2406 break; 2407 case ISD::ZERO_EXTEND: 2408 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2409 "Invalid ZERO_EXTEND!"); 2410 if (Operand.getValueType() == VT) return Operand; // noop extension 2411 assert(Operand.getValueType().getScalarType().bitsLT(VT.getScalarType()) && 2412 "Invalid zext node, dst < src!"); 2413 assert((!VT.isVector() || 2414 VT.getVectorNumElements() == 2415 Operand.getValueType().getVectorNumElements()) && 2416 "Vector element count mismatch!"); 2417 if (OpOpcode == ISD::ZERO_EXTEND) // (zext (zext x)) -> (zext x) 2418 return getNode(ISD::ZERO_EXTEND, DL, VT, 2419 Operand.getNode()->getOperand(0)); 2420 break; 2421 case ISD::ANY_EXTEND: 2422 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2423 "Invalid ANY_EXTEND!"); 2424 if (Operand.getValueType() == VT) return Operand; // noop extension 2425 assert(Operand.getValueType().getScalarType().bitsLT(VT.getScalarType()) && 2426 "Invalid anyext node, dst < src!"); 2427 assert((!VT.isVector() || 2428 VT.getVectorNumElements() == 2429 Operand.getValueType().getVectorNumElements()) && 2430 "Vector element count mismatch!"); 2431 if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND) 2432 // (ext (zext x)) -> (zext x) and (ext (sext x)) -> (sext x) 2433 return getNode(OpOpcode, DL, VT, Operand.getNode()->getOperand(0)); 2434 break; 2435 case ISD::TRUNCATE: 2436 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2437 "Invalid TRUNCATE!"); 2438 if (Operand.getValueType() == VT) return Operand; // noop truncate 2439 assert(Operand.getValueType().getScalarType().bitsGT(VT.getScalarType()) && 2440 "Invalid truncate node, src < dst!"); 2441 assert((!VT.isVector() || 2442 VT.getVectorNumElements() == 2443 Operand.getValueType().getVectorNumElements()) && 2444 "Vector element count mismatch!"); 2445 if (OpOpcode == ISD::TRUNCATE) 2446 return getNode(ISD::TRUNCATE, DL, VT, Operand.getNode()->getOperand(0)); 2447 else if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND || 2448 OpOpcode == ISD::ANY_EXTEND) { 2449 // If the source is smaller than the dest, we still need an extend. 2450 if (Operand.getNode()->getOperand(0).getValueType().getScalarType() 2451 .bitsLT(VT.getScalarType())) 2452 return getNode(OpOpcode, DL, VT, Operand.getNode()->getOperand(0)); 2453 else if (Operand.getNode()->getOperand(0).getValueType().bitsGT(VT)) 2454 return getNode(ISD::TRUNCATE, DL, VT, Operand.getNode()->getOperand(0)); 2455 else 2456 return Operand.getNode()->getOperand(0); 2457 } 2458 break; 2459 case ISD::BIT_CONVERT: 2460 // Basic sanity checking. 2461 assert(VT.getSizeInBits() == Operand.getValueType().getSizeInBits() 2462 && "Cannot BIT_CONVERT between types of different sizes!"); 2463 if (VT == Operand.getValueType()) return Operand; // noop conversion. 2464 if (OpOpcode == ISD::BIT_CONVERT) // bitconv(bitconv(x)) -> bitconv(x) 2465 return getNode(ISD::BIT_CONVERT, DL, VT, Operand.getOperand(0)); 2466 if (OpOpcode == ISD::UNDEF) 2467 return getUNDEF(VT); 2468 break; 2469 case ISD::SCALAR_TO_VECTOR: 2470 assert(VT.isVector() && !Operand.getValueType().isVector() && 2471 (VT.getVectorElementType() == Operand.getValueType() || 2472 (VT.getVectorElementType().isInteger() && 2473 Operand.getValueType().isInteger() && 2474 VT.getVectorElementType().bitsLE(Operand.getValueType()))) && 2475 "Illegal SCALAR_TO_VECTOR node!"); 2476 if (OpOpcode == ISD::UNDEF) 2477 return getUNDEF(VT); 2478 // scalar_to_vector(extract_vector_elt V, 0) -> V, top bits are undefined. 2479 if (OpOpcode == ISD::EXTRACT_VECTOR_ELT && 2480 isa<ConstantSDNode>(Operand.getOperand(1)) && 2481 Operand.getConstantOperandVal(1) == 0 && 2482 Operand.getOperand(0).getValueType() == VT) 2483 return Operand.getOperand(0); 2484 break; 2485 case ISD::FNEG: 2486 // -(X-Y) -> (Y-X) is unsafe because when X==Y, -0.0 != +0.0 2487 if (UnsafeFPMath && OpOpcode == ISD::FSUB) 2488 return getNode(ISD::FSUB, DL, VT, Operand.getNode()->getOperand(1), 2489 Operand.getNode()->getOperand(0)); 2490 if (OpOpcode == ISD::FNEG) // --X -> X 2491 return Operand.getNode()->getOperand(0); 2492 break; 2493 case ISD::FABS: 2494 if (OpOpcode == ISD::FNEG) // abs(-X) -> abs(X) 2495 return getNode(ISD::FABS, DL, VT, Operand.getNode()->getOperand(0)); 2496 break; 2497 } 2498 2499 SDNode *N; 2500 SDVTList VTs = getVTList(VT); 2501 if (VT != MVT::Flag) { // Don't CSE flag producing nodes 2502 FoldingSetNodeID ID; 2503 SDValue Ops[1] = { Operand }; 2504 AddNodeIDNode(ID, Opcode, VTs, Ops, 1); 2505 void *IP = 0; 2506 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2507 return SDValue(E, 0); 2508 2509 N = NodeAllocator.Allocate<UnarySDNode>(); 2510 new (N) UnarySDNode(Opcode, DL, VTs, Operand); 2511 CSEMap.InsertNode(N, IP); 2512 } else { 2513 N = NodeAllocator.Allocate<UnarySDNode>(); 2514 new (N) UnarySDNode(Opcode, DL, VTs, Operand); 2515 } 2516 2517 AllNodes.push_back(N); 2518#ifndef NDEBUG 2519 VerifyNode(N); 2520#endif 2521 return SDValue(N, 0); 2522} 2523 2524SDValue SelectionDAG::FoldConstantArithmetic(unsigned Opcode, 2525 EVT VT, 2526 ConstantSDNode *Cst1, 2527 ConstantSDNode *Cst2) { 2528 const APInt &C1 = Cst1->getAPIntValue(), &C2 = Cst2->getAPIntValue(); 2529 2530 switch (Opcode) { 2531 case ISD::ADD: return getConstant(C1 + C2, VT); 2532 case ISD::SUB: return getConstant(C1 - C2, VT); 2533 case ISD::MUL: return getConstant(C1 * C2, VT); 2534 case ISD::UDIV: 2535 if (C2.getBoolValue()) return getConstant(C1.udiv(C2), VT); 2536 break; 2537 case ISD::UREM: 2538 if (C2.getBoolValue()) return getConstant(C1.urem(C2), VT); 2539 break; 2540 case ISD::SDIV: 2541 if (C2.getBoolValue()) return getConstant(C1.sdiv(C2), VT); 2542 break; 2543 case ISD::SREM: 2544 if (C2.getBoolValue()) return getConstant(C1.srem(C2), VT); 2545 break; 2546 case ISD::AND: return getConstant(C1 & C2, VT); 2547 case ISD::OR: return getConstant(C1 | C2, VT); 2548 case ISD::XOR: return getConstant(C1 ^ C2, VT); 2549 case ISD::SHL: return getConstant(C1 << C2, VT); 2550 case ISD::SRL: return getConstant(C1.lshr(C2), VT); 2551 case ISD::SRA: return getConstant(C1.ashr(C2), VT); 2552 case ISD::ROTL: return getConstant(C1.rotl(C2), VT); 2553 case ISD::ROTR: return getConstant(C1.rotr(C2), VT); 2554 default: break; 2555 } 2556 2557 return SDValue(); 2558} 2559 2560SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, EVT VT, 2561 SDValue N1, SDValue N2) { 2562 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 2563 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 2564 switch (Opcode) { 2565 default: break; 2566 case ISD::TokenFactor: 2567 assert(VT == MVT::Other && N1.getValueType() == MVT::Other && 2568 N2.getValueType() == MVT::Other && "Invalid token factor!"); 2569 // Fold trivial token factors. 2570 if (N1.getOpcode() == ISD::EntryToken) return N2; 2571 if (N2.getOpcode() == ISD::EntryToken) return N1; 2572 if (N1 == N2) return N1; 2573 break; 2574 case ISD::CONCAT_VECTORS: 2575 // A CONCAT_VECTOR with all operands BUILD_VECTOR can be simplified to 2576 // one big BUILD_VECTOR. 2577 if (N1.getOpcode() == ISD::BUILD_VECTOR && 2578 N2.getOpcode() == ISD::BUILD_VECTOR) { 2579 SmallVector<SDValue, 16> Elts(N1.getNode()->op_begin(), N1.getNode()->op_end()); 2580 Elts.insert(Elts.end(), N2.getNode()->op_begin(), N2.getNode()->op_end()); 2581 return getNode(ISD::BUILD_VECTOR, DL, VT, &Elts[0], Elts.size()); 2582 } 2583 break; 2584 case ISD::AND: 2585 assert(VT.isInteger() && N1.getValueType() == N2.getValueType() && 2586 N1.getValueType() == VT && "Binary operator types must match!"); 2587 // (X & 0) -> 0. This commonly occurs when legalizing i64 values, so it's 2588 // worth handling here. 2589 if (N2C && N2C->isNullValue()) 2590 return N2; 2591 if (N2C && N2C->isAllOnesValue()) // X & -1 -> X 2592 return N1; 2593 break; 2594 case ISD::OR: 2595 case ISD::XOR: 2596 case ISD::ADD: 2597 case ISD::SUB: 2598 assert(VT.isInteger() && N1.getValueType() == N2.getValueType() && 2599 N1.getValueType() == VT && "Binary operator types must match!"); 2600 // (X ^|+- 0) -> X. This commonly occurs when legalizing i64 values, so 2601 // it's worth handling here. 2602 if (N2C && N2C->isNullValue()) 2603 return N1; 2604 break; 2605 case ISD::UDIV: 2606 case ISD::UREM: 2607 case ISD::MULHU: 2608 case ISD::MULHS: 2609 case ISD::MUL: 2610 case ISD::SDIV: 2611 case ISD::SREM: 2612 assert(VT.isInteger() && "This operator does not apply to FP types!"); 2613 // fall through 2614 case ISD::FADD: 2615 case ISD::FSUB: 2616 case ISD::FMUL: 2617 case ISD::FDIV: 2618 case ISD::FREM: 2619 if (UnsafeFPMath) { 2620 if (Opcode == ISD::FADD) { 2621 // 0+x --> x 2622 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) 2623 if (CFP->getValueAPF().isZero()) 2624 return N2; 2625 // x+0 --> x 2626 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N2)) 2627 if (CFP->getValueAPF().isZero()) 2628 return N1; 2629 } else if (Opcode == ISD::FSUB) { 2630 // x-0 --> x 2631 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N2)) 2632 if (CFP->getValueAPF().isZero()) 2633 return N1; 2634 } 2635 } 2636 assert(N1.getValueType() == N2.getValueType() && 2637 N1.getValueType() == VT && "Binary operator types must match!"); 2638 break; 2639 case ISD::FCOPYSIGN: // N1 and result must match. N1/N2 need not match. 2640 assert(N1.getValueType() == VT && 2641 N1.getValueType().isFloatingPoint() && 2642 N2.getValueType().isFloatingPoint() && 2643 "Invalid FCOPYSIGN!"); 2644 break; 2645 case ISD::SHL: 2646 case ISD::SRA: 2647 case ISD::SRL: 2648 case ISD::ROTL: 2649 case ISD::ROTR: 2650 assert(VT == N1.getValueType() && 2651 "Shift operators return type must be the same as their first arg"); 2652 assert(VT.isInteger() && N2.getValueType().isInteger() && 2653 "Shifts only work on integers"); 2654 2655 // Always fold shifts of i1 values so the code generator doesn't need to 2656 // handle them. Since we know the size of the shift has to be less than the 2657 // size of the value, the shift/rotate count is guaranteed to be zero. 2658 if (VT == MVT::i1) 2659 return N1; 2660 if (N2C && N2C->isNullValue()) 2661 return N1; 2662 break; 2663 case ISD::FP_ROUND_INREG: { 2664 EVT EVT = cast<VTSDNode>(N2)->getVT(); 2665 assert(VT == N1.getValueType() && "Not an inreg round!"); 2666 assert(VT.isFloatingPoint() && EVT.isFloatingPoint() && 2667 "Cannot FP_ROUND_INREG integer types"); 2668 assert(EVT.isVector() == VT.isVector() && 2669 "FP_ROUND_INREG type should be vector iff the operand " 2670 "type is vector!"); 2671 assert((!EVT.isVector() || 2672 EVT.getVectorNumElements() == VT.getVectorNumElements()) && 2673 "Vector element counts must match in FP_ROUND_INREG"); 2674 assert(EVT.bitsLE(VT) && "Not rounding down!"); 2675 if (cast<VTSDNode>(N2)->getVT() == VT) return N1; // Not actually rounding. 2676 break; 2677 } 2678 case ISD::FP_ROUND: 2679 assert(VT.isFloatingPoint() && 2680 N1.getValueType().isFloatingPoint() && 2681 VT.bitsLE(N1.getValueType()) && 2682 isa<ConstantSDNode>(N2) && "Invalid FP_ROUND!"); 2683 if (N1.getValueType() == VT) return N1; // noop conversion. 2684 break; 2685 case ISD::AssertSext: 2686 case ISD::AssertZext: { 2687 EVT EVT = cast<VTSDNode>(N2)->getVT(); 2688 assert(VT == N1.getValueType() && "Not an inreg extend!"); 2689 assert(VT.isInteger() && EVT.isInteger() && 2690 "Cannot *_EXTEND_INREG FP types"); 2691 assert(!EVT.isVector() && 2692 "AssertSExt/AssertZExt type should be the vector element type " 2693 "rather than the vector type!"); 2694 assert(EVT.bitsLE(VT) && "Not extending!"); 2695 if (VT == EVT) return N1; // noop assertion. 2696 break; 2697 } 2698 case ISD::SIGN_EXTEND_INREG: { 2699 EVT EVT = cast<VTSDNode>(N2)->getVT(); 2700 assert(VT == N1.getValueType() && "Not an inreg extend!"); 2701 assert(VT.isInteger() && EVT.isInteger() && 2702 "Cannot *_EXTEND_INREG FP types"); 2703 assert(EVT.isVector() == VT.isVector() && 2704 "SIGN_EXTEND_INREG type should be vector iff the operand " 2705 "type is vector!"); 2706 assert((!EVT.isVector() || 2707 EVT.getVectorNumElements() == VT.getVectorNumElements()) && 2708 "Vector element counts must match in SIGN_EXTEND_INREG"); 2709 assert(EVT.bitsLE(VT) && "Not extending!"); 2710 if (EVT == VT) return N1; // Not actually extending 2711 2712 if (N1C) { 2713 APInt Val = N1C->getAPIntValue(); 2714 unsigned FromBits = EVT.getScalarType().getSizeInBits(); 2715 Val <<= Val.getBitWidth()-FromBits; 2716 Val = Val.ashr(Val.getBitWidth()-FromBits); 2717 return getConstant(Val, VT); 2718 } 2719 break; 2720 } 2721 case ISD::EXTRACT_VECTOR_ELT: 2722 // EXTRACT_VECTOR_ELT of an UNDEF is an UNDEF. 2723 if (N1.getOpcode() == ISD::UNDEF) 2724 return getUNDEF(VT); 2725 2726 // EXTRACT_VECTOR_ELT of CONCAT_VECTORS is often formed while lowering is 2727 // expanding copies of large vectors from registers. 2728 if (N2C && 2729 N1.getOpcode() == ISD::CONCAT_VECTORS && 2730 N1.getNumOperands() > 0) { 2731 unsigned Factor = 2732 N1.getOperand(0).getValueType().getVectorNumElements(); 2733 return getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, 2734 N1.getOperand(N2C->getZExtValue() / Factor), 2735 getConstant(N2C->getZExtValue() % Factor, 2736 N2.getValueType())); 2737 } 2738 2739 // EXTRACT_VECTOR_ELT of BUILD_VECTOR is often formed while lowering is 2740 // expanding large vector constants. 2741 if (N2C && N1.getOpcode() == ISD::BUILD_VECTOR) { 2742 SDValue Elt = N1.getOperand(N2C->getZExtValue()); 2743 EVT VEltTy = N1.getValueType().getVectorElementType(); 2744 if (Elt.getValueType() != VEltTy) { 2745 // If the vector element type is not legal, the BUILD_VECTOR operands 2746 // are promoted and implicitly truncated. Make that explicit here. 2747 Elt = getNode(ISD::TRUNCATE, DL, VEltTy, Elt); 2748 } 2749 if (VT != VEltTy) { 2750 // If the vector element type is not legal, the EXTRACT_VECTOR_ELT 2751 // result is implicitly extended. 2752 Elt = getNode(ISD::ANY_EXTEND, DL, VT, Elt); 2753 } 2754 return Elt; 2755 } 2756 2757 // EXTRACT_VECTOR_ELT of INSERT_VECTOR_ELT is often formed when vector 2758 // operations are lowered to scalars. 2759 if (N1.getOpcode() == ISD::INSERT_VECTOR_ELT) { 2760 // If the indices are the same, return the inserted element. 2761 if (N1.getOperand(2) == N2) 2762 return N1.getOperand(1); 2763 // If the indices are known different, extract the element from 2764 // the original vector. 2765 else if (isa<ConstantSDNode>(N1.getOperand(2)) && 2766 isa<ConstantSDNode>(N2)) 2767 return getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, N1.getOperand(0), N2); 2768 } 2769 break; 2770 case ISD::EXTRACT_ELEMENT: 2771 assert(N2C && (unsigned)N2C->getZExtValue() < 2 && "Bad EXTRACT_ELEMENT!"); 2772 assert(!N1.getValueType().isVector() && !VT.isVector() && 2773 (N1.getValueType().isInteger() == VT.isInteger()) && 2774 "Wrong types for EXTRACT_ELEMENT!"); 2775 2776 // EXTRACT_ELEMENT of BUILD_PAIR is often formed while legalize is expanding 2777 // 64-bit integers into 32-bit parts. Instead of building the extract of 2778 // the BUILD_PAIR, only to have legalize rip it apart, just do it now. 2779 if (N1.getOpcode() == ISD::BUILD_PAIR) 2780 return N1.getOperand(N2C->getZExtValue()); 2781 2782 // EXTRACT_ELEMENT of a constant int is also very common. 2783 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) { 2784 unsigned ElementSize = VT.getSizeInBits(); 2785 unsigned Shift = ElementSize * N2C->getZExtValue(); 2786 APInt ShiftedVal = C->getAPIntValue().lshr(Shift); 2787 return getConstant(ShiftedVal.trunc(ElementSize), VT); 2788 } 2789 break; 2790 case ISD::EXTRACT_SUBVECTOR: 2791 if (N1.getValueType() == VT) // Trivial extraction. 2792 return N1; 2793 break; 2794 } 2795 2796 if (N1C) { 2797 if (N2C) { 2798 SDValue SV = FoldConstantArithmetic(Opcode, VT, N1C, N2C); 2799 if (SV.getNode()) return SV; 2800 } else { // Cannonicalize constant to RHS if commutative 2801 if (isCommutativeBinOp(Opcode)) { 2802 std::swap(N1C, N2C); 2803 std::swap(N1, N2); 2804 } 2805 } 2806 } 2807 2808 // Constant fold FP operations. 2809 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1.getNode()); 2810 ConstantFPSDNode *N2CFP = dyn_cast<ConstantFPSDNode>(N2.getNode()); 2811 if (N1CFP) { 2812 if (!N2CFP && isCommutativeBinOp(Opcode)) { 2813 // Cannonicalize constant to RHS if commutative 2814 std::swap(N1CFP, N2CFP); 2815 std::swap(N1, N2); 2816 } else if (N2CFP && VT != MVT::ppcf128) { 2817 APFloat V1 = N1CFP->getValueAPF(), V2 = N2CFP->getValueAPF(); 2818 APFloat::opStatus s; 2819 switch (Opcode) { 2820 case ISD::FADD: 2821 s = V1.add(V2, APFloat::rmNearestTiesToEven); 2822 if (s != APFloat::opInvalidOp) 2823 return getConstantFP(V1, VT); 2824 break; 2825 case ISD::FSUB: 2826 s = V1.subtract(V2, APFloat::rmNearestTiesToEven); 2827 if (s!=APFloat::opInvalidOp) 2828 return getConstantFP(V1, VT); 2829 break; 2830 case ISD::FMUL: 2831 s = V1.multiply(V2, APFloat::rmNearestTiesToEven); 2832 if (s!=APFloat::opInvalidOp) 2833 return getConstantFP(V1, VT); 2834 break; 2835 case ISD::FDIV: 2836 s = V1.divide(V2, APFloat::rmNearestTiesToEven); 2837 if (s!=APFloat::opInvalidOp && s!=APFloat::opDivByZero) 2838 return getConstantFP(V1, VT); 2839 break; 2840 case ISD::FREM : 2841 s = V1.mod(V2, APFloat::rmNearestTiesToEven); 2842 if (s!=APFloat::opInvalidOp && s!=APFloat::opDivByZero) 2843 return getConstantFP(V1, VT); 2844 break; 2845 case ISD::FCOPYSIGN: 2846 V1.copySign(V2); 2847 return getConstantFP(V1, VT); 2848 default: break; 2849 } 2850 } 2851 } 2852 2853 // Canonicalize an UNDEF to the RHS, even over a constant. 2854 if (N1.getOpcode() == ISD::UNDEF) { 2855 if (isCommutativeBinOp(Opcode)) { 2856 std::swap(N1, N2); 2857 } else { 2858 switch (Opcode) { 2859 case ISD::FP_ROUND_INREG: 2860 case ISD::SIGN_EXTEND_INREG: 2861 case ISD::SUB: 2862 case ISD::FSUB: 2863 case ISD::FDIV: 2864 case ISD::FREM: 2865 case ISD::SRA: 2866 return N1; // fold op(undef, arg2) -> undef 2867 case ISD::UDIV: 2868 case ISD::SDIV: 2869 case ISD::UREM: 2870 case ISD::SREM: 2871 case ISD::SRL: 2872 case ISD::SHL: 2873 if (!VT.isVector()) 2874 return getConstant(0, VT); // fold op(undef, arg2) -> 0 2875 // For vectors, we can't easily build an all zero vector, just return 2876 // the LHS. 2877 return N2; 2878 } 2879 } 2880 } 2881 2882 // Fold a bunch of operators when the RHS is undef. 2883 if (N2.getOpcode() == ISD::UNDEF) { 2884 switch (Opcode) { 2885 case ISD::XOR: 2886 if (N1.getOpcode() == ISD::UNDEF) 2887 // Handle undef ^ undef -> 0 special case. This is a common 2888 // idiom (misuse). 2889 return getConstant(0, VT); 2890 // fallthrough 2891 case ISD::ADD: 2892 case ISD::ADDC: 2893 case ISD::ADDE: 2894 case ISD::SUB: 2895 case ISD::UDIV: 2896 case ISD::SDIV: 2897 case ISD::UREM: 2898 case ISD::SREM: 2899 return N2; // fold op(arg1, undef) -> undef 2900 case ISD::FADD: 2901 case ISD::FSUB: 2902 case ISD::FMUL: 2903 case ISD::FDIV: 2904 case ISD::FREM: 2905 if (UnsafeFPMath) 2906 return N2; 2907 break; 2908 case ISD::MUL: 2909 case ISD::AND: 2910 case ISD::SRL: 2911 case ISD::SHL: 2912 if (!VT.isVector()) 2913 return getConstant(0, VT); // fold op(arg1, undef) -> 0 2914 // For vectors, we can't easily build an all zero vector, just return 2915 // the LHS. 2916 return N1; 2917 case ISD::OR: 2918 if (!VT.isVector()) 2919 return getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT); 2920 // For vectors, we can't easily build an all one vector, just return 2921 // the LHS. 2922 return N1; 2923 case ISD::SRA: 2924 return N1; 2925 } 2926 } 2927 2928 // Memoize this node if possible. 2929 SDNode *N; 2930 SDVTList VTs = getVTList(VT); 2931 if (VT != MVT::Flag) { 2932 SDValue Ops[] = { N1, N2 }; 2933 FoldingSetNodeID ID; 2934 AddNodeIDNode(ID, Opcode, VTs, Ops, 2); 2935 void *IP = 0; 2936 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2937 return SDValue(E, 0); 2938 2939 N = NodeAllocator.Allocate<BinarySDNode>(); 2940 new (N) BinarySDNode(Opcode, DL, VTs, N1, N2); 2941 CSEMap.InsertNode(N, IP); 2942 } else { 2943 N = NodeAllocator.Allocate<BinarySDNode>(); 2944 new (N) BinarySDNode(Opcode, DL, VTs, N1, N2); 2945 } 2946 2947 AllNodes.push_back(N); 2948#ifndef NDEBUG 2949 VerifyNode(N); 2950#endif 2951 return SDValue(N, 0); 2952} 2953 2954SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, EVT VT, 2955 SDValue N1, SDValue N2, SDValue N3) { 2956 // Perform various simplifications. 2957 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 2958 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 2959 switch (Opcode) { 2960 case ISD::CONCAT_VECTORS: 2961 // A CONCAT_VECTOR with all operands BUILD_VECTOR can be simplified to 2962 // one big BUILD_VECTOR. 2963 if (N1.getOpcode() == ISD::BUILD_VECTOR && 2964 N2.getOpcode() == ISD::BUILD_VECTOR && 2965 N3.getOpcode() == ISD::BUILD_VECTOR) { 2966 SmallVector<SDValue, 16> Elts(N1.getNode()->op_begin(), N1.getNode()->op_end()); 2967 Elts.insert(Elts.end(), N2.getNode()->op_begin(), N2.getNode()->op_end()); 2968 Elts.insert(Elts.end(), N3.getNode()->op_begin(), N3.getNode()->op_end()); 2969 return getNode(ISD::BUILD_VECTOR, DL, VT, &Elts[0], Elts.size()); 2970 } 2971 break; 2972 case ISD::SETCC: { 2973 // Use FoldSetCC to simplify SETCC's. 2974 SDValue Simp = FoldSetCC(VT, N1, N2, cast<CondCodeSDNode>(N3)->get(), DL); 2975 if (Simp.getNode()) return Simp; 2976 break; 2977 } 2978 case ISD::SELECT: 2979 if (N1C) { 2980 if (N1C->getZExtValue()) 2981 return N2; // select true, X, Y -> X 2982 else 2983 return N3; // select false, X, Y -> Y 2984 } 2985 2986 if (N2 == N3) return N2; // select C, X, X -> X 2987 break; 2988 case ISD::BRCOND: 2989 if (N2C) { 2990 if (N2C->getZExtValue()) // Unconditional branch 2991 return getNode(ISD::BR, DL, MVT::Other, N1, N3); 2992 else 2993 return N1; // Never-taken branch 2994 } 2995 break; 2996 case ISD::VECTOR_SHUFFLE: 2997 llvm_unreachable("should use getVectorShuffle constructor!"); 2998 break; 2999 case ISD::BIT_CONVERT: 3000 // Fold bit_convert nodes from a type to themselves. 3001 if (N1.getValueType() == VT) 3002 return N1; 3003 break; 3004 } 3005 3006 // Memoize node if it doesn't produce a flag. 3007 SDNode *N; 3008 SDVTList VTs = getVTList(VT); 3009 if (VT != MVT::Flag) { 3010 SDValue Ops[] = { N1, N2, N3 }; 3011 FoldingSetNodeID ID; 3012 AddNodeIDNode(ID, Opcode, VTs, Ops, 3); 3013 void *IP = 0; 3014 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3015 return SDValue(E, 0); 3016 3017 N = NodeAllocator.Allocate<TernarySDNode>(); 3018 new (N) TernarySDNode(Opcode, DL, VTs, N1, N2, N3); 3019 CSEMap.InsertNode(N, IP); 3020 } else { 3021 N = NodeAllocator.Allocate<TernarySDNode>(); 3022 new (N) TernarySDNode(Opcode, DL, VTs, N1, N2, N3); 3023 } 3024 3025 AllNodes.push_back(N); 3026#ifndef NDEBUG 3027 VerifyNode(N); 3028#endif 3029 return SDValue(N, 0); 3030} 3031 3032SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, EVT VT, 3033 SDValue N1, SDValue N2, SDValue N3, 3034 SDValue N4) { 3035 SDValue Ops[] = { N1, N2, N3, N4 }; 3036 return getNode(Opcode, DL, VT, Ops, 4); 3037} 3038 3039SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, EVT VT, 3040 SDValue N1, SDValue N2, SDValue N3, 3041 SDValue N4, SDValue N5) { 3042 SDValue Ops[] = { N1, N2, N3, N4, N5 }; 3043 return getNode(Opcode, DL, VT, Ops, 5); 3044} 3045 3046/// getStackArgumentTokenFactor - Compute a TokenFactor to force all 3047/// the incoming stack arguments to be loaded from the stack. 3048SDValue SelectionDAG::getStackArgumentTokenFactor(SDValue Chain) { 3049 SmallVector<SDValue, 8> ArgChains; 3050 3051 // Include the original chain at the beginning of the list. When this is 3052 // used by target LowerCall hooks, this helps legalize find the 3053 // CALLSEQ_BEGIN node. 3054 ArgChains.push_back(Chain); 3055 3056 // Add a chain value for each stack argument. 3057 for (SDNode::use_iterator U = getEntryNode().getNode()->use_begin(), 3058 UE = getEntryNode().getNode()->use_end(); U != UE; ++U) 3059 if (LoadSDNode *L = dyn_cast<LoadSDNode>(*U)) 3060 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(L->getBasePtr())) 3061 if (FI->getIndex() < 0) 3062 ArgChains.push_back(SDValue(L, 1)); 3063 3064 // Build a tokenfactor for all the chains. 3065 return getNode(ISD::TokenFactor, Chain.getDebugLoc(), MVT::Other, 3066 &ArgChains[0], ArgChains.size()); 3067} 3068 3069/// getMemsetValue - Vectorized representation of the memset value 3070/// operand. 3071static SDValue getMemsetValue(SDValue Value, EVT VT, SelectionDAG &DAG, 3072 DebugLoc dl) { 3073 unsigned NumBits = VT.isVector() ? 3074 VT.getVectorElementType().getSizeInBits() : VT.getSizeInBits(); 3075 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) { 3076 APInt Val = APInt(NumBits, C->getZExtValue() & 255); 3077 unsigned Shift = 8; 3078 for (unsigned i = NumBits; i > 8; i >>= 1) { 3079 Val = (Val << Shift) | Val; 3080 Shift <<= 1; 3081 } 3082 if (VT.isInteger()) 3083 return DAG.getConstant(Val, VT); 3084 return DAG.getConstantFP(APFloat(Val), VT); 3085 } 3086 3087 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 3088 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Value); 3089 unsigned Shift = 8; 3090 for (unsigned i = NumBits; i > 8; i >>= 1) { 3091 Value = DAG.getNode(ISD::OR, dl, VT, 3092 DAG.getNode(ISD::SHL, dl, VT, Value, 3093 DAG.getConstant(Shift, 3094 TLI.getShiftAmountTy())), 3095 Value); 3096 Shift <<= 1; 3097 } 3098 3099 return Value; 3100} 3101 3102/// getMemsetStringVal - Similar to getMemsetValue. Except this is only 3103/// used when a memcpy is turned into a memset when the source is a constant 3104/// string ptr. 3105static SDValue getMemsetStringVal(EVT VT, DebugLoc dl, SelectionDAG &DAG, 3106 const TargetLowering &TLI, 3107 std::string &Str, unsigned Offset) { 3108 // Handle vector with all elements zero. 3109 if (Str.empty()) { 3110 if (VT.isInteger()) 3111 return DAG.getConstant(0, VT); 3112 unsigned NumElts = VT.getVectorNumElements(); 3113 MVT EltVT = (VT.getVectorElementType() == MVT::f32) ? MVT::i32 : MVT::i64; 3114 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 3115 DAG.getConstant(0, 3116 EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts))); 3117 } 3118 3119 assert(!VT.isVector() && "Can't handle vector type here!"); 3120 unsigned NumBits = VT.getSizeInBits(); 3121 unsigned MSB = NumBits / 8; 3122 uint64_t Val = 0; 3123 if (TLI.isLittleEndian()) 3124 Offset = Offset + MSB - 1; 3125 for (unsigned i = 0; i != MSB; ++i) { 3126 Val = (Val << 8) | (unsigned char)Str[Offset]; 3127 Offset += TLI.isLittleEndian() ? -1 : 1; 3128 } 3129 return DAG.getConstant(Val, VT); 3130} 3131 3132/// getMemBasePlusOffset - Returns base and offset node for the 3133/// 3134static SDValue getMemBasePlusOffset(SDValue Base, unsigned Offset, 3135 SelectionDAG &DAG) { 3136 EVT VT = Base.getValueType(); 3137 return DAG.getNode(ISD::ADD, Base.getDebugLoc(), 3138 VT, Base, DAG.getConstant(Offset, VT)); 3139} 3140 3141/// isMemSrcFromString - Returns true if memcpy source is a string constant. 3142/// 3143static bool isMemSrcFromString(SDValue Src, std::string &Str) { 3144 unsigned SrcDelta = 0; 3145 GlobalAddressSDNode *G = NULL; 3146 if (Src.getOpcode() == ISD::GlobalAddress) 3147 G = cast<GlobalAddressSDNode>(Src); 3148 else if (Src.getOpcode() == ISD::ADD && 3149 Src.getOperand(0).getOpcode() == ISD::GlobalAddress && 3150 Src.getOperand(1).getOpcode() == ISD::Constant) { 3151 G = cast<GlobalAddressSDNode>(Src.getOperand(0)); 3152 SrcDelta = cast<ConstantSDNode>(Src.getOperand(1))->getZExtValue(); 3153 } 3154 if (!G) 3155 return false; 3156 3157 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal()); 3158 if (GV && GetConstantStringInfo(GV, Str, SrcDelta, false)) 3159 return true; 3160 3161 return false; 3162} 3163 3164/// MeetsMaxMemopRequirement - Determines if the number of memory ops required 3165/// to replace the memset / memcpy is below the threshold. It also returns the 3166/// types of the sequence of memory ops to perform memset / memcpy. 3167static 3168bool MeetsMaxMemopRequirement(std::vector<EVT> &MemOps, 3169 SDValue Dst, SDValue Src, 3170 unsigned Limit, uint64_t Size, unsigned &Align, 3171 std::string &Str, bool &isSrcStr, 3172 SelectionDAG &DAG, 3173 const TargetLowering &TLI) { 3174 isSrcStr = isMemSrcFromString(Src, Str); 3175 bool isSrcConst = isa<ConstantSDNode>(Src); 3176 EVT VT = TLI.getOptimalMemOpType(Size, Align, isSrcConst, isSrcStr, DAG); 3177 bool AllowUnalign = TLI.allowsUnalignedMemoryAccesses(VT); 3178 if (VT != MVT::iAny) { 3179 const Type *Ty = VT.getTypeForEVT(*DAG.getContext()); 3180 unsigned NewAlign = (unsigned) TLI.getTargetData()->getABITypeAlignment(Ty); 3181 // If source is a string constant, this will require an unaligned load. 3182 if (NewAlign > Align && (isSrcConst || AllowUnalign)) { 3183 if (Dst.getOpcode() != ISD::FrameIndex) { 3184 // Can't change destination alignment. It requires a unaligned store. 3185 if (AllowUnalign) 3186 VT = MVT::iAny; 3187 } else { 3188 int FI = cast<FrameIndexSDNode>(Dst)->getIndex(); 3189 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 3190 if (MFI->isFixedObjectIndex(FI)) { 3191 // Can't change destination alignment. It requires a unaligned store. 3192 if (AllowUnalign) 3193 VT = MVT::iAny; 3194 } else { 3195 // Give the stack frame object a larger alignment if needed. 3196 if (MFI->getObjectAlignment(FI) < NewAlign) 3197 MFI->setObjectAlignment(FI, NewAlign); 3198 Align = NewAlign; 3199 } 3200 } 3201 } 3202 } 3203 3204 if (VT == MVT::iAny) { 3205 if (TLI.allowsUnalignedMemoryAccesses(MVT::i64)) { 3206 VT = MVT::i64; 3207 } else { 3208 switch (Align & 7) { 3209 case 0: VT = MVT::i64; break; 3210 case 4: VT = MVT::i32; break; 3211 case 2: VT = MVT::i16; break; 3212 default: VT = MVT::i8; break; 3213 } 3214 } 3215 3216 MVT LVT = MVT::i64; 3217 while (!TLI.isTypeLegal(LVT)) 3218 LVT = (MVT::SimpleValueType)(LVT.SimpleTy - 1); 3219 assert(LVT.isInteger()); 3220 3221 if (VT.bitsGT(LVT)) 3222 VT = LVT; 3223 } 3224 3225 unsigned NumMemOps = 0; 3226 while (Size != 0) { 3227 unsigned VTSize = VT.getSizeInBits() / 8; 3228 while (VTSize > Size) { 3229 // For now, only use non-vector load / store's for the left-over pieces. 3230 if (VT.isVector()) { 3231 VT = MVT::i64; 3232 while (!TLI.isTypeLegal(VT)) 3233 VT = (MVT::SimpleValueType)(VT.getSimpleVT().SimpleTy - 1); 3234 VTSize = VT.getSizeInBits() / 8; 3235 } else { 3236 // This can result in a type that is not legal on the target, e.g. 3237 // 1 or 2 bytes on PPC. 3238 VT = (MVT::SimpleValueType)(VT.getSimpleVT().SimpleTy - 1); 3239 VTSize >>= 1; 3240 } 3241 } 3242 3243 if (++NumMemOps > Limit) 3244 return false; 3245 MemOps.push_back(VT); 3246 Size -= VTSize; 3247 } 3248 3249 return true; 3250} 3251 3252static SDValue getMemcpyLoadsAndStores(SelectionDAG &DAG, DebugLoc dl, 3253 SDValue Chain, SDValue Dst, 3254 SDValue Src, uint64_t Size, 3255 unsigned Align, bool AlwaysInline, 3256 const Value *DstSV, uint64_t DstSVOff, 3257 const Value *SrcSV, uint64_t SrcSVOff){ 3258 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 3259 3260 // Expand memcpy to a series of load and store ops if the size operand falls 3261 // below a certain threshold. 3262 std::vector<EVT> MemOps; 3263 uint64_t Limit = -1ULL; 3264 if (!AlwaysInline) 3265 Limit = TLI.getMaxStoresPerMemcpy(); 3266 unsigned DstAlign = Align; // Destination alignment can change. 3267 std::string Str; 3268 bool CopyFromStr; 3269 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, Limit, Size, DstAlign, 3270 Str, CopyFromStr, DAG, TLI)) 3271 return SDValue(); 3272 3273 3274 bool isZeroStr = CopyFromStr && Str.empty(); 3275 SmallVector<SDValue, 8> OutChains; 3276 unsigned NumMemOps = MemOps.size(); 3277 uint64_t SrcOff = 0, DstOff = 0; 3278 for (unsigned i = 0; i != NumMemOps; ++i) { 3279 EVT VT = MemOps[i]; 3280 unsigned VTSize = VT.getSizeInBits() / 8; 3281 SDValue Value, Store; 3282 3283 if (CopyFromStr && (isZeroStr || !VT.isVector())) { 3284 // It's unlikely a store of a vector immediate can be done in a single 3285 // instruction. It would require a load from a constantpool first. 3286 // We also handle store a vector with all zero's. 3287 // FIXME: Handle other cases where store of vector immediate is done in 3288 // a single instruction. 3289 Value = getMemsetStringVal(VT, dl, DAG, TLI, Str, SrcOff); 3290 Store = DAG.getStore(Chain, dl, Value, 3291 getMemBasePlusOffset(Dst, DstOff, DAG), 3292 DstSV, DstSVOff + DstOff, false, DstAlign); 3293 } else { 3294 // The type might not be legal for the target. This should only happen 3295 // if the type is smaller than a legal type, as on PPC, so the right 3296 // thing to do is generate a LoadExt/StoreTrunc pair. These simplify 3297 // to Load/Store if NVT==VT. 3298 // FIXME does the case above also need this? 3299 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); 3300 assert(NVT.bitsGE(VT)); 3301 Value = DAG.getExtLoad(ISD::EXTLOAD, dl, NVT, Chain, 3302 getMemBasePlusOffset(Src, SrcOff, DAG), 3303 SrcSV, SrcSVOff + SrcOff, VT, false, Align); 3304 Store = DAG.getTruncStore(Chain, dl, Value, 3305 getMemBasePlusOffset(Dst, DstOff, DAG), 3306 DstSV, DstSVOff + DstOff, VT, false, DstAlign); 3307 } 3308 OutChains.push_back(Store); 3309 SrcOff += VTSize; 3310 DstOff += VTSize; 3311 } 3312 3313 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3314 &OutChains[0], OutChains.size()); 3315} 3316 3317static SDValue getMemmoveLoadsAndStores(SelectionDAG &DAG, DebugLoc dl, 3318 SDValue Chain, SDValue Dst, 3319 SDValue Src, uint64_t Size, 3320 unsigned Align, bool AlwaysInline, 3321 const Value *DstSV, uint64_t DstSVOff, 3322 const Value *SrcSV, uint64_t SrcSVOff){ 3323 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 3324 3325 // Expand memmove to a series of load and store ops if the size operand falls 3326 // below a certain threshold. 3327 std::vector<EVT> MemOps; 3328 uint64_t Limit = -1ULL; 3329 if (!AlwaysInline) 3330 Limit = TLI.getMaxStoresPerMemmove(); 3331 unsigned DstAlign = Align; // Destination alignment can change. 3332 std::string Str; 3333 bool CopyFromStr; 3334 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, Limit, Size, DstAlign, 3335 Str, CopyFromStr, DAG, TLI)) 3336 return SDValue(); 3337 3338 uint64_t SrcOff = 0, DstOff = 0; 3339 3340 SmallVector<SDValue, 8> LoadValues; 3341 SmallVector<SDValue, 8> LoadChains; 3342 SmallVector<SDValue, 8> OutChains; 3343 unsigned NumMemOps = MemOps.size(); 3344 for (unsigned i = 0; i < NumMemOps; i++) { 3345 EVT VT = MemOps[i]; 3346 unsigned VTSize = VT.getSizeInBits() / 8; 3347 SDValue Value, Store; 3348 3349 Value = DAG.getLoad(VT, dl, Chain, 3350 getMemBasePlusOffset(Src, SrcOff, DAG), 3351 SrcSV, SrcSVOff + SrcOff, false, Align); 3352 LoadValues.push_back(Value); 3353 LoadChains.push_back(Value.getValue(1)); 3354 SrcOff += VTSize; 3355 } 3356 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3357 &LoadChains[0], LoadChains.size()); 3358 OutChains.clear(); 3359 for (unsigned i = 0; i < NumMemOps; i++) { 3360 EVT VT = MemOps[i]; 3361 unsigned VTSize = VT.getSizeInBits() / 8; 3362 SDValue Value, Store; 3363 3364 Store = DAG.getStore(Chain, dl, LoadValues[i], 3365 getMemBasePlusOffset(Dst, DstOff, DAG), 3366 DstSV, DstSVOff + DstOff, false, DstAlign); 3367 OutChains.push_back(Store); 3368 DstOff += VTSize; 3369 } 3370 3371 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3372 &OutChains[0], OutChains.size()); 3373} 3374 3375static SDValue getMemsetStores(SelectionDAG &DAG, DebugLoc dl, 3376 SDValue Chain, SDValue Dst, 3377 SDValue Src, uint64_t Size, 3378 unsigned Align, 3379 const Value *DstSV, uint64_t DstSVOff) { 3380 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 3381 3382 // Expand memset to a series of load/store ops if the size operand 3383 // falls below a certain threshold. 3384 std::vector<EVT> MemOps; 3385 std::string Str; 3386 bool CopyFromStr; 3387 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, TLI.getMaxStoresPerMemset(), 3388 Size, Align, Str, CopyFromStr, DAG, TLI)) 3389 return SDValue(); 3390 3391 SmallVector<SDValue, 8> OutChains; 3392 uint64_t DstOff = 0; 3393 3394 unsigned NumMemOps = MemOps.size(); 3395 for (unsigned i = 0; i < NumMemOps; i++) { 3396 EVT VT = MemOps[i]; 3397 unsigned VTSize = VT.getSizeInBits() / 8; 3398 SDValue Value = getMemsetValue(Src, VT, DAG, dl); 3399 SDValue Store = DAG.getStore(Chain, dl, Value, 3400 getMemBasePlusOffset(Dst, DstOff, DAG), 3401 DstSV, DstSVOff + DstOff); 3402 OutChains.push_back(Store); 3403 DstOff += VTSize; 3404 } 3405 3406 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3407 &OutChains[0], OutChains.size()); 3408} 3409 3410SDValue SelectionDAG::getMemcpy(SDValue Chain, DebugLoc dl, SDValue Dst, 3411 SDValue Src, SDValue Size, 3412 unsigned Align, bool AlwaysInline, 3413 const Value *DstSV, uint64_t DstSVOff, 3414 const Value *SrcSV, uint64_t SrcSVOff) { 3415 3416 // Check to see if we should lower the memcpy to loads and stores first. 3417 // For cases within the target-specified limits, this is the best choice. 3418 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 3419 if (ConstantSize) { 3420 // Memcpy with size zero? Just return the original chain. 3421 if (ConstantSize->isNullValue()) 3422 return Chain; 3423 3424 SDValue Result = 3425 getMemcpyLoadsAndStores(*this, dl, Chain, Dst, Src, 3426 ConstantSize->getZExtValue(), 3427 Align, false, DstSV, DstSVOff, SrcSV, SrcSVOff); 3428 if (Result.getNode()) 3429 return Result; 3430 } 3431 3432 // Then check to see if we should lower the memcpy with target-specific 3433 // code. If the target chooses to do this, this is the next best. 3434 SDValue Result = 3435 TLI.EmitTargetCodeForMemcpy(*this, dl, Chain, Dst, Src, Size, Align, 3436 AlwaysInline, 3437 DstSV, DstSVOff, SrcSV, SrcSVOff); 3438 if (Result.getNode()) 3439 return Result; 3440 3441 // If we really need inline code and the target declined to provide it, 3442 // use a (potentially long) sequence of loads and stores. 3443 if (AlwaysInline) { 3444 assert(ConstantSize && "AlwaysInline requires a constant size!"); 3445 return getMemcpyLoadsAndStores(*this, dl, Chain, Dst, Src, 3446 ConstantSize->getZExtValue(), Align, true, 3447 DstSV, DstSVOff, SrcSV, SrcSVOff); 3448 } 3449 3450 // Emit a library call. 3451 TargetLowering::ArgListTy Args; 3452 TargetLowering::ArgListEntry Entry; 3453 Entry.Ty = TLI.getTargetData()->getIntPtrType(*getContext()); 3454 Entry.Node = Dst; Args.push_back(Entry); 3455 Entry.Node = Src; Args.push_back(Entry); 3456 Entry.Node = Size; Args.push_back(Entry); 3457 // FIXME: pass in DebugLoc 3458 std::pair<SDValue,SDValue> CallResult = 3459 TLI.LowerCallTo(Chain, Type::getVoidTy(*getContext()), 3460 false, false, false, false, 0, 3461 TLI.getLibcallCallingConv(RTLIB::MEMCPY), false, 3462 /*isReturnValueUsed=*/false, 3463 getExternalSymbol(TLI.getLibcallName(RTLIB::MEMCPY), 3464 TLI.getPointerTy()), 3465 Args, *this, dl, GetOrdering(Chain.getNode())); 3466 return CallResult.second; 3467} 3468 3469SDValue SelectionDAG::getMemmove(SDValue Chain, DebugLoc dl, SDValue Dst, 3470 SDValue Src, SDValue Size, 3471 unsigned Align, 3472 const Value *DstSV, uint64_t DstSVOff, 3473 const Value *SrcSV, uint64_t SrcSVOff) { 3474 3475 // Check to see if we should lower the memmove to loads and stores first. 3476 // For cases within the target-specified limits, this is the best choice. 3477 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 3478 if (ConstantSize) { 3479 // Memmove with size zero? Just return the original chain. 3480 if (ConstantSize->isNullValue()) 3481 return Chain; 3482 3483 SDValue Result = 3484 getMemmoveLoadsAndStores(*this, dl, Chain, Dst, Src, 3485 ConstantSize->getZExtValue(), 3486 Align, false, DstSV, DstSVOff, SrcSV, SrcSVOff); 3487 if (Result.getNode()) 3488 return Result; 3489 } 3490 3491 // Then check to see if we should lower the memmove with target-specific 3492 // code. If the target chooses to do this, this is the next best. 3493 SDValue Result = 3494 TLI.EmitTargetCodeForMemmove(*this, dl, Chain, Dst, Src, Size, Align, 3495 DstSV, DstSVOff, SrcSV, SrcSVOff); 3496 if (Result.getNode()) 3497 return Result; 3498 3499 // Emit a library call. 3500 TargetLowering::ArgListTy Args; 3501 TargetLowering::ArgListEntry Entry; 3502 Entry.Ty = TLI.getTargetData()->getIntPtrType(*getContext()); 3503 Entry.Node = Dst; Args.push_back(Entry); 3504 Entry.Node = Src; Args.push_back(Entry); 3505 Entry.Node = Size; Args.push_back(Entry); 3506 // FIXME: pass in DebugLoc 3507 std::pair<SDValue,SDValue> CallResult = 3508 TLI.LowerCallTo(Chain, Type::getVoidTy(*getContext()), 3509 false, false, false, false, 0, 3510 TLI.getLibcallCallingConv(RTLIB::MEMMOVE), false, 3511 /*isReturnValueUsed=*/false, 3512 getExternalSymbol(TLI.getLibcallName(RTLIB::MEMMOVE), 3513 TLI.getPointerTy()), 3514 Args, *this, dl, GetOrdering(Chain.getNode())); 3515 return CallResult.second; 3516} 3517 3518SDValue SelectionDAG::getMemset(SDValue Chain, DebugLoc dl, SDValue Dst, 3519 SDValue Src, SDValue Size, 3520 unsigned Align, 3521 const Value *DstSV, uint64_t DstSVOff) { 3522 3523 // Check to see if we should lower the memset to stores first. 3524 // For cases within the target-specified limits, this is the best choice. 3525 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 3526 if (ConstantSize) { 3527 // Memset with size zero? Just return the original chain. 3528 if (ConstantSize->isNullValue()) 3529 return Chain; 3530 3531 SDValue Result = 3532 getMemsetStores(*this, dl, Chain, Dst, Src, ConstantSize->getZExtValue(), 3533 Align, DstSV, DstSVOff); 3534 if (Result.getNode()) 3535 return Result; 3536 } 3537 3538 // Then check to see if we should lower the memset with target-specific 3539 // code. If the target chooses to do this, this is the next best. 3540 SDValue Result = 3541 TLI.EmitTargetCodeForMemset(*this, dl, Chain, Dst, Src, Size, Align, 3542 DstSV, DstSVOff); 3543 if (Result.getNode()) 3544 return Result; 3545 3546 // Emit a library call. 3547 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType(*getContext()); 3548 TargetLowering::ArgListTy Args; 3549 TargetLowering::ArgListEntry Entry; 3550 Entry.Node = Dst; Entry.Ty = IntPtrTy; 3551 Args.push_back(Entry); 3552 // Extend or truncate the argument to be an i32 value for the call. 3553 if (Src.getValueType().bitsGT(MVT::i32)) 3554 Src = getNode(ISD::TRUNCATE, dl, MVT::i32, Src); 3555 else 3556 Src = getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Src); 3557 Entry.Node = Src; 3558 Entry.Ty = Type::getInt32Ty(*getContext()); 3559 Entry.isSExt = true; 3560 Args.push_back(Entry); 3561 Entry.Node = Size; 3562 Entry.Ty = IntPtrTy; 3563 Entry.isSExt = false; 3564 Args.push_back(Entry); 3565 // FIXME: pass in DebugLoc 3566 std::pair<SDValue,SDValue> CallResult = 3567 TLI.LowerCallTo(Chain, Type::getVoidTy(*getContext()), 3568 false, false, false, false, 0, 3569 TLI.getLibcallCallingConv(RTLIB::MEMSET), false, 3570 /*isReturnValueUsed=*/false, 3571 getExternalSymbol(TLI.getLibcallName(RTLIB::MEMSET), 3572 TLI.getPointerTy()), 3573 Args, *this, dl, GetOrdering(Chain.getNode())); 3574 return CallResult.second; 3575} 3576 3577SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT, 3578 SDValue Chain, 3579 SDValue Ptr, SDValue Cmp, 3580 SDValue Swp, const Value* PtrVal, 3581 unsigned Alignment) { 3582 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3583 Alignment = getEVTAlignment(MemVT); 3584 3585 // Check if the memory reference references a frame index 3586 if (!PtrVal) 3587 if (const FrameIndexSDNode *FI = 3588 dyn_cast<const FrameIndexSDNode>(Ptr.getNode())) 3589 PtrVal = PseudoSourceValue::getFixedStack(FI->getIndex()); 3590 3591 MachineFunction &MF = getMachineFunction(); 3592 unsigned Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore; 3593 3594 // For now, atomics are considered to be volatile always. 3595 Flags |= MachineMemOperand::MOVolatile; 3596 3597 MachineMemOperand *MMO = 3598 MF.getMachineMemOperand(PtrVal, Flags, 0, 3599 MemVT.getStoreSize(), Alignment); 3600 3601 return getAtomic(Opcode, dl, MemVT, Chain, Ptr, Cmp, Swp, MMO); 3602} 3603 3604SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT, 3605 SDValue Chain, 3606 SDValue Ptr, SDValue Cmp, 3607 SDValue Swp, MachineMemOperand *MMO) { 3608 assert(Opcode == ISD::ATOMIC_CMP_SWAP && "Invalid Atomic Op"); 3609 assert(Cmp.getValueType() == Swp.getValueType() && "Invalid Atomic Op Types"); 3610 3611 EVT VT = Cmp.getValueType(); 3612 3613 SDVTList VTs = getVTList(VT, MVT::Other); 3614 FoldingSetNodeID ID; 3615 ID.AddInteger(MemVT.getRawBits()); 3616 SDValue Ops[] = {Chain, Ptr, Cmp, Swp}; 3617 AddNodeIDNode(ID, Opcode, VTs, Ops, 4); 3618 void* IP = 0; 3619 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) { 3620 cast<AtomicSDNode>(E)->refineAlignment(MMO); 3621 return SDValue(E, 0); 3622 } 3623 SDNode* N = NodeAllocator.Allocate<AtomicSDNode>(); 3624 new (N) AtomicSDNode(Opcode, dl, VTs, MemVT, Chain, Ptr, Cmp, Swp, MMO); 3625 CSEMap.InsertNode(N, IP); 3626 AllNodes.push_back(N); 3627 return SDValue(N, 0); 3628} 3629 3630SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT, 3631 SDValue Chain, 3632 SDValue Ptr, SDValue Val, 3633 const Value* PtrVal, 3634 unsigned Alignment) { 3635 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3636 Alignment = getEVTAlignment(MemVT); 3637 3638 // Check if the memory reference references a frame index 3639 if (!PtrVal) 3640 if (const FrameIndexSDNode *FI = 3641 dyn_cast<const FrameIndexSDNode>(Ptr.getNode())) 3642 PtrVal = PseudoSourceValue::getFixedStack(FI->getIndex()); 3643 3644 MachineFunction &MF = getMachineFunction(); 3645 unsigned Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore; 3646 3647 // For now, atomics are considered to be volatile always. 3648 Flags |= MachineMemOperand::MOVolatile; 3649 3650 MachineMemOperand *MMO = 3651 MF.getMachineMemOperand(PtrVal, Flags, 0, 3652 MemVT.getStoreSize(), Alignment); 3653 3654 return getAtomic(Opcode, dl, MemVT, Chain, Ptr, Val, MMO); 3655} 3656 3657SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT, 3658 SDValue Chain, 3659 SDValue Ptr, SDValue Val, 3660 MachineMemOperand *MMO) { 3661 assert((Opcode == ISD::ATOMIC_LOAD_ADD || 3662 Opcode == ISD::ATOMIC_LOAD_SUB || 3663 Opcode == ISD::ATOMIC_LOAD_AND || 3664 Opcode == ISD::ATOMIC_LOAD_OR || 3665 Opcode == ISD::ATOMIC_LOAD_XOR || 3666 Opcode == ISD::ATOMIC_LOAD_NAND || 3667 Opcode == ISD::ATOMIC_LOAD_MIN || 3668 Opcode == ISD::ATOMIC_LOAD_MAX || 3669 Opcode == ISD::ATOMIC_LOAD_UMIN || 3670 Opcode == ISD::ATOMIC_LOAD_UMAX || 3671 Opcode == ISD::ATOMIC_SWAP) && 3672 "Invalid Atomic Op"); 3673 3674 EVT VT = Val.getValueType(); 3675 3676 SDVTList VTs = getVTList(VT, MVT::Other); 3677 FoldingSetNodeID ID; 3678 ID.AddInteger(MemVT.getRawBits()); 3679 SDValue Ops[] = {Chain, Ptr, Val}; 3680 AddNodeIDNode(ID, Opcode, VTs, Ops, 3); 3681 void* IP = 0; 3682 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) { 3683 cast<AtomicSDNode>(E)->refineAlignment(MMO); 3684 return SDValue(E, 0); 3685 } 3686 SDNode* N = NodeAllocator.Allocate<AtomicSDNode>(); 3687 new (N) AtomicSDNode(Opcode, dl, VTs, MemVT, Chain, Ptr, Val, MMO); 3688 CSEMap.InsertNode(N, IP); 3689 AllNodes.push_back(N); 3690 return SDValue(N, 0); 3691} 3692 3693/// getMergeValues - Create a MERGE_VALUES node from the given operands. 3694/// Allowed to return something different (and simpler) if Simplify is true. 3695SDValue SelectionDAG::getMergeValues(const SDValue *Ops, unsigned NumOps, 3696 DebugLoc dl) { 3697 if (NumOps == 1) 3698 return Ops[0]; 3699 3700 SmallVector<EVT, 4> VTs; 3701 VTs.reserve(NumOps); 3702 for (unsigned i = 0; i < NumOps; ++i) 3703 VTs.push_back(Ops[i].getValueType()); 3704 return getNode(ISD::MERGE_VALUES, dl, getVTList(&VTs[0], NumOps), 3705 Ops, NumOps); 3706} 3707 3708SDValue 3709SelectionDAG::getMemIntrinsicNode(unsigned Opcode, DebugLoc dl, 3710 const EVT *VTs, unsigned NumVTs, 3711 const SDValue *Ops, unsigned NumOps, 3712 EVT MemVT, const Value *srcValue, int SVOff, 3713 unsigned Align, bool Vol, 3714 bool ReadMem, bool WriteMem) { 3715 return getMemIntrinsicNode(Opcode, dl, makeVTList(VTs, NumVTs), Ops, NumOps, 3716 MemVT, srcValue, SVOff, Align, Vol, 3717 ReadMem, WriteMem); 3718} 3719 3720SDValue 3721SelectionDAG::getMemIntrinsicNode(unsigned Opcode, DebugLoc dl, SDVTList VTList, 3722 const SDValue *Ops, unsigned NumOps, 3723 EVT MemVT, const Value *srcValue, int SVOff, 3724 unsigned Align, bool Vol, 3725 bool ReadMem, bool WriteMem) { 3726 if (Align == 0) // Ensure that codegen never sees alignment 0 3727 Align = getEVTAlignment(MemVT); 3728 3729 MachineFunction &MF = getMachineFunction(); 3730 unsigned Flags = 0; 3731 if (WriteMem) 3732 Flags |= MachineMemOperand::MOStore; 3733 if (ReadMem) 3734 Flags |= MachineMemOperand::MOLoad; 3735 if (Vol) 3736 Flags |= MachineMemOperand::MOVolatile; 3737 MachineMemOperand *MMO = 3738 MF.getMachineMemOperand(srcValue, Flags, SVOff, 3739 MemVT.getStoreSize(), Align); 3740 3741 return getMemIntrinsicNode(Opcode, dl, VTList, Ops, NumOps, MemVT, MMO); 3742} 3743 3744SDValue 3745SelectionDAG::getMemIntrinsicNode(unsigned Opcode, DebugLoc dl, SDVTList VTList, 3746 const SDValue *Ops, unsigned NumOps, 3747 EVT MemVT, MachineMemOperand *MMO) { 3748 assert((Opcode == ISD::INTRINSIC_VOID || 3749 Opcode == ISD::INTRINSIC_W_CHAIN || 3750 (Opcode <= INT_MAX && 3751 (int)Opcode >= ISD::FIRST_TARGET_MEMORY_OPCODE)) && 3752 "Opcode is not a memory-accessing opcode!"); 3753 3754 // Memoize the node unless it returns a flag. 3755 MemIntrinsicSDNode *N; 3756 if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) { 3757 FoldingSetNodeID ID; 3758 AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps); 3759 void *IP = 0; 3760 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) { 3761 cast<MemIntrinsicSDNode>(E)->refineAlignment(MMO); 3762 return SDValue(E, 0); 3763 } 3764 3765 N = NodeAllocator.Allocate<MemIntrinsicSDNode>(); 3766 new (N) MemIntrinsicSDNode(Opcode, dl, VTList, Ops, NumOps, MemVT, MMO); 3767 CSEMap.InsertNode(N, IP); 3768 } else { 3769 N = NodeAllocator.Allocate<MemIntrinsicSDNode>(); 3770 new (N) MemIntrinsicSDNode(Opcode, dl, VTList, Ops, NumOps, MemVT, MMO); 3771 } 3772 AllNodes.push_back(N); 3773 return SDValue(N, 0); 3774} 3775 3776SDValue 3777SelectionDAG::getLoad(ISD::MemIndexedMode AM, DebugLoc dl, 3778 ISD::LoadExtType ExtType, EVT VT, SDValue Chain, 3779 SDValue Ptr, SDValue Offset, 3780 const Value *SV, int SVOffset, EVT MemVT, 3781 bool isVolatile, unsigned Alignment) { 3782 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3783 Alignment = getEVTAlignment(VT); 3784 3785 // Check if the memory reference references a frame index 3786 if (!SV) 3787 if (const FrameIndexSDNode *FI = 3788 dyn_cast<const FrameIndexSDNode>(Ptr.getNode())) 3789 SV = PseudoSourceValue::getFixedStack(FI->getIndex()); 3790 3791 MachineFunction &MF = getMachineFunction(); 3792 unsigned Flags = MachineMemOperand::MOLoad; 3793 if (isVolatile) 3794 Flags |= MachineMemOperand::MOVolatile; 3795 MachineMemOperand *MMO = 3796 MF.getMachineMemOperand(SV, Flags, SVOffset, 3797 MemVT.getStoreSize(), Alignment); 3798 return getLoad(AM, dl, ExtType, VT, Chain, Ptr, Offset, MemVT, MMO); 3799} 3800 3801SDValue 3802SelectionDAG::getLoad(ISD::MemIndexedMode AM, DebugLoc dl, 3803 ISD::LoadExtType ExtType, EVT VT, SDValue Chain, 3804 SDValue Ptr, SDValue Offset, EVT MemVT, 3805 MachineMemOperand *MMO) { 3806 if (VT == MemVT) { 3807 ExtType = ISD::NON_EXTLOAD; 3808 } else if (ExtType == ISD::NON_EXTLOAD) { 3809 assert(VT == MemVT && "Non-extending load from different memory type!"); 3810 } else { 3811 // Extending load. 3812 assert(MemVT.getScalarType().bitsLT(VT.getScalarType()) && 3813 "Should only be an extending load, not truncating!"); 3814 assert(VT.isInteger() == MemVT.isInteger() && 3815 "Cannot convert from FP to Int or Int -> FP!"); 3816 assert(VT.isVector() == MemVT.isVector() && 3817 "Cannot use trunc store to convert to or from a vector!"); 3818 assert((!VT.isVector() || 3819 VT.getVectorNumElements() == MemVT.getVectorNumElements()) && 3820 "Cannot use trunc store to change the number of vector elements!"); 3821 } 3822 3823 bool Indexed = AM != ISD::UNINDEXED; 3824 assert((Indexed || Offset.getOpcode() == ISD::UNDEF) && 3825 "Unindexed load with an offset!"); 3826 3827 SDVTList VTs = Indexed ? 3828 getVTList(VT, Ptr.getValueType(), MVT::Other) : getVTList(VT, MVT::Other); 3829 SDValue Ops[] = { Chain, Ptr, Offset }; 3830 FoldingSetNodeID ID; 3831 AddNodeIDNode(ID, ISD::LOAD, VTs, Ops, 3); 3832 ID.AddInteger(MemVT.getRawBits()); 3833 ID.AddInteger(encodeMemSDNodeFlags(ExtType, AM, MMO->isVolatile())); 3834 void *IP = 0; 3835 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) { 3836 cast<LoadSDNode>(E)->refineAlignment(MMO); 3837 return SDValue(E, 0); 3838 } 3839 SDNode *N = NodeAllocator.Allocate<LoadSDNode>(); 3840 new (N) LoadSDNode(Ops, dl, VTs, AM, ExtType, MemVT, MMO); 3841 CSEMap.InsertNode(N, IP); 3842 AllNodes.push_back(N); 3843 return SDValue(N, 0); 3844} 3845 3846SDValue SelectionDAG::getLoad(EVT VT, DebugLoc dl, 3847 SDValue Chain, SDValue Ptr, 3848 const Value *SV, int SVOffset, 3849 bool isVolatile, unsigned Alignment) { 3850 SDValue Undef = getUNDEF(Ptr.getValueType()); 3851 return getLoad(ISD::UNINDEXED, dl, ISD::NON_EXTLOAD, VT, Chain, Ptr, Undef, 3852 SV, SVOffset, VT, isVolatile, Alignment); 3853} 3854 3855SDValue SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, DebugLoc dl, EVT VT, 3856 SDValue Chain, SDValue Ptr, 3857 const Value *SV, 3858 int SVOffset, EVT MemVT, 3859 bool isVolatile, unsigned Alignment) { 3860 SDValue Undef = getUNDEF(Ptr.getValueType()); 3861 return getLoad(ISD::UNINDEXED, dl, ExtType, VT, Chain, Ptr, Undef, 3862 SV, SVOffset, MemVT, isVolatile, Alignment); 3863} 3864 3865SDValue 3866SelectionDAG::getIndexedLoad(SDValue OrigLoad, DebugLoc dl, SDValue Base, 3867 SDValue Offset, ISD::MemIndexedMode AM) { 3868 LoadSDNode *LD = cast<LoadSDNode>(OrigLoad); 3869 assert(LD->getOffset().getOpcode() == ISD::UNDEF && 3870 "Load is already a indexed load!"); 3871 return getLoad(AM, dl, LD->getExtensionType(), OrigLoad.getValueType(), 3872 LD->getChain(), Base, Offset, LD->getSrcValue(), 3873 LD->getSrcValueOffset(), LD->getMemoryVT(), 3874 LD->isVolatile(), LD->getAlignment()); 3875} 3876 3877SDValue SelectionDAG::getStore(SDValue Chain, DebugLoc dl, SDValue Val, 3878 SDValue Ptr, const Value *SV, int SVOffset, 3879 bool isVolatile, unsigned Alignment) { 3880 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3881 Alignment = getEVTAlignment(Val.getValueType()); 3882 3883 // Check if the memory reference references a frame index 3884 if (!SV) 3885 if (const FrameIndexSDNode *FI = 3886 dyn_cast<const FrameIndexSDNode>(Ptr.getNode())) 3887 SV = PseudoSourceValue::getFixedStack(FI->getIndex()); 3888 3889 MachineFunction &MF = getMachineFunction(); 3890 unsigned Flags = MachineMemOperand::MOStore; 3891 if (isVolatile) 3892 Flags |= MachineMemOperand::MOVolatile; 3893 MachineMemOperand *MMO = 3894 MF.getMachineMemOperand(SV, Flags, SVOffset, 3895 Val.getValueType().getStoreSize(), Alignment); 3896 3897 return getStore(Chain, dl, Val, Ptr, MMO); 3898} 3899 3900SDValue SelectionDAG::getStore(SDValue Chain, DebugLoc dl, SDValue Val, 3901 SDValue Ptr, MachineMemOperand *MMO) { 3902 EVT VT = Val.getValueType(); 3903 SDVTList VTs = getVTList(MVT::Other); 3904 SDValue Undef = getUNDEF(Ptr.getValueType()); 3905 SDValue Ops[] = { Chain, Val, Ptr, Undef }; 3906 FoldingSetNodeID ID; 3907 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); 3908 ID.AddInteger(VT.getRawBits()); 3909 ID.AddInteger(encodeMemSDNodeFlags(false, ISD::UNINDEXED, MMO->isVolatile())); 3910 void *IP = 0; 3911 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) { 3912 cast<StoreSDNode>(E)->refineAlignment(MMO); 3913 return SDValue(E, 0); 3914 } 3915 SDNode *N = NodeAllocator.Allocate<StoreSDNode>(); 3916 new (N) StoreSDNode(Ops, dl, VTs, ISD::UNINDEXED, false, VT, MMO); 3917 CSEMap.InsertNode(N, IP); 3918 AllNodes.push_back(N); 3919 return SDValue(N, 0); 3920} 3921 3922SDValue SelectionDAG::getTruncStore(SDValue Chain, DebugLoc dl, SDValue Val, 3923 SDValue Ptr, const Value *SV, 3924 int SVOffset, EVT SVT, 3925 bool isVolatile, unsigned Alignment) { 3926 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3927 Alignment = getEVTAlignment(SVT); 3928 3929 // Check if the memory reference references a frame index 3930 if (!SV) 3931 if (const FrameIndexSDNode *FI = 3932 dyn_cast<const FrameIndexSDNode>(Ptr.getNode())) 3933 SV = PseudoSourceValue::getFixedStack(FI->getIndex()); 3934 3935 MachineFunction &MF = getMachineFunction(); 3936 unsigned Flags = MachineMemOperand::MOStore; 3937 if (isVolatile) 3938 Flags |= MachineMemOperand::MOVolatile; 3939 MachineMemOperand *MMO = 3940 MF.getMachineMemOperand(SV, Flags, SVOffset, SVT.getStoreSize(), Alignment); 3941 3942 return getTruncStore(Chain, dl, Val, Ptr, SVT, MMO); 3943} 3944 3945SDValue SelectionDAG::getTruncStore(SDValue Chain, DebugLoc dl, SDValue Val, 3946 SDValue Ptr, EVT SVT, 3947 MachineMemOperand *MMO) { 3948 EVT VT = Val.getValueType(); 3949 3950 if (VT == SVT) 3951 return getStore(Chain, dl, Val, Ptr, MMO); 3952 3953 assert(SVT.getScalarType().bitsLT(VT.getScalarType()) && 3954 "Should only be a truncating store, not extending!"); 3955 assert(VT.isInteger() == SVT.isInteger() && 3956 "Can't do FP-INT conversion!"); 3957 assert(VT.isVector() == SVT.isVector() && 3958 "Cannot use trunc store to convert to or from a vector!"); 3959 assert((!VT.isVector() || 3960 VT.getVectorNumElements() == SVT.getVectorNumElements()) && 3961 "Cannot use trunc store to change the number of vector elements!"); 3962 3963 SDVTList VTs = getVTList(MVT::Other); 3964 SDValue Undef = getUNDEF(Ptr.getValueType()); 3965 SDValue Ops[] = { Chain, Val, Ptr, Undef }; 3966 FoldingSetNodeID ID; 3967 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); 3968 ID.AddInteger(SVT.getRawBits()); 3969 ID.AddInteger(encodeMemSDNodeFlags(true, ISD::UNINDEXED, MMO->isVolatile())); 3970 void *IP = 0; 3971 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) { 3972 cast<StoreSDNode>(E)->refineAlignment(MMO); 3973 return SDValue(E, 0); 3974 } 3975 SDNode *N = NodeAllocator.Allocate<StoreSDNode>(); 3976 new (N) StoreSDNode(Ops, dl, VTs, ISD::UNINDEXED, true, SVT, MMO); 3977 CSEMap.InsertNode(N, IP); 3978 AllNodes.push_back(N); 3979 return SDValue(N, 0); 3980} 3981 3982SDValue 3983SelectionDAG::getIndexedStore(SDValue OrigStore, DebugLoc dl, SDValue Base, 3984 SDValue Offset, ISD::MemIndexedMode AM) { 3985 StoreSDNode *ST = cast<StoreSDNode>(OrigStore); 3986 assert(ST->getOffset().getOpcode() == ISD::UNDEF && 3987 "Store is already a indexed store!"); 3988 SDVTList VTs = getVTList(Base.getValueType(), MVT::Other); 3989 SDValue Ops[] = { ST->getChain(), ST->getValue(), Base, Offset }; 3990 FoldingSetNodeID ID; 3991 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); 3992 ID.AddInteger(ST->getMemoryVT().getRawBits()); 3993 ID.AddInteger(ST->getRawSubclassData()); 3994 void *IP = 0; 3995 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3996 return SDValue(E, 0); 3997 3998 SDNode *N = NodeAllocator.Allocate<StoreSDNode>(); 3999 new (N) StoreSDNode(Ops, dl, VTs, AM, 4000 ST->isTruncatingStore(), ST->getMemoryVT(), 4001 ST->getMemOperand()); 4002 CSEMap.InsertNode(N, IP); 4003 AllNodes.push_back(N); 4004 return SDValue(N, 0); 4005} 4006 4007SDValue SelectionDAG::getVAArg(EVT VT, DebugLoc dl, 4008 SDValue Chain, SDValue Ptr, 4009 SDValue SV) { 4010 SDValue Ops[] = { Chain, Ptr, SV }; 4011 return getNode(ISD::VAARG, dl, getVTList(VT, MVT::Other), Ops, 3); 4012} 4013 4014SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, EVT VT, 4015 const SDUse *Ops, unsigned NumOps) { 4016 switch (NumOps) { 4017 case 0: return getNode(Opcode, DL, VT); 4018 case 1: return getNode(Opcode, DL, VT, Ops[0]); 4019 case 2: return getNode(Opcode, DL, VT, Ops[0], Ops[1]); 4020 case 3: return getNode(Opcode, DL, VT, Ops[0], Ops[1], Ops[2]); 4021 default: break; 4022 } 4023 4024 // Copy from an SDUse array into an SDValue array for use with 4025 // the regular getNode logic. 4026 SmallVector<SDValue, 8> NewOps(Ops, Ops + NumOps); 4027 return getNode(Opcode, DL, VT, &NewOps[0], NumOps); 4028} 4029 4030SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, EVT VT, 4031 const SDValue *Ops, unsigned NumOps) { 4032 switch (NumOps) { 4033 case 0: return getNode(Opcode, DL, VT); 4034 case 1: return getNode(Opcode, DL, VT, Ops[0]); 4035 case 2: return getNode(Opcode, DL, VT, Ops[0], Ops[1]); 4036 case 3: return getNode(Opcode, DL, VT, Ops[0], Ops[1], Ops[2]); 4037 default: break; 4038 } 4039 4040 switch (Opcode) { 4041 default: break; 4042 case ISD::SELECT_CC: { 4043 assert(NumOps == 5 && "SELECT_CC takes 5 operands!"); 4044 assert(Ops[0].getValueType() == Ops[1].getValueType() && 4045 "LHS and RHS of condition must have same type!"); 4046 assert(Ops[2].getValueType() == Ops[3].getValueType() && 4047 "True and False arms of SelectCC must have same type!"); 4048 assert(Ops[2].getValueType() == VT && 4049 "select_cc node must be of same type as true and false value!"); 4050 break; 4051 } 4052 case ISD::BR_CC: { 4053 assert(NumOps == 5 && "BR_CC takes 5 operands!"); 4054 assert(Ops[2].getValueType() == Ops[3].getValueType() && 4055 "LHS/RHS of comparison should match types!"); 4056 break; 4057 } 4058 } 4059 4060 // Memoize nodes. 4061 SDNode *N; 4062 SDVTList VTs = getVTList(VT); 4063 4064 if (VT != MVT::Flag) { 4065 FoldingSetNodeID ID; 4066 AddNodeIDNode(ID, Opcode, VTs, Ops, NumOps); 4067 void *IP = 0; 4068 4069 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 4070 return SDValue(E, 0); 4071 4072 N = NodeAllocator.Allocate<SDNode>(); 4073 new (N) SDNode(Opcode, DL, VTs, Ops, NumOps); 4074 CSEMap.InsertNode(N, IP); 4075 } else { 4076 N = NodeAllocator.Allocate<SDNode>(); 4077 new (N) SDNode(Opcode, DL, VTs, Ops, NumOps); 4078 } 4079 4080 AllNodes.push_back(N); 4081#ifndef NDEBUG 4082 VerifyNode(N); 4083#endif 4084 return SDValue(N, 0); 4085} 4086 4087SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, 4088 const std::vector<EVT> &ResultTys, 4089 const SDValue *Ops, unsigned NumOps) { 4090 return getNode(Opcode, DL, getVTList(&ResultTys[0], ResultTys.size()), 4091 Ops, NumOps); 4092} 4093 4094SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, 4095 const EVT *VTs, unsigned NumVTs, 4096 const SDValue *Ops, unsigned NumOps) { 4097 if (NumVTs == 1) 4098 return getNode(Opcode, DL, VTs[0], Ops, NumOps); 4099 return getNode(Opcode, DL, makeVTList(VTs, NumVTs), Ops, NumOps); 4100} 4101 4102SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, 4103 const SDValue *Ops, unsigned NumOps) { 4104 if (VTList.NumVTs == 1) 4105 return getNode(Opcode, DL, VTList.VTs[0], Ops, NumOps); 4106 4107#if 0 4108 switch (Opcode) { 4109 // FIXME: figure out how to safely handle things like 4110 // int foo(int x) { return 1 << (x & 255); } 4111 // int bar() { return foo(256); } 4112 case ISD::SRA_PARTS: 4113 case ISD::SRL_PARTS: 4114 case ISD::SHL_PARTS: 4115 if (N3.getOpcode() == ISD::SIGN_EXTEND_INREG && 4116 cast<VTSDNode>(N3.getOperand(1))->getVT() != MVT::i1) 4117 return getNode(Opcode, DL, VT, N1, N2, N3.getOperand(0)); 4118 else if (N3.getOpcode() == ISD::AND) 4119 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(N3.getOperand(1))) { 4120 // If the and is only masking out bits that cannot effect the shift, 4121 // eliminate the and. 4122 unsigned NumBits = VT.getScalarType().getSizeInBits()*2; 4123 if ((AndRHS->getValue() & (NumBits-1)) == NumBits-1) 4124 return getNode(Opcode, DL, VT, N1, N2, N3.getOperand(0)); 4125 } 4126 break; 4127 } 4128#endif 4129 4130 // Memoize the node unless it returns a flag. 4131 SDNode *N; 4132 if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) { 4133 FoldingSetNodeID ID; 4134 AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps); 4135 void *IP = 0; 4136 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 4137 return SDValue(E, 0); 4138 4139 if (NumOps == 1) { 4140 N = NodeAllocator.Allocate<UnarySDNode>(); 4141 new (N) UnarySDNode(Opcode, DL, VTList, Ops[0]); 4142 } else if (NumOps == 2) { 4143 N = NodeAllocator.Allocate<BinarySDNode>(); 4144 new (N) BinarySDNode(Opcode, DL, VTList, Ops[0], Ops[1]); 4145 } else if (NumOps == 3) { 4146 N = NodeAllocator.Allocate<TernarySDNode>(); 4147 new (N) TernarySDNode(Opcode, DL, VTList, Ops[0], Ops[1], Ops[2]); 4148 } else { 4149 N = NodeAllocator.Allocate<SDNode>(); 4150 new (N) SDNode(Opcode, DL, VTList, Ops, NumOps); 4151 } 4152 CSEMap.InsertNode(N, IP); 4153 } else { 4154 if (NumOps == 1) { 4155 N = NodeAllocator.Allocate<UnarySDNode>(); 4156 new (N) UnarySDNode(Opcode, DL, VTList, Ops[0]); 4157 } else if (NumOps == 2) { 4158 N = NodeAllocator.Allocate<BinarySDNode>(); 4159 new (N) BinarySDNode(Opcode, DL, VTList, Ops[0], Ops[1]); 4160 } else if (NumOps == 3) { 4161 N = NodeAllocator.Allocate<TernarySDNode>(); 4162 new (N) TernarySDNode(Opcode, DL, VTList, Ops[0], Ops[1], Ops[2]); 4163 } else { 4164 N = NodeAllocator.Allocate<SDNode>(); 4165 new (N) SDNode(Opcode, DL, VTList, Ops, NumOps); 4166 } 4167 } 4168 AllNodes.push_back(N); 4169#ifndef NDEBUG 4170 VerifyNode(N); 4171#endif 4172 return SDValue(N, 0); 4173} 4174 4175SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList) { 4176 return getNode(Opcode, DL, VTList, 0, 0); 4177} 4178 4179SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, 4180 SDValue N1) { 4181 SDValue Ops[] = { N1 }; 4182 return getNode(Opcode, DL, VTList, Ops, 1); 4183} 4184 4185SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, 4186 SDValue N1, SDValue N2) { 4187 SDValue Ops[] = { N1, N2 }; 4188 return getNode(Opcode, DL, VTList, Ops, 2); 4189} 4190 4191SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, 4192 SDValue N1, SDValue N2, SDValue N3) { 4193 SDValue Ops[] = { N1, N2, N3 }; 4194 return getNode(Opcode, DL, VTList, Ops, 3); 4195} 4196 4197SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, 4198 SDValue N1, SDValue N2, SDValue N3, 4199 SDValue N4) { 4200 SDValue Ops[] = { N1, N2, N3, N4 }; 4201 return getNode(Opcode, DL, VTList, Ops, 4); 4202} 4203 4204SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, 4205 SDValue N1, SDValue N2, SDValue N3, 4206 SDValue N4, SDValue N5) { 4207 SDValue Ops[] = { N1, N2, N3, N4, N5 }; 4208 return getNode(Opcode, DL, VTList, Ops, 5); 4209} 4210 4211SDVTList SelectionDAG::getVTList(EVT VT) { 4212 return makeVTList(SDNode::getValueTypeList(VT), 1); 4213} 4214 4215SDVTList SelectionDAG::getVTList(EVT VT1, EVT VT2) { 4216 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 4217 E = VTList.rend(); I != E; ++I) 4218 if (I->NumVTs == 2 && I->VTs[0] == VT1 && I->VTs[1] == VT2) 4219 return *I; 4220 4221 EVT *Array = Allocator.Allocate<EVT>(2); 4222 Array[0] = VT1; 4223 Array[1] = VT2; 4224 SDVTList Result = makeVTList(Array, 2); 4225 VTList.push_back(Result); 4226 return Result; 4227} 4228 4229SDVTList SelectionDAG::getVTList(EVT VT1, EVT VT2, EVT VT3) { 4230 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 4231 E = VTList.rend(); I != E; ++I) 4232 if (I->NumVTs == 3 && I->VTs[0] == VT1 && I->VTs[1] == VT2 && 4233 I->VTs[2] == VT3) 4234 return *I; 4235 4236 EVT *Array = Allocator.Allocate<EVT>(3); 4237 Array[0] = VT1; 4238 Array[1] = VT2; 4239 Array[2] = VT3; 4240 SDVTList Result = makeVTList(Array, 3); 4241 VTList.push_back(Result); 4242 return Result; 4243} 4244 4245SDVTList SelectionDAG::getVTList(EVT VT1, EVT VT2, EVT VT3, EVT VT4) { 4246 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 4247 E = VTList.rend(); I != E; ++I) 4248 if (I->NumVTs == 4 && I->VTs[0] == VT1 && I->VTs[1] == VT2 && 4249 I->VTs[2] == VT3 && I->VTs[3] == VT4) 4250 return *I; 4251 4252 EVT *Array = Allocator.Allocate<EVT>(4); 4253 Array[0] = VT1; 4254 Array[1] = VT2; 4255 Array[2] = VT3; 4256 Array[3] = VT4; 4257 SDVTList Result = makeVTList(Array, 4); 4258 VTList.push_back(Result); 4259 return Result; 4260} 4261 4262SDVTList SelectionDAG::getVTList(const EVT *VTs, unsigned NumVTs) { 4263 switch (NumVTs) { 4264 case 0: llvm_unreachable("Cannot have nodes without results!"); 4265 case 1: return getVTList(VTs[0]); 4266 case 2: return getVTList(VTs[0], VTs[1]); 4267 case 3: return getVTList(VTs[0], VTs[1], VTs[2]); 4268 case 4: return getVTList(VTs[0], VTs[1], VTs[2], VTs[3]); 4269 default: break; 4270 } 4271 4272 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 4273 E = VTList.rend(); I != E; ++I) { 4274 if (I->NumVTs != NumVTs || VTs[0] != I->VTs[0] || VTs[1] != I->VTs[1]) 4275 continue; 4276 4277 bool NoMatch = false; 4278 for (unsigned i = 2; i != NumVTs; ++i) 4279 if (VTs[i] != I->VTs[i]) { 4280 NoMatch = true; 4281 break; 4282 } 4283 if (!NoMatch) 4284 return *I; 4285 } 4286 4287 EVT *Array = Allocator.Allocate<EVT>(NumVTs); 4288 std::copy(VTs, VTs+NumVTs, Array); 4289 SDVTList Result = makeVTList(Array, NumVTs); 4290 VTList.push_back(Result); 4291 return Result; 4292} 4293 4294 4295/// UpdateNodeOperands - *Mutate* the specified node in-place to have the 4296/// specified operands. If the resultant node already exists in the DAG, 4297/// this does not modify the specified node, instead it returns the node that 4298/// already exists. If the resultant node does not exist in the DAG, the 4299/// input node is returned. As a degenerate case, if you specify the same 4300/// input operands as the node already has, the input node is returned. 4301SDValue SelectionDAG::UpdateNodeOperands(SDValue InN, SDValue Op) { 4302 SDNode *N = InN.getNode(); 4303 assert(N->getNumOperands() == 1 && "Update with wrong number of operands"); 4304 4305 // Check to see if there is no change. 4306 if (Op == N->getOperand(0)) return InN; 4307 4308 // See if the modified node already exists. 4309 void *InsertPos = 0; 4310 if (SDNode *Existing = FindModifiedNodeSlot(N, Op, InsertPos)) 4311 return SDValue(Existing, InN.getResNo()); 4312 4313 // Nope it doesn't. Remove the node from its current place in the maps. 4314 if (InsertPos) 4315 if (!RemoveNodeFromCSEMaps(N)) 4316 InsertPos = 0; 4317 4318 // Now we update the operands. 4319 N->OperandList[0].set(Op); 4320 4321 // If this gets put into a CSE map, add it. 4322 if (InsertPos) CSEMap.InsertNode(N, InsertPos); 4323 return InN; 4324} 4325 4326SDValue SelectionDAG:: 4327UpdateNodeOperands(SDValue InN, SDValue Op1, SDValue Op2) { 4328 SDNode *N = InN.getNode(); 4329 assert(N->getNumOperands() == 2 && "Update with wrong number of operands"); 4330 4331 // Check to see if there is no change. 4332 if (Op1 == N->getOperand(0) && Op2 == N->getOperand(1)) 4333 return InN; // No operands changed, just return the input node. 4334 4335 // See if the modified node already exists. 4336 void *InsertPos = 0; 4337 if (SDNode *Existing = FindModifiedNodeSlot(N, Op1, Op2, InsertPos)) 4338 return SDValue(Existing, InN.getResNo()); 4339 4340 // Nope it doesn't. Remove the node from its current place in the maps. 4341 if (InsertPos) 4342 if (!RemoveNodeFromCSEMaps(N)) 4343 InsertPos = 0; 4344 4345 // Now we update the operands. 4346 if (N->OperandList[0] != Op1) 4347 N->OperandList[0].set(Op1); 4348 if (N->OperandList[1] != Op2) 4349 N->OperandList[1].set(Op2); 4350 4351 // If this gets put into a CSE map, add it. 4352 if (InsertPos) CSEMap.InsertNode(N, InsertPos); 4353 return InN; 4354} 4355 4356SDValue SelectionDAG:: 4357UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, SDValue Op3) { 4358 SDValue Ops[] = { Op1, Op2, Op3 }; 4359 return UpdateNodeOperands(N, Ops, 3); 4360} 4361 4362SDValue SelectionDAG:: 4363UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, 4364 SDValue Op3, SDValue Op4) { 4365 SDValue Ops[] = { Op1, Op2, Op3, Op4 }; 4366 return UpdateNodeOperands(N, Ops, 4); 4367} 4368 4369SDValue SelectionDAG:: 4370UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, 4371 SDValue Op3, SDValue Op4, SDValue Op5) { 4372 SDValue Ops[] = { Op1, Op2, Op3, Op4, Op5 }; 4373 return UpdateNodeOperands(N, Ops, 5); 4374} 4375 4376SDValue SelectionDAG:: 4377UpdateNodeOperands(SDValue InN, const SDValue *Ops, unsigned NumOps) { 4378 SDNode *N = InN.getNode(); 4379 assert(N->getNumOperands() == NumOps && 4380 "Update with wrong number of operands"); 4381 4382 // Check to see if there is no change. 4383 bool AnyChange = false; 4384 for (unsigned i = 0; i != NumOps; ++i) { 4385 if (Ops[i] != N->getOperand(i)) { 4386 AnyChange = true; 4387 break; 4388 } 4389 } 4390 4391 // No operands changed, just return the input node. 4392 if (!AnyChange) return InN; 4393 4394 // See if the modified node already exists. 4395 void *InsertPos = 0; 4396 if (SDNode *Existing = FindModifiedNodeSlot(N, Ops, NumOps, InsertPos)) 4397 return SDValue(Existing, InN.getResNo()); 4398 4399 // Nope it doesn't. Remove the node from its current place in the maps. 4400 if (InsertPos) 4401 if (!RemoveNodeFromCSEMaps(N)) 4402 InsertPos = 0; 4403 4404 // Now we update the operands. 4405 for (unsigned i = 0; i != NumOps; ++i) 4406 if (N->OperandList[i] != Ops[i]) 4407 N->OperandList[i].set(Ops[i]); 4408 4409 // If this gets put into a CSE map, add it. 4410 if (InsertPos) CSEMap.InsertNode(N, InsertPos); 4411 return InN; 4412} 4413 4414/// DropOperands - Release the operands and set this node to have 4415/// zero operands. 4416void SDNode::DropOperands() { 4417 // Unlike the code in MorphNodeTo that does this, we don't need to 4418 // watch for dead nodes here. 4419 for (op_iterator I = op_begin(), E = op_end(); I != E; ) { 4420 SDUse &Use = *I++; 4421 Use.set(SDValue()); 4422 } 4423} 4424 4425/// SelectNodeTo - These are wrappers around MorphNodeTo that accept a 4426/// machine opcode. 4427/// 4428SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4429 EVT VT) { 4430 SDVTList VTs = getVTList(VT); 4431 return SelectNodeTo(N, MachineOpc, VTs, 0, 0); 4432} 4433 4434SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4435 EVT VT, SDValue Op1) { 4436 SDVTList VTs = getVTList(VT); 4437 SDValue Ops[] = { Op1 }; 4438 return SelectNodeTo(N, MachineOpc, VTs, Ops, 1); 4439} 4440 4441SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4442 EVT VT, SDValue Op1, 4443 SDValue Op2) { 4444 SDVTList VTs = getVTList(VT); 4445 SDValue Ops[] = { Op1, Op2 }; 4446 return SelectNodeTo(N, MachineOpc, VTs, Ops, 2); 4447} 4448 4449SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4450 EVT VT, SDValue Op1, 4451 SDValue Op2, SDValue Op3) { 4452 SDVTList VTs = getVTList(VT); 4453 SDValue Ops[] = { Op1, Op2, Op3 }; 4454 return SelectNodeTo(N, MachineOpc, VTs, Ops, 3); 4455} 4456 4457SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4458 EVT VT, const SDValue *Ops, 4459 unsigned NumOps) { 4460 SDVTList VTs = getVTList(VT); 4461 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 4462} 4463 4464SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4465 EVT VT1, EVT VT2, const SDValue *Ops, 4466 unsigned NumOps) { 4467 SDVTList VTs = getVTList(VT1, VT2); 4468 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 4469} 4470 4471SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4472 EVT VT1, EVT VT2) { 4473 SDVTList VTs = getVTList(VT1, VT2); 4474 return SelectNodeTo(N, MachineOpc, VTs, (SDValue *)0, 0); 4475} 4476 4477SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4478 EVT VT1, EVT VT2, EVT VT3, 4479 const SDValue *Ops, unsigned NumOps) { 4480 SDVTList VTs = getVTList(VT1, VT2, VT3); 4481 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 4482} 4483 4484SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4485 EVT VT1, EVT VT2, EVT VT3, EVT VT4, 4486 const SDValue *Ops, unsigned NumOps) { 4487 SDVTList VTs = getVTList(VT1, VT2, VT3, VT4); 4488 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 4489} 4490 4491SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4492 EVT VT1, EVT VT2, 4493 SDValue Op1) { 4494 SDVTList VTs = getVTList(VT1, VT2); 4495 SDValue Ops[] = { Op1 }; 4496 return SelectNodeTo(N, MachineOpc, VTs, Ops, 1); 4497} 4498 4499SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4500 EVT VT1, EVT VT2, 4501 SDValue Op1, SDValue Op2) { 4502 SDVTList VTs = getVTList(VT1, VT2); 4503 SDValue Ops[] = { Op1, Op2 }; 4504 return SelectNodeTo(N, MachineOpc, VTs, Ops, 2); 4505} 4506 4507SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4508 EVT VT1, EVT VT2, 4509 SDValue Op1, SDValue Op2, 4510 SDValue Op3) { 4511 SDVTList VTs = getVTList(VT1, VT2); 4512 SDValue Ops[] = { Op1, Op2, Op3 }; 4513 return SelectNodeTo(N, MachineOpc, VTs, Ops, 3); 4514} 4515 4516SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4517 EVT VT1, EVT VT2, EVT VT3, 4518 SDValue Op1, SDValue Op2, 4519 SDValue Op3) { 4520 SDVTList VTs = getVTList(VT1, VT2, VT3); 4521 SDValue Ops[] = { Op1, Op2, Op3 }; 4522 return SelectNodeTo(N, MachineOpc, VTs, Ops, 3); 4523} 4524 4525SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4526 SDVTList VTs, const SDValue *Ops, 4527 unsigned NumOps) { 4528 return MorphNodeTo(N, ~MachineOpc, VTs, Ops, NumOps); 4529} 4530 4531SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4532 EVT VT) { 4533 SDVTList VTs = getVTList(VT); 4534 return MorphNodeTo(N, Opc, VTs, 0, 0); 4535} 4536 4537SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4538 EVT VT, SDValue Op1) { 4539 SDVTList VTs = getVTList(VT); 4540 SDValue Ops[] = { Op1 }; 4541 return MorphNodeTo(N, Opc, VTs, Ops, 1); 4542} 4543 4544SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4545 EVT VT, SDValue Op1, 4546 SDValue Op2) { 4547 SDVTList VTs = getVTList(VT); 4548 SDValue Ops[] = { Op1, Op2 }; 4549 return MorphNodeTo(N, Opc, VTs, Ops, 2); 4550} 4551 4552SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4553 EVT VT, SDValue Op1, 4554 SDValue Op2, SDValue Op3) { 4555 SDVTList VTs = getVTList(VT); 4556 SDValue Ops[] = { Op1, Op2, Op3 }; 4557 return MorphNodeTo(N, Opc, VTs, Ops, 3); 4558} 4559 4560SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4561 EVT VT, const SDValue *Ops, 4562 unsigned NumOps) { 4563 SDVTList VTs = getVTList(VT); 4564 return MorphNodeTo(N, Opc, VTs, Ops, NumOps); 4565} 4566 4567SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4568 EVT VT1, EVT VT2, const SDValue *Ops, 4569 unsigned NumOps) { 4570 SDVTList VTs = getVTList(VT1, VT2); 4571 return MorphNodeTo(N, Opc, VTs, Ops, NumOps); 4572} 4573 4574SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4575 EVT VT1, EVT VT2) { 4576 SDVTList VTs = getVTList(VT1, VT2); 4577 return MorphNodeTo(N, Opc, VTs, (SDValue *)0, 0); 4578} 4579 4580SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4581 EVT VT1, EVT VT2, EVT VT3, 4582 const SDValue *Ops, unsigned NumOps) { 4583 SDVTList VTs = getVTList(VT1, VT2, VT3); 4584 return MorphNodeTo(N, Opc, VTs, Ops, NumOps); 4585} 4586 4587SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4588 EVT VT1, EVT VT2, 4589 SDValue Op1) { 4590 SDVTList VTs = getVTList(VT1, VT2); 4591 SDValue Ops[] = { Op1 }; 4592 return MorphNodeTo(N, Opc, VTs, Ops, 1); 4593} 4594 4595SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4596 EVT VT1, EVT VT2, 4597 SDValue Op1, SDValue Op2) { 4598 SDVTList VTs = getVTList(VT1, VT2); 4599 SDValue Ops[] = { Op1, Op2 }; 4600 return MorphNodeTo(N, Opc, VTs, Ops, 2); 4601} 4602 4603SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4604 EVT VT1, EVT VT2, 4605 SDValue Op1, SDValue Op2, 4606 SDValue Op3) { 4607 SDVTList VTs = getVTList(VT1, VT2); 4608 SDValue Ops[] = { Op1, Op2, Op3 }; 4609 return MorphNodeTo(N, Opc, VTs, Ops, 3); 4610} 4611 4612/// MorphNodeTo - These *mutate* the specified node to have the specified 4613/// return type, opcode, and operands. 4614/// 4615/// Note that MorphNodeTo returns the resultant node. If there is already a 4616/// node of the specified opcode and operands, it returns that node instead of 4617/// the current one. Note that the DebugLoc need not be the same. 4618/// 4619/// Using MorphNodeTo is faster than creating a new node and swapping it in 4620/// with ReplaceAllUsesWith both because it often avoids allocating a new 4621/// node, and because it doesn't require CSE recalculation for any of 4622/// the node's users. 4623/// 4624SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4625 SDVTList VTs, const SDValue *Ops, 4626 unsigned NumOps) { 4627 // If an identical node already exists, use it. 4628 void *IP = 0; 4629 if (VTs.VTs[VTs.NumVTs-1] != MVT::Flag) { 4630 FoldingSetNodeID ID; 4631 AddNodeIDNode(ID, Opc, VTs, Ops, NumOps); 4632 if (SDNode *ON = CSEMap.FindNodeOrInsertPos(ID, IP)) 4633 return ON; 4634 } 4635 4636 if (!RemoveNodeFromCSEMaps(N)) 4637 IP = 0; 4638 4639 // Start the morphing. 4640 N->NodeType = Opc; 4641 N->ValueList = VTs.VTs; 4642 N->NumValues = VTs.NumVTs; 4643 4644 // Clear the operands list, updating used nodes to remove this from their 4645 // use list. Keep track of any operands that become dead as a result. 4646 SmallPtrSet<SDNode*, 16> DeadNodeSet; 4647 for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ) { 4648 SDUse &Use = *I++; 4649 SDNode *Used = Use.getNode(); 4650 Use.set(SDValue()); 4651 if (Used->use_empty()) 4652 DeadNodeSet.insert(Used); 4653 } 4654 4655 if (MachineSDNode *MN = dyn_cast<MachineSDNode>(N)) { 4656 // Initialize the memory references information. 4657 MN->setMemRefs(0, 0); 4658 // If NumOps is larger than the # of operands we can have in a 4659 // MachineSDNode, reallocate the operand list. 4660 if (NumOps > MN->NumOperands || !MN->OperandsNeedDelete) { 4661 if (MN->OperandsNeedDelete) 4662 delete[] MN->OperandList; 4663 if (NumOps > array_lengthof(MN->LocalOperands)) 4664 // We're creating a final node that will live unmorphed for the 4665 // remainder of the current SelectionDAG iteration, so we can allocate 4666 // the operands directly out of a pool with no recycling metadata. 4667 MN->InitOperands(OperandAllocator.Allocate<SDUse>(NumOps), 4668 Ops, NumOps); 4669 else 4670 MN->InitOperands(MN->LocalOperands, Ops, NumOps); 4671 MN->OperandsNeedDelete = false; 4672 } else 4673 MN->InitOperands(MN->OperandList, Ops, NumOps); 4674 } else { 4675 // If NumOps is larger than the # of operands we currently have, reallocate 4676 // the operand list. 4677 if (NumOps > N->NumOperands) { 4678 if (N->OperandsNeedDelete) 4679 delete[] N->OperandList; 4680 N->InitOperands(new SDUse[NumOps], Ops, NumOps); 4681 N->OperandsNeedDelete = true; 4682 } else 4683 N->InitOperands(N->OperandList, Ops, NumOps); 4684 } 4685 4686 // Delete any nodes that are still dead after adding the uses for the 4687 // new operands. 4688 SmallVector<SDNode *, 16> DeadNodes; 4689 for (SmallPtrSet<SDNode *, 16>::iterator I = DeadNodeSet.begin(), 4690 E = DeadNodeSet.end(); I != E; ++I) 4691 if ((*I)->use_empty()) 4692 DeadNodes.push_back(*I); 4693 RemoveDeadNodes(DeadNodes); 4694 4695 if (IP) 4696 CSEMap.InsertNode(N, IP); // Memoize the new node. 4697 return N; 4698} 4699 4700 4701/// getMachineNode - These are used for target selectors to create a new node 4702/// with specified return type(s), MachineInstr opcode, and operands. 4703/// 4704/// Note that getMachineNode returns the resultant node. If there is already a 4705/// node of the specified opcode and operands, it returns that node instead of 4706/// the current one. 4707MachineSDNode * 4708SelectionDAG::getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT) { 4709 SDVTList VTs = getVTList(VT); 4710 return getMachineNode(Opcode, dl, VTs, 0, 0); 4711} 4712 4713MachineSDNode * 4714SelectionDAG::getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT, SDValue Op1) { 4715 SDVTList VTs = getVTList(VT); 4716 SDValue Ops[] = { Op1 }; 4717 return getMachineNode(Opcode, dl, VTs, Ops, array_lengthof(Ops)); 4718} 4719 4720MachineSDNode * 4721SelectionDAG::getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT, 4722 SDValue Op1, SDValue Op2) { 4723 SDVTList VTs = getVTList(VT); 4724 SDValue Ops[] = { Op1, Op2 }; 4725 return getMachineNode(Opcode, dl, VTs, Ops, array_lengthof(Ops)); 4726} 4727 4728MachineSDNode * 4729SelectionDAG::getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT, 4730 SDValue Op1, SDValue Op2, SDValue Op3) { 4731 SDVTList VTs = getVTList(VT); 4732 SDValue Ops[] = { Op1, Op2, Op3 }; 4733 return getMachineNode(Opcode, dl, VTs, Ops, array_lengthof(Ops)); 4734} 4735 4736MachineSDNode * 4737SelectionDAG::getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT, 4738 const SDValue *Ops, unsigned NumOps) { 4739 SDVTList VTs = getVTList(VT); 4740 return getMachineNode(Opcode, dl, VTs, Ops, NumOps); 4741} 4742 4743MachineSDNode * 4744SelectionDAG::getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2) { 4745 SDVTList VTs = getVTList(VT1, VT2); 4746 return getMachineNode(Opcode, dl, VTs, 0, 0); 4747} 4748 4749MachineSDNode * 4750SelectionDAG::getMachineNode(unsigned Opcode, DebugLoc dl, 4751 EVT VT1, EVT VT2, SDValue Op1) { 4752 SDVTList VTs = getVTList(VT1, VT2); 4753 SDValue Ops[] = { Op1 }; 4754 return getMachineNode(Opcode, dl, VTs, Ops, array_lengthof(Ops)); 4755} 4756 4757MachineSDNode * 4758SelectionDAG::getMachineNode(unsigned Opcode, DebugLoc dl, 4759 EVT VT1, EVT VT2, SDValue Op1, SDValue Op2) { 4760 SDVTList VTs = getVTList(VT1, VT2); 4761 SDValue Ops[] = { Op1, Op2 }; 4762 return getMachineNode(Opcode, dl, VTs, Ops, array_lengthof(Ops)); 4763} 4764 4765MachineSDNode * 4766SelectionDAG::getMachineNode(unsigned Opcode, DebugLoc dl, 4767 EVT VT1, EVT VT2, SDValue Op1, 4768 SDValue Op2, SDValue Op3) { 4769 SDVTList VTs = getVTList(VT1, VT2); 4770 SDValue Ops[] = { Op1, Op2, Op3 }; 4771 return getMachineNode(Opcode, dl, VTs, Ops, array_lengthof(Ops)); 4772} 4773 4774MachineSDNode * 4775SelectionDAG::getMachineNode(unsigned Opcode, DebugLoc dl, 4776 EVT VT1, EVT VT2, 4777 const SDValue *Ops, unsigned NumOps) { 4778 SDVTList VTs = getVTList(VT1, VT2); 4779 return getMachineNode(Opcode, dl, VTs, Ops, NumOps); 4780} 4781 4782MachineSDNode * 4783SelectionDAG::getMachineNode(unsigned Opcode, DebugLoc dl, 4784 EVT VT1, EVT VT2, EVT VT3, 4785 SDValue Op1, SDValue Op2) { 4786 SDVTList VTs = getVTList(VT1, VT2, VT3); 4787 SDValue Ops[] = { Op1, Op2 }; 4788 return getMachineNode(Opcode, dl, VTs, Ops, array_lengthof(Ops)); 4789} 4790 4791MachineSDNode * 4792SelectionDAG::getMachineNode(unsigned Opcode, DebugLoc dl, 4793 EVT VT1, EVT VT2, EVT VT3, 4794 SDValue Op1, SDValue Op2, SDValue Op3) { 4795 SDVTList VTs = getVTList(VT1, VT2, VT3); 4796 SDValue Ops[] = { Op1, Op2, Op3 }; 4797 return getMachineNode(Opcode, dl, VTs, Ops, array_lengthof(Ops)); 4798} 4799 4800MachineSDNode * 4801SelectionDAG::getMachineNode(unsigned Opcode, DebugLoc dl, 4802 EVT VT1, EVT VT2, EVT VT3, 4803 const SDValue *Ops, unsigned NumOps) { 4804 SDVTList VTs = getVTList(VT1, VT2, VT3); 4805 return getMachineNode(Opcode, dl, VTs, Ops, NumOps); 4806} 4807 4808MachineSDNode * 4809SelectionDAG::getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT1, 4810 EVT VT2, EVT VT3, EVT VT4, 4811 const SDValue *Ops, unsigned NumOps) { 4812 SDVTList VTs = getVTList(VT1, VT2, VT3, VT4); 4813 return getMachineNode(Opcode, dl, VTs, Ops, NumOps); 4814} 4815 4816MachineSDNode * 4817SelectionDAG::getMachineNode(unsigned Opcode, DebugLoc dl, 4818 const std::vector<EVT> &ResultTys, 4819 const SDValue *Ops, unsigned NumOps) { 4820 SDVTList VTs = getVTList(&ResultTys[0], ResultTys.size()); 4821 return getMachineNode(Opcode, dl, VTs, Ops, NumOps); 4822} 4823 4824MachineSDNode * 4825SelectionDAG::getMachineNode(unsigned Opcode, DebugLoc DL, SDVTList VTs, 4826 const SDValue *Ops, unsigned NumOps) { 4827 bool DoCSE = VTs.VTs[VTs.NumVTs-1] != MVT::Flag; 4828 MachineSDNode *N; 4829 void *IP; 4830 4831 if (DoCSE) { 4832 FoldingSetNodeID ID; 4833 AddNodeIDNode(ID, ~Opcode, VTs, Ops, NumOps); 4834 IP = 0; 4835 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 4836 return cast<MachineSDNode>(E); 4837 } 4838 4839 // Allocate a new MachineSDNode. 4840 N = NodeAllocator.Allocate<MachineSDNode>(); 4841 new (N) MachineSDNode(~Opcode, DL, VTs); 4842 4843 // Initialize the operands list. 4844 if (NumOps > array_lengthof(N->LocalOperands)) 4845 // We're creating a final node that will live unmorphed for the 4846 // remainder of the current SelectionDAG iteration, so we can allocate 4847 // the operands directly out of a pool with no recycling metadata. 4848 N->InitOperands(OperandAllocator.Allocate<SDUse>(NumOps), 4849 Ops, NumOps); 4850 else 4851 N->InitOperands(N->LocalOperands, Ops, NumOps); 4852 N->OperandsNeedDelete = false; 4853 4854 if (DoCSE) 4855 CSEMap.InsertNode(N, IP); 4856 4857 AllNodes.push_back(N); 4858#ifndef NDEBUG 4859 VerifyNode(N); 4860#endif 4861 return N; 4862} 4863 4864/// getTargetExtractSubreg - A convenience function for creating 4865/// TargetInstrInfo::EXTRACT_SUBREG nodes. 4866SDValue 4867SelectionDAG::getTargetExtractSubreg(int SRIdx, DebugLoc DL, EVT VT, 4868 SDValue Operand) { 4869 SDValue SRIdxVal = getTargetConstant(SRIdx, MVT::i32); 4870 SDNode *Subreg = getMachineNode(TargetInstrInfo::EXTRACT_SUBREG, DL, 4871 VT, Operand, SRIdxVal); 4872 return SDValue(Subreg, 0); 4873} 4874 4875/// getTargetInsertSubreg - A convenience function for creating 4876/// TargetInstrInfo::INSERT_SUBREG nodes. 4877SDValue 4878SelectionDAG::getTargetInsertSubreg(int SRIdx, DebugLoc DL, EVT VT, 4879 SDValue Operand, SDValue Subreg) { 4880 SDValue SRIdxVal = getTargetConstant(SRIdx, MVT::i32); 4881 SDNode *Result = getMachineNode(TargetInstrInfo::INSERT_SUBREG, DL, 4882 VT, Operand, Subreg, SRIdxVal); 4883 return SDValue(Result, 0); 4884} 4885 4886/// getNodeIfExists - Get the specified node if it's already available, or 4887/// else return NULL. 4888SDNode *SelectionDAG::getNodeIfExists(unsigned Opcode, SDVTList VTList, 4889 const SDValue *Ops, unsigned NumOps) { 4890 if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) { 4891 FoldingSetNodeID ID; 4892 AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps); 4893 void *IP = 0; 4894 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 4895 return E; 4896 } 4897 return NULL; 4898} 4899 4900/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. 4901/// This can cause recursive merging of nodes in the DAG. 4902/// 4903/// This version assumes From has a single result value. 4904/// 4905void SelectionDAG::ReplaceAllUsesWith(SDValue FromN, SDValue To, 4906 DAGUpdateListener *UpdateListener) { 4907 SDNode *From = FromN.getNode(); 4908 assert(From->getNumValues() == 1 && FromN.getResNo() == 0 && 4909 "Cannot replace with this method!"); 4910 assert(From != To.getNode() && "Cannot replace uses of with self"); 4911 4912 // Iterate over all the existing uses of From. New uses will be added 4913 // to the beginning of the use list, which we avoid visiting. 4914 // This specifically avoids visiting uses of From that arise while the 4915 // replacement is happening, because any such uses would be the result 4916 // of CSE: If an existing node looks like From after one of its operands 4917 // is replaced by To, we don't want to replace of all its users with To 4918 // too. See PR3018 for more info. 4919 SDNode::use_iterator UI = From->use_begin(), UE = From->use_end(); 4920 while (UI != UE) { 4921 SDNode *User = *UI; 4922 4923 // This node is about to morph, remove its old self from the CSE maps. 4924 RemoveNodeFromCSEMaps(User); 4925 4926 // A user can appear in a use list multiple times, and when this 4927 // happens the uses are usually next to each other in the list. 4928 // To help reduce the number of CSE recomputations, process all 4929 // the uses of this user that we can find this way. 4930 do { 4931 SDUse &Use = UI.getUse(); 4932 ++UI; 4933 Use.set(To); 4934 } while (UI != UE && *UI == User); 4935 4936 // Now that we have modified User, add it back to the CSE maps. If it 4937 // already exists there, recursively merge the results together. 4938 AddModifiedNodeToCSEMaps(User, UpdateListener); 4939 } 4940} 4941 4942/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. 4943/// This can cause recursive merging of nodes in the DAG. 4944/// 4945/// This version assumes that for each value of From, there is a 4946/// corresponding value in To in the same position with the same type. 4947/// 4948void SelectionDAG::ReplaceAllUsesWith(SDNode *From, SDNode *To, 4949 DAGUpdateListener *UpdateListener) { 4950#ifndef NDEBUG 4951 for (unsigned i = 0, e = From->getNumValues(); i != e; ++i) 4952 assert((!From->hasAnyUseOfValue(i) || 4953 From->getValueType(i) == To->getValueType(i)) && 4954 "Cannot use this version of ReplaceAllUsesWith!"); 4955#endif 4956 4957 // Handle the trivial case. 4958 if (From == To) 4959 return; 4960 4961 // Iterate over just the existing users of From. See the comments in 4962 // the ReplaceAllUsesWith above. 4963 SDNode::use_iterator UI = From->use_begin(), UE = From->use_end(); 4964 while (UI != UE) { 4965 SDNode *User = *UI; 4966 4967 // This node is about to morph, remove its old self from the CSE maps. 4968 RemoveNodeFromCSEMaps(User); 4969 4970 // A user can appear in a use list multiple times, and when this 4971 // happens the uses are usually next to each other in the list. 4972 // To help reduce the number of CSE recomputations, process all 4973 // the uses of this user that we can find this way. 4974 do { 4975 SDUse &Use = UI.getUse(); 4976 ++UI; 4977 Use.setNode(To); 4978 } while (UI != UE && *UI == User); 4979 4980 // Now that we have modified User, add it back to the CSE maps. If it 4981 // already exists there, recursively merge the results together. 4982 AddModifiedNodeToCSEMaps(User, UpdateListener); 4983 } 4984} 4985 4986/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. 4987/// This can cause recursive merging of nodes in the DAG. 4988/// 4989/// This version can replace From with any result values. To must match the 4990/// number and types of values returned by From. 4991void SelectionDAG::ReplaceAllUsesWith(SDNode *From, 4992 const SDValue *To, 4993 DAGUpdateListener *UpdateListener) { 4994 if (From->getNumValues() == 1) // Handle the simple case efficiently. 4995 return ReplaceAllUsesWith(SDValue(From, 0), To[0], UpdateListener); 4996 4997 // Iterate over just the existing users of From. See the comments in 4998 // the ReplaceAllUsesWith above. 4999 SDNode::use_iterator UI = From->use_begin(), UE = From->use_end(); 5000 while (UI != UE) { 5001 SDNode *User = *UI; 5002 5003 // This node is about to morph, remove its old self from the CSE maps. 5004 RemoveNodeFromCSEMaps(User); 5005 5006 // A user can appear in a use list multiple times, and when this 5007 // happens the uses are usually next to each other in the list. 5008 // To help reduce the number of CSE recomputations, process all 5009 // the uses of this user that we can find this way. 5010 do { 5011 SDUse &Use = UI.getUse(); 5012 const SDValue &ToOp = To[Use.getResNo()]; 5013 ++UI; 5014 Use.set(ToOp); 5015 } while (UI != UE && *UI == User); 5016 5017 // Now that we have modified User, add it back to the CSE maps. If it 5018 // already exists there, recursively merge the results together. 5019 AddModifiedNodeToCSEMaps(User, UpdateListener); 5020 } 5021} 5022 5023/// ReplaceAllUsesOfValueWith - Replace any uses of From with To, leaving 5024/// uses of other values produced by From.getNode() alone. The Deleted 5025/// vector is handled the same way as for ReplaceAllUsesWith. 5026void SelectionDAG::ReplaceAllUsesOfValueWith(SDValue From, SDValue To, 5027 DAGUpdateListener *UpdateListener){ 5028 // Handle the really simple, really trivial case efficiently. 5029 if (From == To) return; 5030 5031 // Handle the simple, trivial, case efficiently. 5032 if (From.getNode()->getNumValues() == 1) { 5033 ReplaceAllUsesWith(From, To, UpdateListener); 5034 return; 5035 } 5036 5037 // Iterate over just the existing users of From. See the comments in 5038 // the ReplaceAllUsesWith above. 5039 SDNode::use_iterator UI = From.getNode()->use_begin(), 5040 UE = From.getNode()->use_end(); 5041 while (UI != UE) { 5042 SDNode *User = *UI; 5043 bool UserRemovedFromCSEMaps = false; 5044 5045 // A user can appear in a use list multiple times, and when this 5046 // happens the uses are usually next to each other in the list. 5047 // To help reduce the number of CSE recomputations, process all 5048 // the uses of this user that we can find this way. 5049 do { 5050 SDUse &Use = UI.getUse(); 5051 5052 // Skip uses of different values from the same node. 5053 if (Use.getResNo() != From.getResNo()) { 5054 ++UI; 5055 continue; 5056 } 5057 5058 // If this node hasn't been modified yet, it's still in the CSE maps, 5059 // so remove its old self from the CSE maps. 5060 if (!UserRemovedFromCSEMaps) { 5061 RemoveNodeFromCSEMaps(User); 5062 UserRemovedFromCSEMaps = true; 5063 } 5064 5065 ++UI; 5066 Use.set(To); 5067 } while (UI != UE && *UI == User); 5068 5069 // We are iterating over all uses of the From node, so if a use 5070 // doesn't use the specific value, no changes are made. 5071 if (!UserRemovedFromCSEMaps) 5072 continue; 5073 5074 // Now that we have modified User, add it back to the CSE maps. If it 5075 // already exists there, recursively merge the results together. 5076 AddModifiedNodeToCSEMaps(User, UpdateListener); 5077 } 5078} 5079 5080namespace { 5081 /// UseMemo - This class is used by SelectionDAG::ReplaceAllUsesOfValuesWith 5082 /// to record information about a use. 5083 struct UseMemo { 5084 SDNode *User; 5085 unsigned Index; 5086 SDUse *Use; 5087 }; 5088 5089 /// operator< - Sort Memos by User. 5090 bool operator<(const UseMemo &L, const UseMemo &R) { 5091 return (intptr_t)L.User < (intptr_t)R.User; 5092 } 5093} 5094 5095/// ReplaceAllUsesOfValuesWith - Replace any uses of From with To, leaving 5096/// uses of other values produced by From.getNode() alone. The same value 5097/// may appear in both the From and To list. The Deleted vector is 5098/// handled the same way as for ReplaceAllUsesWith. 5099void SelectionDAG::ReplaceAllUsesOfValuesWith(const SDValue *From, 5100 const SDValue *To, 5101 unsigned Num, 5102 DAGUpdateListener *UpdateListener){ 5103 // Handle the simple, trivial case efficiently. 5104 if (Num == 1) 5105 return ReplaceAllUsesOfValueWith(*From, *To, UpdateListener); 5106 5107 // Read up all the uses and make records of them. This helps 5108 // processing new uses that are introduced during the 5109 // replacement process. 5110 SmallVector<UseMemo, 4> Uses; 5111 for (unsigned i = 0; i != Num; ++i) { 5112 unsigned FromResNo = From[i].getResNo(); 5113 SDNode *FromNode = From[i].getNode(); 5114 for (SDNode::use_iterator UI = FromNode->use_begin(), 5115 E = FromNode->use_end(); UI != E; ++UI) { 5116 SDUse &Use = UI.getUse(); 5117 if (Use.getResNo() == FromResNo) { 5118 UseMemo Memo = { *UI, i, &Use }; 5119 Uses.push_back(Memo); 5120 } 5121 } 5122 } 5123 5124 // Sort the uses, so that all the uses from a given User are together. 5125 std::sort(Uses.begin(), Uses.end()); 5126 5127 for (unsigned UseIndex = 0, UseIndexEnd = Uses.size(); 5128 UseIndex != UseIndexEnd; ) { 5129 // We know that this user uses some value of From. If it is the right 5130 // value, update it. 5131 SDNode *User = Uses[UseIndex].User; 5132 5133 // This node is about to morph, remove its old self from the CSE maps. 5134 RemoveNodeFromCSEMaps(User); 5135 5136 // The Uses array is sorted, so all the uses for a given User 5137 // are next to each other in the list. 5138 // To help reduce the number of CSE recomputations, process all 5139 // the uses of this user that we can find this way. 5140 do { 5141 unsigned i = Uses[UseIndex].Index; 5142 SDUse &Use = *Uses[UseIndex].Use; 5143 ++UseIndex; 5144 5145 Use.set(To[i]); 5146 } while (UseIndex != UseIndexEnd && Uses[UseIndex].User == User); 5147 5148 // Now that we have modified User, add it back to the CSE maps. If it 5149 // already exists there, recursively merge the results together. 5150 AddModifiedNodeToCSEMaps(User, UpdateListener); 5151 } 5152} 5153 5154/// AssignTopologicalOrder - Assign a unique node id for each node in the DAG 5155/// based on their topological order. It returns the maximum id and a vector 5156/// of the SDNodes* in assigned order by reference. 5157unsigned SelectionDAG::AssignTopologicalOrder() { 5158 5159 unsigned DAGSize = 0; 5160 5161 // SortedPos tracks the progress of the algorithm. Nodes before it are 5162 // sorted, nodes after it are unsorted. When the algorithm completes 5163 // it is at the end of the list. 5164 allnodes_iterator SortedPos = allnodes_begin(); 5165 5166 // Visit all the nodes. Move nodes with no operands to the front of 5167 // the list immediately. Annotate nodes that do have operands with their 5168 // operand count. Before we do this, the Node Id fields of the nodes 5169 // may contain arbitrary values. After, the Node Id fields for nodes 5170 // before SortedPos will contain the topological sort index, and the 5171 // Node Id fields for nodes At SortedPos and after will contain the 5172 // count of outstanding operands. 5173 for (allnodes_iterator I = allnodes_begin(),E = allnodes_end(); I != E; ) { 5174 SDNode *N = I++; 5175 unsigned Degree = N->getNumOperands(); 5176 if (Degree == 0) { 5177 // A node with no uses, add it to the result array immediately. 5178 N->setNodeId(DAGSize++); 5179 allnodes_iterator Q = N; 5180 if (Q != SortedPos) 5181 SortedPos = AllNodes.insert(SortedPos, AllNodes.remove(Q)); 5182 ++SortedPos; 5183 } else { 5184 // Temporarily use the Node Id as scratch space for the degree count. 5185 N->setNodeId(Degree); 5186 } 5187 } 5188 5189 // Visit all the nodes. As we iterate, moves nodes into sorted order, 5190 // such that by the time the end is reached all nodes will be sorted. 5191 for (allnodes_iterator I = allnodes_begin(),E = allnodes_end(); I != E; ++I) { 5192 SDNode *N = I; 5193 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 5194 UI != UE; ++UI) { 5195 SDNode *P = *UI; 5196 unsigned Degree = P->getNodeId(); 5197 --Degree; 5198 if (Degree == 0) { 5199 // All of P's operands are sorted, so P may sorted now. 5200 P->setNodeId(DAGSize++); 5201 if (P != SortedPos) 5202 SortedPos = AllNodes.insert(SortedPos, AllNodes.remove(P)); 5203 ++SortedPos; 5204 } else { 5205 // Update P's outstanding operand count. 5206 P->setNodeId(Degree); 5207 } 5208 } 5209 } 5210 5211 assert(SortedPos == AllNodes.end() && 5212 "Topological sort incomplete!"); 5213 assert(AllNodes.front().getOpcode() == ISD::EntryToken && 5214 "First node in topological sort is not the entry token!"); 5215 assert(AllNodes.front().getNodeId() == 0 && 5216 "First node in topological sort has non-zero id!"); 5217 assert(AllNodes.front().getNumOperands() == 0 && 5218 "First node in topological sort has operands!"); 5219 assert(AllNodes.back().getNodeId() == (int)DAGSize-1 && 5220 "Last node in topologic sort has unexpected id!"); 5221 assert(AllNodes.back().use_empty() && 5222 "Last node in topologic sort has users!"); 5223 assert(DAGSize == allnodes_size() && "Node count mismatch!"); 5224 return DAGSize; 5225} 5226 5227/// AssignOrdering - Assign an order to the SDNode. 5228void SelectionDAG::AssignOrdering(SDNode *SD, unsigned Order) { 5229 assert(SD && "Trying to assign an order to a null node!"); 5230 if (Ordering) 5231 Ordering->add(SD, Order); 5232} 5233 5234/// GetOrdering - Get the order for the SDNode. 5235unsigned SelectionDAG::GetOrdering(const SDNode *SD) const { 5236 assert(SD && "Trying to get the order of a null node!"); 5237 return Ordering ? Ordering->getOrder(SD) : 0; 5238} 5239 5240 5241//===----------------------------------------------------------------------===// 5242// SDNode Class 5243//===----------------------------------------------------------------------===// 5244 5245HandleSDNode::~HandleSDNode() { 5246 DropOperands(); 5247} 5248 5249GlobalAddressSDNode::GlobalAddressSDNode(unsigned Opc, const GlobalValue *GA, 5250 EVT VT, int64_t o, unsigned char TF) 5251 : SDNode(Opc, DebugLoc::getUnknownLoc(), getSDVTList(VT)), 5252 Offset(o), TargetFlags(TF) { 5253 TheGlobal = const_cast<GlobalValue*>(GA); 5254} 5255 5256MemSDNode::MemSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, EVT memvt, 5257 MachineMemOperand *mmo) 5258 : SDNode(Opc, dl, VTs), MemoryVT(memvt), MMO(mmo) { 5259 SubclassData = encodeMemSDNodeFlags(0, ISD::UNINDEXED, MMO->isVolatile()); 5260 assert(isVolatile() == MMO->isVolatile() && "Volatile encoding error!"); 5261 assert(memvt.getStoreSize() == MMO->getSize() && "Size mismatch!"); 5262} 5263 5264MemSDNode::MemSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, 5265 const SDValue *Ops, unsigned NumOps, EVT memvt, 5266 MachineMemOperand *mmo) 5267 : SDNode(Opc, dl, VTs, Ops, NumOps), 5268 MemoryVT(memvt), MMO(mmo) { 5269 SubclassData = encodeMemSDNodeFlags(0, ISD::UNINDEXED, MMO->isVolatile()); 5270 assert(isVolatile() == MMO->isVolatile() && "Volatile encoding error!"); 5271 assert(memvt.getStoreSize() == MMO->getSize() && "Size mismatch!"); 5272} 5273 5274/// Profile - Gather unique data for the node. 5275/// 5276void SDNode::Profile(FoldingSetNodeID &ID) const { 5277 AddNodeIDNode(ID, this); 5278} 5279 5280namespace { 5281 struct EVTArray { 5282 std::vector<EVT> VTs; 5283 5284 EVTArray() { 5285 VTs.reserve(MVT::LAST_VALUETYPE); 5286 for (unsigned i = 0; i < MVT::LAST_VALUETYPE; ++i) 5287 VTs.push_back(MVT((MVT::SimpleValueType)i)); 5288 } 5289 }; 5290} 5291 5292static ManagedStatic<std::set<EVT, EVT::compareRawBits> > EVTs; 5293static ManagedStatic<EVTArray> SimpleVTArray; 5294static ManagedStatic<sys::SmartMutex<true> > VTMutex; 5295 5296/// getValueTypeList - Return a pointer to the specified value type. 5297/// 5298const EVT *SDNode::getValueTypeList(EVT VT) { 5299 if (VT.isExtended()) { 5300 sys::SmartScopedLock<true> Lock(*VTMutex); 5301 return &(*EVTs->insert(VT).first); 5302 } else { 5303 return &SimpleVTArray->VTs[VT.getSimpleVT().SimpleTy]; 5304 } 5305} 5306 5307/// hasNUsesOfValue - Return true if there are exactly NUSES uses of the 5308/// indicated value. This method ignores uses of other values defined by this 5309/// operation. 5310bool SDNode::hasNUsesOfValue(unsigned NUses, unsigned Value) const { 5311 assert(Value < getNumValues() && "Bad value!"); 5312 5313 // TODO: Only iterate over uses of a given value of the node 5314 for (SDNode::use_iterator UI = use_begin(), E = use_end(); UI != E; ++UI) { 5315 if (UI.getUse().getResNo() == Value) { 5316 if (NUses == 0) 5317 return false; 5318 --NUses; 5319 } 5320 } 5321 5322 // Found exactly the right number of uses? 5323 return NUses == 0; 5324} 5325 5326 5327/// hasAnyUseOfValue - Return true if there are any use of the indicated 5328/// value. This method ignores uses of other values defined by this operation. 5329bool SDNode::hasAnyUseOfValue(unsigned Value) const { 5330 assert(Value < getNumValues() && "Bad value!"); 5331 5332 for (SDNode::use_iterator UI = use_begin(), E = use_end(); UI != E; ++UI) 5333 if (UI.getUse().getResNo() == Value) 5334 return true; 5335 5336 return false; 5337} 5338 5339 5340/// isOnlyUserOf - Return true if this node is the only use of N. 5341/// 5342bool SDNode::isOnlyUserOf(SDNode *N) const { 5343 bool Seen = false; 5344 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 5345 SDNode *User = *I; 5346 if (User == this) 5347 Seen = true; 5348 else 5349 return false; 5350 } 5351 5352 return Seen; 5353} 5354 5355/// isOperand - Return true if this node is an operand of N. 5356/// 5357bool SDValue::isOperandOf(SDNode *N) const { 5358 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 5359 if (*this == N->getOperand(i)) 5360 return true; 5361 return false; 5362} 5363 5364bool SDNode::isOperandOf(SDNode *N) const { 5365 for (unsigned i = 0, e = N->NumOperands; i != e; ++i) 5366 if (this == N->OperandList[i].getNode()) 5367 return true; 5368 return false; 5369} 5370 5371/// reachesChainWithoutSideEffects - Return true if this operand (which must 5372/// be a chain) reaches the specified operand without crossing any 5373/// side-effecting instructions. In practice, this looks through token 5374/// factors and non-volatile loads. In order to remain efficient, this only 5375/// looks a couple of nodes in, it does not do an exhaustive search. 5376bool SDValue::reachesChainWithoutSideEffects(SDValue Dest, 5377 unsigned Depth) const { 5378 if (*this == Dest) return true; 5379 5380 // Don't search too deeply, we just want to be able to see through 5381 // TokenFactor's etc. 5382 if (Depth == 0) return false; 5383 5384 // If this is a token factor, all inputs to the TF happen in parallel. If any 5385 // of the operands of the TF reach dest, then we can do the xform. 5386 if (getOpcode() == ISD::TokenFactor) { 5387 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) 5388 if (getOperand(i).reachesChainWithoutSideEffects(Dest, Depth-1)) 5389 return true; 5390 return false; 5391 } 5392 5393 // Loads don't have side effects, look through them. 5394 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(*this)) { 5395 if (!Ld->isVolatile()) 5396 return Ld->getChain().reachesChainWithoutSideEffects(Dest, Depth-1); 5397 } 5398 return false; 5399} 5400 5401/// isPredecessorOf - Return true if this node is a predecessor of N. This node 5402/// is either an operand of N or it can be reached by traversing up the operands. 5403/// NOTE: this is an expensive method. Use it carefully. 5404bool SDNode::isPredecessorOf(SDNode *N) const { 5405 SmallPtrSet<SDNode *, 32> Visited; 5406 SmallVector<SDNode *, 16> Worklist; 5407 Worklist.push_back(N); 5408 5409 do { 5410 N = Worklist.pop_back_val(); 5411 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 5412 SDNode *Op = N->getOperand(i).getNode(); 5413 if (Op == this) 5414 return true; 5415 if (Visited.insert(Op)) 5416 Worklist.push_back(Op); 5417 } 5418 } while (!Worklist.empty()); 5419 5420 return false; 5421} 5422 5423uint64_t SDNode::getConstantOperandVal(unsigned Num) const { 5424 assert(Num < NumOperands && "Invalid child # of SDNode!"); 5425 return cast<ConstantSDNode>(OperandList[Num])->getZExtValue(); 5426} 5427 5428std::string SDNode::getOperationName(const SelectionDAG *G) const { 5429 switch (getOpcode()) { 5430 default: 5431 if (getOpcode() < ISD::BUILTIN_OP_END) 5432 return "<<Unknown DAG Node>>"; 5433 if (isMachineOpcode()) { 5434 if (G) 5435 if (const TargetInstrInfo *TII = G->getTarget().getInstrInfo()) 5436 if (getMachineOpcode() < TII->getNumOpcodes()) 5437 return TII->get(getMachineOpcode()).getName(); 5438 return "<<Unknown Machine Node>>"; 5439 } 5440 if (G) { 5441 const TargetLowering &TLI = G->getTargetLoweringInfo(); 5442 const char *Name = TLI.getTargetNodeName(getOpcode()); 5443 if (Name) return Name; 5444 return "<<Unknown Target Node>>"; 5445 } 5446 return "<<Unknown Node>>"; 5447 5448#ifndef NDEBUG 5449 case ISD::DELETED_NODE: 5450 return "<<Deleted Node!>>"; 5451#endif 5452 case ISD::PREFETCH: return "Prefetch"; 5453 case ISD::MEMBARRIER: return "MemBarrier"; 5454 case ISD::ATOMIC_CMP_SWAP: return "AtomicCmpSwap"; 5455 case ISD::ATOMIC_SWAP: return "AtomicSwap"; 5456 case ISD::ATOMIC_LOAD_ADD: return "AtomicLoadAdd"; 5457 case ISD::ATOMIC_LOAD_SUB: return "AtomicLoadSub"; 5458 case ISD::ATOMIC_LOAD_AND: return "AtomicLoadAnd"; 5459 case ISD::ATOMIC_LOAD_OR: return "AtomicLoadOr"; 5460 case ISD::ATOMIC_LOAD_XOR: return "AtomicLoadXor"; 5461 case ISD::ATOMIC_LOAD_NAND: return "AtomicLoadNand"; 5462 case ISD::ATOMIC_LOAD_MIN: return "AtomicLoadMin"; 5463 case ISD::ATOMIC_LOAD_MAX: return "AtomicLoadMax"; 5464 case ISD::ATOMIC_LOAD_UMIN: return "AtomicLoadUMin"; 5465 case ISD::ATOMIC_LOAD_UMAX: return "AtomicLoadUMax"; 5466 case ISD::PCMARKER: return "PCMarker"; 5467 case ISD::READCYCLECOUNTER: return "ReadCycleCounter"; 5468 case ISD::SRCVALUE: return "SrcValue"; 5469 case ISD::EntryToken: return "EntryToken"; 5470 case ISD::TokenFactor: return "TokenFactor"; 5471 case ISD::AssertSext: return "AssertSext"; 5472 case ISD::AssertZext: return "AssertZext"; 5473 5474 case ISD::BasicBlock: return "BasicBlock"; 5475 case ISD::VALUETYPE: return "ValueType"; 5476 case ISD::Register: return "Register"; 5477 5478 case ISD::Constant: return "Constant"; 5479 case ISD::ConstantFP: return "ConstantFP"; 5480 case ISD::GlobalAddress: return "GlobalAddress"; 5481 case ISD::GlobalTLSAddress: return "GlobalTLSAddress"; 5482 case ISD::FrameIndex: return "FrameIndex"; 5483 case ISD::JumpTable: return "JumpTable"; 5484 case ISD::GLOBAL_OFFSET_TABLE: return "GLOBAL_OFFSET_TABLE"; 5485 case ISD::RETURNADDR: return "RETURNADDR"; 5486 case ISD::FRAMEADDR: return "FRAMEADDR"; 5487 case ISD::FRAME_TO_ARGS_OFFSET: return "FRAME_TO_ARGS_OFFSET"; 5488 case ISD::EXCEPTIONADDR: return "EXCEPTIONADDR"; 5489 case ISD::LSDAADDR: return "LSDAADDR"; 5490 case ISD::EHSELECTION: return "EHSELECTION"; 5491 case ISD::EH_RETURN: return "EH_RETURN"; 5492 case ISD::ConstantPool: return "ConstantPool"; 5493 case ISD::ExternalSymbol: return "ExternalSymbol"; 5494 case ISD::BlockAddress: return "BlockAddress"; 5495 case ISD::INTRINSIC_WO_CHAIN: 5496 case ISD::INTRINSIC_VOID: 5497 case ISD::INTRINSIC_W_CHAIN: { 5498 unsigned OpNo = getOpcode() == ISD::INTRINSIC_WO_CHAIN ? 0 : 1; 5499 unsigned IID = cast<ConstantSDNode>(getOperand(OpNo))->getZExtValue(); 5500 if (IID < Intrinsic::num_intrinsics) 5501 return Intrinsic::getName((Intrinsic::ID)IID); 5502 else if (const TargetIntrinsicInfo *TII = G->getTarget().getIntrinsicInfo()) 5503 return TII->getName(IID); 5504 llvm_unreachable("Invalid intrinsic ID"); 5505 } 5506 5507 case ISD::BUILD_VECTOR: return "BUILD_VECTOR"; 5508 case ISD::TargetConstant: return "TargetConstant"; 5509 case ISD::TargetConstantFP:return "TargetConstantFP"; 5510 case ISD::TargetGlobalAddress: return "TargetGlobalAddress"; 5511 case ISD::TargetGlobalTLSAddress: return "TargetGlobalTLSAddress"; 5512 case ISD::TargetFrameIndex: return "TargetFrameIndex"; 5513 case ISD::TargetJumpTable: return "TargetJumpTable"; 5514 case ISD::TargetConstantPool: return "TargetConstantPool"; 5515 case ISD::TargetExternalSymbol: return "TargetExternalSymbol"; 5516 case ISD::TargetBlockAddress: return "TargetBlockAddress"; 5517 5518 case ISD::CopyToReg: return "CopyToReg"; 5519 case ISD::CopyFromReg: return "CopyFromReg"; 5520 case ISD::UNDEF: return "undef"; 5521 case ISD::MERGE_VALUES: return "merge_values"; 5522 case ISD::INLINEASM: return "inlineasm"; 5523 case ISD::EH_LABEL: return "eh_label"; 5524 case ISD::HANDLENODE: return "handlenode"; 5525 5526 // Unary operators 5527 case ISD::FABS: return "fabs"; 5528 case ISD::FNEG: return "fneg"; 5529 case ISD::FSQRT: return "fsqrt"; 5530 case ISD::FSIN: return "fsin"; 5531 case ISD::FCOS: return "fcos"; 5532 case ISD::FPOWI: return "fpowi"; 5533 case ISD::FPOW: return "fpow"; 5534 case ISD::FTRUNC: return "ftrunc"; 5535 case ISD::FFLOOR: return "ffloor"; 5536 case ISD::FCEIL: return "fceil"; 5537 case ISD::FRINT: return "frint"; 5538 case ISD::FNEARBYINT: return "fnearbyint"; 5539 5540 // Binary operators 5541 case ISD::ADD: return "add"; 5542 case ISD::SUB: return "sub"; 5543 case ISD::MUL: return "mul"; 5544 case ISD::MULHU: return "mulhu"; 5545 case ISD::MULHS: return "mulhs"; 5546 case ISD::SDIV: return "sdiv"; 5547 case ISD::UDIV: return "udiv"; 5548 case ISD::SREM: return "srem"; 5549 case ISD::UREM: return "urem"; 5550 case ISD::SMUL_LOHI: return "smul_lohi"; 5551 case ISD::UMUL_LOHI: return "umul_lohi"; 5552 case ISD::SDIVREM: return "sdivrem"; 5553 case ISD::UDIVREM: return "udivrem"; 5554 case ISD::AND: return "and"; 5555 case ISD::OR: return "or"; 5556 case ISD::XOR: return "xor"; 5557 case ISD::SHL: return "shl"; 5558 case ISD::SRA: return "sra"; 5559 case ISD::SRL: return "srl"; 5560 case ISD::ROTL: return "rotl"; 5561 case ISD::ROTR: return "rotr"; 5562 case ISD::FADD: return "fadd"; 5563 case ISD::FSUB: return "fsub"; 5564 case ISD::FMUL: return "fmul"; 5565 case ISD::FDIV: return "fdiv"; 5566 case ISD::FREM: return "frem"; 5567 case ISD::FCOPYSIGN: return "fcopysign"; 5568 case ISD::FGETSIGN: return "fgetsign"; 5569 5570 case ISD::SETCC: return "setcc"; 5571 case ISD::VSETCC: return "vsetcc"; 5572 case ISD::SELECT: return "select"; 5573 case ISD::SELECT_CC: return "select_cc"; 5574 case ISD::INSERT_VECTOR_ELT: return "insert_vector_elt"; 5575 case ISD::EXTRACT_VECTOR_ELT: return "extract_vector_elt"; 5576 case ISD::CONCAT_VECTORS: return "concat_vectors"; 5577 case ISD::EXTRACT_SUBVECTOR: return "extract_subvector"; 5578 case ISD::SCALAR_TO_VECTOR: return "scalar_to_vector"; 5579 case ISD::VECTOR_SHUFFLE: return "vector_shuffle"; 5580 case ISD::CARRY_FALSE: return "carry_false"; 5581 case ISD::ADDC: return "addc"; 5582 case ISD::ADDE: return "adde"; 5583 case ISD::SADDO: return "saddo"; 5584 case ISD::UADDO: return "uaddo"; 5585 case ISD::SSUBO: return "ssubo"; 5586 case ISD::USUBO: return "usubo"; 5587 case ISD::SMULO: return "smulo"; 5588 case ISD::UMULO: return "umulo"; 5589 case ISD::SUBC: return "subc"; 5590 case ISD::SUBE: return "sube"; 5591 case ISD::SHL_PARTS: return "shl_parts"; 5592 case ISD::SRA_PARTS: return "sra_parts"; 5593 case ISD::SRL_PARTS: return "srl_parts"; 5594 5595 // Conversion operators. 5596 case ISD::SIGN_EXTEND: return "sign_extend"; 5597 case ISD::ZERO_EXTEND: return "zero_extend"; 5598 case ISD::ANY_EXTEND: return "any_extend"; 5599 case ISD::SIGN_EXTEND_INREG: return "sign_extend_inreg"; 5600 case ISD::TRUNCATE: return "truncate"; 5601 case ISD::FP_ROUND: return "fp_round"; 5602 case ISD::FLT_ROUNDS_: return "flt_rounds"; 5603 case ISD::FP_ROUND_INREG: return "fp_round_inreg"; 5604 case ISD::FP_EXTEND: return "fp_extend"; 5605 5606 case ISD::SINT_TO_FP: return "sint_to_fp"; 5607 case ISD::UINT_TO_FP: return "uint_to_fp"; 5608 case ISD::FP_TO_SINT: return "fp_to_sint"; 5609 case ISD::FP_TO_UINT: return "fp_to_uint"; 5610 case ISD::BIT_CONVERT: return "bit_convert"; 5611 5612 case ISD::CONVERT_RNDSAT: { 5613 switch (cast<CvtRndSatSDNode>(this)->getCvtCode()) { 5614 default: llvm_unreachable("Unknown cvt code!"); 5615 case ISD::CVT_FF: return "cvt_ff"; 5616 case ISD::CVT_FS: return "cvt_fs"; 5617 case ISD::CVT_FU: return "cvt_fu"; 5618 case ISD::CVT_SF: return "cvt_sf"; 5619 case ISD::CVT_UF: return "cvt_uf"; 5620 case ISD::CVT_SS: return "cvt_ss"; 5621 case ISD::CVT_SU: return "cvt_su"; 5622 case ISD::CVT_US: return "cvt_us"; 5623 case ISD::CVT_UU: return "cvt_uu"; 5624 } 5625 } 5626 5627 // Control flow instructions 5628 case ISD::BR: return "br"; 5629 case ISD::BRIND: return "brind"; 5630 case ISD::BR_JT: return "br_jt"; 5631 case ISD::BRCOND: return "brcond"; 5632 case ISD::BR_CC: return "br_cc"; 5633 case ISD::CALLSEQ_START: return "callseq_start"; 5634 case ISD::CALLSEQ_END: return "callseq_end"; 5635 5636 // Other operators 5637 case ISD::LOAD: return "load"; 5638 case ISD::STORE: return "store"; 5639 case ISD::VAARG: return "vaarg"; 5640 case ISD::VACOPY: return "vacopy"; 5641 case ISD::VAEND: return "vaend"; 5642 case ISD::VASTART: return "vastart"; 5643 case ISD::DYNAMIC_STACKALLOC: return "dynamic_stackalloc"; 5644 case ISD::EXTRACT_ELEMENT: return "extract_element"; 5645 case ISD::BUILD_PAIR: return "build_pair"; 5646 case ISD::STACKSAVE: return "stacksave"; 5647 case ISD::STACKRESTORE: return "stackrestore"; 5648 case ISD::TRAP: return "trap"; 5649 5650 // Bit manipulation 5651 case ISD::BSWAP: return "bswap"; 5652 case ISD::CTPOP: return "ctpop"; 5653 case ISD::CTTZ: return "cttz"; 5654 case ISD::CTLZ: return "ctlz"; 5655 5656 // Trampolines 5657 case ISD::TRAMPOLINE: return "trampoline"; 5658 5659 case ISD::CONDCODE: 5660 switch (cast<CondCodeSDNode>(this)->get()) { 5661 default: llvm_unreachable("Unknown setcc condition!"); 5662 case ISD::SETOEQ: return "setoeq"; 5663 case ISD::SETOGT: return "setogt"; 5664 case ISD::SETOGE: return "setoge"; 5665 case ISD::SETOLT: return "setolt"; 5666 case ISD::SETOLE: return "setole"; 5667 case ISD::SETONE: return "setone"; 5668 5669 case ISD::SETO: return "seto"; 5670 case ISD::SETUO: return "setuo"; 5671 case ISD::SETUEQ: return "setue"; 5672 case ISD::SETUGT: return "setugt"; 5673 case ISD::SETUGE: return "setuge"; 5674 case ISD::SETULT: return "setult"; 5675 case ISD::SETULE: return "setule"; 5676 case ISD::SETUNE: return "setune"; 5677 5678 case ISD::SETEQ: return "seteq"; 5679 case ISD::SETGT: return "setgt"; 5680 case ISD::SETGE: return "setge"; 5681 case ISD::SETLT: return "setlt"; 5682 case ISD::SETLE: return "setle"; 5683 case ISD::SETNE: return "setne"; 5684 } 5685 } 5686} 5687 5688const char *SDNode::getIndexedModeName(ISD::MemIndexedMode AM) { 5689 switch (AM) { 5690 default: 5691 return ""; 5692 case ISD::PRE_INC: 5693 return "<pre-inc>"; 5694 case ISD::PRE_DEC: 5695 return "<pre-dec>"; 5696 case ISD::POST_INC: 5697 return "<post-inc>"; 5698 case ISD::POST_DEC: 5699 return "<post-dec>"; 5700 } 5701} 5702 5703std::string ISD::ArgFlagsTy::getArgFlagsString() { 5704 std::string S = "< "; 5705 5706 if (isZExt()) 5707 S += "zext "; 5708 if (isSExt()) 5709 S += "sext "; 5710 if (isInReg()) 5711 S += "inreg "; 5712 if (isSRet()) 5713 S += "sret "; 5714 if (isByVal()) 5715 S += "byval "; 5716 if (isNest()) 5717 S += "nest "; 5718 if (getByValAlign()) 5719 S += "byval-align:" + utostr(getByValAlign()) + " "; 5720 if (getOrigAlign()) 5721 S += "orig-align:" + utostr(getOrigAlign()) + " "; 5722 if (getByValSize()) 5723 S += "byval-size:" + utostr(getByValSize()) + " "; 5724 return S + ">"; 5725} 5726 5727void SDNode::dump() const { dump(0); } 5728void SDNode::dump(const SelectionDAG *G) const { 5729 print(dbgs(), G); 5730} 5731 5732void SDNode::print_types(raw_ostream &OS, const SelectionDAG *G) const { 5733 OS << (void*)this << ": "; 5734 5735 for (unsigned i = 0, e = getNumValues(); i != e; ++i) { 5736 if (i) OS << ","; 5737 if (getValueType(i) == MVT::Other) 5738 OS << "ch"; 5739 else 5740 OS << getValueType(i).getEVTString(); 5741 } 5742 OS << " = " << getOperationName(G); 5743} 5744 5745void SDNode::print_details(raw_ostream &OS, const SelectionDAG *G) const { 5746 if (const MachineSDNode *MN = dyn_cast<MachineSDNode>(this)) { 5747 if (!MN->memoperands_empty()) { 5748 OS << "<"; 5749 OS << "Mem:"; 5750 for (MachineSDNode::mmo_iterator i = MN->memoperands_begin(), 5751 e = MN->memoperands_end(); i != e; ++i) { 5752 OS << **i; 5753 if (next(i) != e) 5754 OS << " "; 5755 } 5756 OS << ">"; 5757 } 5758 } else if (const ShuffleVectorSDNode *SVN = 5759 dyn_cast<ShuffleVectorSDNode>(this)) { 5760 OS << "<"; 5761 for (unsigned i = 0, e = ValueList[0].getVectorNumElements(); i != e; ++i) { 5762 int Idx = SVN->getMaskElt(i); 5763 if (i) OS << ","; 5764 if (Idx < 0) 5765 OS << "u"; 5766 else 5767 OS << Idx; 5768 } 5769 OS << ">"; 5770 } else if (const ConstantSDNode *CSDN = dyn_cast<ConstantSDNode>(this)) { 5771 OS << '<' << CSDN->getAPIntValue() << '>'; 5772 } else if (const ConstantFPSDNode *CSDN = dyn_cast<ConstantFPSDNode>(this)) { 5773 if (&CSDN->getValueAPF().getSemantics()==&APFloat::IEEEsingle) 5774 OS << '<' << CSDN->getValueAPF().convertToFloat() << '>'; 5775 else if (&CSDN->getValueAPF().getSemantics()==&APFloat::IEEEdouble) 5776 OS << '<' << CSDN->getValueAPF().convertToDouble() << '>'; 5777 else { 5778 OS << "<APFloat("; 5779 CSDN->getValueAPF().bitcastToAPInt().dump(); 5780 OS << ")>"; 5781 } 5782 } else if (const GlobalAddressSDNode *GADN = 5783 dyn_cast<GlobalAddressSDNode>(this)) { 5784 int64_t offset = GADN->getOffset(); 5785 OS << '<'; 5786 WriteAsOperand(OS, GADN->getGlobal()); 5787 OS << '>'; 5788 if (offset > 0) 5789 OS << " + " << offset; 5790 else 5791 OS << " " << offset; 5792 if (unsigned int TF = GADN->getTargetFlags()) 5793 OS << " [TF=" << TF << ']'; 5794 } else if (const FrameIndexSDNode *FIDN = dyn_cast<FrameIndexSDNode>(this)) { 5795 OS << "<" << FIDN->getIndex() << ">"; 5796 } else if (const JumpTableSDNode *JTDN = dyn_cast<JumpTableSDNode>(this)) { 5797 OS << "<" << JTDN->getIndex() << ">"; 5798 if (unsigned int TF = JTDN->getTargetFlags()) 5799 OS << " [TF=" << TF << ']'; 5800 } else if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(this)){ 5801 int offset = CP->getOffset(); 5802 if (CP->isMachineConstantPoolEntry()) 5803 OS << "<" << *CP->getMachineCPVal() << ">"; 5804 else 5805 OS << "<" << *CP->getConstVal() << ">"; 5806 if (offset > 0) 5807 OS << " + " << offset; 5808 else 5809 OS << " " << offset; 5810 if (unsigned int TF = CP->getTargetFlags()) 5811 OS << " [TF=" << TF << ']'; 5812 } else if (const BasicBlockSDNode *BBDN = dyn_cast<BasicBlockSDNode>(this)) { 5813 OS << "<"; 5814 const Value *LBB = (const Value*)BBDN->getBasicBlock()->getBasicBlock(); 5815 if (LBB) 5816 OS << LBB->getName() << " "; 5817 OS << (const void*)BBDN->getBasicBlock() << ">"; 5818 } else if (const RegisterSDNode *R = dyn_cast<RegisterSDNode>(this)) { 5819 if (G && R->getReg() && 5820 TargetRegisterInfo::isPhysicalRegister(R->getReg())) { 5821 OS << " %" << G->getTarget().getRegisterInfo()->getName(R->getReg()); 5822 } else { 5823 OS << " %reg" << R->getReg(); 5824 } 5825 } else if (const ExternalSymbolSDNode *ES = 5826 dyn_cast<ExternalSymbolSDNode>(this)) { 5827 OS << "'" << ES->getSymbol() << "'"; 5828 if (unsigned int TF = ES->getTargetFlags()) 5829 OS << " [TF=" << TF << ']'; 5830 } else if (const SrcValueSDNode *M = dyn_cast<SrcValueSDNode>(this)) { 5831 if (M->getValue()) 5832 OS << "<" << M->getValue() << ">"; 5833 else 5834 OS << "<null>"; 5835 } else if (const VTSDNode *N = dyn_cast<VTSDNode>(this)) { 5836 OS << ":" << N->getVT().getEVTString(); 5837 } 5838 else if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(this)) { 5839 OS << "<" << *LD->getMemOperand(); 5840 5841 bool doExt = true; 5842 switch (LD->getExtensionType()) { 5843 default: doExt = false; break; 5844 case ISD::EXTLOAD: OS << ", anyext"; break; 5845 case ISD::SEXTLOAD: OS << ", sext"; break; 5846 case ISD::ZEXTLOAD: OS << ", zext"; break; 5847 } 5848 if (doExt) 5849 OS << " from " << LD->getMemoryVT().getEVTString(); 5850 5851 const char *AM = getIndexedModeName(LD->getAddressingMode()); 5852 if (*AM) 5853 OS << ", " << AM; 5854 5855 OS << ">"; 5856 } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(this)) { 5857 OS << "<" << *ST->getMemOperand(); 5858 5859 if (ST->isTruncatingStore()) 5860 OS << ", trunc to " << ST->getMemoryVT().getEVTString(); 5861 5862 const char *AM = getIndexedModeName(ST->getAddressingMode()); 5863 if (*AM) 5864 OS << ", " << AM; 5865 5866 OS << ">"; 5867 } else if (const MemSDNode* M = dyn_cast<MemSDNode>(this)) { 5868 OS << "<" << *M->getMemOperand() << ">"; 5869 } else if (const BlockAddressSDNode *BA = 5870 dyn_cast<BlockAddressSDNode>(this)) { 5871 OS << "<"; 5872 WriteAsOperand(OS, BA->getBlockAddress()->getFunction(), false); 5873 OS << ", "; 5874 WriteAsOperand(OS, BA->getBlockAddress()->getBasicBlock(), false); 5875 OS << ">"; 5876 if (unsigned int TF = BA->getTargetFlags()) 5877 OS << " [TF=" << TF << ']'; 5878 } 5879 5880 if (G) 5881 if (unsigned Order = G->GetOrdering(this)) 5882 OS << " [ORD=" << Order << ']'; 5883} 5884 5885void SDNode::print(raw_ostream &OS, const SelectionDAG *G) const { 5886 print_types(OS, G); 5887 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 5888 if (i) OS << ", "; else OS << " "; 5889 OS << (void*)getOperand(i).getNode(); 5890 if (unsigned RN = getOperand(i).getResNo()) 5891 OS << ":" << RN; 5892 } 5893 print_details(OS, G); 5894} 5895 5896static void DumpNodes(const SDNode *N, unsigned indent, const SelectionDAG *G) { 5897 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 5898 if (N->getOperand(i).getNode()->hasOneUse()) 5899 DumpNodes(N->getOperand(i).getNode(), indent+2, G); 5900 else 5901 dbgs() << "\n" << std::string(indent+2, ' ') 5902 << (void*)N->getOperand(i).getNode() << ": <multiple use>"; 5903 5904 5905 dbgs() << "\n"; 5906 dbgs().indent(indent); 5907 N->dump(G); 5908} 5909 5910SDValue SelectionDAG::UnrollVectorOp(SDNode *N, unsigned ResNE) { 5911 assert(N->getNumValues() == 1 && 5912 "Can't unroll a vector with multiple results!"); 5913 5914 EVT VT = N->getValueType(0); 5915 unsigned NE = VT.getVectorNumElements(); 5916 EVT EltVT = VT.getVectorElementType(); 5917 DebugLoc dl = N->getDebugLoc(); 5918 5919 SmallVector<SDValue, 8> Scalars; 5920 SmallVector<SDValue, 4> Operands(N->getNumOperands()); 5921 5922 // If ResNE is 0, fully unroll the vector op. 5923 if (ResNE == 0) 5924 ResNE = NE; 5925 else if (NE > ResNE) 5926 NE = ResNE; 5927 5928 unsigned i; 5929 for (i= 0; i != NE; ++i) { 5930 for (unsigned j = 0; j != N->getNumOperands(); ++j) { 5931 SDValue Operand = N->getOperand(j); 5932 EVT OperandVT = Operand.getValueType(); 5933 if (OperandVT.isVector()) { 5934 // A vector operand; extract a single element. 5935 EVT OperandEltVT = OperandVT.getVectorElementType(); 5936 Operands[j] = getNode(ISD::EXTRACT_VECTOR_ELT, dl, 5937 OperandEltVT, 5938 Operand, 5939 getConstant(i, MVT::i32)); 5940 } else { 5941 // A scalar operand; just use it as is. 5942 Operands[j] = Operand; 5943 } 5944 } 5945 5946 switch (N->getOpcode()) { 5947 default: 5948 Scalars.push_back(getNode(N->getOpcode(), dl, EltVT, 5949 &Operands[0], Operands.size())); 5950 break; 5951 case ISD::SHL: 5952 case ISD::SRA: 5953 case ISD::SRL: 5954 case ISD::ROTL: 5955 case ISD::ROTR: 5956 Scalars.push_back(getNode(N->getOpcode(), dl, EltVT, Operands[0], 5957 getShiftAmountOperand(Operands[1]))); 5958 break; 5959 case ISD::SIGN_EXTEND_INREG: 5960 case ISD::FP_ROUND_INREG: { 5961 EVT ExtVT = cast<VTSDNode>(Operands[1])->getVT().getVectorElementType(); 5962 Scalars.push_back(getNode(N->getOpcode(), dl, EltVT, 5963 Operands[0], 5964 getValueType(ExtVT))); 5965 } 5966 } 5967 } 5968 5969 for (; i < ResNE; ++i) 5970 Scalars.push_back(getUNDEF(EltVT)); 5971 5972 return getNode(ISD::BUILD_VECTOR, dl, 5973 EVT::getVectorVT(*getContext(), EltVT, ResNE), 5974 &Scalars[0], Scalars.size()); 5975} 5976 5977 5978/// isConsecutiveLoad - Return true if LD is loading 'Bytes' bytes from a 5979/// location that is 'Dist' units away from the location that the 'Base' load 5980/// is loading from. 5981bool SelectionDAG::isConsecutiveLoad(LoadSDNode *LD, LoadSDNode *Base, 5982 unsigned Bytes, int Dist) const { 5983 if (LD->getChain() != Base->getChain()) 5984 return false; 5985 EVT VT = LD->getValueType(0); 5986 if (VT.getSizeInBits() / 8 != Bytes) 5987 return false; 5988 5989 SDValue Loc = LD->getOperand(1); 5990 SDValue BaseLoc = Base->getOperand(1); 5991 if (Loc.getOpcode() == ISD::FrameIndex) { 5992 if (BaseLoc.getOpcode() != ISD::FrameIndex) 5993 return false; 5994 const MachineFrameInfo *MFI = getMachineFunction().getFrameInfo(); 5995 int FI = cast<FrameIndexSDNode>(Loc)->getIndex(); 5996 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex(); 5997 int FS = MFI->getObjectSize(FI); 5998 int BFS = MFI->getObjectSize(BFI); 5999 if (FS != BFS || FS != (int)Bytes) return false; 6000 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Bytes); 6001 } 6002 if (Loc.getOpcode() == ISD::ADD && Loc.getOperand(0) == BaseLoc) { 6003 ConstantSDNode *V = dyn_cast<ConstantSDNode>(Loc.getOperand(1)); 6004 if (V && (V->getSExtValue() == Dist*Bytes)) 6005 return true; 6006 } 6007 6008 GlobalValue *GV1 = NULL; 6009 GlobalValue *GV2 = NULL; 6010 int64_t Offset1 = 0; 6011 int64_t Offset2 = 0; 6012 bool isGA1 = TLI.isGAPlusOffset(Loc.getNode(), GV1, Offset1); 6013 bool isGA2 = TLI.isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2); 6014 if (isGA1 && isGA2 && GV1 == GV2) 6015 return Offset1 == (Offset2 + Dist*Bytes); 6016 return false; 6017} 6018 6019 6020/// InferPtrAlignment - Infer alignment of a load / store address. Return 0 if 6021/// it cannot be inferred. 6022unsigned SelectionDAG::InferPtrAlignment(SDValue Ptr) const { 6023 // If this is a GlobalAddress + cst, return the alignment. 6024 GlobalValue *GV; 6025 int64_t GVOffset = 0; 6026 if (TLI.isGAPlusOffset(Ptr.getNode(), GV, GVOffset)) 6027 return MinAlign(GV->getAlignment(), GVOffset); 6028 6029 // If this is a direct reference to a stack slot, use information about the 6030 // stack slot's alignment. 6031 int FrameIdx = 1 << 31; 6032 int64_t FrameOffset = 0; 6033 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Ptr)) { 6034 FrameIdx = FI->getIndex(); 6035 } else if (Ptr.getOpcode() == ISD::ADD && 6036 isa<ConstantSDNode>(Ptr.getOperand(1)) && 6037 isa<FrameIndexSDNode>(Ptr.getOperand(0))) { 6038 FrameIdx = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex(); 6039 FrameOffset = Ptr.getConstantOperandVal(1); 6040 } 6041 6042 if (FrameIdx != (1 << 31)) { 6043 // FIXME: Handle FI+CST. 6044 const MachineFrameInfo &MFI = *getMachineFunction().getFrameInfo(); 6045 unsigned FIInfoAlign = MinAlign(MFI.getObjectAlignment(FrameIdx), 6046 FrameOffset); 6047 if (MFI.isFixedObjectIndex(FrameIdx)) { 6048 int64_t ObjectOffset = MFI.getObjectOffset(FrameIdx) + FrameOffset; 6049 6050 // The alignment of the frame index can be determined from its offset from 6051 // the incoming frame position. If the frame object is at offset 32 and 6052 // the stack is guaranteed to be 16-byte aligned, then we know that the 6053 // object is 16-byte aligned. 6054 unsigned StackAlign = getTarget().getFrameInfo()->getStackAlignment(); 6055 unsigned Align = MinAlign(ObjectOffset, StackAlign); 6056 6057 // Finally, the frame object itself may have a known alignment. Factor 6058 // the alignment + offset into a new alignment. For example, if we know 6059 // the FI is 8 byte aligned, but the pointer is 4 off, we really have a 6060 // 4-byte alignment of the resultant pointer. Likewise align 4 + 4-byte 6061 // offset = 4-byte alignment, align 4 + 1-byte offset = align 1, etc. 6062 return std::max(Align, FIInfoAlign); 6063 } 6064 return FIInfoAlign; 6065 } 6066 6067 return 0; 6068} 6069 6070void SelectionDAG::dump() const { 6071 dbgs() << "SelectionDAG has " << AllNodes.size() << " nodes:"; 6072 6073 for (allnodes_const_iterator I = allnodes_begin(), E = allnodes_end(); 6074 I != E; ++I) { 6075 const SDNode *N = I; 6076 if (!N->hasOneUse() && N != getRoot().getNode()) 6077 DumpNodes(N, 2, this); 6078 } 6079 6080 if (getRoot().getNode()) DumpNodes(getRoot().getNode(), 2, this); 6081 6082 dbgs() << "\n\n"; 6083} 6084 6085void SDNode::printr(raw_ostream &OS, const SelectionDAG *G) const { 6086 print_types(OS, G); 6087 print_details(OS, G); 6088} 6089 6090typedef SmallPtrSet<const SDNode *, 128> VisitedSDNodeSet; 6091static void DumpNodesr(raw_ostream &OS, const SDNode *N, unsigned indent, 6092 const SelectionDAG *G, VisitedSDNodeSet &once) { 6093 if (!once.insert(N)) // If we've been here before, return now. 6094 return; 6095 6096 // Dump the current SDNode, but don't end the line yet. 6097 OS << std::string(indent, ' '); 6098 N->printr(OS, G); 6099 6100 // Having printed this SDNode, walk the children: 6101 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 6102 const SDNode *child = N->getOperand(i).getNode(); 6103 6104 if (i) OS << ","; 6105 OS << " "; 6106 6107 if (child->getNumOperands() == 0) { 6108 // This child has no grandchildren; print it inline right here. 6109 child->printr(OS, G); 6110 once.insert(child); 6111 } else { // Just the address. FIXME: also print the child's opcode. 6112 OS << (void*)child; 6113 if (unsigned RN = N->getOperand(i).getResNo()) 6114 OS << ":" << RN; 6115 } 6116 } 6117 6118 OS << "\n"; 6119 6120 // Dump children that have grandchildren on their own line(s). 6121 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 6122 const SDNode *child = N->getOperand(i).getNode(); 6123 DumpNodesr(OS, child, indent+2, G, once); 6124 } 6125} 6126 6127void SDNode::dumpr() const { 6128 VisitedSDNodeSet once; 6129 DumpNodesr(dbgs(), this, 0, 0, once); 6130} 6131 6132void SDNode::dumpr(const SelectionDAG *G) const { 6133 VisitedSDNodeSet once; 6134 DumpNodesr(dbgs(), this, 0, G, once); 6135} 6136 6137 6138// getAddressSpace - Return the address space this GlobalAddress belongs to. 6139unsigned GlobalAddressSDNode::getAddressSpace() const { 6140 return getGlobal()->getType()->getAddressSpace(); 6141} 6142 6143 6144const Type *ConstantPoolSDNode::getType() const { 6145 if (isMachineConstantPoolEntry()) 6146 return Val.MachineCPVal->getType(); 6147 return Val.ConstVal->getType(); 6148} 6149 6150bool BuildVectorSDNode::isConstantSplat(APInt &SplatValue, 6151 APInt &SplatUndef, 6152 unsigned &SplatBitSize, 6153 bool &HasAnyUndefs, 6154 unsigned MinSplatBits, 6155 bool isBigEndian) { 6156 EVT VT = getValueType(0); 6157 assert(VT.isVector() && "Expected a vector type"); 6158 unsigned sz = VT.getSizeInBits(); 6159 if (MinSplatBits > sz) 6160 return false; 6161 6162 SplatValue = APInt(sz, 0); 6163 SplatUndef = APInt(sz, 0); 6164 6165 // Get the bits. Bits with undefined values (when the corresponding element 6166 // of the vector is an ISD::UNDEF value) are set in SplatUndef and cleared 6167 // in SplatValue. If any of the values are not constant, give up and return 6168 // false. 6169 unsigned int nOps = getNumOperands(); 6170 assert(nOps > 0 && "isConstantSplat has 0-size build vector"); 6171 unsigned EltBitSize = VT.getVectorElementType().getSizeInBits(); 6172 6173 for (unsigned j = 0; j < nOps; ++j) { 6174 unsigned i = isBigEndian ? nOps-1-j : j; 6175 SDValue OpVal = getOperand(i); 6176 unsigned BitPos = j * EltBitSize; 6177 6178 if (OpVal.getOpcode() == ISD::UNDEF) 6179 SplatUndef |= APInt::getBitsSet(sz, BitPos, BitPos + EltBitSize); 6180 else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) 6181 SplatValue |= (APInt(CN->getAPIntValue()).zextOrTrunc(EltBitSize). 6182 zextOrTrunc(sz) << BitPos); 6183 else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) 6184 SplatValue |= CN->getValueAPF().bitcastToAPInt().zextOrTrunc(sz) <<BitPos; 6185 else 6186 return false; 6187 } 6188 6189 // The build_vector is all constants or undefs. Find the smallest element 6190 // size that splats the vector. 6191 6192 HasAnyUndefs = (SplatUndef != 0); 6193 while (sz > 8) { 6194 6195 unsigned HalfSize = sz / 2; 6196 APInt HighValue = APInt(SplatValue).lshr(HalfSize).trunc(HalfSize); 6197 APInt LowValue = APInt(SplatValue).trunc(HalfSize); 6198 APInt HighUndef = APInt(SplatUndef).lshr(HalfSize).trunc(HalfSize); 6199 APInt LowUndef = APInt(SplatUndef).trunc(HalfSize); 6200 6201 // If the two halves do not match (ignoring undef bits), stop here. 6202 if ((HighValue & ~LowUndef) != (LowValue & ~HighUndef) || 6203 MinSplatBits > HalfSize) 6204 break; 6205 6206 SplatValue = HighValue | LowValue; 6207 SplatUndef = HighUndef & LowUndef; 6208 6209 sz = HalfSize; 6210 } 6211 6212 SplatBitSize = sz; 6213 return true; 6214} 6215 6216bool ShuffleVectorSDNode::isSplatMask(const int *Mask, EVT VT) { 6217 // Find the first non-undef value in the shuffle mask. 6218 unsigned i, e; 6219 for (i = 0, e = VT.getVectorNumElements(); i != e && Mask[i] < 0; ++i) 6220 /* search */; 6221 6222 assert(i != e && "VECTOR_SHUFFLE node with all undef indices!"); 6223 6224 // Make sure all remaining elements are either undef or the same as the first 6225 // non-undef value. 6226 for (int Idx = Mask[i]; i != e; ++i) 6227 if (Mask[i] >= 0 && Mask[i] != Idx) 6228 return false; 6229 return true; 6230} 6231