SelectionDAG.cpp revision e5d63829fd62d815a330c21ea316e6b4cf943562
1//===-- SelectionDAG.cpp - Implement the SelectionDAG data structures -----===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAG class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/Constants.h" 16#include "llvm/GlobalValue.h" 17#include "llvm/Assembly/Writer.h" 18#include "llvm/CodeGen/MachineBasicBlock.h" 19#include "llvm/Support/MathExtras.h" 20#include "llvm/Target/TargetLowering.h" 21#include <iostream> 22#include <set> 23#include <cmath> 24#include <algorithm> 25using namespace llvm; 26 27static bool isCommutativeBinOp(unsigned Opcode) { 28 switch (Opcode) { 29 case ISD::ADD: 30 case ISD::MUL: 31 case ISD::AND: 32 case ISD::OR: 33 case ISD::XOR: return true; 34 default: return false; // FIXME: Need commutative info for user ops! 35 } 36} 37 38static bool isAssociativeBinOp(unsigned Opcode) { 39 switch (Opcode) { 40 case ISD::ADD: 41 case ISD::MUL: 42 case ISD::AND: 43 case ISD::OR: 44 case ISD::XOR: return true; 45 default: return false; // FIXME: Need associative info for user ops! 46 } 47} 48 49// isInvertibleForFree - Return true if there is no cost to emitting the logical 50// inverse of this node. 51static bool isInvertibleForFree(SDOperand N) { 52 if (isa<ConstantSDNode>(N.Val)) return true; 53 if (N.Val->getOpcode() == ISD::SETCC && N.Val->hasOneUse()) 54 return true; 55 return false; 56} 57 58 59/// getSetCCSwappedOperands - Return the operation corresponding to (Y op X) 60/// when given the operation for (X op Y). 61ISD::CondCode ISD::getSetCCSwappedOperands(ISD::CondCode Operation) { 62 // To perform this operation, we just need to swap the L and G bits of the 63 // operation. 64 unsigned OldL = (Operation >> 2) & 1; 65 unsigned OldG = (Operation >> 1) & 1; 66 return ISD::CondCode((Operation & ~6) | // Keep the N, U, E bits 67 (OldL << 1) | // New G bit 68 (OldG << 2)); // New L bit. 69} 70 71/// getSetCCInverse - Return the operation corresponding to !(X op Y), where 72/// 'op' is a valid SetCC operation. 73ISD::CondCode ISD::getSetCCInverse(ISD::CondCode Op, bool isInteger) { 74 unsigned Operation = Op; 75 if (isInteger) 76 Operation ^= 7; // Flip L, G, E bits, but not U. 77 else 78 Operation ^= 15; // Flip all of the condition bits. 79 if (Operation > ISD::SETTRUE2) 80 Operation &= ~8; // Don't let N and U bits get set. 81 return ISD::CondCode(Operation); 82} 83 84 85/// isSignedOp - For an integer comparison, return 1 if the comparison is a 86/// signed operation and 2 if the result is an unsigned comparison. Return zero 87/// if the operation does not depend on the sign of the input (setne and seteq). 88static int isSignedOp(ISD::CondCode Opcode) { 89 switch (Opcode) { 90 default: assert(0 && "Illegal integer setcc operation!"); 91 case ISD::SETEQ: 92 case ISD::SETNE: return 0; 93 case ISD::SETLT: 94 case ISD::SETLE: 95 case ISD::SETGT: 96 case ISD::SETGE: return 1; 97 case ISD::SETULT: 98 case ISD::SETULE: 99 case ISD::SETUGT: 100 case ISD::SETUGE: return 2; 101 } 102} 103 104/// getSetCCOrOperation - Return the result of a logical OR between different 105/// comparisons of identical values: ((X op1 Y) | (X op2 Y)). This function 106/// returns SETCC_INVALID if it is not possible to represent the resultant 107/// comparison. 108ISD::CondCode ISD::getSetCCOrOperation(ISD::CondCode Op1, ISD::CondCode Op2, 109 bool isInteger) { 110 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 111 // Cannot fold a signed integer setcc with an unsigned integer setcc. 112 return ISD::SETCC_INVALID; 113 114 unsigned Op = Op1 | Op2; // Combine all of the condition bits. 115 116 // If the N and U bits get set then the resultant comparison DOES suddenly 117 // care about orderedness, and is true when ordered. 118 if (Op > ISD::SETTRUE2) 119 Op &= ~16; // Clear the N bit. 120 return ISD::CondCode(Op); 121} 122 123/// getSetCCAndOperation - Return the result of a logical AND between different 124/// comparisons of identical values: ((X op1 Y) & (X op2 Y)). This 125/// function returns zero if it is not possible to represent the resultant 126/// comparison. 127ISD::CondCode ISD::getSetCCAndOperation(ISD::CondCode Op1, ISD::CondCode Op2, 128 bool isInteger) { 129 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 130 // Cannot fold a signed setcc with an unsigned setcc. 131 return ISD::SETCC_INVALID; 132 133 // Combine all of the condition bits. 134 return ISD::CondCode(Op1 & Op2); 135} 136 137const TargetMachine &SelectionDAG::getTarget() const { 138 return TLI.getTargetMachine(); 139} 140 141 142/// RemoveDeadNodes - This method deletes all unreachable nodes in the 143/// SelectionDAG, including nodes (like loads) that have uses of their token 144/// chain but no other uses and no side effect. If a node is passed in as an 145/// argument, it is used as the seed for node deletion. 146void SelectionDAG::RemoveDeadNodes(SDNode *N) { 147 std::set<SDNode*> AllNodeSet(AllNodes.begin(), AllNodes.end()); 148 149 // Create a dummy node (which is not added to allnodes), that adds a reference 150 // to the root node, preventing it from being deleted. 151 SDNode *DummyNode = new SDNode(ISD::EntryToken, getRoot()); 152 153 DeleteNodeIfDead(N, &AllNodeSet); 154 155 Restart: 156 unsigned NumNodes = AllNodeSet.size(); 157 for (std::set<SDNode*>::iterator I = AllNodeSet.begin(), E = AllNodeSet.end(); 158 I != E; ++I) { 159 // Try to delete this node. 160 DeleteNodeIfDead(*I, &AllNodeSet); 161 162 // If we actually deleted any nodes, do not use invalid iterators in 163 // AllNodeSet. 164 if (AllNodeSet.size() != NumNodes) 165 goto Restart; 166 } 167 168 // Restore AllNodes. 169 if (AllNodes.size() != NumNodes) 170 AllNodes.assign(AllNodeSet.begin(), AllNodeSet.end()); 171 172 // If the root changed (e.g. it was a dead load, update the root). 173 setRoot(DummyNode->getOperand(0)); 174 175 // Now that we are done with the dummy node, delete it. 176 DummyNode->getOperand(0).Val->removeUser(DummyNode); 177 delete DummyNode; 178} 179 180void SelectionDAG::DeleteNodeIfDead(SDNode *N, void *NodeSet) { 181 if (!N->use_empty()) 182 return; 183 184 // Okay, we really are going to delete this node. First take this out of the 185 // appropriate CSE map. 186 switch (N->getOpcode()) { 187 case ISD::Constant: 188 Constants.erase(std::make_pair(cast<ConstantSDNode>(N)->getValue(), 189 N->getValueType(0))); 190 break; 191 case ISD::ConstantFP: { 192 union { 193 double DV; 194 uint64_t IV; 195 }; 196 DV = cast<ConstantFPSDNode>(N)->getValue(); 197 ConstantFPs.erase(std::make_pair(IV, N->getValueType(0))); 198 break; 199 } 200 case ISD::CONDCODE: 201 assert(CondCodeNodes[cast<CondCodeSDNode>(N)->get()] && 202 "Cond code doesn't exist!"); 203 CondCodeNodes[cast<CondCodeSDNode>(N)->get()] = 0; 204 break; 205 case ISD::GlobalAddress: 206 GlobalValues.erase(cast<GlobalAddressSDNode>(N)->getGlobal()); 207 break; 208 case ISD::FrameIndex: 209 FrameIndices.erase(cast<FrameIndexSDNode>(N)->getIndex()); 210 break; 211 case ISD::ConstantPool: 212 ConstantPoolIndices.erase(cast<ConstantPoolSDNode>(N)->getIndex()); 213 break; 214 case ISD::BasicBlock: 215 BBNodes.erase(cast<BasicBlockSDNode>(N)->getBasicBlock()); 216 break; 217 case ISD::ExternalSymbol: 218 ExternalSymbols.erase(cast<ExternalSymbolSDNode>(N)->getSymbol()); 219 break; 220 case ISD::VALUETYPE: 221 ValueTypeNodes[cast<VTSDNode>(N)->getVT()] = 0; 222 break; 223 case ISD::SRCVALUE: { 224 SrcValueSDNode *SVN = cast<SrcValueSDNode>(N); 225 ValueNodes.erase(std::make_pair(SVN->getValue(), SVN->getOffset())); 226 break; 227 } 228 case ISD::LOAD: 229 Loads.erase(std::make_pair(N->getOperand(1), 230 std::make_pair(N->getOperand(0), 231 N->getValueType(0)))); 232 break; 233 default: 234 if (N->getNumOperands() == 1) 235 UnaryOps.erase(std::make_pair(N->getOpcode(), 236 std::make_pair(N->getOperand(0), 237 N->getValueType(0)))); 238 else if (N->getNumOperands() == 2) 239 BinaryOps.erase(std::make_pair(N->getOpcode(), 240 std::make_pair(N->getOperand(0), 241 N->getOperand(1)))); 242 else if (N->getNumValues() == 1) { 243 std::vector<SDOperand> Ops(N->op_begin(), N->op_end()); 244 OneResultNodes.erase(std::make_pair(N->getOpcode(), 245 std::make_pair(N->getValueType(0), 246 Ops))); 247 } else { 248 // Remove the node from the ArbitraryNodes map. 249 std::vector<MVT::ValueType> RV(N->value_begin(), N->value_end()); 250 std::vector<SDOperand> Ops(N->op_begin(), N->op_end()); 251 ArbitraryNodes.erase(std::make_pair(N->getOpcode(), 252 std::make_pair(RV, Ops))); 253 } 254 break; 255 } 256 257 // Next, brutally remove the operand list. 258 while (!N->Operands.empty()) { 259 SDNode *O = N->Operands.back().Val; 260 N->Operands.pop_back(); 261 O->removeUser(N); 262 263 // Now that we removed this operand, see if there are no uses of it left. 264 DeleteNodeIfDead(O, NodeSet); 265 } 266 267 // Remove the node from the nodes set and delete it. 268 std::set<SDNode*> &AllNodeSet = *(std::set<SDNode*>*)NodeSet; 269 AllNodeSet.erase(N); 270 271 // Now that the node is gone, check to see if any of the operands of this node 272 // are dead now. 273 delete N; 274} 275 276 277SelectionDAG::~SelectionDAG() { 278 for (unsigned i = 0, e = AllNodes.size(); i != e; ++i) 279 delete AllNodes[i]; 280} 281 282SDOperand SelectionDAG::getZeroExtendInReg(SDOperand Op, MVT::ValueType VT) { 283 if (Op.getValueType() == VT) return Op; 284 int64_t Imm = ~0ULL >> (64-MVT::getSizeInBits(VT)); 285 return getNode(ISD::AND, Op.getValueType(), Op, 286 getConstant(Imm, Op.getValueType())); 287} 288 289SDOperand SelectionDAG::getConstant(uint64_t Val, MVT::ValueType VT) { 290 assert(MVT::isInteger(VT) && "Cannot create FP integer constant!"); 291 // Mask out any bits that are not valid for this constant. 292 if (VT != MVT::i64) 293 Val &= ((uint64_t)1 << MVT::getSizeInBits(VT)) - 1; 294 295 SDNode *&N = Constants[std::make_pair(Val, VT)]; 296 if (N) return SDOperand(N, 0); 297 N = new ConstantSDNode(Val, VT); 298 AllNodes.push_back(N); 299 return SDOperand(N, 0); 300} 301 302SDOperand SelectionDAG::getConstantFP(double Val, MVT::ValueType VT) { 303 assert(MVT::isFloatingPoint(VT) && "Cannot create integer FP constant!"); 304 if (VT == MVT::f32) 305 Val = (float)Val; // Mask out extra precision. 306 307 // Do the map lookup using the actual bit pattern for the floating point 308 // value, so that we don't have problems with 0.0 comparing equal to -0.0, and 309 // we don't have issues with SNANs. 310 union { 311 double DV; 312 uint64_t IV; 313 }; 314 315 DV = Val; 316 317 SDNode *&N = ConstantFPs[std::make_pair(IV, VT)]; 318 if (N) return SDOperand(N, 0); 319 N = new ConstantFPSDNode(Val, VT); 320 AllNodes.push_back(N); 321 return SDOperand(N, 0); 322} 323 324 325 326SDOperand SelectionDAG::getGlobalAddress(const GlobalValue *GV, 327 MVT::ValueType VT) { 328 SDNode *&N = GlobalValues[GV]; 329 if (N) return SDOperand(N, 0); 330 N = new GlobalAddressSDNode(GV,VT); 331 AllNodes.push_back(N); 332 return SDOperand(N, 0); 333} 334 335SDOperand SelectionDAG::getFrameIndex(int FI, MVT::ValueType VT) { 336 SDNode *&N = FrameIndices[FI]; 337 if (N) return SDOperand(N, 0); 338 N = new FrameIndexSDNode(FI, VT); 339 AllNodes.push_back(N); 340 return SDOperand(N, 0); 341} 342 343SDOperand SelectionDAG::getConstantPool(unsigned CPIdx, MVT::ValueType VT) { 344 SDNode *N = ConstantPoolIndices[CPIdx]; 345 if (N) return SDOperand(N, 0); 346 N = new ConstantPoolSDNode(CPIdx, VT); 347 AllNodes.push_back(N); 348 return SDOperand(N, 0); 349} 350 351SDOperand SelectionDAG::getBasicBlock(MachineBasicBlock *MBB) { 352 SDNode *&N = BBNodes[MBB]; 353 if (N) return SDOperand(N, 0); 354 N = new BasicBlockSDNode(MBB); 355 AllNodes.push_back(N); 356 return SDOperand(N, 0); 357} 358 359SDOperand SelectionDAG::getValueType(MVT::ValueType VT) { 360 if ((unsigned)VT >= ValueTypeNodes.size()) 361 ValueTypeNodes.resize(VT+1); 362 if (ValueTypeNodes[VT] == 0) { 363 ValueTypeNodes[VT] = new VTSDNode(VT); 364 AllNodes.push_back(ValueTypeNodes[VT]); 365 } 366 367 return SDOperand(ValueTypeNodes[VT], 0); 368} 369 370SDOperand SelectionDAG::getExternalSymbol(const char *Sym, MVT::ValueType VT) { 371 SDNode *&N = ExternalSymbols[Sym]; 372 if (N) return SDOperand(N, 0); 373 N = new ExternalSymbolSDNode(Sym, VT); 374 AllNodes.push_back(N); 375 return SDOperand(N, 0); 376} 377 378SDOperand SelectionDAG::getCondCode(ISD::CondCode Cond) { 379 if ((unsigned)Cond >= CondCodeNodes.size()) 380 CondCodeNodes.resize(Cond+1); 381 382 if (CondCodeNodes[Cond] == 0) { 383 CondCodeNodes[Cond] = new CondCodeSDNode(Cond); 384 AllNodes.push_back(CondCodeNodes[Cond]); 385 } 386 return SDOperand(CondCodeNodes[Cond], 0); 387} 388 389SDOperand SelectionDAG::SimplifySetCC(MVT::ValueType VT, SDOperand N1, 390 SDOperand N2, ISD::CondCode Cond) { 391 // These setcc operations always fold. 392 switch (Cond) { 393 default: break; 394 case ISD::SETFALSE: 395 case ISD::SETFALSE2: return getConstant(0, VT); 396 case ISD::SETTRUE: 397 case ISD::SETTRUE2: return getConstant(1, VT); 398 } 399 400 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val)) { 401 uint64_t C2 = N2C->getValue(); 402 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) { 403 uint64_t C1 = N1C->getValue(); 404 405 // Sign extend the operands if required 406 if (ISD::isSignedIntSetCC(Cond)) { 407 C1 = N1C->getSignExtended(); 408 C2 = N2C->getSignExtended(); 409 } 410 411 switch (Cond) { 412 default: assert(0 && "Unknown integer setcc!"); 413 case ISD::SETEQ: return getConstant(C1 == C2, VT); 414 case ISD::SETNE: return getConstant(C1 != C2, VT); 415 case ISD::SETULT: return getConstant(C1 < C2, VT); 416 case ISD::SETUGT: return getConstant(C1 > C2, VT); 417 case ISD::SETULE: return getConstant(C1 <= C2, VT); 418 case ISD::SETUGE: return getConstant(C1 >= C2, VT); 419 case ISD::SETLT: return getConstant((int64_t)C1 < (int64_t)C2, VT); 420 case ISD::SETGT: return getConstant((int64_t)C1 > (int64_t)C2, VT); 421 case ISD::SETLE: return getConstant((int64_t)C1 <= (int64_t)C2, VT); 422 case ISD::SETGE: return getConstant((int64_t)C1 >= (int64_t)C2, VT); 423 } 424 } else { 425 // If the LHS is a ZERO_EXTEND and if this is an ==/!= comparison, perform 426 // the comparison on the input. 427 if (N1.getOpcode() == ISD::ZERO_EXTEND) { 428 unsigned InSize = MVT::getSizeInBits(N1.getOperand(0).getValueType()); 429 430 // If the comparison constant has bits in the upper part, the 431 // zero-extended value could never match. 432 if (C2 & (~0ULL << InSize)) { 433 unsigned VSize = MVT::getSizeInBits(N1.getValueType()); 434 switch (Cond) { 435 case ISD::SETUGT: 436 case ISD::SETUGE: 437 case ISD::SETEQ: return getConstant(0, VT); 438 case ISD::SETULT: 439 case ISD::SETULE: 440 case ISD::SETNE: return getConstant(1, VT); 441 case ISD::SETGT: 442 case ISD::SETGE: 443 // True if the sign bit of C2 is set. 444 return getConstant((C2 & (1ULL << VSize)) != 0, VT); 445 case ISD::SETLT: 446 case ISD::SETLE: 447 // True if the sign bit of C2 isn't set. 448 return getConstant((C2 & (1ULL << VSize)) == 0, VT); 449 default: 450 break; 451 } 452 } 453 454 // Otherwise, we can perform the comparison with the low bits. 455 switch (Cond) { 456 case ISD::SETEQ: 457 case ISD::SETNE: 458 case ISD::SETUGT: 459 case ISD::SETUGE: 460 case ISD::SETULT: 461 case ISD::SETULE: 462 return getSetCC(VT, N1.getOperand(0), 463 getConstant(C2, N1.getOperand(0).getValueType()), 464 Cond); 465 default: 466 break; // todo, be more careful with signed comparisons 467 } 468 } 469 470 uint64_t MinVal, MaxVal; 471 unsigned OperandBitSize = MVT::getSizeInBits(N2C->getValueType(0)); 472 if (ISD::isSignedIntSetCC(Cond)) { 473 MinVal = 1ULL << (OperandBitSize-1); 474 if (OperandBitSize != 1) // Avoid X >> 64, which is undefined. 475 MaxVal = ~0ULL >> (65-OperandBitSize); 476 else 477 MaxVal = 0; 478 } else { 479 MinVal = 0; 480 MaxVal = ~0ULL >> (64-OperandBitSize); 481 } 482 483 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 484 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 485 if (C2 == MinVal) return getConstant(1, VT); // X >= MIN --> true 486 --C2; // X >= C1 --> X > (C1-1) 487 return getSetCC(VT, N1, getConstant(C2, N2.getValueType()), 488 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); 489 } 490 491 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 492 if (C2 == MaxVal) return getConstant(1, VT); // X <= MAX --> true 493 ++C2; // X <= C1 --> X < (C1+1) 494 return getSetCC(VT, N1, getConstant(C2, N2.getValueType()), 495 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); 496 } 497 498 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C2 == MinVal) 499 return getConstant(0, VT); // X < MIN --> false 500 501 // Canonicalize setgt X, Min --> setne X, Min 502 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C2 == MinVal) 503 return getSetCC(VT, N1, N2, ISD::SETNE); 504 505 // If we have setult X, 1, turn it into seteq X, 0 506 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C2 == MinVal+1) 507 return getSetCC(VT, N1, getConstant(MinVal, N1.getValueType()), 508 ISD::SETEQ); 509 // If we have setugt X, Max-1, turn it into seteq X, Max 510 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C2 == MaxVal-1) 511 return getSetCC(VT, N1, getConstant(MaxVal, N1.getValueType()), 512 ISD::SETEQ); 513 514 // If we have "setcc X, C1", check to see if we can shrink the immediate 515 // by changing cc. 516 517 // SETUGT X, SINTMAX -> SETLT X, 0 518 if (Cond == ISD::SETUGT && OperandBitSize != 1 && 519 C2 == (~0ULL >> (65-OperandBitSize))) 520 return getSetCC(VT, N1, getConstant(0, N2.getValueType()), ISD::SETLT); 521 522 // FIXME: Implement the rest of these. 523 524 525 // Fold bit comparisons when we can. 526 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 527 VT == N1.getValueType() && N1.getOpcode() == ISD::AND) 528 if (ConstantSDNode *AndRHS = 529 dyn_cast<ConstantSDNode>(N1.getOperand(1))) { 530 if (Cond == ISD::SETNE && C2 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 531 // Perform the xform if the AND RHS is a single bit. 532 if ((AndRHS->getValue() & (AndRHS->getValue()-1)) == 0) { 533 return getNode(ISD::SRL, VT, N1, 534 getConstant(Log2_64(AndRHS->getValue()), 535 TLI.getShiftAmountTy())); 536 } 537 } else if (Cond == ISD::SETEQ && C2 == AndRHS->getValue()) { 538 // (X & 8) == 8 --> (X & 8) >> 3 539 // Perform the xform if C2 is a single bit. 540 if ((C2 & (C2-1)) == 0) { 541 return getNode(ISD::SRL, VT, N1, 542 getConstant(Log2_64(C2),TLI.getShiftAmountTy())); 543 } 544 } 545 } 546 } 547 } else if (isa<ConstantSDNode>(N1.Val)) { 548 // Ensure that the constant occurs on the RHS. 549 return getSetCC(VT, N2, N1, ISD::getSetCCSwappedOperands(Cond)); 550 } 551 552 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.Val)) 553 if (ConstantFPSDNode *N2C = dyn_cast<ConstantFPSDNode>(N2.Val)) { 554 double C1 = N1C->getValue(), C2 = N2C->getValue(); 555 556 switch (Cond) { 557 default: break; // FIXME: Implement the rest of these! 558 case ISD::SETEQ: return getConstant(C1 == C2, VT); 559 case ISD::SETNE: return getConstant(C1 != C2, VT); 560 case ISD::SETLT: return getConstant(C1 < C2, VT); 561 case ISD::SETGT: return getConstant(C1 > C2, VT); 562 case ISD::SETLE: return getConstant(C1 <= C2, VT); 563 case ISD::SETGE: return getConstant(C1 >= C2, VT); 564 } 565 } else { 566 // Ensure that the constant occurs on the RHS. 567 return getSetCC(VT, N2, N1, ISD::getSetCCSwappedOperands(Cond)); 568 } 569 570 if (N1 == N2) { 571 // We can always fold X == Y for integer setcc's. 572 if (MVT::isInteger(N1.getValueType())) 573 return getConstant(ISD::isTrueWhenEqual(Cond), VT); 574 unsigned UOF = ISD::getUnorderedFlavor(Cond); 575 if (UOF == 2) // FP operators that are undefined on NaNs. 576 return getConstant(ISD::isTrueWhenEqual(Cond), VT); 577 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 578 return getConstant(UOF, VT); 579 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 580 // if it is not already. 581 ISD::CondCode NewCond = UOF == 0 ? ISD::SETUO : ISD::SETO; 582 if (NewCond != Cond) 583 return getSetCC(VT, N1, N2, NewCond); 584 } 585 586 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 587 MVT::isInteger(N1.getValueType())) { 588 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 589 N1.getOpcode() == ISD::XOR) { 590 // Simplify (X+Y) == (X+Z) --> Y == Z 591 if (N1.getOpcode() == N2.getOpcode()) { 592 if (N1.getOperand(0) == N2.getOperand(0)) 593 return getSetCC(VT, N1.getOperand(1), N2.getOperand(1), Cond); 594 if (N1.getOperand(1) == N2.getOperand(1)) 595 return getSetCC(VT, N1.getOperand(0), N2.getOperand(0), Cond); 596 if (isCommutativeBinOp(N1.getOpcode())) { 597 // If X op Y == Y op X, try other combinations. 598 if (N1.getOperand(0) == N2.getOperand(1)) 599 return getSetCC(VT, N1.getOperand(1), N2.getOperand(0), Cond); 600 if (N1.getOperand(1) == N2.getOperand(0)) 601 return getSetCC(VT, N1.getOperand(1), N2.getOperand(1), Cond); 602 } 603 } 604 605 // FIXME: move this stuff to the DAG Combiner when it exists! 606 607 // Simplify (X+Z) == X --> Z == 0 608 if (N1.getOperand(0) == N2) 609 return getSetCC(VT, N1.getOperand(1), 610 getConstant(0, N1.getValueType()), Cond); 611 if (N1.getOperand(1) == N2) { 612 if (isCommutativeBinOp(N1.getOpcode())) 613 return getSetCC(VT, N1.getOperand(0), 614 getConstant(0, N1.getValueType()), Cond); 615 else { 616 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 617 // (Z-X) == X --> Z == X<<1 618 return getSetCC(VT, N1.getOperand(0), 619 getNode(ISD::SHL, N2.getValueType(), 620 N2, getConstant(1, TLI.getShiftAmountTy())), 621 Cond); 622 } 623 } 624 } 625 626 if (N2.getOpcode() == ISD::ADD || N2.getOpcode() == ISD::SUB || 627 N2.getOpcode() == ISD::XOR) { 628 // Simplify X == (X+Z) --> Z == 0 629 if (N2.getOperand(0) == N1) { 630 return getSetCC(VT, N2.getOperand(1), 631 getConstant(0, N2.getValueType()), Cond); 632 } else if (N2.getOperand(1) == N1) { 633 if (isCommutativeBinOp(N2.getOpcode())) { 634 return getSetCC(VT, N2.getOperand(0), 635 getConstant(0, N2.getValueType()), Cond); 636 } else { 637 assert(N2.getOpcode() == ISD::SUB && "Unexpected operation!"); 638 // X == (Z-X) --> X<<1 == Z 639 return getSetCC(VT, getNode(ISD::SHL, N2.getValueType(), N1, 640 getConstant(1, TLI.getShiftAmountTy())), 641 N2.getOperand(0), Cond); 642 } 643 } 644 } 645 } 646 647 // Fold away ALL boolean setcc's. 648 if (N1.getValueType() == MVT::i1) { 649 switch (Cond) { 650 default: assert(0 && "Unknown integer setcc!"); 651 case ISD::SETEQ: // X == Y -> (X^Y)^1 652 N1 = getNode(ISD::XOR, MVT::i1, 653 getNode(ISD::XOR, MVT::i1, N1, N2), 654 getConstant(1, MVT::i1)); 655 break; 656 case ISD::SETNE: // X != Y --> (X^Y) 657 N1 = getNode(ISD::XOR, MVT::i1, N1, N2); 658 break; 659 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y 660 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y 661 N1 = getNode(ISD::AND, MVT::i1, N2, 662 getNode(ISD::XOR, MVT::i1, N1, getConstant(1, MVT::i1))); 663 break; 664 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X 665 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X 666 N1 = getNode(ISD::AND, MVT::i1, N1, 667 getNode(ISD::XOR, MVT::i1, N2, getConstant(1, MVT::i1))); 668 break; 669 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y 670 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y 671 N1 = getNode(ISD::OR, MVT::i1, N2, 672 getNode(ISD::XOR, MVT::i1, N1, getConstant(1, MVT::i1))); 673 break; 674 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X 675 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X 676 N1 = getNode(ISD::OR, MVT::i1, N1, 677 getNode(ISD::XOR, MVT::i1, N2, getConstant(1, MVT::i1))); 678 break; 679 } 680 if (VT != MVT::i1) 681 N1 = getNode(ISD::ZERO_EXTEND, VT, N1); 682 return N1; 683 } 684 685 // Could not fold it. 686 return SDOperand(); 687} 688 689/// getNode - Gets or creates the specified node. 690/// 691SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT) { 692 SDNode *N = new SDNode(Opcode, VT); 693 AllNodes.push_back(N); 694 return SDOperand(N, 0); 695} 696 697SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, 698 SDOperand Operand) { 699 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Operand.Val)) { 700 uint64_t Val = C->getValue(); 701 switch (Opcode) { 702 default: break; 703 case ISD::SIGN_EXTEND: return getConstant(C->getSignExtended(), VT); 704 case ISD::ZERO_EXTEND: return getConstant(Val, VT); 705 case ISD::TRUNCATE: return getConstant(Val, VT); 706 case ISD::SINT_TO_FP: return getConstantFP(C->getSignExtended(), VT); 707 case ISD::UINT_TO_FP: return getConstantFP(C->getValue(), VT); 708 } 709 } 710 711 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Operand.Val)) 712 switch (Opcode) { 713 case ISD::FNEG: 714 return getConstantFP(-C->getValue(), VT); 715 case ISD::FP_ROUND: 716 case ISD::FP_EXTEND: 717 return getConstantFP(C->getValue(), VT); 718 case ISD::FP_TO_SINT: 719 return getConstant((int64_t)C->getValue(), VT); 720 case ISD::FP_TO_UINT: 721 return getConstant((uint64_t)C->getValue(), VT); 722 } 723 724 unsigned OpOpcode = Operand.Val->getOpcode(); 725 switch (Opcode) { 726 case ISD::TokenFactor: 727 return Operand; // Factor of one node? No factor. 728 case ISD::SIGN_EXTEND: 729 if (Operand.getValueType() == VT) return Operand; // noop extension 730 if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND) 731 return getNode(OpOpcode, VT, Operand.Val->getOperand(0)); 732 break; 733 case ISD::ZERO_EXTEND: 734 if (Operand.getValueType() == VT) return Operand; // noop extension 735 if (OpOpcode == ISD::ZERO_EXTEND) // (zext (zext x)) -> (zext x) 736 return getNode(ISD::ZERO_EXTEND, VT, Operand.Val->getOperand(0)); 737 break; 738 case ISD::TRUNCATE: 739 if (Operand.getValueType() == VT) return Operand; // noop truncate 740 if (OpOpcode == ISD::TRUNCATE) 741 return getNode(ISD::TRUNCATE, VT, Operand.Val->getOperand(0)); 742 else if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND) { 743 // If the source is smaller than the dest, we still need an extend. 744 if (Operand.Val->getOperand(0).getValueType() < VT) 745 return getNode(OpOpcode, VT, Operand.Val->getOperand(0)); 746 else if (Operand.Val->getOperand(0).getValueType() > VT) 747 return getNode(ISD::TRUNCATE, VT, Operand.Val->getOperand(0)); 748 else 749 return Operand.Val->getOperand(0); 750 } 751 break; 752 case ISD::FNEG: 753 if (OpOpcode == ISD::SUB) // -(X-Y) -> (Y-X) 754 return getNode(ISD::SUB, VT, Operand.Val->getOperand(1), 755 Operand.Val->getOperand(0)); 756 if (OpOpcode == ISD::FNEG) // --X -> X 757 return Operand.Val->getOperand(0); 758 break; 759 case ISD::FABS: 760 if (OpOpcode == ISD::FNEG) // abs(-X) -> abs(X) 761 return getNode(ISD::FABS, VT, Operand.Val->getOperand(0)); 762 break; 763 } 764 765 SDNode *&N = UnaryOps[std::make_pair(Opcode, std::make_pair(Operand, VT))]; 766 if (N) return SDOperand(N, 0); 767 N = new SDNode(Opcode, Operand); 768 N->setValueTypes(VT); 769 AllNodes.push_back(N); 770 return SDOperand(N, 0); 771} 772 773/// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero. We use 774/// this predicate to simplify operations downstream. V and Mask are known to 775/// be the same type. 776static bool MaskedValueIsZero(const SDOperand &Op, uint64_t Mask, 777 const TargetLowering &TLI) { 778 unsigned SrcBits; 779 if (Mask == 0) return true; 780 781 // If we know the result of a setcc has the top bits zero, use this info. 782 switch (Op.getOpcode()) { 783 case ISD::Constant: 784 return (cast<ConstantSDNode>(Op)->getValue() & Mask) == 0; 785 786 case ISD::SETCC: 787 return ((Mask & 1) == 0) && 788 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult; 789 790 case ISD::ZEXTLOAD: 791 SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(3))->getVT()); 792 return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits. 793 case ISD::ZERO_EXTEND: 794 SrcBits = MVT::getSizeInBits(Op.getOperand(0).getValueType()); 795 return MaskedValueIsZero(Op.getOperand(0),Mask & ((1ULL << SrcBits)-1),TLI); 796 797 case ISD::AND: 798 // (X & C1) & C2 == 0 iff C1 & C2 == 0. 799 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(Op.getOperand(1))) 800 return MaskedValueIsZero(Op.getOperand(0),AndRHS->getValue() & Mask, TLI); 801 802 // FALL THROUGH 803 case ISD::OR: 804 case ISD::XOR: 805 return MaskedValueIsZero(Op.getOperand(0), Mask, TLI) && 806 MaskedValueIsZero(Op.getOperand(1), Mask, TLI); 807 case ISD::SELECT: 808 return MaskedValueIsZero(Op.getOperand(1), Mask, TLI) && 809 MaskedValueIsZero(Op.getOperand(2), Mask, TLI); 810 811 case ISD::SRL: 812 // (ushr X, C1) & C2 == 0 iff X & (C2 << C1) == 0 813 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 814 uint64_t NewVal = Mask << ShAmt->getValue(); 815 SrcBits = MVT::getSizeInBits(Op.getValueType()); 816 if (SrcBits != 64) NewVal &= (1ULL << SrcBits)-1; 817 return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI); 818 } 819 return false; 820 case ISD::SHL: 821 // (ushl X, C1) & C2 == 0 iff X & (C2 >> C1) == 0 822 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 823 uint64_t NewVal = Mask >> ShAmt->getValue(); 824 return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI); 825 } 826 return false; 827 // TODO we could handle some SRA cases here. 828 default: break; 829 } 830 831 return false; 832} 833 834 835 836SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, 837 SDOperand N1, SDOperand N2) { 838#ifndef NDEBUG 839 switch (Opcode) { 840 case ISD::TokenFactor: 841 assert(VT == MVT::Other && N1.getValueType() == MVT::Other && 842 N2.getValueType() == MVT::Other && "Invalid token factor!"); 843 break; 844 case ISD::AND: 845 case ISD::OR: 846 case ISD::XOR: 847 case ISD::UDIV: 848 case ISD::UREM: 849 case ISD::MULHU: 850 case ISD::MULHS: 851 assert(MVT::isInteger(VT) && "This operator does not apply to FP types!"); 852 // fall through 853 case ISD::ADD: 854 case ISD::SUB: 855 case ISD::MUL: 856 case ISD::SDIV: 857 case ISD::SREM: 858 assert(N1.getValueType() == N2.getValueType() && 859 N1.getValueType() == VT && "Binary operator types must match!"); 860 break; 861 862 case ISD::SHL: 863 case ISD::SRA: 864 case ISD::SRL: 865 assert(VT == N1.getValueType() && 866 "Shift operators return type must be the same as their first arg"); 867 assert(MVT::isInteger(VT) && MVT::isInteger(N2.getValueType()) && 868 VT != MVT::i1 && "Shifts only work on integers"); 869 break; 870 case ISD::FP_ROUND_INREG: { 871 MVT::ValueType EVT = cast<VTSDNode>(N2)->getVT(); 872 assert(VT == N1.getValueType() && "Not an inreg round!"); 873 assert(MVT::isFloatingPoint(VT) && MVT::isFloatingPoint(EVT) && 874 "Cannot FP_ROUND_INREG integer types"); 875 assert(EVT <= VT && "Not rounding down!"); 876 break; 877 } 878 case ISD::SIGN_EXTEND_INREG: { 879 MVT::ValueType EVT = cast<VTSDNode>(N2)->getVT(); 880 assert(VT == N1.getValueType() && "Not an inreg extend!"); 881 assert(MVT::isInteger(VT) && MVT::isInteger(EVT) && 882 "Cannot *_EXTEND_INREG FP types"); 883 assert(EVT <= VT && "Not extending!"); 884 } 885 886 default: break; 887 } 888#endif 889 890 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 891 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 892 if (N1C) { 893 if (N2C) { 894 uint64_t C1 = N1C->getValue(), C2 = N2C->getValue(); 895 switch (Opcode) { 896 case ISD::ADD: return getConstant(C1 + C2, VT); 897 case ISD::SUB: return getConstant(C1 - C2, VT); 898 case ISD::MUL: return getConstant(C1 * C2, VT); 899 case ISD::UDIV: 900 if (C2) return getConstant(C1 / C2, VT); 901 break; 902 case ISD::UREM : 903 if (C2) return getConstant(C1 % C2, VT); 904 break; 905 case ISD::SDIV : 906 if (C2) return getConstant(N1C->getSignExtended() / 907 N2C->getSignExtended(), VT); 908 break; 909 case ISD::SREM : 910 if (C2) return getConstant(N1C->getSignExtended() % 911 N2C->getSignExtended(), VT); 912 break; 913 case ISD::AND : return getConstant(C1 & C2, VT); 914 case ISD::OR : return getConstant(C1 | C2, VT); 915 case ISD::XOR : return getConstant(C1 ^ C2, VT); 916 case ISD::SHL : return getConstant(C1 << (int)C2, VT); 917 case ISD::SRL : return getConstant(C1 >> (unsigned)C2, VT); 918 case ISD::SRA : return getConstant(N1C->getSignExtended() >>(int)C2, VT); 919 default: break; 920 } 921 922 } else { // Cannonicalize constant to RHS if commutative 923 if (isCommutativeBinOp(Opcode)) { 924 std::swap(N1C, N2C); 925 std::swap(N1, N2); 926 } 927 } 928 929 switch (Opcode) { 930 default: break; 931 case ISD::SHL: // shl 0, X -> 0 932 if (N1C->isNullValue()) return N1; 933 break; 934 case ISD::SRL: // srl 0, X -> 0 935 if (N1C->isNullValue()) return N1; 936 break; 937 case ISD::SRA: // sra -1, X -> -1 938 if (N1C->isAllOnesValue()) return N1; 939 break; 940 case ISD::SIGN_EXTEND_INREG: // SIGN_EXTEND_INREG N1C, EVT 941 // Extending a constant? Just return the extended constant. 942 SDOperand Tmp = getNode(ISD::TRUNCATE, cast<VTSDNode>(N2)->getVT(), N1); 943 return getNode(ISD::SIGN_EXTEND, VT, Tmp); 944 } 945 } 946 947 if (N2C) { 948 uint64_t C2 = N2C->getValue(); 949 950 switch (Opcode) { 951 case ISD::ADD: 952 if (!C2) return N1; // add X, 0 -> X 953 break; 954 case ISD::SUB: 955 if (!C2) return N1; // sub X, 0 -> X 956 return getNode(ISD::ADD, VT, N1, getConstant(-C2, VT)); 957 case ISD::MUL: 958 if (!C2) return N2; // mul X, 0 -> 0 959 if (N2C->isAllOnesValue()) // mul X, -1 -> 0-X 960 return getNode(ISD::SUB, VT, getConstant(0, VT), N1); 961 962 // FIXME: Move this to the DAG combiner when it exists. 963 if ((C2 & C2-1) == 0) { 964 SDOperand ShAmt = getConstant(Log2_64(C2), TLI.getShiftAmountTy()); 965 return getNode(ISD::SHL, VT, N1, ShAmt); 966 } 967 break; 968 969 case ISD::MULHU: 970 case ISD::MULHS: 971 if (!C2) return N2; // mul X, 0 -> 0 972 973 if (C2 == 1) // 0X*01 -> 0X hi(0X) == 0 974 return getConstant(0, VT); 975 976 // Many others could be handled here, including -1, powers of 2, etc. 977 break; 978 979 case ISD::UDIV: 980 // FIXME: Move this to the DAG combiner when it exists. 981 if ((C2 & C2-1) == 0 && C2) { 982 SDOperand ShAmt = getConstant(Log2_64(C2), TLI.getShiftAmountTy()); 983 return getNode(ISD::SRL, VT, N1, ShAmt); 984 } 985 break; 986 987 case ISD::SHL: 988 case ISD::SRL: 989 case ISD::SRA: 990 // If the shift amount is bigger than the size of the data, then all the 991 // bits are shifted out. Simplify to undef. 992 if (C2 >= MVT::getSizeInBits(N1.getValueType())) { 993 return getNode(ISD::UNDEF, N1.getValueType()); 994 } 995 if (C2 == 0) return N1; 996 997 if (Opcode == ISD::SHL && N1.getNumOperands() == 2) 998 if (ConstantSDNode *OpSA = dyn_cast<ConstantSDNode>(N1.getOperand(1))) { 999 unsigned OpSAC = OpSA->getValue(); 1000 if (N1.getOpcode() == ISD::SHL) { 1001 if (C2+OpSAC >= MVT::getSizeInBits(N1.getValueType())) 1002 return getConstant(0, N1.getValueType()); 1003 return getNode(ISD::SHL, N1.getValueType(), N1.getOperand(0), 1004 getConstant(C2+OpSAC, N2.getValueType())); 1005 } else if (N1.getOpcode() == ISD::SRL) { 1006 // (X >> C1) << C2: if C2 > C1, ((X & ~0<<C1) << C2-C1) 1007 SDOperand Mask = getNode(ISD::AND, VT, N1.getOperand(0), 1008 getConstant(~0ULL << OpSAC, VT)); 1009 if (C2 > OpSAC) { 1010 return getNode(ISD::SHL, VT, Mask, 1011 getConstant(C2-OpSAC, N2.getValueType())); 1012 } else { 1013 // (X >> C1) << C2: if C2 <= C1, ((X & ~0<<C1) >> C1-C2) 1014 return getNode(ISD::SRL, VT, Mask, 1015 getConstant(OpSAC-C2, N2.getValueType())); 1016 } 1017 } else if (N1.getOpcode() == ISD::SRA) { 1018 // if C1 == C2, just mask out low bits. 1019 if (C2 == OpSAC) 1020 return getNode(ISD::AND, VT, N1.getOperand(0), 1021 getConstant(~0ULL << C2, VT)); 1022 } 1023 } 1024 break; 1025 1026 case ISD::AND: 1027 if (!C2) return N2; // X and 0 -> 0 1028 if (N2C->isAllOnesValue()) 1029 return N1; // X and -1 -> X 1030 1031 if (MaskedValueIsZero(N1, C2, TLI)) // X and 0 -> 0 1032 return getConstant(0, VT); 1033 1034 { 1035 uint64_t NotC2 = ~C2; 1036 if (VT != MVT::i64) 1037 NotC2 &= (1ULL << MVT::getSizeInBits(VT))-1; 1038 1039 if (MaskedValueIsZero(N1, NotC2, TLI)) 1040 return N1; // if (X & ~C2) -> 0, the and is redundant 1041 } 1042 1043 // FIXME: Should add a corresponding version of this for 1044 // ZERO_EXTEND/SIGN_EXTEND by converting them to an ANY_EXTEND node which 1045 // we don't have yet. 1046 1047 // and (sign_extend_inreg x:16:32), 1 -> and x, 1 1048 if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) { 1049 // If we are masking out the part of our input that was extended, just 1050 // mask the input to the extension directly. 1051 unsigned ExtendBits = 1052 MVT::getSizeInBits(cast<VTSDNode>(N1.getOperand(1))->getVT()); 1053 if ((C2 & (~0ULL << ExtendBits)) == 0) 1054 return getNode(ISD::AND, VT, N1.getOperand(0), N2); 1055 } else if (N1.getOpcode() == ISD::OR) { 1056 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N1.getOperand(1))) 1057 if ((ORI->getValue() & C2) == C2) { 1058 // If the 'or' is setting all of the bits that we are masking for, 1059 // we know the result of the AND will be the AND mask itself. 1060 return N2; 1061 } 1062 } 1063 break; 1064 case ISD::OR: 1065 if (!C2)return N1; // X or 0 -> X 1066 if (N2C->isAllOnesValue()) 1067 return N2; // X or -1 -> -1 1068 break; 1069 case ISD::XOR: 1070 if (!C2) return N1; // X xor 0 -> X 1071 if (N2C->isAllOnesValue()) { 1072 if (N1.Val->getOpcode() == ISD::SETCC){ 1073 SDNode *SetCC = N1.Val; 1074 // !(X op Y) -> (X !op Y) 1075 bool isInteger = MVT::isInteger(SetCC->getOperand(0).getValueType()); 1076 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC->getOperand(2))->get(); 1077 return getSetCC(SetCC->getValueType(0), 1078 SetCC->getOperand(0), SetCC->getOperand(1), 1079 ISD::getSetCCInverse(CC, isInteger)); 1080 } else if (N1.getOpcode() == ISD::AND || N1.getOpcode() == ISD::OR) { 1081 SDNode *Op = N1.Val; 1082 // !(X or Y) -> (!X and !Y) iff X or Y are freely invertible 1083 // !(X and Y) -> (!X or !Y) iff X or Y are freely invertible 1084 SDOperand LHS = Op->getOperand(0), RHS = Op->getOperand(1); 1085 if (isInvertibleForFree(RHS) || isInvertibleForFree(LHS)) { 1086 LHS = getNode(ISD::XOR, VT, LHS, N2); // RHS = ~LHS 1087 RHS = getNode(ISD::XOR, VT, RHS, N2); // RHS = ~RHS 1088 if (Op->getOpcode() == ISD::AND) 1089 return getNode(ISD::OR, VT, LHS, RHS); 1090 return getNode(ISD::AND, VT, LHS, RHS); 1091 } 1092 } 1093 // X xor -1 -> not(x) ? 1094 } 1095 break; 1096 } 1097 1098 // Reassociate ((X op C1) op C2) if possible. 1099 if (N1.getOpcode() == Opcode && isAssociativeBinOp(Opcode)) 1100 if (ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N1.Val->getOperand(1))) 1101 return getNode(Opcode, VT, N1.Val->getOperand(0), 1102 getNode(Opcode, VT, N2, N1.Val->getOperand(1))); 1103 } 1104 1105 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1.Val); 1106 ConstantFPSDNode *N2CFP = dyn_cast<ConstantFPSDNode>(N2.Val); 1107 if (N1CFP) { 1108 if (N2CFP) { 1109 double C1 = N1CFP->getValue(), C2 = N2CFP->getValue(); 1110 switch (Opcode) { 1111 case ISD::ADD: return getConstantFP(C1 + C2, VT); 1112 case ISD::SUB: return getConstantFP(C1 - C2, VT); 1113 case ISD::MUL: return getConstantFP(C1 * C2, VT); 1114 case ISD::SDIV: 1115 if (C2) return getConstantFP(C1 / C2, VT); 1116 break; 1117 case ISD::SREM : 1118 if (C2) return getConstantFP(fmod(C1, C2), VT); 1119 break; 1120 default: break; 1121 } 1122 1123 } else { // Cannonicalize constant to RHS if commutative 1124 if (isCommutativeBinOp(Opcode)) { 1125 std::swap(N1CFP, N2CFP); 1126 std::swap(N1, N2); 1127 } 1128 } 1129 1130 if (Opcode == ISD::FP_ROUND_INREG) 1131 return getNode(ISD::FP_EXTEND, VT, 1132 getNode(ISD::FP_ROUND, cast<VTSDNode>(N2)->getVT(), N1)); 1133 } 1134 1135 // Finally, fold operations that do not require constants. 1136 switch (Opcode) { 1137 case ISD::TokenFactor: 1138 if (N1.getOpcode() == ISD::EntryToken) 1139 return N2; 1140 if (N2.getOpcode() == ISD::EntryToken) 1141 return N1; 1142 break; 1143 1144 case ISD::AND: 1145 case ISD::OR: 1146 if (N1.Val->getOpcode() == ISD::SETCC && N2.Val->getOpcode() == ISD::SETCC){ 1147 SDNode *LHS = N1.Val, *RHS = N2.Val; 1148 SDOperand LL = LHS->getOperand(0), RL = RHS->getOperand(0); 1149 SDOperand LR = LHS->getOperand(1), RR = RHS->getOperand(1); 1150 ISD::CondCode Op1 = cast<CondCodeSDNode>(LHS->getOperand(2))->get(); 1151 ISD::CondCode Op2 = cast<CondCodeSDNode>(RHS->getOperand(2))->get(); 1152 1153 if (LR == RR && isa<ConstantSDNode>(LR) && 1154 Op2 == Op1 && MVT::isInteger(LL.getValueType())) { 1155 // (X != 0) | (Y != 0) -> (X|Y != 0) 1156 // (X == 0) & (Y == 0) -> (X|Y == 0) 1157 // (X < 0) | (Y < 0) -> (X|Y < 0) 1158 if (cast<ConstantSDNode>(LR)->getValue() == 0 && 1159 ((Op2 == ISD::SETEQ && Opcode == ISD::AND) || 1160 (Op2 == ISD::SETNE && Opcode == ISD::OR) || 1161 (Op2 == ISD::SETLT && Opcode == ISD::OR))) 1162 return getSetCC(VT, getNode(ISD::OR, LR.getValueType(), LL, RL), LR, 1163 Op2); 1164 1165 if (cast<ConstantSDNode>(LR)->isAllOnesValue()) { 1166 // (X == -1) & (Y == -1) -> (X&Y == -1) 1167 // (X != -1) | (Y != -1) -> (X&Y != -1) 1168 // (X > -1) | (Y > -1) -> (X&Y > -1) 1169 if ((Opcode == ISD::AND && Op2 == ISD::SETEQ) || 1170 (Opcode == ISD::OR && Op2 == ISD::SETNE) || 1171 (Opcode == ISD::OR && Op2 == ISD::SETGT)) 1172 return getSetCC(VT, getNode(ISD::AND, LR.getValueType(), LL, RL), 1173 LR, Op2); 1174 // (X > -1) & (Y > -1) -> (X|Y > -1) 1175 if (Opcode == ISD::AND && Op2 == ISD::SETGT) 1176 return getSetCC(VT, getNode(ISD::OR, LR.getValueType(), LL, RL), 1177 LR, Op2); 1178 } 1179 } 1180 1181 // (X op1 Y) | (Y op2 X) -> (X op1 Y) | (X swapop2 Y) 1182 if (LL == RR && LR == RL) { 1183 Op2 = ISD::getSetCCSwappedOperands(Op2); 1184 goto MatchedBackwards; 1185 } 1186 1187 if (LL == RL && LR == RR) { 1188 MatchedBackwards: 1189 ISD::CondCode Result; 1190 bool isInteger = MVT::isInteger(LL.getValueType()); 1191 if (Opcode == ISD::OR) 1192 Result = ISD::getSetCCOrOperation(Op1, Op2, isInteger); 1193 else 1194 Result = ISD::getSetCCAndOperation(Op1, Op2, isInteger); 1195 1196 if (Result != ISD::SETCC_INVALID) 1197 return getSetCC(LHS->getValueType(0), LL, LR, Result); 1198 } 1199 } 1200 1201 // and/or zext(a), zext(b) -> zext(and/or a, b) 1202 if (N1.getOpcode() == ISD::ZERO_EXTEND && 1203 N2.getOpcode() == ISD::ZERO_EXTEND && 1204 N1.getOperand(0).getValueType() == N2.getOperand(0).getValueType()) 1205 return getNode(ISD::ZERO_EXTEND, VT, 1206 getNode(Opcode, N1.getOperand(0).getValueType(), 1207 N1.getOperand(0), N2.getOperand(0))); 1208 break; 1209 case ISD::XOR: 1210 if (N1 == N2) return getConstant(0, VT); // xor X, Y -> 0 1211 break; 1212 case ISD::ADD: 1213 if (N2.getOpcode() == ISD::FNEG) // (A+ (-B) -> A-B 1214 return getNode(ISD::SUB, VT, N1, N2.getOperand(0)); 1215 if (N1.getOpcode() == ISD::FNEG) // ((-A)+B) -> B-A 1216 return getNode(ISD::SUB, VT, N2, N1.getOperand(0)); 1217 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 1218 cast<ConstantSDNode>(N1.getOperand(0))->getValue() == 0) 1219 return getNode(ISD::SUB, VT, N2, N1.getOperand(1)); // (0-A)+B -> B-A 1220 if (N2.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N2.getOperand(0)) && 1221 cast<ConstantSDNode>(N2.getOperand(0))->getValue() == 0) 1222 return getNode(ISD::SUB, VT, N1, N2.getOperand(1)); // A+(0-B) -> A-B 1223 if (N2.getOpcode() == ISD::SUB && N1 == N2.Val->getOperand(1) && 1224 !MVT::isFloatingPoint(N2.getValueType())) 1225 return N2.Val->getOperand(0); // A+(B-A) -> B 1226 break; 1227 case ISD::SUB: 1228 if (N1.getOpcode() == ISD::ADD) { 1229 if (N1.Val->getOperand(0) == N2 && 1230 !MVT::isFloatingPoint(N2.getValueType())) 1231 return N1.Val->getOperand(1); // (A+B)-A == B 1232 if (N1.Val->getOperand(1) == N2 && 1233 !MVT::isFloatingPoint(N2.getValueType())) 1234 return N1.Val->getOperand(0); // (A+B)-B == A 1235 } 1236 if (N2.getOpcode() == ISD::FNEG) // (A- (-B) -> A+B 1237 return getNode(ISD::ADD, VT, N1, N2.getOperand(0)); 1238 break; 1239 case ISD::FP_ROUND_INREG: 1240 if (cast<VTSDNode>(N2)->getVT() == VT) return N1; // Not actually rounding. 1241 break; 1242 case ISD::SIGN_EXTEND_INREG: { 1243 MVT::ValueType EVT = cast<VTSDNode>(N2)->getVT(); 1244 if (EVT == VT) return N1; // Not actually extending 1245 1246 // If we are sign extending an extension, use the original source. 1247 if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) 1248 if (cast<VTSDNode>(N1.getOperand(1))->getVT() <= EVT) 1249 return N1; 1250 1251 // If we are sign extending a sextload, return just the load. 1252 if (N1.getOpcode() == ISD::SEXTLOAD) 1253 if (cast<VTSDNode>(N1.getOperand(3))->getVT() <= EVT) 1254 return N1; 1255 1256 // If we are extending the result of a setcc, and we already know the 1257 // contents of the top bits, eliminate the extension. 1258 if (N1.getOpcode() == ISD::SETCC && 1259 TLI.getSetCCResultContents() == 1260 TargetLowering::ZeroOrNegativeOneSetCCResult) 1261 return N1; 1262 1263 // If we are sign extending the result of an (and X, C) operation, and we 1264 // know the extended bits are zeros already, don't do the extend. 1265 if (N1.getOpcode() == ISD::AND) 1266 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getOperand(1))) { 1267 uint64_t Mask = N1C->getValue(); 1268 unsigned NumBits = MVT::getSizeInBits(EVT); 1269 if ((Mask & (~0ULL << (NumBits-1))) == 0) 1270 return N1; 1271 } 1272 break; 1273 } 1274 1275 // FIXME: figure out how to safely handle things like 1276 // int foo(int x) { return 1 << (x & 255); } 1277 // int bar() { return foo(256); } 1278#if 0 1279 case ISD::SHL: 1280 case ISD::SRL: 1281 case ISD::SRA: 1282 if (N2.getOpcode() == ISD::SIGN_EXTEND_INREG && 1283 cast<VTSDNode>(N2.getOperand(1))->getVT() != MVT::i1) 1284 return getNode(Opcode, VT, N1, N2.getOperand(0)); 1285 else if (N2.getOpcode() == ISD::AND) 1286 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(N2.getOperand(1))) { 1287 // If the and is only masking out bits that cannot effect the shift, 1288 // eliminate the and. 1289 unsigned NumBits = MVT::getSizeInBits(VT); 1290 if ((AndRHS->getValue() & (NumBits-1)) == NumBits-1) 1291 return getNode(Opcode, VT, N1, N2.getOperand(0)); 1292 } 1293 break; 1294#endif 1295 } 1296 1297 // Memoize this node if possible. 1298 SDNode *N; 1299 if (Opcode != ISD::CALLSEQ_START && Opcode != ISD::CALLSEQ_END) { 1300 SDNode *&BON = BinaryOps[std::make_pair(Opcode, std::make_pair(N1, N2))]; 1301 if (BON) return SDOperand(BON, 0); 1302 1303 BON = N = new SDNode(Opcode, N1, N2); 1304 } else { 1305 N = new SDNode(Opcode, N1, N2); 1306 } 1307 1308 N->setValueTypes(VT); 1309 AllNodes.push_back(N); 1310 return SDOperand(N, 0); 1311} 1312 1313// setAdjCallChain - This method changes the token chain of an 1314// CALLSEQ_START/END node to be the specified operand. 1315void SDNode::setAdjCallChain(SDOperand N) { 1316 assert(N.getValueType() == MVT::Other); 1317 assert((getOpcode() == ISD::CALLSEQ_START || 1318 getOpcode() == ISD::CALLSEQ_END) && "Cannot adjust this node!"); 1319 1320 Operands[0].Val->removeUser(this); 1321 Operands[0] = N; 1322 N.Val->Uses.push_back(this); 1323} 1324 1325 1326 1327SDOperand SelectionDAG::getLoad(MVT::ValueType VT, 1328 SDOperand Chain, SDOperand Ptr, 1329 SDOperand SV) { 1330 SDNode *&N = Loads[std::make_pair(Ptr, std::make_pair(Chain, VT))]; 1331 if (N) return SDOperand(N, 0); 1332 N = new SDNode(ISD::LOAD, Chain, Ptr, SV); 1333 1334 // Loads have a token chain. 1335 N->setValueTypes(VT, MVT::Other); 1336 AllNodes.push_back(N); 1337 return SDOperand(N, 0); 1338} 1339 1340 1341SDOperand SelectionDAG::getExtLoad(unsigned Opcode, MVT::ValueType VT, 1342 SDOperand Chain, SDOperand Ptr, SDOperand SV, 1343 MVT::ValueType EVT) { 1344 std::vector<SDOperand> Ops; 1345 Ops.reserve(4); 1346 Ops.push_back(Chain); 1347 Ops.push_back(Ptr); 1348 Ops.push_back(SV); 1349 Ops.push_back(getValueType(EVT)); 1350 std::vector<MVT::ValueType> VTs; 1351 VTs.reserve(2); 1352 VTs.push_back(VT); VTs.push_back(MVT::Other); // Add token chain. 1353 return getNode(Opcode, VTs, Ops); 1354} 1355 1356SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, 1357 SDOperand N1, SDOperand N2, SDOperand N3) { 1358 // Perform various simplifications. 1359 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1360 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 1361 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val); 1362 switch (Opcode) { 1363 case ISD::SETCC: { 1364 // Use SimplifySetCC to simplify SETCC's. 1365 SDOperand Simp = SimplifySetCC(VT, N1, N2, cast<CondCodeSDNode>(N3)->get()); 1366 if (Simp.Val) return Simp; 1367 break; 1368 } 1369 case ISD::SELECT: 1370 if (N1C) 1371 if (N1C->getValue()) 1372 return N2; // select true, X, Y -> X 1373 else 1374 return N3; // select false, X, Y -> Y 1375 1376 if (N2 == N3) return N2; // select C, X, X -> X 1377 1378 if (VT == MVT::i1) { // Boolean SELECT 1379 if (N2C) { 1380 if (N2C->getValue()) // select C, 1, X -> C | X 1381 return getNode(ISD::OR, VT, N1, N3); 1382 else // select C, 0, X -> ~C & X 1383 return getNode(ISD::AND, VT, 1384 getNode(ISD::XOR, N1.getValueType(), N1, 1385 getConstant(1, N1.getValueType())), N3); 1386 } else if (N3C) { 1387 if (N3C->getValue()) // select C, X, 1 -> ~C | X 1388 return getNode(ISD::OR, VT, 1389 getNode(ISD::XOR, N1.getValueType(), N1, 1390 getConstant(1, N1.getValueType())), N2); 1391 else // select C, X, 0 -> C & X 1392 return getNode(ISD::AND, VT, N1, N2); 1393 } 1394 1395 if (N1 == N2) // X ? X : Y --> X ? 1 : Y --> X | Y 1396 return getNode(ISD::OR, VT, N1, N3); 1397 if (N1 == N3) // X ? Y : X --> X ? Y : 0 --> X & Y 1398 return getNode(ISD::AND, VT, N1, N2); 1399 } 1400 break; 1401 case ISD::BRCOND: 1402 if (N2C) 1403 if (N2C->getValue()) // Unconditional branch 1404 return getNode(ISD::BR, MVT::Other, N1, N3); 1405 else 1406 return N1; // Never-taken branch 1407 break; 1408 } 1409 1410 std::vector<SDOperand> Ops; 1411 Ops.reserve(3); 1412 Ops.push_back(N1); 1413 Ops.push_back(N2); 1414 Ops.push_back(N3); 1415 1416 // Memoize nodes. 1417 SDNode *&N = OneResultNodes[std::make_pair(Opcode, std::make_pair(VT, Ops))]; 1418 if (N) return SDOperand(N, 0); 1419 1420 N = new SDNode(Opcode, N1, N2, N3); 1421 N->setValueTypes(VT); 1422 AllNodes.push_back(N); 1423 return SDOperand(N, 0); 1424} 1425 1426SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, 1427 SDOperand N1, SDOperand N2, SDOperand N3, 1428 SDOperand N4) { 1429 std::vector<SDOperand> Ops; 1430 Ops.reserve(4); 1431 Ops.push_back(N1); 1432 Ops.push_back(N2); 1433 Ops.push_back(N3); 1434 Ops.push_back(N4); 1435 return getNode(Opcode, VT, Ops); 1436} 1437 1438SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, 1439 SDOperand N1, SDOperand N2, SDOperand N3, 1440 SDOperand N4, SDOperand N5) { 1441 if (ISD::SELECT_CC == Opcode) { 1442 assert(N1.getValueType() == N2.getValueType() && 1443 "LHS and RHS of condition must have same type!"); 1444 assert(N3.getValueType() == N4.getValueType() && 1445 "True and False arms of SelectCC must have same type!"); 1446 1447 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 1448 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val); 1449 ConstantSDNode *N4C = dyn_cast<ConstantSDNode>(N4.Val); 1450 ISD::CondCode CC = cast<CondCodeSDNode>(N5)->get(); 1451 1452 // Check to see if we can simplify the select into an fabs node 1453 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N2)) { 1454 // Allow either -0.0 or 0.0 1455 if (CFP->getValue() == 0.0) { 1456 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 1457 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 1458 N1 == N3 && N4.getOpcode() == ISD::FNEG && 1459 N1 == N4.getOperand(0)) 1460 return getNode(ISD::FABS, VT, N1); 1461 1462 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 1463 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 1464 N1 == N4 && N3.getOpcode() == ISD::FNEG && 1465 N3.getOperand(0) == N4) 1466 return getNode(ISD::FABS, VT, N4); 1467 } 1468 } 1469 1470 // Check to see if we can perform the "gzip trick", transforming 1471 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A 1472 if (N2C && N2C->isNullValue() && N4C && N4C->isNullValue() && 1473 MVT::isInteger(N1.getValueType()) && 1474 MVT::isInteger(N3.getValueType()) && CC == ISD::SETLT) { 1475 MVT::ValueType XType = N1.getValueType(); 1476 MVT::ValueType AType = N3.getValueType(); 1477 if (XType >= AType) { 1478 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 1479 // single-bit constant. FIXME: remove once the dag combiner 1480 // exists. 1481 if (N3C && ((N3C->getValue() & (N3C->getValue()-1)) == 0)) { 1482 unsigned ShCtV = Log2_64(N3C->getValue()); 1483 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1; 1484 SDOperand ShCt = getConstant(ShCtV, TLI.getShiftAmountTy()); 1485 SDOperand Shift = getNode(ISD::SRL, XType, N1, ShCt); 1486 if (XType > AType) 1487 Shift = getNode(ISD::TRUNCATE, AType, Shift); 1488 return getNode(ISD::AND, AType, Shift, N3); 1489 } 1490 SDOperand Shift = getNode(ISD::SRA, XType, N1, 1491 getConstant(MVT::getSizeInBits(XType)-1, 1492 TLI.getShiftAmountTy())); 1493 if (XType > AType) 1494 Shift = getNode(ISD::TRUNCATE, AType, Shift); 1495 return getNode(ISD::AND, AType, Shift, N3); 1496 } 1497 } 1498 } 1499 1500 std::vector<SDOperand> Ops; 1501 Ops.reserve(5); 1502 Ops.push_back(N1); 1503 Ops.push_back(N2); 1504 Ops.push_back(N3); 1505 Ops.push_back(N4); 1506 Ops.push_back(N5); 1507 return getNode(Opcode, VT, Ops); 1508} 1509 1510 1511SDOperand SelectionDAG::getSrcValue(const Value *V, int Offset) { 1512 assert((!V || isa<PointerType>(V->getType())) && 1513 "SrcValue is not a pointer?"); 1514 SDNode *&N = ValueNodes[std::make_pair(V, Offset)]; 1515 if (N) return SDOperand(N, 0); 1516 1517 N = new SrcValueSDNode(V, Offset); 1518 AllNodes.push_back(N); 1519 return SDOperand(N, 0); 1520} 1521 1522SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, 1523 std::vector<SDOperand> &Ops) { 1524 switch (Ops.size()) { 1525 case 0: return getNode(Opcode, VT); 1526 case 1: return getNode(Opcode, VT, Ops[0]); 1527 case 2: return getNode(Opcode, VT, Ops[0], Ops[1]); 1528 case 3: return getNode(Opcode, VT, Ops[0], Ops[1], Ops[2]); 1529 default: break; 1530 } 1531 1532 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Ops[1].Val); 1533 switch (Opcode) { 1534 default: break; 1535 case ISD::BRCONDTWOWAY: 1536 if (N1C) 1537 if (N1C->getValue()) // Unconditional branch to true dest. 1538 return getNode(ISD::BR, MVT::Other, Ops[0], Ops[2]); 1539 else // Unconditional branch to false dest. 1540 return getNode(ISD::BR, MVT::Other, Ops[0], Ops[3]); 1541 break; 1542 1543 case ISD::TRUNCSTORE: { 1544 assert(Ops.size() == 5 && "TRUNCSTORE takes 5 operands!"); 1545 MVT::ValueType EVT = cast<VTSDNode>(Ops[4])->getVT(); 1546#if 0 // FIXME: If the target supports EVT natively, convert to a truncate/store 1547 // If this is a truncating store of a constant, convert to the desired type 1548 // and store it instead. 1549 if (isa<Constant>(Ops[0])) { 1550 SDOperand Op = getNode(ISD::TRUNCATE, EVT, N1); 1551 if (isa<Constant>(Op)) 1552 N1 = Op; 1553 } 1554 // Also for ConstantFP? 1555#endif 1556 if (Ops[0].getValueType() == EVT) // Normal store? 1557 return getNode(ISD::STORE, VT, Ops[0], Ops[1], Ops[2], Ops[3]); 1558 assert(Ops[1].getValueType() > EVT && "Not a truncation?"); 1559 assert(MVT::isInteger(Ops[1].getValueType()) == MVT::isInteger(EVT) && 1560 "Can't do FP-INT conversion!"); 1561 break; 1562 } 1563 } 1564 1565 // Memoize nodes. 1566 SDNode *&N = OneResultNodes[std::make_pair(Opcode, std::make_pair(VT, Ops))]; 1567 if (N) return SDOperand(N, 0); 1568 N = new SDNode(Opcode, Ops); 1569 N->setValueTypes(VT); 1570 AllNodes.push_back(N); 1571 return SDOperand(N, 0); 1572} 1573 1574SDOperand SelectionDAG::getNode(unsigned Opcode, 1575 std::vector<MVT::ValueType> &ResultTys, 1576 std::vector<SDOperand> &Ops) { 1577 if (ResultTys.size() == 1) 1578 return getNode(Opcode, ResultTys[0], Ops); 1579 1580 switch (Opcode) { 1581 case ISD::EXTLOAD: 1582 case ISD::SEXTLOAD: 1583 case ISD::ZEXTLOAD: { 1584 MVT::ValueType EVT = cast<VTSDNode>(Ops[3])->getVT(); 1585 assert(Ops.size() == 4 && ResultTys.size() == 2 && "Bad *EXTLOAD!"); 1586 // If they are asking for an extending load from/to the same thing, return a 1587 // normal load. 1588 if (ResultTys[0] == EVT) 1589 return getLoad(ResultTys[0], Ops[0], Ops[1], Ops[2]); 1590 assert(EVT < ResultTys[0] && 1591 "Should only be an extending load, not truncating!"); 1592 assert((Opcode == ISD::EXTLOAD || MVT::isInteger(ResultTys[0])) && 1593 "Cannot sign/zero extend a FP load!"); 1594 assert(MVT::isInteger(ResultTys[0]) == MVT::isInteger(EVT) && 1595 "Cannot convert from FP to Int or Int -> FP!"); 1596 break; 1597 } 1598 1599 // FIXME: figure out how to safely handle things like 1600 // int foo(int x) { return 1 << (x & 255); } 1601 // int bar() { return foo(256); } 1602#if 0 1603 case ISD::SRA_PARTS: 1604 case ISD::SRL_PARTS: 1605 case ISD::SHL_PARTS: 1606 if (N3.getOpcode() == ISD::SIGN_EXTEND_INREG && 1607 cast<VTSDNode>(N3.getOperand(1))->getVT() != MVT::i1) 1608 return getNode(Opcode, VT, N1, N2, N3.getOperand(0)); 1609 else if (N3.getOpcode() == ISD::AND) 1610 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(N3.getOperand(1))) { 1611 // If the and is only masking out bits that cannot effect the shift, 1612 // eliminate the and. 1613 unsigned NumBits = MVT::getSizeInBits(VT)*2; 1614 if ((AndRHS->getValue() & (NumBits-1)) == NumBits-1) 1615 return getNode(Opcode, VT, N1, N2, N3.getOperand(0)); 1616 } 1617 break; 1618#endif 1619 } 1620 1621 // Memoize the node. 1622 SDNode *&N = ArbitraryNodes[std::make_pair(Opcode, std::make_pair(ResultTys, 1623 Ops))]; 1624 if (N) return SDOperand(N, 0); 1625 N = new SDNode(Opcode, Ops); 1626 N->setValueTypes(ResultTys); 1627 AllNodes.push_back(N); 1628 return SDOperand(N, 0); 1629} 1630 1631/// hasNUsesOfValue - Return true if there are exactly NUSES uses of the 1632/// indicated value. This method ignores uses of other values defined by this 1633/// operation. 1634bool SDNode::hasNUsesOfValue(unsigned NUses, unsigned Value) { 1635 assert(Value < getNumValues() && "Bad value!"); 1636 1637 // If there is only one value, this is easy. 1638 if (getNumValues() == 1) 1639 return use_size() == NUses; 1640 if (Uses.size() < NUses) return false; 1641 1642 SDOperand TheValue(this, Value); 1643 1644 std::set<SDNode*> UsersHandled; 1645 1646 for (std::vector<SDNode*>::iterator UI = Uses.begin(), E = Uses.end(); 1647 UI != E; ++UI) { 1648 SDNode *User = *UI; 1649 if (User->getNumOperands() == 1 || 1650 UsersHandled.insert(User).second) // First time we've seen this? 1651 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 1652 if (User->getOperand(i) == TheValue) { 1653 if (NUses == 0) 1654 return false; // too many uses 1655 --NUses; 1656 } 1657 } 1658 1659 // Found exactly the right number of uses? 1660 return NUses == 0; 1661} 1662 1663 1664const char *SDNode::getOperationName() const { 1665 switch (getOpcode()) { 1666 default: return "<<Unknown>>"; 1667 case ISD::PCMARKER: return "PCMarker"; 1668 case ISD::SRCVALUE: return "SrcValue"; 1669 case ISD::EntryToken: return "EntryToken"; 1670 case ISD::TokenFactor: return "TokenFactor"; 1671 case ISD::Constant: return "Constant"; 1672 case ISD::ConstantFP: return "ConstantFP"; 1673 case ISD::GlobalAddress: return "GlobalAddress"; 1674 case ISD::FrameIndex: return "FrameIndex"; 1675 case ISD::BasicBlock: return "BasicBlock"; 1676 case ISD::ExternalSymbol: return "ExternalSymbol"; 1677 case ISD::ConstantPool: return "ConstantPoolIndex"; 1678 case ISD::CopyToReg: return "CopyToReg"; 1679 case ISD::CopyFromReg: return "CopyFromReg"; 1680 case ISD::ImplicitDef: return "ImplicitDef"; 1681 case ISD::UNDEF: return "undef"; 1682 1683 // Unary operators 1684 case ISD::FABS: return "fabs"; 1685 case ISD::FNEG: return "fneg"; 1686 case ISD::FSQRT: return "fsqrt"; 1687 case ISD::FSIN: return "fsin"; 1688 case ISD::FCOS: return "fcos"; 1689 1690 // Binary operators 1691 case ISD::ADD: return "add"; 1692 case ISD::SUB: return "sub"; 1693 case ISD::MUL: return "mul"; 1694 case ISD::MULHU: return "mulhu"; 1695 case ISD::MULHS: return "mulhs"; 1696 case ISD::SDIV: return "sdiv"; 1697 case ISD::UDIV: return "udiv"; 1698 case ISD::SREM: return "srem"; 1699 case ISD::UREM: return "urem"; 1700 case ISD::AND: return "and"; 1701 case ISD::OR: return "or"; 1702 case ISD::XOR: return "xor"; 1703 case ISD::SHL: return "shl"; 1704 case ISD::SRA: return "sra"; 1705 case ISD::SRL: return "srl"; 1706 1707 case ISD::SETCC: return "setcc"; 1708 case ISD::SELECT: return "select"; 1709 case ISD::SELECT_CC: return "select_cc"; 1710 case ISD::ADD_PARTS: return "add_parts"; 1711 case ISD::SUB_PARTS: return "sub_parts"; 1712 case ISD::SHL_PARTS: return "shl_parts"; 1713 case ISD::SRA_PARTS: return "sra_parts"; 1714 case ISD::SRL_PARTS: return "srl_parts"; 1715 1716 // Conversion operators. 1717 case ISD::SIGN_EXTEND: return "sign_extend"; 1718 case ISD::ZERO_EXTEND: return "zero_extend"; 1719 case ISD::SIGN_EXTEND_INREG: return "sign_extend_inreg"; 1720 case ISD::TRUNCATE: return "truncate"; 1721 case ISD::FP_ROUND: return "fp_round"; 1722 case ISD::FP_ROUND_INREG: return "fp_round_inreg"; 1723 case ISD::FP_EXTEND: return "fp_extend"; 1724 1725 case ISD::SINT_TO_FP: return "sint_to_fp"; 1726 case ISD::UINT_TO_FP: return "uint_to_fp"; 1727 case ISD::FP_TO_SINT: return "fp_to_sint"; 1728 case ISD::FP_TO_UINT: return "fp_to_uint"; 1729 1730 // Control flow instructions 1731 case ISD::BR: return "br"; 1732 case ISD::BRCOND: return "brcond"; 1733 case ISD::BRCONDTWOWAY: return "brcondtwoway"; 1734 case ISD::RET: return "ret"; 1735 case ISD::CALL: return "call"; 1736 case ISD::TAILCALL:return "tailcall"; 1737 case ISD::CALLSEQ_START: return "callseq_start"; 1738 case ISD::CALLSEQ_END: return "callseq_end"; 1739 1740 // Other operators 1741 case ISD::LOAD: return "load"; 1742 case ISD::STORE: return "store"; 1743 case ISD::EXTLOAD: return "extload"; 1744 case ISD::SEXTLOAD: return "sextload"; 1745 case ISD::ZEXTLOAD: return "zextload"; 1746 case ISD::TRUNCSTORE: return "truncstore"; 1747 1748 case ISD::DYNAMIC_STACKALLOC: return "dynamic_stackalloc"; 1749 case ISD::EXTRACT_ELEMENT: return "extract_element"; 1750 case ISD::BUILD_PAIR: return "build_pair"; 1751 case ISD::MEMSET: return "memset"; 1752 case ISD::MEMCPY: return "memcpy"; 1753 case ISD::MEMMOVE: return "memmove"; 1754 1755 // Bit counting 1756 case ISD::CTPOP: return "ctpop"; 1757 case ISD::CTTZ: return "cttz"; 1758 case ISD::CTLZ: return "ctlz"; 1759 1760 // IO Intrinsics 1761 case ISD::READPORT: return "readport"; 1762 case ISD::WRITEPORT: return "writeport"; 1763 case ISD::READIO: return "readio"; 1764 case ISD::WRITEIO: return "writeio"; 1765 1766 case ISD::CONDCODE: 1767 switch (cast<CondCodeSDNode>(this)->get()) { 1768 default: assert(0 && "Unknown setcc condition!"); 1769 case ISD::SETOEQ: return "setoeq"; 1770 case ISD::SETOGT: return "setogt"; 1771 case ISD::SETOGE: return "setoge"; 1772 case ISD::SETOLT: return "setolt"; 1773 case ISD::SETOLE: return "setole"; 1774 case ISD::SETONE: return "setone"; 1775 1776 case ISD::SETO: return "seto"; 1777 case ISD::SETUO: return "setuo"; 1778 case ISD::SETUEQ: return "setue"; 1779 case ISD::SETUGT: return "setugt"; 1780 case ISD::SETUGE: return "setuge"; 1781 case ISD::SETULT: return "setult"; 1782 case ISD::SETULE: return "setule"; 1783 case ISD::SETUNE: return "setune"; 1784 1785 case ISD::SETEQ: return "seteq"; 1786 case ISD::SETGT: return "setgt"; 1787 case ISD::SETGE: return "setge"; 1788 case ISD::SETLT: return "setlt"; 1789 case ISD::SETLE: return "setle"; 1790 case ISD::SETNE: return "setne"; 1791 } 1792 } 1793} 1794 1795void SDNode::dump() const { 1796 std::cerr << (void*)this << ": "; 1797 1798 for (unsigned i = 0, e = getNumValues(); i != e; ++i) { 1799 if (i) std::cerr << ","; 1800 if (getValueType(i) == MVT::Other) 1801 std::cerr << "ch"; 1802 else 1803 std::cerr << MVT::getValueTypeString(getValueType(i)); 1804 } 1805 std::cerr << " = " << getOperationName(); 1806 1807 std::cerr << " "; 1808 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1809 if (i) std::cerr << ", "; 1810 std::cerr << (void*)getOperand(i).Val; 1811 if (unsigned RN = getOperand(i).ResNo) 1812 std::cerr << ":" << RN; 1813 } 1814 1815 if (const ConstantSDNode *CSDN = dyn_cast<ConstantSDNode>(this)) { 1816 std::cerr << "<" << CSDN->getValue() << ">"; 1817 } else if (const ConstantFPSDNode *CSDN = dyn_cast<ConstantFPSDNode>(this)) { 1818 std::cerr << "<" << CSDN->getValue() << ">"; 1819 } else if (const GlobalAddressSDNode *GADN = 1820 dyn_cast<GlobalAddressSDNode>(this)) { 1821 std::cerr << "<"; 1822 WriteAsOperand(std::cerr, GADN->getGlobal()) << ">"; 1823 } else if (const FrameIndexSDNode *FIDN = dyn_cast<FrameIndexSDNode>(this)) { 1824 std::cerr << "<" << FIDN->getIndex() << ">"; 1825 } else if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(this)){ 1826 std::cerr << "<" << CP->getIndex() << ">"; 1827 } else if (const BasicBlockSDNode *BBDN = dyn_cast<BasicBlockSDNode>(this)) { 1828 std::cerr << "<"; 1829 const Value *LBB = (const Value*)BBDN->getBasicBlock()->getBasicBlock(); 1830 if (LBB) 1831 std::cerr << LBB->getName() << " "; 1832 std::cerr << (const void*)BBDN->getBasicBlock() << ">"; 1833 } else if (const RegSDNode *C2V = dyn_cast<RegSDNode>(this)) { 1834 std::cerr << "<reg #" << C2V->getReg() << ">"; 1835 } else if (const ExternalSymbolSDNode *ES = 1836 dyn_cast<ExternalSymbolSDNode>(this)) { 1837 std::cerr << "'" << ES->getSymbol() << "'"; 1838 } else if (const SrcValueSDNode *M = dyn_cast<SrcValueSDNode>(this)) { 1839 if (M->getValue()) 1840 std::cerr << "<" << M->getValue() << ":" << M->getOffset() << ">"; 1841 else 1842 std::cerr << "<null:" << M->getOffset() << ">"; 1843 } 1844} 1845 1846static void DumpNodes(SDNode *N, unsigned indent) { 1847 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1848 if (N->getOperand(i).Val->hasOneUse()) 1849 DumpNodes(N->getOperand(i).Val, indent+2); 1850 else 1851 std::cerr << "\n" << std::string(indent+2, ' ') 1852 << (void*)N->getOperand(i).Val << ": <multiple use>"; 1853 1854 1855 std::cerr << "\n" << std::string(indent, ' '); 1856 N->dump(); 1857} 1858 1859void SelectionDAG::dump() const { 1860 std::cerr << "SelectionDAG has " << AllNodes.size() << " nodes:"; 1861 std::vector<SDNode*> Nodes(AllNodes); 1862 std::sort(Nodes.begin(), Nodes.end()); 1863 1864 for (unsigned i = 0, e = Nodes.size(); i != e; ++i) { 1865 if (!Nodes[i]->hasOneUse() && Nodes[i] != getRoot().Val) 1866 DumpNodes(Nodes[i], 2); 1867 } 1868 1869 DumpNodes(getRoot().Val, 2); 1870 1871 std::cerr << "\n\n"; 1872} 1873 1874