SelectionDAGISel.cpp revision 9c4dae6b0bd1b4667b7a6ce5d804f60615bac639
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "ScheduleDAGSDNodes.h" 16#include "SelectionDAGBuilder.h" 17#include "llvm/CodeGen/FunctionLoweringInfo.h" 18#include "llvm/CodeGen/SelectionDAGISel.h" 19#include "llvm/Analysis/AliasAnalysis.h" 20#include "llvm/Analysis/DebugInfo.h" 21#include "llvm/Constants.h" 22#include "llvm/Function.h" 23#include "llvm/InlineAsm.h" 24#include "llvm/Instructions.h" 25#include "llvm/Intrinsics.h" 26#include "llvm/IntrinsicInst.h" 27#include "llvm/LLVMContext.h" 28#include "llvm/Module.h" 29#include "llvm/CodeGen/FastISel.h" 30#include "llvm/CodeGen/GCStrategy.h" 31#include "llvm/CodeGen/GCMetadata.h" 32#include "llvm/CodeGen/MachineFrameInfo.h" 33#include "llvm/CodeGen/MachineFunction.h" 34#include "llvm/CodeGen/MachineInstrBuilder.h" 35#include "llvm/CodeGen/MachineModuleInfo.h" 36#include "llvm/CodeGen/MachineRegisterInfo.h" 37#include "llvm/CodeGen/ScheduleHazardRecognizer.h" 38#include "llvm/CodeGen/SchedulerRegistry.h" 39#include "llvm/CodeGen/SelectionDAG.h" 40#include "llvm/Target/TargetRegisterInfo.h" 41#include "llvm/Target/TargetIntrinsicInfo.h" 42#include "llvm/Target/TargetInstrInfo.h" 43#include "llvm/Target/TargetLowering.h" 44#include "llvm/Target/TargetMachine.h" 45#include "llvm/Target/TargetOptions.h" 46#include "llvm/Transforms/Utils/BasicBlockUtils.h" 47#include "llvm/Support/Compiler.h" 48#include "llvm/Support/Debug.h" 49#include "llvm/Support/ErrorHandling.h" 50#include "llvm/Support/Timer.h" 51#include "llvm/Support/raw_ostream.h" 52#include "llvm/ADT/PostOrderIterator.h" 53#include "llvm/ADT/Statistic.h" 54#include <algorithm> 55using namespace llvm; 56 57STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on"); 58STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected"); 59STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel"); 60STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG"); 61STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path"); 62 63#ifndef NDEBUG 64STATISTIC(NumBBWithOutOfOrderLineInfo, 65 "Number of blocks with out of order line number info"); 66STATISTIC(NumMBBWithOutOfOrderLineInfo, 67 "Number of machine blocks with out of order line number info"); 68#endif 69 70static cl::opt<bool> 71EnableFastISelVerbose("fast-isel-verbose", cl::Hidden, 72 cl::desc("Enable verbose messages in the \"fast\" " 73 "instruction selector")); 74static cl::opt<bool> 75EnableFastISelAbort("fast-isel-abort", cl::Hidden, 76 cl::desc("Enable abort calls when \"fast\" instruction fails")); 77 78#ifndef NDEBUG 79static cl::opt<bool> 80ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 81 cl::desc("Pop up a window to show dags before the first " 82 "dag combine pass")); 83static cl::opt<bool> 84ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden, 85 cl::desc("Pop up a window to show dags before legalize types")); 86static cl::opt<bool> 87ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 88 cl::desc("Pop up a window to show dags before legalize")); 89static cl::opt<bool> 90ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 91 cl::desc("Pop up a window to show dags before the second " 92 "dag combine pass")); 93static cl::opt<bool> 94ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden, 95 cl::desc("Pop up a window to show dags before the post legalize types" 96 " dag combine pass")); 97static cl::opt<bool> 98ViewISelDAGs("view-isel-dags", cl::Hidden, 99 cl::desc("Pop up a window to show isel dags as they are selected")); 100static cl::opt<bool> 101ViewSchedDAGs("view-sched-dags", cl::Hidden, 102 cl::desc("Pop up a window to show sched dags as they are processed")); 103static cl::opt<bool> 104ViewSUnitDAGs("view-sunit-dags", cl::Hidden, 105 cl::desc("Pop up a window to show SUnit dags after they are processed")); 106#else 107static const bool ViewDAGCombine1 = false, 108 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false, 109 ViewDAGCombine2 = false, 110 ViewDAGCombineLT = false, 111 ViewISelDAGs = false, ViewSchedDAGs = false, 112 ViewSUnitDAGs = false; 113#endif 114 115//===---------------------------------------------------------------------===// 116/// 117/// RegisterScheduler class - Track the registration of instruction schedulers. 118/// 119//===---------------------------------------------------------------------===// 120MachinePassRegistry RegisterScheduler::Registry; 121 122//===---------------------------------------------------------------------===// 123/// 124/// ISHeuristic command line option for instruction schedulers. 125/// 126//===---------------------------------------------------------------------===// 127static cl::opt<RegisterScheduler::FunctionPassCtor, false, 128 RegisterPassParser<RegisterScheduler> > 129ISHeuristic("pre-RA-sched", 130 cl::init(&createDefaultScheduler), 131 cl::desc("Instruction schedulers available (before register" 132 " allocation):")); 133 134static RegisterScheduler 135defaultListDAGScheduler("default", "Best scheduler for the target", 136 createDefaultScheduler); 137 138namespace llvm { 139 //===--------------------------------------------------------------------===// 140 /// createDefaultScheduler - This creates an instruction scheduler appropriate 141 /// for the target. 142 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS, 143 CodeGenOpt::Level OptLevel) { 144 const TargetLowering &TLI = IS->getTargetLowering(); 145 146 if (OptLevel == CodeGenOpt::None) 147 return createSourceListDAGScheduler(IS, OptLevel); 148 if (TLI.getSchedulingPreference() == Sched::Latency) 149 return createTDListDAGScheduler(IS, OptLevel); 150 if (TLI.getSchedulingPreference() == Sched::RegPressure) 151 return createBURRListDAGScheduler(IS, OptLevel); 152 if (TLI.getSchedulingPreference() == Sched::Hybrid) 153 return createHybridListDAGScheduler(IS, OptLevel); 154 assert(TLI.getSchedulingPreference() == Sched::ILP && 155 "Unknown sched type!"); 156 return createILPListDAGScheduler(IS, OptLevel); 157 } 158} 159 160// EmitInstrWithCustomInserter - This method should be implemented by targets 161// that mark instructions with the 'usesCustomInserter' flag. These 162// instructions are special in various ways, which require special support to 163// insert. The specified MachineInstr is created but not inserted into any 164// basic blocks, and this method is called to expand it into a sequence of 165// instructions, potentially also creating new basic blocks and control flow. 166// When new basic blocks are inserted and the edges from MBB to its successors 167// are modified, the method should insert pairs of <OldSucc, NewSucc> into the 168// DenseMap. 169MachineBasicBlock * 170TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 171 MachineBasicBlock *MBB) const { 172#ifndef NDEBUG 173 dbgs() << "If a target marks an instruction with " 174 "'usesCustomInserter', it must implement " 175 "TargetLowering::EmitInstrWithCustomInserter!"; 176#endif 177 llvm_unreachable(0); 178 return 0; 179} 180 181//===----------------------------------------------------------------------===// 182// SelectionDAGISel code 183//===----------------------------------------------------------------------===// 184 185SelectionDAGISel::SelectionDAGISel(const TargetMachine &tm, 186 CodeGenOpt::Level OL) : 187 MachineFunctionPass(ID), TM(tm), TLI(*tm.getTargetLowering()), 188 FuncInfo(new FunctionLoweringInfo(TLI)), 189 CurDAG(new SelectionDAG(tm)), 190 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)), 191 GFI(), 192 OptLevel(OL), 193 DAGSize(0) { 194 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry()); 195 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry()); 196 } 197 198SelectionDAGISel::~SelectionDAGISel() { 199 delete SDB; 200 delete CurDAG; 201 delete FuncInfo; 202} 203 204void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 205 AU.addRequired<AliasAnalysis>(); 206 AU.addPreserved<AliasAnalysis>(); 207 AU.addRequired<GCModuleInfo>(); 208 AU.addPreserved<GCModuleInfo>(); 209 MachineFunctionPass::getAnalysisUsage(AU); 210} 211 212/// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that 213/// may trap on it. In this case we have to split the edge so that the path 214/// through the predecessor block that doesn't go to the phi block doesn't 215/// execute the possibly trapping instruction. 216/// 217/// This is required for correctness, so it must be done at -O0. 218/// 219static void SplitCriticalSideEffectEdges(Function &Fn, Pass *SDISel) { 220 // Loop for blocks with phi nodes. 221 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) { 222 PHINode *PN = dyn_cast<PHINode>(BB->begin()); 223 if (PN == 0) continue; 224 225 ReprocessBlock: 226 // For each block with a PHI node, check to see if any of the input values 227 // are potentially trapping constant expressions. Constant expressions are 228 // the only potentially trapping value that can occur as the argument to a 229 // PHI. 230 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I) 231 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) { 232 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i)); 233 if (CE == 0 || !CE->canTrap()) continue; 234 235 // The only case we have to worry about is when the edge is critical. 236 // Since this block has a PHI Node, we assume it has multiple input 237 // edges: check to see if the pred has multiple successors. 238 BasicBlock *Pred = PN->getIncomingBlock(i); 239 if (Pred->getTerminator()->getNumSuccessors() == 1) 240 continue; 241 242 // Okay, we have to split this edge. 243 SplitCriticalEdge(Pred->getTerminator(), 244 GetSuccessorNumber(Pred, BB), SDISel, true); 245 goto ReprocessBlock; 246 } 247 } 248} 249 250bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) { 251 // Do some sanity-checking on the command-line options. 252 assert((!EnableFastISelVerbose || EnableFastISel) && 253 "-fast-isel-verbose requires -fast-isel"); 254 assert((!EnableFastISelAbort || EnableFastISel) && 255 "-fast-isel-abort requires -fast-isel"); 256 257 const Function &Fn = *mf.getFunction(); 258 const TargetInstrInfo &TII = *TM.getInstrInfo(); 259 const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); 260 261 MF = &mf; 262 RegInfo = &MF->getRegInfo(); 263 AA = &getAnalysis<AliasAnalysis>(); 264 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0; 265 266 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n"); 267 268 SplitCriticalSideEffectEdges(const_cast<Function&>(Fn), this); 269 270 CurDAG->init(*MF); 271 FuncInfo->set(Fn, *MF); 272 SDB->init(GFI, *AA); 273 274 SelectAllBasicBlocks(Fn); 275 276 // If the first basic block in the function has live ins that need to be 277 // copied into vregs, emit the copies into the top of the block before 278 // emitting the code for the block. 279 MachineBasicBlock *EntryMBB = MF->begin(); 280 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII); 281 282 DenseMap<unsigned, unsigned> LiveInMap; 283 if (!FuncInfo->ArgDbgValues.empty()) 284 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(), 285 E = RegInfo->livein_end(); LI != E; ++LI) 286 if (LI->second) 287 LiveInMap.insert(std::make_pair(LI->first, LI->second)); 288 289 // Insert DBG_VALUE instructions for function arguments to the entry block. 290 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) { 291 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1]; 292 unsigned Reg = MI->getOperand(0).getReg(); 293 if (TargetRegisterInfo::isPhysicalRegister(Reg)) 294 EntryMBB->insert(EntryMBB->begin(), MI); 295 else { 296 MachineInstr *Def = RegInfo->getVRegDef(Reg); 297 MachineBasicBlock::iterator InsertPos = Def; 298 // FIXME: VR def may not be in entry block. 299 Def->getParent()->insert(llvm::next(InsertPos), MI); 300 } 301 302 // If Reg is live-in then update debug info to track its copy in a vreg. 303 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg); 304 if (LDI != LiveInMap.end()) { 305 MachineInstr *Def = RegInfo->getVRegDef(LDI->second); 306 MachineBasicBlock::iterator InsertPos = Def; 307 const MDNode *Variable = 308 MI->getOperand(MI->getNumOperands()-1).getMetadata(); 309 unsigned Offset = MI->getOperand(1).getImm(); 310 // Def is never a terminator here, so it is ok to increment InsertPos. 311 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(), 312 TII.get(TargetOpcode::DBG_VALUE)) 313 .addReg(LDI->second, RegState::Debug) 314 .addImm(Offset).addMetadata(Variable); 315 316 // If this vreg is directly copied into an exported register then 317 // that COPY instructions also need DBG_VALUE, if it is the only 318 // user of LDI->second. 319 MachineInstr *CopyUseMI = NULL; 320 for (MachineRegisterInfo::use_iterator 321 UI = RegInfo->use_begin(LDI->second); 322 MachineInstr *UseMI = UI.skipInstruction();) { 323 if (UseMI->isDebugValue()) continue; 324 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) { 325 CopyUseMI = UseMI; continue; 326 } 327 // Otherwise this is another use or second copy use. 328 CopyUseMI = NULL; break; 329 } 330 if (CopyUseMI) { 331 MachineInstr *NewMI = 332 BuildMI(*MF, CopyUseMI->getDebugLoc(), 333 TII.get(TargetOpcode::DBG_VALUE)) 334 .addReg(CopyUseMI->getOperand(0).getReg(), RegState::Debug) 335 .addImm(Offset).addMetadata(Variable); 336 EntryMBB->insertAfter(CopyUseMI, NewMI); 337 } 338 } 339 } 340 341 // Determine if there are any calls in this machine function. 342 MachineFrameInfo *MFI = MF->getFrameInfo(); 343 if (!MFI->hasCalls()) { 344 for (MachineFunction::const_iterator 345 I = MF->begin(), E = MF->end(); I != E; ++I) { 346 const MachineBasicBlock *MBB = I; 347 for (MachineBasicBlock::const_iterator 348 II = MBB->begin(), IE = MBB->end(); II != IE; ++II) { 349 const TargetInstrDesc &TID = TM.getInstrInfo()->get(II->getOpcode()); 350 351 if ((TID.isCall() && !TID.isReturn()) || 352 II->isStackAligningInlineAsm()) { 353 MFI->setHasCalls(true); 354 goto done; 355 } 356 } 357 } 358 done:; 359 } 360 361 // Determine if there is a call to setjmp in the machine function. 362 MF->setCallsSetJmp(Fn.callsFunctionThatReturnsTwice()); 363 364 // Replace forward-declared registers with the registers containing 365 // the desired value. 366 MachineRegisterInfo &MRI = MF->getRegInfo(); 367 for (DenseMap<unsigned, unsigned>::iterator 368 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end(); 369 I != E; ++I) { 370 unsigned From = I->first; 371 unsigned To = I->second; 372 // If To is also scheduled to be replaced, find what its ultimate 373 // replacement is. 374 for (;;) { 375 DenseMap<unsigned, unsigned>::iterator J = 376 FuncInfo->RegFixups.find(To); 377 if (J == E) break; 378 To = J->second; 379 } 380 // Replace it. 381 MRI.replaceRegWith(From, To); 382 } 383 384 // Release function-specific state. SDB and CurDAG are already cleared 385 // at this point. 386 FuncInfo->clear(); 387 388 return true; 389} 390 391void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin, 392 BasicBlock::const_iterator End, 393 bool &HadTailCall) { 394 // Lower all of the non-terminator instructions. If a call is emitted 395 // as a tail call, cease emitting nodes for this block. Terminators 396 // are handled below. 397 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I) 398 SDB->visit(*I); 399 400 // Make sure the root of the DAG is up-to-date. 401 CurDAG->setRoot(SDB->getControlRoot()); 402 HadTailCall = SDB->HasTailCall; 403 SDB->clear(); 404 405 // Final step, emit the lowered DAG as machine code. 406 CodeGenAndEmitDAG(); 407} 408 409void SelectionDAGISel::ComputeLiveOutVRegInfo() { 410 SmallPtrSet<SDNode*, 128> VisitedNodes; 411 SmallVector<SDNode*, 128> Worklist; 412 413 Worklist.push_back(CurDAG->getRoot().getNode()); 414 415 APInt Mask; 416 APInt KnownZero; 417 APInt KnownOne; 418 419 do { 420 SDNode *N = Worklist.pop_back_val(); 421 422 // If we've already seen this node, ignore it. 423 if (!VisitedNodes.insert(N)) 424 continue; 425 426 // Otherwise, add all chain operands to the worklist. 427 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 428 if (N->getOperand(i).getValueType() == MVT::Other) 429 Worklist.push_back(N->getOperand(i).getNode()); 430 431 // If this is a CopyToReg with a vreg dest, process it. 432 if (N->getOpcode() != ISD::CopyToReg) 433 continue; 434 435 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg(); 436 if (!TargetRegisterInfo::isVirtualRegister(DestReg)) 437 continue; 438 439 // Ignore non-scalar or non-integer values. 440 SDValue Src = N->getOperand(2); 441 EVT SrcVT = Src.getValueType(); 442 if (!SrcVT.isInteger() || SrcVT.isVector()) 443 continue; 444 445 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src); 446 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits()); 447 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne); 448 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne); 449 } while (!Worklist.empty()); 450} 451 452void SelectionDAGISel::CodeGenAndEmitDAG() { 453 std::string GroupName; 454 if (TimePassesIsEnabled) 455 GroupName = "Instruction Selection and Scheduling"; 456 std::string BlockName; 457 int BlockNumber = -1; 458#ifdef NDEBUG 459 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs || 460 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs || 461 ViewSUnitDAGs) 462#endif 463 { 464 BlockNumber = FuncInfo->MBB->getNumber(); 465 BlockName = MF->getFunction()->getNameStr() + ":" + 466 FuncInfo->MBB->getBasicBlock()->getNameStr(); 467 } 468 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber 469 << " '" << BlockName << "'\n"; CurDAG->dump()); 470 471 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName); 472 473 // Run the DAG combiner in pre-legalize mode. 474 { 475 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled); 476 CurDAG->Combine(Unrestricted, *AA, OptLevel); 477 } 478 479 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber 480 << " '" << BlockName << "'\n"; CurDAG->dump()); 481 482 // Second step, hack on the DAG until it only uses operations and types that 483 // the target supports. 484 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " + 485 BlockName); 486 487 bool Changed; 488 { 489 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled); 490 Changed = CurDAG->LegalizeTypes(); 491 } 492 493 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber 494 << " '" << BlockName << "'\n"; CurDAG->dump()); 495 496 if (Changed) { 497 if (ViewDAGCombineLT) 498 CurDAG->viewGraph("dag-combine-lt input for " + BlockName); 499 500 // Run the DAG combiner in post-type-legalize mode. 501 { 502 NamedRegionTimer T("DAG Combining after legalize types", GroupName, 503 TimePassesIsEnabled); 504 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel); 505 } 506 507 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber 508 << " '" << BlockName << "'\n"; CurDAG->dump()); 509 } 510 511 { 512 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled); 513 Changed = CurDAG->LegalizeVectors(); 514 } 515 516 if (Changed) { 517 { 518 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled); 519 CurDAG->LegalizeTypes(); 520 } 521 522 if (ViewDAGCombineLT) 523 CurDAG->viewGraph("dag-combine-lv input for " + BlockName); 524 525 // Run the DAG combiner in post-type-legalize mode. 526 { 527 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName, 528 TimePassesIsEnabled); 529 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 530 } 531 532 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#" 533 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump()); 534 } 535 536 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName); 537 538 { 539 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled); 540 CurDAG->Legalize(); 541 } 542 543 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber 544 << " '" << BlockName << "'\n"; CurDAG->dump()); 545 546 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName); 547 548 // Run the DAG combiner in post-legalize mode. 549 { 550 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled); 551 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 552 } 553 554 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber 555 << " '" << BlockName << "'\n"; CurDAG->dump()); 556 557 if (OptLevel != CodeGenOpt::None) 558 ComputeLiveOutVRegInfo(); 559 560 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName); 561 562 // Third, instruction select all of the operations to machine code, adding the 563 // code to the MachineBasicBlock. 564 { 565 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled); 566 DoInstructionSelection(); 567 } 568 569 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber 570 << " '" << BlockName << "'\n"; CurDAG->dump()); 571 572 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName); 573 574 // Schedule machine code. 575 ScheduleDAGSDNodes *Scheduler = CreateScheduler(); 576 { 577 NamedRegionTimer T("Instruction Scheduling", GroupName, 578 TimePassesIsEnabled); 579 Scheduler->Run(CurDAG, FuncInfo->MBB, FuncInfo->InsertPt); 580 } 581 582 if (ViewSUnitDAGs) Scheduler->viewGraph(); 583 584 // Emit machine code to BB. This can change 'BB' to the last block being 585 // inserted into. 586 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB; 587 { 588 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled); 589 590 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule(); 591 FuncInfo->InsertPt = Scheduler->InsertPos; 592 } 593 594 // If the block was split, make sure we update any references that are used to 595 // update PHI nodes later on. 596 if (FirstMBB != LastMBB) 597 SDB->UpdateSplitBlock(FirstMBB, LastMBB); 598 599 // Free the scheduler state. 600 { 601 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName, 602 TimePassesIsEnabled); 603 delete Scheduler; 604 } 605 606 // Free the SelectionDAG state, now that we're finished with it. 607 CurDAG->clear(); 608} 609 610void SelectionDAGISel::DoInstructionSelection() { 611 DEBUG(errs() << "===== Instruction selection begins: BB#" 612 << FuncInfo->MBB->getNumber() 613 << " '" << FuncInfo->MBB->getName() << "'\n"); 614 615 PreprocessISelDAG(); 616 617 // Select target instructions for the DAG. 618 { 619 // Number all nodes with a topological order and set DAGSize. 620 DAGSize = CurDAG->AssignTopologicalOrder(); 621 622 // Create a dummy node (which is not added to allnodes), that adds 623 // a reference to the root node, preventing it from being deleted, 624 // and tracking any changes of the root. 625 HandleSDNode Dummy(CurDAG->getRoot()); 626 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode()); 627 ++ISelPosition; 628 629 // The AllNodes list is now topological-sorted. Visit the 630 // nodes by starting at the end of the list (the root of the 631 // graph) and preceding back toward the beginning (the entry 632 // node). 633 while (ISelPosition != CurDAG->allnodes_begin()) { 634 SDNode *Node = --ISelPosition; 635 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes, 636 // but there are currently some corner cases that it misses. Also, this 637 // makes it theoretically possible to disable the DAGCombiner. 638 if (Node->use_empty()) 639 continue; 640 641 SDNode *ResNode = Select(Node); 642 643 // FIXME: This is pretty gross. 'Select' should be changed to not return 644 // anything at all and this code should be nuked with a tactical strike. 645 646 // If node should not be replaced, continue with the next one. 647 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE) 648 continue; 649 // Replace node. 650 if (ResNode) 651 ReplaceUses(Node, ResNode); 652 653 // If after the replacement this node is not used any more, 654 // remove this dead node. 655 if (Node->use_empty()) { // Don't delete EntryToken, etc. 656 ISelUpdater ISU(ISelPosition); 657 CurDAG->RemoveDeadNode(Node, &ISU); 658 } 659 } 660 661 CurDAG->setRoot(Dummy.getValue()); 662 } 663 664 DEBUG(errs() << "===== Instruction selection ends:\n"); 665 666 PostprocessISelDAG(); 667} 668 669/// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and 670/// do other setup for EH landing-pad blocks. 671void SelectionDAGISel::PrepareEHLandingPad() { 672 // Add a label to mark the beginning of the landing pad. Deletion of the 673 // landing pad can thus be detected via the MachineModuleInfo. 674 MCSymbol *Label = MF->getMMI().addLandingPad(FuncInfo->MBB); 675 676 const TargetInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL); 677 BuildMI(*FuncInfo->MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II) 678 .addSym(Label); 679 680 // Mark exception register as live in. 681 unsigned Reg = TLI.getExceptionAddressRegister(); 682 if (Reg) FuncInfo->MBB->addLiveIn(Reg); 683 684 // Mark exception selector register as live in. 685 Reg = TLI.getExceptionSelectorRegister(); 686 if (Reg) FuncInfo->MBB->addLiveIn(Reg); 687 688 // FIXME: Hack around an exception handling flaw (PR1508): the personality 689 // function and list of typeids logically belong to the invoke (or, if you 690 // like, the basic block containing the invoke), and need to be associated 691 // with it in the dwarf exception handling tables. Currently however the 692 // information is provided by an intrinsic (eh.selector) that can be moved 693 // to unexpected places by the optimizers: if the unwind edge is critical, 694 // then breaking it can result in the intrinsics being in the successor of 695 // the landing pad, not the landing pad itself. This results 696 // in exceptions not being caught because no typeids are associated with 697 // the invoke. This may not be the only way things can go wrong, but it 698 // is the only way we try to work around for the moment. 699 const BasicBlock *LLVMBB = FuncInfo->MBB->getBasicBlock(); 700 const BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator()); 701 702 if (Br && Br->isUnconditional()) { // Critical edge? 703 BasicBlock::const_iterator I, E; 704 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I) 705 if (isa<EHSelectorInst>(I)) 706 break; 707 708 if (I == E) 709 // No catch info found - try to extract some from the successor. 710 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, &MF->getMMI(), *FuncInfo); 711 } 712} 713 714 715 716/// TryToFoldFastISelLoad - We're checking to see if we can fold the specified 717/// load into the specified FoldInst. Note that we could have a sequence where 718/// multiple LLVM IR instructions are folded into the same machineinstr. For 719/// example we could have: 720/// A: x = load i32 *P 721/// B: y = icmp A, 42 722/// C: br y, ... 723/// 724/// In this scenario, LI is "A", and FoldInst is "C". We know about "B" (and 725/// any other folded instructions) because it is between A and C. 726/// 727/// If we succeed in folding the load into the operation, return true. 728/// 729bool SelectionDAGISel::TryToFoldFastISelLoad(const LoadInst *LI, 730 const Instruction *FoldInst, 731 FastISel *FastIS) { 732 // We know that the load has a single use, but don't know what it is. If it 733 // isn't one of the folded instructions, then we can't succeed here. Handle 734 // this by scanning the single-use users of the load until we get to FoldInst. 735 unsigned MaxUsers = 6; // Don't scan down huge single-use chains of instrs. 736 737 const Instruction *TheUser = LI->use_back(); 738 while (TheUser != FoldInst && // Scan up until we find FoldInst. 739 // Stay in the right block. 740 TheUser->getParent() == FoldInst->getParent() && 741 --MaxUsers) { // Don't scan too far. 742 // If there are multiple or no uses of this instruction, then bail out. 743 if (!TheUser->hasOneUse()) 744 return false; 745 746 TheUser = TheUser->use_back(); 747 } 748 749 // Don't try to fold volatile loads. Target has to deal with alignment 750 // constraints. 751 if (LI->isVolatile()) return false; 752 753 // Figure out which vreg this is going into. If there is no assigned vreg yet 754 // then there actually was no reference to it. Perhaps the load is referenced 755 // by a dead instruction. 756 unsigned LoadReg = FastIS->getRegForValue(LI); 757 if (LoadReg == 0) 758 return false; 759 760 // Check to see what the uses of this vreg are. If it has no uses, or more 761 // than one use (at the machine instr level) then we can't fold it. 762 MachineRegisterInfo::reg_iterator RI = RegInfo->reg_begin(LoadReg); 763 if (RI == RegInfo->reg_end()) 764 return false; 765 766 // See if there is exactly one use of the vreg. If there are multiple uses, 767 // then the instruction got lowered to multiple machine instructions or the 768 // use of the loaded value ended up being multiple operands of the result, in 769 // either case, we can't fold this. 770 MachineRegisterInfo::reg_iterator PostRI = RI; ++PostRI; 771 if (PostRI != RegInfo->reg_end()) 772 return false; 773 774 assert(RI.getOperand().isUse() && 775 "The only use of the vreg must be a use, we haven't emitted the def!"); 776 777 MachineInstr *User = &*RI; 778 779 // Set the insertion point properly. Folding the load can cause generation of 780 // other random instructions (like sign extends) for addressing modes, make 781 // sure they get inserted in a logical place before the new instruction. 782 FuncInfo->InsertPt = User; 783 FuncInfo->MBB = User->getParent(); 784 785 // Ask the target to try folding the load. 786 return FastIS->TryToFoldLoad(User, RI.getOperandNo(), LI); 787} 788 789#ifndef NDEBUG 790/// CheckLineNumbers - Check if basic block instructions follow source order 791/// or not. 792static void CheckLineNumbers(const BasicBlock *BB) { 793 unsigned Line = 0; 794 unsigned Col = 0; 795 for (BasicBlock::const_iterator BI = BB->begin(), 796 BE = BB->end(); BI != BE; ++BI) { 797 const DebugLoc DL = BI->getDebugLoc(); 798 if (DL.isUnknown()) continue; 799 unsigned L = DL.getLine(); 800 unsigned C = DL.getCol(); 801 if (L < Line || (L == Line && C < Col)) { 802 ++NumBBWithOutOfOrderLineInfo; 803 return; 804 } 805 Line = L; 806 Col = C; 807 } 808} 809 810/// CheckLineNumbers - Check if machine basic block instructions follow source 811/// order or not. 812static void CheckLineNumbers(const MachineBasicBlock *MBB) { 813 unsigned Line = 0; 814 unsigned Col = 0; 815 for (MachineBasicBlock::const_iterator MBI = MBB->begin(), 816 MBE = MBB->end(); MBI != MBE; ++MBI) { 817 const DebugLoc DL = MBI->getDebugLoc(); 818 if (DL.isUnknown()) continue; 819 unsigned L = DL.getLine(); 820 unsigned C = DL.getCol(); 821 if (L < Line || (L == Line && C < Col)) { 822 ++NumMBBWithOutOfOrderLineInfo; 823 return; 824 } 825 Line = L; 826 Col = C; 827 } 828} 829#endif 830 831/// isFoldedOrDeadInstruction - Return true if the specified instruction is 832/// side-effect free and is either dead or folded into a generated instruction. 833/// Return false if it needs to be emitted. 834static bool isFoldedOrDeadInstruction(const Instruction *I, 835 FunctionLoweringInfo *FuncInfo) { 836 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded. 837 !isa<TerminatorInst>(I) && // Terminators aren't folded. 838 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded. 839 !FuncInfo->isExportedInst(I); // Exported instrs must be computed. 840} 841 842void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) { 843 // Initialize the Fast-ISel state, if needed. 844 FastISel *FastIS = 0; 845 if (EnableFastISel) 846 FastIS = TLI.createFastISel(*FuncInfo); 847 848 // Iterate over all basic blocks in the function. 849 ReversePostOrderTraversal<const Function*> RPOT(&Fn); 850 for (ReversePostOrderTraversal<const Function*>::rpo_iterator 851 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) { 852 const BasicBlock *LLVMBB = *I; 853#ifndef NDEBUG 854 CheckLineNumbers(LLVMBB); 855#endif 856 857 if (OptLevel != CodeGenOpt::None) { 858 bool AllPredsVisited = true; 859 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB); 860 PI != PE; ++PI) { 861 if (!FuncInfo->VisitedBBs.count(*PI)) { 862 AllPredsVisited = false; 863 break; 864 } 865 } 866 867 if (AllPredsVisited) { 868 for (BasicBlock::const_iterator I = LLVMBB->begin(); 869 isa<PHINode>(I); ++I) 870 FuncInfo->ComputePHILiveOutRegInfo(cast<PHINode>(I)); 871 } else { 872 for (BasicBlock::const_iterator I = LLVMBB->begin(); 873 isa<PHINode>(I); ++I) 874 FuncInfo->InvalidatePHILiveOutRegInfo(cast<PHINode>(I)); 875 } 876 877 FuncInfo->VisitedBBs.insert(LLVMBB); 878 } 879 880 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB]; 881 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI(); 882 883 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI(); 884 BasicBlock::const_iterator const End = LLVMBB->end(); 885 BasicBlock::const_iterator BI = End; 886 887 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI(); 888 889 // Setup an EH landing-pad block. 890 if (FuncInfo->MBB->isLandingPad()) 891 PrepareEHLandingPad(); 892 893 // Lower any arguments needed in this block if this is the entry block. 894 if (LLVMBB == &Fn.getEntryBlock()) 895 LowerArguments(LLVMBB); 896 897 // Before doing SelectionDAG ISel, see if FastISel has been requested. 898 if (FastIS) { 899 FastIS->startNewBlock(); 900 901 // Emit code for any incoming arguments. This must happen before 902 // beginning FastISel on the entry block. 903 if (LLVMBB == &Fn.getEntryBlock()) { 904 CurDAG->setRoot(SDB->getControlRoot()); 905 SDB->clear(); 906 CodeGenAndEmitDAG(); 907 908 // If we inserted any instructions at the beginning, make a note of 909 // where they are, so we can be sure to emit subsequent instructions 910 // after them. 911 if (FuncInfo->InsertPt != FuncInfo->MBB->begin()) 912 FastIS->setLastLocalValue(llvm::prior(FuncInfo->InsertPt)); 913 else 914 FastIS->setLastLocalValue(0); 915 } 916 917 // Do FastISel on as many instructions as possible. 918 for (; BI != Begin; --BI) { 919 const Instruction *Inst = llvm::prior(BI); 920 921 // If we no longer require this instruction, skip it. 922 if (isFoldedOrDeadInstruction(Inst, FuncInfo)) 923 continue; 924 925 // Bottom-up: reset the insert pos at the top, after any local-value 926 // instructions. 927 FastIS->recomputeInsertPt(); 928 929 // Try to select the instruction with FastISel. 930 if (FastIS->SelectInstruction(Inst)) { 931 ++NumFastIselSuccess; 932 // If fast isel succeeded, skip over all the folded instructions, and 933 // then see if there is a load right before the selected instructions. 934 // Try to fold the load if so. 935 const Instruction *BeforeInst = Inst; 936 while (BeforeInst != Begin) { 937 BeforeInst = llvm::prior(BasicBlock::const_iterator(BeforeInst)); 938 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo)) 939 break; 940 } 941 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) && 942 BeforeInst->hasOneUse() && 943 TryToFoldFastISelLoad(cast<LoadInst>(BeforeInst), Inst, FastIS)) 944 // If we succeeded, don't re-select the load. 945 BI = llvm::next(BasicBlock::const_iterator(BeforeInst)); 946 continue; 947 } 948 949 // Then handle certain instructions as single-LLVM-Instruction blocks. 950 if (isa<CallInst>(Inst)) { 951 ++NumFastIselFailures; 952 if (EnableFastISelVerbose || EnableFastISelAbort) { 953 dbgs() << "FastISel missed call: "; 954 Inst->dump(); 955 } 956 957 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) { 958 unsigned &R = FuncInfo->ValueMap[Inst]; 959 if (!R) 960 R = FuncInfo->CreateRegs(Inst->getType()); 961 } 962 963 bool HadTailCall = false; 964 SelectBasicBlock(Inst, BI, HadTailCall); 965 966 // If the call was emitted as a tail call, we're done with the block. 967 if (HadTailCall) { 968 --BI; 969 break; 970 } 971 972 continue; 973 } 974 975 if (isa<TerminatorInst>(Inst) && !isa<BranchInst>(Inst)) { 976 // Don't abort, and use a different message for terminator misses. 977 ++NumFastIselFailures; 978 if (EnableFastISelVerbose || EnableFastISelAbort) { 979 dbgs() << "FastISel missed terminator: "; 980 Inst->dump(); 981 } 982 } else { 983 ++NumFastIselFailures; 984 if (EnableFastISelVerbose || EnableFastISelAbort) { 985 dbgs() << "FastISel miss: "; 986 Inst->dump(); 987 } 988 if (EnableFastISelAbort) 989 // The "fast" selector couldn't handle something and bailed. 990 // For the purpose of debugging, just abort. 991 llvm_unreachable("FastISel didn't select the entire block"); 992 } 993 break; 994 } 995 996 FastIS->recomputeInsertPt(); 997 } 998 999 if (Begin != BI) 1000 ++NumDAGBlocks; 1001 else 1002 ++NumFastIselBlocks; 1003 1004 if (Begin != BI) { 1005 // Run SelectionDAG instruction selection on the remainder of the block 1006 // not handled by FastISel. If FastISel is not run, this is the entire 1007 // block. 1008 bool HadTailCall; 1009 SelectBasicBlock(Begin, BI, HadTailCall); 1010 } 1011 1012 FinishBasicBlock(); 1013 FuncInfo->PHINodesToUpdate.clear(); 1014 } 1015 1016 delete FastIS; 1017#ifndef NDEBUG 1018 for (MachineFunction::const_iterator MBI = MF->begin(), MBE = MF->end(); 1019 MBI != MBE; ++MBI) 1020 CheckLineNumbers(MBI); 1021#endif 1022} 1023 1024void 1025SelectionDAGISel::FinishBasicBlock() { 1026 1027 DEBUG(dbgs() << "Total amount of phi nodes to update: " 1028 << FuncInfo->PHINodesToUpdate.size() << "\n"; 1029 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) 1030 dbgs() << "Node " << i << " : (" 1031 << FuncInfo->PHINodesToUpdate[i].first 1032 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n"); 1033 1034 // Next, now that we know what the last MBB the LLVM BB expanded is, update 1035 // PHI nodes in successors. 1036 if (SDB->SwitchCases.empty() && 1037 SDB->JTCases.empty() && 1038 SDB->BitTestCases.empty()) { 1039 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) { 1040 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first; 1041 assert(PHI->isPHI() && 1042 "This is not a machine PHI node that we are updating!"); 1043 if (!FuncInfo->MBB->isSuccessor(PHI->getParent())) 1044 continue; 1045 PHI->addOperand( 1046 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false)); 1047 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB)); 1048 } 1049 return; 1050 } 1051 1052 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) { 1053 // Lower header first, if it wasn't already lowered 1054 if (!SDB->BitTestCases[i].Emitted) { 1055 // Set the current basic block to the mbb we wish to insert the code into 1056 FuncInfo->MBB = SDB->BitTestCases[i].Parent; 1057 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1058 // Emit the code 1059 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB); 1060 CurDAG->setRoot(SDB->getRoot()); 1061 SDB->clear(); 1062 CodeGenAndEmitDAG(); 1063 } 1064 1065 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) { 1066 // Set the current basic block to the mbb we wish to insert the code into 1067 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB; 1068 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1069 // Emit the code 1070 if (j+1 != ej) 1071 SDB->visitBitTestCase(SDB->BitTestCases[i], 1072 SDB->BitTestCases[i].Cases[j+1].ThisBB, 1073 SDB->BitTestCases[i].Reg, 1074 SDB->BitTestCases[i].Cases[j], 1075 FuncInfo->MBB); 1076 else 1077 SDB->visitBitTestCase(SDB->BitTestCases[i], 1078 SDB->BitTestCases[i].Default, 1079 SDB->BitTestCases[i].Reg, 1080 SDB->BitTestCases[i].Cases[j], 1081 FuncInfo->MBB); 1082 1083 1084 CurDAG->setRoot(SDB->getRoot()); 1085 SDB->clear(); 1086 CodeGenAndEmitDAG(); 1087 } 1088 1089 // Update PHI Nodes 1090 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size(); 1091 pi != pe; ++pi) { 1092 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first; 1093 MachineBasicBlock *PHIBB = PHI->getParent(); 1094 assert(PHI->isPHI() && 1095 "This is not a machine PHI node that we are updating!"); 1096 // This is "default" BB. We have two jumps to it. From "header" BB and 1097 // from last "case" BB. 1098 if (PHIBB == SDB->BitTestCases[i].Default) { 1099 PHI->addOperand(MachineOperand:: 1100 CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 1101 false)); 1102 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent)); 1103 PHI->addOperand(MachineOperand:: 1104 CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 1105 false)); 1106 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases. 1107 back().ThisBB)); 1108 } 1109 // One of "cases" BB. 1110 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); 1111 j != ej; ++j) { 1112 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB; 1113 if (cBB->isSuccessor(PHIBB)) { 1114 PHI->addOperand(MachineOperand:: 1115 CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 1116 false)); 1117 PHI->addOperand(MachineOperand::CreateMBB(cBB)); 1118 } 1119 } 1120 } 1121 } 1122 SDB->BitTestCases.clear(); 1123 1124 // If the JumpTable record is filled in, then we need to emit a jump table. 1125 // Updating the PHI nodes is tricky in this case, since we need to determine 1126 // whether the PHI is a successor of the range check MBB or the jump table MBB 1127 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) { 1128 // Lower header first, if it wasn't already lowered 1129 if (!SDB->JTCases[i].first.Emitted) { 1130 // Set the current basic block to the mbb we wish to insert the code into 1131 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB; 1132 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1133 // Emit the code 1134 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first, 1135 FuncInfo->MBB); 1136 CurDAG->setRoot(SDB->getRoot()); 1137 SDB->clear(); 1138 CodeGenAndEmitDAG(); 1139 } 1140 1141 // Set the current basic block to the mbb we wish to insert the code into 1142 FuncInfo->MBB = SDB->JTCases[i].second.MBB; 1143 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1144 // Emit the code 1145 SDB->visitJumpTable(SDB->JTCases[i].second); 1146 CurDAG->setRoot(SDB->getRoot()); 1147 SDB->clear(); 1148 CodeGenAndEmitDAG(); 1149 1150 // Update PHI Nodes 1151 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size(); 1152 pi != pe; ++pi) { 1153 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first; 1154 MachineBasicBlock *PHIBB = PHI->getParent(); 1155 assert(PHI->isPHI() && 1156 "This is not a machine PHI node that we are updating!"); 1157 // "default" BB. We can go there only from header BB. 1158 if (PHIBB == SDB->JTCases[i].second.Default) { 1159 PHI->addOperand 1160 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 1161 false)); 1162 PHI->addOperand 1163 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB)); 1164 } 1165 // JT BB. Just iterate over successors here 1166 if (FuncInfo->MBB->isSuccessor(PHIBB)) { 1167 PHI->addOperand 1168 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 1169 false)); 1170 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB)); 1171 } 1172 } 1173 } 1174 SDB->JTCases.clear(); 1175 1176 // If the switch block involved a branch to one of the actual successors, we 1177 // need to update PHI nodes in that block. 1178 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) { 1179 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first; 1180 assert(PHI->isPHI() && 1181 "This is not a machine PHI node that we are updating!"); 1182 if (FuncInfo->MBB->isSuccessor(PHI->getParent())) { 1183 PHI->addOperand( 1184 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false)); 1185 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB)); 1186 } 1187 } 1188 1189 // If we generated any switch lowering information, build and codegen any 1190 // additional DAGs necessary. 1191 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) { 1192 // Set the current basic block to the mbb we wish to insert the code into 1193 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB; 1194 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1195 1196 // Determine the unique successors. 1197 SmallVector<MachineBasicBlock *, 2> Succs; 1198 Succs.push_back(SDB->SwitchCases[i].TrueBB); 1199 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB) 1200 Succs.push_back(SDB->SwitchCases[i].FalseBB); 1201 1202 // Emit the code. Note that this could result in FuncInfo->MBB being split. 1203 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB); 1204 CurDAG->setRoot(SDB->getRoot()); 1205 SDB->clear(); 1206 CodeGenAndEmitDAG(); 1207 1208 // Remember the last block, now that any splitting is done, for use in 1209 // populating PHI nodes in successors. 1210 MachineBasicBlock *ThisBB = FuncInfo->MBB; 1211 1212 // Handle any PHI nodes in successors of this chunk, as if we were coming 1213 // from the original BB before switch expansion. Note that PHI nodes can 1214 // occur multiple times in PHINodesToUpdate. We have to be very careful to 1215 // handle them the right number of times. 1216 for (unsigned i = 0, e = Succs.size(); i != e; ++i) { 1217 FuncInfo->MBB = Succs[i]; 1218 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1219 // FuncInfo->MBB may have been removed from the CFG if a branch was 1220 // constant folded. 1221 if (ThisBB->isSuccessor(FuncInfo->MBB)) { 1222 for (MachineBasicBlock::iterator Phi = FuncInfo->MBB->begin(); 1223 Phi != FuncInfo->MBB->end() && Phi->isPHI(); 1224 ++Phi) { 1225 // This value for this PHI node is recorded in PHINodesToUpdate. 1226 for (unsigned pn = 0; ; ++pn) { 1227 assert(pn != FuncInfo->PHINodesToUpdate.size() && 1228 "Didn't find PHI entry!"); 1229 if (FuncInfo->PHINodesToUpdate[pn].first == Phi) { 1230 Phi->addOperand(MachineOperand:: 1231 CreateReg(FuncInfo->PHINodesToUpdate[pn].second, 1232 false)); 1233 Phi->addOperand(MachineOperand::CreateMBB(ThisBB)); 1234 break; 1235 } 1236 } 1237 } 1238 } 1239 } 1240 } 1241 SDB->SwitchCases.clear(); 1242} 1243 1244 1245/// Create the scheduler. If a specific scheduler was specified 1246/// via the SchedulerRegistry, use it, otherwise select the 1247/// one preferred by the target. 1248/// 1249ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() { 1250 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 1251 1252 if (!Ctor) { 1253 Ctor = ISHeuristic; 1254 RegisterScheduler::setDefault(Ctor); 1255 } 1256 1257 return Ctor(this, OptLevel); 1258} 1259 1260//===----------------------------------------------------------------------===// 1261// Helper functions used by the generated instruction selector. 1262//===----------------------------------------------------------------------===// 1263// Calls to these methods are generated by tblgen. 1264 1265/// CheckAndMask - The isel is trying to match something like (and X, 255). If 1266/// the dag combiner simplified the 255, we still want to match. RHS is the 1267/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 1268/// specified in the .td file (e.g. 255). 1269bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS, 1270 int64_t DesiredMaskS) const { 1271 const APInt &ActualMask = RHS->getAPIntValue(); 1272 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1273 1274 // If the actual mask exactly matches, success! 1275 if (ActualMask == DesiredMask) 1276 return true; 1277 1278 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1279 if (ActualMask.intersects(~DesiredMask)) 1280 return false; 1281 1282 // Otherwise, the DAG Combiner may have proven that the value coming in is 1283 // either already zero or is not demanded. Check for known zero input bits. 1284 APInt NeededMask = DesiredMask & ~ActualMask; 1285 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) 1286 return true; 1287 1288 // TODO: check to see if missing bits are just not demanded. 1289 1290 // Otherwise, this pattern doesn't match. 1291 return false; 1292} 1293 1294/// CheckOrMask - The isel is trying to match something like (or X, 255). If 1295/// the dag combiner simplified the 255, we still want to match. RHS is the 1296/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 1297/// specified in the .td file (e.g. 255). 1298bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS, 1299 int64_t DesiredMaskS) const { 1300 const APInt &ActualMask = RHS->getAPIntValue(); 1301 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1302 1303 // If the actual mask exactly matches, success! 1304 if (ActualMask == DesiredMask) 1305 return true; 1306 1307 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1308 if (ActualMask.intersects(~DesiredMask)) 1309 return false; 1310 1311 // Otherwise, the DAG Combiner may have proven that the value coming in is 1312 // either already zero or is not demanded. Check for known zero input bits. 1313 APInt NeededMask = DesiredMask & ~ActualMask; 1314 1315 APInt KnownZero, KnownOne; 1316 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne); 1317 1318 // If all the missing bits in the or are already known to be set, match! 1319 if ((NeededMask & KnownOne) == NeededMask) 1320 return true; 1321 1322 // TODO: check to see if missing bits are just not demanded. 1323 1324 // Otherwise, this pattern doesn't match. 1325 return false; 1326} 1327 1328 1329/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 1330/// by tblgen. Others should not call it. 1331void SelectionDAGISel:: 1332SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) { 1333 std::vector<SDValue> InOps; 1334 std::swap(InOps, Ops); 1335 1336 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0 1337 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1 1338 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc 1339 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack) 1340 1341 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size(); 1342 if (InOps[e-1].getValueType() == MVT::Glue) 1343 --e; // Don't process a glue operand if it is here. 1344 1345 while (i != e) { 1346 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue(); 1347 if (!InlineAsm::isMemKind(Flags)) { 1348 // Just skip over this operand, copying the operands verbatim. 1349 Ops.insert(Ops.end(), InOps.begin()+i, 1350 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1); 1351 i += InlineAsm::getNumOperandRegisters(Flags) + 1; 1352 } else { 1353 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 && 1354 "Memory operand with multiple values?"); 1355 // Otherwise, this is a memory operand. Ask the target to select it. 1356 std::vector<SDValue> SelOps; 1357 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) 1358 report_fatal_error("Could not match memory address. Inline asm" 1359 " failure!"); 1360 1361 // Add this to the output node. 1362 unsigned NewFlags = 1363 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size()); 1364 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32)); 1365 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 1366 i += 2; 1367 } 1368 } 1369 1370 // Add the glue input back if present. 1371 if (e != InOps.size()) 1372 Ops.push_back(InOps.back()); 1373} 1374 1375/// findGlueUse - Return use of MVT::Glue value produced by the specified 1376/// SDNode. 1377/// 1378static SDNode *findGlueUse(SDNode *N) { 1379 unsigned FlagResNo = N->getNumValues()-1; 1380 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 1381 SDUse &Use = I.getUse(); 1382 if (Use.getResNo() == FlagResNo) 1383 return Use.getUser(); 1384 } 1385 return NULL; 1386} 1387 1388/// findNonImmUse - Return true if "Use" is a non-immediate use of "Def". 1389/// This function recursively traverses up the operand chain, ignoring 1390/// certain nodes. 1391static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse, 1392 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited, 1393 bool IgnoreChains) { 1394 // The NodeID's are given uniques ID's where a node ID is guaranteed to be 1395 // greater than all of its (recursive) operands. If we scan to a point where 1396 // 'use' is smaller than the node we're scanning for, then we know we will 1397 // never find it. 1398 // 1399 // The Use may be -1 (unassigned) if it is a newly allocated node. This can 1400 // happen because we scan down to newly selected nodes in the case of glue 1401 // uses. 1402 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1)) 1403 return false; 1404 1405 // Don't revisit nodes if we already scanned it and didn't fail, we know we 1406 // won't fail if we scan it again. 1407 if (!Visited.insert(Use)) 1408 return false; 1409 1410 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) { 1411 // Ignore chain uses, they are validated by HandleMergeInputChains. 1412 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains) 1413 continue; 1414 1415 SDNode *N = Use->getOperand(i).getNode(); 1416 if (N == Def) { 1417 if (Use == ImmedUse || Use == Root) 1418 continue; // We are not looking for immediate use. 1419 assert(N != Root); 1420 return true; 1421 } 1422 1423 // Traverse up the operand chain. 1424 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains)) 1425 return true; 1426 } 1427 return false; 1428} 1429 1430/// IsProfitableToFold - Returns true if it's profitable to fold the specific 1431/// operand node N of U during instruction selection that starts at Root. 1432bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U, 1433 SDNode *Root) const { 1434 if (OptLevel == CodeGenOpt::None) return false; 1435 return N.hasOneUse(); 1436} 1437 1438/// IsLegalToFold - Returns true if the specific operand node N of 1439/// U can be folded during instruction selection that starts at Root. 1440bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root, 1441 CodeGenOpt::Level OptLevel, 1442 bool IgnoreChains) { 1443 if (OptLevel == CodeGenOpt::None) return false; 1444 1445 // If Root use can somehow reach N through a path that that doesn't contain 1446 // U then folding N would create a cycle. e.g. In the following 1447 // diagram, Root can reach N through X. If N is folded into into Root, then 1448 // X is both a predecessor and a successor of U. 1449 // 1450 // [N*] // 1451 // ^ ^ // 1452 // / \ // 1453 // [U*] [X]? // 1454 // ^ ^ // 1455 // \ / // 1456 // \ / // 1457 // [Root*] // 1458 // 1459 // * indicates nodes to be folded together. 1460 // 1461 // If Root produces glue, then it gets (even more) interesting. Since it 1462 // will be "glued" together with its glue use in the scheduler, we need to 1463 // check if it might reach N. 1464 // 1465 // [N*] // 1466 // ^ ^ // 1467 // / \ // 1468 // [U*] [X]? // 1469 // ^ ^ // 1470 // \ \ // 1471 // \ | // 1472 // [Root*] | // 1473 // ^ | // 1474 // f | // 1475 // | / // 1476 // [Y] / // 1477 // ^ / // 1478 // f / // 1479 // | / // 1480 // [GU] // 1481 // 1482 // If GU (glue use) indirectly reaches N (the load), and Root folds N 1483 // (call it Fold), then X is a predecessor of GU and a successor of 1484 // Fold. But since Fold and GU are glued together, this will create 1485 // a cycle in the scheduling graph. 1486 1487 // If the node has glue, walk down the graph to the "lowest" node in the 1488 // glueged set. 1489 EVT VT = Root->getValueType(Root->getNumValues()-1); 1490 while (VT == MVT::Glue) { 1491 SDNode *GU = findGlueUse(Root); 1492 if (GU == NULL) 1493 break; 1494 Root = GU; 1495 VT = Root->getValueType(Root->getNumValues()-1); 1496 1497 // If our query node has a glue result with a use, we've walked up it. If 1498 // the user (which has already been selected) has a chain or indirectly uses 1499 // the chain, our WalkChainUsers predicate will not consider it. Because of 1500 // this, we cannot ignore chains in this predicate. 1501 IgnoreChains = false; 1502 } 1503 1504 1505 SmallPtrSet<SDNode*, 16> Visited; 1506 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains); 1507} 1508 1509SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) { 1510 std::vector<SDValue> Ops(N->op_begin(), N->op_end()); 1511 SelectInlineAsmMemoryOperands(Ops); 1512 1513 std::vector<EVT> VTs; 1514 VTs.push_back(MVT::Other); 1515 VTs.push_back(MVT::Glue); 1516 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(), 1517 VTs, &Ops[0], Ops.size()); 1518 New->setNodeId(-1); 1519 return New.getNode(); 1520} 1521 1522SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) { 1523 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0)); 1524} 1525 1526/// GetVBR - decode a vbr encoding whose top bit is set. 1527LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t 1528GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) { 1529 assert(Val >= 128 && "Not a VBR"); 1530 Val &= 127; // Remove first vbr bit. 1531 1532 unsigned Shift = 7; 1533 uint64_t NextBits; 1534 do { 1535 NextBits = MatcherTable[Idx++]; 1536 Val |= (NextBits&127) << Shift; 1537 Shift += 7; 1538 } while (NextBits & 128); 1539 1540 return Val; 1541} 1542 1543 1544/// UpdateChainsAndGlue - When a match is complete, this method updates uses of 1545/// interior glue and chain results to use the new glue and chain results. 1546void SelectionDAGISel:: 1547UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain, 1548 const SmallVectorImpl<SDNode*> &ChainNodesMatched, 1549 SDValue InputGlue, 1550 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched, 1551 bool isMorphNodeTo) { 1552 SmallVector<SDNode*, 4> NowDeadNodes; 1553 1554 ISelUpdater ISU(ISelPosition); 1555 1556 // Now that all the normal results are replaced, we replace the chain and 1557 // glue results if present. 1558 if (!ChainNodesMatched.empty()) { 1559 assert(InputChain.getNode() != 0 && 1560 "Matched input chains but didn't produce a chain"); 1561 // Loop over all of the nodes we matched that produced a chain result. 1562 // Replace all the chain results with the final chain we ended up with. 1563 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1564 SDNode *ChainNode = ChainNodesMatched[i]; 1565 1566 // If this node was already deleted, don't look at it. 1567 if (ChainNode->getOpcode() == ISD::DELETED_NODE) 1568 continue; 1569 1570 // Don't replace the results of the root node if we're doing a 1571 // MorphNodeTo. 1572 if (ChainNode == NodeToMatch && isMorphNodeTo) 1573 continue; 1574 1575 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1); 1576 if (ChainVal.getValueType() == MVT::Glue) 1577 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2); 1578 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?"); 1579 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain, &ISU); 1580 1581 // If the node became dead and we haven't already seen it, delete it. 1582 if (ChainNode->use_empty() && 1583 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode)) 1584 NowDeadNodes.push_back(ChainNode); 1585 } 1586 } 1587 1588 // If the result produces glue, update any glue results in the matched 1589 // pattern with the glue result. 1590 if (InputGlue.getNode() != 0) { 1591 // Handle any interior nodes explicitly marked. 1592 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) { 1593 SDNode *FRN = GlueResultNodesMatched[i]; 1594 1595 // If this node was already deleted, don't look at it. 1596 if (FRN->getOpcode() == ISD::DELETED_NODE) 1597 continue; 1598 1599 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue && 1600 "Doesn't have a glue result"); 1601 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1), 1602 InputGlue, &ISU); 1603 1604 // If the node became dead and we haven't already seen it, delete it. 1605 if (FRN->use_empty() && 1606 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN)) 1607 NowDeadNodes.push_back(FRN); 1608 } 1609 } 1610 1611 if (!NowDeadNodes.empty()) 1612 CurDAG->RemoveDeadNodes(NowDeadNodes, &ISU); 1613 1614 DEBUG(errs() << "ISEL: Match complete!\n"); 1615} 1616 1617enum ChainResult { 1618 CR_Simple, 1619 CR_InducesCycle, 1620 CR_LeadsToInteriorNode 1621}; 1622 1623/// WalkChainUsers - Walk down the users of the specified chained node that is 1624/// part of the pattern we're matching, looking at all of the users we find. 1625/// This determines whether something is an interior node, whether we have a 1626/// non-pattern node in between two pattern nodes (which prevent folding because 1627/// it would induce a cycle) and whether we have a TokenFactor node sandwiched 1628/// between pattern nodes (in which case the TF becomes part of the pattern). 1629/// 1630/// The walk we do here is guaranteed to be small because we quickly get down to 1631/// already selected nodes "below" us. 1632static ChainResult 1633WalkChainUsers(SDNode *ChainedNode, 1634 SmallVectorImpl<SDNode*> &ChainedNodesInPattern, 1635 SmallVectorImpl<SDNode*> &InteriorChainedNodes) { 1636 ChainResult Result = CR_Simple; 1637 1638 for (SDNode::use_iterator UI = ChainedNode->use_begin(), 1639 E = ChainedNode->use_end(); UI != E; ++UI) { 1640 // Make sure the use is of the chain, not some other value we produce. 1641 if (UI.getUse().getValueType() != MVT::Other) continue; 1642 1643 SDNode *User = *UI; 1644 1645 // If we see an already-selected machine node, then we've gone beyond the 1646 // pattern that we're selecting down into the already selected chunk of the 1647 // DAG. 1648 if (User->isMachineOpcode() || 1649 User->getOpcode() == ISD::HANDLENODE) // Root of the graph. 1650 continue; 1651 1652 if (User->getOpcode() == ISD::CopyToReg || 1653 User->getOpcode() == ISD::CopyFromReg || 1654 User->getOpcode() == ISD::INLINEASM || 1655 User->getOpcode() == ISD::EH_LABEL) { 1656 // If their node ID got reset to -1 then they've already been selected. 1657 // Treat them like a MachineOpcode. 1658 if (User->getNodeId() == -1) 1659 continue; 1660 } 1661 1662 // If we have a TokenFactor, we handle it specially. 1663 if (User->getOpcode() != ISD::TokenFactor) { 1664 // If the node isn't a token factor and isn't part of our pattern, then it 1665 // must be a random chained node in between two nodes we're selecting. 1666 // This happens when we have something like: 1667 // x = load ptr 1668 // call 1669 // y = x+4 1670 // store y -> ptr 1671 // Because we structurally match the load/store as a read/modify/write, 1672 // but the call is chained between them. We cannot fold in this case 1673 // because it would induce a cycle in the graph. 1674 if (!std::count(ChainedNodesInPattern.begin(), 1675 ChainedNodesInPattern.end(), User)) 1676 return CR_InducesCycle; 1677 1678 // Otherwise we found a node that is part of our pattern. For example in: 1679 // x = load ptr 1680 // y = x+4 1681 // store y -> ptr 1682 // This would happen when we're scanning down from the load and see the 1683 // store as a user. Record that there is a use of ChainedNode that is 1684 // part of the pattern and keep scanning uses. 1685 Result = CR_LeadsToInteriorNode; 1686 InteriorChainedNodes.push_back(User); 1687 continue; 1688 } 1689 1690 // If we found a TokenFactor, there are two cases to consider: first if the 1691 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no 1692 // uses of the TF are in our pattern) we just want to ignore it. Second, 1693 // the TokenFactor can be sandwiched in between two chained nodes, like so: 1694 // [Load chain] 1695 // ^ 1696 // | 1697 // [Load] 1698 // ^ ^ 1699 // | \ DAG's like cheese 1700 // / \ do you? 1701 // / | 1702 // [TokenFactor] [Op] 1703 // ^ ^ 1704 // | | 1705 // \ / 1706 // \ / 1707 // [Store] 1708 // 1709 // In this case, the TokenFactor becomes part of our match and we rewrite it 1710 // as a new TokenFactor. 1711 // 1712 // To distinguish these two cases, do a recursive walk down the uses. 1713 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) { 1714 case CR_Simple: 1715 // If the uses of the TokenFactor are just already-selected nodes, ignore 1716 // it, it is "below" our pattern. 1717 continue; 1718 case CR_InducesCycle: 1719 // If the uses of the TokenFactor lead to nodes that are not part of our 1720 // pattern that are not selected, folding would turn this into a cycle, 1721 // bail out now. 1722 return CR_InducesCycle; 1723 case CR_LeadsToInteriorNode: 1724 break; // Otherwise, keep processing. 1725 } 1726 1727 // Okay, we know we're in the interesting interior case. The TokenFactor 1728 // is now going to be considered part of the pattern so that we rewrite its 1729 // uses (it may have uses that are not part of the pattern) with the 1730 // ultimate chain result of the generated code. We will also add its chain 1731 // inputs as inputs to the ultimate TokenFactor we create. 1732 Result = CR_LeadsToInteriorNode; 1733 ChainedNodesInPattern.push_back(User); 1734 InteriorChainedNodes.push_back(User); 1735 continue; 1736 } 1737 1738 return Result; 1739} 1740 1741/// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains 1742/// operation for when the pattern matched at least one node with a chains. The 1743/// input vector contains a list of all of the chained nodes that we match. We 1744/// must determine if this is a valid thing to cover (i.e. matching it won't 1745/// induce cycles in the DAG) and if so, creating a TokenFactor node. that will 1746/// be used as the input node chain for the generated nodes. 1747static SDValue 1748HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched, 1749 SelectionDAG *CurDAG) { 1750 // Walk all of the chained nodes we've matched, recursively scanning down the 1751 // users of the chain result. This adds any TokenFactor nodes that are caught 1752 // in between chained nodes to the chained and interior nodes list. 1753 SmallVector<SDNode*, 3> InteriorChainedNodes; 1754 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1755 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched, 1756 InteriorChainedNodes) == CR_InducesCycle) 1757 return SDValue(); // Would induce a cycle. 1758 } 1759 1760 // Okay, we have walked all the matched nodes and collected TokenFactor nodes 1761 // that we are interested in. Form our input TokenFactor node. 1762 SmallVector<SDValue, 3> InputChains; 1763 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1764 // Add the input chain of this node to the InputChains list (which will be 1765 // the operands of the generated TokenFactor) if it's not an interior node. 1766 SDNode *N = ChainNodesMatched[i]; 1767 if (N->getOpcode() != ISD::TokenFactor) { 1768 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N)) 1769 continue; 1770 1771 // Otherwise, add the input chain. 1772 SDValue InChain = ChainNodesMatched[i]->getOperand(0); 1773 assert(InChain.getValueType() == MVT::Other && "Not a chain"); 1774 InputChains.push_back(InChain); 1775 continue; 1776 } 1777 1778 // If we have a token factor, we want to add all inputs of the token factor 1779 // that are not part of the pattern we're matching. 1780 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) { 1781 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(), 1782 N->getOperand(op).getNode())) 1783 InputChains.push_back(N->getOperand(op)); 1784 } 1785 } 1786 1787 SDValue Res; 1788 if (InputChains.size() == 1) 1789 return InputChains[0]; 1790 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(), 1791 MVT::Other, &InputChains[0], InputChains.size()); 1792} 1793 1794/// MorphNode - Handle morphing a node in place for the selector. 1795SDNode *SelectionDAGISel:: 1796MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList, 1797 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) { 1798 // It is possible we're using MorphNodeTo to replace a node with no 1799 // normal results with one that has a normal result (or we could be 1800 // adding a chain) and the input could have glue and chains as well. 1801 // In this case we need to shift the operands down. 1802 // FIXME: This is a horrible hack and broken in obscure cases, no worse 1803 // than the old isel though. 1804 int OldGlueResultNo = -1, OldChainResultNo = -1; 1805 1806 unsigned NTMNumResults = Node->getNumValues(); 1807 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) { 1808 OldGlueResultNo = NTMNumResults-1; 1809 if (NTMNumResults != 1 && 1810 Node->getValueType(NTMNumResults-2) == MVT::Other) 1811 OldChainResultNo = NTMNumResults-2; 1812 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other) 1813 OldChainResultNo = NTMNumResults-1; 1814 1815 // Call the underlying SelectionDAG routine to do the transmogrification. Note 1816 // that this deletes operands of the old node that become dead. 1817 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps); 1818 1819 // MorphNodeTo can operate in two ways: if an existing node with the 1820 // specified operands exists, it can just return it. Otherwise, it 1821 // updates the node in place to have the requested operands. 1822 if (Res == Node) { 1823 // If we updated the node in place, reset the node ID. To the isel, 1824 // this should be just like a newly allocated machine node. 1825 Res->setNodeId(-1); 1826 } 1827 1828 unsigned ResNumResults = Res->getNumValues(); 1829 // Move the glue if needed. 1830 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 && 1831 (unsigned)OldGlueResultNo != ResNumResults-1) 1832 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo), 1833 SDValue(Res, ResNumResults-1)); 1834 1835 if ((EmitNodeInfo & OPFL_GlueOutput) != 0) 1836 --ResNumResults; 1837 1838 // Move the chain reference if needed. 1839 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 && 1840 (unsigned)OldChainResultNo != ResNumResults-1) 1841 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo), 1842 SDValue(Res, ResNumResults-1)); 1843 1844 // Otherwise, no replacement happened because the node already exists. Replace 1845 // Uses of the old node with the new one. 1846 if (Res != Node) 1847 CurDAG->ReplaceAllUsesWith(Node, Res); 1848 1849 return Res; 1850} 1851 1852/// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 1853LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 1854CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1855 SDValue N, 1856 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) { 1857 // Accept if it is exactly the same as a previously recorded node. 1858 unsigned RecNo = MatcherTable[MatcherIndex++]; 1859 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 1860 return N == RecordedNodes[RecNo].first; 1861} 1862 1863/// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 1864LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 1865CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1866 SelectionDAGISel &SDISel) { 1867 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]); 1868} 1869 1870/// CheckNodePredicate - Implements OP_CheckNodePredicate. 1871LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 1872CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1873 SelectionDAGISel &SDISel, SDNode *N) { 1874 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]); 1875} 1876 1877LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 1878CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1879 SDNode *N) { 1880 uint16_t Opc = MatcherTable[MatcherIndex++]; 1881 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 1882 return N->getOpcode() == Opc; 1883} 1884 1885LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 1886CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1887 SDValue N, const TargetLowering &TLI) { 1888 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 1889 if (N.getValueType() == VT) return true; 1890 1891 // Handle the case when VT is iPTR. 1892 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy(); 1893} 1894 1895LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 1896CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1897 SDValue N, const TargetLowering &TLI, 1898 unsigned ChildNo) { 1899 if (ChildNo >= N.getNumOperands()) 1900 return false; // Match fails if out of range child #. 1901 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI); 1902} 1903 1904 1905LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 1906CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1907 SDValue N) { 1908 return cast<CondCodeSDNode>(N)->get() == 1909 (ISD::CondCode)MatcherTable[MatcherIndex++]; 1910} 1911 1912LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 1913CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1914 SDValue N, const TargetLowering &TLI) { 1915 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 1916 if (cast<VTSDNode>(N)->getVT() == VT) 1917 return true; 1918 1919 // Handle the case when VT is iPTR. 1920 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy(); 1921} 1922 1923LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 1924CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1925 SDValue N) { 1926 int64_t Val = MatcherTable[MatcherIndex++]; 1927 if (Val & 128) 1928 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1929 1930 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N); 1931 return C != 0 && C->getSExtValue() == Val; 1932} 1933 1934LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 1935CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1936 SDValue N, SelectionDAGISel &SDISel) { 1937 int64_t Val = MatcherTable[MatcherIndex++]; 1938 if (Val & 128) 1939 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1940 1941 if (N->getOpcode() != ISD::AND) return false; 1942 1943 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 1944 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val); 1945} 1946 1947LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 1948CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1949 SDValue N, SelectionDAGISel &SDISel) { 1950 int64_t Val = MatcherTable[MatcherIndex++]; 1951 if (Val & 128) 1952 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1953 1954 if (N->getOpcode() != ISD::OR) return false; 1955 1956 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 1957 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val); 1958} 1959 1960/// IsPredicateKnownToFail - If we know how and can do so without pushing a 1961/// scope, evaluate the current node. If the current predicate is known to 1962/// fail, set Result=true and return anything. If the current predicate is 1963/// known to pass, set Result=false and return the MatcherIndex to continue 1964/// with. If the current predicate is unknown, set Result=false and return the 1965/// MatcherIndex to continue with. 1966static unsigned IsPredicateKnownToFail(const unsigned char *Table, 1967 unsigned Index, SDValue N, 1968 bool &Result, SelectionDAGISel &SDISel, 1969 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) { 1970 switch (Table[Index++]) { 1971 default: 1972 Result = false; 1973 return Index-1; // Could not evaluate this predicate. 1974 case SelectionDAGISel::OPC_CheckSame: 1975 Result = !::CheckSame(Table, Index, N, RecordedNodes); 1976 return Index; 1977 case SelectionDAGISel::OPC_CheckPatternPredicate: 1978 Result = !::CheckPatternPredicate(Table, Index, SDISel); 1979 return Index; 1980 case SelectionDAGISel::OPC_CheckPredicate: 1981 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode()); 1982 return Index; 1983 case SelectionDAGISel::OPC_CheckOpcode: 1984 Result = !::CheckOpcode(Table, Index, N.getNode()); 1985 return Index; 1986 case SelectionDAGISel::OPC_CheckType: 1987 Result = !::CheckType(Table, Index, N, SDISel.TLI); 1988 return Index; 1989 case SelectionDAGISel::OPC_CheckChild0Type: 1990 case SelectionDAGISel::OPC_CheckChild1Type: 1991 case SelectionDAGISel::OPC_CheckChild2Type: 1992 case SelectionDAGISel::OPC_CheckChild3Type: 1993 case SelectionDAGISel::OPC_CheckChild4Type: 1994 case SelectionDAGISel::OPC_CheckChild5Type: 1995 case SelectionDAGISel::OPC_CheckChild6Type: 1996 case SelectionDAGISel::OPC_CheckChild7Type: 1997 Result = !::CheckChildType(Table, Index, N, SDISel.TLI, 1998 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type); 1999 return Index; 2000 case SelectionDAGISel::OPC_CheckCondCode: 2001 Result = !::CheckCondCode(Table, Index, N); 2002 return Index; 2003 case SelectionDAGISel::OPC_CheckValueType: 2004 Result = !::CheckValueType(Table, Index, N, SDISel.TLI); 2005 return Index; 2006 case SelectionDAGISel::OPC_CheckInteger: 2007 Result = !::CheckInteger(Table, Index, N); 2008 return Index; 2009 case SelectionDAGISel::OPC_CheckAndImm: 2010 Result = !::CheckAndImm(Table, Index, N, SDISel); 2011 return Index; 2012 case SelectionDAGISel::OPC_CheckOrImm: 2013 Result = !::CheckOrImm(Table, Index, N, SDISel); 2014 return Index; 2015 } 2016} 2017 2018namespace { 2019 2020struct MatchScope { 2021 /// FailIndex - If this match fails, this is the index to continue with. 2022 unsigned FailIndex; 2023 2024 /// NodeStack - The node stack when the scope was formed. 2025 SmallVector<SDValue, 4> NodeStack; 2026 2027 /// NumRecordedNodes - The number of recorded nodes when the scope was formed. 2028 unsigned NumRecordedNodes; 2029 2030 /// NumMatchedMemRefs - The number of matched memref entries. 2031 unsigned NumMatchedMemRefs; 2032 2033 /// InputChain/InputGlue - The current chain/glue 2034 SDValue InputChain, InputGlue; 2035 2036 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty. 2037 bool HasChainNodesMatched, HasGlueResultNodesMatched; 2038}; 2039 2040} 2041 2042SDNode *SelectionDAGISel:: 2043SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable, 2044 unsigned TableSize) { 2045 // FIXME: Should these even be selected? Handle these cases in the caller? 2046 switch (NodeToMatch->getOpcode()) { 2047 default: 2048 break; 2049 case ISD::EntryToken: // These nodes remain the same. 2050 case ISD::BasicBlock: 2051 case ISD::Register: 2052 //case ISD::VALUETYPE: 2053 //case ISD::CONDCODE: 2054 case ISD::HANDLENODE: 2055 case ISD::MDNODE_SDNODE: 2056 case ISD::TargetConstant: 2057 case ISD::TargetConstantFP: 2058 case ISD::TargetConstantPool: 2059 case ISD::TargetFrameIndex: 2060 case ISD::TargetExternalSymbol: 2061 case ISD::TargetBlockAddress: 2062 case ISD::TargetJumpTable: 2063 case ISD::TargetGlobalTLSAddress: 2064 case ISD::TargetGlobalAddress: 2065 case ISD::TokenFactor: 2066 case ISD::CopyFromReg: 2067 case ISD::CopyToReg: 2068 case ISD::EH_LABEL: 2069 NodeToMatch->setNodeId(-1); // Mark selected. 2070 return 0; 2071 case ISD::AssertSext: 2072 case ISD::AssertZext: 2073 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0), 2074 NodeToMatch->getOperand(0)); 2075 return 0; 2076 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch); 2077 case ISD::UNDEF: return Select_UNDEF(NodeToMatch); 2078 } 2079 2080 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!"); 2081 2082 // Set up the node stack with NodeToMatch as the only node on the stack. 2083 SmallVector<SDValue, 8> NodeStack; 2084 SDValue N = SDValue(NodeToMatch, 0); 2085 NodeStack.push_back(N); 2086 2087 // MatchScopes - Scopes used when matching, if a match failure happens, this 2088 // indicates where to continue checking. 2089 SmallVector<MatchScope, 8> MatchScopes; 2090 2091 // RecordedNodes - This is the set of nodes that have been recorded by the 2092 // state machine. The second value is the parent of the node, or null if the 2093 // root is recorded. 2094 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes; 2095 2096 // MatchedMemRefs - This is the set of MemRef's we've seen in the input 2097 // pattern. 2098 SmallVector<MachineMemOperand*, 2> MatchedMemRefs; 2099 2100 // These are the current input chain and glue for use when generating nodes. 2101 // Various Emit operations change these. For example, emitting a copytoreg 2102 // uses and updates these. 2103 SDValue InputChain, InputGlue; 2104 2105 // ChainNodesMatched - If a pattern matches nodes that have input/output 2106 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates 2107 // which ones they are. The result is captured into this list so that we can 2108 // update the chain results when the pattern is complete. 2109 SmallVector<SDNode*, 3> ChainNodesMatched; 2110 SmallVector<SDNode*, 3> GlueResultNodesMatched; 2111 2112 DEBUG(errs() << "ISEL: Starting pattern match on root node: "; 2113 NodeToMatch->dump(CurDAG); 2114 errs() << '\n'); 2115 2116 // Determine where to start the interpreter. Normally we start at opcode #0, 2117 // but if the state machine starts with an OPC_SwitchOpcode, then we 2118 // accelerate the first lookup (which is guaranteed to be hot) with the 2119 // OpcodeOffset table. 2120 unsigned MatcherIndex = 0; 2121 2122 if (!OpcodeOffset.empty()) { 2123 // Already computed the OpcodeOffset table, just index into it. 2124 if (N.getOpcode() < OpcodeOffset.size()) 2125 MatcherIndex = OpcodeOffset[N.getOpcode()]; 2126 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n"); 2127 2128 } else if (MatcherTable[0] == OPC_SwitchOpcode) { 2129 // Otherwise, the table isn't computed, but the state machine does start 2130 // with an OPC_SwitchOpcode instruction. Populate the table now, since this 2131 // is the first time we're selecting an instruction. 2132 unsigned Idx = 1; 2133 while (1) { 2134 // Get the size of this case. 2135 unsigned CaseSize = MatcherTable[Idx++]; 2136 if (CaseSize & 128) 2137 CaseSize = GetVBR(CaseSize, MatcherTable, Idx); 2138 if (CaseSize == 0) break; 2139 2140 // Get the opcode, add the index to the table. 2141 uint16_t Opc = MatcherTable[Idx++]; 2142 Opc |= (unsigned short)MatcherTable[Idx++] << 8; 2143 if (Opc >= OpcodeOffset.size()) 2144 OpcodeOffset.resize((Opc+1)*2); 2145 OpcodeOffset[Opc] = Idx; 2146 Idx += CaseSize; 2147 } 2148 2149 // Okay, do the lookup for the first opcode. 2150 if (N.getOpcode() < OpcodeOffset.size()) 2151 MatcherIndex = OpcodeOffset[N.getOpcode()]; 2152 } 2153 2154 while (1) { 2155 assert(MatcherIndex < TableSize && "Invalid index"); 2156#ifndef NDEBUG 2157 unsigned CurrentOpcodeIndex = MatcherIndex; 2158#endif 2159 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++]; 2160 switch (Opcode) { 2161 case OPC_Scope: { 2162 // Okay, the semantics of this operation are that we should push a scope 2163 // then evaluate the first child. However, pushing a scope only to have 2164 // the first check fail (which then pops it) is inefficient. If we can 2165 // determine immediately that the first check (or first several) will 2166 // immediately fail, don't even bother pushing a scope for them. 2167 unsigned FailIndex; 2168 2169 while (1) { 2170 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2171 if (NumToSkip & 128) 2172 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2173 // Found the end of the scope with no match. 2174 if (NumToSkip == 0) { 2175 FailIndex = 0; 2176 break; 2177 } 2178 2179 FailIndex = MatcherIndex+NumToSkip; 2180 2181 unsigned MatcherIndexOfPredicate = MatcherIndex; 2182 (void)MatcherIndexOfPredicate; // silence warning. 2183 2184 // If we can't evaluate this predicate without pushing a scope (e.g. if 2185 // it is a 'MoveParent') or if the predicate succeeds on this node, we 2186 // push the scope and evaluate the full predicate chain. 2187 bool Result; 2188 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N, 2189 Result, *this, RecordedNodes); 2190 if (!Result) 2191 break; 2192 2193 DEBUG(errs() << " Skipped scope entry (due to false predicate) at " 2194 << "index " << MatcherIndexOfPredicate 2195 << ", continuing at " << FailIndex << "\n"); 2196 ++NumDAGIselRetries; 2197 2198 // Otherwise, we know that this case of the Scope is guaranteed to fail, 2199 // move to the next case. 2200 MatcherIndex = FailIndex; 2201 } 2202 2203 // If the whole scope failed to match, bail. 2204 if (FailIndex == 0) break; 2205 2206 // Push a MatchScope which indicates where to go if the first child fails 2207 // to match. 2208 MatchScope NewEntry; 2209 NewEntry.FailIndex = FailIndex; 2210 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end()); 2211 NewEntry.NumRecordedNodes = RecordedNodes.size(); 2212 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size(); 2213 NewEntry.InputChain = InputChain; 2214 NewEntry.InputGlue = InputGlue; 2215 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty(); 2216 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty(); 2217 MatchScopes.push_back(NewEntry); 2218 continue; 2219 } 2220 case OPC_RecordNode: { 2221 // Remember this node, it may end up being an operand in the pattern. 2222 SDNode *Parent = 0; 2223 if (NodeStack.size() > 1) 2224 Parent = NodeStack[NodeStack.size()-2].getNode(); 2225 RecordedNodes.push_back(std::make_pair(N, Parent)); 2226 continue; 2227 } 2228 2229 case OPC_RecordChild0: case OPC_RecordChild1: 2230 case OPC_RecordChild2: case OPC_RecordChild3: 2231 case OPC_RecordChild4: case OPC_RecordChild5: 2232 case OPC_RecordChild6: case OPC_RecordChild7: { 2233 unsigned ChildNo = Opcode-OPC_RecordChild0; 2234 if (ChildNo >= N.getNumOperands()) 2235 break; // Match fails if out of range child #. 2236 2237 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo), 2238 N.getNode())); 2239 continue; 2240 } 2241 case OPC_RecordMemRef: 2242 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand()); 2243 continue; 2244 2245 case OPC_CaptureGlueInput: 2246 // If the current node has an input glue, capture it in InputGlue. 2247 if (N->getNumOperands() != 0 && 2248 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue) 2249 InputGlue = N->getOperand(N->getNumOperands()-1); 2250 continue; 2251 2252 case OPC_MoveChild: { 2253 unsigned ChildNo = MatcherTable[MatcherIndex++]; 2254 if (ChildNo >= N.getNumOperands()) 2255 break; // Match fails if out of range child #. 2256 N = N.getOperand(ChildNo); 2257 NodeStack.push_back(N); 2258 continue; 2259 } 2260 2261 case OPC_MoveParent: 2262 // Pop the current node off the NodeStack. 2263 NodeStack.pop_back(); 2264 assert(!NodeStack.empty() && "Node stack imbalance!"); 2265 N = NodeStack.back(); 2266 continue; 2267 2268 case OPC_CheckSame: 2269 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break; 2270 continue; 2271 case OPC_CheckPatternPredicate: 2272 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break; 2273 continue; 2274 case OPC_CheckPredicate: 2275 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this, 2276 N.getNode())) 2277 break; 2278 continue; 2279 case OPC_CheckComplexPat: { 2280 unsigned CPNum = MatcherTable[MatcherIndex++]; 2281 unsigned RecNo = MatcherTable[MatcherIndex++]; 2282 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat"); 2283 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second, 2284 RecordedNodes[RecNo].first, CPNum, 2285 RecordedNodes)) 2286 break; 2287 continue; 2288 } 2289 case OPC_CheckOpcode: 2290 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break; 2291 continue; 2292 2293 case OPC_CheckType: 2294 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break; 2295 continue; 2296 2297 case OPC_SwitchOpcode: { 2298 unsigned CurNodeOpcode = N.getOpcode(); 2299 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2300 unsigned CaseSize; 2301 while (1) { 2302 // Get the size of this case. 2303 CaseSize = MatcherTable[MatcherIndex++]; 2304 if (CaseSize & 128) 2305 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2306 if (CaseSize == 0) break; 2307 2308 uint16_t Opc = MatcherTable[MatcherIndex++]; 2309 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2310 2311 // If the opcode matches, then we will execute this case. 2312 if (CurNodeOpcode == Opc) 2313 break; 2314 2315 // Otherwise, skip over this case. 2316 MatcherIndex += CaseSize; 2317 } 2318 2319 // If no cases matched, bail out. 2320 if (CaseSize == 0) break; 2321 2322 // Otherwise, execute the case we found. 2323 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart 2324 << " to " << MatcherIndex << "\n"); 2325 continue; 2326 } 2327 2328 case OPC_SwitchType: { 2329 MVT CurNodeVT = N.getValueType().getSimpleVT(); 2330 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2331 unsigned CaseSize; 2332 while (1) { 2333 // Get the size of this case. 2334 CaseSize = MatcherTable[MatcherIndex++]; 2335 if (CaseSize & 128) 2336 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2337 if (CaseSize == 0) break; 2338 2339 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2340 if (CaseVT == MVT::iPTR) 2341 CaseVT = TLI.getPointerTy(); 2342 2343 // If the VT matches, then we will execute this case. 2344 if (CurNodeVT == CaseVT) 2345 break; 2346 2347 // Otherwise, skip over this case. 2348 MatcherIndex += CaseSize; 2349 } 2350 2351 // If no cases matched, bail out. 2352 if (CaseSize == 0) break; 2353 2354 // Otherwise, execute the case we found. 2355 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString() 2356 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n'); 2357 continue; 2358 } 2359 case OPC_CheckChild0Type: case OPC_CheckChild1Type: 2360 case OPC_CheckChild2Type: case OPC_CheckChild3Type: 2361 case OPC_CheckChild4Type: case OPC_CheckChild5Type: 2362 case OPC_CheckChild6Type: case OPC_CheckChild7Type: 2363 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI, 2364 Opcode-OPC_CheckChild0Type)) 2365 break; 2366 continue; 2367 case OPC_CheckCondCode: 2368 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break; 2369 continue; 2370 case OPC_CheckValueType: 2371 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break; 2372 continue; 2373 case OPC_CheckInteger: 2374 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break; 2375 continue; 2376 case OPC_CheckAndImm: 2377 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break; 2378 continue; 2379 case OPC_CheckOrImm: 2380 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break; 2381 continue; 2382 2383 case OPC_CheckFoldableChainNode: { 2384 assert(NodeStack.size() != 1 && "No parent node"); 2385 // Verify that all intermediate nodes between the root and this one have 2386 // a single use. 2387 bool HasMultipleUses = false; 2388 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i) 2389 if (!NodeStack[i].hasOneUse()) { 2390 HasMultipleUses = true; 2391 break; 2392 } 2393 if (HasMultipleUses) break; 2394 2395 // Check to see that the target thinks this is profitable to fold and that 2396 // we can fold it without inducing cycles in the graph. 2397 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2398 NodeToMatch) || 2399 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2400 NodeToMatch, OptLevel, 2401 true/*We validate our own chains*/)) 2402 break; 2403 2404 continue; 2405 } 2406 case OPC_EmitInteger: { 2407 MVT::SimpleValueType VT = 2408 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2409 int64_t Val = MatcherTable[MatcherIndex++]; 2410 if (Val & 128) 2411 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2412 RecordedNodes.push_back(std::pair<SDValue, SDNode*>( 2413 CurDAG->getTargetConstant(Val, VT), (SDNode*)0)); 2414 continue; 2415 } 2416 case OPC_EmitRegister: { 2417 MVT::SimpleValueType VT = 2418 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2419 unsigned RegNo = MatcherTable[MatcherIndex++]; 2420 RecordedNodes.push_back(std::pair<SDValue, SDNode*>( 2421 CurDAG->getRegister(RegNo, VT), (SDNode*)0)); 2422 continue; 2423 } 2424 case OPC_EmitRegister2: { 2425 // For targets w/ more than 256 register names, the register enum 2426 // values are stored in two bytes in the matcher table (just like 2427 // opcodes). 2428 MVT::SimpleValueType VT = 2429 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2430 unsigned RegNo = MatcherTable[MatcherIndex++]; 2431 RegNo |= MatcherTable[MatcherIndex++] << 8; 2432 RecordedNodes.push_back(std::pair<SDValue, SDNode*>( 2433 CurDAG->getRegister(RegNo, VT), (SDNode*)0)); 2434 continue; 2435 } 2436 2437 case OPC_EmitConvertToTarget: { 2438 // Convert from IMM/FPIMM to target version. 2439 unsigned RecNo = MatcherTable[MatcherIndex++]; 2440 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2441 SDValue Imm = RecordedNodes[RecNo].first; 2442 2443 if (Imm->getOpcode() == ISD::Constant) { 2444 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue(); 2445 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType()); 2446 } else if (Imm->getOpcode() == ISD::ConstantFP) { 2447 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue(); 2448 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType()); 2449 } 2450 2451 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second)); 2452 continue; 2453 } 2454 2455 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0 2456 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1 2457 // These are space-optimized forms of OPC_EmitMergeInputChains. 2458 assert(InputChain.getNode() == 0 && 2459 "EmitMergeInputChains should be the first chain producing node"); 2460 assert(ChainNodesMatched.empty() && 2461 "Should only have one EmitMergeInputChains per match"); 2462 2463 // Read all of the chained nodes. 2464 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1; 2465 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2466 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode()); 2467 2468 // FIXME: What if other value results of the node have uses not matched 2469 // by this pattern? 2470 if (ChainNodesMatched.back() != NodeToMatch && 2471 !RecordedNodes[RecNo].first.hasOneUse()) { 2472 ChainNodesMatched.clear(); 2473 break; 2474 } 2475 2476 // Merge the input chains if they are not intra-pattern references. 2477 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2478 2479 if (InputChain.getNode() == 0) 2480 break; // Failed to merge. 2481 continue; 2482 } 2483 2484 case OPC_EmitMergeInputChains: { 2485 assert(InputChain.getNode() == 0 && 2486 "EmitMergeInputChains should be the first chain producing node"); 2487 // This node gets a list of nodes we matched in the input that have 2488 // chains. We want to token factor all of the input chains to these nodes 2489 // together. However, if any of the input chains is actually one of the 2490 // nodes matched in this pattern, then we have an intra-match reference. 2491 // Ignore these because the newly token factored chain should not refer to 2492 // the old nodes. 2493 unsigned NumChains = MatcherTable[MatcherIndex++]; 2494 assert(NumChains != 0 && "Can't TF zero chains"); 2495 2496 assert(ChainNodesMatched.empty() && 2497 "Should only have one EmitMergeInputChains per match"); 2498 2499 // Read all of the chained nodes. 2500 for (unsigned i = 0; i != NumChains; ++i) { 2501 unsigned RecNo = MatcherTable[MatcherIndex++]; 2502 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2503 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode()); 2504 2505 // FIXME: What if other value results of the node have uses not matched 2506 // by this pattern? 2507 if (ChainNodesMatched.back() != NodeToMatch && 2508 !RecordedNodes[RecNo].first.hasOneUse()) { 2509 ChainNodesMatched.clear(); 2510 break; 2511 } 2512 } 2513 2514 // If the inner loop broke out, the match fails. 2515 if (ChainNodesMatched.empty()) 2516 break; 2517 2518 // Merge the input chains if they are not intra-pattern references. 2519 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2520 2521 if (InputChain.getNode() == 0) 2522 break; // Failed to merge. 2523 2524 continue; 2525 } 2526 2527 case OPC_EmitCopyToReg: { 2528 unsigned RecNo = MatcherTable[MatcherIndex++]; 2529 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2530 unsigned DestPhysReg = MatcherTable[MatcherIndex++]; 2531 2532 if (InputChain.getNode() == 0) 2533 InputChain = CurDAG->getEntryNode(); 2534 2535 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(), 2536 DestPhysReg, RecordedNodes[RecNo].first, 2537 InputGlue); 2538 2539 InputGlue = InputChain.getValue(1); 2540 continue; 2541 } 2542 2543 case OPC_EmitNodeXForm: { 2544 unsigned XFormNo = MatcherTable[MatcherIndex++]; 2545 unsigned RecNo = MatcherTable[MatcherIndex++]; 2546 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2547 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo); 2548 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, (SDNode*) 0)); 2549 continue; 2550 } 2551 2552 case OPC_EmitNode: 2553 case OPC_MorphNodeTo: { 2554 uint16_t TargetOpc = MatcherTable[MatcherIndex++]; 2555 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2556 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++]; 2557 // Get the result VT list. 2558 unsigned NumVTs = MatcherTable[MatcherIndex++]; 2559 SmallVector<EVT, 4> VTs; 2560 for (unsigned i = 0; i != NumVTs; ++i) { 2561 MVT::SimpleValueType VT = 2562 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2563 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy; 2564 VTs.push_back(VT); 2565 } 2566 2567 if (EmitNodeInfo & OPFL_Chain) 2568 VTs.push_back(MVT::Other); 2569 if (EmitNodeInfo & OPFL_GlueOutput) 2570 VTs.push_back(MVT::Glue); 2571 2572 // This is hot code, so optimize the two most common cases of 1 and 2 2573 // results. 2574 SDVTList VTList; 2575 if (VTs.size() == 1) 2576 VTList = CurDAG->getVTList(VTs[0]); 2577 else if (VTs.size() == 2) 2578 VTList = CurDAG->getVTList(VTs[0], VTs[1]); 2579 else 2580 VTList = CurDAG->getVTList(VTs.data(), VTs.size()); 2581 2582 // Get the operand list. 2583 unsigned NumOps = MatcherTable[MatcherIndex++]; 2584 SmallVector<SDValue, 8> Ops; 2585 for (unsigned i = 0; i != NumOps; ++i) { 2586 unsigned RecNo = MatcherTable[MatcherIndex++]; 2587 if (RecNo & 128) 2588 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2589 2590 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode"); 2591 Ops.push_back(RecordedNodes[RecNo].first); 2592 } 2593 2594 // If there are variadic operands to add, handle them now. 2595 if (EmitNodeInfo & OPFL_VariadicInfo) { 2596 // Determine the start index to copy from. 2597 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo); 2598 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0; 2599 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy && 2600 "Invalid variadic node"); 2601 // Copy all of the variadic operands, not including a potential glue 2602 // input. 2603 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands(); 2604 i != e; ++i) { 2605 SDValue V = NodeToMatch->getOperand(i); 2606 if (V.getValueType() == MVT::Glue) break; 2607 Ops.push_back(V); 2608 } 2609 } 2610 2611 // If this has chain/glue inputs, add them. 2612 if (EmitNodeInfo & OPFL_Chain) 2613 Ops.push_back(InputChain); 2614 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != 0) 2615 Ops.push_back(InputGlue); 2616 2617 // Create the node. 2618 SDNode *Res = 0; 2619 if (Opcode != OPC_MorphNodeTo) { 2620 // If this is a normal EmitNode command, just create the new node and 2621 // add the results to the RecordedNodes list. 2622 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(), 2623 VTList, Ops.data(), Ops.size()); 2624 2625 // Add all the non-glue/non-chain results to the RecordedNodes list. 2626 for (unsigned i = 0, e = VTs.size(); i != e; ++i) { 2627 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break; 2628 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i), 2629 (SDNode*) 0)); 2630 } 2631 2632 } else { 2633 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(), 2634 EmitNodeInfo); 2635 } 2636 2637 // If the node had chain/glue results, update our notion of the current 2638 // chain and glue. 2639 if (EmitNodeInfo & OPFL_GlueOutput) { 2640 InputGlue = SDValue(Res, VTs.size()-1); 2641 if (EmitNodeInfo & OPFL_Chain) 2642 InputChain = SDValue(Res, VTs.size()-2); 2643 } else if (EmitNodeInfo & OPFL_Chain) 2644 InputChain = SDValue(Res, VTs.size()-1); 2645 2646 // If the OPFL_MemRefs glue is set on this node, slap all of the 2647 // accumulated memrefs onto it. 2648 // 2649 // FIXME: This is vastly incorrect for patterns with multiple outputs 2650 // instructions that access memory and for ComplexPatterns that match 2651 // loads. 2652 if (EmitNodeInfo & OPFL_MemRefs) { 2653 MachineSDNode::mmo_iterator MemRefs = 2654 MF->allocateMemRefsArray(MatchedMemRefs.size()); 2655 std::copy(MatchedMemRefs.begin(), MatchedMemRefs.end(), MemRefs); 2656 cast<MachineSDNode>(Res) 2657 ->setMemRefs(MemRefs, MemRefs + MatchedMemRefs.size()); 2658 } 2659 2660 DEBUG(errs() << " " 2661 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created") 2662 << " node: "; Res->dump(CurDAG); errs() << "\n"); 2663 2664 // If this was a MorphNodeTo then we're completely done! 2665 if (Opcode == OPC_MorphNodeTo) { 2666 // Update chain and glue uses. 2667 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched, 2668 InputGlue, GlueResultNodesMatched, true); 2669 return Res; 2670 } 2671 2672 continue; 2673 } 2674 2675 case OPC_MarkGlueResults: { 2676 unsigned NumNodes = MatcherTable[MatcherIndex++]; 2677 2678 // Read and remember all the glue-result nodes. 2679 for (unsigned i = 0; i != NumNodes; ++i) { 2680 unsigned RecNo = MatcherTable[MatcherIndex++]; 2681 if (RecNo & 128) 2682 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2683 2684 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2685 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode()); 2686 } 2687 continue; 2688 } 2689 2690 case OPC_CompleteMatch: { 2691 // The match has been completed, and any new nodes (if any) have been 2692 // created. Patch up references to the matched dag to use the newly 2693 // created nodes. 2694 unsigned NumResults = MatcherTable[MatcherIndex++]; 2695 2696 for (unsigned i = 0; i != NumResults; ++i) { 2697 unsigned ResSlot = MatcherTable[MatcherIndex++]; 2698 if (ResSlot & 128) 2699 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex); 2700 2701 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame"); 2702 SDValue Res = RecordedNodes[ResSlot].first; 2703 2704 assert(i < NodeToMatch->getNumValues() && 2705 NodeToMatch->getValueType(i) != MVT::Other && 2706 NodeToMatch->getValueType(i) != MVT::Glue && 2707 "Invalid number of results to complete!"); 2708 assert((NodeToMatch->getValueType(i) == Res.getValueType() || 2709 NodeToMatch->getValueType(i) == MVT::iPTR || 2710 Res.getValueType() == MVT::iPTR || 2711 NodeToMatch->getValueType(i).getSizeInBits() == 2712 Res.getValueType().getSizeInBits()) && 2713 "invalid replacement"); 2714 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res); 2715 } 2716 2717 // If the root node defines glue, add it to the glue nodes to update list. 2718 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue) 2719 GlueResultNodesMatched.push_back(NodeToMatch); 2720 2721 // Update chain and glue uses. 2722 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched, 2723 InputGlue, GlueResultNodesMatched, false); 2724 2725 assert(NodeToMatch->use_empty() && 2726 "Didn't replace all uses of the node?"); 2727 2728 // FIXME: We just return here, which interacts correctly with SelectRoot 2729 // above. We should fix this to not return an SDNode* anymore. 2730 return 0; 2731 } 2732 } 2733 2734 // If the code reached this point, then the match failed. See if there is 2735 // another child to try in the current 'Scope', otherwise pop it until we 2736 // find a case to check. 2737 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n"); 2738 ++NumDAGIselRetries; 2739 while (1) { 2740 if (MatchScopes.empty()) { 2741 CannotYetSelect(NodeToMatch); 2742 return 0; 2743 } 2744 2745 // Restore the interpreter state back to the point where the scope was 2746 // formed. 2747 MatchScope &LastScope = MatchScopes.back(); 2748 RecordedNodes.resize(LastScope.NumRecordedNodes); 2749 NodeStack.clear(); 2750 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end()); 2751 N = NodeStack.back(); 2752 2753 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size()) 2754 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs); 2755 MatcherIndex = LastScope.FailIndex; 2756 2757 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n"); 2758 2759 InputChain = LastScope.InputChain; 2760 InputGlue = LastScope.InputGlue; 2761 if (!LastScope.HasChainNodesMatched) 2762 ChainNodesMatched.clear(); 2763 if (!LastScope.HasGlueResultNodesMatched) 2764 GlueResultNodesMatched.clear(); 2765 2766 // Check to see what the offset is at the new MatcherIndex. If it is zero 2767 // we have reached the end of this scope, otherwise we have another child 2768 // in the current scope to try. 2769 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2770 if (NumToSkip & 128) 2771 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2772 2773 // If we have another child in this scope to match, update FailIndex and 2774 // try it. 2775 if (NumToSkip != 0) { 2776 LastScope.FailIndex = MatcherIndex+NumToSkip; 2777 break; 2778 } 2779 2780 // End of this scope, pop it and try the next child in the containing 2781 // scope. 2782 MatchScopes.pop_back(); 2783 } 2784 } 2785} 2786 2787 2788 2789void SelectionDAGISel::CannotYetSelect(SDNode *N) { 2790 std::string msg; 2791 raw_string_ostream Msg(msg); 2792 Msg << "Cannot select: "; 2793 2794 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN && 2795 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN && 2796 N->getOpcode() != ISD::INTRINSIC_VOID) { 2797 N->printrFull(Msg, CurDAG); 2798 } else { 2799 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other; 2800 unsigned iid = 2801 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue(); 2802 if (iid < Intrinsic::num_intrinsics) 2803 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid); 2804 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo()) 2805 Msg << "target intrinsic %" << TII->getName(iid); 2806 else 2807 Msg << "unknown intrinsic #" << iid; 2808 } 2809 report_fatal_error(Msg.str()); 2810} 2811 2812char SelectionDAGISel::ID = 0; 2813