SelectionDAGISel.cpp revision d61fc38e3dd74f01134d21747d8003b3ea64d459
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "ScheduleDAGSDNodes.h" 16#include "SelectionDAGBuilder.h" 17#include "llvm/CodeGen/FunctionLoweringInfo.h" 18#include "llvm/CodeGen/SelectionDAGISel.h" 19#include "llvm/Analysis/AliasAnalysis.h" 20#include "llvm/Analysis/DebugInfo.h" 21#include "llvm/Constants.h" 22#include "llvm/Function.h" 23#include "llvm/InlineAsm.h" 24#include "llvm/Instructions.h" 25#include "llvm/Intrinsics.h" 26#include "llvm/IntrinsicInst.h" 27#include "llvm/LLVMContext.h" 28#include "llvm/Module.h" 29#include "llvm/CodeGen/FastISel.h" 30#include "llvm/CodeGen/GCStrategy.h" 31#include "llvm/CodeGen/GCMetadata.h" 32#include "llvm/CodeGen/MachineFrameInfo.h" 33#include "llvm/CodeGen/MachineFunction.h" 34#include "llvm/CodeGen/MachineInstrBuilder.h" 35#include "llvm/CodeGen/MachineModuleInfo.h" 36#include "llvm/CodeGen/MachineRegisterInfo.h" 37#include "llvm/CodeGen/ScheduleHazardRecognizer.h" 38#include "llvm/CodeGen/SchedulerRegistry.h" 39#include "llvm/CodeGen/SelectionDAG.h" 40#include "llvm/Target/TargetRegisterInfo.h" 41#include "llvm/Target/TargetIntrinsicInfo.h" 42#include "llvm/Target/TargetInstrInfo.h" 43#include "llvm/Target/TargetLowering.h" 44#include "llvm/Target/TargetMachine.h" 45#include "llvm/Target/TargetOptions.h" 46#include "llvm/Support/Compiler.h" 47#include "llvm/Support/Debug.h" 48#include "llvm/Support/ErrorHandling.h" 49#include "llvm/Support/Timer.h" 50#include "llvm/Support/raw_ostream.h" 51#include "llvm/ADT/Statistic.h" 52#include <algorithm> 53using namespace llvm; 54 55STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on"); 56STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path"); 57 58static cl::opt<bool> 59EnableFastISelVerbose("fast-isel-verbose", cl::Hidden, 60 cl::desc("Enable verbose messages in the \"fast\" " 61 "instruction selector")); 62static cl::opt<bool> 63EnableFastISelAbort("fast-isel-abort", cl::Hidden, 64 cl::desc("Enable abort calls when \"fast\" instruction fails")); 65 66#ifndef NDEBUG 67static cl::opt<bool> 68ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 69 cl::desc("Pop up a window to show dags before the first " 70 "dag combine pass")); 71static cl::opt<bool> 72ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden, 73 cl::desc("Pop up a window to show dags before legalize types")); 74static cl::opt<bool> 75ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 76 cl::desc("Pop up a window to show dags before legalize")); 77static cl::opt<bool> 78ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 79 cl::desc("Pop up a window to show dags before the second " 80 "dag combine pass")); 81static cl::opt<bool> 82ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden, 83 cl::desc("Pop up a window to show dags before the post legalize types" 84 " dag combine pass")); 85static cl::opt<bool> 86ViewISelDAGs("view-isel-dags", cl::Hidden, 87 cl::desc("Pop up a window to show isel dags as they are selected")); 88static cl::opt<bool> 89ViewSchedDAGs("view-sched-dags", cl::Hidden, 90 cl::desc("Pop up a window to show sched dags as they are processed")); 91static cl::opt<bool> 92ViewSUnitDAGs("view-sunit-dags", cl::Hidden, 93 cl::desc("Pop up a window to show SUnit dags after they are processed")); 94#else 95static const bool ViewDAGCombine1 = false, 96 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false, 97 ViewDAGCombine2 = false, 98 ViewDAGCombineLT = false, 99 ViewISelDAGs = false, ViewSchedDAGs = false, 100 ViewSUnitDAGs = false; 101#endif 102 103//===---------------------------------------------------------------------===// 104/// 105/// RegisterScheduler class - Track the registration of instruction schedulers. 106/// 107//===---------------------------------------------------------------------===// 108MachinePassRegistry RegisterScheduler::Registry; 109 110//===---------------------------------------------------------------------===// 111/// 112/// ISHeuristic command line option for instruction schedulers. 113/// 114//===---------------------------------------------------------------------===// 115static cl::opt<RegisterScheduler::FunctionPassCtor, false, 116 RegisterPassParser<RegisterScheduler> > 117ISHeuristic("pre-RA-sched", 118 cl::init(&createDefaultScheduler), 119 cl::desc("Instruction schedulers available (before register" 120 " allocation):")); 121 122static RegisterScheduler 123defaultListDAGScheduler("default", "Best scheduler for the target", 124 createDefaultScheduler); 125 126namespace llvm { 127 //===--------------------------------------------------------------------===// 128 /// createDefaultScheduler - This creates an instruction scheduler appropriate 129 /// for the target. 130 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS, 131 CodeGenOpt::Level OptLevel) { 132 const TargetLowering &TLI = IS->getTargetLowering(); 133 134 if (OptLevel == CodeGenOpt::None) 135 return createSourceListDAGScheduler(IS, OptLevel); 136 if (TLI.getSchedulingPreference() == Sched::Latency) 137 return createTDListDAGScheduler(IS, OptLevel); 138 if (TLI.getSchedulingPreference() == Sched::RegPressure) 139 return createBURRListDAGScheduler(IS, OptLevel); 140 if (TLI.getSchedulingPreference() == Sched::Hybrid) 141 return createHybridListDAGScheduler(IS, OptLevel); 142 assert(TLI.getSchedulingPreference() == Sched::ILP && 143 "Unknown sched type!"); 144 return createILPListDAGScheduler(IS, OptLevel); 145 } 146} 147 148// EmitInstrWithCustomInserter - This method should be implemented by targets 149// that mark instructions with the 'usesCustomInserter' flag. These 150// instructions are special in various ways, which require special support to 151// insert. The specified MachineInstr is created but not inserted into any 152// basic blocks, and this method is called to expand it into a sequence of 153// instructions, potentially also creating new basic blocks and control flow. 154// When new basic blocks are inserted and the edges from MBB to its successors 155// are modified, the method should insert pairs of <OldSucc, NewSucc> into the 156// DenseMap. 157MachineBasicBlock * 158TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 159 MachineBasicBlock *MBB) const { 160#ifndef NDEBUG 161 dbgs() << "If a target marks an instruction with " 162 "'usesCustomInserter', it must implement " 163 "TargetLowering::EmitInstrWithCustomInserter!"; 164#endif 165 llvm_unreachable(0); 166 return 0; 167} 168 169//===----------------------------------------------------------------------===// 170// SelectionDAGISel code 171//===----------------------------------------------------------------------===// 172 173SelectionDAGISel::SelectionDAGISel(const TargetMachine &tm, CodeGenOpt::Level OL) : 174 MachineFunctionPass(ID), TM(tm), TLI(*tm.getTargetLowering()), 175 FuncInfo(new FunctionLoweringInfo(TLI)), 176 CurDAG(new SelectionDAG(tm)), 177 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)), 178 GFI(), 179 OptLevel(OL), 180 DAGSize(0) 181{} 182 183SelectionDAGISel::~SelectionDAGISel() { 184 delete SDB; 185 delete CurDAG; 186 delete FuncInfo; 187} 188 189void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 190 AU.addRequired<AliasAnalysis>(); 191 AU.addPreserved<AliasAnalysis>(); 192 AU.addRequired<GCModuleInfo>(); 193 AU.addPreserved<GCModuleInfo>(); 194 MachineFunctionPass::getAnalysisUsage(AU); 195} 196 197/// FunctionCallsSetJmp - Return true if the function has a call to setjmp or 198/// other function that gcc recognizes as "returning twice". This is used to 199/// limit code-gen optimizations on the machine function. 200/// 201/// FIXME: Remove after <rdar://problem/8031714> is fixed. 202static bool FunctionCallsSetJmp(const Function *F) { 203 const Module *M = F->getParent(); 204 static const char *ReturnsTwiceFns[] = { 205 "setjmp", 206 "sigsetjmp", 207 "setjmp_syscall", 208 "savectx", 209 "qsetjmp", 210 "vfork", 211 "getcontext" 212 }; 213#define NUM_RETURNS_TWICE_FNS sizeof(ReturnsTwiceFns) / sizeof(const char *) 214 215 for (unsigned I = 0; I < NUM_RETURNS_TWICE_FNS; ++I) 216 if (const Function *Callee = M->getFunction(ReturnsTwiceFns[I])) { 217 if (!Callee->use_empty()) 218 for (Value::const_use_iterator 219 I = Callee->use_begin(), E = Callee->use_end(); 220 I != E; ++I) 221 if (const CallInst *CI = dyn_cast<CallInst>(*I)) 222 if (CI->getParent()->getParent() == F) 223 return true; 224 } 225 226 return false; 227#undef NUM_RETURNS_TWICE_FNS 228} 229 230bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) { 231 // Do some sanity-checking on the command-line options. 232 assert((!EnableFastISelVerbose || EnableFastISel) && 233 "-fast-isel-verbose requires -fast-isel"); 234 assert((!EnableFastISelAbort || EnableFastISel) && 235 "-fast-isel-abort requires -fast-isel"); 236 237 const Function &Fn = *mf.getFunction(); 238 const TargetInstrInfo &TII = *TM.getInstrInfo(); 239 const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); 240 241 MF = &mf; 242 RegInfo = &MF->getRegInfo(); 243 AA = &getAnalysis<AliasAnalysis>(); 244 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0; 245 246 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n"); 247 248 CurDAG->init(*MF); 249 FuncInfo->set(Fn, *MF); 250 SDB->init(GFI, *AA); 251 252 SelectAllBasicBlocks(Fn); 253 254 // If the first basic block in the function has live ins that need to be 255 // copied into vregs, emit the copies into the top of the block before 256 // emitting the code for the block. 257 MachineBasicBlock *EntryMBB = MF->begin(); 258 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII); 259 260 DenseMap<unsigned, unsigned> LiveInMap; 261 if (!FuncInfo->ArgDbgValues.empty()) 262 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(), 263 E = RegInfo->livein_end(); LI != E; ++LI) 264 if (LI->second) 265 LiveInMap.insert(std::make_pair(LI->first, LI->second)); 266 267 // Insert DBG_VALUE instructions for function arguments to the entry block. 268 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) { 269 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1]; 270 unsigned Reg = MI->getOperand(0).getReg(); 271 if (TargetRegisterInfo::isPhysicalRegister(Reg)) 272 EntryMBB->insert(EntryMBB->begin(), MI); 273 else { 274 MachineInstr *Def = RegInfo->getVRegDef(Reg); 275 MachineBasicBlock::iterator InsertPos = Def; 276 // FIXME: VR def may not be in entry block. 277 Def->getParent()->insert(llvm::next(InsertPos), MI); 278 } 279 280 // If Reg is live-in then update debug info to track its copy in a vreg. 281 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg); 282 if (LDI != LiveInMap.end()) { 283 MachineInstr *Def = RegInfo->getVRegDef(LDI->second); 284 MachineBasicBlock::iterator InsertPos = Def; 285 const MDNode *Variable = 286 MI->getOperand(MI->getNumOperands()-1).getMetadata(); 287 unsigned Offset = MI->getOperand(1).getImm(); 288 // Def is never a terminator here, so it is ok to increment InsertPos. 289 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(), 290 TII.get(TargetOpcode::DBG_VALUE)) 291 .addReg(LDI->second, RegState::Debug) 292 .addImm(Offset).addMetadata(Variable); 293 294 // If this vreg is directly copied into an exported register then 295 // that COPY instructions also need DBG_VALUE, if it is the only 296 // user of LDI->second. 297 MachineInstr *CopyUseMI = NULL; 298 for (MachineRegisterInfo::use_iterator 299 UI = RegInfo->use_begin(LDI->second); 300 MachineInstr *UseMI = UI.skipInstruction();) { 301 if (UseMI->isDebugValue()) continue; 302 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) { 303 CopyUseMI = UseMI; continue; 304 } 305 // Otherwise this is another use or second copy use. 306 CopyUseMI = NULL; break; 307 } 308 if (CopyUseMI) { 309 MachineInstr *NewMI = 310 BuildMI(*MF, CopyUseMI->getDebugLoc(), 311 TII.get(TargetOpcode::DBG_VALUE)) 312 .addReg(CopyUseMI->getOperand(0).getReg(), RegState::Debug) 313 .addImm(Offset).addMetadata(Variable); 314 EntryMBB->insertAfter(CopyUseMI, NewMI); 315 } 316 } 317 } 318 319 // Determine if there are any calls in this machine function. 320 MachineFrameInfo *MFI = MF->getFrameInfo(); 321 if (!MFI->hasCalls()) { 322 for (MachineFunction::const_iterator 323 I = MF->begin(), E = MF->end(); I != E; ++I) { 324 const MachineBasicBlock *MBB = I; 325 for (MachineBasicBlock::const_iterator 326 II = MBB->begin(), IE = MBB->end(); II != IE; ++II) { 327 const TargetInstrDesc &TID = TM.getInstrInfo()->get(II->getOpcode()); 328 329 // Operand 1 of an inline asm instruction indicates whether the asm 330 // needs stack or not. 331 if ((II->isInlineAsm() && II->getOperand(1).getImm()) || 332 (TID.isCall() && !TID.isReturn())) { 333 MFI->setHasCalls(true); 334 goto done; 335 } 336 } 337 } 338 done:; 339 } 340 341 // Determine if there is a call to setjmp in the machine function. 342 MF->setCallsSetJmp(FunctionCallsSetJmp(&Fn)); 343 344 // Replace forward-declared registers with the registers containing 345 // the desired value. 346 MachineRegisterInfo &MRI = MF->getRegInfo(); 347 for (DenseMap<unsigned, unsigned>::iterator 348 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end(); 349 I != E; ++I) { 350 unsigned From = I->first; 351 unsigned To = I->second; 352 // If To is also scheduled to be replaced, find what its ultimate 353 // replacement is. 354 for (;;) { 355 DenseMap<unsigned, unsigned>::iterator J = 356 FuncInfo->RegFixups.find(To); 357 if (J == E) break; 358 To = J->second; 359 } 360 // Replace it. 361 MRI.replaceRegWith(From, To); 362 } 363 364 // Release function-specific state. SDB and CurDAG are already cleared 365 // at this point. 366 FuncInfo->clear(); 367 368 return true; 369} 370 371void 372SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin, 373 BasicBlock::const_iterator End, 374 bool &HadTailCall) { 375 // Lower all of the non-terminator instructions. If a call is emitted 376 // as a tail call, cease emitting nodes for this block. Terminators 377 // are handled below. 378 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I) 379 SDB->visit(*I); 380 381 // Make sure the root of the DAG is up-to-date. 382 CurDAG->setRoot(SDB->getControlRoot()); 383 HadTailCall = SDB->HasTailCall; 384 SDB->clear(); 385 386 // Final step, emit the lowered DAG as machine code. 387 CodeGenAndEmitDAG(); 388} 389 390void SelectionDAGISel::ComputeLiveOutVRegInfo() { 391 SmallPtrSet<SDNode*, 128> VisitedNodes; 392 SmallVector<SDNode*, 128> Worklist; 393 394 Worklist.push_back(CurDAG->getRoot().getNode()); 395 396 APInt Mask; 397 APInt KnownZero; 398 APInt KnownOne; 399 400 do { 401 SDNode *N = Worklist.pop_back_val(); 402 403 // If we've already seen this node, ignore it. 404 if (!VisitedNodes.insert(N)) 405 continue; 406 407 // Otherwise, add all chain operands to the worklist. 408 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 409 if (N->getOperand(i).getValueType() == MVT::Other) 410 Worklist.push_back(N->getOperand(i).getNode()); 411 412 // If this is a CopyToReg with a vreg dest, process it. 413 if (N->getOpcode() != ISD::CopyToReg) 414 continue; 415 416 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg(); 417 if (!TargetRegisterInfo::isVirtualRegister(DestReg)) 418 continue; 419 420 // Ignore non-scalar or non-integer values. 421 SDValue Src = N->getOperand(2); 422 EVT SrcVT = Src.getValueType(); 423 if (!SrcVT.isInteger() || SrcVT.isVector()) 424 continue; 425 426 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src); 427 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits()); 428 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne); 429 430 // Only install this information if it tells us something. 431 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) { 432 DestReg -= TargetRegisterInfo::FirstVirtualRegister; 433 if (DestReg >= FuncInfo->LiveOutRegInfo.size()) 434 FuncInfo->LiveOutRegInfo.resize(DestReg+1); 435 FunctionLoweringInfo::LiveOutInfo &LOI = 436 FuncInfo->LiveOutRegInfo[DestReg]; 437 LOI.NumSignBits = NumSignBits; 438 LOI.KnownOne = KnownOne; 439 LOI.KnownZero = KnownZero; 440 } 441 } while (!Worklist.empty()); 442} 443 444void SelectionDAGISel::CodeGenAndEmitDAG() { 445 std::string GroupName; 446 if (TimePassesIsEnabled) 447 GroupName = "Instruction Selection and Scheduling"; 448 std::string BlockName; 449 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs || 450 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs || 451 ViewSUnitDAGs) 452 BlockName = MF->getFunction()->getNameStr() + ":" + 453 FuncInfo->MBB->getBasicBlock()->getNameStr(); 454 455 DEBUG(dbgs() << "Initial selection DAG:\n"; CurDAG->dump()); 456 457 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName); 458 459 // Run the DAG combiner in pre-legalize mode. 460 { 461 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled); 462 CurDAG->Combine(Unrestricted, *AA, OptLevel); 463 } 464 465 DEBUG(dbgs() << "Optimized lowered selection DAG:\n"; CurDAG->dump()); 466 467 // Second step, hack on the DAG until it only uses operations and types that 468 // the target supports. 469 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " + 470 BlockName); 471 472 bool Changed; 473 { 474 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled); 475 Changed = CurDAG->LegalizeTypes(); 476 } 477 478 DEBUG(dbgs() << "Type-legalized selection DAG:\n"; CurDAG->dump()); 479 480 if (Changed) { 481 if (ViewDAGCombineLT) 482 CurDAG->viewGraph("dag-combine-lt input for " + BlockName); 483 484 // Run the DAG combiner in post-type-legalize mode. 485 { 486 NamedRegionTimer T("DAG Combining after legalize types", GroupName, 487 TimePassesIsEnabled); 488 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel); 489 } 490 491 DEBUG(dbgs() << "Optimized type-legalized selection DAG:\n"; 492 CurDAG->dump()); 493 } 494 495 { 496 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled); 497 Changed = CurDAG->LegalizeVectors(); 498 } 499 500 if (Changed) { 501 { 502 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled); 503 CurDAG->LegalizeTypes(); 504 } 505 506 if (ViewDAGCombineLT) 507 CurDAG->viewGraph("dag-combine-lv input for " + BlockName); 508 509 // Run the DAG combiner in post-type-legalize mode. 510 { 511 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName, 512 TimePassesIsEnabled); 513 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 514 } 515 516 DEBUG(dbgs() << "Optimized vector-legalized selection DAG:\n"; 517 CurDAG->dump()); 518 } 519 520 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName); 521 522 { 523 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled); 524 CurDAG->Legalize(OptLevel); 525 } 526 527 DEBUG(dbgs() << "Legalized selection DAG:\n"; CurDAG->dump()); 528 529 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName); 530 531 // Run the DAG combiner in post-legalize mode. 532 { 533 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled); 534 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 535 } 536 537 DEBUG(dbgs() << "Optimized legalized selection DAG:\n"; CurDAG->dump()); 538 539 if (OptLevel != CodeGenOpt::None) 540 ComputeLiveOutVRegInfo(); 541 542 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName); 543 544 // Third, instruction select all of the operations to machine code, adding the 545 // code to the MachineBasicBlock. 546 { 547 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled); 548 DoInstructionSelection(); 549 } 550 551 DEBUG(dbgs() << "Selected selection DAG:\n"; CurDAG->dump()); 552 553 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName); 554 555 // Schedule machine code. 556 ScheduleDAGSDNodes *Scheduler = CreateScheduler(); 557 { 558 NamedRegionTimer T("Instruction Scheduling", GroupName, 559 TimePassesIsEnabled); 560 Scheduler->Run(CurDAG, FuncInfo->MBB, FuncInfo->InsertPt); 561 } 562 563 if (ViewSUnitDAGs) Scheduler->viewGraph(); 564 565 // Emit machine code to BB. This can change 'BB' to the last block being 566 // inserted into. 567 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB; 568 { 569 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled); 570 571 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule(); 572 FuncInfo->InsertPt = Scheduler->InsertPos; 573 } 574 575 // If the block was split, make sure we update any references that are used to 576 // update PHI nodes later on. 577 if (FirstMBB != LastMBB) 578 SDB->UpdateSplitBlock(FirstMBB, LastMBB); 579 580 // Free the scheduler state. 581 { 582 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName, 583 TimePassesIsEnabled); 584 delete Scheduler; 585 } 586 587 // Free the SelectionDAG state, now that we're finished with it. 588 CurDAG->clear(); 589} 590 591void SelectionDAGISel::DoInstructionSelection() { 592 DEBUG(errs() << "===== Instruction selection begins:\n"); 593 594 PreprocessISelDAG(); 595 596 // Select target instructions for the DAG. 597 { 598 // Number all nodes with a topological order and set DAGSize. 599 DAGSize = CurDAG->AssignTopologicalOrder(); 600 601 // Create a dummy node (which is not added to allnodes), that adds 602 // a reference to the root node, preventing it from being deleted, 603 // and tracking any changes of the root. 604 HandleSDNode Dummy(CurDAG->getRoot()); 605 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode()); 606 ++ISelPosition; 607 608 // The AllNodes list is now topological-sorted. Visit the 609 // nodes by starting at the end of the list (the root of the 610 // graph) and preceding back toward the beginning (the entry 611 // node). 612 while (ISelPosition != CurDAG->allnodes_begin()) { 613 SDNode *Node = --ISelPosition; 614 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes, 615 // but there are currently some corner cases that it misses. Also, this 616 // makes it theoretically possible to disable the DAGCombiner. 617 if (Node->use_empty()) 618 continue; 619 620 SDNode *ResNode = Select(Node); 621 622 // FIXME: This is pretty gross. 'Select' should be changed to not return 623 // anything at all and this code should be nuked with a tactical strike. 624 625 // If node should not be replaced, continue with the next one. 626 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE) 627 continue; 628 // Replace node. 629 if (ResNode) 630 ReplaceUses(Node, ResNode); 631 632 // If after the replacement this node is not used any more, 633 // remove this dead node. 634 if (Node->use_empty()) { // Don't delete EntryToken, etc. 635 ISelUpdater ISU(ISelPosition); 636 CurDAG->RemoveDeadNode(Node, &ISU); 637 } 638 } 639 640 CurDAG->setRoot(Dummy.getValue()); 641 } 642 643 DEBUG(errs() << "===== Instruction selection ends:\n"); 644 645 PostprocessISelDAG(); 646} 647 648/// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and 649/// do other setup for EH landing-pad blocks. 650void SelectionDAGISel::PrepareEHLandingPad() { 651 // Add a label to mark the beginning of the landing pad. Deletion of the 652 // landing pad can thus be detected via the MachineModuleInfo. 653 MCSymbol *Label = MF->getMMI().addLandingPad(FuncInfo->MBB); 654 655 const TargetInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL); 656 BuildMI(*FuncInfo->MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II) 657 .addSym(Label); 658 659 // Mark exception register as live in. 660 unsigned Reg = TLI.getExceptionAddressRegister(); 661 if (Reg) FuncInfo->MBB->addLiveIn(Reg); 662 663 // Mark exception selector register as live in. 664 Reg = TLI.getExceptionSelectorRegister(); 665 if (Reg) FuncInfo->MBB->addLiveIn(Reg); 666 667 // FIXME: Hack around an exception handling flaw (PR1508): the personality 668 // function and list of typeids logically belong to the invoke (or, if you 669 // like, the basic block containing the invoke), and need to be associated 670 // with it in the dwarf exception handling tables. Currently however the 671 // information is provided by an intrinsic (eh.selector) that can be moved 672 // to unexpected places by the optimizers: if the unwind edge is critical, 673 // then breaking it can result in the intrinsics being in the successor of 674 // the landing pad, not the landing pad itself. This results 675 // in exceptions not being caught because no typeids are associated with 676 // the invoke. This may not be the only way things can go wrong, but it 677 // is the only way we try to work around for the moment. 678 const BasicBlock *LLVMBB = FuncInfo->MBB->getBasicBlock(); 679 const BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator()); 680 681 if (Br && Br->isUnconditional()) { // Critical edge? 682 BasicBlock::const_iterator I, E; 683 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I) 684 if (isa<EHSelectorInst>(I)) 685 break; 686 687 if (I == E) 688 // No catch info found - try to extract some from the successor. 689 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, &MF->getMMI(), *FuncInfo); 690 } 691} 692 693 694 695 696bool SelectionDAGISel::TryToFoldFastISelLoad(const LoadInst *LI, 697 FastISel *FastIS) { 698 // Don't try to fold volatile loads. Target has to deal with alignment 699 // constraints. 700 if (LI->isVolatile()) return false; 701 702 // Figure out which vreg this is going into. 703 unsigned LoadReg = FastIS->getRegForValue(LI); 704 assert(LoadReg && "Load isn't already assigned a vreg? "); 705 706 // Check to see what the uses of this vreg are. If it has no uses, or more 707 // than one use (at the machine instr level) then we can't fold it. 708 MachineRegisterInfo::reg_iterator RI = RegInfo->reg_begin(LoadReg); 709 if (RI == RegInfo->reg_end()) 710 return false; 711 712 // See if there is exactly one use of the vreg. If there are multiple uses, 713 // then the instruction got lowered to multiple machine instructions or the 714 // use of the loaded value ended up being multiple operands of the result, in 715 // either case, we can't fold this. 716 MachineRegisterInfo::reg_iterator PostRI = RI; ++PostRI; 717 if (PostRI != RegInfo->reg_end()) 718 return false; 719 720 assert(RI.getOperand().isUse() && 721 "The only use of the vreg must be a use, we haven't emitted the def!"); 722 723 // Ask the target to try folding the load. 724 return FastIS->TryToFoldLoad(&*RI, RI.getOperandNo(), LI); 725} 726 727 728 729 730void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) { 731 // Initialize the Fast-ISel state, if needed. 732 FastISel *FastIS = 0; 733 if (EnableFastISel) 734 FastIS = TLI.createFastISel(*FuncInfo); 735 736 // Iterate over all basic blocks in the function. 737 for (Function::const_iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) { 738 const BasicBlock *LLVMBB = &*I; 739 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB]; 740 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI(); 741 742 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI(); 743 BasicBlock::const_iterator const End = LLVMBB->end(); 744 BasicBlock::const_iterator BI = End; 745 746 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI(); 747 748 // Setup an EH landing-pad block. 749 if (FuncInfo->MBB->isLandingPad()) 750 PrepareEHLandingPad(); 751 752 // Lower any arguments needed in this block if this is the entry block. 753 if (LLVMBB == &Fn.getEntryBlock()) 754 LowerArguments(LLVMBB); 755 756 // Before doing SelectionDAG ISel, see if FastISel has been requested. 757 if (FastIS) { 758 FastIS->startNewBlock(); 759 760 // Emit code for any incoming arguments. This must happen before 761 // beginning FastISel on the entry block. 762 if (LLVMBB == &Fn.getEntryBlock()) { 763 CurDAG->setRoot(SDB->getControlRoot()); 764 SDB->clear(); 765 CodeGenAndEmitDAG(); 766 767 // If we inserted any instructions at the beginning, make a note of 768 // where they are, so we can be sure to emit subsequent instructions 769 // after them. 770 if (FuncInfo->InsertPt != FuncInfo->MBB->begin()) 771 FastIS->setLastLocalValue(llvm::prior(FuncInfo->InsertPt)); 772 else 773 FastIS->setLastLocalValue(0); 774 } 775 776 // Do FastISel on as many instructions as possible. 777 for (; BI != Begin; --BI) { 778 const Instruction *Inst = llvm::prior(BI); 779 780 // If we no longer require this instruction, skip it. 781 if (!Inst->mayWriteToMemory() && 782 !isa<TerminatorInst>(Inst) && 783 !isa<DbgInfoIntrinsic>(Inst) && 784 !FuncInfo->isExportedInst(Inst)) 785 continue; 786 787 // Bottom-up: reset the insert pos at the top, after any local-value 788 // instructions. 789 FastIS->recomputeInsertPt(); 790 791 // Try to select the instruction with FastISel. 792 if (FastIS->SelectInstruction(Inst)) { 793 // If fast isel succeeded, check to see if there is a single-use 794 // non-volatile load right before the selected instruction, and see if 795 // the load is used by the instruction. If so, try to fold it. 796 const Instruction *BeforeInst = 0; 797 if (Inst != Begin) 798 BeforeInst = llvm::prior(llvm::prior(BI)); 799 if (BeforeInst && isa<LoadInst>(BeforeInst) && 800 BeforeInst->hasOneUse() && *BeforeInst->use_begin() == Inst && 801 TryToFoldFastISelLoad(cast<LoadInst>(BeforeInst), FastIS)) { 802 // If we succeeded, don't re-select the load. 803 --BI; 804 } 805 continue; 806 } 807 808 // Then handle certain instructions as single-LLVM-Instruction blocks. 809 if (isa<CallInst>(Inst)) { 810 ++NumFastIselFailures; 811 if (EnableFastISelVerbose || EnableFastISelAbort) { 812 dbgs() << "FastISel missed call: "; 813 Inst->dump(); 814 } 815 816 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) { 817 unsigned &R = FuncInfo->ValueMap[Inst]; 818 if (!R) 819 R = FuncInfo->CreateRegs(Inst->getType()); 820 } 821 822 bool HadTailCall = false; 823 SelectBasicBlock(Inst, BI, HadTailCall); 824 825 // If the call was emitted as a tail call, we're done with the block. 826 if (HadTailCall) { 827 --BI; 828 break; 829 } 830 831 continue; 832 } 833 834 // Otherwise, give up on FastISel for the rest of the block. 835 // For now, be a little lenient about non-branch terminators. 836 if (!isa<TerminatorInst>(Inst) || isa<BranchInst>(Inst)) { 837 ++NumFastIselFailures; 838 if (EnableFastISelVerbose || EnableFastISelAbort) { 839 dbgs() << "FastISel miss: "; 840 Inst->dump(); 841 } 842 if (EnableFastISelAbort) 843 // The "fast" selector couldn't handle something and bailed. 844 // For the purpose of debugging, just abort. 845 llvm_unreachable("FastISel didn't select the entire block"); 846 } 847 break; 848 } 849 850 FastIS->recomputeInsertPt(); 851 } 852 853 // Run SelectionDAG instruction selection on the remainder of the block 854 // not handled by FastISel. If FastISel is not run, this is the entire 855 // block. 856 bool HadTailCall; 857 SelectBasicBlock(Begin, BI, HadTailCall); 858 859 FinishBasicBlock(); 860 FuncInfo->PHINodesToUpdate.clear(); 861 } 862 863 delete FastIS; 864} 865 866void 867SelectionDAGISel::FinishBasicBlock() { 868 869 DEBUG(dbgs() << "Total amount of phi nodes to update: " 870 << FuncInfo->PHINodesToUpdate.size() << "\n"; 871 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) 872 dbgs() << "Node " << i << " : (" 873 << FuncInfo->PHINodesToUpdate[i].first 874 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n"); 875 876 // Next, now that we know what the last MBB the LLVM BB expanded is, update 877 // PHI nodes in successors. 878 if (SDB->SwitchCases.empty() && 879 SDB->JTCases.empty() && 880 SDB->BitTestCases.empty()) { 881 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) { 882 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first; 883 assert(PHI->isPHI() && 884 "This is not a machine PHI node that we are updating!"); 885 if (!FuncInfo->MBB->isSuccessor(PHI->getParent())) 886 continue; 887 PHI->addOperand( 888 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false)); 889 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB)); 890 } 891 return; 892 } 893 894 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) { 895 // Lower header first, if it wasn't already lowered 896 if (!SDB->BitTestCases[i].Emitted) { 897 // Set the current basic block to the mbb we wish to insert the code into 898 FuncInfo->MBB = SDB->BitTestCases[i].Parent; 899 FuncInfo->InsertPt = FuncInfo->MBB->end(); 900 // Emit the code 901 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB); 902 CurDAG->setRoot(SDB->getRoot()); 903 SDB->clear(); 904 CodeGenAndEmitDAG(); 905 } 906 907 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) { 908 // Set the current basic block to the mbb we wish to insert the code into 909 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB; 910 FuncInfo->InsertPt = FuncInfo->MBB->end(); 911 // Emit the code 912 if (j+1 != ej) 913 SDB->visitBitTestCase(SDB->BitTestCases[i].Cases[j+1].ThisBB, 914 SDB->BitTestCases[i].Reg, 915 SDB->BitTestCases[i].Cases[j], 916 FuncInfo->MBB); 917 else 918 SDB->visitBitTestCase(SDB->BitTestCases[i].Default, 919 SDB->BitTestCases[i].Reg, 920 SDB->BitTestCases[i].Cases[j], 921 FuncInfo->MBB); 922 923 924 CurDAG->setRoot(SDB->getRoot()); 925 SDB->clear(); 926 CodeGenAndEmitDAG(); 927 } 928 929 // Update PHI Nodes 930 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size(); 931 pi != pe; ++pi) { 932 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first; 933 MachineBasicBlock *PHIBB = PHI->getParent(); 934 assert(PHI->isPHI() && 935 "This is not a machine PHI node that we are updating!"); 936 // This is "default" BB. We have two jumps to it. From "header" BB and 937 // from last "case" BB. 938 if (PHIBB == SDB->BitTestCases[i].Default) { 939 PHI->addOperand(MachineOperand:: 940 CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 941 false)); 942 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent)); 943 PHI->addOperand(MachineOperand:: 944 CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 945 false)); 946 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases. 947 back().ThisBB)); 948 } 949 // One of "cases" BB. 950 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); 951 j != ej; ++j) { 952 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB; 953 if (cBB->isSuccessor(PHIBB)) { 954 PHI->addOperand(MachineOperand:: 955 CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 956 false)); 957 PHI->addOperand(MachineOperand::CreateMBB(cBB)); 958 } 959 } 960 } 961 } 962 SDB->BitTestCases.clear(); 963 964 // If the JumpTable record is filled in, then we need to emit a jump table. 965 // Updating the PHI nodes is tricky in this case, since we need to determine 966 // whether the PHI is a successor of the range check MBB or the jump table MBB 967 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) { 968 // Lower header first, if it wasn't already lowered 969 if (!SDB->JTCases[i].first.Emitted) { 970 // Set the current basic block to the mbb we wish to insert the code into 971 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB; 972 FuncInfo->InsertPt = FuncInfo->MBB->end(); 973 // Emit the code 974 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first, 975 FuncInfo->MBB); 976 CurDAG->setRoot(SDB->getRoot()); 977 SDB->clear(); 978 CodeGenAndEmitDAG(); 979 } 980 981 // Set the current basic block to the mbb we wish to insert the code into 982 FuncInfo->MBB = SDB->JTCases[i].second.MBB; 983 FuncInfo->InsertPt = FuncInfo->MBB->end(); 984 // Emit the code 985 SDB->visitJumpTable(SDB->JTCases[i].second); 986 CurDAG->setRoot(SDB->getRoot()); 987 SDB->clear(); 988 CodeGenAndEmitDAG(); 989 990 // Update PHI Nodes 991 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size(); 992 pi != pe; ++pi) { 993 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first; 994 MachineBasicBlock *PHIBB = PHI->getParent(); 995 assert(PHI->isPHI() && 996 "This is not a machine PHI node that we are updating!"); 997 // "default" BB. We can go there only from header BB. 998 if (PHIBB == SDB->JTCases[i].second.Default) { 999 PHI->addOperand 1000 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 1001 false)); 1002 PHI->addOperand 1003 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB)); 1004 } 1005 // JT BB. Just iterate over successors here 1006 if (FuncInfo->MBB->isSuccessor(PHIBB)) { 1007 PHI->addOperand 1008 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 1009 false)); 1010 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB)); 1011 } 1012 } 1013 } 1014 SDB->JTCases.clear(); 1015 1016 // If the switch block involved a branch to one of the actual successors, we 1017 // need to update PHI nodes in that block. 1018 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) { 1019 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first; 1020 assert(PHI->isPHI() && 1021 "This is not a machine PHI node that we are updating!"); 1022 if (FuncInfo->MBB->isSuccessor(PHI->getParent())) { 1023 PHI->addOperand( 1024 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false)); 1025 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB)); 1026 } 1027 } 1028 1029 // If we generated any switch lowering information, build and codegen any 1030 // additional DAGs necessary. 1031 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) { 1032 // Set the current basic block to the mbb we wish to insert the code into 1033 MachineBasicBlock *ThisBB = FuncInfo->MBB = SDB->SwitchCases[i].ThisBB; 1034 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1035 1036 // Determine the unique successors. 1037 SmallVector<MachineBasicBlock *, 2> Succs; 1038 Succs.push_back(SDB->SwitchCases[i].TrueBB); 1039 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB) 1040 Succs.push_back(SDB->SwitchCases[i].FalseBB); 1041 1042 // Emit the code. Note that this could result in ThisBB being split, so 1043 // we need to check for updates. 1044 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB); 1045 CurDAG->setRoot(SDB->getRoot()); 1046 SDB->clear(); 1047 CodeGenAndEmitDAG(); 1048 ThisBB = FuncInfo->MBB; 1049 1050 // Handle any PHI nodes in successors of this chunk, as if we were coming 1051 // from the original BB before switch expansion. Note that PHI nodes can 1052 // occur multiple times in PHINodesToUpdate. We have to be very careful to 1053 // handle them the right number of times. 1054 for (unsigned i = 0, e = Succs.size(); i != e; ++i) { 1055 FuncInfo->MBB = Succs[i]; 1056 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1057 // FuncInfo->MBB may have been removed from the CFG if a branch was 1058 // constant folded. 1059 if (ThisBB->isSuccessor(FuncInfo->MBB)) { 1060 for (MachineBasicBlock::iterator Phi = FuncInfo->MBB->begin(); 1061 Phi != FuncInfo->MBB->end() && Phi->isPHI(); 1062 ++Phi) { 1063 // This value for this PHI node is recorded in PHINodesToUpdate. 1064 for (unsigned pn = 0; ; ++pn) { 1065 assert(pn != FuncInfo->PHINodesToUpdate.size() && 1066 "Didn't find PHI entry!"); 1067 if (FuncInfo->PHINodesToUpdate[pn].first == Phi) { 1068 Phi->addOperand(MachineOperand:: 1069 CreateReg(FuncInfo->PHINodesToUpdate[pn].second, 1070 false)); 1071 Phi->addOperand(MachineOperand::CreateMBB(ThisBB)); 1072 break; 1073 } 1074 } 1075 } 1076 } 1077 } 1078 } 1079 SDB->SwitchCases.clear(); 1080} 1081 1082 1083/// Create the scheduler. If a specific scheduler was specified 1084/// via the SchedulerRegistry, use it, otherwise select the 1085/// one preferred by the target. 1086/// 1087ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() { 1088 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 1089 1090 if (!Ctor) { 1091 Ctor = ISHeuristic; 1092 RegisterScheduler::setDefault(Ctor); 1093 } 1094 1095 return Ctor(this, OptLevel); 1096} 1097 1098ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() { 1099 return new ScheduleHazardRecognizer(); 1100} 1101 1102//===----------------------------------------------------------------------===// 1103// Helper functions used by the generated instruction selector. 1104//===----------------------------------------------------------------------===// 1105// Calls to these methods are generated by tblgen. 1106 1107/// CheckAndMask - The isel is trying to match something like (and X, 255). If 1108/// the dag combiner simplified the 255, we still want to match. RHS is the 1109/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 1110/// specified in the .td file (e.g. 255). 1111bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS, 1112 int64_t DesiredMaskS) const { 1113 const APInt &ActualMask = RHS->getAPIntValue(); 1114 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1115 1116 // If the actual mask exactly matches, success! 1117 if (ActualMask == DesiredMask) 1118 return true; 1119 1120 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1121 if (ActualMask.intersects(~DesiredMask)) 1122 return false; 1123 1124 // Otherwise, the DAG Combiner may have proven that the value coming in is 1125 // either already zero or is not demanded. Check for known zero input bits. 1126 APInt NeededMask = DesiredMask & ~ActualMask; 1127 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) 1128 return true; 1129 1130 // TODO: check to see if missing bits are just not demanded. 1131 1132 // Otherwise, this pattern doesn't match. 1133 return false; 1134} 1135 1136/// CheckOrMask - The isel is trying to match something like (or X, 255). If 1137/// the dag combiner simplified the 255, we still want to match. RHS is the 1138/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 1139/// specified in the .td file (e.g. 255). 1140bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS, 1141 int64_t DesiredMaskS) const { 1142 const APInt &ActualMask = RHS->getAPIntValue(); 1143 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1144 1145 // If the actual mask exactly matches, success! 1146 if (ActualMask == DesiredMask) 1147 return true; 1148 1149 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1150 if (ActualMask.intersects(~DesiredMask)) 1151 return false; 1152 1153 // Otherwise, the DAG Combiner may have proven that the value coming in is 1154 // either already zero or is not demanded. Check for known zero input bits. 1155 APInt NeededMask = DesiredMask & ~ActualMask; 1156 1157 APInt KnownZero, KnownOne; 1158 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne); 1159 1160 // If all the missing bits in the or are already known to be set, match! 1161 if ((NeededMask & KnownOne) == NeededMask) 1162 return true; 1163 1164 // TODO: check to see if missing bits are just not demanded. 1165 1166 // Otherwise, this pattern doesn't match. 1167 return false; 1168} 1169 1170 1171/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 1172/// by tblgen. Others should not call it. 1173void SelectionDAGISel:: 1174SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) { 1175 std::vector<SDValue> InOps; 1176 std::swap(InOps, Ops); 1177 1178 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0 1179 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1 1180 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc 1181 Ops.push_back(InOps[InlineAsm::Op_IsAlignStack]); // 3 1182 1183 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size(); 1184 if (InOps[e-1].getValueType() == MVT::Flag) 1185 --e; // Don't process a flag operand if it is here. 1186 1187 while (i != e) { 1188 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue(); 1189 if (!InlineAsm::isMemKind(Flags)) { 1190 // Just skip over this operand, copying the operands verbatim. 1191 Ops.insert(Ops.end(), InOps.begin()+i, 1192 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1); 1193 i += InlineAsm::getNumOperandRegisters(Flags) + 1; 1194 } else { 1195 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 && 1196 "Memory operand with multiple values?"); 1197 // Otherwise, this is a memory operand. Ask the target to select it. 1198 std::vector<SDValue> SelOps; 1199 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) 1200 report_fatal_error("Could not match memory address. Inline asm" 1201 " failure!"); 1202 1203 // Add this to the output node. 1204 unsigned NewFlags = 1205 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size()); 1206 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32)); 1207 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 1208 i += 2; 1209 } 1210 } 1211 1212 // Add the flag input back if present. 1213 if (e != InOps.size()) 1214 Ops.push_back(InOps.back()); 1215} 1216 1217/// findFlagUse - Return use of EVT::Flag value produced by the specified 1218/// SDNode. 1219/// 1220static SDNode *findFlagUse(SDNode *N) { 1221 unsigned FlagResNo = N->getNumValues()-1; 1222 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 1223 SDUse &Use = I.getUse(); 1224 if (Use.getResNo() == FlagResNo) 1225 return Use.getUser(); 1226 } 1227 return NULL; 1228} 1229 1230/// findNonImmUse - Return true if "Use" is a non-immediate use of "Def". 1231/// This function recursively traverses up the operand chain, ignoring 1232/// certain nodes. 1233static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse, 1234 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited, 1235 bool IgnoreChains) { 1236 // The NodeID's are given uniques ID's where a node ID is guaranteed to be 1237 // greater than all of its (recursive) operands. If we scan to a point where 1238 // 'use' is smaller than the node we're scanning for, then we know we will 1239 // never find it. 1240 // 1241 // The Use may be -1 (unassigned) if it is a newly allocated node. This can 1242 // happen because we scan down to newly selected nodes in the case of flag 1243 // uses. 1244 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1)) 1245 return false; 1246 1247 // Don't revisit nodes if we already scanned it and didn't fail, we know we 1248 // won't fail if we scan it again. 1249 if (!Visited.insert(Use)) 1250 return false; 1251 1252 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) { 1253 // Ignore chain uses, they are validated by HandleMergeInputChains. 1254 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains) 1255 continue; 1256 1257 SDNode *N = Use->getOperand(i).getNode(); 1258 if (N == Def) { 1259 if (Use == ImmedUse || Use == Root) 1260 continue; // We are not looking for immediate use. 1261 assert(N != Root); 1262 return true; 1263 } 1264 1265 // Traverse up the operand chain. 1266 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains)) 1267 return true; 1268 } 1269 return false; 1270} 1271 1272/// IsProfitableToFold - Returns true if it's profitable to fold the specific 1273/// operand node N of U during instruction selection that starts at Root. 1274bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U, 1275 SDNode *Root) const { 1276 if (OptLevel == CodeGenOpt::None) return false; 1277 return N.hasOneUse(); 1278} 1279 1280/// IsLegalToFold - Returns true if the specific operand node N of 1281/// U can be folded during instruction selection that starts at Root. 1282bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root, 1283 CodeGenOpt::Level OptLevel, 1284 bool IgnoreChains) { 1285 if (OptLevel == CodeGenOpt::None) return false; 1286 1287 // If Root use can somehow reach N through a path that that doesn't contain 1288 // U then folding N would create a cycle. e.g. In the following 1289 // diagram, Root can reach N through X. If N is folded into into Root, then 1290 // X is both a predecessor and a successor of U. 1291 // 1292 // [N*] // 1293 // ^ ^ // 1294 // / \ // 1295 // [U*] [X]? // 1296 // ^ ^ // 1297 // \ / // 1298 // \ / // 1299 // [Root*] // 1300 // 1301 // * indicates nodes to be folded together. 1302 // 1303 // If Root produces a flag, then it gets (even more) interesting. Since it 1304 // will be "glued" together with its flag use in the scheduler, we need to 1305 // check if it might reach N. 1306 // 1307 // [N*] // 1308 // ^ ^ // 1309 // / \ // 1310 // [U*] [X]? // 1311 // ^ ^ // 1312 // \ \ // 1313 // \ | // 1314 // [Root*] | // 1315 // ^ | // 1316 // f | // 1317 // | / // 1318 // [Y] / // 1319 // ^ / // 1320 // f / // 1321 // | / // 1322 // [FU] // 1323 // 1324 // If FU (flag use) indirectly reaches N (the load), and Root folds N 1325 // (call it Fold), then X is a predecessor of FU and a successor of 1326 // Fold. But since Fold and FU are flagged together, this will create 1327 // a cycle in the scheduling graph. 1328 1329 // If the node has flags, walk down the graph to the "lowest" node in the 1330 // flagged set. 1331 EVT VT = Root->getValueType(Root->getNumValues()-1); 1332 while (VT == MVT::Flag) { 1333 SDNode *FU = findFlagUse(Root); 1334 if (FU == NULL) 1335 break; 1336 Root = FU; 1337 VT = Root->getValueType(Root->getNumValues()-1); 1338 1339 // If our query node has a flag result with a use, we've walked up it. If 1340 // the user (which has already been selected) has a chain or indirectly uses 1341 // the chain, our WalkChainUsers predicate will not consider it. Because of 1342 // this, we cannot ignore chains in this predicate. 1343 IgnoreChains = false; 1344 } 1345 1346 1347 SmallPtrSet<SDNode*, 16> Visited; 1348 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains); 1349} 1350 1351SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) { 1352 std::vector<SDValue> Ops(N->op_begin(), N->op_end()); 1353 SelectInlineAsmMemoryOperands(Ops); 1354 1355 std::vector<EVT> VTs; 1356 VTs.push_back(MVT::Other); 1357 VTs.push_back(MVT::Flag); 1358 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(), 1359 VTs, &Ops[0], Ops.size()); 1360 New->setNodeId(-1); 1361 return New.getNode(); 1362} 1363 1364SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) { 1365 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0)); 1366} 1367 1368/// GetVBR - decode a vbr encoding whose top bit is set. 1369ALWAYS_INLINE static uint64_t 1370GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) { 1371 assert(Val >= 128 && "Not a VBR"); 1372 Val &= 127; // Remove first vbr bit. 1373 1374 unsigned Shift = 7; 1375 uint64_t NextBits; 1376 do { 1377 NextBits = MatcherTable[Idx++]; 1378 Val |= (NextBits&127) << Shift; 1379 Shift += 7; 1380 } while (NextBits & 128); 1381 1382 return Val; 1383} 1384 1385 1386/// UpdateChainsAndFlags - When a match is complete, this method updates uses of 1387/// interior flag and chain results to use the new flag and chain results. 1388void SelectionDAGISel:: 1389UpdateChainsAndFlags(SDNode *NodeToMatch, SDValue InputChain, 1390 const SmallVectorImpl<SDNode*> &ChainNodesMatched, 1391 SDValue InputFlag, 1392 const SmallVectorImpl<SDNode*> &FlagResultNodesMatched, 1393 bool isMorphNodeTo) { 1394 SmallVector<SDNode*, 4> NowDeadNodes; 1395 1396 ISelUpdater ISU(ISelPosition); 1397 1398 // Now that all the normal results are replaced, we replace the chain and 1399 // flag results if present. 1400 if (!ChainNodesMatched.empty()) { 1401 assert(InputChain.getNode() != 0 && 1402 "Matched input chains but didn't produce a chain"); 1403 // Loop over all of the nodes we matched that produced a chain result. 1404 // Replace all the chain results with the final chain we ended up with. 1405 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1406 SDNode *ChainNode = ChainNodesMatched[i]; 1407 1408 // If this node was already deleted, don't look at it. 1409 if (ChainNode->getOpcode() == ISD::DELETED_NODE) 1410 continue; 1411 1412 // Don't replace the results of the root node if we're doing a 1413 // MorphNodeTo. 1414 if (ChainNode == NodeToMatch && isMorphNodeTo) 1415 continue; 1416 1417 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1); 1418 if (ChainVal.getValueType() == MVT::Flag) 1419 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2); 1420 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?"); 1421 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain, &ISU); 1422 1423 // If the node became dead and we haven't already seen it, delete it. 1424 if (ChainNode->use_empty() && 1425 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode)) 1426 NowDeadNodes.push_back(ChainNode); 1427 } 1428 } 1429 1430 // If the result produces a flag, update any flag results in the matched 1431 // pattern with the flag result. 1432 if (InputFlag.getNode() != 0) { 1433 // Handle any interior nodes explicitly marked. 1434 for (unsigned i = 0, e = FlagResultNodesMatched.size(); i != e; ++i) { 1435 SDNode *FRN = FlagResultNodesMatched[i]; 1436 1437 // If this node was already deleted, don't look at it. 1438 if (FRN->getOpcode() == ISD::DELETED_NODE) 1439 continue; 1440 1441 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Flag && 1442 "Doesn't have a flag result"); 1443 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1), 1444 InputFlag, &ISU); 1445 1446 // If the node became dead and we haven't already seen it, delete it. 1447 if (FRN->use_empty() && 1448 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN)) 1449 NowDeadNodes.push_back(FRN); 1450 } 1451 } 1452 1453 if (!NowDeadNodes.empty()) 1454 CurDAG->RemoveDeadNodes(NowDeadNodes, &ISU); 1455 1456 DEBUG(errs() << "ISEL: Match complete!\n"); 1457} 1458 1459enum ChainResult { 1460 CR_Simple, 1461 CR_InducesCycle, 1462 CR_LeadsToInteriorNode 1463}; 1464 1465/// WalkChainUsers - Walk down the users of the specified chained node that is 1466/// part of the pattern we're matching, looking at all of the users we find. 1467/// This determines whether something is an interior node, whether we have a 1468/// non-pattern node in between two pattern nodes (which prevent folding because 1469/// it would induce a cycle) and whether we have a TokenFactor node sandwiched 1470/// between pattern nodes (in which case the TF becomes part of the pattern). 1471/// 1472/// The walk we do here is guaranteed to be small because we quickly get down to 1473/// already selected nodes "below" us. 1474static ChainResult 1475WalkChainUsers(SDNode *ChainedNode, 1476 SmallVectorImpl<SDNode*> &ChainedNodesInPattern, 1477 SmallVectorImpl<SDNode*> &InteriorChainedNodes) { 1478 ChainResult Result = CR_Simple; 1479 1480 for (SDNode::use_iterator UI = ChainedNode->use_begin(), 1481 E = ChainedNode->use_end(); UI != E; ++UI) { 1482 // Make sure the use is of the chain, not some other value we produce. 1483 if (UI.getUse().getValueType() != MVT::Other) continue; 1484 1485 SDNode *User = *UI; 1486 1487 // If we see an already-selected machine node, then we've gone beyond the 1488 // pattern that we're selecting down into the already selected chunk of the 1489 // DAG. 1490 if (User->isMachineOpcode() || 1491 User->getOpcode() == ISD::HANDLENODE) // Root of the graph. 1492 continue; 1493 1494 if (User->getOpcode() == ISD::CopyToReg || 1495 User->getOpcode() == ISD::CopyFromReg || 1496 User->getOpcode() == ISD::INLINEASM || 1497 User->getOpcode() == ISD::EH_LABEL) { 1498 // If their node ID got reset to -1 then they've already been selected. 1499 // Treat them like a MachineOpcode. 1500 if (User->getNodeId() == -1) 1501 continue; 1502 } 1503 1504 // If we have a TokenFactor, we handle it specially. 1505 if (User->getOpcode() != ISD::TokenFactor) { 1506 // If the node isn't a token factor and isn't part of our pattern, then it 1507 // must be a random chained node in between two nodes we're selecting. 1508 // This happens when we have something like: 1509 // x = load ptr 1510 // call 1511 // y = x+4 1512 // store y -> ptr 1513 // Because we structurally match the load/store as a read/modify/write, 1514 // but the call is chained between them. We cannot fold in this case 1515 // because it would induce a cycle in the graph. 1516 if (!std::count(ChainedNodesInPattern.begin(), 1517 ChainedNodesInPattern.end(), User)) 1518 return CR_InducesCycle; 1519 1520 // Otherwise we found a node that is part of our pattern. For example in: 1521 // x = load ptr 1522 // y = x+4 1523 // store y -> ptr 1524 // This would happen when we're scanning down from the load and see the 1525 // store as a user. Record that there is a use of ChainedNode that is 1526 // part of the pattern and keep scanning uses. 1527 Result = CR_LeadsToInteriorNode; 1528 InteriorChainedNodes.push_back(User); 1529 continue; 1530 } 1531 1532 // If we found a TokenFactor, there are two cases to consider: first if the 1533 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no 1534 // uses of the TF are in our pattern) we just want to ignore it. Second, 1535 // the TokenFactor can be sandwiched in between two chained nodes, like so: 1536 // [Load chain] 1537 // ^ 1538 // | 1539 // [Load] 1540 // ^ ^ 1541 // | \ DAG's like cheese 1542 // / \ do you? 1543 // / | 1544 // [TokenFactor] [Op] 1545 // ^ ^ 1546 // | | 1547 // \ / 1548 // \ / 1549 // [Store] 1550 // 1551 // In this case, the TokenFactor becomes part of our match and we rewrite it 1552 // as a new TokenFactor. 1553 // 1554 // To distinguish these two cases, do a recursive walk down the uses. 1555 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) { 1556 case CR_Simple: 1557 // If the uses of the TokenFactor are just already-selected nodes, ignore 1558 // it, it is "below" our pattern. 1559 continue; 1560 case CR_InducesCycle: 1561 // If the uses of the TokenFactor lead to nodes that are not part of our 1562 // pattern that are not selected, folding would turn this into a cycle, 1563 // bail out now. 1564 return CR_InducesCycle; 1565 case CR_LeadsToInteriorNode: 1566 break; // Otherwise, keep processing. 1567 } 1568 1569 // Okay, we know we're in the interesting interior case. The TokenFactor 1570 // is now going to be considered part of the pattern so that we rewrite its 1571 // uses (it may have uses that are not part of the pattern) with the 1572 // ultimate chain result of the generated code. We will also add its chain 1573 // inputs as inputs to the ultimate TokenFactor we create. 1574 Result = CR_LeadsToInteriorNode; 1575 ChainedNodesInPattern.push_back(User); 1576 InteriorChainedNodes.push_back(User); 1577 continue; 1578 } 1579 1580 return Result; 1581} 1582 1583/// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains 1584/// operation for when the pattern matched at least one node with a chains. The 1585/// input vector contains a list of all of the chained nodes that we match. We 1586/// must determine if this is a valid thing to cover (i.e. matching it won't 1587/// induce cycles in the DAG) and if so, creating a TokenFactor node. that will 1588/// be used as the input node chain for the generated nodes. 1589static SDValue 1590HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched, 1591 SelectionDAG *CurDAG) { 1592 // Walk all of the chained nodes we've matched, recursively scanning down the 1593 // users of the chain result. This adds any TokenFactor nodes that are caught 1594 // in between chained nodes to the chained and interior nodes list. 1595 SmallVector<SDNode*, 3> InteriorChainedNodes; 1596 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1597 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched, 1598 InteriorChainedNodes) == CR_InducesCycle) 1599 return SDValue(); // Would induce a cycle. 1600 } 1601 1602 // Okay, we have walked all the matched nodes and collected TokenFactor nodes 1603 // that we are interested in. Form our input TokenFactor node. 1604 SmallVector<SDValue, 3> InputChains; 1605 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1606 // Add the input chain of this node to the InputChains list (which will be 1607 // the operands of the generated TokenFactor) if it's not an interior node. 1608 SDNode *N = ChainNodesMatched[i]; 1609 if (N->getOpcode() != ISD::TokenFactor) { 1610 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N)) 1611 continue; 1612 1613 // Otherwise, add the input chain. 1614 SDValue InChain = ChainNodesMatched[i]->getOperand(0); 1615 assert(InChain.getValueType() == MVT::Other && "Not a chain"); 1616 InputChains.push_back(InChain); 1617 continue; 1618 } 1619 1620 // If we have a token factor, we want to add all inputs of the token factor 1621 // that are not part of the pattern we're matching. 1622 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) { 1623 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(), 1624 N->getOperand(op).getNode())) 1625 InputChains.push_back(N->getOperand(op)); 1626 } 1627 } 1628 1629 SDValue Res; 1630 if (InputChains.size() == 1) 1631 return InputChains[0]; 1632 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(), 1633 MVT::Other, &InputChains[0], InputChains.size()); 1634} 1635 1636/// MorphNode - Handle morphing a node in place for the selector. 1637SDNode *SelectionDAGISel:: 1638MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList, 1639 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) { 1640 // It is possible we're using MorphNodeTo to replace a node with no 1641 // normal results with one that has a normal result (or we could be 1642 // adding a chain) and the input could have flags and chains as well. 1643 // In this case we need to shift the operands down. 1644 // FIXME: This is a horrible hack and broken in obscure cases, no worse 1645 // than the old isel though. 1646 int OldFlagResultNo = -1, OldChainResultNo = -1; 1647 1648 unsigned NTMNumResults = Node->getNumValues(); 1649 if (Node->getValueType(NTMNumResults-1) == MVT::Flag) { 1650 OldFlagResultNo = NTMNumResults-1; 1651 if (NTMNumResults != 1 && 1652 Node->getValueType(NTMNumResults-2) == MVT::Other) 1653 OldChainResultNo = NTMNumResults-2; 1654 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other) 1655 OldChainResultNo = NTMNumResults-1; 1656 1657 // Call the underlying SelectionDAG routine to do the transmogrification. Note 1658 // that this deletes operands of the old node that become dead. 1659 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps); 1660 1661 // MorphNodeTo can operate in two ways: if an existing node with the 1662 // specified operands exists, it can just return it. Otherwise, it 1663 // updates the node in place to have the requested operands. 1664 if (Res == Node) { 1665 // If we updated the node in place, reset the node ID. To the isel, 1666 // this should be just like a newly allocated machine node. 1667 Res->setNodeId(-1); 1668 } 1669 1670 unsigned ResNumResults = Res->getNumValues(); 1671 // Move the flag if needed. 1672 if ((EmitNodeInfo & OPFL_FlagOutput) && OldFlagResultNo != -1 && 1673 (unsigned)OldFlagResultNo != ResNumResults-1) 1674 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldFlagResultNo), 1675 SDValue(Res, ResNumResults-1)); 1676 1677 if ((EmitNodeInfo & OPFL_FlagOutput) != 0) 1678 --ResNumResults; 1679 1680 // Move the chain reference if needed. 1681 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 && 1682 (unsigned)OldChainResultNo != ResNumResults-1) 1683 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo), 1684 SDValue(Res, ResNumResults-1)); 1685 1686 // Otherwise, no replacement happened because the node already exists. Replace 1687 // Uses of the old node with the new one. 1688 if (Res != Node) 1689 CurDAG->ReplaceAllUsesWith(Node, Res); 1690 1691 return Res; 1692} 1693 1694/// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 1695ALWAYS_INLINE static bool 1696CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1697 SDValue N, 1698 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) { 1699 // Accept if it is exactly the same as a previously recorded node. 1700 unsigned RecNo = MatcherTable[MatcherIndex++]; 1701 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 1702 return N == RecordedNodes[RecNo].first; 1703} 1704 1705/// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 1706ALWAYS_INLINE static bool 1707CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1708 SelectionDAGISel &SDISel) { 1709 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]); 1710} 1711 1712/// CheckNodePredicate - Implements OP_CheckNodePredicate. 1713ALWAYS_INLINE static bool 1714CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1715 SelectionDAGISel &SDISel, SDNode *N) { 1716 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]); 1717} 1718 1719ALWAYS_INLINE static bool 1720CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1721 SDNode *N) { 1722 uint16_t Opc = MatcherTable[MatcherIndex++]; 1723 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 1724 return N->getOpcode() == Opc; 1725} 1726 1727ALWAYS_INLINE static bool 1728CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1729 SDValue N, const TargetLowering &TLI) { 1730 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 1731 if (N.getValueType() == VT) return true; 1732 1733 // Handle the case when VT is iPTR. 1734 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy(); 1735} 1736 1737ALWAYS_INLINE static bool 1738CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1739 SDValue N, const TargetLowering &TLI, 1740 unsigned ChildNo) { 1741 if (ChildNo >= N.getNumOperands()) 1742 return false; // Match fails if out of range child #. 1743 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI); 1744} 1745 1746 1747ALWAYS_INLINE static bool 1748CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1749 SDValue N) { 1750 return cast<CondCodeSDNode>(N)->get() == 1751 (ISD::CondCode)MatcherTable[MatcherIndex++]; 1752} 1753 1754ALWAYS_INLINE static bool 1755CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1756 SDValue N, const TargetLowering &TLI) { 1757 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 1758 if (cast<VTSDNode>(N)->getVT() == VT) 1759 return true; 1760 1761 // Handle the case when VT is iPTR. 1762 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy(); 1763} 1764 1765ALWAYS_INLINE static bool 1766CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1767 SDValue N) { 1768 int64_t Val = MatcherTable[MatcherIndex++]; 1769 if (Val & 128) 1770 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1771 1772 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N); 1773 return C != 0 && C->getSExtValue() == Val; 1774} 1775 1776ALWAYS_INLINE static bool 1777CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1778 SDValue N, SelectionDAGISel &SDISel) { 1779 int64_t Val = MatcherTable[MatcherIndex++]; 1780 if (Val & 128) 1781 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1782 1783 if (N->getOpcode() != ISD::AND) return false; 1784 1785 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 1786 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val); 1787} 1788 1789ALWAYS_INLINE static bool 1790CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1791 SDValue N, SelectionDAGISel &SDISel) { 1792 int64_t Val = MatcherTable[MatcherIndex++]; 1793 if (Val & 128) 1794 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1795 1796 if (N->getOpcode() != ISD::OR) return false; 1797 1798 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 1799 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val); 1800} 1801 1802/// IsPredicateKnownToFail - If we know how and can do so without pushing a 1803/// scope, evaluate the current node. If the current predicate is known to 1804/// fail, set Result=true and return anything. If the current predicate is 1805/// known to pass, set Result=false and return the MatcherIndex to continue 1806/// with. If the current predicate is unknown, set Result=false and return the 1807/// MatcherIndex to continue with. 1808static unsigned IsPredicateKnownToFail(const unsigned char *Table, 1809 unsigned Index, SDValue N, 1810 bool &Result, SelectionDAGISel &SDISel, 1811 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) { 1812 switch (Table[Index++]) { 1813 default: 1814 Result = false; 1815 return Index-1; // Could not evaluate this predicate. 1816 case SelectionDAGISel::OPC_CheckSame: 1817 Result = !::CheckSame(Table, Index, N, RecordedNodes); 1818 return Index; 1819 case SelectionDAGISel::OPC_CheckPatternPredicate: 1820 Result = !::CheckPatternPredicate(Table, Index, SDISel); 1821 return Index; 1822 case SelectionDAGISel::OPC_CheckPredicate: 1823 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode()); 1824 return Index; 1825 case SelectionDAGISel::OPC_CheckOpcode: 1826 Result = !::CheckOpcode(Table, Index, N.getNode()); 1827 return Index; 1828 case SelectionDAGISel::OPC_CheckType: 1829 Result = !::CheckType(Table, Index, N, SDISel.TLI); 1830 return Index; 1831 case SelectionDAGISel::OPC_CheckChild0Type: 1832 case SelectionDAGISel::OPC_CheckChild1Type: 1833 case SelectionDAGISel::OPC_CheckChild2Type: 1834 case SelectionDAGISel::OPC_CheckChild3Type: 1835 case SelectionDAGISel::OPC_CheckChild4Type: 1836 case SelectionDAGISel::OPC_CheckChild5Type: 1837 case SelectionDAGISel::OPC_CheckChild6Type: 1838 case SelectionDAGISel::OPC_CheckChild7Type: 1839 Result = !::CheckChildType(Table, Index, N, SDISel.TLI, 1840 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type); 1841 return Index; 1842 case SelectionDAGISel::OPC_CheckCondCode: 1843 Result = !::CheckCondCode(Table, Index, N); 1844 return Index; 1845 case SelectionDAGISel::OPC_CheckValueType: 1846 Result = !::CheckValueType(Table, Index, N, SDISel.TLI); 1847 return Index; 1848 case SelectionDAGISel::OPC_CheckInteger: 1849 Result = !::CheckInteger(Table, Index, N); 1850 return Index; 1851 case SelectionDAGISel::OPC_CheckAndImm: 1852 Result = !::CheckAndImm(Table, Index, N, SDISel); 1853 return Index; 1854 case SelectionDAGISel::OPC_CheckOrImm: 1855 Result = !::CheckOrImm(Table, Index, N, SDISel); 1856 return Index; 1857 } 1858} 1859 1860namespace { 1861 1862struct MatchScope { 1863 /// FailIndex - If this match fails, this is the index to continue with. 1864 unsigned FailIndex; 1865 1866 /// NodeStack - The node stack when the scope was formed. 1867 SmallVector<SDValue, 4> NodeStack; 1868 1869 /// NumRecordedNodes - The number of recorded nodes when the scope was formed. 1870 unsigned NumRecordedNodes; 1871 1872 /// NumMatchedMemRefs - The number of matched memref entries. 1873 unsigned NumMatchedMemRefs; 1874 1875 /// InputChain/InputFlag - The current chain/flag 1876 SDValue InputChain, InputFlag; 1877 1878 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty. 1879 bool HasChainNodesMatched, HasFlagResultNodesMatched; 1880}; 1881 1882} 1883 1884SDNode *SelectionDAGISel:: 1885SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable, 1886 unsigned TableSize) { 1887 // FIXME: Should these even be selected? Handle these cases in the caller? 1888 switch (NodeToMatch->getOpcode()) { 1889 default: 1890 break; 1891 case ISD::EntryToken: // These nodes remain the same. 1892 case ISD::BasicBlock: 1893 case ISD::Register: 1894 //case ISD::VALUETYPE: 1895 //case ISD::CONDCODE: 1896 case ISD::HANDLENODE: 1897 case ISD::MDNODE_SDNODE: 1898 case ISD::TargetConstant: 1899 case ISD::TargetConstantFP: 1900 case ISD::TargetConstantPool: 1901 case ISD::TargetFrameIndex: 1902 case ISD::TargetExternalSymbol: 1903 case ISD::TargetBlockAddress: 1904 case ISD::TargetJumpTable: 1905 case ISD::TargetGlobalTLSAddress: 1906 case ISD::TargetGlobalAddress: 1907 case ISD::TokenFactor: 1908 case ISD::CopyFromReg: 1909 case ISD::CopyToReg: 1910 case ISD::EH_LABEL: 1911 NodeToMatch->setNodeId(-1); // Mark selected. 1912 return 0; 1913 case ISD::AssertSext: 1914 case ISD::AssertZext: 1915 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0), 1916 NodeToMatch->getOperand(0)); 1917 return 0; 1918 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch); 1919 case ISD::UNDEF: return Select_UNDEF(NodeToMatch); 1920 } 1921 1922 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!"); 1923 1924 // Set up the node stack with NodeToMatch as the only node on the stack. 1925 SmallVector<SDValue, 8> NodeStack; 1926 SDValue N = SDValue(NodeToMatch, 0); 1927 NodeStack.push_back(N); 1928 1929 // MatchScopes - Scopes used when matching, if a match failure happens, this 1930 // indicates where to continue checking. 1931 SmallVector<MatchScope, 8> MatchScopes; 1932 1933 // RecordedNodes - This is the set of nodes that have been recorded by the 1934 // state machine. The second value is the parent of the node, or null if the 1935 // root is recorded. 1936 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes; 1937 1938 // MatchedMemRefs - This is the set of MemRef's we've seen in the input 1939 // pattern. 1940 SmallVector<MachineMemOperand*, 2> MatchedMemRefs; 1941 1942 // These are the current input chain and flag for use when generating nodes. 1943 // Various Emit operations change these. For example, emitting a copytoreg 1944 // uses and updates these. 1945 SDValue InputChain, InputFlag; 1946 1947 // ChainNodesMatched - If a pattern matches nodes that have input/output 1948 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates 1949 // which ones they are. The result is captured into this list so that we can 1950 // update the chain results when the pattern is complete. 1951 SmallVector<SDNode*, 3> ChainNodesMatched; 1952 SmallVector<SDNode*, 3> FlagResultNodesMatched; 1953 1954 DEBUG(errs() << "ISEL: Starting pattern match on root node: "; 1955 NodeToMatch->dump(CurDAG); 1956 errs() << '\n'); 1957 1958 // Determine where to start the interpreter. Normally we start at opcode #0, 1959 // but if the state machine starts with an OPC_SwitchOpcode, then we 1960 // accelerate the first lookup (which is guaranteed to be hot) with the 1961 // OpcodeOffset table. 1962 unsigned MatcherIndex = 0; 1963 1964 if (!OpcodeOffset.empty()) { 1965 // Already computed the OpcodeOffset table, just index into it. 1966 if (N.getOpcode() < OpcodeOffset.size()) 1967 MatcherIndex = OpcodeOffset[N.getOpcode()]; 1968 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n"); 1969 1970 } else if (MatcherTable[0] == OPC_SwitchOpcode) { 1971 // Otherwise, the table isn't computed, but the state machine does start 1972 // with an OPC_SwitchOpcode instruction. Populate the table now, since this 1973 // is the first time we're selecting an instruction. 1974 unsigned Idx = 1; 1975 while (1) { 1976 // Get the size of this case. 1977 unsigned CaseSize = MatcherTable[Idx++]; 1978 if (CaseSize & 128) 1979 CaseSize = GetVBR(CaseSize, MatcherTable, Idx); 1980 if (CaseSize == 0) break; 1981 1982 // Get the opcode, add the index to the table. 1983 uint16_t Opc = MatcherTable[Idx++]; 1984 Opc |= (unsigned short)MatcherTable[Idx++] << 8; 1985 if (Opc >= OpcodeOffset.size()) 1986 OpcodeOffset.resize((Opc+1)*2); 1987 OpcodeOffset[Opc] = Idx; 1988 Idx += CaseSize; 1989 } 1990 1991 // Okay, do the lookup for the first opcode. 1992 if (N.getOpcode() < OpcodeOffset.size()) 1993 MatcherIndex = OpcodeOffset[N.getOpcode()]; 1994 } 1995 1996 while (1) { 1997 assert(MatcherIndex < TableSize && "Invalid index"); 1998#ifndef NDEBUG 1999 unsigned CurrentOpcodeIndex = MatcherIndex; 2000#endif 2001 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++]; 2002 switch (Opcode) { 2003 case OPC_Scope: { 2004 // Okay, the semantics of this operation are that we should push a scope 2005 // then evaluate the first child. However, pushing a scope only to have 2006 // the first check fail (which then pops it) is inefficient. If we can 2007 // determine immediately that the first check (or first several) will 2008 // immediately fail, don't even bother pushing a scope for them. 2009 unsigned FailIndex; 2010 2011 while (1) { 2012 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2013 if (NumToSkip & 128) 2014 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2015 // Found the end of the scope with no match. 2016 if (NumToSkip == 0) { 2017 FailIndex = 0; 2018 break; 2019 } 2020 2021 FailIndex = MatcherIndex+NumToSkip; 2022 2023 unsigned MatcherIndexOfPredicate = MatcherIndex; 2024 (void)MatcherIndexOfPredicate; // silence warning. 2025 2026 // If we can't evaluate this predicate without pushing a scope (e.g. if 2027 // it is a 'MoveParent') or if the predicate succeeds on this node, we 2028 // push the scope and evaluate the full predicate chain. 2029 bool Result; 2030 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N, 2031 Result, *this, RecordedNodes); 2032 if (!Result) 2033 break; 2034 2035 DEBUG(errs() << " Skipped scope entry (due to false predicate) at " 2036 << "index " << MatcherIndexOfPredicate 2037 << ", continuing at " << FailIndex << "\n"); 2038 ++NumDAGIselRetries; 2039 2040 // Otherwise, we know that this case of the Scope is guaranteed to fail, 2041 // move to the next case. 2042 MatcherIndex = FailIndex; 2043 } 2044 2045 // If the whole scope failed to match, bail. 2046 if (FailIndex == 0) break; 2047 2048 // Push a MatchScope which indicates where to go if the first child fails 2049 // to match. 2050 MatchScope NewEntry; 2051 NewEntry.FailIndex = FailIndex; 2052 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end()); 2053 NewEntry.NumRecordedNodes = RecordedNodes.size(); 2054 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size(); 2055 NewEntry.InputChain = InputChain; 2056 NewEntry.InputFlag = InputFlag; 2057 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty(); 2058 NewEntry.HasFlagResultNodesMatched = !FlagResultNodesMatched.empty(); 2059 MatchScopes.push_back(NewEntry); 2060 continue; 2061 } 2062 case OPC_RecordNode: { 2063 // Remember this node, it may end up being an operand in the pattern. 2064 SDNode *Parent = 0; 2065 if (NodeStack.size() > 1) 2066 Parent = NodeStack[NodeStack.size()-2].getNode(); 2067 RecordedNodes.push_back(std::make_pair(N, Parent)); 2068 continue; 2069 } 2070 2071 case OPC_RecordChild0: case OPC_RecordChild1: 2072 case OPC_RecordChild2: case OPC_RecordChild3: 2073 case OPC_RecordChild4: case OPC_RecordChild5: 2074 case OPC_RecordChild6: case OPC_RecordChild7: { 2075 unsigned ChildNo = Opcode-OPC_RecordChild0; 2076 if (ChildNo >= N.getNumOperands()) 2077 break; // Match fails if out of range child #. 2078 2079 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo), 2080 N.getNode())); 2081 continue; 2082 } 2083 case OPC_RecordMemRef: 2084 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand()); 2085 continue; 2086 2087 case OPC_CaptureFlagInput: 2088 // If the current node has an input flag, capture it in InputFlag. 2089 if (N->getNumOperands() != 0 && 2090 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag) 2091 InputFlag = N->getOperand(N->getNumOperands()-1); 2092 continue; 2093 2094 case OPC_MoveChild: { 2095 unsigned ChildNo = MatcherTable[MatcherIndex++]; 2096 if (ChildNo >= N.getNumOperands()) 2097 break; // Match fails if out of range child #. 2098 N = N.getOperand(ChildNo); 2099 NodeStack.push_back(N); 2100 continue; 2101 } 2102 2103 case OPC_MoveParent: 2104 // Pop the current node off the NodeStack. 2105 NodeStack.pop_back(); 2106 assert(!NodeStack.empty() && "Node stack imbalance!"); 2107 N = NodeStack.back(); 2108 continue; 2109 2110 case OPC_CheckSame: 2111 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break; 2112 continue; 2113 case OPC_CheckPatternPredicate: 2114 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break; 2115 continue; 2116 case OPC_CheckPredicate: 2117 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this, 2118 N.getNode())) 2119 break; 2120 continue; 2121 case OPC_CheckComplexPat: { 2122 unsigned CPNum = MatcherTable[MatcherIndex++]; 2123 unsigned RecNo = MatcherTable[MatcherIndex++]; 2124 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat"); 2125 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second, 2126 RecordedNodes[RecNo].first, CPNum, 2127 RecordedNodes)) 2128 break; 2129 continue; 2130 } 2131 case OPC_CheckOpcode: 2132 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break; 2133 continue; 2134 2135 case OPC_CheckType: 2136 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break; 2137 continue; 2138 2139 case OPC_SwitchOpcode: { 2140 unsigned CurNodeOpcode = N.getOpcode(); 2141 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2142 unsigned CaseSize; 2143 while (1) { 2144 // Get the size of this case. 2145 CaseSize = MatcherTable[MatcherIndex++]; 2146 if (CaseSize & 128) 2147 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2148 if (CaseSize == 0) break; 2149 2150 uint16_t Opc = MatcherTable[MatcherIndex++]; 2151 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2152 2153 // If the opcode matches, then we will execute this case. 2154 if (CurNodeOpcode == Opc) 2155 break; 2156 2157 // Otherwise, skip over this case. 2158 MatcherIndex += CaseSize; 2159 } 2160 2161 // If no cases matched, bail out. 2162 if (CaseSize == 0) break; 2163 2164 // Otherwise, execute the case we found. 2165 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart 2166 << " to " << MatcherIndex << "\n"); 2167 continue; 2168 } 2169 2170 case OPC_SwitchType: { 2171 MVT::SimpleValueType CurNodeVT = N.getValueType().getSimpleVT().SimpleTy; 2172 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2173 unsigned CaseSize; 2174 while (1) { 2175 // Get the size of this case. 2176 CaseSize = MatcherTable[MatcherIndex++]; 2177 if (CaseSize & 128) 2178 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2179 if (CaseSize == 0) break; 2180 2181 MVT::SimpleValueType CaseVT = 2182 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2183 if (CaseVT == MVT::iPTR) 2184 CaseVT = TLI.getPointerTy().SimpleTy; 2185 2186 // If the VT matches, then we will execute this case. 2187 if (CurNodeVT == CaseVT) 2188 break; 2189 2190 // Otherwise, skip over this case. 2191 MatcherIndex += CaseSize; 2192 } 2193 2194 // If no cases matched, bail out. 2195 if (CaseSize == 0) break; 2196 2197 // Otherwise, execute the case we found. 2198 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString() 2199 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n'); 2200 continue; 2201 } 2202 case OPC_CheckChild0Type: case OPC_CheckChild1Type: 2203 case OPC_CheckChild2Type: case OPC_CheckChild3Type: 2204 case OPC_CheckChild4Type: case OPC_CheckChild5Type: 2205 case OPC_CheckChild6Type: case OPC_CheckChild7Type: 2206 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI, 2207 Opcode-OPC_CheckChild0Type)) 2208 break; 2209 continue; 2210 case OPC_CheckCondCode: 2211 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break; 2212 continue; 2213 case OPC_CheckValueType: 2214 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break; 2215 continue; 2216 case OPC_CheckInteger: 2217 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break; 2218 continue; 2219 case OPC_CheckAndImm: 2220 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break; 2221 continue; 2222 case OPC_CheckOrImm: 2223 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break; 2224 continue; 2225 2226 case OPC_CheckFoldableChainNode: { 2227 assert(NodeStack.size() != 1 && "No parent node"); 2228 // Verify that all intermediate nodes between the root and this one have 2229 // a single use. 2230 bool HasMultipleUses = false; 2231 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i) 2232 if (!NodeStack[i].hasOneUse()) { 2233 HasMultipleUses = true; 2234 break; 2235 } 2236 if (HasMultipleUses) break; 2237 2238 // Check to see that the target thinks this is profitable to fold and that 2239 // we can fold it without inducing cycles in the graph. 2240 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2241 NodeToMatch) || 2242 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2243 NodeToMatch, OptLevel, 2244 true/*We validate our own chains*/)) 2245 break; 2246 2247 continue; 2248 } 2249 case OPC_EmitInteger: { 2250 MVT::SimpleValueType VT = 2251 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2252 int64_t Val = MatcherTable[MatcherIndex++]; 2253 if (Val & 128) 2254 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2255 RecordedNodes.push_back(std::pair<SDValue, SDNode*>( 2256 CurDAG->getTargetConstant(Val, VT), (SDNode*)0)); 2257 continue; 2258 } 2259 case OPC_EmitRegister: { 2260 MVT::SimpleValueType VT = 2261 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2262 unsigned RegNo = MatcherTable[MatcherIndex++]; 2263 RecordedNodes.push_back(std::pair<SDValue, SDNode*>( 2264 CurDAG->getRegister(RegNo, VT), (SDNode*)0)); 2265 continue; 2266 } 2267 2268 case OPC_EmitConvertToTarget: { 2269 // Convert from IMM/FPIMM to target version. 2270 unsigned RecNo = MatcherTable[MatcherIndex++]; 2271 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2272 SDValue Imm = RecordedNodes[RecNo].first; 2273 2274 if (Imm->getOpcode() == ISD::Constant) { 2275 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue(); 2276 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType()); 2277 } else if (Imm->getOpcode() == ISD::ConstantFP) { 2278 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue(); 2279 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType()); 2280 } 2281 2282 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second)); 2283 continue; 2284 } 2285 2286 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0 2287 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1 2288 // These are space-optimized forms of OPC_EmitMergeInputChains. 2289 assert(InputChain.getNode() == 0 && 2290 "EmitMergeInputChains should be the first chain producing node"); 2291 assert(ChainNodesMatched.empty() && 2292 "Should only have one EmitMergeInputChains per match"); 2293 2294 // Read all of the chained nodes. 2295 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1; 2296 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2297 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode()); 2298 2299 // FIXME: What if other value results of the node have uses not matched 2300 // by this pattern? 2301 if (ChainNodesMatched.back() != NodeToMatch && 2302 !RecordedNodes[RecNo].first.hasOneUse()) { 2303 ChainNodesMatched.clear(); 2304 break; 2305 } 2306 2307 // Merge the input chains if they are not intra-pattern references. 2308 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2309 2310 if (InputChain.getNode() == 0) 2311 break; // Failed to merge. 2312 continue; 2313 } 2314 2315 case OPC_EmitMergeInputChains: { 2316 assert(InputChain.getNode() == 0 && 2317 "EmitMergeInputChains should be the first chain producing node"); 2318 // This node gets a list of nodes we matched in the input that have 2319 // chains. We want to token factor all of the input chains to these nodes 2320 // together. However, if any of the input chains is actually one of the 2321 // nodes matched in this pattern, then we have an intra-match reference. 2322 // Ignore these because the newly token factored chain should not refer to 2323 // the old nodes. 2324 unsigned NumChains = MatcherTable[MatcherIndex++]; 2325 assert(NumChains != 0 && "Can't TF zero chains"); 2326 2327 assert(ChainNodesMatched.empty() && 2328 "Should only have one EmitMergeInputChains per match"); 2329 2330 // Read all of the chained nodes. 2331 for (unsigned i = 0; i != NumChains; ++i) { 2332 unsigned RecNo = MatcherTable[MatcherIndex++]; 2333 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2334 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode()); 2335 2336 // FIXME: What if other value results of the node have uses not matched 2337 // by this pattern? 2338 if (ChainNodesMatched.back() != NodeToMatch && 2339 !RecordedNodes[RecNo].first.hasOneUse()) { 2340 ChainNodesMatched.clear(); 2341 break; 2342 } 2343 } 2344 2345 // If the inner loop broke out, the match fails. 2346 if (ChainNodesMatched.empty()) 2347 break; 2348 2349 // Merge the input chains if they are not intra-pattern references. 2350 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2351 2352 if (InputChain.getNode() == 0) 2353 break; // Failed to merge. 2354 2355 continue; 2356 } 2357 2358 case OPC_EmitCopyToReg: { 2359 unsigned RecNo = MatcherTable[MatcherIndex++]; 2360 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2361 unsigned DestPhysReg = MatcherTable[MatcherIndex++]; 2362 2363 if (InputChain.getNode() == 0) 2364 InputChain = CurDAG->getEntryNode(); 2365 2366 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(), 2367 DestPhysReg, RecordedNodes[RecNo].first, 2368 InputFlag); 2369 2370 InputFlag = InputChain.getValue(1); 2371 continue; 2372 } 2373 2374 case OPC_EmitNodeXForm: { 2375 unsigned XFormNo = MatcherTable[MatcherIndex++]; 2376 unsigned RecNo = MatcherTable[MatcherIndex++]; 2377 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2378 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo); 2379 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, (SDNode*) 0)); 2380 continue; 2381 } 2382 2383 case OPC_EmitNode: 2384 case OPC_MorphNodeTo: { 2385 uint16_t TargetOpc = MatcherTable[MatcherIndex++]; 2386 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2387 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++]; 2388 // Get the result VT list. 2389 unsigned NumVTs = MatcherTable[MatcherIndex++]; 2390 SmallVector<EVT, 4> VTs; 2391 for (unsigned i = 0; i != NumVTs; ++i) { 2392 MVT::SimpleValueType VT = 2393 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2394 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy; 2395 VTs.push_back(VT); 2396 } 2397 2398 if (EmitNodeInfo & OPFL_Chain) 2399 VTs.push_back(MVT::Other); 2400 if (EmitNodeInfo & OPFL_FlagOutput) 2401 VTs.push_back(MVT::Flag); 2402 2403 // This is hot code, so optimize the two most common cases of 1 and 2 2404 // results. 2405 SDVTList VTList; 2406 if (VTs.size() == 1) 2407 VTList = CurDAG->getVTList(VTs[0]); 2408 else if (VTs.size() == 2) 2409 VTList = CurDAG->getVTList(VTs[0], VTs[1]); 2410 else 2411 VTList = CurDAG->getVTList(VTs.data(), VTs.size()); 2412 2413 // Get the operand list. 2414 unsigned NumOps = MatcherTable[MatcherIndex++]; 2415 SmallVector<SDValue, 8> Ops; 2416 for (unsigned i = 0; i != NumOps; ++i) { 2417 unsigned RecNo = MatcherTable[MatcherIndex++]; 2418 if (RecNo & 128) 2419 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2420 2421 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode"); 2422 Ops.push_back(RecordedNodes[RecNo].first); 2423 } 2424 2425 // If there are variadic operands to add, handle them now. 2426 if (EmitNodeInfo & OPFL_VariadicInfo) { 2427 // Determine the start index to copy from. 2428 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo); 2429 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0; 2430 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy && 2431 "Invalid variadic node"); 2432 // Copy all of the variadic operands, not including a potential flag 2433 // input. 2434 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands(); 2435 i != e; ++i) { 2436 SDValue V = NodeToMatch->getOperand(i); 2437 if (V.getValueType() == MVT::Flag) break; 2438 Ops.push_back(V); 2439 } 2440 } 2441 2442 // If this has chain/flag inputs, add them. 2443 if (EmitNodeInfo & OPFL_Chain) 2444 Ops.push_back(InputChain); 2445 if ((EmitNodeInfo & OPFL_FlagInput) && InputFlag.getNode() != 0) 2446 Ops.push_back(InputFlag); 2447 2448 // Create the node. 2449 SDNode *Res = 0; 2450 if (Opcode != OPC_MorphNodeTo) { 2451 // If this is a normal EmitNode command, just create the new node and 2452 // add the results to the RecordedNodes list. 2453 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(), 2454 VTList, Ops.data(), Ops.size()); 2455 2456 // Add all the non-flag/non-chain results to the RecordedNodes list. 2457 for (unsigned i = 0, e = VTs.size(); i != e; ++i) { 2458 if (VTs[i] == MVT::Other || VTs[i] == MVT::Flag) break; 2459 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i), 2460 (SDNode*) 0)); 2461 } 2462 2463 } else { 2464 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(), 2465 EmitNodeInfo); 2466 } 2467 2468 // If the node had chain/flag results, update our notion of the current 2469 // chain and flag. 2470 if (EmitNodeInfo & OPFL_FlagOutput) { 2471 InputFlag = SDValue(Res, VTs.size()-1); 2472 if (EmitNodeInfo & OPFL_Chain) 2473 InputChain = SDValue(Res, VTs.size()-2); 2474 } else if (EmitNodeInfo & OPFL_Chain) 2475 InputChain = SDValue(Res, VTs.size()-1); 2476 2477 // If the OPFL_MemRefs flag is set on this node, slap all of the 2478 // accumulated memrefs onto it. 2479 // 2480 // FIXME: This is vastly incorrect for patterns with multiple outputs 2481 // instructions that access memory and for ComplexPatterns that match 2482 // loads. 2483 if (EmitNodeInfo & OPFL_MemRefs) { 2484 MachineSDNode::mmo_iterator MemRefs = 2485 MF->allocateMemRefsArray(MatchedMemRefs.size()); 2486 std::copy(MatchedMemRefs.begin(), MatchedMemRefs.end(), MemRefs); 2487 cast<MachineSDNode>(Res) 2488 ->setMemRefs(MemRefs, MemRefs + MatchedMemRefs.size()); 2489 } 2490 2491 DEBUG(errs() << " " 2492 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created") 2493 << " node: "; Res->dump(CurDAG); errs() << "\n"); 2494 2495 // If this was a MorphNodeTo then we're completely done! 2496 if (Opcode == OPC_MorphNodeTo) { 2497 // Update chain and flag uses. 2498 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched, 2499 InputFlag, FlagResultNodesMatched, true); 2500 return Res; 2501 } 2502 2503 continue; 2504 } 2505 2506 case OPC_MarkFlagResults: { 2507 unsigned NumNodes = MatcherTable[MatcherIndex++]; 2508 2509 // Read and remember all the flag-result nodes. 2510 for (unsigned i = 0; i != NumNodes; ++i) { 2511 unsigned RecNo = MatcherTable[MatcherIndex++]; 2512 if (RecNo & 128) 2513 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2514 2515 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2516 FlagResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode()); 2517 } 2518 continue; 2519 } 2520 2521 case OPC_CompleteMatch: { 2522 // The match has been completed, and any new nodes (if any) have been 2523 // created. Patch up references to the matched dag to use the newly 2524 // created nodes. 2525 unsigned NumResults = MatcherTable[MatcherIndex++]; 2526 2527 for (unsigned i = 0; i != NumResults; ++i) { 2528 unsigned ResSlot = MatcherTable[MatcherIndex++]; 2529 if (ResSlot & 128) 2530 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex); 2531 2532 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame"); 2533 SDValue Res = RecordedNodes[ResSlot].first; 2534 2535 assert(i < NodeToMatch->getNumValues() && 2536 NodeToMatch->getValueType(i) != MVT::Other && 2537 NodeToMatch->getValueType(i) != MVT::Flag && 2538 "Invalid number of results to complete!"); 2539 assert((NodeToMatch->getValueType(i) == Res.getValueType() || 2540 NodeToMatch->getValueType(i) == MVT::iPTR || 2541 Res.getValueType() == MVT::iPTR || 2542 NodeToMatch->getValueType(i).getSizeInBits() == 2543 Res.getValueType().getSizeInBits()) && 2544 "invalid replacement"); 2545 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res); 2546 } 2547 2548 // If the root node defines a flag, add it to the flag nodes to update 2549 // list. 2550 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Flag) 2551 FlagResultNodesMatched.push_back(NodeToMatch); 2552 2553 // Update chain and flag uses. 2554 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched, 2555 InputFlag, FlagResultNodesMatched, false); 2556 2557 assert(NodeToMatch->use_empty() && 2558 "Didn't replace all uses of the node?"); 2559 2560 // FIXME: We just return here, which interacts correctly with SelectRoot 2561 // above. We should fix this to not return an SDNode* anymore. 2562 return 0; 2563 } 2564 } 2565 2566 // If the code reached this point, then the match failed. See if there is 2567 // another child to try in the current 'Scope', otherwise pop it until we 2568 // find a case to check. 2569 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n"); 2570 ++NumDAGIselRetries; 2571 while (1) { 2572 if (MatchScopes.empty()) { 2573 CannotYetSelect(NodeToMatch); 2574 return 0; 2575 } 2576 2577 // Restore the interpreter state back to the point where the scope was 2578 // formed. 2579 MatchScope &LastScope = MatchScopes.back(); 2580 RecordedNodes.resize(LastScope.NumRecordedNodes); 2581 NodeStack.clear(); 2582 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end()); 2583 N = NodeStack.back(); 2584 2585 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size()) 2586 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs); 2587 MatcherIndex = LastScope.FailIndex; 2588 2589 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n"); 2590 2591 InputChain = LastScope.InputChain; 2592 InputFlag = LastScope.InputFlag; 2593 if (!LastScope.HasChainNodesMatched) 2594 ChainNodesMatched.clear(); 2595 if (!LastScope.HasFlagResultNodesMatched) 2596 FlagResultNodesMatched.clear(); 2597 2598 // Check to see what the offset is at the new MatcherIndex. If it is zero 2599 // we have reached the end of this scope, otherwise we have another child 2600 // in the current scope to try. 2601 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2602 if (NumToSkip & 128) 2603 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2604 2605 // If we have another child in this scope to match, update FailIndex and 2606 // try it. 2607 if (NumToSkip != 0) { 2608 LastScope.FailIndex = MatcherIndex+NumToSkip; 2609 break; 2610 } 2611 2612 // End of this scope, pop it and try the next child in the containing 2613 // scope. 2614 MatchScopes.pop_back(); 2615 } 2616 } 2617} 2618 2619 2620 2621void SelectionDAGISel::CannotYetSelect(SDNode *N) { 2622 std::string msg; 2623 raw_string_ostream Msg(msg); 2624 Msg << "Cannot yet select: "; 2625 2626 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN && 2627 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN && 2628 N->getOpcode() != ISD::INTRINSIC_VOID) { 2629 N->printrFull(Msg, CurDAG); 2630 } else { 2631 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other; 2632 unsigned iid = 2633 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue(); 2634 if (iid < Intrinsic::num_intrinsics) 2635 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid); 2636 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo()) 2637 Msg << "target intrinsic %" << TII->getName(iid); 2638 else 2639 Msg << "unknown intrinsic #" << iid; 2640 } 2641 report_fatal_error(Msg.str()); 2642} 2643 2644char SelectionDAGISel::ID = 0; 2645