ARMMCTargetDesc.cpp revision 3e74d6fdd248e20a280f1dff3da9a6c689c2c4c3 
1//===-- ARMMCTargetDesc.cpp - ARM Target Descriptions -----------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file provides ARM specific target descriptions.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARMMCTargetDesc.h"
15#include "ARMMCAsmInfo.h"
16#include "ARMBaseInfo.h"
17#include "InstPrinter/ARMInstPrinter.h"
18#include "llvm/MC/MCCodeGenInfo.h"
19#include "llvm/MC/MCInstrAnalysis.h"
20#include "llvm/MC/MCInstrInfo.h"
21#include "llvm/MC/MCRegisterInfo.h"
22#include "llvm/MC/MCStreamer.h"
23#include "llvm/MC/MCSubtargetInfo.h"
24#include "llvm/Support/ErrorHandling.h"
25#include "llvm/Support/TargetRegistry.h"
26
27#define GET_REGINFO_MC_DESC
28#include "ARMGenRegisterInfo.inc"
29
30#define GET_INSTRINFO_MC_DESC
31#include "ARMGenInstrInfo.inc"
32
33#define GET_SUBTARGETINFO_MC_DESC
34#include "ARMGenSubtargetInfo.inc"
35
36using namespace llvm;
37
38std::string ARM_MC::ParseARMTriple(StringRef TT) {
39  // Set the boolean corresponding to the current target triple, or the default
40  // if one cannot be determined, to true.
41  unsigned Len = TT.size();
42  unsigned Idx = 0;
43
44  // FIXME: Enahnce Triple helper class to extract ARM version.
45  bool isThumb = false;
46  if (Len >= 5 && TT.substr(0, 4) == "armv")
47    Idx = 4;
48  else if (Len >= 6 && TT.substr(0, 5) == "thumb") {
49    isThumb = true;
50    if (Len >= 7 && TT[5] == 'v')
51      Idx = 6;
52  }
53
54  std::string ARMArchFeature;
55  if (Idx) {
56    unsigned SubVer = TT[Idx];
57    if (SubVer >= '7' && SubVer <= '9') {
58      if (Len >= Idx+2 && TT[Idx+1] == 'm') {
59        // v7m: FeatureNoARM, FeatureDB, FeatureHWDiv
60        ARMArchFeature = "+v7,+noarm,+db,+hwdiv";
61      } else if (Len >= Idx+3 && TT[Idx+1] == 'e'&& TT[Idx+2] == 'm') {
62        // v7em: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureDSPThumb2,
63        //       FeatureT2XtPk
64        ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+t2dsp,t2xtpk";
65      } else
66        // v7a: FeatureNEON, FeatureDB, FeatureDSPThumb2
67        ARMArchFeature = "+v7,+neon,+db,+t2dsp";
68    } else if (SubVer == '6') {
69      if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == '2')
70        ARMArchFeature = "+v6t2";
71      else
72        ARMArchFeature = "+v6";
73    } else if (SubVer == '5') {
74      if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == 'e')
75        ARMArchFeature = "+v5te";
76      else
77        ARMArchFeature = "+v5t";
78    } else if (SubVer == '4' && Len >= Idx+2 && TT[Idx+1] == 't')
79      ARMArchFeature = "+v4t";
80  }
81
82  if (isThumb) {
83    if (ARMArchFeature.empty())
84      ARMArchFeature = "+thumb-mode";
85    else
86      ARMArchFeature += ",+thumb-mode";
87  }
88
89  return ARMArchFeature;
90}
91
92MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(StringRef TT, StringRef CPU,
93                                                  StringRef FS) {
94  std::string ArchFS = ARM_MC::ParseARMTriple(TT);
95  if (!FS.empty()) {
96    if (!ArchFS.empty())
97      ArchFS = ArchFS + "," + FS.str();
98    else
99      ArchFS = FS;
100  }
101
102  MCSubtargetInfo *X = new MCSubtargetInfo();
103  InitARMMCSubtargetInfo(X, TT, CPU, ArchFS);
104  return X;
105}
106
107static MCInstrInfo *createARMMCInstrInfo() {
108  MCInstrInfo *X = new MCInstrInfo();
109  InitARMMCInstrInfo(X);
110  return X;
111}
112
113static MCRegisterInfo *createARMMCRegisterInfo(StringRef Triple) {
114  MCRegisterInfo *X = new MCRegisterInfo();
115  InitARMMCRegisterInfo(X, ARM::LR);
116  return X;
117}
118
119static MCAsmInfo *createARMMCAsmInfo(const Target &T, StringRef TT) {
120  Triple TheTriple(TT);
121
122  if (TheTriple.isOSDarwin())
123    return new ARMMCAsmInfoDarwin();
124
125  return new ARMELFMCAsmInfo();
126}
127
128static MCCodeGenInfo *createARMMCCodeGenInfo(StringRef TT, Reloc::Model RM,
129                                             CodeModel::Model CM) {
130  MCCodeGenInfo *X = new MCCodeGenInfo();
131  if (RM == Reloc::Default)
132    RM = Reloc::DynamicNoPIC;
133  X->InitMCCodeGenInfo(RM, CM);
134  return X;
135}
136
137// This is duplicated code. Refactor this.
138static MCStreamer *createMCStreamer(const Target &T, StringRef TT,
139                                    MCContext &Ctx, MCAsmBackend &MAB,
140                                    raw_ostream &OS,
141                                    MCCodeEmitter *Emitter,
142                                    bool RelaxAll,
143                                    bool NoExecStack) {
144  Triple TheTriple(TT);
145
146  if (TheTriple.isOSDarwin())
147    return createMachOStreamer(Ctx, MAB, OS, Emitter, RelaxAll);
148
149  if (TheTriple.isOSWindows()) {
150    llvm_unreachable("ARM does not support Windows COFF format");
151    return NULL;
152  }
153
154  return createELFStreamer(Ctx, MAB, OS, Emitter, RelaxAll, NoExecStack);
155}
156
157static MCInstPrinter *createARMMCInstPrinter(const Target &T,
158                                             unsigned SyntaxVariant,
159                                             const MCAsmInfo &MAI) {
160  if (SyntaxVariant == 0)
161    return new ARMInstPrinter(MAI);
162  return 0;
163}
164
165namespace {
166
167class ARMMCInstrAnalysis : public MCInstrAnalysis {
168public:
169  ARMMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
170
171  virtual bool isUnconditionalBranch(const MCInst &Inst) const {
172    // BCCs with the "always" predicate are unconditional branches.
173    if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
174      return true;
175    return MCInstrAnalysis::isUnconditionalBranch(Inst);
176  }
177
178  virtual bool isConditionalBranch(const MCInst &Inst) const {
179    // BCCs with the "always" predicate are unconditional branches.
180    if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
181      return false;
182    return MCInstrAnalysis::isConditionalBranch(Inst);
183  }
184
185  uint64_t evaluateBranch(const MCInst &Inst, uint64_t Addr,
186                          uint64_t Size) const {
187    // We only handle PCRel branches for now.
188    if (Info->get(Inst.getOpcode()).OpInfo[0].OperandType!=MCOI::OPERAND_PCREL)
189      return -1ULL;
190
191    int64_t Imm = Inst.getOperand(0).getImm();
192    // FIXME: This is not right for thumb.
193    return Addr+Imm+8; // In ARM mode the PC is always off by 8 bytes.
194  }
195};
196
197}
198
199static MCInstrAnalysis *createARMMCInstrAnalysis(const MCInstrInfo *Info) {
200  return new ARMMCInstrAnalysis(Info);
201}
202
203// Force static initialization.
204extern "C" void LLVMInitializeARMTargetMC() {
205  // Register the MC asm info.
206  RegisterMCAsmInfoFn A(TheARMTarget, createARMMCAsmInfo);
207  RegisterMCAsmInfoFn B(TheThumbTarget, createARMMCAsmInfo);
208
209  // Register the MC codegen info.
210  TargetRegistry::RegisterMCCodeGenInfo(TheARMTarget, createARMMCCodeGenInfo);
211  TargetRegistry::RegisterMCCodeGenInfo(TheThumbTarget, createARMMCCodeGenInfo);
212
213  // Register the MC instruction info.
214  TargetRegistry::RegisterMCInstrInfo(TheARMTarget, createARMMCInstrInfo);
215  TargetRegistry::RegisterMCInstrInfo(TheThumbTarget, createARMMCInstrInfo);
216
217  // Register the MC register info.
218  TargetRegistry::RegisterMCRegInfo(TheARMTarget, createARMMCRegisterInfo);
219  TargetRegistry::RegisterMCRegInfo(TheThumbTarget, createARMMCRegisterInfo);
220
221  // Register the MC subtarget info.
222  TargetRegistry::RegisterMCSubtargetInfo(TheARMTarget,
223                                          ARM_MC::createARMMCSubtargetInfo);
224  TargetRegistry::RegisterMCSubtargetInfo(TheThumbTarget,
225                                          ARM_MC::createARMMCSubtargetInfo);
226
227  // Register the MC instruction analyzer.
228  TargetRegistry::RegisterMCInstrAnalysis(TheARMTarget,
229                                          createARMMCInstrAnalysis);
230  TargetRegistry::RegisterMCInstrAnalysis(TheThumbTarget,
231                                          createARMMCInstrAnalysis);
232
233  // Register the MC Code Emitter
234  TargetRegistry::RegisterMCCodeEmitter(TheARMTarget, createARMMCCodeEmitter);
235  TargetRegistry::RegisterMCCodeEmitter(TheThumbTarget, createARMMCCodeEmitter);
236
237  // Register the asm backend.
238  TargetRegistry::RegisterMCAsmBackend(TheARMTarget, createARMAsmBackend);
239  TargetRegistry::RegisterMCAsmBackend(TheThumbTarget, createARMAsmBackend);
240
241  // Register the object streamer.
242  TargetRegistry::RegisterMCObjectStreamer(TheARMTarget, createMCStreamer);
243  TargetRegistry::RegisterMCObjectStreamer(TheThumbTarget, createMCStreamer);
244
245  // Register the MCInstPrinter.
246  TargetRegistry::RegisterMCInstPrinter(TheARMTarget, createARMMCInstPrinter);
247  TargetRegistry::RegisterMCInstPrinter(TheThumbTarget, createARMMCInstPrinter);
248}
249