HexagonVLIWPacketizer.cpp revision 7a2e472d527156165273a6c105ca7a93ff9e48f8 
1//===----- HexagonPacketizer.cpp - vliw packetizer ---------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This implements a simple VLIW packetizer using DFA. The packetizer works on
11// machine basic blocks. For each instruction I in BB, the packetizer consults
12// the DFA to see if machine resources are available to execute I. If so, the
13// packetizer checks if I depends on any instruction J in the current packet.
14// If no dependency is found, I is added to current packet and machine resource
15// is marked as taken. If any dependency is found, a target API call is made to
16// prune the dependence.
17//
18//===----------------------------------------------------------------------===//
19#define DEBUG_TYPE "packets"
20#include "llvm/CodeGen/DFAPacketizer.h"
21#include "llvm/CodeGen/Passes.h"
22#include "llvm/CodeGen/MachineDominators.h"
23#include "llvm/CodeGen/MachineFunctionPass.h"
24#include "llvm/CodeGen/MachineLoopInfo.h"
25#include "llvm/CodeGen/ScheduleDAG.h"
26#include "llvm/CodeGen/ScheduleDAGInstrs.h"
27#include "llvm/CodeGen/LatencyPriorityQueue.h"
28#include "llvm/CodeGen/SchedulerRegistry.h"
29#include "llvm/CodeGen/MachineFrameInfo.h"
30#include "llvm/CodeGen/MachineInstrBuilder.h"
31#include "llvm/CodeGen/MachineRegisterInfo.h"
32#include "llvm/CodeGen/MachineFunctionAnalysis.h"
33#include "llvm/CodeGen/ScheduleHazardRecognizer.h"
34#include "llvm/Target/TargetMachine.h"
35#include "llvm/Target/TargetInstrInfo.h"
36#include "llvm/Target/TargetRegisterInfo.h"
37#include "llvm/ADT/DenseMap.h"
38#include "llvm/ADT/Statistic.h"
39#include "llvm/Support/MathExtras.h"
40#include "llvm/MC/MCInstrItineraries.h"
41#include "llvm/Support/Compiler.h"
42#include "llvm/Support/CommandLine.h"
43#include "llvm/Support/Debug.h"
44#include "Hexagon.h"
45#include "HexagonTargetMachine.h"
46#include "HexagonRegisterInfo.h"
47#include "HexagonSubtarget.h"
48#include "HexagonMachineFunctionInfo.h"
49
50#include <map>
51
52using namespace llvm;
53
54namespace {
55  class HexagonPacketizer : public MachineFunctionPass {
56
57  public:
58    static char ID;
59    HexagonPacketizer() : MachineFunctionPass(ID) {}
60
61    void getAnalysisUsage(AnalysisUsage &AU) const {
62      AU.setPreservesCFG();
63      AU.addRequired<MachineDominatorTree>();
64      AU.addPreserved<MachineDominatorTree>();
65      AU.addRequired<MachineLoopInfo>();
66      AU.addPreserved<MachineLoopInfo>();
67      MachineFunctionPass::getAnalysisUsage(AU);
68    }
69
70    const char *getPassName() const {
71      return "Hexagon Packetizer";
72    }
73
74    bool runOnMachineFunction(MachineFunction &Fn);
75  };
76  char HexagonPacketizer::ID = 0;
77
78  class HexagonPacketizerList : public VLIWPacketizerList {
79
80  private:
81
82    // Has the instruction been promoted to a dot-new instruction.
83    bool PromotedToDotNew;
84
85    // Has the instruction been glued to allocframe.
86    bool GlueAllocframeStore;
87
88    // Has the feeder instruction been glued to new value jump.
89    bool GlueToNewValueJump;
90
91    // Check if there is a dependence between some instruction already in this
92    // packet and this instruction.
93    bool Dependence;
94
95    // Only check for dependence if there are resources available to
96    // schedule this instruction.
97    bool FoundSequentialDependence;
98
99  public:
100    // Ctor.
101    HexagonPacketizerList(MachineFunction &MF, MachineLoopInfo &MLI,
102                          MachineDominatorTree &MDT);
103
104    // initPacketizerState - initialize some internal flags.
105    void initPacketizerState();
106
107    // ignorePseudoInstruction - Ignore bundling of pseudo instructions.
108    bool ignorePseudoInstruction(MachineInstr *MI, MachineBasicBlock *MBB);
109
110    // isSoloInstruction - return true if instruction MI can not be packetized
111    // with any other instruction, which means that MI itself is a packet.
112    bool isSoloInstruction(MachineInstr *MI);
113
114    // isLegalToPacketizeTogether - Is it legal to packetize SUI and SUJ
115    // together.
116    bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ);
117
118    // isLegalToPruneDependencies - Is it legal to prune dependece between SUI
119    // and SUJ.
120    bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ);
121
122    MachineBasicBlock::iterator addToPacket(MachineInstr *MI);
123  private:
124    bool IsCallDependent(MachineInstr* MI, SDep::Kind DepType, unsigned DepReg);
125    bool PromoteToDotNew(MachineInstr* MI, SDep::Kind DepType,
126                    MachineBasicBlock::iterator &MII,
127                    const TargetRegisterClass* RC);
128    bool CanPromoteToDotNew(MachineInstr* MI, SUnit* PacketSU,
129                    unsigned DepReg,
130                    std::map <MachineInstr*, SUnit*> MIToSUnit,
131                    MachineBasicBlock::iterator &MII,
132                    const TargetRegisterClass* RC);
133    bool CanPromoteToNewValue(MachineInstr* MI, SUnit* PacketSU,
134                    unsigned DepReg,
135                    std::map <MachineInstr*, SUnit*> MIToSUnit,
136                    MachineBasicBlock::iterator &MII);
137    bool CanPromoteToNewValueStore(MachineInstr* MI, MachineInstr* PacketMI,
138                    unsigned DepReg,
139                    std::map <MachineInstr*, SUnit*> MIToSUnit);
140    bool DemoteToDotOld(MachineInstr* MI);
141    bool ArePredicatesComplements(MachineInstr* MI1, MachineInstr* MI2,
142                    std::map <MachineInstr*, SUnit*> MIToSUnit);
143    bool RestrictingDepExistInPacket(MachineInstr*,
144                    unsigned, std::map <MachineInstr*, SUnit*>);
145    bool isNewifiable(MachineInstr* MI);
146    bool isCondInst(MachineInstr* MI);
147    bool IsNewifyStore (MachineInstr* MI);
148    bool tryAllocateResourcesForConstExt(MachineInstr* MI);
149    bool canReserveResourcesForConstExt(MachineInstr *MI);
150    void reserveResourcesForConstExt(MachineInstr* MI);
151    bool isNewValueInst(MachineInstr* MI);
152    bool isDotNewInst(MachineInstr* MI);
153  };
154}
155
156// HexagonPacketizerList Ctor.
157HexagonPacketizerList::HexagonPacketizerList(
158  MachineFunction &MF, MachineLoopInfo &MLI,MachineDominatorTree &MDT)
159  : VLIWPacketizerList(MF, MLI, MDT, true){
160}
161
162bool HexagonPacketizer::runOnMachineFunction(MachineFunction &Fn) {
163  const TargetInstrInfo *TII = Fn.getTarget().getInstrInfo();
164  MachineLoopInfo &MLI = getAnalysis<MachineLoopInfo>();
165  MachineDominatorTree &MDT = getAnalysis<MachineDominatorTree>();
166
167  // Instantiate the packetizer.
168  HexagonPacketizerList Packetizer(Fn, MLI, MDT);
169
170  // DFA state table should not be empty.
171  assert(Packetizer.getResourceTracker() && "Empty DFA table!");
172
173  //
174  // Loop over all basic blocks and remove KILL pseudo-instructions
175  // These instructions confuse the dependence analysis. Consider:
176  // D0 = ...   (Insn 0)
177  // R0 = KILL R0, D0 (Insn 1)
178  // R0 = ... (Insn 2)
179  // Here, Insn 1 will result in the dependence graph not emitting an output
180  // dependence between Insn 0 and Insn 2. This can lead to incorrect
181  // packetization
182  //
183  for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
184       MBB != MBBe; ++MBB) {
185    MachineBasicBlock::iterator End = MBB->end();
186    MachineBasicBlock::iterator MI = MBB->begin();
187    while (MI != End) {
188      if (MI->isKill()) {
189        MachineBasicBlock::iterator DeleteMI = MI;
190        ++MI;
191        MBB->erase(DeleteMI);
192        End = MBB->end();
193        continue;
194      }
195      ++MI;
196    }
197  }
198
199  // Loop over all of the basic blocks.
200  for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
201       MBB != MBBe; ++MBB) {
202    // Find scheduling regions and schedule / packetize each region.
203    unsigned RemainingCount = MBB->size();
204    for(MachineBasicBlock::iterator RegionEnd = MBB->end();
205        RegionEnd != MBB->begin();) {
206      // The next region starts above the previous region. Look backward in the
207      // instruction stream until we find the nearest boundary.
208      MachineBasicBlock::iterator I = RegionEnd;
209      for(;I != MBB->begin(); --I, --RemainingCount) {
210        if (TII->isSchedulingBoundary(llvm::prior(I), MBB, Fn))
211          break;
212      }
213      I = MBB->begin();
214
215      // Skip empty scheduling regions.
216      if (I == RegionEnd) {
217        RegionEnd = llvm::prior(RegionEnd);
218        --RemainingCount;
219        continue;
220      }
221      // Skip regions with one instruction.
222      if (I == llvm::prior(RegionEnd)) {
223        RegionEnd = llvm::prior(RegionEnd);
224        continue;
225      }
226
227      Packetizer.PacketizeMIs(MBB, I, RegionEnd);
228      RegionEnd = I;
229    }
230  }
231
232  return true;
233}
234
235
236static bool IsIndirectCall(MachineInstr* MI) {
237  return ((MI->getOpcode() == Hexagon::CALLR) ||
238          (MI->getOpcode() == Hexagon::CALLRv3));
239}
240
241// Reserve resources for constant extender. Trigure an assertion if
242// reservation fail.
243void HexagonPacketizerList::reserveResourcesForConstExt(MachineInstr* MI) {
244  const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
245  MachineInstr *PseudoMI = MI->getParent()->getParent()->CreateMachineInstr(
246                                  QII->get(Hexagon::IMMEXT), MI->getDebugLoc());
247
248  if (ResourceTracker->canReserveResources(PseudoMI)) {
249    ResourceTracker->reserveResources(PseudoMI);
250    MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);
251  } else {
252    MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);
253    llvm_unreachable("can not reserve resources for constant extender.");
254  }
255  return;
256}
257
258bool HexagonPacketizerList::canReserveResourcesForConstExt(MachineInstr *MI) {
259  const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
260  assert(QII->isExtended(MI) &&
261         "Should only be called for constant extended instructions");
262  MachineFunction *MF = MI->getParent()->getParent();
263  MachineInstr *PseudoMI = MF->CreateMachineInstr(QII->get(Hexagon::IMMEXT),
264                                                  MI->getDebugLoc());
265  bool CanReserve = ResourceTracker->canReserveResources(PseudoMI);
266  MF->DeleteMachineInstr(PseudoMI);
267  return CanReserve;
268}
269
270// Allocate resources (i.e. 4 bytes) for constant extender. If succeed, return
271// true, otherwise, return false.
272bool HexagonPacketizerList::tryAllocateResourcesForConstExt(MachineInstr* MI) {
273  const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
274  MachineInstr *PseudoMI = MI->getParent()->getParent()->CreateMachineInstr(
275                                  QII->get(Hexagon::IMMEXT), MI->getDebugLoc());
276
277  if (ResourceTracker->canReserveResources(PseudoMI)) {
278    ResourceTracker->reserveResources(PseudoMI);
279    MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);
280    return true;
281  } else {
282    MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);
283    return false;
284  }
285}
286
287
288bool HexagonPacketizerList::IsCallDependent(MachineInstr* MI,
289                                          SDep::Kind DepType,
290                                          unsigned DepReg) {
291
292  const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
293  const HexagonRegisterInfo* QRI = (const HexagonRegisterInfo *) TM.getRegisterInfo();
294
295  // Check for lr dependence
296  if (DepReg == QRI->getRARegister()) {
297    return true;
298  }
299
300  if (QII->isDeallocRet(MI)) {
301    if (DepReg == QRI->getFrameRegister() ||
302        DepReg == QRI->getStackRegister())
303      return true;
304  }
305
306  // Check if this is a predicate dependence
307  const TargetRegisterClass* RC = QRI->getMinimalPhysRegClass(DepReg);
308  if (RC == Hexagon::PredRegsRegisterClass) {
309    return true;
310  }
311
312  //
313  // Lastly check for an operand used in an indirect call
314  // If we had an attribute for checking if an instruction is an indirect call,
315  // then we could have avoided this relatively brittle implementation of
316  // IsIndirectCall()
317  //
318  // Assumes that the first operand of the CALLr is the function address
319  //
320  if (IsIndirectCall(MI) && (DepType == SDep::Data)) {
321    MachineOperand MO = MI->getOperand(0);
322    if (MO.isReg() && MO.isUse() && (MO.getReg() == DepReg)) {
323      return true;
324    }
325  }
326
327  return false;
328}
329
330static bool IsRegDependence(const SDep::Kind DepType) {
331  return (DepType == SDep::Data || DepType == SDep::Anti ||
332          DepType == SDep::Output);
333}
334
335static bool IsDirectJump(MachineInstr* MI) {
336  return (MI->getOpcode() == Hexagon::JMP);
337}
338
339static bool IsSchedBarrier(MachineInstr* MI) {
340  switch (MI->getOpcode()) {
341  case Hexagon::BARRIER:
342    return true;
343  }
344  return false;
345}
346
347static bool IsControlFlow(MachineInstr* MI) {
348  return (MI->getDesc().isTerminator() || MI->getDesc().isCall());
349}
350
351bool HexagonPacketizerList::isNewValueInst(MachineInstr* MI) {
352  const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
353  if (QII->isNewValueJump(MI))
354    return true;
355
356  if (QII->isNewValueStore(MI))
357    return true;
358
359  return false;
360}
361
362// Function returns true if an instruction can be promoted to the new-value
363// store. It will always return false for v2 and v3.
364// It lists all the conditional and unconditional stores that can be promoted
365// to the new-value stores.
366
367bool HexagonPacketizerList::IsNewifyStore (MachineInstr* MI) {
368  const HexagonRegisterInfo* QRI = (const HexagonRegisterInfo *) TM.getRegisterInfo();
369  switch (MI->getOpcode())
370  {
371    // store byte
372    case Hexagon::STrib:
373    case Hexagon::STrib_indexed:
374    case Hexagon::STrib_indexed_shl_V4:
375    case Hexagon::STrib_shl_V4:
376    case Hexagon::STrib_GP_V4:
377    case Hexagon::STb_GP_V4:
378    case Hexagon::POST_STbri:
379    case Hexagon::STrib_cPt:
380    case Hexagon::STrib_cdnPt_V4:
381    case Hexagon::STrib_cNotPt:
382    case Hexagon::STrib_cdnNotPt_V4:
383    case Hexagon::STrib_indexed_cPt:
384    case Hexagon::STrib_indexed_cdnPt_V4:
385    case Hexagon::STrib_indexed_cNotPt:
386    case Hexagon::STrib_indexed_cdnNotPt_V4:
387    case Hexagon::STrib_indexed_shl_cPt_V4:
388    case Hexagon::STrib_indexed_shl_cdnPt_V4:
389    case Hexagon::STrib_indexed_shl_cNotPt_V4:
390    case Hexagon::STrib_indexed_shl_cdnNotPt_V4:
391    case Hexagon::POST_STbri_cPt:
392    case Hexagon::POST_STbri_cdnPt_V4:
393    case Hexagon::POST_STbri_cNotPt:
394    case Hexagon::POST_STbri_cdnNotPt_V4:
395    case Hexagon::STb_GP_cPt_V4:
396    case Hexagon::STb_GP_cNotPt_V4:
397    case Hexagon::STb_GP_cdnPt_V4:
398    case Hexagon::STb_GP_cdnNotPt_V4:
399    case Hexagon::STrib_GP_cPt_V4:
400    case Hexagon::STrib_GP_cNotPt_V4:
401    case Hexagon::STrib_GP_cdnPt_V4:
402    case Hexagon::STrib_GP_cdnNotPt_V4:
403
404    // store halfword
405    case Hexagon::STrih:
406    case Hexagon::STrih_indexed:
407    case Hexagon::STrih_indexed_shl_V4:
408    case Hexagon::STrih_shl_V4:
409    case Hexagon::STrih_GP_V4:
410    case Hexagon::STh_GP_V4:
411    case Hexagon::POST_SThri:
412    case Hexagon::STrih_cPt:
413    case Hexagon::STrih_cdnPt_V4:
414    case Hexagon::STrih_cNotPt:
415    case Hexagon::STrih_cdnNotPt_V4:
416    case Hexagon::STrih_indexed_cPt:
417    case Hexagon::STrih_indexed_cdnPt_V4:
418    case Hexagon::STrih_indexed_cNotPt:
419    case Hexagon::STrih_indexed_cdnNotPt_V4:
420    case Hexagon::STrih_indexed_shl_cPt_V4:
421    case Hexagon::STrih_indexed_shl_cdnPt_V4:
422    case Hexagon::STrih_indexed_shl_cNotPt_V4:
423    case Hexagon::STrih_indexed_shl_cdnNotPt_V4:
424    case Hexagon::POST_SThri_cPt:
425    case Hexagon::POST_SThri_cdnPt_V4:
426    case Hexagon::POST_SThri_cNotPt:
427    case Hexagon::POST_SThri_cdnNotPt_V4:
428    case Hexagon::STh_GP_cPt_V4:
429    case Hexagon::STh_GP_cNotPt_V4:
430    case Hexagon::STh_GP_cdnPt_V4:
431    case Hexagon::STh_GP_cdnNotPt_V4:
432    case Hexagon::STrih_GP_cPt_V4:
433    case Hexagon::STrih_GP_cNotPt_V4:
434    case Hexagon::STrih_GP_cdnPt_V4:
435    case Hexagon::STrih_GP_cdnNotPt_V4:
436
437    // store word
438    case Hexagon::STriw:
439    case Hexagon::STriw_indexed:
440    case Hexagon::STriw_indexed_shl_V4:
441    case Hexagon::STriw_shl_V4:
442    case Hexagon::STriw_GP_V4:
443    case Hexagon::STw_GP_V4:
444    case Hexagon::POST_STwri:
445    case Hexagon::STriw_cPt:
446    case Hexagon::STriw_cdnPt_V4:
447    case Hexagon::STriw_cNotPt:
448    case Hexagon::STriw_cdnNotPt_V4:
449    case Hexagon::STriw_indexed_cPt:
450    case Hexagon::STriw_indexed_cdnPt_V4:
451    case Hexagon::STriw_indexed_cNotPt:
452    case Hexagon::STriw_indexed_cdnNotPt_V4:
453    case Hexagon::STriw_indexed_shl_cPt_V4:
454    case Hexagon::STriw_indexed_shl_cdnPt_V4:
455    case Hexagon::STriw_indexed_shl_cNotPt_V4:
456    case Hexagon::STriw_indexed_shl_cdnNotPt_V4:
457    case Hexagon::POST_STwri_cPt:
458    case Hexagon::POST_STwri_cdnPt_V4:
459    case Hexagon::POST_STwri_cNotPt:
460    case Hexagon::POST_STwri_cdnNotPt_V4:
461    case Hexagon::STw_GP_cPt_V4:
462    case Hexagon::STw_GP_cNotPt_V4:
463    case Hexagon::STw_GP_cdnPt_V4:
464    case Hexagon::STw_GP_cdnNotPt_V4:
465    case Hexagon::STriw_GP_cPt_V4:
466    case Hexagon::STriw_GP_cNotPt_V4:
467    case Hexagon::STriw_GP_cdnPt_V4:
468    case Hexagon::STriw_GP_cdnNotPt_V4:
469        return QRI->Subtarget.hasV4TOps();
470  }
471  return false;
472}
473
474static bool IsLoopN(MachineInstr *MI) {
475  return (MI->getOpcode() == Hexagon::LOOP0_i ||
476          MI->getOpcode() == Hexagon::LOOP0_r);
477}
478
479/// DoesModifyCalleeSavedReg - Returns true if the instruction modifies a
480/// callee-saved register.
481static bool DoesModifyCalleeSavedReg(MachineInstr *MI,
482                                     const TargetRegisterInfo *TRI) {
483  for (const uint16_t *CSR = TRI->getCalleeSavedRegs(); *CSR; ++CSR) {
484    unsigned CalleeSavedReg = *CSR;
485    if (MI->modifiesRegister(CalleeSavedReg, TRI))
486      return true;
487  }
488  return false;
489}
490
491// Return the new value instruction for a given store.
492static int GetDotNewOp(const int opc) {
493  switch (opc) {
494  default: llvm_unreachable("Unknown .new type");
495
496  // store new value byte
497  case Hexagon::STrib:
498    return Hexagon::STrib_nv_V4;
499
500  case Hexagon::STrib_indexed:
501    return Hexagon::STrib_indexed_nv_V4;
502
503  case Hexagon::STrib_indexed_shl_V4:
504    return Hexagon::STrib_indexed_shl_nv_V4;
505
506  case Hexagon::STrib_shl_V4:
507    return Hexagon::STrib_shl_nv_V4;
508
509  case Hexagon::STrib_GP_V4:
510    return Hexagon::STrib_GP_nv_V4;
511
512  case Hexagon::STb_GP_V4:
513    return Hexagon::STb_GP_nv_V4;
514
515  case Hexagon::POST_STbri:
516    return Hexagon::POST_STbri_nv_V4;
517
518  case Hexagon::STrib_cPt:
519    return Hexagon::STrib_cPt_nv_V4;
520
521  case Hexagon::STrib_cdnPt_V4:
522    return Hexagon::STrib_cdnPt_nv_V4;
523
524  case Hexagon::STrib_cNotPt:
525    return Hexagon::STrib_cNotPt_nv_V4;
526
527  case Hexagon::STrib_cdnNotPt_V4:
528    return Hexagon::STrib_cdnNotPt_nv_V4;
529
530  case Hexagon::STrib_indexed_cPt:
531    return Hexagon::STrib_indexed_cPt_nv_V4;
532
533  case Hexagon::STrib_indexed_cdnPt_V4:
534    return Hexagon::STrib_indexed_cdnPt_nv_V4;
535
536  case Hexagon::STrib_indexed_cNotPt:
537    return Hexagon::STrib_indexed_cNotPt_nv_V4;
538
539  case Hexagon::STrib_indexed_cdnNotPt_V4:
540    return Hexagon::STrib_indexed_cdnNotPt_nv_V4;
541
542  case Hexagon::STrib_indexed_shl_cPt_V4:
543    return Hexagon::STrib_indexed_shl_cPt_nv_V4;
544
545  case Hexagon::STrib_indexed_shl_cdnPt_V4:
546    return Hexagon::STrib_indexed_shl_cdnPt_nv_V4;
547
548  case Hexagon::STrib_indexed_shl_cNotPt_V4:
549    return Hexagon::STrib_indexed_shl_cNotPt_nv_V4;
550
551  case Hexagon::STrib_indexed_shl_cdnNotPt_V4:
552    return Hexagon::STrib_indexed_shl_cdnNotPt_nv_V4;
553
554  case Hexagon::POST_STbri_cPt:
555    return Hexagon::POST_STbri_cPt_nv_V4;
556
557  case Hexagon::POST_STbri_cdnPt_V4:
558    return Hexagon::POST_STbri_cdnPt_nv_V4;
559
560  case Hexagon::POST_STbri_cNotPt:
561    return Hexagon::POST_STbri_cNotPt_nv_V4;
562
563  case Hexagon::POST_STbri_cdnNotPt_V4:
564    return Hexagon::POST_STbri_cdnNotPt_nv_V4;
565
566  case Hexagon::STb_GP_cPt_V4:
567    return Hexagon::STb_GP_cPt_nv_V4;
568
569  case Hexagon::STb_GP_cNotPt_V4:
570    return Hexagon::STb_GP_cNotPt_nv_V4;
571
572  case Hexagon::STb_GP_cdnPt_V4:
573    return Hexagon::STb_GP_cdnPt_nv_V4;
574
575  case Hexagon::STb_GP_cdnNotPt_V4:
576    return Hexagon::STb_GP_cdnNotPt_nv_V4;
577
578  case Hexagon::STrib_GP_cPt_V4:
579    return Hexagon::STrib_GP_cPt_nv_V4;
580
581  case Hexagon::STrib_GP_cNotPt_V4:
582    return Hexagon::STrib_GP_cNotPt_nv_V4;
583
584  case Hexagon::STrib_GP_cdnPt_V4:
585    return Hexagon::STrib_GP_cdnPt_nv_V4;
586
587  case Hexagon::STrib_GP_cdnNotPt_V4:
588    return Hexagon::STrib_GP_cdnNotPt_nv_V4;
589
590  // store new value halfword
591  case Hexagon::STrih:
592    return Hexagon::STrih_nv_V4;
593
594  case Hexagon::STrih_indexed:
595    return Hexagon::STrih_indexed_nv_V4;
596
597  case Hexagon::STrih_indexed_shl_V4:
598    return Hexagon::STrih_indexed_shl_nv_V4;
599
600  case Hexagon::STrih_shl_V4:
601    return Hexagon::STrih_shl_nv_V4;
602
603  case Hexagon::STrih_GP_V4:
604    return Hexagon::STrih_GP_nv_V4;
605
606  case Hexagon::STh_GP_V4:
607    return Hexagon::STh_GP_nv_V4;
608
609  case Hexagon::POST_SThri:
610    return Hexagon::POST_SThri_nv_V4;
611
612  case Hexagon::STrih_cPt:
613    return Hexagon::STrih_cPt_nv_V4;
614
615  case Hexagon::STrih_cdnPt_V4:
616    return Hexagon::STrih_cdnPt_nv_V4;
617
618  case Hexagon::STrih_cNotPt:
619    return Hexagon::STrih_cNotPt_nv_V4;
620
621  case Hexagon::STrih_cdnNotPt_V4:
622    return Hexagon::STrih_cdnNotPt_nv_V4;
623
624  case Hexagon::STrih_indexed_cPt:
625    return Hexagon::STrih_indexed_cPt_nv_V4;
626
627  case Hexagon::STrih_indexed_cdnPt_V4:
628    return Hexagon::STrih_indexed_cdnPt_nv_V4;
629
630  case Hexagon::STrih_indexed_cNotPt:
631    return Hexagon::STrih_indexed_cNotPt_nv_V4;
632
633  case Hexagon::STrih_indexed_cdnNotPt_V4:
634    return Hexagon::STrih_indexed_cdnNotPt_nv_V4;
635
636  case Hexagon::STrih_indexed_shl_cPt_V4:
637    return Hexagon::STrih_indexed_shl_cPt_nv_V4;
638
639  case Hexagon::STrih_indexed_shl_cdnPt_V4:
640    return Hexagon::STrih_indexed_shl_cdnPt_nv_V4;
641
642  case Hexagon::STrih_indexed_shl_cNotPt_V4:
643    return Hexagon::STrih_indexed_shl_cNotPt_nv_V4;
644
645  case Hexagon::STrih_indexed_shl_cdnNotPt_V4:
646    return Hexagon::STrih_indexed_shl_cdnNotPt_nv_V4;
647
648  case Hexagon::POST_SThri_cPt:
649    return Hexagon::POST_SThri_cPt_nv_V4;
650
651  case Hexagon::POST_SThri_cdnPt_V4:
652    return Hexagon::POST_SThri_cdnPt_nv_V4;
653
654  case Hexagon::POST_SThri_cNotPt:
655    return Hexagon::POST_SThri_cNotPt_nv_V4;
656
657  case Hexagon::POST_SThri_cdnNotPt_V4:
658    return Hexagon::POST_SThri_cdnNotPt_nv_V4;
659
660  case Hexagon::STh_GP_cPt_V4:
661    return Hexagon::STh_GP_cPt_nv_V4;
662
663  case Hexagon::STh_GP_cNotPt_V4:
664    return Hexagon::STh_GP_cNotPt_nv_V4;
665
666  case Hexagon::STh_GP_cdnPt_V4:
667    return Hexagon::STh_GP_cdnPt_nv_V4;
668
669  case Hexagon::STh_GP_cdnNotPt_V4:
670    return Hexagon::STh_GP_cdnNotPt_nv_V4;
671
672  case Hexagon::STrih_GP_cPt_V4:
673    return Hexagon::STrih_GP_cPt_nv_V4;
674
675  case Hexagon::STrih_GP_cNotPt_V4:
676    return Hexagon::STrih_GP_cNotPt_nv_V4;
677
678  case Hexagon::STrih_GP_cdnPt_V4:
679    return Hexagon::STrih_GP_cdnPt_nv_V4;
680
681  case Hexagon::STrih_GP_cdnNotPt_V4:
682    return Hexagon::STrih_GP_cdnNotPt_nv_V4;
683
684  // store new value word
685  case Hexagon::STriw:
686    return Hexagon::STriw_nv_V4;
687
688  case Hexagon::STriw_indexed:
689    return Hexagon::STriw_indexed_nv_V4;
690
691  case Hexagon::STriw_indexed_shl_V4:
692    return Hexagon::STriw_indexed_shl_nv_V4;
693
694  case Hexagon::STriw_shl_V4:
695    return Hexagon::STriw_shl_nv_V4;
696
697  case Hexagon::STriw_GP_V4:
698    return Hexagon::STriw_GP_nv_V4;
699
700  case Hexagon::STw_GP_V4:
701    return Hexagon::STw_GP_nv_V4;
702
703  case Hexagon::POST_STwri:
704    return Hexagon::POST_STwri_nv_V4;
705
706  case Hexagon::STriw_cPt:
707    return Hexagon::STriw_cPt_nv_V4;
708
709  case Hexagon::STriw_cdnPt_V4:
710    return Hexagon::STriw_cdnPt_nv_V4;
711
712  case Hexagon::STriw_cNotPt:
713    return Hexagon::STriw_cNotPt_nv_V4;
714
715  case Hexagon::STriw_cdnNotPt_V4:
716    return Hexagon::STriw_cdnNotPt_nv_V4;
717
718  case Hexagon::STriw_indexed_cPt:
719    return Hexagon::STriw_indexed_cPt_nv_V4;
720
721  case Hexagon::STriw_indexed_cdnPt_V4:
722    return Hexagon::STriw_indexed_cdnPt_nv_V4;
723
724  case Hexagon::STriw_indexed_cNotPt:
725    return Hexagon::STriw_indexed_cNotPt_nv_V4;
726
727  case Hexagon::STriw_indexed_cdnNotPt_V4:
728    return Hexagon::STriw_indexed_cdnNotPt_nv_V4;
729
730  case Hexagon::STriw_indexed_shl_cPt_V4:
731    return Hexagon::STriw_indexed_shl_cPt_nv_V4;
732
733  case Hexagon::STriw_indexed_shl_cdnPt_V4:
734    return Hexagon::STriw_indexed_shl_cdnPt_nv_V4;
735
736  case Hexagon::STriw_indexed_shl_cNotPt_V4:
737    return Hexagon::STriw_indexed_shl_cNotPt_nv_V4;
738
739  case Hexagon::STriw_indexed_shl_cdnNotPt_V4:
740    return Hexagon::STriw_indexed_shl_cdnNotPt_nv_V4;
741
742  case Hexagon::POST_STwri_cPt:
743    return Hexagon::POST_STwri_cPt_nv_V4;
744
745  case Hexagon::POST_STwri_cdnPt_V4:
746    return Hexagon::POST_STwri_cdnPt_nv_V4;
747
748  case Hexagon::POST_STwri_cNotPt:
749    return Hexagon::POST_STwri_cNotPt_nv_V4;
750
751  case Hexagon::POST_STwri_cdnNotPt_V4:
752    return Hexagon::POST_STwri_cdnNotPt_nv_V4;
753
754  case Hexagon::STw_GP_cPt_V4:
755    return Hexagon::STw_GP_cPt_nv_V4;
756
757  case Hexagon::STw_GP_cNotPt_V4:
758    return Hexagon::STw_GP_cNotPt_nv_V4;
759
760  case Hexagon::STw_GP_cdnPt_V4:
761    return Hexagon::STw_GP_cdnPt_nv_V4;
762
763  case Hexagon::STw_GP_cdnNotPt_V4:
764    return Hexagon::STw_GP_cdnNotPt_nv_V4;
765
766  case Hexagon::STriw_GP_cPt_V4:
767    return Hexagon::STriw_GP_cPt_nv_V4;
768
769  case Hexagon::STriw_GP_cNotPt_V4:
770    return Hexagon::STriw_GP_cNotPt_nv_V4;
771
772  case Hexagon::STriw_GP_cdnPt_V4:
773    return Hexagon::STriw_GP_cdnPt_nv_V4;
774
775  case Hexagon::STriw_GP_cdnNotPt_V4:
776    return Hexagon::STriw_GP_cdnNotPt_nv_V4;
777  }
778}
779
780// Return .new predicate version for an instruction
781static int GetDotNewPredOp(const int opc) {
782  switch (opc) {
783  default: llvm_unreachable("Unknown .new type");
784
785  // Conditional stores
786  // Store byte conditionally
787  case Hexagon::STrib_cPt :
788    return Hexagon::STrib_cdnPt_V4;
789
790  case Hexagon::STrib_cNotPt :
791    return Hexagon::STrib_cdnNotPt_V4;
792
793  case Hexagon::STrib_indexed_cPt :
794    return Hexagon::STrib_indexed_cdnPt_V4;
795
796  case Hexagon::STrib_indexed_cNotPt :
797    return Hexagon::STrib_indexed_cdnNotPt_V4;
798
799  case Hexagon::STrib_imm_cPt_V4 :
800    return Hexagon::STrib_imm_cdnPt_V4;
801
802  case Hexagon::STrib_imm_cNotPt_V4 :
803    return Hexagon::STrib_imm_cdnNotPt_V4;
804
805  case Hexagon::POST_STbri_cPt :
806    return Hexagon::POST_STbri_cdnPt_V4;
807
808  case Hexagon::POST_STbri_cNotPt :
809    return Hexagon::POST_STbri_cdnNotPt_V4;
810
811  case Hexagon::STrib_indexed_shl_cPt_V4 :
812    return Hexagon::STrib_indexed_shl_cdnPt_V4;
813
814  case Hexagon::STrib_indexed_shl_cNotPt_V4 :
815    return Hexagon::STrib_indexed_shl_cdnNotPt_V4;
816
817  case Hexagon::STb_GP_cPt_V4 :
818    return Hexagon::STb_GP_cdnPt_V4;
819
820  case Hexagon::STb_GP_cNotPt_V4 :
821    return Hexagon::STb_GP_cdnNotPt_V4;
822
823  case Hexagon::STrib_GP_cPt_V4 :
824    return Hexagon::STrib_GP_cdnPt_V4;
825
826  case Hexagon::STrib_GP_cNotPt_V4 :
827    return Hexagon::STrib_GP_cdnNotPt_V4;
828
829  // Store doubleword conditionally
830  case Hexagon::STrid_cPt :
831    return Hexagon::STrid_cdnPt_V4;
832
833  case Hexagon::STrid_cNotPt :
834    return Hexagon::STrid_cdnNotPt_V4;
835
836  case Hexagon::STrid_indexed_cPt :
837    return Hexagon::STrid_indexed_cdnPt_V4;
838
839  case Hexagon::STrid_indexed_cNotPt :
840    return Hexagon::STrid_indexed_cdnNotPt_V4;
841
842  case Hexagon::STrid_indexed_shl_cPt_V4 :
843    return Hexagon::STrid_indexed_shl_cdnPt_V4;
844
845  case Hexagon::STrid_indexed_shl_cNotPt_V4 :
846    return Hexagon::STrid_indexed_shl_cdnNotPt_V4;
847
848  case Hexagon::POST_STdri_cPt :
849    return Hexagon::POST_STdri_cdnPt_V4;
850
851  case Hexagon::POST_STdri_cNotPt :
852    return Hexagon::POST_STdri_cdnNotPt_V4;
853
854  case Hexagon::STd_GP_cPt_V4 :
855    return Hexagon::STd_GP_cdnPt_V4;
856
857  case Hexagon::STd_GP_cNotPt_V4 :
858    return Hexagon::STd_GP_cdnNotPt_V4;
859
860  case Hexagon::STrid_GP_cPt_V4 :
861    return Hexagon::STrid_GP_cdnPt_V4;
862
863  case Hexagon::STrid_GP_cNotPt_V4 :
864    return Hexagon::STrid_GP_cdnNotPt_V4;
865
866  // Store halfword conditionally
867  case Hexagon::STrih_cPt :
868    return Hexagon::STrih_cdnPt_V4;
869
870  case Hexagon::STrih_cNotPt :
871    return Hexagon::STrih_cdnNotPt_V4;
872
873  case Hexagon::STrih_indexed_cPt :
874    return Hexagon::STrih_indexed_cdnPt_V4;
875
876  case Hexagon::STrih_indexed_cNotPt :
877    return Hexagon::STrih_indexed_cdnNotPt_V4;
878
879  case Hexagon::STrih_imm_cPt_V4 :
880    return Hexagon::STrih_imm_cdnPt_V4;
881
882  case Hexagon::STrih_imm_cNotPt_V4 :
883    return Hexagon::STrih_imm_cdnNotPt_V4;
884
885  case Hexagon::STrih_indexed_shl_cPt_V4 :
886    return Hexagon::STrih_indexed_shl_cdnPt_V4;
887
888  case Hexagon::STrih_indexed_shl_cNotPt_V4 :
889    return Hexagon::STrih_indexed_shl_cdnNotPt_V4;
890
891  case Hexagon::POST_SThri_cPt :
892    return Hexagon::POST_SThri_cdnPt_V4;
893
894  case Hexagon::POST_SThri_cNotPt :
895    return Hexagon::POST_SThri_cdnNotPt_V4;
896
897  case Hexagon::STh_GP_cPt_V4 :
898    return Hexagon::STh_GP_cdnPt_V4;
899
900  case Hexagon::STh_GP_cNotPt_V4 :
901    return Hexagon::STh_GP_cdnNotPt_V4;
902
903  case Hexagon::STrih_GP_cPt_V4 :
904    return Hexagon::STrih_GP_cdnPt_V4;
905
906  case Hexagon::STrih_GP_cNotPt_V4 :
907    return Hexagon::STrih_GP_cdnNotPt_V4;
908
909  // Store word conditionally
910  case Hexagon::STriw_cPt :
911    return Hexagon::STriw_cdnPt_V4;
912
913  case Hexagon::STriw_cNotPt :
914    return Hexagon::STriw_cdnNotPt_V4;
915
916  case Hexagon::STriw_indexed_cPt :
917    return Hexagon::STriw_indexed_cdnPt_V4;
918
919  case Hexagon::STriw_indexed_cNotPt :
920    return Hexagon::STriw_indexed_cdnNotPt_V4;
921
922  case Hexagon::STriw_imm_cPt_V4 :
923    return Hexagon::STriw_imm_cdnPt_V4;
924
925  case Hexagon::STriw_imm_cNotPt_V4 :
926    return Hexagon::STriw_imm_cdnNotPt_V4;
927
928  case Hexagon::STriw_indexed_shl_cPt_V4 :
929    return Hexagon::STriw_indexed_shl_cdnPt_V4;
930
931  case Hexagon::STriw_indexed_shl_cNotPt_V4 :
932    return Hexagon::STriw_indexed_shl_cdnNotPt_V4;
933
934  case Hexagon::POST_STwri_cPt :
935    return Hexagon::POST_STwri_cdnPt_V4;
936
937  case Hexagon::POST_STwri_cNotPt :
938    return Hexagon::POST_STwri_cdnNotPt_V4;
939
940  case Hexagon::STw_GP_cPt_V4 :
941    return Hexagon::STw_GP_cdnPt_V4;
942
943  case Hexagon::STw_GP_cNotPt_V4 :
944    return Hexagon::STw_GP_cdnNotPt_V4;
945
946  case Hexagon::STriw_GP_cPt_V4 :
947    return Hexagon::STriw_GP_cdnPt_V4;
948
949  case Hexagon::STriw_GP_cNotPt_V4 :
950    return Hexagon::STriw_GP_cdnNotPt_V4;
951
952  // Condtional Jumps
953  case Hexagon::JMP_c:
954    return Hexagon::JMP_cdnPt;
955
956  case Hexagon::JMP_cNot:
957    return Hexagon::JMP_cdnNotPt;
958
959  case Hexagon::JMPR_cPt:
960    return Hexagon::JMPR_cdnPt_V3;
961
962  case Hexagon::JMPR_cNotPt:
963    return Hexagon::JMPR_cdnNotPt_V3;
964
965  // Conditional Transfers
966  case Hexagon::TFR_cPt:
967    return Hexagon::TFR_cdnPt;
968
969  case Hexagon::TFR_cNotPt:
970    return Hexagon::TFR_cdnNotPt;
971
972  case Hexagon::TFRI_cPt:
973    return Hexagon::TFRI_cdnPt;
974
975  case Hexagon::TFRI_cNotPt:
976    return Hexagon::TFRI_cdnNotPt;
977
978  // Load double word
979  case Hexagon::LDrid_cPt :
980    return Hexagon::LDrid_cdnPt;
981
982  case Hexagon::LDrid_cNotPt :
983    return Hexagon::LDrid_cdnNotPt;
984
985  case Hexagon::LDrid_indexed_cPt :
986    return Hexagon::LDrid_indexed_cdnPt;
987
988  case Hexagon::LDrid_indexed_cNotPt :
989    return Hexagon::LDrid_indexed_cdnNotPt;
990
991  case Hexagon::POST_LDrid_cPt :
992    return Hexagon::POST_LDrid_cdnPt_V4;
993
994  case Hexagon::POST_LDrid_cNotPt :
995    return Hexagon::POST_LDrid_cdnNotPt_V4;
996
997  // Load word
998  case Hexagon::LDriw_cPt :
999    return Hexagon::LDriw_cdnPt;
1000
1001  case Hexagon::LDriw_cNotPt :
1002    return Hexagon::LDriw_cdnNotPt;
1003
1004  case Hexagon::LDriw_indexed_cPt :
1005    return Hexagon::LDriw_indexed_cdnPt;
1006
1007  case Hexagon::LDriw_indexed_cNotPt :
1008    return Hexagon::LDriw_indexed_cdnNotPt;
1009
1010  case Hexagon::POST_LDriw_cPt :
1011    return Hexagon::POST_LDriw_cdnPt_V4;
1012
1013  case Hexagon::POST_LDriw_cNotPt :
1014    return Hexagon::POST_LDriw_cdnNotPt_V4;
1015
1016  // Load halfword
1017  case Hexagon::LDrih_cPt :
1018    return Hexagon::LDrih_cdnPt;
1019
1020  case Hexagon::LDrih_cNotPt :
1021    return Hexagon::LDrih_cdnNotPt;
1022
1023  case Hexagon::LDrih_indexed_cPt :
1024    return Hexagon::LDrih_indexed_cdnPt;
1025
1026  case Hexagon::LDrih_indexed_cNotPt :
1027    return Hexagon::LDrih_indexed_cdnNotPt;
1028
1029  case Hexagon::POST_LDrih_cPt :
1030    return Hexagon::POST_LDrih_cdnPt_V4;
1031
1032  case Hexagon::POST_LDrih_cNotPt :
1033    return Hexagon::POST_LDrih_cdnNotPt_V4;
1034
1035  // Load byte
1036  case Hexagon::LDrib_cPt :
1037    return Hexagon::LDrib_cdnPt;
1038
1039  case Hexagon::LDrib_cNotPt :
1040    return Hexagon::LDrib_cdnNotPt;
1041
1042  case Hexagon::LDrib_indexed_cPt :
1043    return Hexagon::LDrib_indexed_cdnPt;
1044
1045  case Hexagon::LDrib_indexed_cNotPt :
1046    return Hexagon::LDrib_indexed_cdnNotPt;
1047
1048  case Hexagon::POST_LDrib_cPt :
1049    return Hexagon::POST_LDrib_cdnPt_V4;
1050
1051  case Hexagon::POST_LDrib_cNotPt :
1052    return Hexagon::POST_LDrib_cdnNotPt_V4;
1053
1054  // Load unsigned halfword
1055  case Hexagon::LDriuh_cPt :
1056    return Hexagon::LDriuh_cdnPt;
1057
1058  case Hexagon::LDriuh_cNotPt :
1059    return Hexagon::LDriuh_cdnNotPt;
1060
1061  case Hexagon::LDriuh_indexed_cPt :
1062    return Hexagon::LDriuh_indexed_cdnPt;
1063
1064  case Hexagon::LDriuh_indexed_cNotPt :
1065    return Hexagon::LDriuh_indexed_cdnNotPt;
1066
1067  case Hexagon::POST_LDriuh_cPt :
1068    return Hexagon::POST_LDriuh_cdnPt_V4;
1069
1070  case Hexagon::POST_LDriuh_cNotPt :
1071    return Hexagon::POST_LDriuh_cdnNotPt_V4;
1072
1073  // Load unsigned byte
1074  case Hexagon::LDriub_cPt :
1075    return Hexagon::LDriub_cdnPt;
1076
1077  case Hexagon::LDriub_cNotPt :
1078    return Hexagon::LDriub_cdnNotPt;
1079
1080  case Hexagon::LDriub_indexed_cPt :
1081    return Hexagon::LDriub_indexed_cdnPt;
1082
1083  case Hexagon::LDriub_indexed_cNotPt :
1084    return Hexagon::LDriub_indexed_cdnNotPt;
1085
1086  case Hexagon::POST_LDriub_cPt :
1087    return Hexagon::POST_LDriub_cdnPt_V4;
1088
1089  case Hexagon::POST_LDriub_cNotPt :
1090    return Hexagon::POST_LDriub_cdnNotPt_V4;
1091
1092  // V4 indexed+scaled load
1093
1094  case Hexagon::LDrid_indexed_cPt_V4 :
1095    return Hexagon::LDrid_indexed_cdnPt_V4;
1096
1097  case Hexagon::LDrid_indexed_cNotPt_V4 :
1098    return Hexagon::LDrid_indexed_cdnNotPt_V4;
1099
1100  case Hexagon::LDrid_indexed_shl_cPt_V4 :
1101    return Hexagon::LDrid_indexed_shl_cdnPt_V4;
1102
1103  case Hexagon::LDrid_indexed_shl_cNotPt_V4 :
1104    return Hexagon::LDrid_indexed_shl_cdnNotPt_V4;
1105
1106  case Hexagon::LDrib_indexed_cPt_V4 :
1107    return Hexagon::LDrib_indexed_cdnPt_V4;
1108
1109  case Hexagon::LDrib_indexed_cNotPt_V4 :
1110    return Hexagon::LDrib_indexed_cdnNotPt_V4;
1111
1112  case Hexagon::LDrib_indexed_shl_cPt_V4 :
1113    return Hexagon::LDrib_indexed_shl_cdnPt_V4;
1114
1115  case Hexagon::LDrib_indexed_shl_cNotPt_V4 :
1116    return Hexagon::LDrib_indexed_shl_cdnNotPt_V4;
1117
1118  case Hexagon::LDriub_indexed_cPt_V4 :
1119    return Hexagon::LDriub_indexed_cdnPt_V4;
1120
1121  case Hexagon::LDriub_indexed_cNotPt_V4 :
1122    return Hexagon::LDriub_indexed_cdnNotPt_V4;
1123
1124  case Hexagon::LDriub_indexed_shl_cPt_V4 :
1125    return Hexagon::LDriub_indexed_shl_cdnPt_V4;
1126
1127  case Hexagon::LDriub_indexed_shl_cNotPt_V4 :
1128    return Hexagon::LDriub_indexed_shl_cdnNotPt_V4;
1129
1130  case Hexagon::LDrih_indexed_cPt_V4 :
1131    return Hexagon::LDrih_indexed_cdnPt_V4;
1132
1133  case Hexagon::LDrih_indexed_cNotPt_V4 :
1134    return Hexagon::LDrih_indexed_cdnNotPt_V4;
1135
1136  case Hexagon::LDrih_indexed_shl_cPt_V4 :
1137    return Hexagon::LDrih_indexed_shl_cdnPt_V4;
1138
1139  case Hexagon::LDrih_indexed_shl_cNotPt_V4 :
1140    return Hexagon::LDrih_indexed_shl_cdnNotPt_V4;
1141
1142  case Hexagon::LDriuh_indexed_cPt_V4 :
1143    return Hexagon::LDriuh_indexed_cdnPt_V4;
1144
1145  case Hexagon::LDriuh_indexed_cNotPt_V4 :
1146    return Hexagon::LDriuh_indexed_cdnNotPt_V4;
1147
1148  case Hexagon::LDriuh_indexed_shl_cPt_V4 :
1149    return Hexagon::LDriuh_indexed_shl_cdnPt_V4;
1150
1151  case Hexagon::LDriuh_indexed_shl_cNotPt_V4 :
1152    return Hexagon::LDriuh_indexed_shl_cdnNotPt_V4;
1153
1154  case Hexagon::LDriw_indexed_cPt_V4 :
1155    return Hexagon::LDriw_indexed_cdnPt_V4;
1156
1157  case Hexagon::LDriw_indexed_cNotPt_V4 :
1158    return Hexagon::LDriw_indexed_cdnNotPt_V4;
1159
1160  case Hexagon::LDriw_indexed_shl_cPt_V4 :
1161    return Hexagon::LDriw_indexed_shl_cdnPt_V4;
1162
1163  case Hexagon::LDriw_indexed_shl_cNotPt_V4 :
1164    return Hexagon::LDriw_indexed_shl_cdnNotPt_V4;
1165
1166  // V4 global address load
1167
1168  case Hexagon::LDd_GP_cPt_V4:
1169    return Hexagon::LDd_GP_cdnPt_V4;
1170
1171  case Hexagon::LDd_GP_cNotPt_V4:
1172    return Hexagon::LDd_GP_cdnNotPt_V4;
1173
1174  case Hexagon::LDb_GP_cPt_V4:
1175    return Hexagon::LDb_GP_cdnPt_V4;
1176
1177  case Hexagon::LDb_GP_cNotPt_V4:
1178    return Hexagon::LDb_GP_cdnNotPt_V4;
1179
1180  case Hexagon::LDub_GP_cPt_V4:
1181    return Hexagon::LDub_GP_cdnPt_V4;
1182
1183  case Hexagon::LDub_GP_cNotPt_V4:
1184    return Hexagon::LDub_GP_cdnNotPt_V4;
1185
1186  case Hexagon::LDh_GP_cPt_V4:
1187    return Hexagon::LDh_GP_cdnPt_V4;
1188
1189  case Hexagon::LDh_GP_cNotPt_V4:
1190    return Hexagon::LDh_GP_cdnNotPt_V4;
1191
1192  case Hexagon::LDuh_GP_cPt_V4:
1193    return Hexagon::LDuh_GP_cdnPt_V4;
1194
1195  case Hexagon::LDuh_GP_cNotPt_V4:
1196    return Hexagon::LDuh_GP_cdnNotPt_V4;
1197
1198  case Hexagon::LDw_GP_cPt_V4:
1199    return Hexagon::LDw_GP_cdnPt_V4;
1200
1201  case Hexagon::LDw_GP_cNotPt_V4:
1202    return Hexagon::LDw_GP_cdnNotPt_V4;
1203
1204  case Hexagon::LDrid_GP_cPt_V4:
1205    return Hexagon::LDrid_GP_cdnPt_V4;
1206
1207  case Hexagon::LDrid_GP_cNotPt_V4:
1208    return Hexagon::LDrid_GP_cdnNotPt_V4;
1209
1210  case Hexagon::LDrib_GP_cPt_V4:
1211    return Hexagon::LDrib_GP_cdnPt_V4;
1212
1213  case Hexagon::LDrib_GP_cNotPt_V4:
1214    return Hexagon::LDrib_GP_cdnNotPt_V4;
1215
1216  case Hexagon::LDriub_GP_cPt_V4:
1217    return Hexagon::LDriub_GP_cdnPt_V4;
1218
1219  case Hexagon::LDriub_GP_cNotPt_V4:
1220    return Hexagon::LDriub_GP_cdnNotPt_V4;
1221
1222  case Hexagon::LDrih_GP_cPt_V4:
1223    return Hexagon::LDrih_GP_cdnPt_V4;
1224
1225  case Hexagon::LDrih_GP_cNotPt_V4:
1226    return Hexagon::LDrih_GP_cdnNotPt_V4;
1227
1228  case Hexagon::LDriuh_GP_cPt_V4:
1229    return Hexagon::LDriuh_GP_cdnPt_V4;
1230
1231  case Hexagon::LDriuh_GP_cNotPt_V4:
1232    return Hexagon::LDriuh_GP_cdnNotPt_V4;
1233
1234  case Hexagon::LDriw_GP_cPt_V4:
1235    return Hexagon::LDriw_GP_cdnPt_V4;
1236
1237  case Hexagon::LDriw_GP_cNotPt_V4:
1238    return Hexagon::LDriw_GP_cdnNotPt_V4;
1239
1240  // Conditional store new-value byte
1241  case Hexagon::STrib_cPt_nv_V4 :
1242    return Hexagon::STrib_cdnPt_nv_V4;
1243  case Hexagon::STrib_cNotPt_nv_V4 :
1244    return Hexagon::STrib_cdnNotPt_nv_V4;
1245
1246  case Hexagon::STrib_indexed_cPt_nv_V4 :
1247    return Hexagon::STrib_indexed_cdnPt_nv_V4;
1248  case Hexagon::STrib_indexed_cNotPt_nv_V4 :
1249    return Hexagon::STrib_indexed_cdnNotPt_nv_V4;
1250
1251  case Hexagon::STrib_indexed_shl_cPt_nv_V4 :
1252    return Hexagon::STrib_indexed_shl_cdnPt_nv_V4;
1253  case Hexagon::STrib_indexed_shl_cNotPt_nv_V4 :
1254    return Hexagon::STrib_indexed_shl_cdnNotPt_nv_V4;
1255
1256  case Hexagon::POST_STbri_cPt_nv_V4 :
1257    return Hexagon::POST_STbri_cdnPt_nv_V4;
1258  case Hexagon::POST_STbri_cNotPt_nv_V4 :
1259    return Hexagon::POST_STbri_cdnNotPt_nv_V4;
1260
1261  case Hexagon::STb_GP_cPt_nv_V4 :
1262    return Hexagon::STb_GP_cdnPt_nv_V4;
1263
1264  case Hexagon::STb_GP_cNotPt_nv_V4 :
1265    return Hexagon::STb_GP_cdnNotPt_nv_V4;
1266
1267  case Hexagon::STrib_GP_cPt_nv_V4 :
1268    return Hexagon::STrib_GP_cdnPt_nv_V4;
1269
1270  case Hexagon::STrib_GP_cNotPt_nv_V4 :
1271    return Hexagon::STrib_GP_cdnNotPt_nv_V4;
1272
1273  // Conditional store new-value halfword
1274  case Hexagon::STrih_cPt_nv_V4 :
1275    return Hexagon::STrih_cdnPt_nv_V4;
1276  case Hexagon::STrih_cNotPt_nv_V4 :
1277    return Hexagon::STrih_cdnNotPt_nv_V4;
1278
1279  case Hexagon::STrih_indexed_cPt_nv_V4 :
1280    return Hexagon::STrih_indexed_cdnPt_nv_V4;
1281  case Hexagon::STrih_indexed_cNotPt_nv_V4 :
1282    return Hexagon::STrih_indexed_cdnNotPt_nv_V4;
1283
1284  case Hexagon::STrih_indexed_shl_cPt_nv_V4 :
1285    return Hexagon::STrih_indexed_shl_cdnPt_nv_V4;
1286  case Hexagon::STrih_indexed_shl_cNotPt_nv_V4 :
1287    return Hexagon::STrih_indexed_shl_cdnNotPt_nv_V4;
1288
1289  case Hexagon::POST_SThri_cPt_nv_V4 :
1290    return Hexagon::POST_SThri_cdnPt_nv_V4;
1291  case Hexagon::POST_SThri_cNotPt_nv_V4 :
1292    return Hexagon::POST_SThri_cdnNotPt_nv_V4;
1293
1294  case Hexagon::STh_GP_cPt_nv_V4 :
1295    return Hexagon::STh_GP_cdnPt_nv_V4;
1296
1297  case Hexagon::STh_GP_cNotPt_nv_V4 :
1298    return Hexagon::STh_GP_cdnNotPt_nv_V4;
1299
1300  case Hexagon::STrih_GP_cPt_nv_V4 :
1301    return Hexagon::STrih_GP_cdnPt_nv_V4;
1302
1303  case Hexagon::STrih_GP_cNotPt_nv_V4 :
1304    return Hexagon::STrih_GP_cdnNotPt_nv_V4;
1305
1306  // Conditional store new-value word
1307  case Hexagon::STriw_cPt_nv_V4 :
1308    return  Hexagon::STriw_cdnPt_nv_V4;
1309  case Hexagon::STriw_cNotPt_nv_V4 :
1310    return Hexagon::STriw_cdnNotPt_nv_V4;
1311
1312  case Hexagon::STriw_indexed_cPt_nv_V4 :
1313    return Hexagon::STriw_indexed_cdnPt_nv_V4;
1314  case Hexagon::STriw_indexed_cNotPt_nv_V4 :
1315    return Hexagon::STriw_indexed_cdnNotPt_nv_V4;
1316
1317  case Hexagon::STriw_indexed_shl_cPt_nv_V4 :
1318    return Hexagon::STriw_indexed_shl_cdnPt_nv_V4;
1319  case Hexagon::STriw_indexed_shl_cNotPt_nv_V4 :
1320    return Hexagon::STriw_indexed_shl_cdnNotPt_nv_V4;
1321
1322  case Hexagon::POST_STwri_cPt_nv_V4 :
1323    return Hexagon::POST_STwri_cdnPt_nv_V4;
1324  case Hexagon::POST_STwri_cNotPt_nv_V4:
1325    return Hexagon::POST_STwri_cdnNotPt_nv_V4;
1326
1327  case Hexagon::STw_GP_cPt_nv_V4 :
1328    return Hexagon::STw_GP_cdnPt_nv_V4;
1329
1330  case Hexagon::STw_GP_cNotPt_nv_V4 :
1331    return Hexagon::STw_GP_cdnNotPt_nv_V4;
1332
1333  case Hexagon::STriw_GP_cPt_nv_V4 :
1334    return Hexagon::STriw_GP_cdnPt_nv_V4;
1335
1336  case Hexagon::STriw_GP_cNotPt_nv_V4 :
1337    return Hexagon::STriw_GP_cdnNotPt_nv_V4;
1338
1339  // Conditional add
1340  case Hexagon::ADD_ri_cPt :
1341    return Hexagon::ADD_ri_cdnPt;
1342  case Hexagon::ADD_ri_cNotPt :
1343    return Hexagon::ADD_ri_cdnNotPt;
1344
1345  case Hexagon::ADD_rr_cPt :
1346    return Hexagon::ADD_rr_cdnPt;
1347  case Hexagon::ADD_rr_cNotPt :
1348    return Hexagon::ADD_rr_cdnNotPt;
1349
1350  // Conditional logical Operations
1351  case Hexagon::XOR_rr_cPt :
1352    return Hexagon::XOR_rr_cdnPt;
1353  case Hexagon::XOR_rr_cNotPt :
1354    return Hexagon::XOR_rr_cdnNotPt;
1355
1356  case Hexagon::AND_rr_cPt :
1357    return Hexagon::AND_rr_cdnPt;
1358  case Hexagon::AND_rr_cNotPt :
1359    return Hexagon::AND_rr_cdnNotPt;
1360
1361  case Hexagon::OR_rr_cPt :
1362    return Hexagon::OR_rr_cdnPt;
1363  case Hexagon::OR_rr_cNotPt :
1364    return Hexagon::OR_rr_cdnNotPt;
1365
1366  // Conditional Subtract
1367  case Hexagon::SUB_rr_cPt :
1368    return Hexagon::SUB_rr_cdnPt;
1369  case Hexagon::SUB_rr_cNotPt :
1370    return Hexagon::SUB_rr_cdnNotPt;
1371
1372  // Conditional combine
1373  case Hexagon::COMBINE_rr_cPt :
1374    return Hexagon::COMBINE_rr_cdnPt;
1375  case Hexagon::COMBINE_rr_cNotPt :
1376    return Hexagon::COMBINE_rr_cdnNotPt;
1377
1378  case Hexagon::ASLH_cPt_V4 :
1379    return Hexagon::ASLH_cdnPt_V4;
1380  case Hexagon::ASLH_cNotPt_V4 :
1381    return Hexagon::ASLH_cdnNotPt_V4;
1382
1383  case Hexagon::ASRH_cPt_V4 :
1384    return Hexagon::ASRH_cdnPt_V4;
1385  case Hexagon::ASRH_cNotPt_V4 :
1386    return Hexagon::ASRH_cdnNotPt_V4;
1387
1388  case Hexagon::SXTB_cPt_V4 :
1389    return Hexagon::SXTB_cdnPt_V4;
1390  case Hexagon::SXTB_cNotPt_V4 :
1391    return Hexagon::SXTB_cdnNotPt_V4;
1392
1393  case Hexagon::SXTH_cPt_V4 :
1394    return Hexagon::SXTH_cdnPt_V4;
1395  case Hexagon::SXTH_cNotPt_V4 :
1396    return Hexagon::SXTH_cdnNotPt_V4;
1397
1398  case Hexagon::ZXTB_cPt_V4 :
1399    return Hexagon::ZXTB_cdnPt_V4;
1400  case Hexagon::ZXTB_cNotPt_V4 :
1401    return Hexagon::ZXTB_cdnNotPt_V4;
1402
1403  case Hexagon::ZXTH_cPt_V4 :
1404    return Hexagon::ZXTH_cdnPt_V4;
1405  case Hexagon::ZXTH_cNotPt_V4 :
1406    return Hexagon::ZXTH_cdnNotPt_V4;
1407  }
1408}
1409
1410// Returns true if an instruction can be promoted to .new predicate
1411// or new-value store.
1412bool HexagonPacketizerList::isNewifiable(MachineInstr* MI) {
1413  if ( isCondInst(MI) || IsNewifyStore(MI))
1414    return true;
1415  else
1416    return false;
1417}
1418
1419bool HexagonPacketizerList::isCondInst (MachineInstr* MI) {
1420  const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
1421  const MCInstrDesc& TID = MI->getDesc();
1422                                    // bug 5670: until that is fixed,
1423                                    // this portion is disabled.
1424  if (   TID.isConditionalBranch()  // && !IsRegisterJump(MI)) ||
1425      || QII->isConditionalTransfer(MI)
1426      || QII->isConditionalALU32(MI)
1427      || QII->isConditionalLoad(MI)
1428      || QII->isConditionalStore(MI)) {
1429    return true;
1430  }
1431  return false;
1432}
1433
1434
1435// Promote an instructiont to its .new form.
1436// At this time, we have already made a call to CanPromoteToDotNew
1437// and made sure that it can *indeed* be promoted.
1438bool HexagonPacketizerList::PromoteToDotNew(MachineInstr* MI,
1439                        SDep::Kind DepType, MachineBasicBlock::iterator &MII,
1440                        const TargetRegisterClass* RC) {
1441
1442  assert (DepType == SDep::Data);
1443  const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
1444
1445  int NewOpcode;
1446  if (RC == Hexagon::PredRegsRegisterClass)
1447    NewOpcode = GetDotNewPredOp(MI->getOpcode());
1448  else
1449    NewOpcode = GetDotNewOp(MI->getOpcode());
1450  MI->setDesc(QII->get(NewOpcode));
1451
1452  return true;
1453}
1454
1455// Returns the most basic instruction for the .new predicated instructions and
1456// new-value stores.
1457// For example, all of the following instructions will be converted back to the
1458// same instruction:
1459// 1) if (p0.new) memw(R0+#0) = R1.new  --->
1460// 2) if (p0) memw(R0+#0)= R1.new      -------> if (p0) memw(R0+#0) = R1
1461// 3) if (p0.new) memw(R0+#0) = R1      --->
1462//
1463// To understand the translation of instruction 1 to its original form, consider
1464// a packet with 3 instructions.
1465// { p0 = cmp.eq(R0,R1)
1466//   if (p0.new) R2 = add(R3, R4)
1467//   R5 = add (R3, R1)
1468//   }
1469// if (p0) memw(R5+#0) = R2 <--- trying to include it in the previous packet
1470//
1471// This instruction can be part of the previous packet only if both p0 and R2
1472// are promoted to .new values. This promotion happens in steps, first
1473// predicate register is promoted to .new and in the next iteration R2 is
1474// promoted. Therefore, in case of dependence check failure (due to R5) during
1475// next iteration, it should be converted back to its most basic form.
1476
1477static int GetDotOldOp(const int opc) {
1478  switch (opc) {
1479  default: llvm_unreachable("Unknown .old type");
1480
1481  case Hexagon::TFR_cdnPt:
1482    return Hexagon::TFR_cPt;
1483
1484  case Hexagon::TFR_cdnNotPt:
1485    return Hexagon::TFR_cNotPt;
1486
1487  case Hexagon::TFRI_cdnPt:
1488    return Hexagon::TFRI_cPt;
1489
1490  case Hexagon::TFRI_cdnNotPt:
1491    return Hexagon::TFRI_cNotPt;
1492
1493  case Hexagon::JMP_cdnPt:
1494    return Hexagon::JMP_c;
1495
1496  case Hexagon::JMP_cdnNotPt:
1497    return Hexagon::JMP_cNot;
1498
1499  case Hexagon::JMPR_cdnPt_V3:
1500    return Hexagon::JMPR_cPt;
1501
1502  case Hexagon::JMPR_cdnNotPt_V3:
1503    return Hexagon::JMPR_cNotPt;
1504
1505  // Load double word
1506
1507  case Hexagon::LDrid_cdnPt :
1508    return Hexagon::LDrid_cPt;
1509
1510  case Hexagon::LDrid_cdnNotPt :
1511    return Hexagon::LDrid_cNotPt;
1512
1513  case Hexagon::LDrid_indexed_cdnPt :
1514    return Hexagon::LDrid_indexed_cPt;
1515
1516  case Hexagon::LDrid_indexed_cdnNotPt :
1517    return Hexagon::LDrid_indexed_cNotPt;
1518
1519  case Hexagon::POST_LDrid_cdnPt_V4 :
1520    return Hexagon::POST_LDrid_cPt;
1521
1522  case Hexagon::POST_LDrid_cdnNotPt_V4 :
1523    return Hexagon::POST_LDrid_cNotPt;
1524
1525  // Load word
1526
1527  case Hexagon::LDriw_cdnPt :
1528    return Hexagon::LDriw_cPt;
1529
1530  case Hexagon::LDriw_cdnNotPt :
1531    return Hexagon::LDriw_cNotPt;
1532
1533  case Hexagon::LDriw_indexed_cdnPt :
1534    return Hexagon::LDriw_indexed_cPt;
1535
1536  case Hexagon::LDriw_indexed_cdnNotPt :
1537    return Hexagon::LDriw_indexed_cNotPt;
1538
1539  case Hexagon::POST_LDriw_cdnPt_V4 :
1540    return Hexagon::POST_LDriw_cPt;
1541
1542  case Hexagon::POST_LDriw_cdnNotPt_V4 :
1543    return Hexagon::POST_LDriw_cNotPt;
1544
1545  // Load half
1546
1547  case Hexagon::LDrih_cdnPt :
1548    return Hexagon::LDrih_cPt;
1549
1550  case Hexagon::LDrih_cdnNotPt :
1551    return Hexagon::LDrih_cNotPt;
1552
1553  case Hexagon::LDrih_indexed_cdnPt :
1554    return Hexagon::LDrih_indexed_cPt;
1555
1556  case Hexagon::LDrih_indexed_cdnNotPt :
1557    return Hexagon::LDrih_indexed_cNotPt;
1558
1559  case Hexagon::POST_LDrih_cdnPt_V4 :
1560    return Hexagon::POST_LDrih_cPt;
1561
1562  case Hexagon::POST_LDrih_cdnNotPt_V4 :
1563    return Hexagon::POST_LDrih_cNotPt;
1564
1565  // Load byte
1566
1567  case Hexagon::LDrib_cdnPt :
1568    return Hexagon::LDrib_cPt;
1569
1570  case Hexagon::LDrib_cdnNotPt :
1571    return Hexagon::LDrib_cNotPt;
1572
1573  case Hexagon::LDrib_indexed_cdnPt :
1574    return Hexagon::LDrib_indexed_cPt;
1575
1576  case Hexagon::LDrib_indexed_cdnNotPt :
1577    return Hexagon::LDrib_indexed_cNotPt;
1578
1579  case Hexagon::POST_LDrib_cdnPt_V4 :
1580    return Hexagon::POST_LDrib_cPt;
1581
1582  case Hexagon::POST_LDrib_cdnNotPt_V4 :
1583    return Hexagon::POST_LDrib_cNotPt;
1584
1585  // Load unsigned half
1586
1587  case Hexagon::LDriuh_cdnPt :
1588    return Hexagon::LDriuh_cPt;
1589
1590  case Hexagon::LDriuh_cdnNotPt :
1591    return Hexagon::LDriuh_cNotPt;
1592
1593  case Hexagon::LDriuh_indexed_cdnPt :
1594    return Hexagon::LDriuh_indexed_cPt;
1595
1596  case Hexagon::LDriuh_indexed_cdnNotPt :
1597    return Hexagon::LDriuh_indexed_cNotPt;
1598
1599  case Hexagon::POST_LDriuh_cdnPt_V4 :
1600    return Hexagon::POST_LDriuh_cPt;
1601
1602  case Hexagon::POST_LDriuh_cdnNotPt_V4 :
1603    return Hexagon::POST_LDriuh_cNotPt;
1604
1605  // Load unsigned byte
1606  case Hexagon::LDriub_cdnPt :
1607    return Hexagon::LDriub_cPt;
1608
1609  case Hexagon::LDriub_cdnNotPt :
1610    return Hexagon::LDriub_cNotPt;
1611
1612  case Hexagon::LDriub_indexed_cdnPt :
1613    return Hexagon::LDriub_indexed_cPt;
1614
1615  case Hexagon::LDriub_indexed_cdnNotPt :
1616    return Hexagon::LDriub_indexed_cNotPt;
1617
1618  case Hexagon::POST_LDriub_cdnPt_V4 :
1619    return Hexagon::POST_LDriub_cPt;
1620
1621  case Hexagon::POST_LDriub_cdnNotPt_V4 :
1622    return Hexagon::POST_LDriub_cNotPt;
1623
1624  // V4 indexed+scaled Load
1625
1626  case Hexagon::LDrid_indexed_cdnPt_V4 :
1627    return Hexagon::LDrid_indexed_cPt_V4;
1628
1629  case Hexagon::LDrid_indexed_cdnNotPt_V4 :
1630    return Hexagon::LDrid_indexed_cNotPt_V4;
1631
1632  case Hexagon::LDrid_indexed_shl_cdnPt_V4 :
1633    return Hexagon::LDrid_indexed_shl_cPt_V4;
1634
1635  case Hexagon::LDrid_indexed_shl_cdnNotPt_V4 :
1636    return Hexagon::LDrid_indexed_shl_cNotPt_V4;
1637
1638  case Hexagon::LDrib_indexed_cdnPt_V4 :
1639    return Hexagon::LDrib_indexed_cPt_V4;
1640
1641  case Hexagon::LDrib_indexed_cdnNotPt_V4 :
1642    return Hexagon::LDrib_indexed_cNotPt_V4;
1643
1644  case Hexagon::LDrib_indexed_shl_cdnPt_V4 :
1645    return Hexagon::LDrib_indexed_shl_cPt_V4;
1646
1647  case Hexagon::LDrib_indexed_shl_cdnNotPt_V4 :
1648    return Hexagon::LDrib_indexed_shl_cNotPt_V4;
1649
1650  case Hexagon::LDriub_indexed_cdnPt_V4 :
1651    return Hexagon::LDriub_indexed_cPt_V4;
1652
1653  case Hexagon::LDriub_indexed_cdnNotPt_V4 :
1654    return Hexagon::LDriub_indexed_cNotPt_V4;
1655
1656  case Hexagon::LDriub_indexed_shl_cdnPt_V4 :
1657    return Hexagon::LDriub_indexed_shl_cPt_V4;
1658
1659  case Hexagon::LDriub_indexed_shl_cdnNotPt_V4 :
1660    return Hexagon::LDriub_indexed_shl_cNotPt_V4;
1661
1662  case Hexagon::LDrih_indexed_cdnPt_V4 :
1663    return Hexagon::LDrih_indexed_cPt_V4;
1664
1665  case Hexagon::LDrih_indexed_cdnNotPt_V4 :
1666    return Hexagon::LDrih_indexed_cNotPt_V4;
1667
1668  case Hexagon::LDrih_indexed_shl_cdnPt_V4 :
1669    return Hexagon::LDrih_indexed_shl_cPt_V4;
1670
1671  case Hexagon::LDrih_indexed_shl_cdnNotPt_V4 :
1672    return Hexagon::LDrih_indexed_shl_cNotPt_V4;
1673
1674  case Hexagon::LDriuh_indexed_cdnPt_V4 :
1675    return Hexagon::LDriuh_indexed_cPt_V4;
1676
1677  case Hexagon::LDriuh_indexed_cdnNotPt_V4 :
1678    return Hexagon::LDriuh_indexed_cNotPt_V4;
1679
1680  case Hexagon::LDriuh_indexed_shl_cdnPt_V4 :
1681    return Hexagon::LDriuh_indexed_shl_cPt_V4;
1682
1683  case Hexagon::LDriuh_indexed_shl_cdnNotPt_V4 :
1684    return Hexagon::LDriuh_indexed_shl_cNotPt_V4;
1685
1686  case Hexagon::LDriw_indexed_cdnPt_V4 :
1687    return Hexagon::LDriw_indexed_cPt_V4;
1688
1689  case Hexagon::LDriw_indexed_cdnNotPt_V4 :
1690    return Hexagon::LDriw_indexed_cNotPt_V4;
1691
1692  case Hexagon::LDriw_indexed_shl_cdnPt_V4 :
1693    return Hexagon::LDriw_indexed_shl_cPt_V4;
1694
1695  case Hexagon::LDriw_indexed_shl_cdnNotPt_V4 :
1696    return Hexagon::LDriw_indexed_shl_cNotPt_V4;
1697
1698  // V4 global address load
1699
1700  case Hexagon::LDd_GP_cdnPt_V4:
1701    return Hexagon::LDd_GP_cPt_V4;
1702
1703  case Hexagon::LDd_GP_cdnNotPt_V4:
1704    return Hexagon::LDd_GP_cNotPt_V4;
1705
1706  case Hexagon::LDb_GP_cdnPt_V4:
1707    return Hexagon::LDb_GP_cPt_V4;
1708
1709  case Hexagon::LDb_GP_cdnNotPt_V4:
1710    return Hexagon::LDb_GP_cNotPt_V4;
1711
1712  case Hexagon::LDub_GP_cdnPt_V4:
1713    return Hexagon::LDub_GP_cPt_V4;
1714
1715  case Hexagon::LDub_GP_cdnNotPt_V4:
1716    return Hexagon::LDub_GP_cNotPt_V4;
1717
1718  case Hexagon::LDh_GP_cdnPt_V4:
1719    return Hexagon::LDh_GP_cPt_V4;
1720
1721  case Hexagon::LDh_GP_cdnNotPt_V4:
1722    return Hexagon::LDh_GP_cNotPt_V4;
1723
1724  case Hexagon::LDuh_GP_cdnPt_V4:
1725    return Hexagon::LDuh_GP_cPt_V4;
1726
1727  case Hexagon::LDuh_GP_cdnNotPt_V4:
1728    return Hexagon::LDuh_GP_cNotPt_V4;
1729
1730  case Hexagon::LDw_GP_cdnPt_V4:
1731    return Hexagon::LDw_GP_cPt_V4;
1732
1733  case Hexagon::LDw_GP_cdnNotPt_V4:
1734    return Hexagon::LDw_GP_cNotPt_V4;
1735
1736  case Hexagon::LDrid_GP_cdnPt_V4:
1737    return Hexagon::LDrid_GP_cPt_V4;
1738
1739  case Hexagon::LDrid_GP_cdnNotPt_V4:
1740    return Hexagon::LDrid_GP_cNotPt_V4;
1741
1742  case Hexagon::LDrib_GP_cdnPt_V4:
1743    return Hexagon::LDrib_GP_cPt_V4;
1744
1745  case Hexagon::LDrib_GP_cdnNotPt_V4:
1746    return Hexagon::LDrib_GP_cNotPt_V4;
1747
1748  case Hexagon::LDriub_GP_cdnPt_V4:
1749    return Hexagon::LDriub_GP_cPt_V4;
1750
1751  case Hexagon::LDriub_GP_cdnNotPt_V4:
1752    return Hexagon::LDriub_GP_cNotPt_V4;
1753
1754  case Hexagon::LDrih_GP_cdnPt_V4:
1755    return Hexagon::LDrih_GP_cPt_V4;
1756
1757  case Hexagon::LDrih_GP_cdnNotPt_V4:
1758    return Hexagon::LDrih_GP_cNotPt_V4;
1759
1760  case Hexagon::LDriuh_GP_cdnPt_V4:
1761    return Hexagon::LDriuh_GP_cPt_V4;
1762
1763  case Hexagon::LDriuh_GP_cdnNotPt_V4:
1764    return Hexagon::LDriuh_GP_cNotPt_V4;
1765
1766  case Hexagon::LDriw_GP_cdnPt_V4:
1767    return Hexagon::LDriw_GP_cPt_V4;
1768
1769  case Hexagon::LDriw_GP_cdnNotPt_V4:
1770    return Hexagon::LDriw_GP_cNotPt_V4;
1771
1772  // Conditional add
1773
1774  case Hexagon::ADD_ri_cdnPt :
1775    return Hexagon::ADD_ri_cPt;
1776  case Hexagon::ADD_ri_cdnNotPt :
1777    return Hexagon::ADD_ri_cNotPt;
1778
1779  case Hexagon::ADD_rr_cdnPt :
1780    return Hexagon::ADD_rr_cPt;
1781  case Hexagon::ADD_rr_cdnNotPt:
1782    return Hexagon::ADD_rr_cNotPt;
1783
1784  // Conditional logical Operations
1785
1786  case Hexagon::XOR_rr_cdnPt :
1787    return Hexagon::XOR_rr_cPt;
1788  case Hexagon::XOR_rr_cdnNotPt :
1789    return Hexagon::XOR_rr_cNotPt;
1790
1791  case Hexagon::AND_rr_cdnPt :
1792    return Hexagon::AND_rr_cPt;
1793  case Hexagon::AND_rr_cdnNotPt :
1794    return Hexagon::AND_rr_cNotPt;
1795
1796  case Hexagon::OR_rr_cdnPt :
1797    return Hexagon::OR_rr_cPt;
1798  case Hexagon::OR_rr_cdnNotPt :
1799    return Hexagon::OR_rr_cNotPt;
1800
1801  // Conditional Subtract
1802
1803  case Hexagon::SUB_rr_cdnPt :
1804    return Hexagon::SUB_rr_cPt;
1805  case Hexagon::SUB_rr_cdnNotPt :
1806    return Hexagon::SUB_rr_cNotPt;
1807
1808  // Conditional combine
1809
1810  case Hexagon::COMBINE_rr_cdnPt :
1811    return Hexagon::COMBINE_rr_cPt;
1812  case Hexagon::COMBINE_rr_cdnNotPt :
1813    return Hexagon::COMBINE_rr_cNotPt;
1814
1815// Conditional shift operations
1816
1817  case Hexagon::ASLH_cdnPt_V4 :
1818    return Hexagon::ASLH_cPt_V4;
1819  case Hexagon::ASLH_cdnNotPt_V4 :
1820    return Hexagon::ASLH_cNotPt_V4;
1821
1822  case Hexagon::ASRH_cdnPt_V4 :
1823    return Hexagon::ASRH_cPt_V4;
1824  case Hexagon::ASRH_cdnNotPt_V4 :
1825    return Hexagon::ASRH_cNotPt_V4;
1826
1827  case Hexagon::SXTB_cdnPt_V4 :
1828    return Hexagon::SXTB_cPt_V4;
1829  case Hexagon::SXTB_cdnNotPt_V4 :
1830    return Hexagon::SXTB_cNotPt_V4;
1831
1832  case Hexagon::SXTH_cdnPt_V4 :
1833    return Hexagon::SXTH_cPt_V4;
1834  case Hexagon::SXTH_cdnNotPt_V4 :
1835    return Hexagon::SXTH_cNotPt_V4;
1836
1837  case Hexagon::ZXTB_cdnPt_V4 :
1838    return Hexagon::ZXTB_cPt_V4;
1839  case Hexagon::ZXTB_cdnNotPt_V4 :
1840    return Hexagon::ZXTB_cNotPt_V4;
1841
1842  case Hexagon::ZXTH_cdnPt_V4 :
1843    return Hexagon::ZXTH_cPt_V4;
1844  case Hexagon::ZXTH_cdnNotPt_V4 :
1845    return Hexagon::ZXTH_cNotPt_V4;
1846
1847  // Store byte
1848
1849  case Hexagon::STrib_imm_cdnPt_V4 :
1850    return Hexagon::STrib_imm_cPt_V4;
1851
1852  case Hexagon::STrib_imm_cdnNotPt_V4 :
1853    return Hexagon::STrib_imm_cNotPt_V4;
1854
1855  case Hexagon::STrib_cdnPt_nv_V4 :
1856  case Hexagon::STrib_cPt_nv_V4 :
1857  case Hexagon::STrib_cdnPt_V4 :
1858    return Hexagon::STrib_cPt;
1859
1860  case Hexagon::STrib_cdnNotPt_nv_V4 :
1861  case Hexagon::STrib_cNotPt_nv_V4 :
1862  case Hexagon::STrib_cdnNotPt_V4 :
1863    return Hexagon::STrib_cNotPt;
1864
1865  case Hexagon::STrib_indexed_cdnPt_V4 :
1866  case Hexagon::STrib_indexed_cPt_nv_V4 :
1867  case Hexagon::STrib_indexed_cdnPt_nv_V4 :
1868    return Hexagon::STrib_indexed_cPt;
1869
1870  case Hexagon::STrib_indexed_cdnNotPt_V4 :
1871  case Hexagon::STrib_indexed_cNotPt_nv_V4 :
1872  case Hexagon::STrib_indexed_cdnNotPt_nv_V4 :
1873    return Hexagon::STrib_indexed_cNotPt;
1874
1875  case Hexagon::STrib_indexed_shl_cdnPt_nv_V4:
1876  case Hexagon::STrib_indexed_shl_cPt_nv_V4 :
1877  case Hexagon::STrib_indexed_shl_cdnPt_V4 :
1878    return Hexagon::STrib_indexed_shl_cPt_V4;
1879
1880  case Hexagon::STrib_indexed_shl_cdnNotPt_nv_V4:
1881  case Hexagon::STrib_indexed_shl_cNotPt_nv_V4 :
1882  case Hexagon::STrib_indexed_shl_cdnNotPt_V4 :
1883    return Hexagon::STrib_indexed_shl_cNotPt_V4;
1884
1885  case Hexagon::POST_STbri_cdnPt_nv_V4 :
1886  case Hexagon::POST_STbri_cPt_nv_V4 :
1887  case Hexagon::POST_STbri_cdnPt_V4 :
1888    return Hexagon::POST_STbri_cPt;
1889
1890  case Hexagon::POST_STbri_cdnNotPt_nv_V4 :
1891  case Hexagon::POST_STbri_cNotPt_nv_V4:
1892  case Hexagon::POST_STbri_cdnNotPt_V4 :
1893    return Hexagon::POST_STbri_cNotPt;
1894
1895  case Hexagon::STb_GP_cdnPt_nv_V4:
1896  case Hexagon::STb_GP_cdnPt_V4:
1897  case Hexagon::STb_GP_cPt_nv_V4:
1898    return Hexagon::STb_GP_cPt_V4;
1899
1900  case Hexagon::STb_GP_cdnNotPt_nv_V4:
1901  case Hexagon::STb_GP_cdnNotPt_V4:
1902  case Hexagon::STb_GP_cNotPt_nv_V4:
1903    return Hexagon::STb_GP_cNotPt_V4;
1904
1905  case Hexagon::STrib_GP_cdnPt_nv_V4:
1906  case Hexagon::STrib_GP_cdnPt_V4:
1907  case Hexagon::STrib_GP_cPt_nv_V4:
1908    return Hexagon::STrib_GP_cPt_V4;
1909
1910  case Hexagon::STrib_GP_cdnNotPt_nv_V4:
1911  case Hexagon::STrib_GP_cdnNotPt_V4:
1912  case Hexagon::STrib_GP_cNotPt_nv_V4:
1913    return Hexagon::STrib_GP_cNotPt_V4;
1914
1915  // Store new-value byte - unconditional
1916  case Hexagon::STrib_nv_V4:
1917    return Hexagon::STrib;
1918
1919  case Hexagon::STrib_indexed_nv_V4:
1920    return Hexagon::STrib_indexed;
1921
1922  case Hexagon::STrib_indexed_shl_nv_V4:
1923    return Hexagon::STrib_indexed_shl_V4;
1924
1925  case Hexagon::STrib_shl_nv_V4:
1926    return Hexagon::STrib_shl_V4;
1927
1928  case Hexagon::STrib_GP_nv_V4:
1929    return Hexagon::STrib_GP_V4;
1930
1931  case Hexagon::STb_GP_nv_V4:
1932    return Hexagon::STb_GP_V4;
1933
1934  case Hexagon::POST_STbri_nv_V4:
1935    return Hexagon::POST_STbri;
1936
1937  // Store halfword
1938  case Hexagon::STrih_imm_cdnPt_V4 :
1939    return Hexagon::STrih_imm_cPt_V4;
1940
1941  case Hexagon::STrih_imm_cdnNotPt_V4 :
1942    return Hexagon::STrih_imm_cNotPt_V4;
1943
1944  case Hexagon::STrih_cdnPt_nv_V4 :
1945  case Hexagon::STrih_cPt_nv_V4 :
1946  case Hexagon::STrih_cdnPt_V4 :
1947    return Hexagon::STrih_cPt;
1948
1949  case Hexagon::STrih_cdnNotPt_nv_V4 :
1950  case Hexagon::STrih_cNotPt_nv_V4 :
1951  case Hexagon::STrih_cdnNotPt_V4 :
1952    return Hexagon::STrih_cNotPt;
1953
1954  case Hexagon::STrih_indexed_cdnPt_nv_V4:
1955  case Hexagon::STrih_indexed_cPt_nv_V4 :
1956  case Hexagon::STrih_indexed_cdnPt_V4 :
1957    return Hexagon::STrih_indexed_cPt;
1958
1959  case Hexagon::STrih_indexed_cdnNotPt_nv_V4:
1960  case Hexagon::STrih_indexed_cNotPt_nv_V4 :
1961  case Hexagon::STrih_indexed_cdnNotPt_V4 :
1962    return Hexagon::STrih_indexed_cNotPt;
1963
1964  case Hexagon::STrih_indexed_shl_cdnPt_nv_V4 :
1965  case Hexagon::STrih_indexed_shl_cPt_nv_V4 :
1966  case Hexagon::STrih_indexed_shl_cdnPt_V4 :
1967    return Hexagon::STrih_indexed_shl_cPt_V4;
1968
1969  case Hexagon::STrih_indexed_shl_cdnNotPt_nv_V4 :
1970  case Hexagon::STrih_indexed_shl_cNotPt_nv_V4 :
1971  case Hexagon::STrih_indexed_shl_cdnNotPt_V4 :
1972    return Hexagon::STrih_indexed_shl_cNotPt_V4;
1973
1974  case Hexagon::POST_SThri_cdnPt_nv_V4 :
1975  case Hexagon::POST_SThri_cPt_nv_V4 :
1976  case Hexagon::POST_SThri_cdnPt_V4 :
1977    return Hexagon::POST_SThri_cPt;
1978
1979  case Hexagon::POST_SThri_cdnNotPt_nv_V4 :
1980  case Hexagon::POST_SThri_cNotPt_nv_V4 :
1981  case Hexagon::POST_SThri_cdnNotPt_V4 :
1982    return Hexagon::POST_SThri_cNotPt;
1983
1984  case Hexagon::STh_GP_cdnPt_nv_V4:
1985  case Hexagon::STh_GP_cdnPt_V4:
1986  case Hexagon::STh_GP_cPt_nv_V4:
1987    return Hexagon::STh_GP_cPt_V4;
1988
1989  case Hexagon::STh_GP_cdnNotPt_nv_V4:
1990  case Hexagon::STh_GP_cdnNotPt_V4:
1991  case Hexagon::STh_GP_cNotPt_nv_V4:
1992    return Hexagon::STh_GP_cNotPt_V4;
1993
1994  case Hexagon::STrih_GP_cdnPt_nv_V4:
1995  case Hexagon::STrih_GP_cdnPt_V4:
1996  case Hexagon::STrih_GP_cPt_nv_V4:
1997    return Hexagon::STrih_GP_cPt_V4;
1998
1999  case Hexagon::STrih_GP_cdnNotPt_nv_V4:
2000  case Hexagon::STrih_GP_cdnNotPt_V4:
2001  case Hexagon::STrih_GP_cNotPt_nv_V4:
2002    return Hexagon::STrih_GP_cNotPt_V4;
2003
2004  // Store new-value halfword - unconditional
2005
2006  case Hexagon::STrih_nv_V4:
2007    return Hexagon::STrih;
2008
2009  case Hexagon::STrih_indexed_nv_V4:
2010    return Hexagon::STrih_indexed;
2011
2012  case Hexagon::STrih_indexed_shl_nv_V4:
2013    return Hexagon::STrih_indexed_shl_V4;
2014
2015  case Hexagon::STrih_shl_nv_V4:
2016    return Hexagon::STrih_shl_V4;
2017
2018  case Hexagon::STrih_GP_nv_V4:
2019    return Hexagon::STrih_GP_V4;
2020
2021  case Hexagon::STh_GP_nv_V4:
2022    return Hexagon::STh_GP_V4;
2023
2024  case Hexagon::POST_SThri_nv_V4:
2025    return Hexagon::POST_SThri;
2026
2027   // Store word
2028
2029   case Hexagon::STriw_imm_cdnPt_V4 :
2030    return Hexagon::STriw_imm_cPt_V4;
2031
2032  case Hexagon::STriw_imm_cdnNotPt_V4 :
2033    return Hexagon::STriw_imm_cNotPt_V4;
2034
2035  case Hexagon::STriw_cdnPt_nv_V4 :
2036  case Hexagon::STriw_cPt_nv_V4 :
2037  case Hexagon::STriw_cdnPt_V4 :
2038    return Hexagon::STriw_cPt;
2039
2040  case Hexagon::STriw_cdnNotPt_nv_V4 :
2041  case Hexagon::STriw_cNotPt_nv_V4 :
2042  case Hexagon::STriw_cdnNotPt_V4 :
2043    return Hexagon::STriw_cNotPt;
2044
2045  case Hexagon::STriw_indexed_cdnPt_nv_V4 :
2046  case Hexagon::STriw_indexed_cPt_nv_V4 :
2047  case Hexagon::STriw_indexed_cdnPt_V4 :
2048    return Hexagon::STriw_indexed_cPt;
2049
2050  case Hexagon::STriw_indexed_cdnNotPt_nv_V4 :
2051  case Hexagon::STriw_indexed_cNotPt_nv_V4 :
2052  case Hexagon::STriw_indexed_cdnNotPt_V4 :
2053    return Hexagon::STriw_indexed_cNotPt;
2054
2055  case Hexagon::STriw_indexed_shl_cdnPt_nv_V4 :
2056  case Hexagon::STriw_indexed_shl_cPt_nv_V4 :
2057  case Hexagon::STriw_indexed_shl_cdnPt_V4 :
2058    return Hexagon::STriw_indexed_shl_cPt_V4;
2059
2060  case Hexagon::STriw_indexed_shl_cdnNotPt_nv_V4 :
2061  case Hexagon::STriw_indexed_shl_cNotPt_nv_V4 :
2062  case Hexagon::STriw_indexed_shl_cdnNotPt_V4 :
2063    return Hexagon::STriw_indexed_shl_cNotPt_V4;
2064
2065  case Hexagon::POST_STwri_cdnPt_nv_V4 :
2066  case Hexagon::POST_STwri_cPt_nv_V4 :
2067  case Hexagon::POST_STwri_cdnPt_V4 :
2068    return Hexagon::POST_STwri_cPt;
2069
2070  case Hexagon::POST_STwri_cdnNotPt_nv_V4 :
2071  case Hexagon::POST_STwri_cNotPt_nv_V4 :
2072  case Hexagon::POST_STwri_cdnNotPt_V4 :
2073    return Hexagon::POST_STwri_cNotPt;
2074
2075  case Hexagon::STw_GP_cdnPt_nv_V4:
2076  case Hexagon::STw_GP_cdnPt_V4:
2077  case Hexagon::STw_GP_cPt_nv_V4:
2078    return Hexagon::STw_GP_cPt_V4;
2079
2080  case Hexagon::STw_GP_cdnNotPt_nv_V4:
2081  case Hexagon::STw_GP_cdnNotPt_V4:
2082  case Hexagon::STw_GP_cNotPt_nv_V4:
2083    return Hexagon::STw_GP_cNotPt_V4;
2084
2085  case Hexagon::STriw_GP_cdnPt_nv_V4:
2086  case Hexagon::STriw_GP_cdnPt_V4:
2087  case Hexagon::STriw_GP_cPt_nv_V4:
2088    return Hexagon::STriw_GP_cPt_V4;
2089
2090  case Hexagon::STriw_GP_cdnNotPt_nv_V4:
2091  case Hexagon::STriw_GP_cdnNotPt_V4:
2092  case Hexagon::STriw_GP_cNotPt_nv_V4:
2093    return Hexagon::STriw_GP_cNotPt_V4;
2094
2095  // Store new-value word - unconditional
2096
2097  case Hexagon::STriw_nv_V4:
2098    return Hexagon::STriw;
2099
2100  case Hexagon::STriw_indexed_nv_V4:
2101    return Hexagon::STriw_indexed;
2102
2103  case Hexagon::STriw_indexed_shl_nv_V4:
2104    return Hexagon::STriw_indexed_shl_V4;
2105
2106  case Hexagon::STriw_shl_nv_V4:
2107    return Hexagon::STriw_shl_V4;
2108
2109  case Hexagon::STriw_GP_nv_V4:
2110    return Hexagon::STriw_GP_V4;
2111
2112  case Hexagon::STw_GP_nv_V4:
2113    return Hexagon::STw_GP_V4;
2114
2115  case Hexagon::POST_STwri_nv_V4:
2116    return Hexagon::POST_STwri;
2117
2118 // Store doubleword
2119
2120  case Hexagon::STrid_cdnPt_V4 :
2121    return Hexagon::STrid_cPt;
2122
2123  case Hexagon::STrid_cdnNotPt_V4 :
2124    return Hexagon::STrid_cNotPt;
2125
2126  case Hexagon::STrid_indexed_cdnPt_V4 :
2127    return Hexagon::STrid_indexed_cPt;
2128
2129  case Hexagon::STrid_indexed_cdnNotPt_V4 :
2130    return Hexagon::STrid_indexed_cNotPt;
2131
2132  case Hexagon::STrid_indexed_shl_cdnPt_V4 :
2133    return Hexagon::STrid_indexed_shl_cPt_V4;
2134
2135  case Hexagon::STrid_indexed_shl_cdnNotPt_V4 :
2136    return Hexagon::STrid_indexed_shl_cNotPt_V4;
2137
2138  case Hexagon::POST_STdri_cdnPt_V4 :
2139    return Hexagon::POST_STdri_cPt;
2140
2141  case Hexagon::POST_STdri_cdnNotPt_V4 :
2142    return Hexagon::POST_STdri_cNotPt;
2143
2144  case Hexagon::STd_GP_cdnPt_V4 :
2145    return Hexagon::STd_GP_cPt_V4;
2146
2147  case Hexagon::STd_GP_cdnNotPt_V4 :
2148    return Hexagon::STd_GP_cNotPt_V4;
2149
2150  case Hexagon::STrid_GP_cdnPt_V4 :
2151    return Hexagon::STrid_GP_cPt_V4;
2152
2153  case Hexagon::STrid_GP_cdnNotPt_V4 :
2154    return Hexagon::STrid_GP_cNotPt_V4;
2155  }
2156}
2157
2158bool HexagonPacketizerList::DemoteToDotOld(MachineInstr* MI) {
2159  const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
2160  int NewOpcode = GetDotOldOp(MI->getOpcode());
2161  MI->setDesc(QII->get(NewOpcode));
2162  return true;
2163}
2164
2165// Returns true if an instruction is predicated on p0 and false if it's
2166// predicated on !p0.
2167
2168static bool GetPredicateSense(MachineInstr* MI,
2169                              const HexagonInstrInfo *QII) {
2170
2171  switch (MI->getOpcode()) {
2172  case Hexagon::TFR_cPt:
2173  case Hexagon::TFR_cdnPt:
2174  case Hexagon::TFRI_cPt:
2175  case Hexagon::TFRI_cdnPt:
2176  case Hexagon::STrib_cPt :
2177  case Hexagon::STrib_cdnPt_V4 :
2178  case Hexagon::STrib_indexed_cPt :
2179  case Hexagon::STrib_indexed_cdnPt_V4 :
2180  case Hexagon::STrib_indexed_shl_cPt_V4 :
2181  case Hexagon::STrib_indexed_shl_cdnPt_V4 :
2182  case Hexagon::POST_STbri_cPt :
2183  case Hexagon::POST_STbri_cdnPt_V4 :
2184  case Hexagon::STrih_cPt :
2185  case Hexagon::STrih_cdnPt_V4 :
2186  case Hexagon::STrih_indexed_cPt :
2187  case Hexagon::STrih_indexed_cdnPt_V4 :
2188  case Hexagon::STrih_indexed_shl_cPt_V4 :
2189  case Hexagon::STrih_indexed_shl_cdnPt_V4 :
2190  case Hexagon::POST_SThri_cPt :
2191  case Hexagon::POST_SThri_cdnPt_V4 :
2192  case Hexagon::STriw_cPt :
2193  case Hexagon::STriw_cdnPt_V4 :
2194  case Hexagon::STriw_indexed_cPt :
2195  case Hexagon::STriw_indexed_cdnPt_V4 :
2196  case Hexagon::STriw_indexed_shl_cPt_V4 :
2197  case Hexagon::STriw_indexed_shl_cdnPt_V4 :
2198  case Hexagon::POST_STwri_cPt :
2199  case Hexagon::POST_STwri_cdnPt_V4 :
2200  case Hexagon::STrib_imm_cPt_V4 :
2201  case Hexagon::STrib_imm_cdnPt_V4 :
2202  case Hexagon::STrid_cPt :
2203  case Hexagon::STrid_cdnPt_V4 :
2204  case Hexagon::STrid_indexed_cPt :
2205  case Hexagon::STrid_indexed_cdnPt_V4 :
2206  case Hexagon::STrid_indexed_shl_cPt_V4 :
2207  case Hexagon::STrid_indexed_shl_cdnPt_V4 :
2208  case Hexagon::POST_STdri_cPt :
2209  case Hexagon::POST_STdri_cdnPt_V4 :
2210  case Hexagon::STrih_imm_cPt_V4 :
2211  case Hexagon::STrih_imm_cdnPt_V4 :
2212  case Hexagon::STriw_imm_cPt_V4 :
2213  case Hexagon::STriw_imm_cdnPt_V4 :
2214  case Hexagon::JMP_cdnPt :
2215  case Hexagon::LDrid_cPt :
2216  case Hexagon::LDrid_cdnPt :
2217  case Hexagon::LDrid_indexed_cPt :
2218  case Hexagon::LDrid_indexed_cdnPt :
2219  case Hexagon::POST_LDrid_cPt :
2220  case Hexagon::POST_LDrid_cdnPt_V4 :
2221  case Hexagon::LDriw_cPt :
2222  case Hexagon::LDriw_cdnPt :
2223  case Hexagon::LDriw_indexed_cPt :
2224  case Hexagon::LDriw_indexed_cdnPt :
2225  case Hexagon::POST_LDriw_cPt :
2226  case Hexagon::POST_LDriw_cdnPt_V4 :
2227  case Hexagon::LDrih_cPt :
2228  case Hexagon::LDrih_cdnPt :
2229  case Hexagon::LDrih_indexed_cPt :
2230  case Hexagon::LDrih_indexed_cdnPt :
2231  case Hexagon::POST_LDrih_cPt :
2232  case Hexagon::POST_LDrih_cdnPt_V4 :
2233  case Hexagon::LDrib_cPt :
2234  case Hexagon::LDrib_cdnPt :
2235  case Hexagon::LDrib_indexed_cPt :
2236  case Hexagon::LDrib_indexed_cdnPt :
2237  case Hexagon::POST_LDrib_cPt :
2238  case Hexagon::POST_LDrib_cdnPt_V4 :
2239  case Hexagon::LDriuh_cPt :
2240  case Hexagon::LDriuh_cdnPt :
2241  case Hexagon::LDriuh_indexed_cPt :
2242  case Hexagon::LDriuh_indexed_cdnPt :
2243  case Hexagon::POST_LDriuh_cPt :
2244  case Hexagon::POST_LDriuh_cdnPt_V4 :
2245  case Hexagon::LDriub_cPt :
2246  case Hexagon::LDriub_cdnPt :
2247  case Hexagon::LDriub_indexed_cPt :
2248  case Hexagon::LDriub_indexed_cdnPt :
2249  case Hexagon::POST_LDriub_cPt :
2250  case Hexagon::POST_LDriub_cdnPt_V4 :
2251  case Hexagon::LDrid_indexed_cPt_V4 :
2252  case Hexagon::LDrid_indexed_cdnPt_V4 :
2253  case Hexagon::LDrid_indexed_shl_cPt_V4 :
2254  case Hexagon::LDrid_indexed_shl_cdnPt_V4 :
2255  case Hexagon::LDrib_indexed_cPt_V4 :
2256  case Hexagon::LDrib_indexed_cdnPt_V4 :
2257  case Hexagon::LDrib_indexed_shl_cPt_V4 :
2258  case Hexagon::LDrib_indexed_shl_cdnPt_V4 :
2259  case Hexagon::LDriub_indexed_cPt_V4 :
2260  case Hexagon::LDriub_indexed_cdnPt_V4 :
2261  case Hexagon::LDriub_indexed_shl_cPt_V4 :
2262  case Hexagon::LDriub_indexed_shl_cdnPt_V4 :
2263  case Hexagon::LDrih_indexed_cPt_V4 :
2264  case Hexagon::LDrih_indexed_cdnPt_V4 :
2265  case Hexagon::LDrih_indexed_shl_cPt_V4 :
2266  case Hexagon::LDrih_indexed_shl_cdnPt_V4 :
2267  case Hexagon::LDriuh_indexed_cPt_V4 :
2268  case Hexagon::LDriuh_indexed_cdnPt_V4 :
2269  case Hexagon::LDriuh_indexed_shl_cPt_V4 :
2270  case Hexagon::LDriuh_indexed_shl_cdnPt_V4 :
2271  case Hexagon::LDriw_indexed_cPt_V4 :
2272  case Hexagon::LDriw_indexed_cdnPt_V4 :
2273  case Hexagon::LDriw_indexed_shl_cPt_V4 :
2274  case Hexagon::LDriw_indexed_shl_cdnPt_V4 :
2275  case Hexagon::ADD_ri_cPt :
2276  case Hexagon::ADD_ri_cdnPt :
2277  case Hexagon::ADD_rr_cPt :
2278  case Hexagon::ADD_rr_cdnPt :
2279  case Hexagon::XOR_rr_cPt :
2280  case Hexagon::XOR_rr_cdnPt :
2281  case Hexagon::AND_rr_cPt :
2282  case Hexagon::AND_rr_cdnPt :
2283  case Hexagon::OR_rr_cPt :
2284  case Hexagon::OR_rr_cdnPt :
2285  case Hexagon::SUB_rr_cPt :
2286  case Hexagon::SUB_rr_cdnPt :
2287  case Hexagon::COMBINE_rr_cPt :
2288  case Hexagon::COMBINE_rr_cdnPt :
2289  case Hexagon::ASLH_cPt_V4 :
2290  case Hexagon::ASLH_cdnPt_V4 :
2291  case Hexagon::ASRH_cPt_V4 :
2292  case Hexagon::ASRH_cdnPt_V4 :
2293  case Hexagon::SXTB_cPt_V4 :
2294  case Hexagon::SXTB_cdnPt_V4 :
2295  case Hexagon::SXTH_cPt_V4 :
2296  case Hexagon::SXTH_cdnPt_V4 :
2297  case Hexagon::ZXTB_cPt_V4 :
2298  case Hexagon::ZXTB_cdnPt_V4 :
2299  case Hexagon::ZXTH_cPt_V4 :
2300  case Hexagon::ZXTH_cdnPt_V4 :
2301  case Hexagon::LDrid_GP_cPt_V4 :
2302  case Hexagon::LDrib_GP_cPt_V4 :
2303  case Hexagon::LDriub_GP_cPt_V4 :
2304  case Hexagon::LDrih_GP_cPt_V4 :
2305  case Hexagon::LDriuh_GP_cPt_V4 :
2306  case Hexagon::LDriw_GP_cPt_V4 :
2307  case Hexagon::LDd_GP_cPt_V4 :
2308  case Hexagon::LDb_GP_cPt_V4 :
2309  case Hexagon::LDub_GP_cPt_V4 :
2310  case Hexagon::LDh_GP_cPt_V4 :
2311  case Hexagon::LDuh_GP_cPt_V4 :
2312  case Hexagon::LDw_GP_cPt_V4 :
2313  case Hexagon::STrid_GP_cPt_V4 :
2314  case Hexagon::STrib_GP_cPt_V4 :
2315  case Hexagon::STrih_GP_cPt_V4 :
2316  case Hexagon::STriw_GP_cPt_V4 :
2317  case Hexagon::STd_GP_cPt_V4 :
2318  case Hexagon::STb_GP_cPt_V4 :
2319  case Hexagon::STh_GP_cPt_V4 :
2320  case Hexagon::STw_GP_cPt_V4 :
2321  case Hexagon::LDrid_GP_cdnPt_V4 :
2322  case Hexagon::LDrib_GP_cdnPt_V4 :
2323  case Hexagon::LDriub_GP_cdnPt_V4 :
2324  case Hexagon::LDrih_GP_cdnPt_V4 :
2325  case Hexagon::LDriuh_GP_cdnPt_V4 :
2326  case Hexagon::LDriw_GP_cdnPt_V4 :
2327  case Hexagon::LDd_GP_cdnPt_V4 :
2328  case Hexagon::LDb_GP_cdnPt_V4 :
2329  case Hexagon::LDub_GP_cdnPt_V4 :
2330  case Hexagon::LDh_GP_cdnPt_V4 :
2331  case Hexagon::LDuh_GP_cdnPt_V4 :
2332  case Hexagon::LDw_GP_cdnPt_V4 :
2333  case Hexagon::STrid_GP_cdnPt_V4 :
2334  case Hexagon::STrib_GP_cdnPt_V4 :
2335  case Hexagon::STrih_GP_cdnPt_V4 :
2336  case Hexagon::STriw_GP_cdnPt_V4 :
2337  case Hexagon::STd_GP_cdnPt_V4 :
2338  case Hexagon::STb_GP_cdnPt_V4 :
2339  case Hexagon::STh_GP_cdnPt_V4 :
2340  case Hexagon::STw_GP_cdnPt_V4 :
2341    return true;
2342
2343  case Hexagon::TFR_cNotPt:
2344  case Hexagon::TFR_cdnNotPt:
2345  case Hexagon::TFRI_cNotPt:
2346  case Hexagon::TFRI_cdnNotPt:
2347  case Hexagon::STrib_cNotPt :
2348  case Hexagon::STrib_cdnNotPt_V4 :
2349  case Hexagon::STrib_indexed_cNotPt :
2350  case Hexagon::STrib_indexed_cdnNotPt_V4 :
2351  case Hexagon::STrib_indexed_shl_cNotPt_V4 :
2352  case Hexagon::STrib_indexed_shl_cdnNotPt_V4 :
2353  case Hexagon::POST_STbri_cNotPt :
2354  case Hexagon::POST_STbri_cdnNotPt_V4 :
2355  case Hexagon::STrih_cNotPt :
2356  case Hexagon::STrih_cdnNotPt_V4 :
2357  case Hexagon::STrih_indexed_cNotPt :
2358  case Hexagon::STrih_indexed_cdnNotPt_V4 :
2359  case Hexagon::STrih_indexed_shl_cNotPt_V4 :
2360  case Hexagon::STrih_indexed_shl_cdnNotPt_V4 :
2361  case Hexagon::POST_SThri_cNotPt :
2362  case Hexagon::POST_SThri_cdnNotPt_V4 :
2363  case Hexagon::STriw_cNotPt :
2364  case Hexagon::STriw_cdnNotPt_V4 :
2365  case Hexagon::STriw_indexed_cNotPt :
2366  case Hexagon::STriw_indexed_cdnNotPt_V4 :
2367  case Hexagon::STriw_indexed_shl_cNotPt_V4 :
2368  case Hexagon::STriw_indexed_shl_cdnNotPt_V4 :
2369  case Hexagon::POST_STwri_cNotPt :
2370  case Hexagon::POST_STwri_cdnNotPt_V4 :
2371  case Hexagon::STrib_imm_cNotPt_V4 :
2372  case Hexagon::STrib_imm_cdnNotPt_V4 :
2373  case Hexagon::STrid_cNotPt :
2374  case Hexagon::STrid_cdnNotPt_V4 :
2375  case Hexagon::STrid_indexed_cdnNotPt_V4 :
2376  case Hexagon::STrid_indexed_cNotPt :
2377  case Hexagon::STrid_indexed_shl_cNotPt_V4 :
2378  case Hexagon::STrid_indexed_shl_cdnNotPt_V4 :
2379  case Hexagon::POST_STdri_cNotPt :
2380  case Hexagon::POST_STdri_cdnNotPt_V4 :
2381  case Hexagon::STrih_imm_cNotPt_V4 :
2382  case Hexagon::STrih_imm_cdnNotPt_V4 :
2383  case Hexagon::STriw_imm_cNotPt_V4 :
2384  case Hexagon::STriw_imm_cdnNotPt_V4 :
2385  case Hexagon::JMP_cdnNotPt :
2386  case Hexagon::LDrid_cNotPt :
2387  case Hexagon::LDrid_cdnNotPt :
2388  case Hexagon::LDrid_indexed_cNotPt :
2389  case Hexagon::LDrid_indexed_cdnNotPt :
2390  case Hexagon::POST_LDrid_cNotPt :
2391  case Hexagon::POST_LDrid_cdnNotPt_V4 :
2392  case Hexagon::LDriw_cNotPt :
2393  case Hexagon::LDriw_cdnNotPt :
2394  case Hexagon::LDriw_indexed_cNotPt :
2395  case Hexagon::LDriw_indexed_cdnNotPt :
2396  case Hexagon::POST_LDriw_cNotPt :
2397  case Hexagon::POST_LDriw_cdnNotPt_V4 :
2398  case Hexagon::LDrih_cNotPt :
2399  case Hexagon::LDrih_cdnNotPt :
2400  case Hexagon::LDrih_indexed_cNotPt :
2401  case Hexagon::LDrih_indexed_cdnNotPt :
2402  case Hexagon::POST_LDrih_cNotPt :
2403  case Hexagon::POST_LDrih_cdnNotPt_V4 :
2404  case Hexagon::LDrib_cNotPt :
2405  case Hexagon::LDrib_cdnNotPt :
2406  case Hexagon::LDrib_indexed_cNotPt :
2407  case Hexagon::LDrib_indexed_cdnNotPt :
2408  case Hexagon::POST_LDrib_cNotPt :
2409  case Hexagon::POST_LDrib_cdnNotPt_V4 :
2410  case Hexagon::LDriuh_cNotPt :
2411  case Hexagon::LDriuh_cdnNotPt :
2412  case Hexagon::LDriuh_indexed_cNotPt :
2413  case Hexagon::LDriuh_indexed_cdnNotPt :
2414  case Hexagon::POST_LDriuh_cNotPt :
2415  case Hexagon::POST_LDriuh_cdnNotPt_V4 :
2416  case Hexagon::LDriub_cNotPt :
2417  case Hexagon::LDriub_cdnNotPt :
2418  case Hexagon::LDriub_indexed_cNotPt :
2419  case Hexagon::LDriub_indexed_cdnNotPt :
2420  case Hexagon::POST_LDriub_cNotPt :
2421  case Hexagon::POST_LDriub_cdnNotPt_V4 :
2422  case Hexagon::LDrid_indexed_cNotPt_V4 :
2423  case Hexagon::LDrid_indexed_cdnNotPt_V4 :
2424  case Hexagon::LDrid_indexed_shl_cNotPt_V4 :
2425  case Hexagon::LDrid_indexed_shl_cdnNotPt_V4 :
2426  case Hexagon::LDrib_indexed_cNotPt_V4 :
2427  case Hexagon::LDrib_indexed_cdnNotPt_V4 :
2428  case Hexagon::LDrib_indexed_shl_cNotPt_V4 :
2429  case Hexagon::LDrib_indexed_shl_cdnNotPt_V4 :
2430  case Hexagon::LDriub_indexed_cNotPt_V4 :
2431  case Hexagon::LDriub_indexed_cdnNotPt_V4 :
2432  case Hexagon::LDriub_indexed_shl_cNotPt_V4 :
2433  case Hexagon::LDriub_indexed_shl_cdnNotPt_V4 :
2434  case Hexagon::LDrih_indexed_cNotPt_V4 :
2435  case Hexagon::LDrih_indexed_cdnNotPt_V4 :
2436  case Hexagon::LDrih_indexed_shl_cNotPt_V4 :
2437  case Hexagon::LDrih_indexed_shl_cdnNotPt_V4 :
2438  case Hexagon::LDriuh_indexed_cNotPt_V4 :
2439  case Hexagon::LDriuh_indexed_cdnNotPt_V4 :
2440  case Hexagon::LDriuh_indexed_shl_cNotPt_V4 :
2441  case Hexagon::LDriuh_indexed_shl_cdnNotPt_V4 :
2442  case Hexagon::LDriw_indexed_cNotPt_V4 :
2443  case Hexagon::LDriw_indexed_cdnNotPt_V4 :
2444  case Hexagon::LDriw_indexed_shl_cNotPt_V4 :
2445  case Hexagon::LDriw_indexed_shl_cdnNotPt_V4 :
2446  case Hexagon::ADD_ri_cNotPt :
2447  case Hexagon::ADD_ri_cdnNotPt :
2448  case Hexagon::ADD_rr_cNotPt :
2449  case Hexagon::ADD_rr_cdnNotPt :
2450  case Hexagon::XOR_rr_cNotPt :
2451  case Hexagon::XOR_rr_cdnNotPt :
2452  case Hexagon::AND_rr_cNotPt :
2453  case Hexagon::AND_rr_cdnNotPt :
2454  case Hexagon::OR_rr_cNotPt :
2455  case Hexagon::OR_rr_cdnNotPt :
2456  case Hexagon::SUB_rr_cNotPt :
2457  case Hexagon::SUB_rr_cdnNotPt :
2458  case Hexagon::COMBINE_rr_cNotPt :
2459  case Hexagon::COMBINE_rr_cdnNotPt :
2460  case Hexagon::ASLH_cNotPt_V4 :
2461  case Hexagon::ASLH_cdnNotPt_V4 :
2462  case Hexagon::ASRH_cNotPt_V4 :
2463  case Hexagon::ASRH_cdnNotPt_V4 :
2464  case Hexagon::SXTB_cNotPt_V4 :
2465  case Hexagon::SXTB_cdnNotPt_V4 :
2466  case Hexagon::SXTH_cNotPt_V4 :
2467  case Hexagon::SXTH_cdnNotPt_V4 :
2468  case Hexagon::ZXTB_cNotPt_V4 :
2469  case Hexagon::ZXTB_cdnNotPt_V4 :
2470  case Hexagon::ZXTH_cNotPt_V4 :
2471  case Hexagon::ZXTH_cdnNotPt_V4 :
2472
2473  case Hexagon::LDrid_GP_cNotPt_V4 :
2474  case Hexagon::LDrib_GP_cNotPt_V4 :
2475  case Hexagon::LDriub_GP_cNotPt_V4 :
2476  case Hexagon::LDrih_GP_cNotPt_V4 :
2477  case Hexagon::LDriuh_GP_cNotPt_V4 :
2478  case Hexagon::LDriw_GP_cNotPt_V4 :
2479  case Hexagon::LDd_GP_cNotPt_V4 :
2480  case Hexagon::LDb_GP_cNotPt_V4 :
2481  case Hexagon::LDub_GP_cNotPt_V4 :
2482  case Hexagon::LDh_GP_cNotPt_V4 :
2483  case Hexagon::LDuh_GP_cNotPt_V4 :
2484  case Hexagon::LDw_GP_cNotPt_V4 :
2485  case Hexagon::STrid_GP_cNotPt_V4 :
2486  case Hexagon::STrib_GP_cNotPt_V4 :
2487  case Hexagon::STrih_GP_cNotPt_V4 :
2488  case Hexagon::STriw_GP_cNotPt_V4 :
2489  case Hexagon::STd_GP_cNotPt_V4 :
2490  case Hexagon::STb_GP_cNotPt_V4 :
2491  case Hexagon::STh_GP_cNotPt_V4 :
2492  case Hexagon::STw_GP_cNotPt_V4 :
2493  case Hexagon::LDrid_GP_cdnNotPt_V4 :
2494  case Hexagon::LDrib_GP_cdnNotPt_V4 :
2495  case Hexagon::LDriub_GP_cdnNotPt_V4 :
2496  case Hexagon::LDrih_GP_cdnNotPt_V4 :
2497  case Hexagon::LDriuh_GP_cdnNotPt_V4 :
2498  case Hexagon::LDriw_GP_cdnNotPt_V4 :
2499  case Hexagon::LDd_GP_cdnNotPt_V4 :
2500  case Hexagon::LDb_GP_cdnNotPt_V4 :
2501  case Hexagon::LDub_GP_cdnNotPt_V4 :
2502  case Hexagon::LDh_GP_cdnNotPt_V4 :
2503  case Hexagon::LDuh_GP_cdnNotPt_V4 :
2504  case Hexagon::LDw_GP_cdnNotPt_V4 :
2505  case Hexagon::STrid_GP_cdnNotPt_V4 :
2506  case Hexagon::STrib_GP_cdnNotPt_V4 :
2507  case Hexagon::STrih_GP_cdnNotPt_V4 :
2508  case Hexagon::STriw_GP_cdnNotPt_V4 :
2509  case Hexagon::STd_GP_cdnNotPt_V4 :
2510  case Hexagon::STb_GP_cdnNotPt_V4 :
2511  case Hexagon::STh_GP_cdnNotPt_V4 :
2512  case Hexagon::STw_GP_cdnNotPt_V4 :
2513    return false;
2514
2515  default:
2516    assert (false && "Unknown predicate sense of the instruction");
2517  }
2518  // return *some value* to avoid compiler warning
2519  return false;
2520}
2521
2522bool HexagonPacketizerList::isDotNewInst(MachineInstr* MI) {
2523  if (isNewValueInst(MI))
2524    return true;
2525
2526  switch (MI->getOpcode()) {
2527  case Hexagon::TFR_cdnNotPt:
2528  case Hexagon::TFR_cdnPt:
2529  case Hexagon::TFRI_cdnNotPt:
2530  case Hexagon::TFRI_cdnPt:
2531  case Hexagon::LDrid_cdnPt :
2532  case Hexagon::LDrid_cdnNotPt :
2533  case Hexagon::LDrid_indexed_cdnPt :
2534  case Hexagon::LDrid_indexed_cdnNotPt :
2535  case Hexagon::POST_LDrid_cdnPt_V4 :
2536  case Hexagon::POST_LDrid_cdnNotPt_V4 :
2537  case Hexagon::LDriw_cdnPt :
2538  case Hexagon::LDriw_cdnNotPt :
2539  case Hexagon::LDriw_indexed_cdnPt :
2540  case Hexagon::LDriw_indexed_cdnNotPt :
2541  case Hexagon::POST_LDriw_cdnPt_V4 :
2542  case Hexagon::POST_LDriw_cdnNotPt_V4 :
2543  case Hexagon::LDrih_cdnPt :
2544  case Hexagon::LDrih_cdnNotPt :
2545  case Hexagon::LDrih_indexed_cdnPt :
2546  case Hexagon::LDrih_indexed_cdnNotPt :
2547  case Hexagon::POST_LDrih_cdnPt_V4 :
2548  case Hexagon::POST_LDrih_cdnNotPt_V4 :
2549  case Hexagon::LDrib_cdnPt :
2550  case Hexagon::LDrib_cdnNotPt :
2551  case Hexagon::LDrib_indexed_cdnPt :
2552  case Hexagon::LDrib_indexed_cdnNotPt :
2553  case Hexagon::POST_LDrib_cdnPt_V4 :
2554  case Hexagon::POST_LDrib_cdnNotPt_V4 :
2555  case Hexagon::LDriuh_cdnPt :
2556  case Hexagon::LDriuh_cdnNotPt :
2557  case Hexagon::LDriuh_indexed_cdnPt :
2558  case Hexagon::LDriuh_indexed_cdnNotPt :
2559  case Hexagon::POST_LDriuh_cdnPt_V4 :
2560  case Hexagon::POST_LDriuh_cdnNotPt_V4 :
2561  case Hexagon::LDriub_cdnPt :
2562  case Hexagon::LDriub_cdnNotPt :
2563  case Hexagon::LDriub_indexed_cdnPt :
2564  case Hexagon::LDriub_indexed_cdnNotPt :
2565  case Hexagon::POST_LDriub_cdnPt_V4 :
2566  case Hexagon::POST_LDriub_cdnNotPt_V4 :
2567
2568  case Hexagon::LDrid_indexed_cdnPt_V4 :
2569  case Hexagon::LDrid_indexed_cdnNotPt_V4 :
2570  case Hexagon::LDrid_indexed_shl_cdnPt_V4 :
2571  case Hexagon::LDrid_indexed_shl_cdnNotPt_V4 :
2572  case Hexagon::LDrib_indexed_cdnPt_V4 :
2573  case Hexagon::LDrib_indexed_cdnNotPt_V4 :
2574  case Hexagon::LDrib_indexed_shl_cdnPt_V4 :
2575  case Hexagon::LDrib_indexed_shl_cdnNotPt_V4 :
2576  case Hexagon::LDriub_indexed_cdnPt_V4 :
2577  case Hexagon::LDriub_indexed_cdnNotPt_V4 :
2578  case Hexagon::LDriub_indexed_shl_cdnPt_V4 :
2579  case Hexagon::LDriub_indexed_shl_cdnNotPt_V4 :
2580  case Hexagon::LDrih_indexed_cdnPt_V4 :
2581  case Hexagon::LDrih_indexed_cdnNotPt_V4 :
2582  case Hexagon::LDrih_indexed_shl_cdnPt_V4 :
2583  case Hexagon::LDrih_indexed_shl_cdnNotPt_V4 :
2584  case Hexagon::LDriuh_indexed_cdnPt_V4 :
2585  case Hexagon::LDriuh_indexed_cdnNotPt_V4 :
2586  case Hexagon::LDriuh_indexed_shl_cdnPt_V4 :
2587  case Hexagon::LDriuh_indexed_shl_cdnNotPt_V4 :
2588  case Hexagon::LDriw_indexed_cdnPt_V4 :
2589  case Hexagon::LDriw_indexed_cdnNotPt_V4 :
2590  case Hexagon::LDriw_indexed_shl_cdnPt_V4 :
2591  case Hexagon::LDriw_indexed_shl_cdnNotPt_V4 :
2592
2593// Coditional add
2594  case Hexagon::ADD_ri_cdnPt:
2595  case Hexagon::ADD_ri_cdnNotPt:
2596  case Hexagon::ADD_rr_cdnPt:
2597  case Hexagon::ADD_rr_cdnNotPt:
2598
2599  // Conditional logical operations
2600  case Hexagon::XOR_rr_cdnPt :
2601  case Hexagon::XOR_rr_cdnNotPt :
2602  case Hexagon::AND_rr_cdnPt :
2603  case Hexagon::AND_rr_cdnNotPt :
2604  case Hexagon::OR_rr_cdnPt :
2605  case Hexagon::OR_rr_cdnNotPt :
2606
2607  // Conditonal subtract
2608  case Hexagon::SUB_rr_cdnPt :
2609  case Hexagon::SUB_rr_cdnNotPt :
2610
2611  // Conditional combine
2612  case Hexagon::COMBINE_rr_cdnPt :
2613  case Hexagon::COMBINE_rr_cdnNotPt :
2614
2615  // Conditional shift operations
2616  case Hexagon::ASLH_cdnPt_V4:
2617  case Hexagon::ASLH_cdnNotPt_V4:
2618  case Hexagon::ASRH_cdnPt_V4:
2619  case Hexagon::ASRH_cdnNotPt_V4:
2620  case Hexagon::SXTB_cdnPt_V4:
2621  case Hexagon::SXTB_cdnNotPt_V4:
2622  case Hexagon::SXTH_cdnPt_V4:
2623  case Hexagon::SXTH_cdnNotPt_V4:
2624  case Hexagon::ZXTB_cdnPt_V4:
2625  case Hexagon::ZXTB_cdnNotPt_V4:
2626  case Hexagon::ZXTH_cdnPt_V4:
2627  case Hexagon::ZXTH_cdnNotPt_V4:
2628
2629  // Conditional stores
2630  case Hexagon::STrib_imm_cdnPt_V4 :
2631  case Hexagon::STrib_imm_cdnNotPt_V4 :
2632  case Hexagon::STrib_cdnPt_V4 :
2633  case Hexagon::STrib_cdnNotPt_V4 :
2634  case Hexagon::STrib_indexed_cdnPt_V4 :
2635  case Hexagon::STrib_indexed_cdnNotPt_V4 :
2636  case Hexagon::POST_STbri_cdnPt_V4 :
2637  case Hexagon::POST_STbri_cdnNotPt_V4 :
2638  case Hexagon::STrib_indexed_shl_cdnPt_V4 :
2639  case Hexagon::STrib_indexed_shl_cdnNotPt_V4 :
2640
2641  // Store doubleword conditionally
2642  case Hexagon::STrid_indexed_cdnPt_V4 :
2643  case Hexagon::STrid_indexed_cdnNotPt_V4 :
2644  case Hexagon::STrid_indexed_shl_cdnPt_V4 :
2645  case Hexagon::STrid_indexed_shl_cdnNotPt_V4 :
2646  case Hexagon::POST_STdri_cdnPt_V4 :
2647  case Hexagon::POST_STdri_cdnNotPt_V4 :
2648
2649  // Store halfword conditionally
2650  case Hexagon::STrih_cdnPt_V4 :
2651  case Hexagon::STrih_cdnNotPt_V4 :
2652  case Hexagon::STrih_indexed_cdnPt_V4 :
2653  case Hexagon::STrih_indexed_cdnNotPt_V4 :
2654  case Hexagon::STrih_imm_cdnPt_V4 :
2655  case Hexagon::STrih_imm_cdnNotPt_V4 :
2656  case Hexagon::STrih_indexed_shl_cdnPt_V4 :
2657  case Hexagon::STrih_indexed_shl_cdnNotPt_V4 :
2658  case Hexagon::POST_SThri_cdnPt_V4 :
2659  case Hexagon::POST_SThri_cdnNotPt_V4 :
2660
2661  // Store word conditionally
2662  case Hexagon::STriw_cdnPt_V4 :
2663  case Hexagon::STriw_cdnNotPt_V4 :
2664  case Hexagon::STriw_indexed_cdnPt_V4 :
2665  case Hexagon::STriw_indexed_cdnNotPt_V4 :
2666  case Hexagon::STriw_imm_cdnPt_V4 :
2667  case Hexagon::STriw_imm_cdnNotPt_V4 :
2668  case Hexagon::STriw_indexed_shl_cdnPt_V4 :
2669  case Hexagon::STriw_indexed_shl_cdnNotPt_V4 :
2670  case Hexagon::POST_STwri_cdnPt_V4 :
2671  case Hexagon::POST_STwri_cdnNotPt_V4 :
2672
2673  case Hexagon::LDd_GP_cdnPt_V4:
2674  case Hexagon::LDd_GP_cdnNotPt_V4:
2675  case Hexagon::LDb_GP_cdnPt_V4:
2676  case Hexagon::LDb_GP_cdnNotPt_V4:
2677  case Hexagon::LDub_GP_cdnPt_V4:
2678  case Hexagon::LDub_GP_cdnNotPt_V4:
2679  case Hexagon::LDh_GP_cdnPt_V4:
2680  case Hexagon::LDh_GP_cdnNotPt_V4:
2681  case Hexagon::LDuh_GP_cdnPt_V4:
2682  case Hexagon::LDuh_GP_cdnNotPt_V4:
2683  case Hexagon::LDw_GP_cdnPt_V4:
2684  case Hexagon::LDw_GP_cdnNotPt_V4:
2685  case Hexagon::LDrid_GP_cdnPt_V4:
2686  case Hexagon::LDrid_GP_cdnNotPt_V4:
2687  case Hexagon::LDrib_GP_cdnPt_V4:
2688  case Hexagon::LDrib_GP_cdnNotPt_V4:
2689  case Hexagon::LDriub_GP_cdnPt_V4:
2690  case Hexagon::LDriub_GP_cdnNotPt_V4:
2691  case Hexagon::LDrih_GP_cdnPt_V4:
2692  case Hexagon::LDrih_GP_cdnNotPt_V4:
2693  case Hexagon::LDriuh_GP_cdnPt_V4:
2694  case Hexagon::LDriuh_GP_cdnNotPt_V4:
2695  case Hexagon::LDriw_GP_cdnPt_V4:
2696  case Hexagon::LDriw_GP_cdnNotPt_V4:
2697
2698  case Hexagon::STrid_GP_cdnPt_V4:
2699  case Hexagon::STrid_GP_cdnNotPt_V4:
2700  case Hexagon::STrib_GP_cdnPt_V4:
2701  case Hexagon::STrib_GP_cdnNotPt_V4:
2702  case Hexagon::STrih_GP_cdnPt_V4:
2703  case Hexagon::STrih_GP_cdnNotPt_V4:
2704  case Hexagon::STriw_GP_cdnPt_V4:
2705  case Hexagon::STriw_GP_cdnNotPt_V4:
2706  case Hexagon::STd_GP_cdnPt_V4:
2707  case Hexagon::STd_GP_cdnNotPt_V4:
2708  case Hexagon::STb_GP_cdnPt_V4:
2709  case Hexagon::STb_GP_cdnNotPt_V4:
2710  case Hexagon::STh_GP_cdnPt_V4:
2711  case Hexagon::STh_GP_cdnNotPt_V4:
2712  case Hexagon::STw_GP_cdnPt_V4:
2713  case Hexagon::STw_GP_cdnNotPt_V4:
2714
2715    return true;
2716  }
2717  return false;
2718}
2719
2720static MachineOperand& GetPostIncrementOperand(MachineInstr *MI,
2721                                               const HexagonInstrInfo *QII) {
2722  assert(QII->isPostIncrement(MI) && "Not a post increment operation.");
2723#ifndef NDEBUG
2724  // Post Increment means duplicates. Use dense map to find duplicates in the
2725  // list. Caution: Densemap initializes with the minimum of 64 buckets,
2726  // whereas there are at most 5 operands in the post increment.
2727  DenseMap<unsigned,  unsigned> DefRegsSet;
2728  for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++)
2729    if (MI->getOperand(opNum).isReg() &&
2730        MI->getOperand(opNum).isDef()) {
2731      DefRegsSet[MI->getOperand(opNum).getReg()] = 1;
2732    }
2733
2734  for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++)
2735    if (MI->getOperand(opNum).isReg() &&
2736        MI->getOperand(opNum).isUse()) {
2737      if (DefRegsSet[MI->getOperand(opNum).getReg()]) {
2738        return MI->getOperand(opNum);
2739      }
2740    }
2741#else
2742  if (MI->getDesc().mayLoad()) {
2743    // The 2nd operand is always the post increment operand in load.
2744    assert(MI->getOperand(1).isReg() &&
2745                "Post increment operand has be to a register.");
2746    return (MI->getOperand(1));
2747  }
2748  if (MI->getDesc().mayStore()) {
2749    // The 1st operand is always the post increment operand in store.
2750    assert(MI->getOperand(0).isReg() &&
2751                "Post increment operand has be to a register.");
2752    return (MI->getOperand(0));
2753  }
2754#endif
2755  // we should never come here.
2756  llvm_unreachable("mayLoad or mayStore not set for Post Increment operation");
2757}
2758
2759// get the value being stored
2760static MachineOperand& GetStoreValueOperand(MachineInstr *MI) {
2761  // value being stored is always the last operand.
2762  return (MI->getOperand(MI->getNumOperands()-1));
2763}
2764
2765// can be new value store?
2766// Following restrictions are to be respected in convert a store into
2767// a new value store.
2768// 1. If an instruction uses auto-increment, its address register cannot
2769//    be a new-value register. Arch Spec 5.4.2.1
2770// 2. If an instruction uses absolute-set addressing mode,
2771//    its address register cannot be a new-value register.
2772//    Arch Spec 5.4.2.1.TODO: This is not enabled as
2773//    as absolute-set address mode patters are not implemented.
2774// 3. If an instruction produces a 64-bit result, its registers cannot be used
2775//    as new-value registers. Arch Spec 5.4.2.2.
2776// 4. If the instruction that sets a new-value register is conditional, then
2777//    the instruction that uses the new-value register must also be conditional,
2778//    and both must always have their predicates evaluate identically.
2779//    Arch Spec 5.4.2.3.
2780// 5. There is an implied restriction of a packet can not have another store,
2781//    if there is a  new value store in the packet. Corollary, if there is
2782//    already a store in a packet, there can not be a new value store.
2783//    Arch Spec: 3.4.4.2
2784bool HexagonPacketizerList::CanPromoteToNewValueStore( MachineInstr *MI,
2785                MachineInstr *PacketMI, unsigned DepReg,
2786                std::map <MachineInstr*, SUnit*> MIToSUnit)
2787{
2788  // Make sure we are looking at the store
2789  if (!IsNewifyStore(MI))
2790    return false;
2791
2792  // Make sure there is dependency and can be new value'ed
2793  if (GetStoreValueOperand(MI).isReg() &&
2794      GetStoreValueOperand(MI).getReg() != DepReg)
2795    return false;
2796
2797  const HexagonRegisterInfo* QRI = (const HexagonRegisterInfo *) TM.getRegisterInfo();
2798  const MCInstrDesc& MCID = PacketMI->getDesc();
2799  // first operand is always the result
2800
2801  const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
2802  const TargetRegisterClass* PacketRC = QII->getRegClass(MCID, 0, QRI);
2803
2804  // if there is already an store in the packet, no can do new value store
2805  // Arch Spec 3.4.4.2.
2806  for (std::vector<MachineInstr*>::iterator VI = CurrentPacketMIs.begin(),
2807         VE = CurrentPacketMIs.end();
2808       (VI != VE); ++VI) {
2809    SUnit* PacketSU = MIToSUnit[*VI];
2810    if (PacketSU->getInstr()->getDesc().mayStore() ||
2811        // if we have mayStore = 1 set on ALLOCFRAME and DEALLOCFRAME,
2812        // then we don't need this
2813        PacketSU->getInstr()->getOpcode() == Hexagon::ALLOCFRAME ||
2814        PacketSU->getInstr()->getOpcode() == Hexagon::DEALLOCFRAME)
2815      return false;
2816  }
2817
2818  if (PacketRC == Hexagon::DoubleRegsRegisterClass) {
2819    // new value store constraint: double regs can not feed into new value store
2820    // arch spec section: 5.4.2.2
2821    return false;
2822  }
2823
2824  // Make sure it's NOT the post increment register that we are going to
2825  // new value.
2826  if (QII->isPostIncrement(MI) &&
2827      MI->getDesc().mayStore() &&
2828      GetPostIncrementOperand(MI, QII).getReg() == DepReg) {
2829    return false;
2830  }
2831
2832  if (QII->isPostIncrement(PacketMI) &&
2833      PacketMI->getDesc().mayLoad() &&
2834      GetPostIncrementOperand(PacketMI, QII).getReg() == DepReg) {
2835    // if source is post_inc, or absolute-set addressing,
2836    // it can not feed into new value store
2837    //  r3 = memw(r2++#4)
2838    //  memw(r30 + #-1404) = r2.new -> can not be new value store
2839    // arch spec section: 5.4.2.1
2840    return false;
2841  }
2842
2843  // If the source that feeds the store is predicated, new value store must also be
2844  // also predicated.
2845  if (QII->isPredicated(PacketMI)) {
2846    if (!QII->isPredicated(MI))
2847      return false;
2848
2849    // Check to make sure that they both will have their predicates
2850    // evaluate identically
2851    unsigned predRegNumSrc;
2852    unsigned predRegNumDst;
2853    const TargetRegisterClass* predRegClass;
2854
2855    // Get predicate register used in the source instruction
2856    for(unsigned opNum = 0; opNum < PacketMI->getNumOperands(); opNum++) {
2857      if ( PacketMI->getOperand(opNum).isReg())
2858      predRegNumSrc = PacketMI->getOperand(opNum).getReg();
2859      predRegClass = QRI->getMinimalPhysRegClass(predRegNumSrc);
2860      if (predRegClass == Hexagon::PredRegsRegisterClass) {
2861        break;
2862      }
2863    }
2864    assert ((predRegClass == Hexagon::PredRegsRegisterClass ) &&
2865        ("predicate register not found in a predicated PacketMI instruction"));
2866
2867    // Get predicate register used in new-value store instruction
2868    for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++) {
2869      if ( MI->getOperand(opNum).isReg())
2870      predRegNumDst = MI->getOperand(opNum).getReg();
2871      predRegClass = QRI->getMinimalPhysRegClass(predRegNumDst);
2872      if (predRegClass == Hexagon::PredRegsRegisterClass) {
2873        break;
2874      }
2875    }
2876    assert ((predRegClass == Hexagon::PredRegsRegisterClass ) &&
2877            ("predicate register not found in a predicated MI instruction"));
2878
2879    // New-value register producer and user (store) need to satisfy these
2880    // constraints:
2881    // 1) Both instructions should be predicated on the same register.
2882    // 2) If producer of the new-value register is .new predicated then store
2883    // should also be .new predicated and if producer is not .new predicated
2884    // then store should not be .new predicated.
2885    // 3) Both new-value register producer and user should have same predicate
2886    // sense, i.e, either both should be negated or both should be none negated.
2887
2888    if (( predRegNumDst != predRegNumSrc) ||
2889          isDotNewInst(PacketMI) != isDotNewInst(MI)  ||
2890          GetPredicateSense(MI, QII) != GetPredicateSense(PacketMI, QII)) {
2891      return false;
2892    }
2893  }
2894
2895  // Make sure that other than the new-value register no other store instruction
2896  // register has been modified in the same packet. Predicate registers can be
2897  // modified by they should not be modified between the producer and the store
2898  // instruction as it will make them both conditional on different values.
2899  // We already know this to be true for all the instructions before and
2900  // including PacketMI. Howerver, we need to perform the check for the
2901  // remaining instructions in the packet.
2902
2903  std::vector<MachineInstr*>::iterator VI;
2904  std::vector<MachineInstr*>::iterator VE;
2905  unsigned StartCheck = 0;
2906
2907  for (VI=CurrentPacketMIs.begin(), VE = CurrentPacketMIs.end();
2908      (VI != VE); ++VI) {
2909    SUnit* TempSU = MIToSUnit[*VI];
2910    MachineInstr* TempMI = TempSU->getInstr();
2911
2912    // Following condition is true for all the instructions until PacketMI is
2913    // reached (StartCheck is set to 0 before the for loop).
2914    // StartCheck flag is 1 for all the instructions after PacketMI.
2915    if (TempMI != PacketMI && !StartCheck) // start processing only after
2916      continue;                            // encountering PacketMI
2917
2918    StartCheck = 1;
2919    if (TempMI == PacketMI) // We don't want to check PacketMI for dependence
2920      continue;
2921
2922    for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++) {
2923      if (MI->getOperand(opNum).isReg() &&
2924          TempSU->getInstr()->modifiesRegister(MI->getOperand(opNum).getReg(), QRI))
2925        return false;
2926    }
2927  }
2928
2929  // Make sure that for non POST_INC stores:
2930  // 1. The only use of reg is DepReg and no other registers.
2931  //    This handles V4 base+index registers.
2932  //    The following store can not be dot new.
2933  //    Eg.   r0 = add(r0, #3)a
2934  //          memw(r1+r0<<#2) = r0
2935  if (!QII->isPostIncrement(MI) &&
2936      GetStoreValueOperand(MI).isReg() &&
2937      GetStoreValueOperand(MI).getReg() == DepReg) {
2938    for(unsigned opNum = 0; opNum < MI->getNumOperands()-1; opNum++) {
2939      if (MI->getOperand(opNum).isReg() &&
2940          MI->getOperand(opNum).getReg() == DepReg) {
2941        return false;
2942      }
2943    }
2944    // 2. If data definition is because of implicit definition of the register,
2945    //    do not newify the store. Eg.
2946    //    %R9<def> = ZXTH %R12, %D6<imp-use>, %R12<imp-def>
2947    //    STrih_indexed %R8, 2, %R12<kill>; mem:ST2[%scevgep343]
2948    for(unsigned opNum = 0; opNum < PacketMI->getNumOperands(); opNum++) {
2949      if (PacketMI->getOperand(opNum).isReg() &&
2950          PacketMI->getOperand(opNum).getReg() == DepReg &&
2951          PacketMI->getOperand(opNum).isDef() &&
2952          PacketMI->getOperand(opNum).isImplicit()) {
2953        return false;
2954      }
2955    }
2956  }
2957
2958  // Can be dot new store.
2959  return true;
2960}
2961
2962// can this MI to promoted to either
2963// new value store or new value jump
2964bool HexagonPacketizerList::CanPromoteToNewValue( MachineInstr *MI,
2965                SUnit *PacketSU, unsigned DepReg,
2966                std::map <MachineInstr*, SUnit*> MIToSUnit,
2967                MachineBasicBlock::iterator &MII)
2968{
2969
2970  const HexagonRegisterInfo* QRI = (const HexagonRegisterInfo *) TM.getRegisterInfo();
2971  if (!QRI->Subtarget.hasV4TOps() ||
2972      !IsNewifyStore(MI))
2973    return false;
2974
2975  MachineInstr *PacketMI = PacketSU->getInstr();
2976
2977  // Check to see the store can be new value'ed.
2978  if (CanPromoteToNewValueStore(MI, PacketMI, DepReg, MIToSUnit))
2979    return true;
2980
2981  // Check to see the compare/jump can be new value'ed.
2982  // This is done as a pass on its own. Don't need to check it here.
2983  return false;
2984}
2985
2986// Check to see if an instruction can be dot new
2987// There are three kinds.
2988// 1. dot new on predicate - V2/V3/V4
2989// 2. dot new on stores NV/ST - V4
2990// 3. dot new on jump NV/J - V4 -- This is generated in a pass.
2991bool HexagonPacketizerList::CanPromoteToDotNew( MachineInstr *MI,
2992                              SUnit *PacketSU, unsigned DepReg,
2993                              std::map <MachineInstr*, SUnit*> MIToSUnit,
2994                              MachineBasicBlock::iterator &MII,
2995                              const TargetRegisterClass* RC )
2996{
2997  // already a dot new instruction
2998  if (isDotNewInst(MI) && !IsNewifyStore(MI))
2999    return false;
3000
3001  if (!isNewifiable(MI))
3002    return false;
3003
3004  // predicate .new
3005  if (RC == Hexagon::PredRegsRegisterClass && isCondInst(MI))
3006      return true;
3007  else if (RC != Hexagon::PredRegsRegisterClass &&
3008      !IsNewifyStore(MI)) // MI is not a new-value store
3009    return false;
3010  else {
3011    // Create a dot new machine instruction to see if resources can be
3012    // allocated. If not, bail out now.
3013    const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
3014    int NewOpcode = GetDotNewOp(MI->getOpcode());
3015    const MCInstrDesc &desc = QII->get(NewOpcode);
3016    DebugLoc dl;
3017    MachineInstr *NewMI = MI->getParent()->getParent()->CreateMachineInstr(desc, dl);
3018    bool ResourcesAvailable = ResourceTracker->canReserveResources(NewMI);
3019    MI->getParent()->getParent()->DeleteMachineInstr(NewMI);
3020
3021    if (!ResourcesAvailable)
3022      return false;
3023
3024    // new value store only
3025    // new new value jump generated as a passes
3026    if (!CanPromoteToNewValue(MI, PacketSU, DepReg, MIToSUnit, MII)) {
3027      return false;
3028    }
3029  }
3030  return true;
3031}
3032
3033// Go through the packet instructions and search for anti dependency
3034// between them and DepReg from MI
3035// Consider this case:
3036// Trying to add
3037// a) %R1<def> = TFRI_cdNotPt %P3, 2
3038// to this packet:
3039// {
3040//   b) %P0<def> = OR_pp %P3<kill>, %P0<kill>
3041//   c) %P3<def> = TFR_PdRs %R23
3042//   d) %R1<def> = TFRI_cdnPt %P3, 4
3043//  }
3044// The P3 from a) and d) will be complements after
3045// a)'s P3 is converted to .new form
3046// Anti Dep between c) and b) is irrelevant for this case
3047bool HexagonPacketizerList::RestrictingDepExistInPacket (MachineInstr* MI,
3048      unsigned DepReg,
3049      std::map <MachineInstr*, SUnit*> MIToSUnit) {
3050
3051  const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
3052  SUnit* PacketSUDep = MIToSUnit[MI];
3053
3054  for (std::vector<MachineInstr*>::iterator VIN = CurrentPacketMIs.begin(),
3055       VEN = CurrentPacketMIs.end(); (VIN != VEN); ++VIN) {
3056
3057    // We only care for dependencies to predicated instructions
3058    if(!QII->isPredicated(*VIN)) continue;
3059
3060    // Scheduling Unit for current insn in the packet
3061    SUnit* PacketSU = MIToSUnit[*VIN];
3062
3063    // Look at dependencies between current members of the packet
3064    // and predicate defining instruction MI.
3065    // Make sure that dependency is on the exact register
3066    // we care about.
3067    if (PacketSU->isSucc(PacketSUDep)) {
3068      for (unsigned i = 0; i < PacketSU->Succs.size(); ++i) {
3069        if ((PacketSU->Succs[i].getSUnit() == PacketSUDep) &&
3070            (PacketSU->Succs[i].getKind() == SDep::Anti) &&
3071            (PacketSU->Succs[i].getReg() == DepReg)) {
3072          return true;
3073        }
3074      }
3075    }
3076  }
3077
3078  return false;
3079}
3080
3081
3082// Given two predicated instructions, this function detects whether
3083// the predicates are complements
3084bool HexagonPacketizerList::ArePredicatesComplements (MachineInstr* MI1,
3085     MachineInstr* MI2, std::map <MachineInstr*, SUnit*> MIToSUnit) {
3086
3087  const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
3088  // Currently can only reason about conditional transfers
3089  if (!QII->isConditionalTransfer(MI1) || !QII->isConditionalTransfer(MI2)) {
3090    return false;
3091  }
3092
3093  // Scheduling unit for candidate
3094  SUnit* SU = MIToSUnit[MI1];
3095
3096  // One corner case deals with the following scenario:
3097  // Trying to add
3098  // a) %R24<def> = TFR_cPt %P0, %R25
3099  // to this packet:
3100  //
3101  // {
3102  //   b) %R25<def> = TFR_cNotPt %P0, %R24
3103  //   c) %P0<def> = CMPEQri %R26, 1
3104  // }
3105  //
3106  // On general check a) and b) are complements, but
3107  // presence of c) will convert a) to .new form, and
3108  // then it is not a complement
3109  // We attempt to detect it by analyzing  existing
3110  // dependencies in the packet
3111
3112  // Analyze relationships between all existing members of the packet.
3113  // Look for Anti dependecy on the same predicate reg
3114  // as used in the candidate
3115  for (std::vector<MachineInstr*>::iterator VIN = CurrentPacketMIs.begin(),
3116       VEN = CurrentPacketMIs.end(); (VIN != VEN); ++VIN) {
3117
3118    // Scheduling Unit for current insn in the packet
3119    SUnit* PacketSU = MIToSUnit[*VIN];
3120
3121    // If this instruction in the packet is succeeded by the candidate...
3122    if (PacketSU->isSucc(SU)) {
3123      for (unsigned i = 0; i < PacketSU->Succs.size(); ++i) {
3124        // The corner case exist when there is true data
3125        // dependency between candidate and one of current
3126        // packet members, this dep is on predicate reg, and
3127        // there already exist anti dep on the same pred in
3128        // the packet.
3129        if (PacketSU->Succs[i].getSUnit() == SU &&
3130            Hexagon::PredRegsRegisterClass->contains(
3131              PacketSU->Succs[i].getReg()) &&
3132            PacketSU->Succs[i].getKind() == SDep::Data &&
3133            // Here I know that *VIN is predicate setting instruction
3134            // with true data dep to candidate on the register
3135            // we care about - c) in the above example.
3136            // Now I need to see if there is an anti dependency
3137            // from c) to any other instruction in the
3138            // same packet on the pred reg of interest
3139            RestrictingDepExistInPacket(*VIN,PacketSU->Succs[i].getReg(),
3140                                        MIToSUnit)) {
3141           return false;
3142        }
3143      }
3144    }
3145  }
3146
3147  // If the above case does not apply, check regular
3148  // complement condition.
3149  // Check that the predicate register is the same and
3150  // that the predicate sense is different
3151  // We also need to differentiate .old vs. .new:
3152  // !p0 is not complimentary to p0.new
3153  return ((MI1->getOperand(1).getReg() == MI2->getOperand(1).getReg()) &&
3154          (GetPredicateSense(MI1, QII) != GetPredicateSense(MI2, QII)) &&
3155          (isDotNewInst(MI1) == isDotNewInst(MI2)));
3156}
3157
3158// initPacketizerState - Initialize packetizer flags
3159void HexagonPacketizerList::initPacketizerState() {
3160
3161  Dependence = false;
3162  PromotedToDotNew = false;
3163  GlueToNewValueJump = false;
3164  GlueAllocframeStore = false;
3165  FoundSequentialDependence = false;
3166
3167  return;
3168}
3169
3170// ignorePseudoInstruction - Ignore bundling of pseudo instructions.
3171bool HexagonPacketizerList::ignorePseudoInstruction(MachineInstr *MI,
3172                                                    MachineBasicBlock *MBB) {
3173  if (MI->isDebugValue())
3174    return true;
3175
3176  // We must print out inline assembly
3177  if (MI->isInlineAsm())
3178    return false;
3179
3180  // We check if MI has any functional units mapped to it.
3181  // If it doesn't, we ignore the instruction.
3182  const MCInstrDesc& TID = MI->getDesc();
3183  unsigned SchedClass = TID.getSchedClass();
3184  const InstrStage* IS = ResourceTracker->getInstrItins()->beginStage(SchedClass);
3185  unsigned FuncUnits = IS->getUnits();
3186  return !FuncUnits;
3187}
3188
3189// isSoloInstruction: - Returns true for instructions that must be
3190// scheduled in their own packet.
3191bool HexagonPacketizerList::isSoloInstruction(MachineInstr *MI) {
3192
3193  if (MI->isInlineAsm())
3194    return true;
3195
3196  if (MI->isEHLabel())
3197    return true;
3198
3199  // From Hexagon V4 Programmer's Reference Manual 3.4.4 Grouping constraints:
3200  // trap, pause, barrier, icinva, isync, and syncht are solo instructions.
3201  // They must not be grouped with other instructions in a packet.
3202  if (IsSchedBarrier(MI))
3203    return true;
3204
3205  return false;
3206}
3207
3208// isLegalToPacketizeTogether:
3209// SUI is the current instruction that is out side of the current packet.
3210// SUJ is the current instruction inside the current packet against which that
3211// SUI will be packetized.
3212bool HexagonPacketizerList::isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) {
3213  MachineInstr *I = SUI->getInstr();
3214  MachineInstr *J = SUJ->getInstr();
3215  assert(I && J && "Unable to packetize null instruction!");
3216
3217  const MCInstrDesc &MCIDI = I->getDesc();
3218  const MCInstrDesc &MCIDJ = J->getDesc();
3219
3220  MachineBasicBlock::iterator II = I;
3221
3222  const unsigned FrameSize = MF.getFrameInfo()->getStackSize();
3223  const HexagonRegisterInfo* QRI = (const HexagonRegisterInfo *) TM.getRegisterInfo();
3224  const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
3225
3226  // Inline asm cannot go in the packet.
3227  if (I->getOpcode() == Hexagon::INLINEASM)
3228    llvm_unreachable("Should not meet inline asm here!");
3229
3230  if (isSoloInstruction(I))
3231    llvm_unreachable("Should not meet solo instr here!");
3232
3233  // A save callee-save register function call can only be in a packet
3234  // with instructions that don't write to the callee-save registers.
3235  if ((QII->isSaveCalleeSavedRegsCall(I) &&
3236       DoesModifyCalleeSavedReg(J, QRI)) ||
3237      (QII->isSaveCalleeSavedRegsCall(J) &&
3238       DoesModifyCalleeSavedReg(I, QRI))) {
3239    Dependence = true;
3240    return false;
3241  }
3242
3243  // Two control flow instructions cannot go in the same packet.
3244  if (IsControlFlow(I) && IsControlFlow(J)) {
3245    Dependence = true;
3246    return false;
3247  }
3248
3249  // A LoopN instruction cannot appear in the same packet as a jump or call.
3250  if (IsLoopN(I) && (   IsDirectJump(J)
3251                     || MCIDJ.isCall()
3252                     || QII->isDeallocRet(J))) {
3253    Dependence = true;
3254    return false;
3255  }
3256  if (IsLoopN(J) && (   IsDirectJump(I)
3257                     || MCIDI.isCall()
3258                     || QII->isDeallocRet(I))) {
3259    Dependence = true;
3260    return false;
3261  }
3262
3263  // dealloc_return cannot appear in the same packet as a conditional or
3264  // unconditional jump.
3265  if (QII->isDeallocRet(I) && (   MCIDJ.isBranch()
3266                               || MCIDJ.isCall()
3267                               || MCIDJ.isBarrier())) {
3268    Dependence = true;
3269    return false;
3270  }
3271
3272
3273  // V4 allows dual store. But does not allow second store, if the
3274  // first store is not in SLOT0. New value store, new value jump,
3275  // dealloc_return and memop always take SLOT0.
3276  // Arch spec 3.4.4.2
3277  if (QRI->Subtarget.hasV4TOps()) {
3278
3279    if (MCIDI.mayStore() && MCIDJ.mayStore() && isNewValueInst(J)) {
3280      Dependence = true;
3281      return false;
3282    }
3283
3284    if (   (QII->isMemOp(J) && MCIDI.mayStore())
3285        || (MCIDJ.mayStore() && QII->isMemOp(I))
3286        || (QII->isMemOp(J) && QII->isMemOp(I))) {
3287      Dependence = true;
3288      return false;
3289    }
3290
3291    //if dealloc_return
3292    if (MCIDJ.mayStore() && QII->isDeallocRet(I)){
3293      Dependence = true;
3294      return false;
3295    }
3296
3297    // If an instruction feeds new value jump, glue it.
3298    MachineBasicBlock::iterator NextMII = I;
3299    ++NextMII;
3300    MachineInstr *NextMI = NextMII;
3301
3302    if (QII->isNewValueJump(NextMI)) {
3303
3304      bool secondRegMatch = false;
3305      bool maintainNewValueJump = false;
3306
3307      if (NextMI->getOperand(1).isReg() &&
3308          I->getOperand(0).getReg() == NextMI->getOperand(1).getReg()) {
3309        secondRegMatch = true;
3310        maintainNewValueJump = true;
3311      }
3312
3313      if (!secondRegMatch &&
3314           I->getOperand(0).getReg() == NextMI->getOperand(0).getReg()) {
3315        maintainNewValueJump = true;
3316      }
3317
3318      for (std::vector<MachineInstr*>::iterator
3319            VI = CurrentPacketMIs.begin(),
3320             VE = CurrentPacketMIs.end();
3321           (VI != VE && maintainNewValueJump); ++VI) {
3322        SUnit* PacketSU = MIToSUnit[*VI];
3323
3324        // NVJ can not be part of the dual jump - Arch Spec: section 7.8
3325        if (PacketSU->getInstr()->getDesc().isCall()) {
3326          Dependence = true;
3327          break;
3328        }
3329        // Validate
3330        // 1. Packet does not have a store in it.
3331        // 2. If the first operand of the nvj is newified, and the second
3332        //    operand is also a reg, it (second reg) is not defined in
3333        //    the same packet.
3334        // 3. If the second operand of the nvj is newified, (which means
3335        //    first operand is also a reg), first reg is not defined in
3336        //    the same packet.
3337        if (PacketSU->getInstr()->getDesc().mayStore()               ||
3338            PacketSU->getInstr()->getOpcode() == Hexagon::ALLOCFRAME ||
3339            // Check #2.
3340            (!secondRegMatch && NextMI->getOperand(1).isReg() &&
3341             PacketSU->getInstr()->modifiesRegister(
3342                               NextMI->getOperand(1).getReg(), QRI)) ||
3343            // Check #3.
3344            (secondRegMatch &&
3345             PacketSU->getInstr()->modifiesRegister(
3346                               NextMI->getOperand(0).getReg(), QRI))) {
3347          Dependence = true;
3348          break;
3349        }
3350      }
3351      if (!Dependence)
3352        GlueToNewValueJump = true;
3353      else
3354        return false;
3355    }
3356  }
3357
3358  if (SUJ->isSucc(SUI)) {
3359    for (unsigned i = 0;
3360         (i < SUJ->Succs.size()) && !FoundSequentialDependence;
3361         ++i) {
3362
3363      if (SUJ->Succs[i].getSUnit() != SUI) {
3364        continue;
3365      }
3366
3367      SDep::Kind DepType = SUJ->Succs[i].getKind();
3368
3369      // For direct calls:
3370      // Ignore register dependences for call instructions for
3371      // packetization purposes except for those due to r31 and
3372      // predicate registers.
3373      //
3374      // For indirect calls:
3375      // Same as direct calls + check for true dependences to the register
3376      // used in the indirect call.
3377      //
3378      // We completely ignore Order dependences for call instructions
3379      //
3380      // For returns:
3381      // Ignore register dependences for return instructions like jumpr,
3382      // dealloc return unless we have dependencies on the explicit uses
3383      // of the registers used by jumpr (like r31) or dealloc return
3384      // (like r29 or r30).
3385      //
3386      // TODO: Currently, jumpr is handling only return of r31. So, the
3387      // following logic (specificaly IsCallDependent) is working fine.
3388      // We need to enable jumpr for register other than r31 and then,
3389      // we need to rework the last part, where it handles indirect call
3390      // of that (IsCallDependent) function. Bug 6216 is opened for this.
3391      //
3392      unsigned DepReg;
3393      const TargetRegisterClass* RC;
3394      if (DepType == SDep::Data) {
3395        DepReg = SUJ->Succs[i].getReg();
3396        RC = QRI->getMinimalPhysRegClass(DepReg);
3397      }
3398      if ((MCIDI.isCall() || MCIDI.isReturn()) &&
3399          (!IsRegDependence(DepType) ||
3400            !IsCallDependent(I, DepType, SUJ->Succs[i].getReg()))) {
3401        /* do nothing */
3402      }
3403
3404      // For instructions that can be promoted to dot-new, try to promote.
3405      else if ((DepType == SDep::Data) &&
3406               CanPromoteToDotNew(I, SUJ, DepReg, MIToSUnit, II, RC) &&
3407               PromoteToDotNew(I, DepType, II, RC)) {
3408        PromotedToDotNew = true;
3409        /* do nothing */
3410      }
3411
3412      else if ((DepType == SDep::Data) &&
3413               (QII->isNewValueJump(I))) {
3414        /* do nothing */
3415      }
3416
3417      // For predicated instructions, if the predicates are complements
3418      // then there can be no dependence.
3419      else if (QII->isPredicated(I) &&
3420               QII->isPredicated(J) &&
3421          ArePredicatesComplements(I, J, MIToSUnit)) {
3422        /* do nothing */
3423
3424      }
3425      else if (IsDirectJump(I) &&
3426               !MCIDJ.isBranch() &&
3427               !MCIDJ.isCall() &&
3428               (DepType == SDep::Order)) {
3429        // Ignore Order dependences between unconditional direct branches
3430        // and non-control-flow instructions
3431        /* do nothing */
3432      }
3433      else if (MCIDI.isConditionalBranch() && (DepType != SDep::Data) &&
3434               (DepType != SDep::Output)) {
3435        // Ignore all dependences for jumps except for true and output
3436        // dependences
3437        /* do nothing */
3438      }
3439
3440      // Ignore output dependences due to superregs. We can
3441      // write to two different subregisters of R1:0 for instance
3442      // in the same cycle
3443      //
3444
3445      //
3446      // Let the
3447      // If neither I nor J defines DepReg, then this is a
3448      // superfluous output dependence. The dependence must be of the
3449      // form:
3450      //  R0 = ...
3451      //  R1 = ...
3452      // and there is an output dependence between the two instructions
3453      // with
3454      // DepReg = D0
3455      // We want to ignore these dependences.
3456      // Ideally, the dependence constructor should annotate such
3457      // dependences. We can then avoid this relatively expensive check.
3458      //
3459      else if (DepType == SDep::Output) {
3460        // DepReg is the register that's responsible for the dependence.
3461        unsigned DepReg = SUJ->Succs[i].getReg();
3462
3463        // Check if I and J really defines DepReg.
3464        if (I->definesRegister(DepReg) ||
3465            J->definesRegister(DepReg)) {
3466          FoundSequentialDependence = true;
3467          break;
3468        }
3469      }
3470
3471      // We ignore Order dependences for
3472      // 1. Two loads unless they are volatile.
3473      // 2. Two stores in V4 unless they are volatile.
3474      else if ((DepType == SDep::Order) &&
3475               !I->hasVolatileMemoryRef() &&
3476               !J->hasVolatileMemoryRef()) {
3477        if (QRI->Subtarget.hasV4TOps() &&
3478            // hexagonv4 allows dual store.
3479            MCIDI.mayStore() && MCIDJ.mayStore()) {
3480          /* do nothing */
3481        }
3482        // store followed by store-- not OK on V2
3483        // store followed by load -- not OK on all (OK if addresses
3484        // are not aliased)
3485        // load followed by store -- OK on all
3486        // load followed by load  -- OK on all
3487        else if ( !MCIDJ.mayStore()) {
3488          /* do nothing */
3489        }
3490        else {
3491          FoundSequentialDependence = true;
3492          break;
3493        }
3494      }
3495
3496      // For V4, special case ALLOCFRAME. Even though there is dependency
3497      // between ALLOCAFRAME and subsequent store, allow it to be
3498      // packetized in a same packet. This implies that the store is using
3499      // caller's SP. Hense, offset needs to be updated accordingly.
3500      else if (DepType == SDep::Data
3501               && QRI->Subtarget.hasV4TOps()
3502               && J->getOpcode() == Hexagon::ALLOCFRAME
3503               && (I->getOpcode() == Hexagon::STrid
3504                   || I->getOpcode() == Hexagon::STriw
3505                   || I->getOpcode() == Hexagon::STrib)
3506               && I->getOperand(0).getReg() == QRI->getStackRegister()
3507               && QII->isValidOffset(I->getOpcode(),
3508                                     I->getOperand(1).getImm() -
3509                                     (FrameSize + HEXAGON_LRFP_SIZE)))
3510      {
3511        GlueAllocframeStore = true;
3512        // Since this store is to be glued with allocframe in the same
3513        // packet, it will use SP of the previous stack frame, i.e
3514        // caller's SP. Therefore, we need to recalculate offset according
3515        // to this change.
3516        I->getOperand(1).setImm(I->getOperand(1).getImm() -
3517                                        (FrameSize + HEXAGON_LRFP_SIZE));
3518      }
3519
3520      //
3521      // Skip over anti-dependences. Two instructions that are
3522      // anti-dependent can share a packet
3523      //
3524      else if (DepType != SDep::Anti) {
3525        FoundSequentialDependence = true;
3526        break;
3527      }
3528    }
3529
3530    if (FoundSequentialDependence) {
3531      Dependence = true;
3532      return false;
3533    }
3534  }
3535
3536  return true;
3537}
3538
3539// isLegalToPruneDependencies
3540bool HexagonPacketizerList::isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) {
3541  MachineInstr *I = SUI->getInstr();
3542  assert(I && SUJ->getInstr() && "Unable to packetize null instruction!");
3543
3544  const unsigned FrameSize = MF.getFrameInfo()->getStackSize();
3545
3546  if (Dependence) {
3547
3548    // Check if the instruction was promoted to a dot-new. If so, demote it
3549    // back into a dot-old.
3550    if (PromotedToDotNew) {
3551      DemoteToDotOld(I);
3552    }
3553
3554    // Check if the instruction (must be a store) was glued with an Allocframe
3555    // instruction. If so, restore its offset to its original value, i.e. use
3556    // curent SP instead of caller's SP.
3557    if (GlueAllocframeStore) {
3558      I->getOperand(1).setImm(I->getOperand(1).getImm() +
3559                                             FrameSize + HEXAGON_LRFP_SIZE);
3560    }
3561
3562    return false;
3563  }
3564  return true;
3565}
3566
3567MachineBasicBlock::iterator HexagonPacketizerList::addToPacket(MachineInstr *MI) {
3568
3569    MachineBasicBlock::iterator MII = MI;
3570    MachineBasicBlock *MBB = MI->getParent();
3571
3572    const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
3573
3574    if (GlueToNewValueJump) {
3575
3576      ++MII;
3577      MachineInstr *nvjMI = MII;
3578      assert(ResourceTracker->canReserveResources(MI));
3579      ResourceTracker->reserveResources(MI);
3580      if (QII->isExtended(MI) &&
3581          !tryAllocateResourcesForConstExt(MI)) {
3582        endPacket(MBB, MI);
3583        ResourceTracker->reserveResources(MI);
3584        assert(canReserveResourcesForConstExt(MI) &&
3585               "Ensure that there is a slot");
3586        reserveResourcesForConstExt(MI);
3587        // Reserve resources for new value jump constant extender.
3588        assert(canReserveResourcesForConstExt(MI) &&
3589               "Ensure that there is a slot");
3590        reserveResourcesForConstExt(nvjMI);
3591        assert(ResourceTracker->canReserveResources(nvjMI) &&
3592               "Ensure that there is a slot");
3593
3594      } else if (   // Extended instruction takes two slots in the packet.
3595        // Try reserve and allocate 4-byte in the current packet first.
3596        (QII->isExtended(nvjMI)
3597            && (!tryAllocateResourcesForConstExt(nvjMI)
3598                || !ResourceTracker->canReserveResources(nvjMI)))
3599        || // For non-extended instruction, no need to allocate extra 4 bytes.
3600        (!QII->isExtended(nvjMI) && !ResourceTracker->canReserveResources(nvjMI)))
3601      {
3602        endPacket(MBB, MI);
3603        // A new and empty packet starts.
3604        // We are sure that the resources requirements can be satisfied.
3605        // Therefore, do not need to call "canReserveResources" anymore.
3606        ResourceTracker->reserveResources(MI);
3607        if (QII->isExtended(nvjMI))
3608          reserveResourcesForConstExt(nvjMI);
3609      }
3610      // Here, we are sure that "reserveResources" would succeed.
3611      ResourceTracker->reserveResources(nvjMI);
3612      CurrentPacketMIs.push_back(MI);
3613      CurrentPacketMIs.push_back(nvjMI);
3614    } else {
3615      if (   QII->isExtended(MI)
3616          && (   !tryAllocateResourcesForConstExt(MI)
3617              || !ResourceTracker->canReserveResources(MI)))
3618      {
3619        endPacket(MBB, MI);
3620        // Check if the instruction was promoted to a dot-new. If so, demote it
3621        // back into a dot-old
3622        if (PromotedToDotNew) {
3623          DemoteToDotOld(MI);
3624        }
3625        reserveResourcesForConstExt(MI);
3626      }
3627      // In case that "MI" is not an extended insn,
3628      // the resource availability has already been checked.
3629      ResourceTracker->reserveResources(MI);
3630      CurrentPacketMIs.push_back(MI);
3631    }
3632    return MII;
3633}
3634
3635//===----------------------------------------------------------------------===//
3636//                         Public Constructor Functions
3637//===----------------------------------------------------------------------===//
3638
3639FunctionPass *llvm::createHexagonPacketizer() {
3640  return new HexagonPacketizer();
3641}
3642
3643