HexagonVLIWPacketizer.cpp revision 80d81aa8ba923c9f9a953410677ac53c4c2b8318 
1//===----- HexagonPacketizer.cpp - vliw packetizer ---------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This implements a simple VLIW packetizer using DFA. The packetizer works on
11// machine basic blocks. For each instruction I in BB, the packetizer consults
12// the DFA to see if machine resources are available to execute I. If so, the
13// packetizer checks if I depends on any instruction J in the current packet.
14// If no dependency is found, I is added to current packet and machine resource
15// is marked as taken. If any dependency is found, a target API call is made to
16// prune the dependence.
17//
18//===----------------------------------------------------------------------===//
19#define DEBUG_TYPE "packets"
20#include "llvm/CodeGen/DFAPacketizer.h"
21#include "llvm/CodeGen/Passes.h"
22#include "llvm/CodeGen/MachineDominators.h"
23#include "llvm/CodeGen/MachineFunctionPass.h"
24#include "llvm/CodeGen/MachineLoopInfo.h"
25#include "llvm/CodeGen/ScheduleDAG.h"
26#include "llvm/CodeGen/ScheduleDAGInstrs.h"
27#include "llvm/CodeGen/LatencyPriorityQueue.h"
28#include "llvm/CodeGen/SchedulerRegistry.h"
29#include "llvm/CodeGen/MachineFrameInfo.h"
30#include "llvm/CodeGen/MachineInstrBuilder.h"
31#include "llvm/CodeGen/MachineRegisterInfo.h"
32#include "llvm/CodeGen/MachineFunctionAnalysis.h"
33#include "llvm/CodeGen/ScheduleHazardRecognizer.h"
34#include "llvm/Target/TargetMachine.h"
35#include "llvm/Target/TargetInstrInfo.h"
36#include "llvm/Target/TargetRegisterInfo.h"
37#include "llvm/ADT/DenseMap.h"
38#include "llvm/ADT/Statistic.h"
39#include "llvm/Support/MathExtras.h"
40#include "llvm/MC/MCInstrItineraries.h"
41#include "llvm/Support/Compiler.h"
42#include "llvm/Support/CommandLine.h"
43#include "llvm/Support/Debug.h"
44#include "Hexagon.h"
45#include "HexagonTargetMachine.h"
46#include "HexagonRegisterInfo.h"
47#include "HexagonSubtarget.h"
48#include "HexagonMachineFunctionInfo.h"
49
50#include <map>
51#include <vector>
52
53using namespace llvm;
54
55static cl::opt<bool> PacketizeVolatiles("hexagon-packetize-volatiles",
56      cl::ZeroOrMore, cl::Hidden, cl::init(true),
57      cl::desc("Allow non-solo packetization of volatile memory references"));
58
59namespace llvm {
60  void initializeHexagonPacketizerPass(PassRegistry&);
61}
62
63
64namespace {
65  class HexagonPacketizer : public MachineFunctionPass {
66
67  public:
68    static char ID;
69    HexagonPacketizer() : MachineFunctionPass(ID) {
70      initializeHexagonPacketizerPass(*PassRegistry::getPassRegistry());
71    }
72
73    void getAnalysisUsage(AnalysisUsage &AU) const {
74      AU.setPreservesCFG();
75      AU.addRequired<MachineDominatorTree>();
76      AU.addRequired<MachineBranchProbabilityInfo>();
77      AU.addPreserved<MachineDominatorTree>();
78      AU.addRequired<MachineLoopInfo>();
79      AU.addPreserved<MachineLoopInfo>();
80      MachineFunctionPass::getAnalysisUsage(AU);
81    }
82
83    const char *getPassName() const {
84      return "Hexagon Packetizer";
85    }
86
87    bool runOnMachineFunction(MachineFunction &Fn);
88  };
89  char HexagonPacketizer::ID = 0;
90
91  class HexagonPacketizerList : public VLIWPacketizerList {
92
93  private:
94
95    // Has the instruction been promoted to a dot-new instruction.
96    bool PromotedToDotNew;
97
98    // Has the instruction been glued to allocframe.
99    bool GlueAllocframeStore;
100
101    // Has the feeder instruction been glued to new value jump.
102    bool GlueToNewValueJump;
103
104    // Check if there is a dependence between some instruction already in this
105    // packet and this instruction.
106    bool Dependence;
107
108    // Only check for dependence if there are resources available to
109    // schedule this instruction.
110    bool FoundSequentialDependence;
111
112    /// \brief A handle to the branch probability pass.
113   const MachineBranchProbabilityInfo *MBPI;
114
115   // Track MIs with ignored dependece.
116   std::vector<MachineInstr*> IgnoreDepMIs;
117
118  public:
119    // Ctor.
120    HexagonPacketizerList(MachineFunction &MF, MachineLoopInfo &MLI,
121                          MachineDominatorTree &MDT,
122                          const MachineBranchProbabilityInfo *MBPI);
123
124    // initPacketizerState - initialize some internal flags.
125    void initPacketizerState();
126
127    // ignorePseudoInstruction - Ignore bundling of pseudo instructions.
128    bool ignorePseudoInstruction(MachineInstr *MI, MachineBasicBlock *MBB);
129
130    // isSoloInstruction - return true if instruction MI can not be packetized
131    // with any other instruction, which means that MI itself is a packet.
132    bool isSoloInstruction(MachineInstr *MI);
133
134    // isLegalToPacketizeTogether - Is it legal to packetize SUI and SUJ
135    // together.
136    bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ);
137
138    // isLegalToPruneDependencies - Is it legal to prune dependece between SUI
139    // and SUJ.
140    bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ);
141
142    MachineBasicBlock::iterator addToPacket(MachineInstr *MI);
143  private:
144    bool IsCallDependent(MachineInstr* MI, SDep::Kind DepType, unsigned DepReg);
145    bool PromoteToDotNew(MachineInstr* MI, SDep::Kind DepType,
146                         MachineBasicBlock::iterator &MII,
147                         const TargetRegisterClass* RC);
148    bool CanPromoteToDotNew(MachineInstr* MI, SUnit* PacketSU,
149                            unsigned DepReg,
150                            std::map <MachineInstr*, SUnit*> MIToSUnit,
151                            MachineBasicBlock::iterator &MII,
152                            const TargetRegisterClass* RC);
153    bool CanPromoteToNewValue(MachineInstr* MI, SUnit* PacketSU,
154                              unsigned DepReg,
155                              std::map <MachineInstr*, SUnit*> MIToSUnit,
156                              MachineBasicBlock::iterator &MII);
157    bool CanPromoteToNewValueStore(MachineInstr* MI, MachineInstr* PacketMI,
158                                   unsigned DepReg,
159                                   std::map <MachineInstr*, SUnit*> MIToSUnit);
160    bool DemoteToDotOld(MachineInstr* MI);
161    bool ArePredicatesComplements(MachineInstr* MI1, MachineInstr* MI2,
162                    std::map <MachineInstr*, SUnit*> MIToSUnit);
163    bool RestrictingDepExistInPacket(MachineInstr*,
164                    unsigned, std::map <MachineInstr*, SUnit*>);
165    bool isNewifiable(MachineInstr* MI);
166    bool isCondInst(MachineInstr* MI);
167    bool IsNewifyStore (MachineInstr* MI);
168    bool tryAllocateResourcesForConstExt(MachineInstr* MI);
169    bool canReserveResourcesForConstExt(MachineInstr *MI);
170    void reserveResourcesForConstExt(MachineInstr* MI);
171    bool isNewValueInst(MachineInstr* MI);
172  };
173}
174
175INITIALIZE_PASS_BEGIN(HexagonPacketizer, "packets", "Hexagon Packetizer",
176                      false, false)
177INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
178INITIALIZE_PASS_DEPENDENCY(MachineBranchProbabilityInfo)
179INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
180INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
181INITIALIZE_PASS_END(HexagonPacketizer, "packets", "Hexagon Packetizer",
182                    false, false)
183
184
185// HexagonPacketizerList Ctor.
186HexagonPacketizerList::HexagonPacketizerList(
187  MachineFunction &MF, MachineLoopInfo &MLI,MachineDominatorTree &MDT,
188  const MachineBranchProbabilityInfo *MBPI)
189  : VLIWPacketizerList(MF, MLI, MDT, true){
190  this->MBPI = MBPI;
191}
192
193bool HexagonPacketizer::runOnMachineFunction(MachineFunction &Fn) {
194  const TargetInstrInfo *TII = Fn.getTarget().getInstrInfo();
195  MachineLoopInfo &MLI = getAnalysis<MachineLoopInfo>();
196  MachineDominatorTree &MDT = getAnalysis<MachineDominatorTree>();
197  const MachineBranchProbabilityInfo *MBPI =
198    &getAnalysis<MachineBranchProbabilityInfo>();
199  // Instantiate the packetizer.
200  HexagonPacketizerList Packetizer(Fn, MLI, MDT, MBPI);
201
202  // DFA state table should not be empty.
203  assert(Packetizer.getResourceTracker() && "Empty DFA table!");
204
205  //
206  // Loop over all basic blocks and remove KILL pseudo-instructions
207  // These instructions confuse the dependence analysis. Consider:
208  // D0 = ...   (Insn 0)
209  // R0 = KILL R0, D0 (Insn 1)
210  // R0 = ... (Insn 2)
211  // Here, Insn 1 will result in the dependence graph not emitting an output
212  // dependence between Insn 0 and Insn 2. This can lead to incorrect
213  // packetization
214  //
215  for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
216       MBB != MBBe; ++MBB) {
217    MachineBasicBlock::iterator End = MBB->end();
218    MachineBasicBlock::iterator MI = MBB->begin();
219    while (MI != End) {
220      if (MI->isKill()) {
221        MachineBasicBlock::iterator DeleteMI = MI;
222        ++MI;
223        MBB->erase(DeleteMI);
224        End = MBB->end();
225        continue;
226      }
227      ++MI;
228    }
229  }
230
231  // Loop over all of the basic blocks.
232  for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
233       MBB != MBBe; ++MBB) {
234    // Find scheduling regions and schedule / packetize each region.
235    unsigned RemainingCount = MBB->size();
236    for(MachineBasicBlock::iterator RegionEnd = MBB->end();
237        RegionEnd != MBB->begin();) {
238      // The next region starts above the previous region. Look backward in the
239      // instruction stream until we find the nearest boundary.
240      MachineBasicBlock::iterator I = RegionEnd;
241      for(;I != MBB->begin(); --I, --RemainingCount) {
242        if (TII->isSchedulingBoundary(llvm::prior(I), MBB, Fn))
243          break;
244      }
245      I = MBB->begin();
246
247      // Skip empty scheduling regions.
248      if (I == RegionEnd) {
249        RegionEnd = llvm::prior(RegionEnd);
250        --RemainingCount;
251        continue;
252      }
253      // Skip regions with one instruction.
254      if (I == llvm::prior(RegionEnd)) {
255        RegionEnd = llvm::prior(RegionEnd);
256        continue;
257      }
258
259      Packetizer.PacketizeMIs(MBB, I, RegionEnd);
260      RegionEnd = I;
261    }
262  }
263
264  return true;
265}
266
267
268static bool IsIndirectCall(MachineInstr* MI) {
269  return ((MI->getOpcode() == Hexagon::CALLR) ||
270          (MI->getOpcode() == Hexagon::CALLRv3));
271}
272
273// Reserve resources for constant extender. Trigure an assertion if
274// reservation fail.
275void HexagonPacketizerList::reserveResourcesForConstExt(MachineInstr* MI) {
276  const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
277  MachineFunction *MF = MI->getParent()->getParent();
278  MachineInstr *PseudoMI = MF->CreateMachineInstr(QII->get(Hexagon::IMMEXT_i),
279                                                  MI->getDebugLoc());
280
281  if (ResourceTracker->canReserveResources(PseudoMI)) {
282    ResourceTracker->reserveResources(PseudoMI);
283    MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);
284  } else {
285    MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);
286    llvm_unreachable("can not reserve resources for constant extender.");
287  }
288  return;
289}
290
291bool HexagonPacketizerList::canReserveResourcesForConstExt(MachineInstr *MI) {
292  const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
293  assert((QII->isExtended(MI) || QII->isConstExtended(MI)) &&
294         "Should only be called for constant extended instructions");
295  MachineFunction *MF = MI->getParent()->getParent();
296  MachineInstr *PseudoMI = MF->CreateMachineInstr(QII->get(Hexagon::IMMEXT_i),
297                                                  MI->getDebugLoc());
298  bool CanReserve = ResourceTracker->canReserveResources(PseudoMI);
299  MF->DeleteMachineInstr(PseudoMI);
300  return CanReserve;
301}
302
303// Allocate resources (i.e. 4 bytes) for constant extender. If succeed, return
304// true, otherwise, return false.
305bool HexagonPacketizerList::tryAllocateResourcesForConstExt(MachineInstr* MI) {
306  const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
307  MachineFunction *MF = MI->getParent()->getParent();
308  MachineInstr *PseudoMI = MF->CreateMachineInstr(QII->get(Hexagon::IMMEXT_i),
309                                                  MI->getDebugLoc());
310
311  if (ResourceTracker->canReserveResources(PseudoMI)) {
312    ResourceTracker->reserveResources(PseudoMI);
313    MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);
314    return true;
315  } else {
316    MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);
317    return false;
318  }
319}
320
321
322bool HexagonPacketizerList::IsCallDependent(MachineInstr* MI,
323                                          SDep::Kind DepType,
324                                          unsigned DepReg) {
325
326  const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
327  const HexagonRegisterInfo* QRI =
328              (const HexagonRegisterInfo *) TM.getRegisterInfo();
329
330  // Check for lr dependence
331  if (DepReg == QRI->getRARegister()) {
332    return true;
333  }
334
335  if (QII->isDeallocRet(MI)) {
336    if (DepReg == QRI->getFrameRegister() ||
337        DepReg == QRI->getStackRegister())
338      return true;
339  }
340
341  // Check if this is a predicate dependence
342  const TargetRegisterClass* RC = QRI->getMinimalPhysRegClass(DepReg);
343  if (RC == &Hexagon::PredRegsRegClass) {
344    return true;
345  }
346
347  //
348  // Lastly check for an operand used in an indirect call
349  // If we had an attribute for checking if an instruction is an indirect call,
350  // then we could have avoided this relatively brittle implementation of
351  // IsIndirectCall()
352  //
353  // Assumes that the first operand of the CALLr is the function address
354  //
355  if (IsIndirectCall(MI) && (DepType == SDep::Data)) {
356    MachineOperand MO = MI->getOperand(0);
357    if (MO.isReg() && MO.isUse() && (MO.getReg() == DepReg)) {
358      return true;
359    }
360  }
361
362  return false;
363}
364
365static bool IsRegDependence(const SDep::Kind DepType) {
366  return (DepType == SDep::Data || DepType == SDep::Anti ||
367          DepType == SDep::Output);
368}
369
370static bool IsDirectJump(MachineInstr* MI) {
371  return (MI->getOpcode() == Hexagon::JMP);
372}
373
374static bool IsSchedBarrier(MachineInstr* MI) {
375  switch (MI->getOpcode()) {
376  case Hexagon::BARRIER:
377    return true;
378  }
379  return false;
380}
381
382static bool IsControlFlow(MachineInstr* MI) {
383  return (MI->getDesc().isTerminator() || MI->getDesc().isCall());
384}
385
386// Function returns true if an instruction can be promoted to the new-value
387// store. It will always return false for v2 and v3.
388// It lists all the conditional and unconditional stores that can be promoted
389// to the new-value stores.
390
391bool HexagonPacketizerList::IsNewifyStore (MachineInstr* MI) {
392  const HexagonRegisterInfo* QRI =
393                          (const HexagonRegisterInfo *) TM.getRegisterInfo();
394  switch (MI->getOpcode())
395  {
396    // store byte
397    case Hexagon::STrib:
398    case Hexagon::STrib_indexed:
399    case Hexagon::STrib_indexed_shl_V4:
400    case Hexagon::STrib_shl_V4:
401    case Hexagon::STb_GP_V4:
402    case Hexagon::POST_STbri:
403    case Hexagon::STrib_cPt:
404    case Hexagon::STrib_cdnPt_V4:
405    case Hexagon::STrib_cNotPt:
406    case Hexagon::STrib_cdnNotPt_V4:
407    case Hexagon::STrib_indexed_cPt:
408    case Hexagon::STrib_indexed_cdnPt_V4:
409    case Hexagon::STrib_indexed_cNotPt:
410    case Hexagon::STrib_indexed_cdnNotPt_V4:
411    case Hexagon::STrib_indexed_shl_cPt_V4:
412    case Hexagon::STrib_indexed_shl_cdnPt_V4:
413    case Hexagon::STrib_indexed_shl_cNotPt_V4:
414    case Hexagon::STrib_indexed_shl_cdnNotPt_V4:
415    case Hexagon::POST_STbri_cPt:
416    case Hexagon::POST_STbri_cdnPt_V4:
417    case Hexagon::POST_STbri_cNotPt:
418    case Hexagon::POST_STbri_cdnNotPt_V4:
419    case Hexagon::STb_GP_cPt_V4:
420    case Hexagon::STb_GP_cNotPt_V4:
421    case Hexagon::STb_GP_cdnPt_V4:
422    case Hexagon::STb_GP_cdnNotPt_V4:
423
424    // store halfword
425    case Hexagon::STrih:
426    case Hexagon::STrih_indexed:
427    case Hexagon::STrih_indexed_shl_V4:
428    case Hexagon::STrih_shl_V4:
429    case Hexagon::STh_GP_V4:
430    case Hexagon::POST_SThri:
431    case Hexagon::STrih_cPt:
432    case Hexagon::STrih_cdnPt_V4:
433    case Hexagon::STrih_cNotPt:
434    case Hexagon::STrih_cdnNotPt_V4:
435    case Hexagon::STrih_indexed_cPt:
436    case Hexagon::STrih_indexed_cdnPt_V4:
437    case Hexagon::STrih_indexed_cNotPt:
438    case Hexagon::STrih_indexed_cdnNotPt_V4:
439    case Hexagon::STrih_indexed_shl_cPt_V4:
440    case Hexagon::STrih_indexed_shl_cdnPt_V4:
441    case Hexagon::STrih_indexed_shl_cNotPt_V4:
442    case Hexagon::STrih_indexed_shl_cdnNotPt_V4:
443    case Hexagon::POST_SThri_cPt:
444    case Hexagon::POST_SThri_cdnPt_V4:
445    case Hexagon::POST_SThri_cNotPt:
446    case Hexagon::POST_SThri_cdnNotPt_V4:
447    case Hexagon::STh_GP_cPt_V4:
448    case Hexagon::STh_GP_cNotPt_V4:
449    case Hexagon::STh_GP_cdnPt_V4:
450    case Hexagon::STh_GP_cdnNotPt_V4:
451
452    // store word
453    case Hexagon::STriw:
454    case Hexagon::STriw_indexed:
455    case Hexagon::STriw_indexed_shl_V4:
456    case Hexagon::STriw_shl_V4:
457    case Hexagon::STw_GP_V4:
458    case Hexagon::POST_STwri:
459    case Hexagon::STriw_cPt:
460    case Hexagon::STriw_cdnPt_V4:
461    case Hexagon::STriw_cNotPt:
462    case Hexagon::STriw_cdnNotPt_V4:
463    case Hexagon::STriw_indexed_cPt:
464    case Hexagon::STriw_indexed_cdnPt_V4:
465    case Hexagon::STriw_indexed_cNotPt:
466    case Hexagon::STriw_indexed_cdnNotPt_V4:
467    case Hexagon::STriw_indexed_shl_cPt_V4:
468    case Hexagon::STriw_indexed_shl_cdnPt_V4:
469    case Hexagon::STriw_indexed_shl_cNotPt_V4:
470    case Hexagon::STriw_indexed_shl_cdnNotPt_V4:
471    case Hexagon::POST_STwri_cPt:
472    case Hexagon::POST_STwri_cdnPt_V4:
473    case Hexagon::POST_STwri_cNotPt:
474    case Hexagon::POST_STwri_cdnNotPt_V4:
475    case Hexagon::STw_GP_cPt_V4:
476    case Hexagon::STw_GP_cNotPt_V4:
477    case Hexagon::STw_GP_cdnPt_V4:
478    case Hexagon::STw_GP_cdnNotPt_V4:
479        return QRI->Subtarget.hasV4TOps();
480  }
481  return false;
482}
483
484static bool IsLoopN(MachineInstr *MI) {
485  return (MI->getOpcode() == Hexagon::LOOP0_i ||
486          MI->getOpcode() == Hexagon::LOOP0_r);
487}
488
489/// DoesModifyCalleeSavedReg - Returns true if the instruction modifies a
490/// callee-saved register.
491static bool DoesModifyCalleeSavedReg(MachineInstr *MI,
492                                     const TargetRegisterInfo *TRI) {
493  for (const uint16_t *CSR = TRI->getCalleeSavedRegs(); *CSR; ++CSR) {
494    unsigned CalleeSavedReg = *CSR;
495    if (MI->modifiesRegister(CalleeSavedReg, TRI))
496      return true;
497  }
498  return false;
499}
500
501// Return the new value instruction for a given store.
502static int GetDotNewOp(const int opc) {
503  switch (opc) {
504  default: llvm_unreachable("Unknown .new type");
505  // store new value byte
506  case Hexagon::STrib:
507    return Hexagon::STrib_nv_V4;
508
509  case Hexagon::STrib_indexed:
510    return Hexagon::STrib_indexed_nv_V4;
511
512  case Hexagon::STrib_indexed_shl_V4:
513    return Hexagon::STrib_indexed_shl_nv_V4;
514
515  case Hexagon::STrib_shl_V4:
516    return Hexagon::STrib_shl_nv_V4;
517
518  case Hexagon::STb_GP_V4:
519    return Hexagon::STb_GP_nv_V4;
520
521  case Hexagon::POST_STbri:
522    return Hexagon::POST_STbri_nv_V4;
523
524  case Hexagon::STrib_cPt:
525    return Hexagon::STrib_cPt_nv_V4;
526
527  case Hexagon::STrib_cdnPt_V4:
528    return Hexagon::STrib_cdnPt_nv_V4;
529
530  case Hexagon::STrib_cNotPt:
531    return Hexagon::STrib_cNotPt_nv_V4;
532
533  case Hexagon::STrib_cdnNotPt_V4:
534    return Hexagon::STrib_cdnNotPt_nv_V4;
535
536  case Hexagon::STrib_indexed_cPt:
537    return Hexagon::STrib_indexed_cPt_nv_V4;
538
539  case Hexagon::STrib_indexed_cdnPt_V4:
540    return Hexagon::STrib_indexed_cdnPt_nv_V4;
541
542  case Hexagon::STrib_indexed_cNotPt:
543    return Hexagon::STrib_indexed_cNotPt_nv_V4;
544
545  case Hexagon::STrib_indexed_cdnNotPt_V4:
546    return Hexagon::STrib_indexed_cdnNotPt_nv_V4;
547
548  case Hexagon::STrib_indexed_shl_cPt_V4:
549    return Hexagon::STrib_indexed_shl_cPt_nv_V4;
550
551  case Hexagon::STrib_indexed_shl_cdnPt_V4:
552    return Hexagon::STrib_indexed_shl_cdnPt_nv_V4;
553
554  case Hexagon::STrib_indexed_shl_cNotPt_V4:
555    return Hexagon::STrib_indexed_shl_cNotPt_nv_V4;
556
557  case Hexagon::STrib_indexed_shl_cdnNotPt_V4:
558    return Hexagon::STrib_indexed_shl_cdnNotPt_nv_V4;
559
560  case Hexagon::POST_STbri_cPt:
561    return Hexagon::POST_STbri_cPt_nv_V4;
562
563  case Hexagon::POST_STbri_cdnPt_V4:
564    return Hexagon::POST_STbri_cdnPt_nv_V4;
565
566  case Hexagon::POST_STbri_cNotPt:
567    return Hexagon::POST_STbri_cNotPt_nv_V4;
568
569  case Hexagon::POST_STbri_cdnNotPt_V4:
570    return Hexagon::POST_STbri_cdnNotPt_nv_V4;
571
572  case Hexagon::STb_GP_cPt_V4:
573    return Hexagon::STb_GP_cPt_nv_V4;
574
575  case Hexagon::STb_GP_cNotPt_V4:
576    return Hexagon::STb_GP_cNotPt_nv_V4;
577
578  case Hexagon::STb_GP_cdnPt_V4:
579    return Hexagon::STb_GP_cdnPt_nv_V4;
580
581  case Hexagon::STb_GP_cdnNotPt_V4:
582    return Hexagon::STb_GP_cdnNotPt_nv_V4;
583
584  // store new value halfword
585  case Hexagon::STrih:
586    return Hexagon::STrih_nv_V4;
587
588  case Hexagon::STrih_indexed:
589    return Hexagon::STrih_indexed_nv_V4;
590
591  case Hexagon::STrih_indexed_shl_V4:
592    return Hexagon::STrih_indexed_shl_nv_V4;
593
594  case Hexagon::STrih_shl_V4:
595    return Hexagon::STrih_shl_nv_V4;
596
597  case Hexagon::STh_GP_V4:
598    return Hexagon::STh_GP_nv_V4;
599
600  case Hexagon::POST_SThri:
601    return Hexagon::POST_SThri_nv_V4;
602
603  case Hexagon::STrih_cPt:
604    return Hexagon::STrih_cPt_nv_V4;
605
606  case Hexagon::STrih_cdnPt_V4:
607    return Hexagon::STrih_cdnPt_nv_V4;
608
609  case Hexagon::STrih_cNotPt:
610    return Hexagon::STrih_cNotPt_nv_V4;
611
612  case Hexagon::STrih_cdnNotPt_V4:
613    return Hexagon::STrih_cdnNotPt_nv_V4;
614
615  case Hexagon::STrih_indexed_cPt:
616    return Hexagon::STrih_indexed_cPt_nv_V4;
617
618  case Hexagon::STrih_indexed_cdnPt_V4:
619    return Hexagon::STrih_indexed_cdnPt_nv_V4;
620
621  case Hexagon::STrih_indexed_cNotPt:
622    return Hexagon::STrih_indexed_cNotPt_nv_V4;
623
624  case Hexagon::STrih_indexed_cdnNotPt_V4:
625    return Hexagon::STrih_indexed_cdnNotPt_nv_V4;
626
627  case Hexagon::STrih_indexed_shl_cPt_V4:
628    return Hexagon::STrih_indexed_shl_cPt_nv_V4;
629
630  case Hexagon::STrih_indexed_shl_cdnPt_V4:
631    return Hexagon::STrih_indexed_shl_cdnPt_nv_V4;
632
633  case Hexagon::STrih_indexed_shl_cNotPt_V4:
634    return Hexagon::STrih_indexed_shl_cNotPt_nv_V4;
635
636  case Hexagon::STrih_indexed_shl_cdnNotPt_V4:
637    return Hexagon::STrih_indexed_shl_cdnNotPt_nv_V4;
638
639  case Hexagon::POST_SThri_cPt:
640    return Hexagon::POST_SThri_cPt_nv_V4;
641
642  case Hexagon::POST_SThri_cdnPt_V4:
643    return Hexagon::POST_SThri_cdnPt_nv_V4;
644
645  case Hexagon::POST_SThri_cNotPt:
646    return Hexagon::POST_SThri_cNotPt_nv_V4;
647
648  case Hexagon::POST_SThri_cdnNotPt_V4:
649    return Hexagon::POST_SThri_cdnNotPt_nv_V4;
650
651  case Hexagon::STh_GP_cPt_V4:
652    return Hexagon::STh_GP_cPt_nv_V4;
653
654  case Hexagon::STh_GP_cNotPt_V4:
655    return Hexagon::STh_GP_cNotPt_nv_V4;
656
657  case Hexagon::STh_GP_cdnPt_V4:
658    return Hexagon::STh_GP_cdnPt_nv_V4;
659
660  case Hexagon::STh_GP_cdnNotPt_V4:
661    return Hexagon::STh_GP_cdnNotPt_nv_V4;
662
663  // store new value word
664  case Hexagon::STriw:
665    return Hexagon::STriw_nv_V4;
666
667  case Hexagon::STriw_indexed:
668    return Hexagon::STriw_indexed_nv_V4;
669
670  case Hexagon::STriw_indexed_shl_V4:
671    return Hexagon::STriw_indexed_shl_nv_V4;
672
673  case Hexagon::STriw_shl_V4:
674    return Hexagon::STriw_shl_nv_V4;
675
676  case Hexagon::STw_GP_V4:
677    return Hexagon::STw_GP_nv_V4;
678
679  case Hexagon::POST_STwri:
680    return Hexagon::POST_STwri_nv_V4;
681
682  case Hexagon::STriw_cPt:
683    return Hexagon::STriw_cPt_nv_V4;
684
685  case Hexagon::STriw_cdnPt_V4:
686    return Hexagon::STriw_cdnPt_nv_V4;
687
688  case Hexagon::STriw_cNotPt:
689    return Hexagon::STriw_cNotPt_nv_V4;
690
691  case Hexagon::STriw_cdnNotPt_V4:
692    return Hexagon::STriw_cdnNotPt_nv_V4;
693
694  case Hexagon::STriw_indexed_cPt:
695    return Hexagon::STriw_indexed_cPt_nv_V4;
696
697  case Hexagon::STriw_indexed_cdnPt_V4:
698    return Hexagon::STriw_indexed_cdnPt_nv_V4;
699
700  case Hexagon::STriw_indexed_cNotPt:
701    return Hexagon::STriw_indexed_cNotPt_nv_V4;
702
703  case Hexagon::STriw_indexed_cdnNotPt_V4:
704    return Hexagon::STriw_indexed_cdnNotPt_nv_V4;
705
706  case Hexagon::STriw_indexed_shl_cPt_V4:
707    return Hexagon::STriw_indexed_shl_cPt_nv_V4;
708
709  case Hexagon::STriw_indexed_shl_cdnPt_V4:
710    return Hexagon::STriw_indexed_shl_cdnPt_nv_V4;
711
712  case Hexagon::STriw_indexed_shl_cNotPt_V4:
713    return Hexagon::STriw_indexed_shl_cNotPt_nv_V4;
714
715  case Hexagon::STriw_indexed_shl_cdnNotPt_V4:
716    return Hexagon::STriw_indexed_shl_cdnNotPt_nv_V4;
717
718  case Hexagon::POST_STwri_cPt:
719    return Hexagon::POST_STwri_cPt_nv_V4;
720
721  case Hexagon::POST_STwri_cdnPt_V4:
722    return Hexagon::POST_STwri_cdnPt_nv_V4;
723
724  case Hexagon::POST_STwri_cNotPt:
725    return Hexagon::POST_STwri_cNotPt_nv_V4;
726
727  case Hexagon::POST_STwri_cdnNotPt_V4:
728    return Hexagon::POST_STwri_cdnNotPt_nv_V4;
729
730  case Hexagon::STw_GP_cPt_V4:
731    return Hexagon::STw_GP_cPt_nv_V4;
732
733  case Hexagon::STw_GP_cNotPt_V4:
734    return Hexagon::STw_GP_cNotPt_nv_V4;
735
736  case Hexagon::STw_GP_cdnPt_V4:
737    return Hexagon::STw_GP_cdnPt_nv_V4;
738
739  case Hexagon::STw_GP_cdnNotPt_V4:
740    return Hexagon::STw_GP_cdnNotPt_nv_V4;
741
742  }
743}
744
745// Returns true if an instruction can be promoted to .new predicate
746// or new-value store.
747bool HexagonPacketizerList::isNewifiable(MachineInstr* MI) {
748  if ( isCondInst(MI) || IsNewifyStore(MI))
749    return true;
750  else
751    return false;
752}
753
754bool HexagonPacketizerList::isCondInst (MachineInstr* MI) {
755  const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
756  const MCInstrDesc& TID = MI->getDesc();
757                                    // bug 5670: until that is fixed,
758                                    // this portion is disabled.
759  if (   TID.isConditionalBranch()  // && !IsRegisterJump(MI)) ||
760      || QII->isConditionalTransfer(MI)
761      || QII->isConditionalALU32(MI)
762      || QII->isConditionalLoad(MI)
763      || QII->isConditionalStore(MI)) {
764    return true;
765  }
766  return false;
767}
768
769
770// Promote an instructiont to its .new form.
771// At this time, we have already made a call to CanPromoteToDotNew
772// and made sure that it can *indeed* be promoted.
773bool HexagonPacketizerList::PromoteToDotNew(MachineInstr* MI,
774                        SDep::Kind DepType, MachineBasicBlock::iterator &MII,
775                        const TargetRegisterClass* RC) {
776
777  assert (DepType == SDep::Data);
778  const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
779
780  int NewOpcode;
781  if (RC == &Hexagon::PredRegsRegClass)
782    NewOpcode = QII->GetDotNewPredOp(MI, MBPI);
783  else
784    NewOpcode = GetDotNewOp(MI->getOpcode());
785  MI->setDesc(QII->get(NewOpcode));
786
787  return true;
788}
789
790// Returns the most basic instruction for the .new predicated instructions and
791// new-value stores.
792// For example, all of the following instructions will be converted back to the
793// same instruction:
794// 1) if (p0.new) memw(R0+#0) = R1.new  --->
795// 2) if (p0) memw(R0+#0)= R1.new      -------> if (p0) memw(R0+#0) = R1
796// 3) if (p0.new) memw(R0+#0) = R1      --->
797//
798// To understand the translation of instruction 1 to its original form, consider
799// a packet with 3 instructions.
800// { p0 = cmp.eq(R0,R1)
801//   if (p0.new) R2 = add(R3, R4)
802//   R5 = add (R3, R1)
803//   }
804// if (p0) memw(R5+#0) = R2 <--- trying to include it in the previous packet
805//
806// This instruction can be part of the previous packet only if both p0 and R2
807// are promoted to .new values. This promotion happens in steps, first
808// predicate register is promoted to .new and in the next iteration R2 is
809// promoted. Therefore, in case of dependence check failure (due to R5) during
810// next iteration, it should be converted back to its most basic form.
811
812static int GetDotOldOp(const int opc) {
813  switch (opc) {
814  default: llvm_unreachable("Unknown .old type");
815  case Hexagon::TFR_cdnPt:
816    return Hexagon::TFR_cPt;
817
818  case Hexagon::TFR_cdnNotPt:
819    return Hexagon::TFR_cNotPt;
820
821  case Hexagon::TFRI_cdnPt:
822    return Hexagon::TFRI_cPt;
823
824  case Hexagon::TFRI_cdnNotPt:
825    return Hexagon::TFRI_cNotPt;
826
827  case Hexagon::JMP_tnew_t:
828    return Hexagon::JMP_t;
829
830  case Hexagon::JMP_fnew_t:
831    return Hexagon::JMP_f;
832
833  case Hexagon::JMPR_tnew_tV3:
834    return Hexagon::JMPR_t;
835
836  case Hexagon::JMPR_fnew_tV3:
837    return Hexagon::JMPR_f;
838
839  // Load double word
840
841  case Hexagon::LDrid_cdnPt :
842    return Hexagon::LDrid_cPt;
843
844  case Hexagon::LDrid_cdnNotPt :
845    return Hexagon::LDrid_cNotPt;
846
847  case Hexagon::LDrid_indexed_cdnPt :
848    return Hexagon::LDrid_indexed_cPt;
849
850  case Hexagon::LDrid_indexed_cdnNotPt :
851    return Hexagon::LDrid_indexed_cNotPt;
852
853  case Hexagon::POST_LDrid_cdnPt_V4 :
854    return Hexagon::POST_LDrid_cPt;
855
856  case Hexagon::POST_LDrid_cdnNotPt_V4 :
857    return Hexagon::POST_LDrid_cNotPt;
858
859  // Load word
860
861  case Hexagon::LDriw_cdnPt :
862    return Hexagon::LDriw_cPt;
863
864  case Hexagon::LDriw_cdnNotPt :
865    return Hexagon::LDriw_cNotPt;
866
867  case Hexagon::LDriw_indexed_cdnPt :
868    return Hexagon::LDriw_indexed_cPt;
869
870  case Hexagon::LDriw_indexed_cdnNotPt :
871    return Hexagon::LDriw_indexed_cNotPt;
872
873  case Hexagon::POST_LDriw_cdnPt_V4 :
874    return Hexagon::POST_LDriw_cPt;
875
876  case Hexagon::POST_LDriw_cdnNotPt_V4 :
877    return Hexagon::POST_LDriw_cNotPt;
878
879  // Load half
880
881  case Hexagon::LDrih_cdnPt :
882    return Hexagon::LDrih_cPt;
883
884  case Hexagon::LDrih_cdnNotPt :
885    return Hexagon::LDrih_cNotPt;
886
887  case Hexagon::LDrih_indexed_cdnPt :
888    return Hexagon::LDrih_indexed_cPt;
889
890  case Hexagon::LDrih_indexed_cdnNotPt :
891    return Hexagon::LDrih_indexed_cNotPt;
892
893  case Hexagon::POST_LDrih_cdnPt_V4 :
894    return Hexagon::POST_LDrih_cPt;
895
896  case Hexagon::POST_LDrih_cdnNotPt_V4 :
897    return Hexagon::POST_LDrih_cNotPt;
898
899  // Load byte
900
901  case Hexagon::LDrib_cdnPt :
902    return Hexagon::LDrib_cPt;
903
904  case Hexagon::LDrib_cdnNotPt :
905    return Hexagon::LDrib_cNotPt;
906
907  case Hexagon::LDrib_indexed_cdnPt :
908    return Hexagon::LDrib_indexed_cPt;
909
910  case Hexagon::LDrib_indexed_cdnNotPt :
911    return Hexagon::LDrib_indexed_cNotPt;
912
913  case Hexagon::POST_LDrib_cdnPt_V4 :
914    return Hexagon::POST_LDrib_cPt;
915
916  case Hexagon::POST_LDrib_cdnNotPt_V4 :
917    return Hexagon::POST_LDrib_cNotPt;
918
919  // Load unsigned half
920
921  case Hexagon::LDriuh_cdnPt :
922    return Hexagon::LDriuh_cPt;
923
924  case Hexagon::LDriuh_cdnNotPt :
925    return Hexagon::LDriuh_cNotPt;
926
927  case Hexagon::LDriuh_indexed_cdnPt :
928    return Hexagon::LDriuh_indexed_cPt;
929
930  case Hexagon::LDriuh_indexed_cdnNotPt :
931    return Hexagon::LDriuh_indexed_cNotPt;
932
933  case Hexagon::POST_LDriuh_cdnPt_V4 :
934    return Hexagon::POST_LDriuh_cPt;
935
936  case Hexagon::POST_LDriuh_cdnNotPt_V4 :
937    return Hexagon::POST_LDriuh_cNotPt;
938
939  // Load unsigned byte
940  case Hexagon::LDriub_cdnPt :
941    return Hexagon::LDriub_cPt;
942
943  case Hexagon::LDriub_cdnNotPt :
944    return Hexagon::LDriub_cNotPt;
945
946  case Hexagon::LDriub_indexed_cdnPt :
947    return Hexagon::LDriub_indexed_cPt;
948
949  case Hexagon::LDriub_indexed_cdnNotPt :
950    return Hexagon::LDriub_indexed_cNotPt;
951
952  case Hexagon::POST_LDriub_cdnPt_V4 :
953    return Hexagon::POST_LDriub_cPt;
954
955  case Hexagon::POST_LDriub_cdnNotPt_V4 :
956    return Hexagon::POST_LDriub_cNotPt;
957
958  // V4 indexed+scaled Load
959
960  case Hexagon::LDrid_indexed_shl_cdnPt_V4 :
961    return Hexagon::LDrid_indexed_shl_cPt_V4;
962
963  case Hexagon::LDrid_indexed_shl_cdnNotPt_V4 :
964    return Hexagon::LDrid_indexed_shl_cNotPt_V4;
965
966  case Hexagon::LDrib_indexed_shl_cdnPt_V4 :
967    return Hexagon::LDrib_indexed_shl_cPt_V4;
968
969  case Hexagon::LDrib_indexed_shl_cdnNotPt_V4 :
970    return Hexagon::LDrib_indexed_shl_cNotPt_V4;
971
972  case Hexagon::LDriub_indexed_shl_cdnPt_V4 :
973    return Hexagon::LDriub_indexed_shl_cPt_V4;
974
975  case Hexagon::LDriub_indexed_shl_cdnNotPt_V4 :
976    return Hexagon::LDriub_indexed_shl_cNotPt_V4;
977
978  case Hexagon::LDrih_indexed_shl_cdnPt_V4 :
979    return Hexagon::LDrih_indexed_shl_cPt_V4;
980
981  case Hexagon::LDrih_indexed_shl_cdnNotPt_V4 :
982    return Hexagon::LDrih_indexed_shl_cNotPt_V4;
983
984  case Hexagon::LDriuh_indexed_shl_cdnPt_V4 :
985    return Hexagon::LDriuh_indexed_shl_cPt_V4;
986
987  case Hexagon::LDriuh_indexed_shl_cdnNotPt_V4 :
988    return Hexagon::LDriuh_indexed_shl_cNotPt_V4;
989
990  case Hexagon::LDriw_indexed_shl_cdnPt_V4 :
991    return Hexagon::LDriw_indexed_shl_cPt_V4;
992
993  case Hexagon::LDriw_indexed_shl_cdnNotPt_V4 :
994    return Hexagon::LDriw_indexed_shl_cNotPt_V4;
995
996  // V4 global address load
997
998  case Hexagon::LDd_GP_cdnPt_V4:
999    return Hexagon::LDd_GP_cPt_V4;
1000
1001  case Hexagon::LDd_GP_cdnNotPt_V4:
1002    return Hexagon::LDd_GP_cNotPt_V4;
1003
1004  case Hexagon::LDb_GP_cdnPt_V4:
1005    return Hexagon::LDb_GP_cPt_V4;
1006
1007  case Hexagon::LDb_GP_cdnNotPt_V4:
1008    return Hexagon::LDb_GP_cNotPt_V4;
1009
1010  case Hexagon::LDub_GP_cdnPt_V4:
1011    return Hexagon::LDub_GP_cPt_V4;
1012
1013  case Hexagon::LDub_GP_cdnNotPt_V4:
1014    return Hexagon::LDub_GP_cNotPt_V4;
1015
1016  case Hexagon::LDh_GP_cdnPt_V4:
1017    return Hexagon::LDh_GP_cPt_V4;
1018
1019  case Hexagon::LDh_GP_cdnNotPt_V4:
1020    return Hexagon::LDh_GP_cNotPt_V4;
1021
1022  case Hexagon::LDuh_GP_cdnPt_V4:
1023    return Hexagon::LDuh_GP_cPt_V4;
1024
1025  case Hexagon::LDuh_GP_cdnNotPt_V4:
1026    return Hexagon::LDuh_GP_cNotPt_V4;
1027
1028  case Hexagon::LDw_GP_cdnPt_V4:
1029    return Hexagon::LDw_GP_cPt_V4;
1030
1031  case Hexagon::LDw_GP_cdnNotPt_V4:
1032    return Hexagon::LDw_GP_cNotPt_V4;
1033
1034  // Conditional add
1035
1036  case Hexagon::ADD_ri_cdnPt :
1037    return Hexagon::ADD_ri_cPt;
1038  case Hexagon::ADD_ri_cdnNotPt :
1039    return Hexagon::ADD_ri_cNotPt;
1040
1041  case Hexagon::ADD_rr_cdnPt :
1042    return Hexagon::ADD_rr_cPt;
1043  case Hexagon::ADD_rr_cdnNotPt:
1044    return Hexagon::ADD_rr_cNotPt;
1045
1046  // Conditional logical Operations
1047
1048  case Hexagon::XOR_rr_cdnPt :
1049    return Hexagon::XOR_rr_cPt;
1050  case Hexagon::XOR_rr_cdnNotPt :
1051    return Hexagon::XOR_rr_cNotPt;
1052
1053  case Hexagon::AND_rr_cdnPt :
1054    return Hexagon::AND_rr_cPt;
1055  case Hexagon::AND_rr_cdnNotPt :
1056    return Hexagon::AND_rr_cNotPt;
1057
1058  case Hexagon::OR_rr_cdnPt :
1059    return Hexagon::OR_rr_cPt;
1060  case Hexagon::OR_rr_cdnNotPt :
1061    return Hexagon::OR_rr_cNotPt;
1062
1063  // Conditional Subtract
1064
1065  case Hexagon::SUB_rr_cdnPt :
1066    return Hexagon::SUB_rr_cPt;
1067  case Hexagon::SUB_rr_cdnNotPt :
1068    return Hexagon::SUB_rr_cNotPt;
1069
1070  // Conditional combine
1071
1072  case Hexagon::COMBINE_rr_cdnPt :
1073    return Hexagon::COMBINE_rr_cPt;
1074  case Hexagon::COMBINE_rr_cdnNotPt :
1075    return Hexagon::COMBINE_rr_cNotPt;
1076
1077// Conditional shift operations
1078
1079  case Hexagon::ASLH_cdnPt_V4 :
1080    return Hexagon::ASLH_cPt_V4;
1081  case Hexagon::ASLH_cdnNotPt_V4 :
1082    return Hexagon::ASLH_cNotPt_V4;
1083
1084  case Hexagon::ASRH_cdnPt_V4 :
1085    return Hexagon::ASRH_cPt_V4;
1086  case Hexagon::ASRH_cdnNotPt_V4 :
1087    return Hexagon::ASRH_cNotPt_V4;
1088
1089  case Hexagon::SXTB_cdnPt_V4 :
1090    return Hexagon::SXTB_cPt_V4;
1091  case Hexagon::SXTB_cdnNotPt_V4 :
1092    return Hexagon::SXTB_cNotPt_V4;
1093
1094  case Hexagon::SXTH_cdnPt_V4 :
1095    return Hexagon::SXTH_cPt_V4;
1096  case Hexagon::SXTH_cdnNotPt_V4 :
1097    return Hexagon::SXTH_cNotPt_V4;
1098
1099  case Hexagon::ZXTB_cdnPt_V4 :
1100    return Hexagon::ZXTB_cPt_V4;
1101  case Hexagon::ZXTB_cdnNotPt_V4 :
1102    return Hexagon::ZXTB_cNotPt_V4;
1103
1104  case Hexagon::ZXTH_cdnPt_V4 :
1105    return Hexagon::ZXTH_cPt_V4;
1106  case Hexagon::ZXTH_cdnNotPt_V4 :
1107    return Hexagon::ZXTH_cNotPt_V4;
1108
1109  // Store byte
1110
1111  case Hexagon::STrib_imm_cdnPt_V4 :
1112    return Hexagon::STrib_imm_cPt_V4;
1113
1114  case Hexagon::STrib_imm_cdnNotPt_V4 :
1115    return Hexagon::STrib_imm_cNotPt_V4;
1116
1117  case Hexagon::STrib_cdnPt_nv_V4 :
1118  case Hexagon::STrib_cPt_nv_V4 :
1119  case Hexagon::STrib_cdnPt_V4 :
1120    return Hexagon::STrib_cPt;
1121
1122  case Hexagon::STrib_cdnNotPt_nv_V4 :
1123  case Hexagon::STrib_cNotPt_nv_V4 :
1124  case Hexagon::STrib_cdnNotPt_V4 :
1125    return Hexagon::STrib_cNotPt;
1126
1127  case Hexagon::STrib_indexed_cdnPt_V4 :
1128  case Hexagon::STrib_indexed_cPt_nv_V4 :
1129  case Hexagon::STrib_indexed_cdnPt_nv_V4 :
1130    return Hexagon::STrib_indexed_cPt;
1131
1132  case Hexagon::STrib_indexed_cdnNotPt_V4 :
1133  case Hexagon::STrib_indexed_cNotPt_nv_V4 :
1134  case Hexagon::STrib_indexed_cdnNotPt_nv_V4 :
1135    return Hexagon::STrib_indexed_cNotPt;
1136
1137  case Hexagon::STrib_indexed_shl_cdnPt_nv_V4:
1138  case Hexagon::STrib_indexed_shl_cPt_nv_V4 :
1139  case Hexagon::STrib_indexed_shl_cdnPt_V4 :
1140    return Hexagon::STrib_indexed_shl_cPt_V4;
1141
1142  case Hexagon::STrib_indexed_shl_cdnNotPt_nv_V4:
1143  case Hexagon::STrib_indexed_shl_cNotPt_nv_V4 :
1144  case Hexagon::STrib_indexed_shl_cdnNotPt_V4 :
1145    return Hexagon::STrib_indexed_shl_cNotPt_V4;
1146
1147  case Hexagon::POST_STbri_cdnPt_nv_V4 :
1148  case Hexagon::POST_STbri_cPt_nv_V4 :
1149  case Hexagon::POST_STbri_cdnPt_V4 :
1150    return Hexagon::POST_STbri_cPt;
1151
1152  case Hexagon::POST_STbri_cdnNotPt_nv_V4 :
1153  case Hexagon::POST_STbri_cNotPt_nv_V4:
1154  case Hexagon::POST_STbri_cdnNotPt_V4 :
1155    return Hexagon::POST_STbri_cNotPt;
1156
1157  case Hexagon::STb_GP_cdnPt_nv_V4:
1158  case Hexagon::STb_GP_cdnPt_V4:
1159  case Hexagon::STb_GP_cPt_nv_V4:
1160    return Hexagon::STb_GP_cPt_V4;
1161
1162  case Hexagon::STb_GP_cdnNotPt_nv_V4:
1163  case Hexagon::STb_GP_cdnNotPt_V4:
1164  case Hexagon::STb_GP_cNotPt_nv_V4:
1165    return Hexagon::STb_GP_cNotPt_V4;
1166
1167  // Store new-value byte - unconditional
1168  case Hexagon::STrib_nv_V4:
1169    return Hexagon::STrib;
1170
1171  case Hexagon::STrib_indexed_nv_V4:
1172    return Hexagon::STrib_indexed;
1173
1174  case Hexagon::STrib_indexed_shl_nv_V4:
1175    return Hexagon::STrib_indexed_shl_V4;
1176
1177  case Hexagon::STrib_shl_nv_V4:
1178    return Hexagon::STrib_shl_V4;
1179
1180  case Hexagon::STb_GP_nv_V4:
1181    return Hexagon::STb_GP_V4;
1182
1183  case Hexagon::POST_STbri_nv_V4:
1184    return Hexagon::POST_STbri;
1185
1186  // Store halfword
1187  case Hexagon::STrih_imm_cdnPt_V4 :
1188    return Hexagon::STrih_imm_cPt_V4;
1189
1190  case Hexagon::STrih_imm_cdnNotPt_V4 :
1191    return Hexagon::STrih_imm_cNotPt_V4;
1192
1193  case Hexagon::STrih_cdnPt_nv_V4 :
1194  case Hexagon::STrih_cPt_nv_V4 :
1195  case Hexagon::STrih_cdnPt_V4 :
1196    return Hexagon::STrih_cPt;
1197
1198  case Hexagon::STrih_cdnNotPt_nv_V4 :
1199  case Hexagon::STrih_cNotPt_nv_V4 :
1200  case Hexagon::STrih_cdnNotPt_V4 :
1201    return Hexagon::STrih_cNotPt;
1202
1203  case Hexagon::STrih_indexed_cdnPt_nv_V4:
1204  case Hexagon::STrih_indexed_cPt_nv_V4 :
1205  case Hexagon::STrih_indexed_cdnPt_V4 :
1206    return Hexagon::STrih_indexed_cPt;
1207
1208  case Hexagon::STrih_indexed_cdnNotPt_nv_V4:
1209  case Hexagon::STrih_indexed_cNotPt_nv_V4 :
1210  case Hexagon::STrih_indexed_cdnNotPt_V4 :
1211    return Hexagon::STrih_indexed_cNotPt;
1212
1213  case Hexagon::STrih_indexed_shl_cdnPt_nv_V4 :
1214  case Hexagon::STrih_indexed_shl_cPt_nv_V4 :
1215  case Hexagon::STrih_indexed_shl_cdnPt_V4 :
1216    return Hexagon::STrih_indexed_shl_cPt_V4;
1217
1218  case Hexagon::STrih_indexed_shl_cdnNotPt_nv_V4 :
1219  case Hexagon::STrih_indexed_shl_cNotPt_nv_V4 :
1220  case Hexagon::STrih_indexed_shl_cdnNotPt_V4 :
1221    return Hexagon::STrih_indexed_shl_cNotPt_V4;
1222
1223  case Hexagon::POST_SThri_cdnPt_nv_V4 :
1224  case Hexagon::POST_SThri_cPt_nv_V4 :
1225  case Hexagon::POST_SThri_cdnPt_V4 :
1226    return Hexagon::POST_SThri_cPt;
1227
1228  case Hexagon::POST_SThri_cdnNotPt_nv_V4 :
1229  case Hexagon::POST_SThri_cNotPt_nv_V4 :
1230  case Hexagon::POST_SThri_cdnNotPt_V4 :
1231    return Hexagon::POST_SThri_cNotPt;
1232
1233  case Hexagon::STh_GP_cdnPt_nv_V4:
1234  case Hexagon::STh_GP_cdnPt_V4:
1235  case Hexagon::STh_GP_cPt_nv_V4:
1236    return Hexagon::STh_GP_cPt_V4;
1237
1238  case Hexagon::STh_GP_cdnNotPt_nv_V4:
1239  case Hexagon::STh_GP_cdnNotPt_V4:
1240  case Hexagon::STh_GP_cNotPt_nv_V4:
1241    return Hexagon::STh_GP_cNotPt_V4;
1242
1243  // Store new-value halfword - unconditional
1244
1245  case Hexagon::STrih_nv_V4:
1246    return Hexagon::STrih;
1247
1248  case Hexagon::STrih_indexed_nv_V4:
1249    return Hexagon::STrih_indexed;
1250
1251  case Hexagon::STrih_indexed_shl_nv_V4:
1252    return Hexagon::STrih_indexed_shl_V4;
1253
1254  case Hexagon::STrih_shl_nv_V4:
1255    return Hexagon::STrih_shl_V4;
1256
1257  case Hexagon::STh_GP_nv_V4:
1258    return Hexagon::STh_GP_V4;
1259
1260  case Hexagon::POST_SThri_nv_V4:
1261    return Hexagon::POST_SThri;
1262
1263   // Store word
1264
1265   case Hexagon::STriw_imm_cdnPt_V4 :
1266    return Hexagon::STriw_imm_cPt_V4;
1267
1268  case Hexagon::STriw_imm_cdnNotPt_V4 :
1269    return Hexagon::STriw_imm_cNotPt_V4;
1270
1271  case Hexagon::STriw_cdnPt_nv_V4 :
1272  case Hexagon::STriw_cPt_nv_V4 :
1273  case Hexagon::STriw_cdnPt_V4 :
1274    return Hexagon::STriw_cPt;
1275
1276  case Hexagon::STriw_cdnNotPt_nv_V4 :
1277  case Hexagon::STriw_cNotPt_nv_V4 :
1278  case Hexagon::STriw_cdnNotPt_V4 :
1279    return Hexagon::STriw_cNotPt;
1280
1281  case Hexagon::STriw_indexed_cdnPt_nv_V4 :
1282  case Hexagon::STriw_indexed_cPt_nv_V4 :
1283  case Hexagon::STriw_indexed_cdnPt_V4 :
1284    return Hexagon::STriw_indexed_cPt;
1285
1286  case Hexagon::STriw_indexed_cdnNotPt_nv_V4 :
1287  case Hexagon::STriw_indexed_cNotPt_nv_V4 :
1288  case Hexagon::STriw_indexed_cdnNotPt_V4 :
1289    return Hexagon::STriw_indexed_cNotPt;
1290
1291  case Hexagon::STriw_indexed_shl_cdnPt_nv_V4 :
1292  case Hexagon::STriw_indexed_shl_cPt_nv_V4 :
1293  case Hexagon::STriw_indexed_shl_cdnPt_V4 :
1294    return Hexagon::STriw_indexed_shl_cPt_V4;
1295
1296  case Hexagon::STriw_indexed_shl_cdnNotPt_nv_V4 :
1297  case Hexagon::STriw_indexed_shl_cNotPt_nv_V4 :
1298  case Hexagon::STriw_indexed_shl_cdnNotPt_V4 :
1299    return Hexagon::STriw_indexed_shl_cNotPt_V4;
1300
1301  case Hexagon::POST_STwri_cdnPt_nv_V4 :
1302  case Hexagon::POST_STwri_cPt_nv_V4 :
1303  case Hexagon::POST_STwri_cdnPt_V4 :
1304    return Hexagon::POST_STwri_cPt;
1305
1306  case Hexagon::POST_STwri_cdnNotPt_nv_V4 :
1307  case Hexagon::POST_STwri_cNotPt_nv_V4 :
1308  case Hexagon::POST_STwri_cdnNotPt_V4 :
1309    return Hexagon::POST_STwri_cNotPt;
1310
1311  case Hexagon::STw_GP_cdnPt_nv_V4:
1312  case Hexagon::STw_GP_cdnPt_V4:
1313  case Hexagon::STw_GP_cPt_nv_V4:
1314    return Hexagon::STw_GP_cPt_V4;
1315
1316  case Hexagon::STw_GP_cdnNotPt_nv_V4:
1317  case Hexagon::STw_GP_cdnNotPt_V4:
1318  case Hexagon::STw_GP_cNotPt_nv_V4:
1319    return Hexagon::STw_GP_cNotPt_V4;
1320
1321  // Store new-value word - unconditional
1322
1323  case Hexagon::STriw_nv_V4:
1324    return Hexagon::STriw;
1325
1326  case Hexagon::STriw_indexed_nv_V4:
1327    return Hexagon::STriw_indexed;
1328
1329  case Hexagon::STriw_indexed_shl_nv_V4:
1330    return Hexagon::STriw_indexed_shl_V4;
1331
1332  case Hexagon::STriw_shl_nv_V4:
1333    return Hexagon::STriw_shl_V4;
1334
1335  case Hexagon::STw_GP_nv_V4:
1336    return Hexagon::STw_GP_V4;
1337
1338  case Hexagon::POST_STwri_nv_V4:
1339    return Hexagon::POST_STwri;
1340
1341 // Store doubleword
1342
1343  case Hexagon::STrid_cdnPt_V4 :
1344    return Hexagon::STrid_cPt;
1345
1346  case Hexagon::STrid_cdnNotPt_V4 :
1347    return Hexagon::STrid_cNotPt;
1348
1349  case Hexagon::STrid_indexed_cdnPt_V4 :
1350    return Hexagon::STrid_indexed_cPt;
1351
1352  case Hexagon::STrid_indexed_cdnNotPt_V4 :
1353    return Hexagon::STrid_indexed_cNotPt;
1354
1355  case Hexagon::STrid_indexed_shl_cdnPt_V4 :
1356    return Hexagon::STrid_indexed_shl_cPt_V4;
1357
1358  case Hexagon::STrid_indexed_shl_cdnNotPt_V4 :
1359    return Hexagon::STrid_indexed_shl_cNotPt_V4;
1360
1361  case Hexagon::POST_STdri_cdnPt_V4 :
1362    return Hexagon::POST_STdri_cPt;
1363
1364  case Hexagon::POST_STdri_cdnNotPt_V4 :
1365    return Hexagon::POST_STdri_cNotPt;
1366
1367  case Hexagon::STd_GP_cdnPt_V4 :
1368    return Hexagon::STd_GP_cPt_V4;
1369
1370  case Hexagon::STd_GP_cdnNotPt_V4 :
1371    return Hexagon::STd_GP_cNotPt_V4;
1372
1373  }
1374}
1375
1376bool HexagonPacketizerList::DemoteToDotOld(MachineInstr* MI) {
1377  const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
1378  int NewOpcode = GetDotOldOp(MI->getOpcode());
1379  MI->setDesc(QII->get(NewOpcode));
1380  return true;
1381}
1382
1383// Returns true if an instruction is predicated on p0 and false if it's
1384// predicated on !p0.
1385
1386static bool GetPredicateSense(MachineInstr* MI,
1387                              const HexagonInstrInfo *QII) {
1388
1389  switch (MI->getOpcode()) {
1390  default: llvm_unreachable("Unknown predicate sense of the instruction");
1391  case Hexagon::TFR_cPt:
1392  case Hexagon::TFR_cdnPt:
1393  case Hexagon::TFRI_cPt:
1394  case Hexagon::TFRI_cdnPt:
1395  case Hexagon::STrib_cPt :
1396  case Hexagon::STrib_cdnPt_V4 :
1397  case Hexagon::STrib_indexed_cPt :
1398  case Hexagon::STrib_indexed_cdnPt_V4 :
1399  case Hexagon::STrib_indexed_shl_cPt_V4 :
1400  case Hexagon::STrib_indexed_shl_cdnPt_V4 :
1401  case Hexagon::POST_STbri_cPt :
1402  case Hexagon::POST_STbri_cdnPt_V4 :
1403  case Hexagon::STrih_cPt :
1404  case Hexagon::STrih_cdnPt_V4 :
1405  case Hexagon::STrih_indexed_cPt :
1406  case Hexagon::STrih_indexed_cdnPt_V4 :
1407  case Hexagon::STrih_indexed_shl_cPt_V4 :
1408  case Hexagon::STrih_indexed_shl_cdnPt_V4 :
1409  case Hexagon::POST_SThri_cPt :
1410  case Hexagon::POST_SThri_cdnPt_V4 :
1411  case Hexagon::STriw_cPt :
1412  case Hexagon::STriw_cdnPt_V4 :
1413  case Hexagon::STriw_indexed_cPt :
1414  case Hexagon::STriw_indexed_cdnPt_V4 :
1415  case Hexagon::STriw_indexed_shl_cPt_V4 :
1416  case Hexagon::STriw_indexed_shl_cdnPt_V4 :
1417  case Hexagon::POST_STwri_cPt :
1418  case Hexagon::POST_STwri_cdnPt_V4 :
1419  case Hexagon::STrib_imm_cPt_V4 :
1420  case Hexagon::STrib_imm_cdnPt_V4 :
1421  case Hexagon::STrid_cPt :
1422  case Hexagon::STrid_cdnPt_V4 :
1423  case Hexagon::STrid_indexed_cPt :
1424  case Hexagon::STrid_indexed_cdnPt_V4 :
1425  case Hexagon::STrid_indexed_shl_cPt_V4 :
1426  case Hexagon::STrid_indexed_shl_cdnPt_V4 :
1427  case Hexagon::POST_STdri_cPt :
1428  case Hexagon::POST_STdri_cdnPt_V4 :
1429  case Hexagon::STrih_imm_cPt_V4 :
1430  case Hexagon::STrih_imm_cdnPt_V4 :
1431  case Hexagon::STriw_imm_cPt_V4 :
1432  case Hexagon::STriw_imm_cdnPt_V4 :
1433  case Hexagon::JMP_tnew_t :
1434  case Hexagon::LDrid_cPt :
1435  case Hexagon::LDrid_cdnPt :
1436  case Hexagon::LDrid_indexed_cPt :
1437  case Hexagon::LDrid_indexed_cdnPt :
1438  case Hexagon::POST_LDrid_cPt :
1439  case Hexagon::POST_LDrid_cdnPt_V4 :
1440  case Hexagon::LDriw_cPt :
1441  case Hexagon::LDriw_cdnPt :
1442  case Hexagon::LDriw_indexed_cPt :
1443  case Hexagon::LDriw_indexed_cdnPt :
1444  case Hexagon::POST_LDriw_cPt :
1445  case Hexagon::POST_LDriw_cdnPt_V4 :
1446  case Hexagon::LDrih_cPt :
1447  case Hexagon::LDrih_cdnPt :
1448  case Hexagon::LDrih_indexed_cPt :
1449  case Hexagon::LDrih_indexed_cdnPt :
1450  case Hexagon::POST_LDrih_cPt :
1451  case Hexagon::POST_LDrih_cdnPt_V4 :
1452  case Hexagon::LDrib_cPt :
1453  case Hexagon::LDrib_cdnPt :
1454  case Hexagon::LDrib_indexed_cPt :
1455  case Hexagon::LDrib_indexed_cdnPt :
1456  case Hexagon::POST_LDrib_cPt :
1457  case Hexagon::POST_LDrib_cdnPt_V4 :
1458  case Hexagon::LDriuh_cPt :
1459  case Hexagon::LDriuh_cdnPt :
1460  case Hexagon::LDriuh_indexed_cPt :
1461  case Hexagon::LDriuh_indexed_cdnPt :
1462  case Hexagon::POST_LDriuh_cPt :
1463  case Hexagon::POST_LDriuh_cdnPt_V4 :
1464  case Hexagon::LDriub_cPt :
1465  case Hexagon::LDriub_cdnPt :
1466  case Hexagon::LDriub_indexed_cPt :
1467  case Hexagon::LDriub_indexed_cdnPt :
1468  case Hexagon::POST_LDriub_cPt :
1469  case Hexagon::POST_LDriub_cdnPt_V4 :
1470  case Hexagon::LDrid_indexed_shl_cPt_V4 :
1471  case Hexagon::LDrid_indexed_shl_cdnPt_V4 :
1472  case Hexagon::LDrib_indexed_shl_cPt_V4 :
1473  case Hexagon::LDrib_indexed_shl_cdnPt_V4 :
1474  case Hexagon::LDriub_indexed_shl_cPt_V4 :
1475  case Hexagon::LDriub_indexed_shl_cdnPt_V4 :
1476  case Hexagon::LDrih_indexed_shl_cPt_V4 :
1477  case Hexagon::LDrih_indexed_shl_cdnPt_V4 :
1478  case Hexagon::LDriuh_indexed_shl_cPt_V4 :
1479  case Hexagon::LDriuh_indexed_shl_cdnPt_V4 :
1480  case Hexagon::LDriw_indexed_shl_cPt_V4 :
1481  case Hexagon::LDriw_indexed_shl_cdnPt_V4 :
1482  case Hexagon::ADD_ri_cPt :
1483  case Hexagon::ADD_ri_cdnPt :
1484  case Hexagon::ADD_rr_cPt :
1485  case Hexagon::ADD_rr_cdnPt :
1486  case Hexagon::XOR_rr_cPt :
1487  case Hexagon::XOR_rr_cdnPt :
1488  case Hexagon::AND_rr_cPt :
1489  case Hexagon::AND_rr_cdnPt :
1490  case Hexagon::OR_rr_cPt :
1491  case Hexagon::OR_rr_cdnPt :
1492  case Hexagon::SUB_rr_cPt :
1493  case Hexagon::SUB_rr_cdnPt :
1494  case Hexagon::COMBINE_rr_cPt :
1495  case Hexagon::COMBINE_rr_cdnPt :
1496  case Hexagon::ASLH_cPt_V4 :
1497  case Hexagon::ASLH_cdnPt_V4 :
1498  case Hexagon::ASRH_cPt_V4 :
1499  case Hexagon::ASRH_cdnPt_V4 :
1500  case Hexagon::SXTB_cPt_V4 :
1501  case Hexagon::SXTB_cdnPt_V4 :
1502  case Hexagon::SXTH_cPt_V4 :
1503  case Hexagon::SXTH_cdnPt_V4 :
1504  case Hexagon::ZXTB_cPt_V4 :
1505  case Hexagon::ZXTB_cdnPt_V4 :
1506  case Hexagon::ZXTH_cPt_V4 :
1507  case Hexagon::ZXTH_cdnPt_V4 :
1508  case Hexagon::LDd_GP_cPt_V4 :
1509  case Hexagon::LDb_GP_cPt_V4 :
1510  case Hexagon::LDub_GP_cPt_V4 :
1511  case Hexagon::LDh_GP_cPt_V4 :
1512  case Hexagon::LDuh_GP_cPt_V4 :
1513  case Hexagon::LDw_GP_cPt_V4 :
1514  case Hexagon::STd_GP_cPt_V4 :
1515  case Hexagon::STb_GP_cPt_V4 :
1516  case Hexagon::STh_GP_cPt_V4 :
1517  case Hexagon::STw_GP_cPt_V4 :
1518  case Hexagon::LDd_GP_cdnPt_V4 :
1519  case Hexagon::LDb_GP_cdnPt_V4 :
1520  case Hexagon::LDub_GP_cdnPt_V4 :
1521  case Hexagon::LDh_GP_cdnPt_V4 :
1522  case Hexagon::LDuh_GP_cdnPt_V4 :
1523  case Hexagon::LDw_GP_cdnPt_V4 :
1524  case Hexagon::STd_GP_cdnPt_V4 :
1525  case Hexagon::STb_GP_cdnPt_V4 :
1526  case Hexagon::STh_GP_cdnPt_V4 :
1527  case Hexagon::STw_GP_cdnPt_V4 :
1528    return true;
1529
1530  case Hexagon::TFR_cNotPt:
1531  case Hexagon::TFR_cdnNotPt:
1532  case Hexagon::TFRI_cNotPt:
1533  case Hexagon::TFRI_cdnNotPt:
1534  case Hexagon::STrib_cNotPt :
1535  case Hexagon::STrib_cdnNotPt_V4 :
1536  case Hexagon::STrib_indexed_cNotPt :
1537  case Hexagon::STrib_indexed_cdnNotPt_V4 :
1538  case Hexagon::STrib_indexed_shl_cNotPt_V4 :
1539  case Hexagon::STrib_indexed_shl_cdnNotPt_V4 :
1540  case Hexagon::POST_STbri_cNotPt :
1541  case Hexagon::POST_STbri_cdnNotPt_V4 :
1542  case Hexagon::STrih_cNotPt :
1543  case Hexagon::STrih_cdnNotPt_V4 :
1544  case Hexagon::STrih_indexed_cNotPt :
1545  case Hexagon::STrih_indexed_cdnNotPt_V4 :
1546  case Hexagon::STrih_indexed_shl_cNotPt_V4 :
1547  case Hexagon::STrih_indexed_shl_cdnNotPt_V4 :
1548  case Hexagon::POST_SThri_cNotPt :
1549  case Hexagon::POST_SThri_cdnNotPt_V4 :
1550  case Hexagon::STriw_cNotPt :
1551  case Hexagon::STriw_cdnNotPt_V4 :
1552  case Hexagon::STriw_indexed_cNotPt :
1553  case Hexagon::STriw_indexed_cdnNotPt_V4 :
1554  case Hexagon::STriw_indexed_shl_cNotPt_V4 :
1555  case Hexagon::STriw_indexed_shl_cdnNotPt_V4 :
1556  case Hexagon::POST_STwri_cNotPt :
1557  case Hexagon::POST_STwri_cdnNotPt_V4 :
1558  case Hexagon::STrib_imm_cNotPt_V4 :
1559  case Hexagon::STrib_imm_cdnNotPt_V4 :
1560  case Hexagon::STrid_cNotPt :
1561  case Hexagon::STrid_cdnNotPt_V4 :
1562  case Hexagon::STrid_indexed_cdnNotPt_V4 :
1563  case Hexagon::STrid_indexed_cNotPt :
1564  case Hexagon::STrid_indexed_shl_cNotPt_V4 :
1565  case Hexagon::STrid_indexed_shl_cdnNotPt_V4 :
1566  case Hexagon::POST_STdri_cNotPt :
1567  case Hexagon::POST_STdri_cdnNotPt_V4 :
1568  case Hexagon::STrih_imm_cNotPt_V4 :
1569  case Hexagon::STrih_imm_cdnNotPt_V4 :
1570  case Hexagon::STriw_imm_cNotPt_V4 :
1571  case Hexagon::STriw_imm_cdnNotPt_V4 :
1572  case Hexagon::JMP_fnew_t :
1573  case Hexagon::LDrid_cNotPt :
1574  case Hexagon::LDrid_cdnNotPt :
1575  case Hexagon::LDrid_indexed_cNotPt :
1576  case Hexagon::LDrid_indexed_cdnNotPt :
1577  case Hexagon::POST_LDrid_cNotPt :
1578  case Hexagon::POST_LDrid_cdnNotPt_V4 :
1579  case Hexagon::LDriw_cNotPt :
1580  case Hexagon::LDriw_cdnNotPt :
1581  case Hexagon::LDriw_indexed_cNotPt :
1582  case Hexagon::LDriw_indexed_cdnNotPt :
1583  case Hexagon::POST_LDriw_cNotPt :
1584  case Hexagon::POST_LDriw_cdnNotPt_V4 :
1585  case Hexagon::LDrih_cNotPt :
1586  case Hexagon::LDrih_cdnNotPt :
1587  case Hexagon::LDrih_indexed_cNotPt :
1588  case Hexagon::LDrih_indexed_cdnNotPt :
1589  case Hexagon::POST_LDrih_cNotPt :
1590  case Hexagon::POST_LDrih_cdnNotPt_V4 :
1591  case Hexagon::LDrib_cNotPt :
1592  case Hexagon::LDrib_cdnNotPt :
1593  case Hexagon::LDrib_indexed_cNotPt :
1594  case Hexagon::LDrib_indexed_cdnNotPt :
1595  case Hexagon::POST_LDrib_cNotPt :
1596  case Hexagon::POST_LDrib_cdnNotPt_V4 :
1597  case Hexagon::LDriuh_cNotPt :
1598  case Hexagon::LDriuh_cdnNotPt :
1599  case Hexagon::LDriuh_indexed_cNotPt :
1600  case Hexagon::LDriuh_indexed_cdnNotPt :
1601  case Hexagon::POST_LDriuh_cNotPt :
1602  case Hexagon::POST_LDriuh_cdnNotPt_V4 :
1603  case Hexagon::LDriub_cNotPt :
1604  case Hexagon::LDriub_cdnNotPt :
1605  case Hexagon::LDriub_indexed_cNotPt :
1606  case Hexagon::LDriub_indexed_cdnNotPt :
1607  case Hexagon::POST_LDriub_cNotPt :
1608  case Hexagon::POST_LDriub_cdnNotPt_V4 :
1609  case Hexagon::LDrid_indexed_shl_cNotPt_V4 :
1610  case Hexagon::LDrid_indexed_shl_cdnNotPt_V4 :
1611  case Hexagon::LDrib_indexed_shl_cNotPt_V4 :
1612  case Hexagon::LDrib_indexed_shl_cdnNotPt_V4 :
1613  case Hexagon::LDriub_indexed_shl_cNotPt_V4 :
1614  case Hexagon::LDriub_indexed_shl_cdnNotPt_V4 :
1615  case Hexagon::LDrih_indexed_shl_cNotPt_V4 :
1616  case Hexagon::LDrih_indexed_shl_cdnNotPt_V4 :
1617  case Hexagon::LDriuh_indexed_shl_cNotPt_V4 :
1618  case Hexagon::LDriuh_indexed_shl_cdnNotPt_V4 :
1619  case Hexagon::LDriw_indexed_shl_cNotPt_V4 :
1620  case Hexagon::LDriw_indexed_shl_cdnNotPt_V4 :
1621  case Hexagon::ADD_ri_cNotPt :
1622  case Hexagon::ADD_ri_cdnNotPt :
1623  case Hexagon::ADD_rr_cNotPt :
1624  case Hexagon::ADD_rr_cdnNotPt :
1625  case Hexagon::XOR_rr_cNotPt :
1626  case Hexagon::XOR_rr_cdnNotPt :
1627  case Hexagon::AND_rr_cNotPt :
1628  case Hexagon::AND_rr_cdnNotPt :
1629  case Hexagon::OR_rr_cNotPt :
1630  case Hexagon::OR_rr_cdnNotPt :
1631  case Hexagon::SUB_rr_cNotPt :
1632  case Hexagon::SUB_rr_cdnNotPt :
1633  case Hexagon::COMBINE_rr_cNotPt :
1634  case Hexagon::COMBINE_rr_cdnNotPt :
1635  case Hexagon::ASLH_cNotPt_V4 :
1636  case Hexagon::ASLH_cdnNotPt_V4 :
1637  case Hexagon::ASRH_cNotPt_V4 :
1638  case Hexagon::ASRH_cdnNotPt_V4 :
1639  case Hexagon::SXTB_cNotPt_V4 :
1640  case Hexagon::SXTB_cdnNotPt_V4 :
1641  case Hexagon::SXTH_cNotPt_V4 :
1642  case Hexagon::SXTH_cdnNotPt_V4 :
1643  case Hexagon::ZXTB_cNotPt_V4 :
1644  case Hexagon::ZXTB_cdnNotPt_V4 :
1645  case Hexagon::ZXTH_cNotPt_V4 :
1646  case Hexagon::ZXTH_cdnNotPt_V4 :
1647
1648  case Hexagon::LDd_GP_cNotPt_V4 :
1649  case Hexagon::LDb_GP_cNotPt_V4 :
1650  case Hexagon::LDub_GP_cNotPt_V4 :
1651  case Hexagon::LDh_GP_cNotPt_V4 :
1652  case Hexagon::LDuh_GP_cNotPt_V4 :
1653  case Hexagon::LDw_GP_cNotPt_V4 :
1654  case Hexagon::STd_GP_cNotPt_V4 :
1655  case Hexagon::STb_GP_cNotPt_V4 :
1656  case Hexagon::STh_GP_cNotPt_V4 :
1657  case Hexagon::STw_GP_cNotPt_V4 :
1658  case Hexagon::LDd_GP_cdnNotPt_V4 :
1659  case Hexagon::LDb_GP_cdnNotPt_V4 :
1660  case Hexagon::LDub_GP_cdnNotPt_V4 :
1661  case Hexagon::LDh_GP_cdnNotPt_V4 :
1662  case Hexagon::LDuh_GP_cdnNotPt_V4 :
1663  case Hexagon::LDw_GP_cdnNotPt_V4 :
1664  case Hexagon::STd_GP_cdnNotPt_V4 :
1665  case Hexagon::STb_GP_cdnNotPt_V4 :
1666  case Hexagon::STh_GP_cdnNotPt_V4 :
1667  case Hexagon::STw_GP_cdnNotPt_V4 :
1668    return false;
1669  }
1670  // return *some value* to avoid compiler warning
1671  return false;
1672}
1673
1674static MachineOperand& GetPostIncrementOperand(MachineInstr *MI,
1675                                               const HexagonInstrInfo *QII) {
1676  assert(QII->isPostIncrement(MI) && "Not a post increment operation.");
1677#ifndef NDEBUG
1678  // Post Increment means duplicates. Use dense map to find duplicates in the
1679  // list. Caution: Densemap initializes with the minimum of 64 buckets,
1680  // whereas there are at most 5 operands in the post increment.
1681  DenseMap<unsigned,  unsigned> DefRegsSet;
1682  for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++)
1683    if (MI->getOperand(opNum).isReg() &&
1684        MI->getOperand(opNum).isDef()) {
1685      DefRegsSet[MI->getOperand(opNum).getReg()] = 1;
1686    }
1687
1688  for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++)
1689    if (MI->getOperand(opNum).isReg() &&
1690        MI->getOperand(opNum).isUse()) {
1691      if (DefRegsSet[MI->getOperand(opNum).getReg()]) {
1692        return MI->getOperand(opNum);
1693      }
1694    }
1695#else
1696  if (MI->getDesc().mayLoad()) {
1697    // The 2nd operand is always the post increment operand in load.
1698    assert(MI->getOperand(1).isReg() &&
1699                "Post increment operand has be to a register.");
1700    return (MI->getOperand(1));
1701  }
1702  if (MI->getDesc().mayStore()) {
1703    // The 1st operand is always the post increment operand in store.
1704    assert(MI->getOperand(0).isReg() &&
1705                "Post increment operand has be to a register.");
1706    return (MI->getOperand(0));
1707  }
1708#endif
1709  // we should never come here.
1710  llvm_unreachable("mayLoad or mayStore not set for Post Increment operation");
1711}
1712
1713// get the value being stored
1714static MachineOperand& GetStoreValueOperand(MachineInstr *MI) {
1715  // value being stored is always the last operand.
1716  return (MI->getOperand(MI->getNumOperands()-1));
1717}
1718
1719// can be new value store?
1720// Following restrictions are to be respected in convert a store into
1721// a new value store.
1722// 1. If an instruction uses auto-increment, its address register cannot
1723//    be a new-value register. Arch Spec 5.4.2.1
1724// 2. If an instruction uses absolute-set addressing mode,
1725//    its address register cannot be a new-value register.
1726//    Arch Spec 5.4.2.1.TODO: This is not enabled as
1727//    as absolute-set address mode patters are not implemented.
1728// 3. If an instruction produces a 64-bit result, its registers cannot be used
1729//    as new-value registers. Arch Spec 5.4.2.2.
1730// 4. If the instruction that sets a new-value register is conditional, then
1731//    the instruction that uses the new-value register must also be conditional,
1732//    and both must always have their predicates evaluate identically.
1733//    Arch Spec 5.4.2.3.
1734// 5. There is an implied restriction of a packet can not have another store,
1735//    if there is a  new value store in the packet. Corollary, if there is
1736//    already a store in a packet, there can not be a new value store.
1737//    Arch Spec: 3.4.4.2
1738bool HexagonPacketizerList::CanPromoteToNewValueStore( MachineInstr *MI,
1739                MachineInstr *PacketMI, unsigned DepReg,
1740                std::map <MachineInstr*, SUnit*> MIToSUnit)
1741{
1742  // Make sure we are looking at the store
1743  if (!IsNewifyStore(MI))
1744    return false;
1745
1746  // Make sure there is dependency and can be new value'ed
1747  if (GetStoreValueOperand(MI).isReg() &&
1748      GetStoreValueOperand(MI).getReg() != DepReg)
1749    return false;
1750
1751  const HexagonRegisterInfo* QRI =
1752                            (const HexagonRegisterInfo *) TM.getRegisterInfo();
1753  const MCInstrDesc& MCID = PacketMI->getDesc();
1754  // first operand is always the result
1755
1756  const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
1757  const TargetRegisterClass* PacketRC = QII->getRegClass(MCID, 0, QRI, MF);
1758
1759  // if there is already an store in the packet, no can do new value store
1760  // Arch Spec 3.4.4.2.
1761  for (std::vector<MachineInstr*>::iterator VI = CurrentPacketMIs.begin(),
1762         VE = CurrentPacketMIs.end();
1763       (VI != VE); ++VI) {
1764    SUnit* PacketSU = MIToSUnit[*VI];
1765    if (PacketSU->getInstr()->getDesc().mayStore() ||
1766        // if we have mayStore = 1 set on ALLOCFRAME and DEALLOCFRAME,
1767        // then we don't need this
1768        PacketSU->getInstr()->getOpcode() == Hexagon::ALLOCFRAME ||
1769        PacketSU->getInstr()->getOpcode() == Hexagon::DEALLOCFRAME)
1770      return false;
1771  }
1772
1773  if (PacketRC == &Hexagon::DoubleRegsRegClass) {
1774    // new value store constraint: double regs can not feed into new value store
1775    // arch spec section: 5.4.2.2
1776    return false;
1777  }
1778
1779  // Make sure it's NOT the post increment register that we are going to
1780  // new value.
1781  if (QII->isPostIncrement(MI) &&
1782      MI->getDesc().mayStore() &&
1783      GetPostIncrementOperand(MI, QII).getReg() == DepReg) {
1784    return false;
1785  }
1786
1787  if (QII->isPostIncrement(PacketMI) &&
1788      PacketMI->getDesc().mayLoad() &&
1789      GetPostIncrementOperand(PacketMI, QII).getReg() == DepReg) {
1790    // if source is post_inc, or absolute-set addressing,
1791    // it can not feed into new value store
1792    //  r3 = memw(r2++#4)
1793    //  memw(r30 + #-1404) = r2.new -> can not be new value store
1794    // arch spec section: 5.4.2.1
1795    return false;
1796  }
1797
1798  // If the source that feeds the store is predicated, new value store must
1799  // also be also predicated.
1800  if (QII->isPredicated(PacketMI)) {
1801    if (!QII->isPredicated(MI))
1802      return false;
1803
1804    // Check to make sure that they both will have their predicates
1805    // evaluate identically
1806    unsigned predRegNumSrc = 0;
1807    unsigned predRegNumDst = 0;
1808    const TargetRegisterClass* predRegClass = NULL;
1809
1810    // Get predicate register used in the source instruction
1811    for(unsigned opNum = 0; opNum < PacketMI->getNumOperands(); opNum++) {
1812      if ( PacketMI->getOperand(opNum).isReg())
1813      predRegNumSrc = PacketMI->getOperand(opNum).getReg();
1814      predRegClass = QRI->getMinimalPhysRegClass(predRegNumSrc);
1815      if (predRegClass == &Hexagon::PredRegsRegClass) {
1816        break;
1817      }
1818    }
1819    assert ((predRegClass == &Hexagon::PredRegsRegClass ) &&
1820        ("predicate register not found in a predicated PacketMI instruction"));
1821
1822    // Get predicate register used in new-value store instruction
1823    for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++) {
1824      if ( MI->getOperand(opNum).isReg())
1825      predRegNumDst = MI->getOperand(opNum).getReg();
1826      predRegClass = QRI->getMinimalPhysRegClass(predRegNumDst);
1827      if (predRegClass == &Hexagon::PredRegsRegClass) {
1828        break;
1829      }
1830    }
1831    assert ((predRegClass == &Hexagon::PredRegsRegClass ) &&
1832            ("predicate register not found in a predicated MI instruction"));
1833
1834    // New-value register producer and user (store) need to satisfy these
1835    // constraints:
1836    // 1) Both instructions should be predicated on the same register.
1837    // 2) If producer of the new-value register is .new predicated then store
1838    // should also be .new predicated and if producer is not .new predicated
1839    // then store should not be .new predicated.
1840    // 3) Both new-value register producer and user should have same predicate
1841    // sense, i.e, either both should be negated or both should be none negated.
1842
1843    if (( predRegNumDst != predRegNumSrc) ||
1844          QII->isDotNewInst(PacketMI) != QII->isDotNewInst(MI)  ||
1845          GetPredicateSense(MI, QII) != GetPredicateSense(PacketMI, QII)) {
1846      return false;
1847    }
1848  }
1849
1850  // Make sure that other than the new-value register no other store instruction
1851  // register has been modified in the same packet. Predicate registers can be
1852  // modified by they should not be modified between the producer and the store
1853  // instruction as it will make them both conditional on different values.
1854  // We already know this to be true for all the instructions before and
1855  // including PacketMI. Howerver, we need to perform the check for the
1856  // remaining instructions in the packet.
1857
1858  std::vector<MachineInstr*>::iterator VI;
1859  std::vector<MachineInstr*>::iterator VE;
1860  unsigned StartCheck = 0;
1861
1862  for (VI=CurrentPacketMIs.begin(), VE = CurrentPacketMIs.end();
1863      (VI != VE); ++VI) {
1864    SUnit* TempSU = MIToSUnit[*VI];
1865    MachineInstr* TempMI = TempSU->getInstr();
1866
1867    // Following condition is true for all the instructions until PacketMI is
1868    // reached (StartCheck is set to 0 before the for loop).
1869    // StartCheck flag is 1 for all the instructions after PacketMI.
1870    if (TempMI != PacketMI && !StartCheck) // start processing only after
1871      continue;                            // encountering PacketMI
1872
1873    StartCheck = 1;
1874    if (TempMI == PacketMI) // We don't want to check PacketMI for dependence
1875      continue;
1876
1877    for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++) {
1878      if (MI->getOperand(opNum).isReg() &&
1879          TempSU->getInstr()->modifiesRegister(MI->getOperand(opNum).getReg(),
1880                                               QRI))
1881        return false;
1882    }
1883  }
1884
1885  // Make sure that for non POST_INC stores:
1886  // 1. The only use of reg is DepReg and no other registers.
1887  //    This handles V4 base+index registers.
1888  //    The following store can not be dot new.
1889  //    Eg.   r0 = add(r0, #3)a
1890  //          memw(r1+r0<<#2) = r0
1891  if (!QII->isPostIncrement(MI) &&
1892      GetStoreValueOperand(MI).isReg() &&
1893      GetStoreValueOperand(MI).getReg() == DepReg) {
1894    for(unsigned opNum = 0; opNum < MI->getNumOperands()-1; opNum++) {
1895      if (MI->getOperand(opNum).isReg() &&
1896          MI->getOperand(opNum).getReg() == DepReg) {
1897        return false;
1898      }
1899    }
1900    // 2. If data definition is because of implicit definition of the register,
1901    //    do not newify the store. Eg.
1902    //    %R9<def> = ZXTH %R12, %D6<imp-use>, %R12<imp-def>
1903    //    STrih_indexed %R8, 2, %R12<kill>; mem:ST2[%scevgep343]
1904    for(unsigned opNum = 0; opNum < PacketMI->getNumOperands(); opNum++) {
1905      if (PacketMI->getOperand(opNum).isReg() &&
1906          PacketMI->getOperand(opNum).getReg() == DepReg &&
1907          PacketMI->getOperand(opNum).isDef() &&
1908          PacketMI->getOperand(opNum).isImplicit()) {
1909        return false;
1910      }
1911    }
1912  }
1913
1914  // Can be dot new store.
1915  return true;
1916}
1917
1918// can this MI to promoted to either
1919// new value store or new value jump
1920bool HexagonPacketizerList::CanPromoteToNewValue( MachineInstr *MI,
1921                SUnit *PacketSU, unsigned DepReg,
1922                std::map <MachineInstr*, SUnit*> MIToSUnit,
1923                MachineBasicBlock::iterator &MII)
1924{
1925
1926  const HexagonRegisterInfo* QRI =
1927                            (const HexagonRegisterInfo *) TM.getRegisterInfo();
1928  if (!QRI->Subtarget.hasV4TOps() ||
1929      !IsNewifyStore(MI))
1930    return false;
1931
1932  MachineInstr *PacketMI = PacketSU->getInstr();
1933
1934  // Check to see the store can be new value'ed.
1935  if (CanPromoteToNewValueStore(MI, PacketMI, DepReg, MIToSUnit))
1936    return true;
1937
1938  // Check to see the compare/jump can be new value'ed.
1939  // This is done as a pass on its own. Don't need to check it here.
1940  return false;
1941}
1942
1943// Check to see if an instruction can be dot new
1944// There are three kinds.
1945// 1. dot new on predicate - V2/V3/V4
1946// 2. dot new on stores NV/ST - V4
1947// 3. dot new on jump NV/J - V4 -- This is generated in a pass.
1948bool HexagonPacketizerList::CanPromoteToDotNew( MachineInstr *MI,
1949                              SUnit *PacketSU, unsigned DepReg,
1950                              std::map <MachineInstr*, SUnit*> MIToSUnit,
1951                              MachineBasicBlock::iterator &MII,
1952                              const TargetRegisterClass* RC )
1953{
1954  const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
1955  // Already a dot new instruction.
1956  if (QII->isDotNewInst(MI) && !IsNewifyStore(MI))
1957    return false;
1958
1959  if (!isNewifiable(MI))
1960    return false;
1961
1962  // predicate .new
1963  if (RC == &Hexagon::PredRegsRegClass && isCondInst(MI))
1964      return true;
1965  else if (RC != &Hexagon::PredRegsRegClass &&
1966      !IsNewifyStore(MI)) // MI is not a new-value store
1967    return false;
1968  else {
1969    // Create a dot new machine instruction to see if resources can be
1970    // allocated. If not, bail out now.
1971    int NewOpcode = GetDotNewOp(MI->getOpcode());
1972    const MCInstrDesc &desc = QII->get(NewOpcode);
1973    DebugLoc dl;
1974    MachineInstr *NewMI =
1975                    MI->getParent()->getParent()->CreateMachineInstr(desc, dl);
1976    bool ResourcesAvailable = ResourceTracker->canReserveResources(NewMI);
1977    MI->getParent()->getParent()->DeleteMachineInstr(NewMI);
1978
1979    if (!ResourcesAvailable)
1980      return false;
1981
1982    // new value store only
1983    // new new value jump generated as a passes
1984    if (!CanPromoteToNewValue(MI, PacketSU, DepReg, MIToSUnit, MII)) {
1985      return false;
1986    }
1987  }
1988  return true;
1989}
1990
1991// Go through the packet instructions and search for anti dependency
1992// between them and DepReg from MI
1993// Consider this case:
1994// Trying to add
1995// a) %R1<def> = TFRI_cdNotPt %P3, 2
1996// to this packet:
1997// {
1998//   b) %P0<def> = OR_pp %P3<kill>, %P0<kill>
1999//   c) %P3<def> = TFR_PdRs %R23
2000//   d) %R1<def> = TFRI_cdnPt %P3, 4
2001//  }
2002// The P3 from a) and d) will be complements after
2003// a)'s P3 is converted to .new form
2004// Anti Dep between c) and b) is irrelevant for this case
2005bool HexagonPacketizerList::RestrictingDepExistInPacket (MachineInstr* MI,
2006      unsigned DepReg,
2007      std::map <MachineInstr*, SUnit*> MIToSUnit) {
2008
2009  const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
2010  SUnit* PacketSUDep = MIToSUnit[MI];
2011
2012  for (std::vector<MachineInstr*>::iterator VIN = CurrentPacketMIs.begin(),
2013       VEN = CurrentPacketMIs.end(); (VIN != VEN); ++VIN) {
2014
2015    // We only care for dependencies to predicated instructions
2016    if(!QII->isPredicated(*VIN)) continue;
2017
2018    // Scheduling Unit for current insn in the packet
2019    SUnit* PacketSU = MIToSUnit[*VIN];
2020
2021    // Look at dependencies between current members of the packet
2022    // and predicate defining instruction MI.
2023    // Make sure that dependency is on the exact register
2024    // we care about.
2025    if (PacketSU->isSucc(PacketSUDep)) {
2026      for (unsigned i = 0; i < PacketSU->Succs.size(); ++i) {
2027        if ((PacketSU->Succs[i].getSUnit() == PacketSUDep) &&
2028            (PacketSU->Succs[i].getKind() == SDep::Anti) &&
2029            (PacketSU->Succs[i].getReg() == DepReg)) {
2030          return true;
2031        }
2032      }
2033    }
2034  }
2035
2036  return false;
2037}
2038
2039
2040// Given two predicated instructions, this function detects whether
2041// the predicates are complements
2042bool HexagonPacketizerList::ArePredicatesComplements (MachineInstr* MI1,
2043     MachineInstr* MI2, std::map <MachineInstr*, SUnit*> MIToSUnit) {
2044
2045  const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
2046  // Currently can only reason about conditional transfers
2047  if (!QII->isConditionalTransfer(MI1) || !QII->isConditionalTransfer(MI2)) {
2048    return false;
2049  }
2050
2051  // Scheduling unit for candidate
2052  SUnit* SU = MIToSUnit[MI1];
2053
2054  // One corner case deals with the following scenario:
2055  // Trying to add
2056  // a) %R24<def> = TFR_cPt %P0, %R25
2057  // to this packet:
2058  //
2059  // {
2060  //   b) %R25<def> = TFR_cNotPt %P0, %R24
2061  //   c) %P0<def> = CMPEQri %R26, 1
2062  // }
2063  //
2064  // On general check a) and b) are complements, but
2065  // presence of c) will convert a) to .new form, and
2066  // then it is not a complement
2067  // We attempt to detect it by analyzing  existing
2068  // dependencies in the packet
2069
2070  // Analyze relationships between all existing members of the packet.
2071  // Look for Anti dependecy on the same predicate reg
2072  // as used in the candidate
2073  for (std::vector<MachineInstr*>::iterator VIN = CurrentPacketMIs.begin(),
2074       VEN = CurrentPacketMIs.end(); (VIN != VEN); ++VIN) {
2075
2076    // Scheduling Unit for current insn in the packet
2077    SUnit* PacketSU = MIToSUnit[*VIN];
2078
2079    // If this instruction in the packet is succeeded by the candidate...
2080    if (PacketSU->isSucc(SU)) {
2081      for (unsigned i = 0; i < PacketSU->Succs.size(); ++i) {
2082        // The corner case exist when there is true data
2083        // dependency between candidate and one of current
2084        // packet members, this dep is on predicate reg, and
2085        // there already exist anti dep on the same pred in
2086        // the packet.
2087        if (PacketSU->Succs[i].getSUnit() == SU &&
2088            Hexagon::PredRegsRegClass.contains(
2089              PacketSU->Succs[i].getReg()) &&
2090            PacketSU->Succs[i].getKind() == SDep::Data &&
2091            // Here I know that *VIN is predicate setting instruction
2092            // with true data dep to candidate on the register
2093            // we care about - c) in the above example.
2094            // Now I need to see if there is an anti dependency
2095            // from c) to any other instruction in the
2096            // same packet on the pred reg of interest
2097            RestrictingDepExistInPacket(*VIN,PacketSU->Succs[i].getReg(),
2098                                        MIToSUnit)) {
2099           return false;
2100        }
2101      }
2102    }
2103  }
2104
2105  // If the above case does not apply, check regular
2106  // complement condition.
2107  // Check that the predicate register is the same and
2108  // that the predicate sense is different
2109  // We also need to differentiate .old vs. .new:
2110  // !p0 is not complimentary to p0.new
2111  return ((MI1->getOperand(1).getReg() == MI2->getOperand(1).getReg()) &&
2112          (GetPredicateSense(MI1, QII) != GetPredicateSense(MI2, QII)) &&
2113          (QII->isDotNewInst(MI1) == QII->isDotNewInst(MI2)));
2114}
2115
2116// initPacketizerState - Initialize packetizer flags
2117void HexagonPacketizerList::initPacketizerState() {
2118
2119  Dependence = false;
2120  PromotedToDotNew = false;
2121  GlueToNewValueJump = false;
2122  GlueAllocframeStore = false;
2123  FoundSequentialDependence = false;
2124
2125  return;
2126}
2127
2128// ignorePseudoInstruction - Ignore bundling of pseudo instructions.
2129bool HexagonPacketizerList::ignorePseudoInstruction(MachineInstr *MI,
2130                                                    MachineBasicBlock *MBB) {
2131  if (MI->isDebugValue())
2132    return true;
2133
2134  // We must print out inline assembly
2135  if (MI->isInlineAsm())
2136    return false;
2137
2138  // We check if MI has any functional units mapped to it.
2139  // If it doesn't, we ignore the instruction.
2140  const MCInstrDesc& TID = MI->getDesc();
2141  unsigned SchedClass = TID.getSchedClass();
2142  const InstrStage* IS =
2143                    ResourceTracker->getInstrItins()->beginStage(SchedClass);
2144  unsigned FuncUnits = IS->getUnits();
2145  return !FuncUnits;
2146}
2147
2148// isSoloInstruction: - Returns true for instructions that must be
2149// scheduled in their own packet.
2150bool HexagonPacketizerList::isSoloInstruction(MachineInstr *MI) {
2151
2152  if (MI->isInlineAsm())
2153    return true;
2154
2155  if (MI->isEHLabel())
2156    return true;
2157
2158  // From Hexagon V4 Programmer's Reference Manual 3.4.4 Grouping constraints:
2159  // trap, pause, barrier, icinva, isync, and syncht are solo instructions.
2160  // They must not be grouped with other instructions in a packet.
2161  if (IsSchedBarrier(MI))
2162    return true;
2163
2164  return false;
2165}
2166
2167// isLegalToPacketizeTogether:
2168// SUI is the current instruction that is out side of the current packet.
2169// SUJ is the current instruction inside the current packet against which that
2170// SUI will be packetized.
2171bool HexagonPacketizerList::isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) {
2172  MachineInstr *I = SUI->getInstr();
2173  MachineInstr *J = SUJ->getInstr();
2174  assert(I && J && "Unable to packetize null instruction!");
2175
2176  const MCInstrDesc &MCIDI = I->getDesc();
2177  const MCInstrDesc &MCIDJ = J->getDesc();
2178
2179  MachineBasicBlock::iterator II = I;
2180
2181  const unsigned FrameSize = MF.getFrameInfo()->getStackSize();
2182  const HexagonRegisterInfo* QRI =
2183                      (const HexagonRegisterInfo *) TM.getRegisterInfo();
2184  const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
2185
2186  // Inline asm cannot go in the packet.
2187  if (I->getOpcode() == Hexagon::INLINEASM)
2188    llvm_unreachable("Should not meet inline asm here!");
2189
2190  if (isSoloInstruction(I))
2191    llvm_unreachable("Should not meet solo instr here!");
2192
2193  // A save callee-save register function call can only be in a packet
2194  // with instructions that don't write to the callee-save registers.
2195  if ((QII->isSaveCalleeSavedRegsCall(I) &&
2196       DoesModifyCalleeSavedReg(J, QRI)) ||
2197      (QII->isSaveCalleeSavedRegsCall(J) &&
2198       DoesModifyCalleeSavedReg(I, QRI))) {
2199    Dependence = true;
2200    return false;
2201  }
2202
2203  // Two control flow instructions cannot go in the same packet.
2204  if (IsControlFlow(I) && IsControlFlow(J)) {
2205    Dependence = true;
2206    return false;
2207  }
2208
2209  // A LoopN instruction cannot appear in the same packet as a jump or call.
2210  if (IsLoopN(I) && (   IsDirectJump(J)
2211                     || MCIDJ.isCall()
2212                     || QII->isDeallocRet(J))) {
2213    Dependence = true;
2214    return false;
2215  }
2216  if (IsLoopN(J) && (   IsDirectJump(I)
2217                     || MCIDI.isCall()
2218                     || QII->isDeallocRet(I))) {
2219    Dependence = true;
2220    return false;
2221  }
2222
2223  // dealloc_return cannot appear in the same packet as a conditional or
2224  // unconditional jump.
2225  if (QII->isDeallocRet(I) && (   MCIDJ.isBranch()
2226                               || MCIDJ.isCall()
2227                               || MCIDJ.isBarrier())) {
2228    Dependence = true;
2229    return false;
2230  }
2231
2232
2233  // V4 allows dual store. But does not allow second store, if the
2234  // first store is not in SLOT0. New value store, new value jump,
2235  // dealloc_return and memop always take SLOT0.
2236  // Arch spec 3.4.4.2
2237  if (QRI->Subtarget.hasV4TOps()) {
2238    if (MCIDI.mayStore() && MCIDJ.mayStore() &&
2239       (QII->isNewValueInst(J) || QII->isMemOp(J) || QII->isMemOp(I))) {
2240      Dependence = true;
2241      return false;
2242    }
2243
2244    if ((QII->isMemOp(J) && MCIDI.mayStore())
2245        || (MCIDJ.mayStore() && QII->isMemOp(I))
2246        || (QII->isMemOp(J) && QII->isMemOp(I))) {
2247      Dependence = true;
2248      return false;
2249    }
2250
2251    //if dealloc_return
2252    if (MCIDJ.mayStore() && QII->isDeallocRet(I)){
2253      Dependence = true;
2254      return false;
2255    }
2256
2257    // If an instruction feeds new value jump, glue it.
2258    MachineBasicBlock::iterator NextMII = I;
2259    ++NextMII;
2260    if (NextMII != I->getParent()->end() && QII->isNewValueJump(NextMII)) {
2261      MachineInstr *NextMI = NextMII;
2262
2263      bool secondRegMatch = false;
2264      bool maintainNewValueJump = false;
2265
2266      if (NextMI->getOperand(1).isReg() &&
2267          I->getOperand(0).getReg() == NextMI->getOperand(1).getReg()) {
2268        secondRegMatch = true;
2269        maintainNewValueJump = true;
2270      }
2271
2272      if (!secondRegMatch &&
2273           I->getOperand(0).getReg() == NextMI->getOperand(0).getReg()) {
2274        maintainNewValueJump = true;
2275      }
2276
2277      for (std::vector<MachineInstr*>::iterator
2278            VI = CurrentPacketMIs.begin(),
2279             VE = CurrentPacketMIs.end();
2280           (VI != VE && maintainNewValueJump); ++VI) {
2281        SUnit* PacketSU = MIToSUnit[*VI];
2282
2283        // NVJ can not be part of the dual jump - Arch Spec: section 7.8
2284        if (PacketSU->getInstr()->getDesc().isCall()) {
2285          Dependence = true;
2286          break;
2287        }
2288        // Validate
2289        // 1. Packet does not have a store in it.
2290        // 2. If the first operand of the nvj is newified, and the second
2291        //    operand is also a reg, it (second reg) is not defined in
2292        //    the same packet.
2293        // 3. If the second operand of the nvj is newified, (which means
2294        //    first operand is also a reg), first reg is not defined in
2295        //    the same packet.
2296        if (PacketSU->getInstr()->getDesc().mayStore()               ||
2297            PacketSU->getInstr()->getOpcode() == Hexagon::ALLOCFRAME ||
2298            // Check #2.
2299            (!secondRegMatch && NextMI->getOperand(1).isReg() &&
2300             PacketSU->getInstr()->modifiesRegister(
2301                               NextMI->getOperand(1).getReg(), QRI)) ||
2302            // Check #3.
2303            (secondRegMatch &&
2304             PacketSU->getInstr()->modifiesRegister(
2305                               NextMI->getOperand(0).getReg(), QRI))) {
2306          Dependence = true;
2307          break;
2308        }
2309      }
2310      if (!Dependence)
2311        GlueToNewValueJump = true;
2312      else
2313        return false;
2314    }
2315  }
2316
2317  if (SUJ->isSucc(SUI)) {
2318    for (unsigned i = 0;
2319         (i < SUJ->Succs.size()) && !FoundSequentialDependence;
2320         ++i) {
2321
2322      if (SUJ->Succs[i].getSUnit() != SUI) {
2323        continue;
2324      }
2325
2326      SDep::Kind DepType = SUJ->Succs[i].getKind();
2327
2328      // For direct calls:
2329      // Ignore register dependences for call instructions for
2330      // packetization purposes except for those due to r31 and
2331      // predicate registers.
2332      //
2333      // For indirect calls:
2334      // Same as direct calls + check for true dependences to the register
2335      // used in the indirect call.
2336      //
2337      // We completely ignore Order dependences for call instructions
2338      //
2339      // For returns:
2340      // Ignore register dependences for return instructions like jumpr,
2341      // dealloc return unless we have dependencies on the explicit uses
2342      // of the registers used by jumpr (like r31) or dealloc return
2343      // (like r29 or r30).
2344      //
2345      // TODO: Currently, jumpr is handling only return of r31. So, the
2346      // following logic (specificaly IsCallDependent) is working fine.
2347      // We need to enable jumpr for register other than r31 and then,
2348      // we need to rework the last part, where it handles indirect call
2349      // of that (IsCallDependent) function. Bug 6216 is opened for this.
2350      //
2351      unsigned DepReg = 0;
2352      const TargetRegisterClass* RC = NULL;
2353      if (DepType == SDep::Data) {
2354        DepReg = SUJ->Succs[i].getReg();
2355        RC = QRI->getMinimalPhysRegClass(DepReg);
2356      }
2357      if ((MCIDI.isCall() || MCIDI.isReturn()) &&
2358          (!IsRegDependence(DepType) ||
2359            !IsCallDependent(I, DepType, SUJ->Succs[i].getReg()))) {
2360        /* do nothing */
2361      }
2362
2363      // For instructions that can be promoted to dot-new, try to promote.
2364      else if ((DepType == SDep::Data) &&
2365               CanPromoteToDotNew(I, SUJ, DepReg, MIToSUnit, II, RC) &&
2366               PromoteToDotNew(I, DepType, II, RC)) {
2367        PromotedToDotNew = true;
2368        /* do nothing */
2369      }
2370
2371      else if ((DepType == SDep::Data) &&
2372               (QII->isNewValueJump(I))) {
2373        /* do nothing */
2374      }
2375
2376      // For predicated instructions, if the predicates are complements
2377      // then there can be no dependence.
2378      else if (QII->isPredicated(I) &&
2379               QII->isPredicated(J) &&
2380          ArePredicatesComplements(I, J, MIToSUnit)) {
2381        /* do nothing */
2382
2383      }
2384      else if (IsDirectJump(I) &&
2385               !MCIDJ.isBranch() &&
2386               !MCIDJ.isCall() &&
2387               (DepType == SDep::Order)) {
2388        // Ignore Order dependences between unconditional direct branches
2389        // and non-control-flow instructions
2390        /* do nothing */
2391      }
2392      else if (MCIDI.isConditionalBranch() && (DepType != SDep::Data) &&
2393               (DepType != SDep::Output)) {
2394        // Ignore all dependences for jumps except for true and output
2395        // dependences
2396        /* do nothing */
2397      }
2398
2399      // Ignore output dependences due to superregs. We can
2400      // write to two different subregisters of R1:0 for instance
2401      // in the same cycle
2402      //
2403
2404      //
2405      // Let the
2406      // If neither I nor J defines DepReg, then this is a
2407      // superfluous output dependence. The dependence must be of the
2408      // form:
2409      //  R0 = ...
2410      //  R1 = ...
2411      // and there is an output dependence between the two instructions
2412      // with
2413      // DepReg = D0
2414      // We want to ignore these dependences.
2415      // Ideally, the dependence constructor should annotate such
2416      // dependences. We can then avoid this relatively expensive check.
2417      //
2418      else if (DepType == SDep::Output) {
2419        // DepReg is the register that's responsible for the dependence.
2420        unsigned DepReg = SUJ->Succs[i].getReg();
2421
2422        // Check if I and J really defines DepReg.
2423        if (I->definesRegister(DepReg) ||
2424            J->definesRegister(DepReg)) {
2425          FoundSequentialDependence = true;
2426          break;
2427        }
2428      }
2429
2430      // We ignore Order dependences for
2431      // 1. Two loads unless they are volatile.
2432      // 2. Two stores in V4 unless they are volatile.
2433      else if ((DepType == SDep::Order) &&
2434               !I->hasOrderedMemoryRef() &&
2435               !J->hasOrderedMemoryRef()) {
2436        if (QRI->Subtarget.hasV4TOps() &&
2437            // hexagonv4 allows dual store.
2438            MCIDI.mayStore() && MCIDJ.mayStore()) {
2439          /* do nothing */
2440        }
2441        // store followed by store-- not OK on V2
2442        // store followed by load -- not OK on all (OK if addresses
2443        // are not aliased)
2444        // load followed by store -- OK on all
2445        // load followed by load  -- OK on all
2446        else if ( !MCIDJ.mayStore()) {
2447          /* do nothing */
2448        }
2449        else {
2450          FoundSequentialDependence = true;
2451          break;
2452        }
2453      }
2454
2455      // For V4, special case ALLOCFRAME. Even though there is dependency
2456      // between ALLOCAFRAME and subsequent store, allow it to be
2457      // packetized in a same packet. This implies that the store is using
2458      // caller's SP. Hense, offset needs to be updated accordingly.
2459      else if (DepType == SDep::Data
2460               && QRI->Subtarget.hasV4TOps()
2461               && J->getOpcode() == Hexagon::ALLOCFRAME
2462               && (I->getOpcode() == Hexagon::STrid
2463                   || I->getOpcode() == Hexagon::STriw
2464                   || I->getOpcode() == Hexagon::STrib)
2465               && I->getOperand(0).getReg() == QRI->getStackRegister()
2466               && QII->isValidOffset(I->getOpcode(),
2467                                     I->getOperand(1).getImm() -
2468                                     (FrameSize + HEXAGON_LRFP_SIZE)))
2469      {
2470        GlueAllocframeStore = true;
2471        // Since this store is to be glued with allocframe in the same
2472        // packet, it will use SP of the previous stack frame, i.e
2473        // caller's SP. Therefore, we need to recalculate offset according
2474        // to this change.
2475        I->getOperand(1).setImm(I->getOperand(1).getImm() -
2476                                        (FrameSize + HEXAGON_LRFP_SIZE));
2477      }
2478
2479      //
2480      // Skip over anti-dependences. Two instructions that are
2481      // anti-dependent can share a packet
2482      //
2483      else if (DepType != SDep::Anti) {
2484        FoundSequentialDependence = true;
2485        break;
2486      }
2487    }
2488
2489    if (FoundSequentialDependence) {
2490      Dependence = true;
2491      return false;
2492    }
2493  }
2494
2495  return true;
2496}
2497
2498// isLegalToPruneDependencies
2499bool HexagonPacketizerList::isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) {
2500  MachineInstr *I = SUI->getInstr();
2501  assert(I && SUJ->getInstr() && "Unable to packetize null instruction!");
2502
2503  const unsigned FrameSize = MF.getFrameInfo()->getStackSize();
2504
2505  if (Dependence) {
2506
2507    // Check if the instruction was promoted to a dot-new. If so, demote it
2508    // back into a dot-old.
2509    if (PromotedToDotNew) {
2510      DemoteToDotOld(I);
2511    }
2512
2513    // Check if the instruction (must be a store) was glued with an Allocframe
2514    // instruction. If so, restore its offset to its original value, i.e. use
2515    // curent SP instead of caller's SP.
2516    if (GlueAllocframeStore) {
2517      I->getOperand(1).setImm(I->getOperand(1).getImm() +
2518                                             FrameSize + HEXAGON_LRFP_SIZE);
2519    }
2520
2521    return false;
2522  }
2523  return true;
2524}
2525
2526MachineBasicBlock::iterator
2527HexagonPacketizerList::addToPacket(MachineInstr *MI) {
2528
2529    MachineBasicBlock::iterator MII = MI;
2530    MachineBasicBlock *MBB = MI->getParent();
2531
2532    const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
2533
2534    if (GlueToNewValueJump) {
2535
2536      ++MII;
2537      MachineInstr *nvjMI = MII;
2538      assert(ResourceTracker->canReserveResources(MI));
2539      ResourceTracker->reserveResources(MI);
2540      if ((QII->isExtended(MI) || QII->isConstExtended(MI)) &&
2541          !tryAllocateResourcesForConstExt(MI)) {
2542        endPacket(MBB, MI);
2543        ResourceTracker->reserveResources(MI);
2544        assert(canReserveResourcesForConstExt(MI) &&
2545               "Ensure that there is a slot");
2546        reserveResourcesForConstExt(MI);
2547        // Reserve resources for new value jump constant extender.
2548        assert(canReserveResourcesForConstExt(MI) &&
2549               "Ensure that there is a slot");
2550        reserveResourcesForConstExt(nvjMI);
2551        assert(ResourceTracker->canReserveResources(nvjMI) &&
2552               "Ensure that there is a slot");
2553
2554      } else if (   // Extended instruction takes two slots in the packet.
2555        // Try reserve and allocate 4-byte in the current packet first.
2556        (QII->isExtended(nvjMI)
2557            && (!tryAllocateResourcesForConstExt(nvjMI)
2558                || !ResourceTracker->canReserveResources(nvjMI)))
2559        || // For non-extended instruction, no need to allocate extra 4 bytes.
2560        (!QII->isExtended(nvjMI) &&
2561              !ResourceTracker->canReserveResources(nvjMI)))
2562      {
2563        endPacket(MBB, MI);
2564        // A new and empty packet starts.
2565        // We are sure that the resources requirements can be satisfied.
2566        // Therefore, do not need to call "canReserveResources" anymore.
2567        ResourceTracker->reserveResources(MI);
2568        if (QII->isExtended(nvjMI))
2569          reserveResourcesForConstExt(nvjMI);
2570      }
2571      // Here, we are sure that "reserveResources" would succeed.
2572      ResourceTracker->reserveResources(nvjMI);
2573      CurrentPacketMIs.push_back(MI);
2574      CurrentPacketMIs.push_back(nvjMI);
2575    } else {
2576      if (   (QII->isExtended(MI) || QII->isConstExtended(MI))
2577          && (   !tryAllocateResourcesForConstExt(MI)
2578              || !ResourceTracker->canReserveResources(MI)))
2579      {
2580        endPacket(MBB, MI);
2581        // Check if the instruction was promoted to a dot-new. If so, demote it
2582        // back into a dot-old
2583        if (PromotedToDotNew) {
2584          DemoteToDotOld(MI);
2585        }
2586        reserveResourcesForConstExt(MI);
2587      }
2588      // In case that "MI" is not an extended insn,
2589      // the resource availability has already been checked.
2590      ResourceTracker->reserveResources(MI);
2591      CurrentPacketMIs.push_back(MI);
2592    }
2593    return MII;
2594}
2595
2596//===----------------------------------------------------------------------===//
2597//                         Public Constructor Functions
2598//===----------------------------------------------------------------------===//
2599
2600FunctionPass *llvm::createHexagonPacketizer() {
2601  return new HexagonPacketizer();
2602}
2603
2604