MSP430ISelLowering.cpp revision 8725bd22bf91c29e2351a127295c19fea996e2c7 
1//===-- MSP430ISelLowering.cpp - MSP430 DAG Lowering Implementation  ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the MSP430TargetLowering class.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "msp430-lower"
15
16#include "MSP430ISelLowering.h"
17#include "MSP430.h"
18#include "MSP430TargetMachine.h"
19#include "MSP430Subtarget.h"
20#include "llvm/DerivedTypes.h"
21#include "llvm/Function.h"
22#include "llvm/Intrinsics.h"
23#include "llvm/CallingConv.h"
24#include "llvm/GlobalVariable.h"
25#include "llvm/GlobalAlias.h"
26#include "llvm/CodeGen/CallingConvLower.h"
27#include "llvm/CodeGen/MachineFrameInfo.h"
28#include "llvm/CodeGen/MachineFunction.h"
29#include "llvm/CodeGen/MachineInstrBuilder.h"
30#include "llvm/CodeGen/MachineRegisterInfo.h"
31#include "llvm/CodeGen/PseudoSourceValue.h"
32#include "llvm/CodeGen/SelectionDAGISel.h"
33#include "llvm/CodeGen/ValueTypes.h"
34#include "llvm/Support/Debug.h"
35#include "llvm/ADT/VectorExtras.h"
36using namespace llvm;
37
38MSP430TargetLowering::MSP430TargetLowering(MSP430TargetMachine &tm) :
39  TargetLowering(tm), Subtarget(*tm.getSubtargetImpl()), TM(tm) {
40
41  // Set up the register classes.
42  addRegisterClass(MVT::i8,  MSP430::GR8RegisterClass);
43  addRegisterClass(MVT::i16, MSP430::GR16RegisterClass);
44
45  // Compute derived properties from the register classes
46  computeRegisterProperties();
47
48  // Provide all sorts of operation actions
49
50  // Division is expensive
51  setIntDivIsCheap(false);
52
53  // Even if we have only 1 bit shift here, we can perform
54  // shifts of the whole bitwidth 1 bit per step.
55  setShiftAmountType(MVT::i8);
56
57  setStackPointerRegisterToSaveRestore(MSP430::SPW);
58  setBooleanContents(ZeroOrOneBooleanContent);
59  setSchedulingPreference(SchedulingForLatency);
60
61  setLoadExtAction(ISD::EXTLOAD,  MVT::i1, Promote);
62  setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
63  setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
64  setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
65  setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
66
67  // We don't have any truncstores
68  setTruncStoreAction(MVT::i16, MVT::i8, Expand);
69
70  setOperationAction(ISD::SRA,              MVT::i16,   Custom);
71  setOperationAction(ISD::SHL,              MVT::i16,   Custom);
72  setOperationAction(ISD::RET,              MVT::Other, Custom);
73  setOperationAction(ISD::GlobalAddress,    MVT::i16,   Custom);
74  setOperationAction(ISD::BR_CC,            MVT::Other, Expand);
75  setOperationAction(ISD::BRCOND,           MVT::Other, Custom);
76  setOperationAction(ISD::SETCC,            MVT::i8,    Custom);
77  setOperationAction(ISD::SETCC,            MVT::i16,   Custom);
78  setOperationAction(ISD::SELECT_CC,        MVT::Other, Expand);
79  setOperationAction(ISD::SELECT,           MVT::i8,    Custom);
80  setOperationAction(ISD::SELECT,           MVT::i16,   Custom);
81
82  // FIXME: Implement efficiently multiplication by a constant
83  setOperationAction(ISD::MUL,              MVT::i16,   Expand);
84  setOperationAction(ISD::MULHS,            MVT::i16,   Expand);
85  setOperationAction(ISD::MULHU,            MVT::i16,   Expand);
86  setOperationAction(ISD::SMUL_LOHI,        MVT::i16,   Expand);
87  setOperationAction(ISD::UMUL_LOHI,        MVT::i16,   Expand);
88}
89
90SDValue MSP430TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
91  switch (Op.getOpcode()) {
92  case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
93  case ISD::SHL: // FALLTHROUGH
94  case ISD::SRA:              return LowerShifts(Op, DAG);
95  case ISD::RET:              return LowerRET(Op, DAG);
96  case ISD::CALL:             return LowerCALL(Op, DAG);
97  case ISD::GlobalAddress:    return LowerGlobalAddress(Op, DAG);
98  case ISD::SETCC:            return LowerSETCC(Op, DAG);
99  case ISD::BRCOND:           return LowerBRCOND(Op, DAG);
100  case ISD::SELECT:           return LowerSELECT(Op, DAG);
101  default:
102    assert(0 && "unimplemented operand");
103    return SDValue();
104  }
105}
106
107//===----------------------------------------------------------------------===//
108//                      Calling Convention Implementation
109//===----------------------------------------------------------------------===//
110
111#include "MSP430GenCallingConv.inc"
112
113SDValue MSP430TargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op,
114                                                    SelectionDAG &DAG) {
115  unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
116  switch (CC) {
117  default:
118    assert(0 && "Unsupported calling convention");
119  case CallingConv::C:
120  case CallingConv::Fast:
121    return LowerCCCArguments(Op, DAG);
122  }
123}
124
125SDValue MSP430TargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
126  CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
127  unsigned CallingConv = TheCall->getCallingConv();
128  switch (CallingConv) {
129  default:
130    assert(0 && "Unsupported calling convention");
131  case CallingConv::Fast:
132  case CallingConv::C:
133    return LowerCCCCallTo(Op, DAG, CallingConv);
134  }
135}
136
137/// LowerCCCArguments - transform physical registers into virtual registers and
138/// generate load operations for arguments places on the stack.
139// FIXME: struct return stuff
140// FIXME: varargs
141SDValue MSP430TargetLowering::LowerCCCArguments(SDValue Op,
142                                                SelectionDAG &DAG) {
143  MachineFunction &MF = DAG.getMachineFunction();
144  MachineFrameInfo *MFI = MF.getFrameInfo();
145  MachineRegisterInfo &RegInfo = MF.getRegInfo();
146  SDValue Root = Op.getOperand(0);
147  bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
148  unsigned CC = MF.getFunction()->getCallingConv();
149  DebugLoc dl = Op.getDebugLoc();
150
151  // Assign locations to all of the incoming arguments.
152  SmallVector<CCValAssign, 16> ArgLocs;
153  CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
154  CCInfo.AnalyzeFormalArguments(Op.getNode(), CC_MSP430);
155
156  assert(!isVarArg && "Varargs not supported yet");
157
158  SmallVector<SDValue, 16> ArgValues;
159  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
160    CCValAssign &VA = ArgLocs[i];
161    if (VA.isRegLoc()) {
162      // Arguments passed in registers
163      MVT RegVT = VA.getLocVT();
164      switch (RegVT.getSimpleVT()) {
165      default:
166        cerr << "LowerFORMAL_ARGUMENTS Unhandled argument type: "
167             << RegVT.getSimpleVT()
168             << "\n";
169        abort();
170      case MVT::i16:
171        unsigned VReg =
172          RegInfo.createVirtualRegister(MSP430::GR16RegisterClass);
173        RegInfo.addLiveIn(VA.getLocReg(), VReg);
174        SDValue ArgValue = DAG.getCopyFromReg(Root, dl, VReg, RegVT);
175
176        // If this is an 8-bit value, it is really passed promoted to 16
177        // bits. Insert an assert[sz]ext to capture this, then truncate to the
178        // right size.
179        if (VA.getLocInfo() == CCValAssign::SExt)
180          ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
181                                 DAG.getValueType(VA.getValVT()));
182        else if (VA.getLocInfo() == CCValAssign::ZExt)
183          ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
184                                 DAG.getValueType(VA.getValVT()));
185
186        if (VA.getLocInfo() != CCValAssign::Full)
187          ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
188
189        ArgValues.push_back(ArgValue);
190      }
191    } else {
192      // Sanity check
193      assert(VA.isMemLoc());
194      // Load the argument to a virtual register
195      unsigned ObjSize = VA.getLocVT().getSizeInBits()/8;
196      if (ObjSize > 2) {
197        cerr << "LowerFORMAL_ARGUMENTS Unhandled argument type: "
198             << VA.getLocVT().getSimpleVT()
199             << "\n";
200      }
201      // Create the frame index object for this incoming parameter...
202      int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset());
203
204      // Create the SelectionDAG nodes corresponding to a load
205      //from this parameter
206      SDValue FIN = DAG.getFrameIndex(FI, MVT::i16);
207      ArgValues.push_back(DAG.getLoad(VA.getLocVT(), dl, Root, FIN,
208                                      PseudoSourceValue::getFixedStack(FI), 0));
209    }
210  }
211
212  ArgValues.push_back(Root);
213
214  // Return the new list of results.
215  return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(),
216                     &ArgValues[0], ArgValues.size()).getValue(Op.getResNo());
217}
218
219SDValue MSP430TargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) {
220  // CCValAssign - represent the assignment of the return value to a location
221  SmallVector<CCValAssign, 16> RVLocs;
222  unsigned CC   = DAG.getMachineFunction().getFunction()->getCallingConv();
223  bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
224  DebugLoc dl = Op.getDebugLoc();
225
226  // CCState - Info about the registers and stack slot.
227  CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
228
229  // Analize return values of ISD::RET
230  CCInfo.AnalyzeReturn(Op.getNode(), RetCC_MSP430);
231
232  // If this is the first return lowered for this function, add the regs to the
233  // liveout set for the function.
234  if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
235    for (unsigned i = 0; i != RVLocs.size(); ++i)
236      if (RVLocs[i].isRegLoc())
237        DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
238  }
239
240  // The chain is always operand #0
241  SDValue Chain = Op.getOperand(0);
242  SDValue Flag;
243
244  // Copy the result values into the output registers.
245  for (unsigned i = 0; i != RVLocs.size(); ++i) {
246    CCValAssign &VA = RVLocs[i];
247    assert(VA.isRegLoc() && "Can only return in registers!");
248
249    // ISD::RET => ret chain, (regnum1,val1), ...
250    // So i*2+1 index only the regnums
251    Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
252                             Op.getOperand(i*2+1), Flag);
253
254    // Guarantee that all emitted copies are stuck together,
255    // avoiding something bad.
256    Flag = Chain.getValue(1);
257  }
258
259  if (Flag.getNode())
260    return DAG.getNode(MSP430ISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
261
262  // Return Void
263  return DAG.getNode(MSP430ISD::RET_FLAG, dl, MVT::Other, Chain);
264}
265
266/// LowerCCCCallTo - functions arguments are copied from virtual regs to
267/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
268/// TODO: sret.
269SDValue MSP430TargetLowering::LowerCCCCallTo(SDValue Op, SelectionDAG &DAG,
270                                             unsigned CC) {
271  CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
272  SDValue Chain  = TheCall->getChain();
273  SDValue Callee = TheCall->getCallee();
274  bool isVarArg  = TheCall->isVarArg();
275  DebugLoc dl = Op.getDebugLoc();
276
277  // Analyze operands of the call, assigning locations to each operand.
278  SmallVector<CCValAssign, 16> ArgLocs;
279  CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
280
281  CCInfo.AnalyzeCallOperands(TheCall, CC_MSP430);
282
283  // Get a count of how many bytes are to be pushed on the stack.
284  unsigned NumBytes = CCInfo.getNextStackOffset();
285
286  Chain = DAG.getCALLSEQ_START(Chain ,DAG.getConstant(NumBytes,
287                                                      getPointerTy(), true));
288
289  SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
290  SmallVector<SDValue, 12> MemOpChains;
291  SDValue StackPtr;
292
293  // Walk the register/memloc assignments, inserting copies/loads.
294  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
295    CCValAssign &VA = ArgLocs[i];
296
297    // Arguments start after the 5 first operands of ISD::CALL
298    SDValue Arg = TheCall->getArg(i);
299
300    // Promote the value if needed.
301    switch (VA.getLocInfo()) {
302      default: assert(0 && "Unknown loc info!");
303      case CCValAssign::Full: break;
304      case CCValAssign::SExt:
305        Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
306        break;
307      case CCValAssign::ZExt:
308        Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
309        break;
310      case CCValAssign::AExt:
311        Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
312        break;
313    }
314
315    // Arguments that can be passed on register must be kept at RegsToPass
316    // vector
317    if (VA.isRegLoc()) {
318      RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
319    } else {
320      assert(VA.isMemLoc());
321
322      if (StackPtr.getNode() == 0)
323        StackPtr = DAG.getCopyFromReg(Chain, dl, MSP430::SPW, getPointerTy());
324
325      SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(),
326                                   StackPtr,
327                                   DAG.getIntPtrConstant(VA.getLocMemOffset()));
328
329
330      MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
331                                         PseudoSourceValue::getStack(),
332                                         VA.getLocMemOffset()));
333    }
334  }
335
336  // Transform all store nodes into one single node because all store nodes are
337  // independent of each other.
338  if (!MemOpChains.empty())
339    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
340                        &MemOpChains[0], MemOpChains.size());
341
342  // Build a sequence of copy-to-reg nodes chained together with token chain and
343  // flag operands which copy the outgoing args into registers.  The InFlag in
344  // necessary since all emited instructions must be stuck together.
345  SDValue InFlag;
346  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
347    Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
348                             RegsToPass[i].second, InFlag);
349    InFlag = Chain.getValue(1);
350  }
351
352  // If the callee is a GlobalAddress node (quite common, every direct call is)
353  // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
354  // Likewise ExternalSymbol -> TargetExternalSymbol.
355  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
356    Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i16);
357  else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
358    Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i16);
359
360  // Returns a chain & a flag for retval copy to use.
361  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
362  SmallVector<SDValue, 8> Ops;
363  Ops.push_back(Chain);
364  Ops.push_back(Callee);
365
366  // Add argument registers to the end of the list so that they are
367  // known live into the call.
368  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
369    Ops.push_back(DAG.getRegister(RegsToPass[i].first,
370                                  RegsToPass[i].second.getValueType()));
371
372  if (InFlag.getNode())
373    Ops.push_back(InFlag);
374
375  Chain = DAG.getNode(MSP430ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
376  InFlag = Chain.getValue(1);
377
378  // Create the CALLSEQ_END node.
379  Chain = DAG.getCALLSEQ_END(Chain,
380                             DAG.getConstant(NumBytes, getPointerTy(), true),
381                             DAG.getConstant(0, getPointerTy(), true),
382                             InFlag);
383  InFlag = Chain.getValue(1);
384
385  // Handle result values, copying them out of physregs into vregs that we
386  // return.
387  return SDValue(LowerCallResult(Chain, InFlag, TheCall, CC, DAG),
388                 Op.getResNo());
389}
390
391/// LowerCallResult - Lower the result values of an ISD::CALL into the
392/// appropriate copies out of appropriate physical registers.  This assumes that
393/// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
394/// being lowered. Returns a SDNode with the same number of values as the
395/// ISD::CALL.
396SDNode*
397MSP430TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
398                                      CallSDNode *TheCall,
399                                      unsigned CallingConv,
400                                      SelectionDAG &DAG) {
401  bool isVarArg = TheCall->isVarArg();
402  DebugLoc dl = TheCall->getDebugLoc();
403
404  // Assign locations to each value returned by this call.
405  SmallVector<CCValAssign, 16> RVLocs;
406  CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
407
408  CCInfo.AnalyzeCallResult(TheCall, RetCC_MSP430);
409  SmallVector<SDValue, 8> ResultVals;
410
411  // Copy all of the result registers out of their specified physreg.
412  for (unsigned i = 0; i != RVLocs.size(); ++i) {
413    Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
414                               RVLocs[i].getValVT(), InFlag).getValue(1);
415    InFlag = Chain.getValue(2);
416    ResultVals.push_back(Chain.getValue(0));
417  }
418
419  ResultVals.push_back(Chain);
420
421  // Merge everything together with a MERGE_VALUES node.
422  return DAG.getNode(ISD::MERGE_VALUES, dl, TheCall->getVTList(),
423                     &ResultVals[0], ResultVals.size()).getNode();
424}
425
426SDValue MSP430TargetLowering::LowerShifts(SDValue Op,
427                                          SelectionDAG &DAG) {
428  unsigned Opc = Op.getOpcode();
429  assert((Opc == ISD::SRA || ISD::SHL) &&
430         "Only SRA and SHL are currently supported.");
431  SDNode* N = Op.getNode();
432  MVT VT = Op.getValueType();
433  DebugLoc dl = N->getDebugLoc();
434
435  // We currently only lower shifts of constant argument.
436  if (!isa<ConstantSDNode>(N->getOperand(1)))
437    return SDValue();
438
439  uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
440
441  // Expand the stuff into sequence of shifts.
442  // FIXME: for some shift amounts this might be done better!
443  // E.g.: foo >> (8 + N) => sxt(swpb(foo)) >> N
444  SDValue Victim = N->getOperand(0);
445  while (ShiftAmount--)
446    Victim = DAG.getNode((Opc == ISD::SRA ? MSP430ISD::RRA : MSP430ISD::RLA),
447                         dl, VT, Victim);
448
449  return Victim;
450}
451
452SDValue MSP430TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) {
453  const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
454  int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
455
456  // Create the TargetGlobalAddress node, folding in the constant offset.
457  SDValue Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset);
458  return DAG.getNode(MSP430ISD::Wrapper, Op.getDebugLoc(),
459                     getPointerTy(), Result);
460}
461
462MVT MSP430TargetLowering::getSetCCResultType(MVT VT) const {
463  return MVT::i8;
464}
465
466SDValue MSP430TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) {
467  assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
468  SDValue LHS = Op.getOperand(0);
469  SDValue RHS = Op.getOperand(1);
470  DebugLoc dl = Op.getDebugLoc();
471  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
472
473  // FIXME: Handle bittests someday
474  assert(!LHS.getValueType().isFloatingPoint() && "We don't handle FP yet");
475
476  // FIXME: Handle jump negative someday
477  unsigned TargetCC = 0;
478  switch (CC) {
479  default: assert(0 && "Invalid integer condition!");
480  case ISD::SETEQ:
481    TargetCC = MSP430::COND_E;  // aka COND_Z
482    break;
483  case ISD::SETNE:
484    TargetCC = MSP430::COND_NE; // aka COND_NZ
485    break;
486  case ISD::SETULE:
487    std::swap(LHS, RHS);        // FALLTHROUGH
488  case ISD::SETUGE:
489    TargetCC = MSP430::COND_HS; // aka COND_C
490    break;
491  case ISD::SETUGT:
492    std::swap(LHS, RHS);        // FALLTHROUGH
493  case ISD::SETULT:
494    TargetCC = MSP430::COND_LO; // aka COND_NC
495    break;
496  case ISD::SETLE:
497    std::swap(LHS, RHS);        // FALLTHROUGH
498  case ISD::SETGE:
499    TargetCC = MSP430::COND_GE;
500    break;
501  case ISD::SETGT:
502    std::swap(LHS, RHS);        // FALLTHROUGH
503  case ISD::SETLT:
504    TargetCC = MSP430::COND_L;
505    break;
506  }
507
508  SDValue Cond = DAG.getNode(MSP430ISD::CMP, dl, MVT::i16, LHS, RHS);
509  return DAG.getNode(MSP430ISD::SETCC, dl, MVT::i8,
510                     DAG.getConstant(TargetCC, MVT::i8), Cond);
511}
512
513SDValue MSP430TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) {
514  SDValue Chain = Op.getOperand(0);
515  SDValue Cond  = Op.getOperand(1);
516  SDValue Dest  = Op.getOperand(2);
517  DebugLoc dl = Op.getDebugLoc();
518  SDValue CC;
519
520  // Lower condition if not lowered yet
521  if (Cond.getOpcode() == ISD::SETCC)
522    Cond = LowerSETCC(Cond, DAG);
523
524  // If condition flag is set by a MSP430ISD::CMP, then use it as the condition
525  // setting operand in place of the MSP430ISD::SETCC.
526  if (Cond.getOpcode() == MSP430ISD::SETCC) {
527    CC = Cond.getOperand(0);
528    Cond = Cond.getOperand(1);
529  } else
530    assert(0 && "Unimplemented condition!");
531
532  return DAG.getNode(MSP430ISD::BRCOND, dl, Op.getValueType(),
533                     Chain, Dest, CC, Cond);
534}
535
536SDValue MSP430TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) {
537  SDValue Cond   = Op.getOperand(0);
538  SDValue TrueV  = Op.getOperand(1);
539  SDValue FalseV = Op.getOperand(2);
540  DebugLoc dl    = Op.getDebugLoc();
541  SDValue CC;
542
543  // Lower condition if not lowered yet
544  if (Cond.getOpcode() == ISD::SETCC)
545    Cond = LowerSETCC(Cond, DAG);
546
547  // If condition flag is set by a MSP430ISD::CMP, then use it as the condition
548  // setting operand in place of the MSP430ISD::SETCC.
549  if (Cond.getOpcode() == MSP430ISD::SETCC) {
550    CC = Cond.getOperand(0);
551    Cond = Cond.getOperand(1);
552    TrueV = Cond.getOperand(0);
553    FalseV = Cond.getOperand(1);
554  } else {
555    CC = DAG.getConstant(MSP430::COND_NE, MVT::i16);
556    Cond = DAG.getNode(MSP430ISD::CMP, dl, MVT::i16,
557                       Cond, DAG.getConstant(0, MVT::i16));
558  }
559
560  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
561  SmallVector<SDValue, 4> Ops;
562  Ops.push_back(TrueV);
563  Ops.push_back(FalseV);
564  Ops.push_back(CC);
565  Ops.push_back(Cond);
566
567  return DAG.getNode(MSP430ISD::SELECT, dl, VTs, &Ops[0], Ops.size());
568}
569
570const char *MSP430TargetLowering::getTargetNodeName(unsigned Opcode) const {
571  switch (Opcode) {
572  default: return NULL;
573  case MSP430ISD::RET_FLAG:           return "MSP430ISD::RET_FLAG";
574  case MSP430ISD::RRA:                return "MSP430ISD::RRA";
575  case MSP430ISD::RLA:                return "MSP430ISD::RRA";
576  case MSP430ISD::CALL:               return "MSP430ISD::CALL";
577  case MSP430ISD::Wrapper:            return "MSP430ISD::Wrapper";
578  case MSP430ISD::BRCOND:             return "MSP430ISD::BRCOND";
579  case MSP430ISD::CMP:                return "MSP430ISD::CMP";
580  case MSP430ISD::SETCC:              return "MSP430ISD::SETCC";
581  case MSP430ISD::SELECT:             return "MSP430ISD::SELECT";
582  }
583}
584
585//===----------------------------------------------------------------------===//
586//  Other Lowering Code
587//===----------------------------------------------------------------------===//
588
589MachineBasicBlock*
590MSP430TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
591                                                  MachineBasicBlock *BB) const {
592  const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
593  DebugLoc dl = MI->getDebugLoc();
594  assert((MI->getOpcode() == MSP430::Select16) &&
595         "Unexpected instr type to insert");
596
597  // To "insert" a SELECT instruction, we actually have to insert the diamond
598  // control-flow pattern.  The incoming instruction knows the destination vreg
599  // to set, the condition code register to branch on, the true/false values to
600  // select between, and a branch opcode to use.
601  const BasicBlock *LLVM_BB = BB->getBasicBlock();
602  MachineFunction::iterator I = BB;
603  ++I;
604
605  //  thisMBB:
606  //  ...
607  //   TrueVal = ...
608  //   cmpTY ccX, r1, r2
609  //   jCC copy1MBB
610  //   fallthrough --> copy0MBB
611  MachineBasicBlock *thisMBB = BB;
612  MachineFunction *F = BB->getParent();
613  MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
614  MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);
615  BuildMI(BB, dl, TII.get(MSP430::JCC))
616    .addMBB(copy1MBB)
617    .addImm(MI->getOperand(3).getImm());
618  F->insert(I, copy0MBB);
619  F->insert(I, copy1MBB);
620  // Update machine-CFG edges by transferring all successors of the current
621  // block to the new block which will contain the Phi node for the select.
622  copy1MBB->transferSuccessors(BB);
623  // Next, add the true and fallthrough blocks as its successors.
624  BB->addSuccessor(copy0MBB);
625  BB->addSuccessor(copy1MBB);
626
627  //  copy0MBB:
628  //   %FalseValue = ...
629  //   # fallthrough to copy1MBB
630  BB = copy0MBB;
631
632  // Update machine-CFG edges
633  BB->addSuccessor(copy1MBB);
634
635  //  copy1MBB:
636  //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
637  //  ...
638  BB = copy1MBB;
639  BuildMI(BB, dl, TII.get(MSP430::PHI),
640          MI->getOperand(0).getReg())
641    .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
642    .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
643
644  F->DeleteMachineInstr(MI);   // The pseudo instruction is gone now.
645  return BB;
646}
647