MSP430ISelLowering.cpp revision 90f20044ade3712c8b0c3f4ebe47d57ad15ae6ce
1//===-- MSP430ISelLowering.cpp - MSP430 DAG Lowering Implementation ------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the MSP430TargetLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "msp430-lower" 15 16#include "MSP430ISelLowering.h" 17#include "MSP430.h" 18#include "MSP430MachineFunctionInfo.h" 19#include "MSP430TargetMachine.h" 20#include "MSP430Subtarget.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/Function.h" 23#include "llvm/Intrinsics.h" 24#include "llvm/CallingConv.h" 25#include "llvm/GlobalVariable.h" 26#include "llvm/GlobalAlias.h" 27#include "llvm/CodeGen/CallingConvLower.h" 28#include "llvm/CodeGen/MachineFrameInfo.h" 29#include "llvm/CodeGen/MachineFunction.h" 30#include "llvm/CodeGen/MachineInstrBuilder.h" 31#include "llvm/CodeGen/MachineRegisterInfo.h" 32#include "llvm/CodeGen/SelectionDAGISel.h" 33#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" 34#include "llvm/CodeGen/ValueTypes.h" 35#include "llvm/Support/CommandLine.h" 36#include "llvm/Support/Debug.h" 37#include "llvm/Support/ErrorHandling.h" 38#include "llvm/Support/raw_ostream.h" 39using namespace llvm; 40 41typedef enum { 42 NoHWMult, 43 HWMultIntr, 44 HWMultNoIntr 45} HWMultUseMode; 46 47static cl::opt<HWMultUseMode> 48HWMultMode("msp430-hwmult-mode", 49 cl::desc("Hardware multiplier use mode"), 50 cl::init(HWMultNoIntr), 51 cl::values( 52 clEnumValN(NoHWMult, "no", 53 "Do not use hardware multiplier"), 54 clEnumValN(HWMultIntr, "interrupts", 55 "Assume hardware multiplier can be used inside interrupts"), 56 clEnumValN(HWMultNoIntr, "use", 57 "Assume hardware multiplier cannot be used inside interrupts"), 58 clEnumValEnd)); 59 60MSP430TargetLowering::MSP430TargetLowering(MSP430TargetMachine &tm) : 61 TargetLowering(tm, new TargetLoweringObjectFileELF()), 62 Subtarget(*tm.getSubtargetImpl()), TM(tm) { 63 64 TD = getTargetData(); 65 66 // Set up the register classes. 67 addRegisterClass(MVT::i8, MSP430::GR8RegisterClass); 68 addRegisterClass(MVT::i16, MSP430::GR16RegisterClass); 69 70 // Compute derived properties from the register classes 71 computeRegisterProperties(); 72 73 // Provide all sorts of operation actions 74 75 // Division is expensive 76 setIntDivIsCheap(false); 77 78 setStackPointerRegisterToSaveRestore(MSP430::SPW); 79 setBooleanContents(ZeroOrOneBooleanContent); 80 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct? 81 82 // We have post-incremented loads / stores. 83 setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal); 84 setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal); 85 86 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); 87 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 88 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); 89 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand); 90 setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand); 91 92 // We don't have any truncstores 93 setTruncStoreAction(MVT::i16, MVT::i8, Expand); 94 95 setOperationAction(ISD::SRA, MVT::i8, Custom); 96 setOperationAction(ISD::SHL, MVT::i8, Custom); 97 setOperationAction(ISD::SRL, MVT::i8, Custom); 98 setOperationAction(ISD::SRA, MVT::i16, Custom); 99 setOperationAction(ISD::SHL, MVT::i16, Custom); 100 setOperationAction(ISD::SRL, MVT::i16, Custom); 101 setOperationAction(ISD::ROTL, MVT::i8, Expand); 102 setOperationAction(ISD::ROTR, MVT::i8, Expand); 103 setOperationAction(ISD::ROTL, MVT::i16, Expand); 104 setOperationAction(ISD::ROTR, MVT::i16, Expand); 105 setOperationAction(ISD::GlobalAddress, MVT::i16, Custom); 106 setOperationAction(ISD::ExternalSymbol, MVT::i16, Custom); 107 setOperationAction(ISD::BlockAddress, MVT::i16, Custom); 108 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 109 setOperationAction(ISD::BR_CC, MVT::i8, Custom); 110 setOperationAction(ISD::BR_CC, MVT::i16, Custom); 111 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 112 setOperationAction(ISD::SETCC, MVT::i8, Custom); 113 setOperationAction(ISD::SETCC, MVT::i16, Custom); 114 setOperationAction(ISD::SELECT, MVT::i8, Expand); 115 setOperationAction(ISD::SELECT, MVT::i16, Expand); 116 setOperationAction(ISD::SELECT_CC, MVT::i8, Custom); 117 setOperationAction(ISD::SELECT_CC, MVT::i16, Custom); 118 setOperationAction(ISD::SIGN_EXTEND, MVT::i16, Custom); 119 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i8, Expand); 120 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i16, Expand); 121 122 setOperationAction(ISD::CTTZ, MVT::i8, Expand); 123 setOperationAction(ISD::CTTZ, MVT::i16, Expand); 124 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i8, Expand); 125 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16, Expand); 126 setOperationAction(ISD::CTLZ, MVT::i8, Expand); 127 setOperationAction(ISD::CTLZ, MVT::i16, Expand); 128 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8, Expand); 129 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16, Expand); 130 setOperationAction(ISD::CTPOP, MVT::i8, Expand); 131 setOperationAction(ISD::CTPOP, MVT::i16, Expand); 132 133 setOperationAction(ISD::SHL_PARTS, MVT::i8, Expand); 134 setOperationAction(ISD::SHL_PARTS, MVT::i16, Expand); 135 setOperationAction(ISD::SRL_PARTS, MVT::i8, Expand); 136 setOperationAction(ISD::SRL_PARTS, MVT::i16, Expand); 137 setOperationAction(ISD::SRA_PARTS, MVT::i8, Expand); 138 setOperationAction(ISD::SRA_PARTS, MVT::i16, Expand); 139 140 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 141 142 // FIXME: Implement efficiently multiplication by a constant 143 setOperationAction(ISD::MUL, MVT::i8, Expand); 144 setOperationAction(ISD::MULHS, MVT::i8, Expand); 145 setOperationAction(ISD::MULHU, MVT::i8, Expand); 146 setOperationAction(ISD::SMUL_LOHI, MVT::i8, Expand); 147 setOperationAction(ISD::UMUL_LOHI, MVT::i8, Expand); 148 setOperationAction(ISD::MUL, MVT::i16, Expand); 149 setOperationAction(ISD::MULHS, MVT::i16, Expand); 150 setOperationAction(ISD::MULHU, MVT::i16, Expand); 151 setOperationAction(ISD::SMUL_LOHI, MVT::i16, Expand); 152 setOperationAction(ISD::UMUL_LOHI, MVT::i16, Expand); 153 154 setOperationAction(ISD::UDIV, MVT::i8, Expand); 155 setOperationAction(ISD::UDIVREM, MVT::i8, Expand); 156 setOperationAction(ISD::UREM, MVT::i8, Expand); 157 setOperationAction(ISD::SDIV, MVT::i8, Expand); 158 setOperationAction(ISD::SDIVREM, MVT::i8, Expand); 159 setOperationAction(ISD::SREM, MVT::i8, Expand); 160 setOperationAction(ISD::UDIV, MVT::i16, Expand); 161 setOperationAction(ISD::UDIVREM, MVT::i16, Expand); 162 setOperationAction(ISD::UREM, MVT::i16, Expand); 163 setOperationAction(ISD::SDIV, MVT::i16, Expand); 164 setOperationAction(ISD::SDIVREM, MVT::i16, Expand); 165 setOperationAction(ISD::SREM, MVT::i16, Expand); 166 167 // Libcalls names. 168 if (HWMultMode == HWMultIntr) { 169 setLibcallName(RTLIB::MUL_I8, "__mulqi3hw"); 170 setLibcallName(RTLIB::MUL_I16, "__mulhi3hw"); 171 } else if (HWMultMode == HWMultNoIntr) { 172 setLibcallName(RTLIB::MUL_I8, "__mulqi3hw_noint"); 173 setLibcallName(RTLIB::MUL_I16, "__mulhi3hw_noint"); 174 } 175 176 setMinFunctionAlignment(1); 177 setPrefFunctionAlignment(2); 178} 179 180SDValue MSP430TargetLowering::LowerOperation(SDValue Op, 181 SelectionDAG &DAG) const { 182 switch (Op.getOpcode()) { 183 case ISD::SHL: // FALLTHROUGH 184 case ISD::SRL: 185 case ISD::SRA: return LowerShifts(Op, DAG); 186 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 187 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 188 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG); 189 case ISD::SETCC: return LowerSETCC(Op, DAG); 190 case ISD::BR_CC: return LowerBR_CC(Op, DAG); 191 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 192 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, DAG); 193 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 194 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 195 default: 196 llvm_unreachable("unimplemented operand"); 197 } 198} 199 200//===----------------------------------------------------------------------===// 201// MSP430 Inline Assembly Support 202//===----------------------------------------------------------------------===// 203 204/// getConstraintType - Given a constraint letter, return the type of 205/// constraint it is for this target. 206TargetLowering::ConstraintType 207MSP430TargetLowering::getConstraintType(const std::string &Constraint) const { 208 if (Constraint.size() == 1) { 209 switch (Constraint[0]) { 210 case 'r': 211 return C_RegisterClass; 212 default: 213 break; 214 } 215 } 216 return TargetLowering::getConstraintType(Constraint); 217} 218 219std::pair<unsigned, const TargetRegisterClass*> 220MSP430TargetLowering:: 221getRegForInlineAsmConstraint(const std::string &Constraint, 222 EVT VT) const { 223 if (Constraint.size() == 1) { 224 // GCC Constraint Letters 225 switch (Constraint[0]) { 226 default: break; 227 case 'r': // GENERAL_REGS 228 if (VT == MVT::i8) 229 return std::make_pair(0U, MSP430::GR8RegisterClass); 230 231 return std::make_pair(0U, MSP430::GR16RegisterClass); 232 } 233 } 234 235 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 236} 237 238//===----------------------------------------------------------------------===// 239// Calling Convention Implementation 240//===----------------------------------------------------------------------===// 241 242#include "MSP430GenCallingConv.inc" 243 244SDValue 245MSP430TargetLowering::LowerFormalArguments(SDValue Chain, 246 CallingConv::ID CallConv, 247 bool isVarArg, 248 const SmallVectorImpl<ISD::InputArg> 249 &Ins, 250 DebugLoc dl, 251 SelectionDAG &DAG, 252 SmallVectorImpl<SDValue> &InVals) 253 const { 254 255 switch (CallConv) { 256 default: 257 llvm_unreachable("Unsupported calling convention"); 258 case CallingConv::C: 259 case CallingConv::Fast: 260 return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals); 261 case CallingConv::MSP430_INTR: 262 if (Ins.empty()) 263 return Chain; 264 report_fatal_error("ISRs cannot have arguments"); 265 } 266} 267 268SDValue 269MSP430TargetLowering::LowerCall(SDValue Chain, SDValue Callee, 270 CallingConv::ID CallConv, bool isVarArg, 271 bool &isTailCall, 272 const SmallVectorImpl<ISD::OutputArg> &Outs, 273 const SmallVectorImpl<SDValue> &OutVals, 274 const SmallVectorImpl<ISD::InputArg> &Ins, 275 DebugLoc dl, SelectionDAG &DAG, 276 SmallVectorImpl<SDValue> &InVals) const { 277 // MSP430 target does not yet support tail call optimization. 278 isTailCall = false; 279 280 switch (CallConv) { 281 default: 282 llvm_unreachable("Unsupported calling convention"); 283 case CallingConv::Fast: 284 case CallingConv::C: 285 return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall, 286 Outs, OutVals, Ins, dl, DAG, InVals); 287 case CallingConv::MSP430_INTR: 288 report_fatal_error("ISRs cannot be called directly"); 289 } 290} 291 292/// LowerCCCArguments - transform physical registers into virtual registers and 293/// generate load operations for arguments places on the stack. 294// FIXME: struct return stuff 295// FIXME: varargs 296SDValue 297MSP430TargetLowering::LowerCCCArguments(SDValue Chain, 298 CallingConv::ID CallConv, 299 bool isVarArg, 300 const SmallVectorImpl<ISD::InputArg> 301 &Ins, 302 DebugLoc dl, 303 SelectionDAG &DAG, 304 SmallVectorImpl<SDValue> &InVals) 305 const { 306 MachineFunction &MF = DAG.getMachineFunction(); 307 MachineFrameInfo *MFI = MF.getFrameInfo(); 308 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 309 310 // Assign locations to all of the incoming arguments. 311 SmallVector<CCValAssign, 16> ArgLocs; 312 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 313 getTargetMachine(), ArgLocs, *DAG.getContext()); 314 CCInfo.AnalyzeFormalArguments(Ins, CC_MSP430); 315 316 assert(!isVarArg && "Varargs not supported yet"); 317 318 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 319 CCValAssign &VA = ArgLocs[i]; 320 if (VA.isRegLoc()) { 321 // Arguments passed in registers 322 EVT RegVT = VA.getLocVT(); 323 switch (RegVT.getSimpleVT().SimpleTy) { 324 default: 325 { 326#ifndef NDEBUG 327 errs() << "LowerFormalArguments Unhandled argument type: " 328 << RegVT.getSimpleVT().SimpleTy << "\n"; 329#endif 330 llvm_unreachable(0); 331 } 332 case MVT::i16: 333 unsigned VReg = 334 RegInfo.createVirtualRegister(MSP430::GR16RegisterClass); 335 RegInfo.addLiveIn(VA.getLocReg(), VReg); 336 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT); 337 338 // If this is an 8-bit value, it is really passed promoted to 16 339 // bits. Insert an assert[sz]ext to capture this, then truncate to the 340 // right size. 341 if (VA.getLocInfo() == CCValAssign::SExt) 342 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, 343 DAG.getValueType(VA.getValVT())); 344 else if (VA.getLocInfo() == CCValAssign::ZExt) 345 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, 346 DAG.getValueType(VA.getValVT())); 347 348 if (VA.getLocInfo() != CCValAssign::Full) 349 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 350 351 InVals.push_back(ArgValue); 352 } 353 } else { 354 // Sanity check 355 assert(VA.isMemLoc()); 356 // Load the argument to a virtual register 357 unsigned ObjSize = VA.getLocVT().getSizeInBits()/8; 358 if (ObjSize > 2) { 359 errs() << "LowerFormalArguments Unhandled argument type: " 360 << EVT(VA.getLocVT()).getEVTString() 361 << "\n"; 362 } 363 // Create the frame index object for this incoming parameter... 364 int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset(), true); 365 366 // Create the SelectionDAG nodes corresponding to a load 367 //from this parameter 368 SDValue FIN = DAG.getFrameIndex(FI, MVT::i16); 369 InVals.push_back(DAG.getLoad(VA.getLocVT(), dl, Chain, FIN, 370 MachinePointerInfo::getFixedStack(FI), 371 false, false, false, 0)); 372 } 373 } 374 375 return Chain; 376} 377 378SDValue 379MSP430TargetLowering::LowerReturn(SDValue Chain, 380 CallingConv::ID CallConv, bool isVarArg, 381 const SmallVectorImpl<ISD::OutputArg> &Outs, 382 const SmallVectorImpl<SDValue> &OutVals, 383 DebugLoc dl, SelectionDAG &DAG) const { 384 385 // CCValAssign - represent the assignment of the return value to a location 386 SmallVector<CCValAssign, 16> RVLocs; 387 388 // ISRs cannot return any value. 389 if (CallConv == CallingConv::MSP430_INTR && !Outs.empty()) 390 report_fatal_error("ISRs cannot return any value"); 391 392 // CCState - Info about the registers and stack slot. 393 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 394 getTargetMachine(), RVLocs, *DAG.getContext()); 395 396 // Analize return values. 397 CCInfo.AnalyzeReturn(Outs, RetCC_MSP430); 398 399 // If this is the first return lowered for this function, add the regs to the 400 // liveout set for the function. 401 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 402 for (unsigned i = 0; i != RVLocs.size(); ++i) 403 if (RVLocs[i].isRegLoc()) 404 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 405 } 406 407 SDValue Flag; 408 409 // Copy the result values into the output registers. 410 for (unsigned i = 0; i != RVLocs.size(); ++i) { 411 CCValAssign &VA = RVLocs[i]; 412 assert(VA.isRegLoc() && "Can only return in registers!"); 413 414 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), 415 OutVals[i], Flag); 416 417 // Guarantee that all emitted copies are stuck together, 418 // avoiding something bad. 419 Flag = Chain.getValue(1); 420 } 421 422 unsigned Opc = (CallConv == CallingConv::MSP430_INTR ? 423 MSP430ISD::RETI_FLAG : MSP430ISD::RET_FLAG); 424 425 if (Flag.getNode()) 426 return DAG.getNode(Opc, dl, MVT::Other, Chain, Flag); 427 428 // Return Void 429 return DAG.getNode(Opc, dl, MVT::Other, Chain); 430} 431 432/// LowerCCCCallTo - functions arguments are copied from virtual regs to 433/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted. 434/// TODO: sret. 435SDValue 436MSP430TargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee, 437 CallingConv::ID CallConv, bool isVarArg, 438 bool isTailCall, 439 const SmallVectorImpl<ISD::OutputArg> 440 &Outs, 441 const SmallVectorImpl<SDValue> &OutVals, 442 const SmallVectorImpl<ISD::InputArg> &Ins, 443 DebugLoc dl, SelectionDAG &DAG, 444 SmallVectorImpl<SDValue> &InVals) const { 445 // Analyze operands of the call, assigning locations to each operand. 446 SmallVector<CCValAssign, 16> ArgLocs; 447 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 448 getTargetMachine(), ArgLocs, *DAG.getContext()); 449 450 CCInfo.AnalyzeCallOperands(Outs, CC_MSP430); 451 452 // Get a count of how many bytes are to be pushed on the stack. 453 unsigned NumBytes = CCInfo.getNextStackOffset(); 454 455 Chain = DAG.getCALLSEQ_START(Chain ,DAG.getConstant(NumBytes, 456 getPointerTy(), true)); 457 458 SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass; 459 SmallVector<SDValue, 12> MemOpChains; 460 SDValue StackPtr; 461 462 // Walk the register/memloc assignments, inserting copies/loads. 463 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 464 CCValAssign &VA = ArgLocs[i]; 465 466 SDValue Arg = OutVals[i]; 467 468 // Promote the value if needed. 469 switch (VA.getLocInfo()) { 470 default: llvm_unreachable("Unknown loc info!"); 471 case CCValAssign::Full: break; 472 case CCValAssign::SExt: 473 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); 474 break; 475 case CCValAssign::ZExt: 476 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); 477 break; 478 case CCValAssign::AExt: 479 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); 480 break; 481 } 482 483 // Arguments that can be passed on register must be kept at RegsToPass 484 // vector 485 if (VA.isRegLoc()) { 486 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 487 } else { 488 assert(VA.isMemLoc()); 489 490 if (StackPtr.getNode() == 0) 491 StackPtr = DAG.getCopyFromReg(Chain, dl, MSP430::SPW, getPointerTy()); 492 493 SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), 494 StackPtr, 495 DAG.getIntPtrConstant(VA.getLocMemOffset())); 496 497 498 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 499 MachinePointerInfo(),false, false, 0)); 500 } 501 } 502 503 // Transform all store nodes into one single node because all store nodes are 504 // independent of each other. 505 if (!MemOpChains.empty()) 506 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 507 &MemOpChains[0], MemOpChains.size()); 508 509 // Build a sequence of copy-to-reg nodes chained together with token chain and 510 // flag operands which copy the outgoing args into registers. The InFlag in 511 // necessary since all emitted instructions must be stuck together. 512 SDValue InFlag; 513 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 514 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 515 RegsToPass[i].second, InFlag); 516 InFlag = Chain.getValue(1); 517 } 518 519 // If the callee is a GlobalAddress node (quite common, every direct call is) 520 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 521 // Likewise ExternalSymbol -> TargetExternalSymbol. 522 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 523 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i16); 524 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) 525 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i16); 526 527 // Returns a chain & a flag for retval copy to use. 528 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 529 SmallVector<SDValue, 8> Ops; 530 Ops.push_back(Chain); 531 Ops.push_back(Callee); 532 533 // Add argument registers to the end of the list so that they are 534 // known live into the call. 535 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 536 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 537 RegsToPass[i].second.getValueType())); 538 539 if (InFlag.getNode()) 540 Ops.push_back(InFlag); 541 542 Chain = DAG.getNode(MSP430ISD::CALL, dl, NodeTys, &Ops[0], Ops.size()); 543 InFlag = Chain.getValue(1); 544 545 // Create the CALLSEQ_END node. 546 Chain = DAG.getCALLSEQ_END(Chain, 547 DAG.getConstant(NumBytes, getPointerTy(), true), 548 DAG.getConstant(0, getPointerTy(), true), 549 InFlag); 550 InFlag = Chain.getValue(1); 551 552 // Handle result values, copying them out of physregs into vregs that we 553 // return. 554 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, 555 DAG, InVals); 556} 557 558/// LowerCallResult - Lower the result values of a call into the 559/// appropriate copies out of appropriate physical registers. 560/// 561SDValue 562MSP430TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 563 CallingConv::ID CallConv, bool isVarArg, 564 const SmallVectorImpl<ISD::InputArg> &Ins, 565 DebugLoc dl, SelectionDAG &DAG, 566 SmallVectorImpl<SDValue> &InVals) const { 567 568 // Assign locations to each value returned by this call. 569 SmallVector<CCValAssign, 16> RVLocs; 570 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 571 getTargetMachine(), RVLocs, *DAG.getContext()); 572 573 CCInfo.AnalyzeCallResult(Ins, RetCC_MSP430); 574 575 // Copy all of the result registers out of their specified physreg. 576 for (unsigned i = 0; i != RVLocs.size(); ++i) { 577 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), 578 RVLocs[i].getValVT(), InFlag).getValue(1); 579 InFlag = Chain.getValue(2); 580 InVals.push_back(Chain.getValue(0)); 581 } 582 583 return Chain; 584} 585 586SDValue MSP430TargetLowering::LowerShifts(SDValue Op, 587 SelectionDAG &DAG) const { 588 unsigned Opc = Op.getOpcode(); 589 SDNode* N = Op.getNode(); 590 EVT VT = Op.getValueType(); 591 DebugLoc dl = N->getDebugLoc(); 592 593 // Expand non-constant shifts to loops: 594 if (!isa<ConstantSDNode>(N->getOperand(1))) 595 switch (Opc) { 596 default: llvm_unreachable("Invalid shift opcode!"); 597 case ISD::SHL: 598 return DAG.getNode(MSP430ISD::SHL, dl, 599 VT, N->getOperand(0), N->getOperand(1)); 600 case ISD::SRA: 601 return DAG.getNode(MSP430ISD::SRA, dl, 602 VT, N->getOperand(0), N->getOperand(1)); 603 case ISD::SRL: 604 return DAG.getNode(MSP430ISD::SRL, dl, 605 VT, N->getOperand(0), N->getOperand(1)); 606 } 607 608 uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(); 609 610 // Expand the stuff into sequence of shifts. 611 // FIXME: for some shift amounts this might be done better! 612 // E.g.: foo >> (8 + N) => sxt(swpb(foo)) >> N 613 SDValue Victim = N->getOperand(0); 614 615 if (Opc == ISD::SRL && ShiftAmount) { 616 // Emit a special goodness here: 617 // srl A, 1 => clrc; rrc A 618 Victim = DAG.getNode(MSP430ISD::RRC, dl, VT, Victim); 619 ShiftAmount -= 1; 620 } 621 622 while (ShiftAmount--) 623 Victim = DAG.getNode((Opc == ISD::SHL ? MSP430ISD::RLA : MSP430ISD::RRA), 624 dl, VT, Victim); 625 626 return Victim; 627} 628 629SDValue MSP430TargetLowering::LowerGlobalAddress(SDValue Op, 630 SelectionDAG &DAG) const { 631 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 632 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset(); 633 634 // Create the TargetGlobalAddress node, folding in the constant offset. 635 SDValue Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(), 636 getPointerTy(), Offset); 637 return DAG.getNode(MSP430ISD::Wrapper, Op.getDebugLoc(), 638 getPointerTy(), Result); 639} 640 641SDValue MSP430TargetLowering::LowerExternalSymbol(SDValue Op, 642 SelectionDAG &DAG) const { 643 DebugLoc dl = Op.getDebugLoc(); 644 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol(); 645 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy()); 646 647 return DAG.getNode(MSP430ISD::Wrapper, dl, getPointerTy(), Result); 648} 649 650SDValue MSP430TargetLowering::LowerBlockAddress(SDValue Op, 651 SelectionDAG &DAG) const { 652 DebugLoc dl = Op.getDebugLoc(); 653 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 654 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(), /*isTarget=*/true); 655 656 return DAG.getNode(MSP430ISD::Wrapper, dl, getPointerTy(), Result); 657} 658 659static SDValue EmitCMP(SDValue &LHS, SDValue &RHS, SDValue &TargetCC, 660 ISD::CondCode CC, 661 DebugLoc dl, SelectionDAG &DAG) { 662 // FIXME: Handle bittests someday 663 assert(!LHS.getValueType().isFloatingPoint() && "We don't handle FP yet"); 664 665 // FIXME: Handle jump negative someday 666 MSP430CC::CondCodes TCC = MSP430CC::COND_INVALID; 667 switch (CC) { 668 default: llvm_unreachable("Invalid integer condition!"); 669 case ISD::SETEQ: 670 TCC = MSP430CC::COND_E; // aka COND_Z 671 // Minor optimization: if LHS is a constant, swap operands, then the 672 // constant can be folded into comparison. 673 if (LHS.getOpcode() == ISD::Constant) 674 std::swap(LHS, RHS); 675 break; 676 case ISD::SETNE: 677 TCC = MSP430CC::COND_NE; // aka COND_NZ 678 // Minor optimization: if LHS is a constant, swap operands, then the 679 // constant can be folded into comparison. 680 if (LHS.getOpcode() == ISD::Constant) 681 std::swap(LHS, RHS); 682 break; 683 case ISD::SETULE: 684 std::swap(LHS, RHS); // FALLTHROUGH 685 case ISD::SETUGE: 686 // Turn lhs u>= rhs with lhs constant into rhs u< lhs+1, this allows us to 687 // fold constant into instruction. 688 if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) { 689 LHS = RHS; 690 RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0)); 691 TCC = MSP430CC::COND_LO; 692 break; 693 } 694 TCC = MSP430CC::COND_HS; // aka COND_C 695 break; 696 case ISD::SETUGT: 697 std::swap(LHS, RHS); // FALLTHROUGH 698 case ISD::SETULT: 699 // Turn lhs u< rhs with lhs constant into rhs u>= lhs+1, this allows us to 700 // fold constant into instruction. 701 if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) { 702 LHS = RHS; 703 RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0)); 704 TCC = MSP430CC::COND_HS; 705 break; 706 } 707 TCC = MSP430CC::COND_LO; // aka COND_NC 708 break; 709 case ISD::SETLE: 710 std::swap(LHS, RHS); // FALLTHROUGH 711 case ISD::SETGE: 712 // Turn lhs >= rhs with lhs constant into rhs < lhs+1, this allows us to 713 // fold constant into instruction. 714 if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) { 715 LHS = RHS; 716 RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0)); 717 TCC = MSP430CC::COND_L; 718 break; 719 } 720 TCC = MSP430CC::COND_GE; 721 break; 722 case ISD::SETGT: 723 std::swap(LHS, RHS); // FALLTHROUGH 724 case ISD::SETLT: 725 // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows us to 726 // fold constant into instruction. 727 if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) { 728 LHS = RHS; 729 RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0)); 730 TCC = MSP430CC::COND_GE; 731 break; 732 } 733 TCC = MSP430CC::COND_L; 734 break; 735 } 736 737 TargetCC = DAG.getConstant(TCC, MVT::i8); 738 return DAG.getNode(MSP430ISD::CMP, dl, MVT::Glue, LHS, RHS); 739} 740 741 742SDValue MSP430TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const { 743 SDValue Chain = Op.getOperand(0); 744 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 745 SDValue LHS = Op.getOperand(2); 746 SDValue RHS = Op.getOperand(3); 747 SDValue Dest = Op.getOperand(4); 748 DebugLoc dl = Op.getDebugLoc(); 749 750 SDValue TargetCC; 751 SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG); 752 753 return DAG.getNode(MSP430ISD::BR_CC, dl, Op.getValueType(), 754 Chain, Dest, TargetCC, Flag); 755} 756 757SDValue MSP430TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { 758 SDValue LHS = Op.getOperand(0); 759 SDValue RHS = Op.getOperand(1); 760 DebugLoc dl = Op.getDebugLoc(); 761 762 // If we are doing an AND and testing against zero, then the CMP 763 // will not be generated. The AND (or BIT) will generate the condition codes, 764 // but they are different from CMP. 765 // FIXME: since we're doing a post-processing, use a pseudoinstr here, so 766 // lowering & isel wouldn't diverge. 767 bool andCC = false; 768 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 769 if (RHSC->isNullValue() && LHS.hasOneUse() && 770 (LHS.getOpcode() == ISD::AND || 771 (LHS.getOpcode() == ISD::TRUNCATE && 772 LHS.getOperand(0).getOpcode() == ISD::AND))) { 773 andCC = true; 774 } 775 } 776 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 777 SDValue TargetCC; 778 SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG); 779 780 // Get the condition codes directly from the status register, if its easy. 781 // Otherwise a branch will be generated. Note that the AND and BIT 782 // instructions generate different flags than CMP, the carry bit can be used 783 // for NE/EQ. 784 bool Invert = false; 785 bool Shift = false; 786 bool Convert = true; 787 switch (cast<ConstantSDNode>(TargetCC)->getZExtValue()) { 788 default: 789 Convert = false; 790 break; 791 case MSP430CC::COND_HS: 792 // Res = SRW & 1, no processing is required 793 break; 794 case MSP430CC::COND_LO: 795 // Res = ~(SRW & 1) 796 Invert = true; 797 break; 798 case MSP430CC::COND_NE: 799 if (andCC) { 800 // C = ~Z, thus Res = SRW & 1, no processing is required 801 } else { 802 // Res = ~((SRW >> 1) & 1) 803 Shift = true; 804 Invert = true; 805 } 806 break; 807 case MSP430CC::COND_E: 808 Shift = true; 809 // C = ~Z for AND instruction, thus we can put Res = ~(SRW & 1), however, 810 // Res = (SRW >> 1) & 1 is 1 word shorter. 811 break; 812 } 813 EVT VT = Op.getValueType(); 814 SDValue One = DAG.getConstant(1, VT); 815 if (Convert) { 816 SDValue SR = DAG.getCopyFromReg(DAG.getEntryNode(), dl, MSP430::SRW, 817 MVT::i16, Flag); 818 if (Shift) 819 // FIXME: somewhere this is turned into a SRL, lower it MSP specific? 820 SR = DAG.getNode(ISD::SRA, dl, MVT::i16, SR, One); 821 SR = DAG.getNode(ISD::AND, dl, MVT::i16, SR, One); 822 if (Invert) 823 SR = DAG.getNode(ISD::XOR, dl, MVT::i16, SR, One); 824 return SR; 825 } else { 826 SDValue Zero = DAG.getConstant(0, VT); 827 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue); 828 SmallVector<SDValue, 4> Ops; 829 Ops.push_back(One); 830 Ops.push_back(Zero); 831 Ops.push_back(TargetCC); 832 Ops.push_back(Flag); 833 return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, &Ops[0], Ops.size()); 834 } 835} 836 837SDValue MSP430TargetLowering::LowerSELECT_CC(SDValue Op, 838 SelectionDAG &DAG) const { 839 SDValue LHS = Op.getOperand(0); 840 SDValue RHS = Op.getOperand(1); 841 SDValue TrueV = Op.getOperand(2); 842 SDValue FalseV = Op.getOperand(3); 843 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 844 DebugLoc dl = Op.getDebugLoc(); 845 846 SDValue TargetCC; 847 SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG); 848 849 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue); 850 SmallVector<SDValue, 4> Ops; 851 Ops.push_back(TrueV); 852 Ops.push_back(FalseV); 853 Ops.push_back(TargetCC); 854 Ops.push_back(Flag); 855 856 return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, &Ops[0], Ops.size()); 857} 858 859SDValue MSP430TargetLowering::LowerSIGN_EXTEND(SDValue Op, 860 SelectionDAG &DAG) const { 861 SDValue Val = Op.getOperand(0); 862 EVT VT = Op.getValueType(); 863 DebugLoc dl = Op.getDebugLoc(); 864 865 assert(VT == MVT::i16 && "Only support i16 for now!"); 866 867 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT, 868 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Val), 869 DAG.getValueType(Val.getValueType())); 870} 871 872SDValue 873MSP430TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const { 874 MachineFunction &MF = DAG.getMachineFunction(); 875 MSP430MachineFunctionInfo *FuncInfo = MF.getInfo<MSP430MachineFunctionInfo>(); 876 int ReturnAddrIndex = FuncInfo->getRAIndex(); 877 878 if (ReturnAddrIndex == 0) { 879 // Set up a frame object for the return address. 880 uint64_t SlotSize = TD->getPointerSize(); 881 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize, 882 true); 883 FuncInfo->setRAIndex(ReturnAddrIndex); 884 } 885 886 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy()); 887} 888 889SDValue MSP430TargetLowering::LowerRETURNADDR(SDValue Op, 890 SelectionDAG &DAG) const { 891 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 892 MFI->setReturnAddressIsTaken(true); 893 894 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 895 DebugLoc dl = Op.getDebugLoc(); 896 897 if (Depth > 0) { 898 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); 899 SDValue Offset = 900 DAG.getConstant(TD->getPointerSize(), MVT::i16); 901 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 902 DAG.getNode(ISD::ADD, dl, getPointerTy(), 903 FrameAddr, Offset), 904 MachinePointerInfo(), false, false, false, 0); 905 } 906 907 // Just load the return address. 908 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG); 909 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 910 RetAddrFI, MachinePointerInfo(), false, false, false, 0); 911} 912 913SDValue MSP430TargetLowering::LowerFRAMEADDR(SDValue Op, 914 SelectionDAG &DAG) const { 915 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 916 MFI->setFrameAddressIsTaken(true); 917 918 EVT VT = Op.getValueType(); 919 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful 920 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 921 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, 922 MSP430::FPW, VT); 923 while (Depth--) 924 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, 925 MachinePointerInfo(), 926 false, false, false, 0); 927 return FrameAddr; 928} 929 930/// getPostIndexedAddressParts - returns true by value, base pointer and 931/// offset pointer and addressing mode by reference if this node can be 932/// combined with a load / store to form a post-indexed load / store. 933bool MSP430TargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op, 934 SDValue &Base, 935 SDValue &Offset, 936 ISD::MemIndexedMode &AM, 937 SelectionDAG &DAG) const { 938 939 LoadSDNode *LD = cast<LoadSDNode>(N); 940 if (LD->getExtensionType() != ISD::NON_EXTLOAD) 941 return false; 942 943 EVT VT = LD->getMemoryVT(); 944 if (VT != MVT::i8 && VT != MVT::i16) 945 return false; 946 947 if (Op->getOpcode() != ISD::ADD) 948 return false; 949 950 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) { 951 uint64_t RHSC = RHS->getZExtValue(); 952 if ((VT == MVT::i16 && RHSC != 2) || 953 (VT == MVT::i8 && RHSC != 1)) 954 return false; 955 956 Base = Op->getOperand(0); 957 Offset = DAG.getConstant(RHSC, VT); 958 AM = ISD::POST_INC; 959 return true; 960 } 961 962 return false; 963} 964 965 966const char *MSP430TargetLowering::getTargetNodeName(unsigned Opcode) const { 967 switch (Opcode) { 968 default: return NULL; 969 case MSP430ISD::RET_FLAG: return "MSP430ISD::RET_FLAG"; 970 case MSP430ISD::RETI_FLAG: return "MSP430ISD::RETI_FLAG"; 971 case MSP430ISD::RRA: return "MSP430ISD::RRA"; 972 case MSP430ISD::RLA: return "MSP430ISD::RLA"; 973 case MSP430ISD::RRC: return "MSP430ISD::RRC"; 974 case MSP430ISD::CALL: return "MSP430ISD::CALL"; 975 case MSP430ISD::Wrapper: return "MSP430ISD::Wrapper"; 976 case MSP430ISD::BR_CC: return "MSP430ISD::BR_CC"; 977 case MSP430ISD::CMP: return "MSP430ISD::CMP"; 978 case MSP430ISD::SELECT_CC: return "MSP430ISD::SELECT_CC"; 979 case MSP430ISD::SHL: return "MSP430ISD::SHL"; 980 case MSP430ISD::SRA: return "MSP430ISD::SRA"; 981 } 982} 983 984bool MSP430TargetLowering::isTruncateFree(Type *Ty1, 985 Type *Ty2) const { 986 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy()) 987 return false; 988 989 return (Ty1->getPrimitiveSizeInBits() > Ty2->getPrimitiveSizeInBits()); 990} 991 992bool MSP430TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { 993 if (!VT1.isInteger() || !VT2.isInteger()) 994 return false; 995 996 return (VT1.getSizeInBits() > VT2.getSizeInBits()); 997} 998 999bool MSP430TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const { 1000 // MSP430 implicitly zero-extends 8-bit results in 16-bit registers. 1001 return 0 && Ty1->isIntegerTy(8) && Ty2->isIntegerTy(16); 1002} 1003 1004bool MSP430TargetLowering::isZExtFree(EVT VT1, EVT VT2) const { 1005 // MSP430 implicitly zero-extends 8-bit results in 16-bit registers. 1006 return 0 && VT1 == MVT::i8 && VT2 == MVT::i16; 1007} 1008 1009//===----------------------------------------------------------------------===// 1010// Other Lowering Code 1011//===----------------------------------------------------------------------===// 1012 1013MachineBasicBlock* 1014MSP430TargetLowering::EmitShiftInstr(MachineInstr *MI, 1015 MachineBasicBlock *BB) const { 1016 MachineFunction *F = BB->getParent(); 1017 MachineRegisterInfo &RI = F->getRegInfo(); 1018 DebugLoc dl = MI->getDebugLoc(); 1019 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo(); 1020 1021 unsigned Opc; 1022 const TargetRegisterClass * RC; 1023 switch (MI->getOpcode()) { 1024 default: llvm_unreachable("Invalid shift opcode!"); 1025 case MSP430::Shl8: 1026 Opc = MSP430::SHL8r1; 1027 RC = MSP430::GR8RegisterClass; 1028 break; 1029 case MSP430::Shl16: 1030 Opc = MSP430::SHL16r1; 1031 RC = MSP430::GR16RegisterClass; 1032 break; 1033 case MSP430::Sra8: 1034 Opc = MSP430::SAR8r1; 1035 RC = MSP430::GR8RegisterClass; 1036 break; 1037 case MSP430::Sra16: 1038 Opc = MSP430::SAR16r1; 1039 RC = MSP430::GR16RegisterClass; 1040 break; 1041 case MSP430::Srl8: 1042 Opc = MSP430::SAR8r1c; 1043 RC = MSP430::GR8RegisterClass; 1044 break; 1045 case MSP430::Srl16: 1046 Opc = MSP430::SAR16r1c; 1047 RC = MSP430::GR16RegisterClass; 1048 break; 1049 } 1050 1051 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1052 MachineFunction::iterator I = BB; 1053 ++I; 1054 1055 // Create loop block 1056 MachineBasicBlock *LoopBB = F->CreateMachineBasicBlock(LLVM_BB); 1057 MachineBasicBlock *RemBB = F->CreateMachineBasicBlock(LLVM_BB); 1058 1059 F->insert(I, LoopBB); 1060 F->insert(I, RemBB); 1061 1062 // Update machine-CFG edges by transferring all successors of the current 1063 // block to the block containing instructions after shift. 1064 RemBB->splice(RemBB->begin(), BB, 1065 llvm::next(MachineBasicBlock::iterator(MI)), 1066 BB->end()); 1067 RemBB->transferSuccessorsAndUpdatePHIs(BB); 1068 1069 // Add adges BB => LoopBB => RemBB, BB => RemBB, LoopBB => LoopBB 1070 BB->addSuccessor(LoopBB); 1071 BB->addSuccessor(RemBB); 1072 LoopBB->addSuccessor(RemBB); 1073 LoopBB->addSuccessor(LoopBB); 1074 1075 unsigned ShiftAmtReg = RI.createVirtualRegister(MSP430::GR8RegisterClass); 1076 unsigned ShiftAmtReg2 = RI.createVirtualRegister(MSP430::GR8RegisterClass); 1077 unsigned ShiftReg = RI.createVirtualRegister(RC); 1078 unsigned ShiftReg2 = RI.createVirtualRegister(RC); 1079 unsigned ShiftAmtSrcReg = MI->getOperand(2).getReg(); 1080 unsigned SrcReg = MI->getOperand(1).getReg(); 1081 unsigned DstReg = MI->getOperand(0).getReg(); 1082 1083 // BB: 1084 // cmp 0, N 1085 // je RemBB 1086 BuildMI(BB, dl, TII.get(MSP430::CMP8ri)) 1087 .addReg(ShiftAmtSrcReg).addImm(0); 1088 BuildMI(BB, dl, TII.get(MSP430::JCC)) 1089 .addMBB(RemBB) 1090 .addImm(MSP430CC::COND_E); 1091 1092 // LoopBB: 1093 // ShiftReg = phi [%SrcReg, BB], [%ShiftReg2, LoopBB] 1094 // ShiftAmt = phi [%N, BB], [%ShiftAmt2, LoopBB] 1095 // ShiftReg2 = shift ShiftReg 1096 // ShiftAmt2 = ShiftAmt - 1; 1097 BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftReg) 1098 .addReg(SrcReg).addMBB(BB) 1099 .addReg(ShiftReg2).addMBB(LoopBB); 1100 BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftAmtReg) 1101 .addReg(ShiftAmtSrcReg).addMBB(BB) 1102 .addReg(ShiftAmtReg2).addMBB(LoopBB); 1103 BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2) 1104 .addReg(ShiftReg); 1105 BuildMI(LoopBB, dl, TII.get(MSP430::SUB8ri), ShiftAmtReg2) 1106 .addReg(ShiftAmtReg).addImm(1); 1107 BuildMI(LoopBB, dl, TII.get(MSP430::JCC)) 1108 .addMBB(LoopBB) 1109 .addImm(MSP430CC::COND_NE); 1110 1111 // RemBB: 1112 // DestReg = phi [%SrcReg, BB], [%ShiftReg, LoopBB] 1113 BuildMI(*RemBB, RemBB->begin(), dl, TII.get(MSP430::PHI), DstReg) 1114 .addReg(SrcReg).addMBB(BB) 1115 .addReg(ShiftReg2).addMBB(LoopBB); 1116 1117 MI->eraseFromParent(); // The pseudo instruction is gone now. 1118 return RemBB; 1119} 1120 1121MachineBasicBlock* 1122MSP430TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 1123 MachineBasicBlock *BB) const { 1124 unsigned Opc = MI->getOpcode(); 1125 1126 if (Opc == MSP430::Shl8 || Opc == MSP430::Shl16 || 1127 Opc == MSP430::Sra8 || Opc == MSP430::Sra16 || 1128 Opc == MSP430::Srl8 || Opc == MSP430::Srl16) 1129 return EmitShiftInstr(MI, BB); 1130 1131 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo(); 1132 DebugLoc dl = MI->getDebugLoc(); 1133 1134 assert((Opc == MSP430::Select16 || Opc == MSP430::Select8) && 1135 "Unexpected instr type to insert"); 1136 1137 // To "insert" a SELECT instruction, we actually have to insert the diamond 1138 // control-flow pattern. The incoming instruction knows the destination vreg 1139 // to set, the condition code register to branch on, the true/false values to 1140 // select between, and a branch opcode to use. 1141 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1142 MachineFunction::iterator I = BB; 1143 ++I; 1144 1145 // thisMBB: 1146 // ... 1147 // TrueVal = ... 1148 // cmpTY ccX, r1, r2 1149 // jCC copy1MBB 1150 // fallthrough --> copy0MBB 1151 MachineBasicBlock *thisMBB = BB; 1152 MachineFunction *F = BB->getParent(); 1153 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 1154 MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB); 1155 F->insert(I, copy0MBB); 1156 F->insert(I, copy1MBB); 1157 // Update machine-CFG edges by transferring all successors of the current 1158 // block to the new block which will contain the Phi node for the select. 1159 copy1MBB->splice(copy1MBB->begin(), BB, 1160 llvm::next(MachineBasicBlock::iterator(MI)), 1161 BB->end()); 1162 copy1MBB->transferSuccessorsAndUpdatePHIs(BB); 1163 // Next, add the true and fallthrough blocks as its successors. 1164 BB->addSuccessor(copy0MBB); 1165 BB->addSuccessor(copy1MBB); 1166 1167 BuildMI(BB, dl, TII.get(MSP430::JCC)) 1168 .addMBB(copy1MBB) 1169 .addImm(MI->getOperand(3).getImm()); 1170 1171 // copy0MBB: 1172 // %FalseValue = ... 1173 // # fallthrough to copy1MBB 1174 BB = copy0MBB; 1175 1176 // Update machine-CFG edges 1177 BB->addSuccessor(copy1MBB); 1178 1179 // copy1MBB: 1180 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 1181 // ... 1182 BB = copy1MBB; 1183 BuildMI(*BB, BB->begin(), dl, TII.get(MSP430::PHI), 1184 MI->getOperand(0).getReg()) 1185 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB) 1186 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB); 1187 1188 MI->eraseFromParent(); // The pseudo instruction is gone now. 1189 return BB; 1190} 1191